drivers/gpu/drm/i915/display/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <drm/drm_scdc_helper.h>
  29
  30 #include "i915_drv.h"
  31 #include "intel_audio.h"
  32 #include "intel_combo_phy.h"
  33 #include "intel_connector.h"
  34 #include "intel_ddi.h"
  35 #include "intel_display_types.h"
  36 #include "intel_dp.h"
  37 #include "intel_dp_mst.h"
  38 #include "intel_dp_link_training.h"
  39 #include "intel_dpio_phy.h"
  40 #include "intel_dsi.h"
  41 #include "intel_fifo_underrun.h"
  42 #include "intel_gmbus.h"
  43 #include "intel_hdcp.h"
  44 #include "intel_hdmi.h"
  45 #include "intel_hotplug.h"
  46 #include "intel_lspcon.h"
  47 #include "intel_panel.h"
  48 #include "intel_psr.h"
  49 #include "intel_sprite.h"
  50 #include "intel_tc.h"
  51 #include "intel_vdsc.h"
  52
  53 struct ddi_buf_trans {
  54         u32 trans1;     /* balance leg enable, de-emph level */
  55         u32 trans2;     /* vref sel, vswing */
  56         u8 i_boost;     /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
  57 };
  58
  59 static const u8 index_to_dp_signal_levels[] = {
  60         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  61         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  62         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  63         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  64         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  65         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  66         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  67         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  68         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  69         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  70 };
  71
  72 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  73  * them for both DP and FDI transports, allowing those ports to
  74  * automatically adapt to HDMI connections as well
  75  */
  76 static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
  77         { 0x00FFFFFF, 0x0006000E, 0x0 },
  78         { 0x00D75FFF, 0x0005000A, 0x0 },
  79         { 0x00C30FFF, 0x00040006, 0x0 },
  80         { 0x80AAAFFF, 0x000B0000, 0x0 },
  81         { 0x00FFFFFF, 0x0005000A, 0x0 },
  82         { 0x00D75FFF, 0x000C0004, 0x0 },
  83         { 0x80C30FFF, 0x000B0000, 0x0 },
  84         { 0x00FFFFFF, 0x00040006, 0x0 },
  85         { 0x80D75FFF, 0x000B0000, 0x0 },
  86 };
  87
  88 static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
  89         { 0x00FFFFFF, 0x0007000E, 0x0 },
  90         { 0x00D75FFF, 0x000F000A, 0x0 },
  91         { 0x00C30FFF, 0x00060006, 0x0 },
  92         { 0x00AAAFFF, 0x001E0000, 0x0 },
  93         { 0x00FFFFFF, 0x000F000A, 0x0 },
  94         { 0x00D75FFF, 0x00160004, 0x0 },
  95         { 0x00C30FFF, 0x001E0000, 0x0 },
  96         { 0x00FFFFFF, 0x00060006, 0x0 },
  97         { 0x00D75FFF, 0x001E0000, 0x0 },
  98 };
  99
 100 static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
 101                                         /* Idx  NT mV d T mV d  db      */
 102         { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0:   400     400     0       */
 103         { 0x00E79FFF, 0x000E000C, 0x0 },/* 1:   400     500     2       */
 104         { 0x00D75FFF, 0x0005000A, 0x0 },/* 2:   400     600     3.5     */
 105         { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3:   600     600     0       */
 106         { 0x00E79FFF, 0x001D0007, 0x0 },/* 4:   600     750     2       */
 107         { 0x00D75FFF, 0x000C0004, 0x0 },/* 5:   600     900     3.5     */
 108         { 0x00FFFFFF, 0x00040006, 0x0 },/* 6:   800     800     0       */
 109         { 0x80E79FFF, 0x00030002, 0x0 },/* 7:   800     1000    2       */
 110         { 0x00FFFFFF, 0x00140005, 0x0 },/* 8:   850     850     0       */
 111         { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9:   900     900     0       */
 112         { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10:  950     950     0       */
 113         { 0x80FFFFFF, 0x00030002, 0x0 },/* 11:  1000    1000    0       */
 114 };
 115
 116 static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
 117         { 0x00FFFFFF, 0x00000012, 0x0 },
 118         { 0x00EBAFFF, 0x00020011, 0x0 },
 119         { 0x00C71FFF, 0x0006000F, 0x0 },
 120         { 0x00AAAFFF, 0x000E000A, 0x0 },
 121         { 0x00FFFFFF, 0x00020011, 0x0 },
 122         { 0x00DB6FFF, 0x0005000F, 0x0 },
 123         { 0x00BEEFFF, 0x000A000C, 0x0 },
 124         { 0x00FFFFFF, 0x0005000F, 0x0 },
 125         { 0x00DB6FFF, 0x000A000C, 0x0 },
 126 };
 127
 128 static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
 129         { 0x00FFFFFF, 0x0007000E, 0x0 },
 130         { 0x00D75FFF, 0x000E000A, 0x0 },
 131         { 0x00BEFFFF, 0x00140006, 0x0 },
 132         { 0x80B2CFFF, 0x001B0002, 0x0 },
 133         { 0x00FFFFFF, 0x000E000A, 0x0 },
 134         { 0x00DB6FFF, 0x00160005, 0x0 },
 135         { 0x80C71FFF, 0x001A0002, 0x0 },
 136         { 0x00F7DFFF, 0x00180004, 0x0 },
 137         { 0x80D75FFF, 0x001B0002, 0x0 },
 138 };
 139
 140 static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
 141         { 0x00FFFFFF, 0x0001000E, 0x0 },
 142         { 0x00D75FFF, 0x0004000A, 0x0 },
 143         { 0x00C30FFF, 0x00070006, 0x0 },
 144         { 0x00AAAFFF, 0x000C0000, 0x0 },
 145         { 0x00FFFFFF, 0x0004000A, 0x0 },
 146         { 0x00D75FFF, 0x00090004, 0x0 },
 147         { 0x00C30FFF, 0x000C0000, 0x0 },
 148         { 0x00FFFFFF, 0x00070006, 0x0 },
 149         { 0x00D75FFF, 0x000C0000, 0x0 },
 150 };
 151
 152 static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
 153                                         /* Idx  NT mV d T mV df db      */
 154         { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0:   400     400     0       */
 155         { 0x00D75FFF, 0x000E000A, 0x0 },/* 1:   400     600     3.5     */
 156         { 0x00BEFFFF, 0x00140006, 0x0 },/* 2:   400     800     6       */
 157         { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3:   450     450     0       */
 158         { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4:   600     600     0       */
 159         { 0x00D7FFFF, 0x00140006, 0x0 },/* 5:   600     800     2.5     */
 160         { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6:   600     1000    4.5     */
 161         { 0x00FFFFFF, 0x00140006, 0x0 },/* 7:   800     800     0       */
 162         { 0x80E79FFF, 0x001B0002, 0x0 },/* 8:   800     1000    2       */
 163         { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9:   1000    1000    0       */
 164 };
 165
 166 /* Skylake H and S */
 167 static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
 168         { 0x00002016, 0x000000A0, 0x0 },
 169         { 0x00005012, 0x0000009B, 0x0 },
 170         { 0x00007011, 0x00000088, 0x0 },
 171         { 0x80009010, 0x000000C0, 0x1 },
 172         { 0x00002016, 0x0000009B, 0x0 },
 173         { 0x00005012, 0x00000088, 0x0 },
 174         { 0x80007011, 0x000000C0, 0x1 },
 175         { 0x00002016, 0x000000DF, 0x0 },
 176         { 0x80005012, 0x000000C0, 0x1 },
 177 };
 178
 179 /* Skylake U */
 180 static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
 181         { 0x0000201B, 0x000000A2, 0x0 },
 182         { 0x00005012, 0x00000088, 0x0 },
 183         { 0x80007011, 0x000000CD, 0x1 },
 184         { 0x80009010, 0x000000C0, 0x1 },
 185         { 0x0000201B, 0x0000009D, 0x0 },
 186         { 0x80005012, 0x000000C0, 0x1 },
 187         { 0x80007011, 0x000000C0, 0x1 },
 188         { 0x00002016, 0x00000088, 0x0 },
 189         { 0x80005012, 0x000000C0, 0x1 },
 190 };
 191
 192 /* Skylake Y */
 193 static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
 194         { 0x00000018, 0x000000A2, 0x0 },
 195         { 0x00005012, 0x00000088, 0x0 },
 196         { 0x80007011, 0x000000CD, 0x3 },
 197         { 0x80009010, 0x000000C0, 0x3 },
 198         { 0x00000018, 0x0000009D, 0x0 },
 199         { 0x80005012, 0x000000C0, 0x3 },
 200         { 0x80007011, 0x000000C0, 0x3 },
 201         { 0x00000018, 0x00000088, 0x0 },
 202         { 0x80005012, 0x000000C0, 0x3 },
 203 };
 204
 205 /* Kabylake H and S */
 206 static const struct ddi_buf_trans kbl_ddi_translations_dp[] = {
 207         { 0x00002016, 0x000000A0, 0x0 },
 208         { 0x00005012, 0x0000009B, 0x0 },
 209         { 0x00007011, 0x00000088, 0x0 },
 210         { 0x80009010, 0x000000C0, 0x1 },
 211         { 0x00002016, 0x0000009B, 0x0 },
 212         { 0x00005012, 0x00000088, 0x0 },
 213         { 0x80007011, 0x000000C0, 0x1 },
 214         { 0x00002016, 0x00000097, 0x0 },
 215         { 0x80005012, 0x000000C0, 0x1 },
 216 };
 217
 218 /* Kabylake U */
 219 static const struct ddi_buf_trans kbl_u_ddi_translations_dp[] = {
 220         { 0x0000201B, 0x000000A1, 0x0 },
 221         { 0x00005012, 0x00000088, 0x0 },
 222         { 0x80007011, 0x000000CD, 0x3 },
 223         { 0x80009010, 0x000000C0, 0x3 },
 224         { 0x0000201B, 0x0000009D, 0x0 },
 225         { 0x80005012, 0x000000C0, 0x3 },
 226         { 0x80007011, 0x000000C0, 0x3 },
 227         { 0x00002016, 0x0000004F, 0x0 },
 228         { 0x80005012, 0x000000C0, 0x3 },
 229 };
 230
 231 /* Kabylake Y */
 232 static const struct ddi_buf_trans kbl_y_ddi_translations_dp[] = {
 233         { 0x00001017, 0x000000A1, 0x0 },
 234         { 0x00005012, 0x00000088, 0x0 },
 235         { 0x80007011, 0x000000CD, 0x3 },
 236         { 0x8000800F, 0x000000C0, 0x3 },
 237         { 0x00001017, 0x0000009D, 0x0 },
 238         { 0x80005012, 0x000000C0, 0x3 },
 239         { 0x80007011, 0x000000C0, 0x3 },
 240         { 0x00001017, 0x0000004C, 0x0 },
 241         { 0x80005012, 0x000000C0, 0x3 },
 242 };
 243
 244 /*
 245  * Skylake/Kabylake H and S
 246  * eDP 1.4 low vswing translation parameters
 247  */
 248 static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
 249         { 0x00000018, 0x000000A8, 0x0 },
 250         { 0x00004013, 0x000000A9, 0x0 },
 251         { 0x00007011, 0x000000A2, 0x0 },
 252         { 0x00009010, 0x0000009C, 0x0 },
 253         { 0x00000018, 0x000000A9, 0x0 },
 254         { 0x00006013, 0x000000A2, 0x0 },
 255         { 0x00007011, 0x000000A6, 0x0 },
 256         { 0x00000018, 0x000000AB, 0x0 },
 257         { 0x00007013, 0x0000009F, 0x0 },
 258         { 0x00000018, 0x000000DF, 0x0 },
 259 };
 260
 261 /*
 262  * Skylake/Kabylake U
 263  * eDP 1.4 low vswing translation parameters
 264  */
 265 static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
 266         { 0x00000018, 0x000000A8, 0x0 },
 267         { 0x00004013, 0x000000A9, 0x0 },
 268         { 0x00007011, 0x000000A2, 0x0 },
 269         { 0x00009010, 0x0000009C, 0x0 },
 270         { 0x00000018, 0x000000A9, 0x0 },
 271         { 0x00006013, 0x000000A2, 0x0 },
 272         { 0x00007011, 0x000000A6, 0x0 },
 273         { 0x00002016, 0x000000AB, 0x0 },
 274         { 0x00005013, 0x0000009F, 0x0 },
 275         { 0x00000018, 0x000000DF, 0x0 },
 276 };
 277
 278 /*
 279  * Skylake/Kabylake Y
 280  * eDP 1.4 low vswing translation parameters
 281  */
 282 static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
 283         { 0x00000018, 0x000000A8, 0x0 },
 284         { 0x00004013, 0x000000AB, 0x0 },
 285         { 0x00007011, 0x000000A4, 0x0 },
 286         { 0x00009010, 0x000000DF, 0x0 },
 287         { 0x00000018, 0x000000AA, 0x0 },
 288         { 0x00006013, 0x000000A4, 0x0 },
 289         { 0x00007011, 0x0000009D, 0x0 },
 290         { 0x00000018, 0x000000A0, 0x0 },
 291         { 0x00006012, 0x000000DF, 0x0 },
 292         { 0x00000018, 0x0000008A, 0x0 },
 293 };
 294
 295 /* Skylake/Kabylake U, H and S */
 296 static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
 297         { 0x00000018, 0x000000AC, 0x0 },
 298         { 0x00005012, 0x0000009D, 0x0 },
 299         { 0x00007011, 0x00000088, 0x0 },
 300         { 0x00000018, 0x000000A1, 0x0 },
 301         { 0x00000018, 0x00000098, 0x0 },
 302         { 0x00004013, 0x00000088, 0x0 },
 303         { 0x80006012, 0x000000CD, 0x1 },
 304         { 0x00000018, 0x000000DF, 0x0 },
 305         { 0x80003015, 0x000000CD, 0x1 },        /* Default */
 306         { 0x80003015, 0x000000C0, 0x1 },
 307         { 0x80000018, 0x000000C0, 0x1 },
 308 };
 309
 310 /* Skylake/Kabylake Y */
 311 static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
 312         { 0x00000018, 0x000000A1, 0x0 },
 313         { 0x00005012, 0x000000DF, 0x0 },
 314         { 0x80007011, 0x000000CB, 0x3 },
 315         { 0x00000018, 0x000000A4, 0x0 },
 316         { 0x00000018, 0x0000009D, 0x0 },
 317         { 0x00004013, 0x00000080, 0x0 },
 318         { 0x80006013, 0x000000C0, 0x3 },
 319         { 0x00000018, 0x0000008A, 0x0 },
 320         { 0x80003015, 0x000000C0, 0x3 },        /* Default */
 321         { 0x80003015, 0x000000C0, 0x3 },
 322         { 0x80000018, 0x000000C0, 0x3 },
 323 };
 324
 325 struct bxt_ddi_buf_trans {
 326         u8 margin;      /* swing value */
 327         u8 scale;       /* scale value */
 328         u8 enable;      /* scale enable */
 329         u8 deemphasis;
 330 };
 331
 332 static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
 333                                         /* Idx  NT mV diff      db  */
 334         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 335         { 78,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 336         { 104, 0x9A, 0, 64,  }, /* 2:   400             6   */
 337         { 154, 0x9A, 0, 43,  }, /* 3:   400             9.5 */
 338         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 339         { 116, 0x9A, 0, 85,  }, /* 5:   600             3.5 */
 340         { 154, 0x9A, 0, 64,  }, /* 6:   600             6   */
 341         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 342         { 154, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 343         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 344 };
 345
 346 static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
 347                                         /* Idx  NT mV diff      db  */
 348         { 26, 0, 0, 128, },     /* 0:   200             0   */
 349         { 38, 0, 0, 112, },     /* 1:   200             1.5 */
 350         { 48, 0, 0, 96,  },     /* 2:   200             4   */
 351         { 54, 0, 0, 69,  },     /* 3:   200             6   */
 352         { 32, 0, 0, 128, },     /* 4:   250             0   */
 353         { 48, 0, 0, 104, },     /* 5:   250             1.5 */
 354         { 54, 0, 0, 85,  },     /* 6:   250             4   */
 355         { 43, 0, 0, 128, },     /* 7:   300             0   */
 356         { 54, 0, 0, 101, },     /* 8:   300             1.5 */
 357         { 48, 0, 0, 128, },     /* 9:   300             0   */
 358 };
 359
 360 /* BSpec has 2 recommended values - entries 0 and 8.
 361  * Using the entry with higher vswing.
 362  */
 363 static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
 364                                         /* Idx  NT mV diff      db  */
 365         { 52,  0x9A, 0, 128, }, /* 0:   400             0   */
 366         { 52,  0x9A, 0, 85,  }, /* 1:   400             3.5 */
 367         { 52,  0x9A, 0, 64,  }, /* 2:   400             6   */
 368         { 42,  0x9A, 0, 43,  }, /* 3:   400             9.5 */
 369         { 77,  0x9A, 0, 128, }, /* 4:   600             0   */
 370         { 77,  0x9A, 0, 85,  }, /* 5:   600             3.5 */
 371         { 77,  0x9A, 0, 64,  }, /* 6:   600             6   */
 372         { 102, 0x9A, 0, 128, }, /* 7:   800             0   */
 373         { 102, 0x9A, 0, 85,  }, /* 8:   800             3.5 */
 374         { 154, 0x9A, 1, 128, }, /* 9:   1200            0   */
 375 };
 376
 377 struct cnl_ddi_buf_trans {
 378         u8 dw2_swing_sel;
 379         u8 dw7_n_scalar;
 380         u8 dw4_cursor_coeff;
 381         u8 dw4_post_cursor_2;
 382         u8 dw4_post_cursor_1;
 383 };
 384
 385 /* Voltage Swing Programming for VccIO 0.85V for DP */
 386 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_85V[] = {
 387                                                 /* NT mV Trans mV db    */
 388         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 389         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 390         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 391         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 392         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 393         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 394         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 395         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 396         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 397         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 398 };
 399
 400 /* Voltage Swing Programming for VccIO 0.85V for HDMI */
 401 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_85V[] = {
 402                                                 /* NT mV Trans mV db    */
 403         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 404         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 405         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 406         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   */
 407         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 408         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 409         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 410 };
 411
 412 /* Voltage Swing Programming for VccIO 0.85V for eDP */
 413 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_85V[] = {
 414                                                 /* NT mV Trans mV db    */
 415         { 0xA, 0x66, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 416         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 417         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 418         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 419         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 420         { 0xA, 0x66, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 421         { 0xB, 0x70, 0x3C, 0x00, 0x03 },        /* 460   600      2.3   */
 422         { 0xC, 0x75, 0x3C, 0x00, 0x03 },        /* 537   700      2.3   */
 423         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 424 };
 425
 426 /* Voltage Swing Programming for VccIO 0.95V for DP */
 427 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_0_95V[] = {
 428                                                 /* NT mV Trans mV db    */
 429         { 0xA, 0x5D, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 430         { 0xA, 0x6A, 0x38, 0x00, 0x07 },        /* 350   500      3.1   */
 431         { 0xB, 0x7A, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 432         { 0x6, 0x7C, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 433         { 0xA, 0x69, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 434         { 0xB, 0x7A, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 435         { 0x6, 0x7C, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 436         { 0xB, 0x7D, 0x3C, 0x00, 0x03 },        /* 650   725      0.9   */
 437         { 0x6, 0x7C, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 438         { 0x6, 0x7B, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 439 };
 440
 441 /* Voltage Swing Programming for VccIO 0.95V for HDMI */
 442 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_0_95V[] = {
 443                                                 /* NT mV Trans mV db    */
 444         { 0xA, 0x5C, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 445         { 0xB, 0x69, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 446         { 0x5, 0x76, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 447         { 0xA, 0x5E, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 448         { 0xB, 0x69, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 449         { 0xB, 0x79, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 450         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 451         { 0x5, 0x76, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 452         { 0x6, 0x7D, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 453         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 454         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 455 };
 456
 457 /* Voltage Swing Programming for VccIO 0.95V for eDP */
 458 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_0_95V[] = {
 459                                                 /* NT mV Trans mV db    */
 460         { 0xA, 0x61, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 461         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 462         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 463         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 464         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 465         { 0xA, 0x61, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 466         { 0xB, 0x68, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 467         { 0xC, 0x6E, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 468         { 0x4, 0x7F, 0x3A, 0x00, 0x05 },        /* 460   600      2.3   */
 469         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 470 };
 471
 472 /* Voltage Swing Programming for VccIO 1.05V for DP */
 473 static const struct cnl_ddi_buf_trans cnl_ddi_translations_dp_1_05V[] = {
 474                                                 /* NT mV Trans mV db    */
 475         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 476         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 477         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 478         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 400   1050     8.4   */
 479         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 480         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 481         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 550   1050     5.6   */
 482         { 0x5, 0x76, 0x3E, 0x00, 0x01 },        /* 850   900      0.5   */
 483         { 0x6, 0x7F, 0x36, 0x00, 0x09 },        /* 750   1050     2.9   */
 484         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 485 };
 486
 487 /* Voltage Swing Programming for VccIO 1.05V for HDMI */
 488 static const struct cnl_ddi_buf_trans cnl_ddi_translations_hdmi_1_05V[] = {
 489                                                 /* NT mV Trans mV db    */
 490         { 0xA, 0x58, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 491         { 0xB, 0x64, 0x37, 0x00, 0x08 },        /* 400   600      3.5   */
 492         { 0x5, 0x70, 0x31, 0x00, 0x0E },        /* 400   800      6.0   */
 493         { 0xA, 0x5B, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 494         { 0xB, 0x64, 0x3F, 0x00, 0x00 },        /* 600   600      0.0   */
 495         { 0x5, 0x73, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 496         { 0x6, 0x7C, 0x32, 0x00, 0x0D },        /* 600   1000     4.4   */
 497         { 0x5, 0x70, 0x3F, 0x00, 0x00 },        /* 800   800      0.0   */
 498         { 0x6, 0x7C, 0x39, 0x00, 0x06 },        /* 800   1000     1.9   */
 499         { 0x6, 0x7F, 0x39, 0x00, 0x06 },        /* 850   1050     1.8   */
 500         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1050  1050     0.0   */
 501 };
 502
 503 /* Voltage Swing Programming for VccIO 1.05V for eDP */
 504 static const struct cnl_ddi_buf_trans cnl_ddi_translations_edp_1_05V[] = {
 505                                                 /* NT mV Trans mV db    */
 506         { 0xA, 0x5E, 0x3A, 0x00, 0x05 },        /* 384   500      2.3   */
 507         { 0x0, 0x7F, 0x38, 0x00, 0x07 },        /* 153   200      2.3   */
 508         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 192   250      2.3   */
 509         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 230   300      2.3   */
 510         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 269   350      2.3   */
 511         { 0xA, 0x5E, 0x3C, 0x00, 0x03 },        /* 446   500      1.0   */
 512         { 0xB, 0x64, 0x39, 0x00, 0x06 },        /* 460   600      2.3   */
 513         { 0xE, 0x6A, 0x39, 0x00, 0x06 },        /* 537   700      2.3   */
 514         { 0x2, 0x7F, 0x3F, 0x00, 0x00 },        /* 400   400      0.0   */
 515 };
 516
 517 /* icl_combo_phy_ddi_translations */
 518 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_dp_hbr2[] = {
 519                                                 /* NT mV Trans mV db    */
 520         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 521         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 522         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 523         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 524         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 525         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 526         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 527         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 528         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 529         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 530 };
 531
 532 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr2[] = {
 533                                                 /* NT mV Trans mV db    */
 534         { 0x0, 0x7F, 0x3F, 0x00, 0x00 },        /* 200   200      0.0   */
 535         { 0x8, 0x7F, 0x38, 0x00, 0x07 },        /* 200   250      1.9   */
 536         { 0x1, 0x7F, 0x33, 0x00, 0x0C },        /* 200   300      3.5   */
 537         { 0x9, 0x7F, 0x31, 0x00, 0x0E },        /* 200   350      4.9   */
 538         { 0x8, 0x7F, 0x3F, 0x00, 0x00 },        /* 250   250      0.0   */
 539         { 0x1, 0x7F, 0x38, 0x00, 0x07 },        /* 250   300      1.6   */
 540         { 0x9, 0x7F, 0x35, 0x00, 0x0A },        /* 250   350      2.9   */
 541         { 0x1, 0x7F, 0x3F, 0x00, 0x00 },        /* 300   300      0.0   */
 542         { 0x9, 0x7F, 0x38, 0x00, 0x07 },        /* 300   350      1.3   */
 543         { 0x9, 0x7F, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 544 };
 545
 546 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_edp_hbr3[] = {
 547                                                 /* NT mV Trans mV db    */
 548         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 549         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 550         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 551         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 552         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 553         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 554         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 555         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 556         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 557         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 558 };
 559
 560 static const struct cnl_ddi_buf_trans icl_combo_phy_ddi_translations_hdmi[] = {
 561                                                 /* NT mV Trans mV db    */
 562         { 0xA, 0x60, 0x3F, 0x00, 0x00 },        /* 450   450      0.0   */
 563         { 0xB, 0x73, 0x36, 0x00, 0x09 },        /* 450   650      3.2   */
 564         { 0x6, 0x7F, 0x31, 0x00, 0x0E },        /* 450   850      5.5   */
 565         { 0xB, 0x73, 0x3F, 0x00, 0x00 },        /* 650   650      0.0   ALS */
 566         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 650   850      2.3   */
 567         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 850   850      0.0   */
 568         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   850      3.0   */
 569 };
 570
 571 static const struct cnl_ddi_buf_trans ehl_combo_phy_ddi_translations_dp[] = {
 572                                                 /* NT mV Trans mV db    */
 573         { 0xA, 0x33, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 574         { 0xA, 0x47, 0x36, 0x00, 0x09 },        /* 350   500      3.1   */
 575         { 0xC, 0x64, 0x30, 0x00, 0x0F },        /* 350   700      6.0   */
 576         { 0x6, 0x7F, 0x2C, 0x00, 0x13 },        /* 350   900      8.2   */
 577         { 0xA, 0x46, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 578         { 0xC, 0x64, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 579         { 0x6, 0x7F, 0x30, 0x00, 0x0F },        /* 500   900      5.1   */
 580         { 0xC, 0x61, 0x3F, 0x00, 0x00 },        /* 650   700      0.6   */
 581         { 0x6, 0x7F, 0x37, 0x00, 0x08 },        /* 600   900      3.5   */
 582         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 583 };
 584
 585 struct icl_mg_phy_ddi_buf_trans {
 586         u32 cri_txdeemph_override_11_6;
 587         u32 cri_txdeemph_override_5_0;
 588         u32 cri_txdeemph_override_17_12;
 589 };
 590
 591 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_rbr_hbr[] = {
 592                                 /* Voltage swing  pre-emphasis */
 593         { 0x18, 0x00, 0x00 },   /* 0              0   */
 594         { 0x1D, 0x00, 0x05 },   /* 0              1   */
 595         { 0x24, 0x00, 0x0C },   /* 0              2   */
 596         { 0x2B, 0x00, 0x14 },   /* 0              3   */
 597         { 0x21, 0x00, 0x00 },   /* 1              0   */
 598         { 0x2B, 0x00, 0x08 },   /* 1              1   */
 599         { 0x30, 0x00, 0x0F },   /* 1              2   */
 600         { 0x31, 0x00, 0x03 },   /* 2              0   */
 601         { 0x34, 0x00, 0x0B },   /* 2              1   */
 602         { 0x3F, 0x00, 0x00 },   /* 3              0   */
 603 };
 604
 605 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hbr2_hbr3[] = {
 606                                 /* Voltage swing  pre-emphasis */
 607         { 0x18, 0x00, 0x00 },   /* 0              0   */
 608         { 0x1D, 0x00, 0x05 },   /* 0              1   */
 609         { 0x24, 0x00, 0x0C },   /* 0              2   */
 610         { 0x2B, 0x00, 0x14 },   /* 0              3   */
 611         { 0x26, 0x00, 0x00 },   /* 1              0   */
 612         { 0x2C, 0x00, 0x07 },   /* 1              1   */
 613         { 0x33, 0x00, 0x0C },   /* 1              2   */
 614         { 0x2E, 0x00, 0x00 },   /* 2              0   */
 615         { 0x36, 0x00, 0x09 },   /* 2              1   */
 616         { 0x3F, 0x00, 0x00 },   /* 3              0   */
 617 };
 618
 619 static const struct icl_mg_phy_ddi_buf_trans icl_mg_phy_ddi_translations_hdmi[] = {
 620                                 /* HDMI Preset  VS      Pre-emph */
 621         { 0x1A, 0x0, 0x0 },     /* 1            400mV   0dB */
 622         { 0x20, 0x0, 0x0 },     /* 2            500mV   0dB */
 623         { 0x29, 0x0, 0x0 },     /* 3            650mV   0dB */
 624         { 0x32, 0x0, 0x0 },     /* 4            800mV   0dB */
 625         { 0x3F, 0x0, 0x0 },     /* 5            1000mV  0dB */
 626         { 0x3A, 0x0, 0x5 },     /* 6            Full    -1.5 dB */
 627         { 0x39, 0x0, 0x6 },     /* 7            Full    -1.8 dB */
 628         { 0x38, 0x0, 0x7 },     /* 8            Full    -2 dB */
 629         { 0x37, 0x0, 0x8 },     /* 9            Full    -2.5 dB */
 630         { 0x36, 0x0, 0x9 },     /* 10           Full    -3 dB */
 631 };
 632
 633 struct tgl_dkl_phy_ddi_buf_trans {
 634         u32 dkl_vswing_control;
 635         u32 dkl_preshoot_control;
 636         u32 dkl_de_emphasis_control;
 637 };
 638
 639 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans[] = {
 640                                 /* VS   pre-emp Non-trans mV    Pre-emph dB */
 641         { 0x7, 0x0, 0x00 },     /* 0    0       400mV           0 dB */
 642         { 0x5, 0x0, 0x05 },     /* 0    1       400mV           3.5 dB */
 643         { 0x2, 0x0, 0x0B },     /* 0    2       400mV           6 dB */
 644         { 0x0, 0x0, 0x18 },     /* 0    3       400mV           9.5 dB */
 645         { 0x5, 0x0, 0x00 },     /* 1    0       600mV           0 dB */
 646         { 0x2, 0x0, 0x08 },     /* 1    1       600mV           3.5 dB */
 647         { 0x0, 0x0, 0x14 },     /* 1    2       600mV           6 dB */
 648         { 0x2, 0x0, 0x00 },     /* 2    0       800mV           0 dB */
 649         { 0x0, 0x0, 0x0B },     /* 2    1       800mV           3.5 dB */
 650         { 0x0, 0x0, 0x00 },     /* 3    0       1200mV          0 dB HDMI default */
 651 };
 652
 653 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_dp_ddi_trans_hbr2[] = {
 654                                 /* VS   pre-emp Non-trans mV    Pre-emph dB */
 655         { 0x7, 0x0, 0x00 },     /* 0    0       400mV           0 dB */
 656         { 0x5, 0x0, 0x05 },     /* 0    1       400mV           3.5 dB */
 657         { 0x2, 0x0, 0x0B },     /* 0    2       400mV           6 dB */
 658         { 0x0, 0x0, 0x19 },     /* 0    3       400mV           9.5 dB */
 659         { 0x5, 0x0, 0x00 },     /* 1    0       600mV           0 dB */
 660         { 0x2, 0x0, 0x08 },     /* 1    1       600mV           3.5 dB */
 661         { 0x0, 0x0, 0x14 },     /* 1    2       600mV           6 dB */
 662         { 0x2, 0x0, 0x00 },     /* 2    0       800mV           0 dB */
 663         { 0x0, 0x0, 0x0B },     /* 2    1       800mV           3.5 dB */
 664         { 0x0, 0x0, 0x00 },     /* 3    0       1200mV          0 dB HDMI default */
 665 };
 666
 667 static const struct tgl_dkl_phy_ddi_buf_trans tgl_dkl_phy_hdmi_ddi_trans[] = {
 668                                 /* HDMI Preset  VS      Pre-emph */
 669         { 0x7, 0x0, 0x0 },      /* 1            400mV   0dB */
 670         { 0x6, 0x0, 0x0 },      /* 2            500mV   0dB */
 671         { 0x4, 0x0, 0x0 },      /* 3            650mV   0dB */
 672         { 0x2, 0x0, 0x0 },      /* 4            800mV   0dB */
 673         { 0x0, 0x0, 0x0 },      /* 5            1000mV  0dB */
 674         { 0x0, 0x0, 0x5 },      /* 6            Full    -1.5 dB */
 675         { 0x0, 0x0, 0x6 },      /* 7            Full    -1.8 dB */
 676         { 0x0, 0x0, 0x7 },      /* 8            Full    -2 dB */
 677         { 0x0, 0x0, 0x8 },      /* 9            Full    -2.5 dB */
 678         { 0x0, 0x0, 0xA },      /* 10           Full    -3 dB */
 679 };
 680
 681 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr[] = {
 682                                                 /* NT mV Trans mV db    */
 683         { 0xA, 0x32, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 684         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 685         { 0xC, 0x71, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 686         { 0x6, 0x7D, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 687         { 0xA, 0x4C, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 688         { 0xC, 0x73, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 689         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 690         { 0xC, 0x6C, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 691         { 0x6, 0x7F, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 692         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 693 };
 694
 695 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_dp_hbr2[] = {
 696                                                 /* NT mV Trans mV db    */
 697         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 698         { 0xA, 0x4F, 0x37, 0x00, 0x08 },        /* 350   500      3.1   */
 699         { 0xC, 0x63, 0x2F, 0x00, 0x10 },        /* 350   700      6.0   */
 700         { 0x6, 0x7F, 0x2B, 0x00, 0x14 },        /* 350   900      8.2   */
 701         { 0xA, 0x47, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 702         { 0xC, 0x63, 0x34, 0x00, 0x0B },        /* 500   700      2.9   */
 703         { 0x6, 0x7F, 0x2F, 0x00, 0x10 },        /* 500   900      5.1   */
 704         { 0xC, 0x61, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 705         { 0x6, 0x7B, 0x35, 0x00, 0x0A },        /* 600   900      3.5   */
 706         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 707 };
 708
 709 static const struct cnl_ddi_buf_trans tgl_uy_combo_phy_ddi_translations_dp_hbr2[] = {
 710                                                 /* NT mV Trans mV db    */
 711         { 0xA, 0x35, 0x3F, 0x00, 0x00 },        /* 350   350      0.0   */
 712         { 0xA, 0x4F, 0x36, 0x00, 0x09 },        /* 350   500      3.1   */
 713         { 0xC, 0x60, 0x32, 0x00, 0x0D },        /* 350   700      6.0   */
 714         { 0xC, 0x7F, 0x2D, 0x00, 0x12 },        /* 350   900      8.2   */
 715         { 0xC, 0x47, 0x3F, 0x00, 0x00 },        /* 500   500      0.0   */
 716         { 0xC, 0x6F, 0x36, 0x00, 0x09 },        /* 500   700      2.9   */
 717         { 0x6, 0x7D, 0x32, 0x00, 0x0D },        /* 500   900      5.1   */
 718         { 0x6, 0x60, 0x3C, 0x00, 0x03 },        /* 650   700      0.6   */
 719         { 0x6, 0x7F, 0x34, 0x00, 0x0B },        /* 600   900      3.5   */
 720         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 900   900      0.0   */
 721 };
 722
 723 /*
 724  * Cloned the HOBL entry to comply with the voltage and pre-emphasis entries
 725  * that DisplayPort specification requires
 726  */
 727 static const struct cnl_ddi_buf_trans tgl_combo_phy_ddi_translations_edp_hbr2_hobl[] = {
 728                                                 /* VS   pre-emp */
 729         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 0    0       */
 730         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 0    1       */
 731         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 0    2       */
 732         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 0    3       */
 733         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1    0       */
 734         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1    1       */
 735         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 1    2       */
 736         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 2    0       */
 737         { 0x6, 0x7F, 0x3F, 0x00, 0x00 },        /* 2    1       */
 738 };
 739
 740 static bool is_hobl_buf_trans(const struct cnl_ddi_buf_trans *table)
 741 {
 742         return table == tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
 743 }
 744
 745 static const struct ddi_buf_trans *
 746 bdw_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
 747 {
 748         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 749
 750         if (dev_priv->vbt.edp.low_vswing) {
 751                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
 752                 return bdw_ddi_translations_edp;
 753         } else {
 754                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 755                 return bdw_ddi_translations_dp;
 756         }
 757 }
 758
 759 static const struct ddi_buf_trans *
 760 skl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
 761 {
 762         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 763
 764         if (IS_SKL_ULX(dev_priv)) {
 765                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
 766                 return skl_y_ddi_translations_dp;
 767         } else if (IS_SKL_ULT(dev_priv)) {
 768                 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
 769                 return skl_u_ddi_translations_dp;
 770         } else {
 771                 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
 772                 return skl_ddi_translations_dp;
 773         }
 774 }
 775
 776 static const struct ddi_buf_trans *
 777 kbl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
 778 {
 779         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 780
 781         if (IS_KBL_ULX(dev_priv) ||
 782             IS_CFL_ULX(dev_priv) ||
 783             IS_CML_ULX(dev_priv)) {
 784                 *n_entries = ARRAY_SIZE(kbl_y_ddi_translations_dp);
 785                 return kbl_y_ddi_translations_dp;
 786         } else if (IS_KBL_ULT(dev_priv) ||
 787                    IS_CFL_ULT(dev_priv) ||
 788                    IS_CML_ULT(dev_priv)) {
 789                 *n_entries = ARRAY_SIZE(kbl_u_ddi_translations_dp);
 790                 return kbl_u_ddi_translations_dp;
 791         } else {
 792                 *n_entries = ARRAY_SIZE(kbl_ddi_translations_dp);
 793                 return kbl_ddi_translations_dp;
 794         }
 795 }
 796
 797 static const struct ddi_buf_trans *
 798 skl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
 799 {
 800         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 801
 802         if (dev_priv->vbt.edp.low_vswing) {
 803                 if (IS_SKL_ULX(dev_priv) ||
 804                     IS_KBL_ULX(dev_priv) ||
 805                     IS_CFL_ULX(dev_priv) ||
 806                     IS_CML_ULX(dev_priv)) {
 807                         *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
 808                         return skl_y_ddi_translations_edp;
 809                 } else if (IS_SKL_ULT(dev_priv) ||
 810                            IS_KBL_ULT(dev_priv) ||
 811                            IS_CFL_ULT(dev_priv) ||
 812                            IS_CML_ULT(dev_priv)) {
 813                         *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
 814                         return skl_u_ddi_translations_edp;
 815                 } else {
 816                         *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
 817                         return skl_ddi_translations_edp;
 818                 }
 819         }
 820
 821         if (IS_KABYLAKE(dev_priv) ||
 822             IS_COFFEELAKE(dev_priv) ||
 823             IS_COMETLAKE(dev_priv))
 824                 return kbl_get_buf_trans_dp(encoder, n_entries);
 825         else
 826                 return skl_get_buf_trans_dp(encoder, n_entries);
 827 }
 828
 829 static const struct ddi_buf_trans *
 830 skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
 831 {
 832         if (IS_SKL_ULX(dev_priv) ||
 833             IS_KBL_ULX(dev_priv) ||
 834             IS_CFL_ULX(dev_priv) ||
 835             IS_CML_ULX(dev_priv)) {
 836                 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
 837                 return skl_y_ddi_translations_hdmi;
 838         } else {
 839                 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
 840                 return skl_ddi_translations_hdmi;
 841         }
 842 }
 843
 844 static int skl_buf_trans_num_entries(enum port port, int n_entries)
 845 {
 846         /* Only DDIA and DDIE can select the 10th register with DP */
 847         if (port == PORT_A || port == PORT_E)
 848                 return min(n_entries, 10);
 849         else
 850                 return min(n_entries, 9);
 851 }
 852
 853 static const struct ddi_buf_trans *
 854 intel_ddi_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
 855 {
 856         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 857
 858         if (IS_KABYLAKE(dev_priv) ||
 859             IS_COFFEELAKE(dev_priv) ||
 860             IS_COMETLAKE(dev_priv)) {
 861                 const struct ddi_buf_trans *ddi_translations =
 862                         kbl_get_buf_trans_dp(encoder, n_entries);
 863                 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
 864                 return ddi_translations;
 865         } else if (IS_SKYLAKE(dev_priv)) {
 866                 const struct ddi_buf_trans *ddi_translations =
 867                         skl_get_buf_trans_dp(encoder, n_entries);
 868                 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
 869                 return ddi_translations;
 870         } else if (IS_BROADWELL(dev_priv)) {
 871                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
 872                 return  bdw_ddi_translations_dp;
 873         } else if (IS_HASWELL(dev_priv)) {
 874                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 875                 return hsw_ddi_translations_dp;
 876         }
 877
 878         *n_entries = 0;
 879         return NULL;
 880 }
 881
 882 static const struct ddi_buf_trans *
 883 intel_ddi_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
 884 {
 885         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 886
 887         if (IS_GEN9_BC(dev_priv)) {
 888                 const struct ddi_buf_trans *ddi_translations =
 889                         skl_get_buf_trans_edp(encoder, n_entries);
 890                 *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
 891                 return ddi_translations;
 892         } else if (IS_BROADWELL(dev_priv)) {
 893                 return bdw_get_buf_trans_edp(encoder, n_entries);
 894         } else if (IS_HASWELL(dev_priv)) {
 895                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
 896                 return hsw_ddi_translations_dp;
 897         }
 898
 899         *n_entries = 0;
 900         return NULL;
 901 }
 902
 903 static const struct ddi_buf_trans *
 904 intel_ddi_get_buf_trans_fdi(struct drm_i915_private *dev_priv,
 905                             int *n_entries)
 906 {
 907         if (IS_BROADWELL(dev_priv)) {
 908                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_fdi);
 909                 return bdw_ddi_translations_fdi;
 910         } else if (IS_HASWELL(dev_priv)) {
 911                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_fdi);
 912                 return hsw_ddi_translations_fdi;
 913         }
 914
 915         *n_entries = 0;
 916         return NULL;
 917 }
 918
 919 static const struct ddi_buf_trans *
 920 intel_ddi_get_buf_trans_hdmi(struct intel_encoder *encoder,
 921                              int *n_entries)
 922 {
 923         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 924
 925         if (IS_GEN9_BC(dev_priv)) {
 926                 return skl_get_buf_trans_hdmi(dev_priv, n_entries);
 927         } else if (IS_BROADWELL(dev_priv)) {
 928                 *n_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
 929                 return bdw_ddi_translations_hdmi;
 930         } else if (IS_HASWELL(dev_priv)) {
 931                 *n_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
 932                 return hsw_ddi_translations_hdmi;
 933         }
 934
 935         *n_entries = 0;
 936         return NULL;
 937 }
 938
 939 static const struct bxt_ddi_buf_trans *
 940 bxt_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
 941 {
 942         *n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
 943         return bxt_ddi_translations_dp;
 944 }
 945
 946 static const struct bxt_ddi_buf_trans *
 947 bxt_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
 948 {
 949         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 950
 951         if (dev_priv->vbt.edp.low_vswing) {
 952                 *n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
 953                 return bxt_ddi_translations_edp;
 954         }
 955
 956         return bxt_get_buf_trans_dp(encoder, n_entries);
 957 }
 958
 959 static const struct bxt_ddi_buf_trans *
 960 bxt_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries)
 961 {
 962         *n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
 963         return bxt_ddi_translations_hdmi;
 964 }
 965
 966 static const struct cnl_ddi_buf_trans *
 967 cnl_get_buf_trans_hdmi(struct intel_encoder *encoder, int *n_entries)
 968 {
 969         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 970         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 971
 972         if (voltage == VOLTAGE_INFO_0_85V) {
 973                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_85V);
 974                 return cnl_ddi_translations_hdmi_0_85V;
 975         } else if (voltage == VOLTAGE_INFO_0_95V) {
 976                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_0_95V);
 977                 return cnl_ddi_translations_hdmi_0_95V;
 978         } else if (voltage == VOLTAGE_INFO_1_05V) {
 979                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_hdmi_1_05V);
 980                 return cnl_ddi_translations_hdmi_1_05V;
 981         } else {
 982                 *n_entries = 1; /* shut up gcc */
 983                 MISSING_CASE(voltage);
 984         }
 985         return NULL;
 986 }
 987
 988 static const struct cnl_ddi_buf_trans *
 989 cnl_get_buf_trans_dp(struct intel_encoder *encoder, int *n_entries)
 990 {
 991         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 992         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
 993
 994         if (voltage == VOLTAGE_INFO_0_85V) {
 995                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_85V);
 996                 return cnl_ddi_translations_dp_0_85V;
 997         } else if (voltage == VOLTAGE_INFO_0_95V) {
 998                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_0_95V);
 999                 return cnl_ddi_translations_dp_0_95V;
1000         } else if (voltage == VOLTAGE_INFO_1_05V) {
1001                 *n_entries = ARRAY_SIZE(cnl_ddi_translations_dp_1_05V);
1002                 return cnl_ddi_translations_dp_1_05V;
1003         } else {
1004                 *n_entries = 1; /* shut up gcc */
1005                 MISSING_CASE(voltage);
1006         }
1007         return NULL;
1008 }
1009
1010 static const struct cnl_ddi_buf_trans *
1011 cnl_get_buf_trans_edp(struct intel_encoder *encoder, int *n_entries)
1012 {
1013         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1014         u32 voltage = intel_de_read(dev_priv, CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK;
1015
1016         if (dev_priv->vbt.edp.low_vswing) {
1017                 if (voltage == VOLTAGE_INFO_0_85V) {
1018                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_85V);
1019                         return cnl_ddi_translations_edp_0_85V;
1020                 } else if (voltage == VOLTAGE_INFO_0_95V) {
1021                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_0_95V);
1022                         return cnl_ddi_translations_edp_0_95V;
1023                 } else if (voltage == VOLTAGE_INFO_1_05V) {
1024                         *n_entries = ARRAY_SIZE(cnl_ddi_translations_edp_1_05V);
1025                         return cnl_ddi_translations_edp_1_05V;
1026                 } else {
1027                         *n_entries = 1; /* shut up gcc */
1028                         MISSING_CASE(voltage);
1029                 }
1030                 return NULL;
1031         } else {
1032                 return cnl_get_buf_trans_dp(encoder, n_entries);
1033         }
1034 }
1035
1036 static const struct cnl_ddi_buf_trans *
1037 icl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
1038                         int *n_entries)
1039 {
1040         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1041
1042         if (type == INTEL_OUTPUT_HDMI) {
1043                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
1044                 return icl_combo_phy_ddi_translations_hdmi;
1045         } else if (rate > 540000 && type == INTEL_OUTPUT_EDP) {
1046                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
1047                 return icl_combo_phy_ddi_translations_edp_hbr3;
1048         } else if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
1049                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
1050                 return icl_combo_phy_ddi_translations_edp_hbr2;
1051         }
1052
1053         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_dp_hbr2);
1054         return icl_combo_phy_ddi_translations_dp_hbr2;
1055 }
1056
1057 static const struct icl_mg_phy_ddi_buf_trans *
1058 icl_get_mg_buf_trans(struct intel_encoder *encoder, int type, int rate,
1059                      int *n_entries)
1060 {
1061         if (type == INTEL_OUTPUT_HDMI) {
1062                 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hdmi);
1063                 return icl_mg_phy_ddi_translations_hdmi;
1064         } else if (rate > 270000) {
1065                 *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_hbr2_hbr3);
1066                 return icl_mg_phy_ddi_translations_hbr2_hbr3;
1067         }
1068
1069         *n_entries = ARRAY_SIZE(icl_mg_phy_ddi_translations_rbr_hbr);
1070         return icl_mg_phy_ddi_translations_rbr_hbr;
1071 }
1072
1073 static const struct cnl_ddi_buf_trans *
1074 ehl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
1075                         int *n_entries)
1076 {
1077         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1078
1079         switch (type) {
1080         case INTEL_OUTPUT_HDMI:
1081                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
1082                 return icl_combo_phy_ddi_translations_hdmi;
1083         case INTEL_OUTPUT_EDP:
1084                 if (dev_priv->vbt.edp.low_vswing) {
1085                         if (rate > 540000) {
1086                                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
1087                                 return icl_combo_phy_ddi_translations_edp_hbr3;
1088                         } else {
1089                                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
1090                                 return icl_combo_phy_ddi_translations_edp_hbr2;
1091                         }
1092                 }
1093                 /* fall through */
1094         default:
1095                 /* All combo DP and eDP ports that do not support low_vswing */
1096                 *n_entries = ARRAY_SIZE(ehl_combo_phy_ddi_translations_dp);
1097                 return ehl_combo_phy_ddi_translations_dp;
1098         }
1099 }
1100
1101 static const struct cnl_ddi_buf_trans *
1102 tgl_get_combo_buf_trans(struct intel_encoder *encoder, int type, int rate,
1103                         int *n_entries)
1104 {
1105         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1106
1107         switch (type) {
1108         case INTEL_OUTPUT_HDMI:
1109                 *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_hdmi);
1110                 return icl_combo_phy_ddi_translations_hdmi;
1111         case INTEL_OUTPUT_EDP:
1112                 if (dev_priv->vbt.edp.hobl) {
1113                         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1114
1115                         if (!intel_dp->hobl_failed && rate <= 540000) {
1116                                 /* Same table applies to TGL, RKL and DG1 */
1117                                 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_edp_hbr2_hobl);
1118                                 return tgl_combo_phy_ddi_translations_edp_hbr2_hobl;
1119                         }
1120                 }
1121
1122                 if (rate > 540000) {
1123                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr3);
1124                         return icl_combo_phy_ddi_translations_edp_hbr3;
1125                 } else if (dev_priv->vbt.edp.low_vswing) {
1126                         *n_entries = ARRAY_SIZE(icl_combo_phy_ddi_translations_edp_hbr2);
1127                         return icl_combo_phy_ddi_translations_edp_hbr2;
1128                 }
1129                 /* fall through */
1130         default:
1131                 /* All combo DP and eDP ports that do not support low_vswing */
1132                 if (rate > 270000) {
1133                         if (IS_TGL_U(dev_priv) || IS_TGL_Y(dev_priv)) {
1134                                 *n_entries = ARRAY_SIZE(tgl_uy_combo_phy_ddi_translations_dp_hbr2);
1135                                 return tgl_uy_combo_phy_ddi_translations_dp_hbr2;
1136                         }
1137
1138                         *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr2);
1139                         return tgl_combo_phy_ddi_translations_dp_hbr2;
1140                 }
1141
1142                 *n_entries = ARRAY_SIZE(tgl_combo_phy_ddi_translations_dp_hbr);
1143                 return tgl_combo_phy_ddi_translations_dp_hbr;
1144         }
1145 }
1146
1147 static const struct tgl_dkl_phy_ddi_buf_trans *
1148 tgl_get_dkl_buf_trans(struct intel_encoder *encoder, int type, int rate,
1149                       int *n_entries)
1150 {
1151         if (type == INTEL_OUTPUT_HDMI) {
1152                 *n_entries = ARRAY_SIZE(tgl_dkl_phy_hdmi_ddi_trans);
1153                 return tgl_dkl_phy_hdmi_ddi_trans;
1154         } else if (rate > 270000) {
1155                 *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans_hbr2);
1156                 return tgl_dkl_phy_dp_ddi_trans_hbr2;
1157         }
1158
1159         *n_entries = ARRAY_SIZE(tgl_dkl_phy_dp_ddi_trans);
1160         return tgl_dkl_phy_dp_ddi_trans;
1161 }
1162
1163 static int intel_ddi_hdmi_level(struct intel_encoder *encoder)
1164 {
1165         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1166         int n_entries, level, default_entry;
1167         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1168
1169         if (INTEL_GEN(dev_priv) >= 12) {
1170                 if (intel_phy_is_combo(dev_priv, phy))
1171                         tgl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI,
1172                                                 0, &n_entries);
1173                 else
1174                         tgl_get_dkl_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0,
1175                                               &n_entries);
1176                 default_entry = n_entries - 1;
1177         } else if (INTEL_GEN(dev_priv) == 11) {
1178                 if (intel_phy_is_combo(dev_priv, phy))
1179                         icl_get_combo_buf_trans(encoder, INTEL_OUTPUT_HDMI,
1180                                                 0, &n_entries);
1181                 else
1182                         icl_get_mg_buf_trans(encoder, INTEL_OUTPUT_HDMI, 0,
1183                                              &n_entries);
1184                 default_entry = n_entries - 1;
1185         } else if (IS_CANNONLAKE(dev_priv)) {
1186                 cnl_get_buf_trans_hdmi(encoder, &n_entries);
1187                 default_entry = n_entries - 1;
1188         } else if (IS_GEN9_LP(dev_priv)) {
1189                 bxt_get_buf_trans_hdmi(encoder, &n_entries);
1190                 default_entry = n_entries - 1;
1191         } else if (IS_GEN9_BC(dev_priv)) {
1192                 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1193                 default_entry = 8;
1194         } else if (IS_BROADWELL(dev_priv)) {
1195                 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1196                 default_entry = 7;
1197         } else if (IS_HASWELL(dev_priv)) {
1198                 intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1199                 default_entry = 6;
1200         } else {
1201                 drm_WARN(&dev_priv->drm, 1, "ddi translation table missing\n");
1202                 return 0;
1203         }
1204
1205         if (drm_WARN_ON_ONCE(&dev_priv->drm, n_entries == 0))
1206                 return 0;
1207
1208         level = intel_bios_hdmi_level_shift(encoder);
1209         if (level < 0)
1210                 level = default_entry;
1211
1212         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1213                 level = n_entries - 1;
1214
1215         return level;
1216 }
1217
1218 /*
1219  * Starting with Haswell, DDI port buffers must be programmed with correct
1220  * values in advance. This function programs the correct values for
1221  * DP/eDP/FDI use cases.
1222  */
1223 static void intel_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
1224                                          const struct intel_crtc_state *crtc_state)
1225 {
1226         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1227         u32 iboost_bit = 0;
1228         int i, n_entries;
1229         enum port port = encoder->port;
1230         const struct ddi_buf_trans *ddi_translations;
1231
1232         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1233                 ddi_translations = intel_ddi_get_buf_trans_fdi(dev_priv,
1234                                                                &n_entries);
1235         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1236                 ddi_translations = intel_ddi_get_buf_trans_edp(encoder,
1237                                                                &n_entries);
1238         else
1239                 ddi_translations = intel_ddi_get_buf_trans_dp(encoder,
1240                                                               &n_entries);
1241
1242         /* If we're boosting the current, set bit 31 of trans1 */
1243         if (IS_GEN9_BC(dev_priv) && intel_bios_dp_boost_level(encoder))
1244                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1245
1246         for (i = 0; i < n_entries; i++) {
1247                 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i),
1248                                ddi_translations[i].trans1 | iboost_bit);
1249                 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i),
1250                                ddi_translations[i].trans2);
1251         }
1252 }
1253
1254 /*
1255  * Starting with Haswell, DDI port buffers must be programmed with correct
1256  * values in advance. This function programs the correct values for
1257  * HDMI/DVI use cases.
1258  */
1259 static void intel_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
1260                                            int level)
1261 {
1262         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1263         u32 iboost_bit = 0;
1264         int n_entries;
1265         enum port port = encoder->port;
1266         const struct ddi_buf_trans *ddi_translations;
1267
1268         ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
1269
1270         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
1271                 return;
1272         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
1273                 level = n_entries - 1;
1274
1275         /* If we're boosting the current, set bit 31 of trans1 */
1276         if (IS_GEN9_BC(dev_priv) && intel_bios_hdmi_boost_level(encoder))
1277                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
1278
1279         /* Entry 9 is for HDMI: */
1280         intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9),
1281                        ddi_translations[level].trans1 | iboost_bit);
1282         intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9),
1283                        ddi_translations[level].trans2);
1284 }
1285
1286 static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
1287                                     enum port port)
1288 {
1289         if (IS_BROXTON(dev_priv)) {
1290                 udelay(16);
1291                 return;
1292         }
1293
1294         if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
1295                          DDI_BUF_IS_IDLE), 8))
1296                 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n",
1297                         port_name(port));
1298 }
1299
1300 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
1301                                       enum port port)
1302 {
1303         /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */
1304         if (INTEL_GEN(dev_priv) < 10 && !IS_GEMINILAKE(dev_priv)) {
1305                 usleep_range(518, 1000);
1306                 return;
1307         }
1308
1309         if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
1310                           DDI_BUF_IS_IDLE), 500))
1311                 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n",
1312                         port_name(port));
1313 }
1314
1315 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
1316 {
1317         switch (pll->info->id) {
1318         case DPLL_ID_WRPLL1:
1319                 return PORT_CLK_SEL_WRPLL1;
1320         case DPLL_ID_WRPLL2:
1321                 return PORT_CLK_SEL_WRPLL2;
1322         case DPLL_ID_SPLL:
1323                 return PORT_CLK_SEL_SPLL;
1324         case DPLL_ID_LCPLL_810:
1325                 return PORT_CLK_SEL_LCPLL_810;
1326         case DPLL_ID_LCPLL_1350:
1327                 return PORT_CLK_SEL_LCPLL_1350;
1328         case DPLL_ID_LCPLL_2700:
1329                 return PORT_CLK_SEL_LCPLL_2700;
1330         default:
1331                 MISSING_CASE(pll->info->id);
1332                 return PORT_CLK_SEL_NONE;
1333         }
1334 }
1335
1336 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
1337                                   const struct intel_crtc_state *crtc_state)
1338 {
1339         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1340         int clock = crtc_state->port_clock;
1341         const enum intel_dpll_id id = pll->info->id;
1342
1343         switch (id) {
1344         default:
1345                 /*
1346                  * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
1347                  * here, so do warn if this get passed in
1348                  */
1349                 MISSING_CASE(id);
1350                 return DDI_CLK_SEL_NONE;
1351         case DPLL_ID_ICL_TBTPLL:
1352                 switch (clock) {
1353                 case 162000:
1354                         return DDI_CLK_SEL_TBT_162;
1355                 case 270000:
1356                         return DDI_CLK_SEL_TBT_270;
1357                 case 540000:
1358                         return DDI_CLK_SEL_TBT_540;
1359                 case 810000:
1360                         return DDI_CLK_SEL_TBT_810;
1361                 default:
1362                         MISSING_CASE(clock);
1363                         return DDI_CLK_SEL_NONE;
1364                 }
1365         case DPLL_ID_ICL_MGPLL1:
1366         case DPLL_ID_ICL_MGPLL2:
1367         case DPLL_ID_ICL_MGPLL3:
1368         case DPLL_ID_ICL_MGPLL4:
1369         case DPLL_ID_TGL_MGPLL5:
1370         case DPLL_ID_TGL_MGPLL6:
1371                 return DDI_CLK_SEL_MG;
1372         }
1373 }
1374
1375 /* Starting with Haswell, different DDI ports can work in FDI mode for
1376  * connection to the PCH-located connectors. For this, it is necessary to train
1377  * both the DDI port and PCH receiver for the desired DDI buffer settings.
1378  *
1379  * The recommended port to work in FDI mode is DDI E, which we use here. Also,
1380  * please note that when FDI mode is active on DDI E, it shares 2 lines with
1381  * DDI A (which is used for eDP)
1382  */
1383
1384 void hsw_fdi_link_train(struct intel_encoder *encoder,
1385                         const struct intel_crtc_state *crtc_state)
1386 {
1387         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1388         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1389         u32 temp, i, rx_ctl_val, ddi_pll_sel;
1390
1391         intel_prepare_dp_ddi_buffers(encoder, crtc_state);
1392
1393         /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
1394          * mode set "sequence for CRT port" document:
1395          * - TP1 to TP2 time with the default value
1396          * - FDI delay to 90h
1397          *
1398          * WaFDIAutoLinkSetTimingOverrride:hsw
1399          */
1400         intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A),
1401                        FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
1402
1403         /* Enable the PCH Receiver FDI PLL */
1404         rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
1405                      FDI_RX_PLL_ENABLE |
1406                      FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
1407         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1408         intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1409         udelay(220);
1410
1411         /* Switch from Rawclk to PCDclk */
1412         rx_ctl_val |= FDI_PCDCLK;
1413         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1414
1415         /* Configure Port Clock Select */
1416         ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll);
1417         intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel);
1418         drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL);
1419
1420         /* Start the training iterating through available voltages and emphasis,
1421          * testing each value twice. */
1422         for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
1423                 /* Configure DP_TP_CTL with auto-training */
1424                 intel_de_write(dev_priv, DP_TP_CTL(PORT_E),
1425                                DP_TP_CTL_FDI_AUTOTRAIN |
1426                                DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1427                                DP_TP_CTL_LINK_TRAIN_PAT1 |
1428                                DP_TP_CTL_ENABLE);
1429
1430                 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
1431                  * DDI E does not support port reversal, the functionality is
1432                  * achieved on the PCH side in FDI_RX_CTL, so no need to set the
1433                  * port reversal bit */
1434                 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E),
1435                                DDI_BUF_CTL_ENABLE | ((crtc_state->fdi_lanes - 1) << 1) | DDI_BUF_TRANS_SELECT(i / 2));
1436                 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
1437
1438                 udelay(600);
1439
1440                 /* Program PCH FDI Receiver TU */
1441                 intel_de_write(dev_priv, FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
1442
1443                 /* Enable PCH FDI Receiver with auto-training */
1444                 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
1445                 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1446                 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1447
1448                 /* Wait for FDI receiver lane calibration */
1449                 udelay(30);
1450
1451                 /* Unset FDI_RX_MISC pwrdn lanes */
1452                 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
1453                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1454                 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
1455                 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
1456
1457                 /* Wait for FDI auto training time */
1458                 udelay(5);
1459
1460                 temp = intel_de_read(dev_priv, DP_TP_STATUS(PORT_E));
1461                 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
1462                         drm_dbg_kms(&dev_priv->drm,
1463                                     "FDI link training done on step %d\n", i);
1464                         break;
1465                 }
1466
1467                 /*
1468                  * Leave things enabled even if we failed to train FDI.
1469                  * Results in less fireworks from the state checker.
1470                  */
1471                 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
1472                         drm_err(&dev_priv->drm, "FDI link training failed!\n");
1473                         break;
1474                 }
1475
1476                 rx_ctl_val &= ~FDI_RX_ENABLE;
1477                 intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val);
1478                 intel_de_posting_read(dev_priv, FDI_RX_CTL(PIPE_A));
1479
1480                 temp = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_E));
1481                 temp &= ~DDI_BUF_CTL_ENABLE;
1482                 intel_de_write(dev_priv, DDI_BUF_CTL(PORT_E), temp);
1483                 intel_de_posting_read(dev_priv, DDI_BUF_CTL(PORT_E));
1484
1485                 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
1486                 temp = intel_de_read(dev_priv, DP_TP_CTL(PORT_E));
1487                 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1488                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1489                 intel_de_write(dev_priv, DP_TP_CTL(PORT_E), temp);
1490                 intel_de_posting_read(dev_priv, DP_TP_CTL(PORT_E));
1491
1492                 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
1493
1494                 /* Reset FDI_RX_MISC pwrdn lanes */
1495                 temp = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
1496                 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
1497                 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
1498                 intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), temp);
1499                 intel_de_posting_read(dev_priv, FDI_RX_MISC(PIPE_A));
1500         }
1501
1502         /* Enable normal pixel sending for FDI */
1503         intel_de_write(dev_priv, DP_TP_CTL(PORT_E),
1504                        DP_TP_CTL_FDI_AUTOTRAIN |
1505                        DP_TP_CTL_LINK_TRAIN_NORMAL |
1506                        DP_TP_CTL_ENHANCED_FRAME_ENABLE |
1507                        DP_TP_CTL_ENABLE);
1508 }
1509
1510 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
1511 {
1512         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1513         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1514
1515         intel_dp->DP = dig_port->saved_port_bits |
1516                 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
1517         intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
1518 }
1519
1520 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
1521                                  enum port port)
1522 {
1523         u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
1524
1525         switch (val) {
1526         case DDI_CLK_SEL_NONE:
1527                 return 0;
1528         case DDI_CLK_SEL_TBT_162:
1529                 return 162000;
1530         case DDI_CLK_SEL_TBT_270:
1531                 return 270000;
1532         case DDI_CLK_SEL_TBT_540:
1533                 return 540000;
1534         case DDI_CLK_SEL_TBT_810:
1535                 return 810000;
1536         default:
1537                 MISSING_CASE(val);
1538                 return 0;
1539         }
1540 }
1541
1542 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
1543 {
1544         int dotclock;
1545
1546         if (pipe_config->has_pch_encoder)
1547                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1548                                                     &pipe_config->fdi_m_n);
1549         else if (intel_crtc_has_dp_encoder(pipe_config))
1550                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
1551                                                     &pipe_config->dp_m_n);
1552         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
1553                 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
1554         else
1555                 dotclock = pipe_config->port_clock;
1556
1557         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
1558             !intel_crtc_has_dp_encoder(pipe_config))
1559                 dotclock *= 2;
1560
1561         if (pipe_config->pixel_multiplier)
1562                 dotclock /= pipe_config->pixel_multiplier;
1563
1564         pipe_config->hw.adjusted_mode.crtc_clock = dotclock;
1565 }
1566
1567 static void intel_ddi_clock_get(struct intel_encoder *encoder,
1568                                 struct intel_crtc_state *pipe_config)
1569 {
1570         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1571         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1572
1573         if (intel_phy_is_tc(dev_priv, phy) &&
1574             intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll) ==
1575             DPLL_ID_ICL_TBTPLL)
1576                 pipe_config->port_clock = icl_calc_tbt_pll_link(dev_priv,
1577                                                                 encoder->port);
1578         else
1579                 pipe_config->port_clock =
1580                         intel_dpll_get_freq(dev_priv, pipe_config->shared_dpll);
1581
1582         ddi_dotclock_get(pipe_config);
1583 }
1584
1585 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
1586                           const struct drm_connector_state *conn_state)
1587 {
1588         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1589         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1590         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1591         u32 temp;
1592
1593         if (!intel_crtc_has_dp_encoder(crtc_state))
1594                 return;
1595
1596         drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder));
1597
1598         temp = DP_MSA_MISC_SYNC_CLOCK;
1599
1600         switch (crtc_state->pipe_bpp) {
1601         case 18:
1602                 temp |= DP_MSA_MISC_6_BPC;
1603                 break;
1604         case 24:
1605                 temp |= DP_MSA_MISC_8_BPC;
1606                 break;
1607         case 30:
1608                 temp |= DP_MSA_MISC_10_BPC;
1609                 break;
1610         case 36:
1611                 temp |= DP_MSA_MISC_12_BPC;
1612                 break;
1613         default:
1614                 MISSING_CASE(crtc_state->pipe_bpp);
1615                 break;
1616         }
1617
1618         /* nonsense combination */
1619         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
1620                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
1621
1622         if (crtc_state->limited_color_range)
1623                 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
1624
1625         /*
1626          * As per DP 1.2 spec section 2.3.4.3 while sending
1627          * YCBCR 444 signals we should program MSA MISC1/0 fields with
1628          * colorspace information.
1629          */
1630         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
1631                 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
1632
1633         /*
1634          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
1635          * of Color Encoding Format and Content Color Gamut] while sending
1636          * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
1637          * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
1638          */
1639         if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
1640                 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
1641
1642         intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp);
1643 }
1644
1645 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
1646 {
1647         if (master_transcoder == TRANSCODER_EDP)
1648                 return 0;
1649         else
1650                 return master_transcoder + 1;
1651 }
1652
1653 /*
1654  * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
1655  *
1656  * Only intended to be used by intel_ddi_enable_transcoder_func() and
1657  * intel_ddi_config_transcoder_func().
1658  */
1659 static u32
1660 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
1661                                       const struct intel_crtc_state *crtc_state)
1662 {
1663         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1664         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1665         enum pipe pipe = crtc->pipe;
1666         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1667         enum port port = encoder->port;
1668         u32 temp;
1669
1670         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1671         temp = TRANS_DDI_FUNC_ENABLE;
1672         if (INTEL_GEN(dev_priv) >= 12)
1673                 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
1674         else
1675                 temp |= TRANS_DDI_SELECT_PORT(port);
1676
1677         switch (crtc_state->pipe_bpp) {
1678         case 18:
1679                 temp |= TRANS_DDI_BPC_6;
1680                 break;
1681         case 24:
1682                 temp |= TRANS_DDI_BPC_8;
1683                 break;
1684         case 30:
1685                 temp |= TRANS_DDI_BPC_10;
1686                 break;
1687         case 36:
1688                 temp |= TRANS_DDI_BPC_12;
1689                 break;
1690         default:
1691                 BUG();
1692         }
1693
1694         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
1695                 temp |= TRANS_DDI_PVSYNC;
1696         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
1697                 temp |= TRANS_DDI_PHSYNC;
1698
1699         if (cpu_transcoder == TRANSCODER_EDP) {
1700                 switch (pipe) {
1701                 case PIPE_A:
1702                         /* On Haswell, can only use the always-on power well for
1703                          * eDP when not using the panel fitter, and when not
1704                          * using motion blur mitigation (which we don't
1705                          * support). */
1706                         if (crtc_state->pch_pfit.force_thru)
1707                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1708                         else
1709                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
1710                         break;
1711                 case PIPE_B:
1712                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1713                         break;
1714                 case PIPE_C:
1715                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1716                         break;
1717                 default:
1718                         BUG();
1719                         break;
1720                 }
1721         }
1722
1723         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1724                 if (crtc_state->has_hdmi_sink)
1725                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
1726                 else
1727                         temp |= TRANS_DDI_MODE_SELECT_DVI;
1728
1729                 if (crtc_state->hdmi_scrambling)
1730                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
1731                 if (crtc_state->hdmi_high_tmds_clock_ratio)
1732                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
1733         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
1734                 temp |= TRANS_DDI_MODE_SELECT_FDI;
1735                 temp |= (crtc_state->fdi_lanes - 1) << 1;
1736         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
1737                 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1738                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1739
1740                 if (INTEL_GEN(dev_priv) >= 12) {
1741                         enum transcoder master;
1742
1743                         master = crtc_state->mst_master_transcoder;
1744                         drm_WARN_ON(&dev_priv->drm,
1745                                     master == INVALID_TRANSCODER);
1746                         temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
1747                 }
1748         } else {
1749                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1750                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
1751         }
1752
1753         if (IS_GEN_RANGE(dev_priv, 8, 10) &&
1754             crtc_state->master_transcoder != INVALID_TRANSCODER) {
1755                 u8 master_select =
1756                         bdw_trans_port_sync_master_select(crtc_state->master_transcoder);
1757
1758                 temp |= TRANS_DDI_PORT_SYNC_ENABLE |
1759                         TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select);
1760         }
1761
1762         return temp;
1763 }
1764
1765 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
1766                                       const struct intel_crtc_state *crtc_state)
1767 {
1768         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1769         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1770         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1771
1772         if (INTEL_GEN(dev_priv) >= 11) {
1773                 enum transcoder master_transcoder = crtc_state->master_transcoder;
1774                 u32 ctl2 = 0;
1775
1776                 if (master_transcoder != INVALID_TRANSCODER) {
1777                         u8 master_select =
1778                                 bdw_trans_port_sync_master_select(master_transcoder);
1779
1780                         ctl2 |= PORT_SYNC_MODE_ENABLE |
1781                                 PORT_SYNC_MODE_MASTER_SELECT(master_select);
1782                 }
1783
1784                 intel_de_write(dev_priv,
1785                                TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2);
1786         }
1787
1788         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
1789                        intel_ddi_transcoder_func_reg_val_get(encoder,
1790                                                              crtc_state));
1791 }
1792
1793 /*
1794  * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
1795  * bit.
1796  */
1797 static void
1798 intel_ddi_config_transcoder_func(struct intel_encoder *encoder,
1799                                  const struct intel_crtc_state *crtc_state)
1800 {
1801         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1802         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1803         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1804         u32 ctl;
1805
1806         ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
1807         ctl &= ~TRANS_DDI_FUNC_ENABLE;
1808         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
1809 }
1810
1811 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
1812 {
1813         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1814         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1815         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1816         u32 ctl;
1817
1818         if (INTEL_GEN(dev_priv) >= 11)
1819                 intel_de_write(dev_priv,
1820                                TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0);
1821
1822         ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
1823
1824         ctl &= ~TRANS_DDI_FUNC_ENABLE;
1825
1826         if (IS_GEN_RANGE(dev_priv, 8, 10))
1827                 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
1828                          TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
1829
1830         if (INTEL_GEN(dev_priv) >= 12) {
1831                 if (!intel_dp_mst_is_master_trans(crtc_state)) {
1832                         ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
1833                                  TRANS_DDI_MODE_SELECT_MASK);
1834                 }
1835         } else {
1836                 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
1837         }
1838
1839         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
1840
1841         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
1842             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1843                 drm_dbg_kms(&dev_priv->drm,
1844                             "Quirk Increase DDI disabled time\n");
1845                 /* Quirk time at 100ms for reliable operation */
1846                 msleep(100);
1847         }
1848 }
1849
1850 int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder,
1851                                      bool enable)
1852 {
1853         struct drm_device *dev = intel_encoder->base.dev;
1854         struct drm_i915_private *dev_priv = to_i915(dev);
1855         intel_wakeref_t wakeref;
1856         enum pipe pipe = 0;
1857         int ret = 0;
1858         u32 tmp;
1859
1860         wakeref = intel_display_power_get_if_enabled(dev_priv,
1861                                                      intel_encoder->power_domain);
1862         if (drm_WARN_ON(dev, !wakeref))
1863                 return -ENXIO;
1864
1865         if (drm_WARN_ON(dev,
1866                         !intel_encoder->get_hw_state(intel_encoder, &pipe))) {
1867                 ret = -EIO;
1868                 goto out;
1869         }
1870
1871         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe));
1872         if (enable)
1873                 tmp |= TRANS_DDI_HDCP_SIGNALLING;
1874         else
1875                 tmp &= ~TRANS_DDI_HDCP_SIGNALLING;
1876         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), tmp);
1877 out:
1878         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
1879         return ret;
1880 }
1881
1882 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1883 {
1884         struct drm_device *dev = intel_connector->base.dev;
1885         struct drm_i915_private *dev_priv = to_i915(dev);
1886         struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
1887         int type = intel_connector->base.connector_type;
1888         enum port port = encoder->port;
1889         enum transcoder cpu_transcoder;
1890         intel_wakeref_t wakeref;
1891         enum pipe pipe = 0;
1892         u32 tmp;
1893         bool ret;
1894
1895         wakeref = intel_display_power_get_if_enabled(dev_priv,
1896                                                      encoder->power_domain);
1897         if (!wakeref)
1898                 return false;
1899
1900         if (!encoder->get_hw_state(encoder, &pipe)) {
1901                 ret = false;
1902                 goto out;
1903         }
1904
1905         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
1906                 cpu_transcoder = TRANSCODER_EDP;
1907         else
1908                 cpu_transcoder = (enum transcoder) pipe;
1909
1910         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
1911
1912         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1913         case TRANS_DDI_MODE_SELECT_HDMI:
1914         case TRANS_DDI_MODE_SELECT_DVI:
1915                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1916                 break;
1917
1918         case TRANS_DDI_MODE_SELECT_DP_SST:
1919                 ret = type == DRM_MODE_CONNECTOR_eDP ||
1920                       type == DRM_MODE_CONNECTOR_DisplayPort;
1921                 break;
1922
1923         case TRANS_DDI_MODE_SELECT_DP_MST:
1924                 /* if the transcoder is in MST state then
1925                  * connector isn't connected */
1926                 ret = false;
1927                 break;
1928
1929         case TRANS_DDI_MODE_SELECT_FDI:
1930                 ret = type == DRM_MODE_CONNECTOR_VGA;
1931                 break;
1932
1933         default:
1934                 ret = false;
1935                 break;
1936         }
1937
1938 out:
1939         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1940
1941         return ret;
1942 }
1943
1944 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
1945                                         u8 *pipe_mask, bool *is_dp_mst)
1946 {
1947         struct drm_device *dev = encoder->base.dev;
1948         struct drm_i915_private *dev_priv = to_i915(dev);
1949         enum port port = encoder->port;
1950         intel_wakeref_t wakeref;
1951         enum pipe p;
1952         u32 tmp;
1953         u8 mst_pipe_mask;
1954
1955         *pipe_mask = 0;
1956         *is_dp_mst = false;
1957
1958         wakeref = intel_display_power_get_if_enabled(dev_priv,
1959                                                      encoder->power_domain);
1960         if (!wakeref)
1961                 return;
1962
1963         tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
1964         if (!(tmp & DDI_BUF_CTL_ENABLE))
1965                 goto out;
1966
1967         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) {
1968                 tmp = intel_de_read(dev_priv,
1969                                     TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
1970
1971                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1972                 default:
1973                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
1974                         /* fallthrough */
1975                 case TRANS_DDI_EDP_INPUT_A_ON:
1976                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1977                         *pipe_mask = BIT(PIPE_A);
1978                         break;
1979                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1980                         *pipe_mask = BIT(PIPE_B);
1981                         break;
1982                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1983                         *pipe_mask = BIT(PIPE_C);
1984                         break;
1985                 }
1986
1987                 goto out;
1988         }
1989
1990         mst_pipe_mask = 0;
1991         for_each_pipe(dev_priv, p) {
1992                 enum transcoder cpu_transcoder = (enum transcoder)p;
1993                 unsigned int port_mask, ddi_select;
1994                 intel_wakeref_t trans_wakeref;
1995
1996                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
1997                                                                    POWER_DOMAIN_TRANSCODER(cpu_transcoder));
1998                 if (!trans_wakeref)
1999                         continue;
2000
2001                 if (INTEL_GEN(dev_priv) >= 12) {
2002                         port_mask = TGL_TRANS_DDI_PORT_MASK;
2003                         ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
2004                 } else {
2005                         port_mask = TRANS_DDI_PORT_MASK;
2006                         ddi_select = TRANS_DDI_SELECT_PORT(port);
2007                 }
2008
2009                 tmp = intel_de_read(dev_priv,
2010                                     TRANS_DDI_FUNC_CTL(cpu_transcoder));
2011                 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
2012                                         trans_wakeref);
2013
2014                 if ((tmp & port_mask) != ddi_select)
2015                         continue;
2016
2017                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
2018                     TRANS_DDI_MODE_SELECT_DP_MST)
2019                         mst_pipe_mask |= BIT(p);
2020
2021                 *pipe_mask |= BIT(p);
2022         }
2023
2024         if (!*pipe_mask)
2025                 drm_dbg_kms(&dev_priv->drm,
2026                             "No pipe for [ENCODER:%d:%s] found\n",
2027                             encoder->base.base.id, encoder->base.name);
2028
2029         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
2030                 drm_dbg_kms(&dev_priv->drm,
2031                             "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
2032                             encoder->base.base.id, encoder->base.name,
2033                             *pipe_mask);
2034                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
2035         }
2036
2037         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
2038                 drm_dbg_kms(&dev_priv->drm,
2039                             "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
2040                             encoder->base.base.id, encoder->base.name,
2041                             *pipe_mask, mst_pipe_mask);
2042         else
2043                 *is_dp_mst = mst_pipe_mask;
2044
2045 out:
2046         if (*pipe_mask && IS_GEN9_LP(dev_priv)) {
2047                 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port));
2048                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
2049                             BXT_PHY_LANE_POWERDOWN_ACK |
2050                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
2051                         drm_err(&dev_priv->drm,
2052                                 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n",
2053                                 encoder->base.base.id, encoder->base.name, tmp);
2054         }
2055
2056         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
2057 }
2058
2059 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
2060                             enum pipe *pipe)
2061 {
2062         u8 pipe_mask;
2063         bool is_mst;
2064
2065         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
2066
2067         if (is_mst || !pipe_mask)
2068                 return false;
2069
2070         *pipe = ffs(pipe_mask) - 1;
2071
2072         return true;
2073 }
2074
2075 static enum intel_display_power_domain
2076 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
2077 {
2078         /* CNL+ HW requires corresponding AUX IOs to be powered up for PSR with
2079          * DC states enabled at the same time, while for driver initiated AUX
2080          * transfers we need the same AUX IOs to be powered but with DC states
2081          * disabled. Accordingly use the AUX power domain here which leaves DC
2082          * states enabled.
2083          * However, for non-A AUX ports the corresponding non-EDP transcoders
2084          * would have already enabled power well 2 and DC_OFF. This means we can
2085          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
2086          * specific AUX_IO reference without powering up any extra wells.
2087          * Note that PSR is enabled only on Port A even though this function
2088          * returns the correct domain for other ports too.
2089          */
2090         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
2091                                               intel_aux_power_domain(dig_port);
2092 }
2093
2094 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
2095                                         struct intel_crtc_state *crtc_state)
2096 {
2097         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2098         struct intel_digital_port *dig_port;
2099         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2100
2101         /*
2102          * TODO: Add support for MST encoders. Atm, the following should never
2103          * happen since fake-MST encoders don't set their get_power_domains()
2104          * hook.
2105          */
2106         if (drm_WARN_ON(&dev_priv->drm,
2107                         intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
2108                 return;
2109
2110         dig_port = enc_to_dig_port(encoder);
2111
2112         if (!intel_phy_is_tc(dev_priv, phy) ||
2113             dig_port->tc_mode != TC_PORT_TBT_ALT)
2114                 intel_display_power_get(dev_priv,
2115                                         dig_port->ddi_io_power_domain);
2116
2117         /*
2118          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
2119          * ports.
2120          */
2121         if (intel_crtc_has_dp_encoder(crtc_state) ||
2122             intel_phy_is_tc(dev_priv, phy))
2123                 intel_display_power_get(dev_priv,
2124                                         intel_ddi_main_link_aux_domain(dig_port));
2125
2126         /*
2127          * VDSC power is needed when DSC is enabled
2128          */
2129         if (crtc_state->dsc.compression_enable)
2130                 intel_display_power_get(dev_priv,
2131                                         intel_dsc_power_domain(crtc_state));
2132 }
2133
2134 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
2135                                  const struct intel_crtc_state *crtc_state)
2136 {
2137         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2138         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2139         enum port port = encoder->port;
2140         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2141
2142         if (cpu_transcoder != TRANSCODER_EDP) {
2143                 if (INTEL_GEN(dev_priv) >= 12)
2144                         intel_de_write(dev_priv,
2145                                        TRANS_CLK_SEL(cpu_transcoder),
2146                                        TGL_TRANS_CLK_SEL_PORT(port));
2147                 else
2148                         intel_de_write(dev_priv,
2149                                        TRANS_CLK_SEL(cpu_transcoder),
2150                                        TRANS_CLK_SEL_PORT(port));
2151         }
2152 }
2153
2154 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
2155 {
2156         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2157         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2158
2159         if (cpu_transcoder != TRANSCODER_EDP) {
2160                 if (INTEL_GEN(dev_priv) >= 12)
2161                         intel_de_write(dev_priv,
2162                                        TRANS_CLK_SEL(cpu_transcoder),
2163                                        TGL_TRANS_CLK_SEL_DISABLED);
2164                 else
2165                         intel_de_write(dev_priv,
2166                                        TRANS_CLK_SEL(cpu_transcoder),
2167                                        TRANS_CLK_SEL_DISABLED);
2168         }
2169 }
2170
2171 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
2172                                 enum port port, u8 iboost)
2173 {
2174         u32 tmp;
2175
2176         tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0);
2177         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
2178         if (iboost)
2179                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
2180         else
2181                 tmp |= BALANCE_LEG_DISABLE(port);
2182         intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp);
2183 }
2184
2185 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
2186                                int level, enum intel_output_type type)
2187 {
2188         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2189         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2190         u8 iboost;
2191
2192         if (type == INTEL_OUTPUT_HDMI)
2193                 iboost = intel_bios_hdmi_boost_level(encoder);
2194         else
2195                 iboost = intel_bios_dp_boost_level(encoder);
2196
2197         if (iboost == 0) {
2198                 const struct ddi_buf_trans *ddi_translations;
2199                 int n_entries;
2200
2201                 if (type == INTEL_OUTPUT_HDMI)
2202                         ddi_translations = intel_ddi_get_buf_trans_hdmi(encoder, &n_entries);
2203                 else if (type == INTEL_OUTPUT_EDP)
2204                         ddi_translations = intel_ddi_get_buf_trans_edp(encoder,
2205                                                                        &n_entries);
2206                 else
2207                         ddi_translations = intel_ddi_get_buf_trans_dp(encoder,
2208                                                                       &n_entries);
2209
2210                 if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
2211                         return;
2212                 if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
2213                         level = n_entries - 1;
2214
2215                 iboost = ddi_translations[level].i_boost;
2216         }
2217
2218         /* Make sure that the requested I_boost is valid */
2219         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
2220                 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost);
2221                 return;
2222         }
2223
2224         _skl_ddi_set_iboost(dev_priv, encoder->port, iboost);
2225
2226         if (encoder->port == PORT_A && dig_port->max_lanes == 4)
2227                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
2228 }
2229
2230 static void bxt_ddi_vswing_sequence(struct intel_encoder *encoder,
2231                                     int level, enum intel_output_type type)
2232 {
2233         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2234         const struct bxt_ddi_buf_trans *ddi_translations;
2235         enum port port = encoder->port;
2236         int n_entries;
2237
2238         if (type == INTEL_OUTPUT_HDMI)
2239                 ddi_translations = bxt_get_buf_trans_hdmi(encoder, &n_entries);
2240         else if (type == INTEL_OUTPUT_EDP)
2241                 ddi_translations = bxt_get_buf_trans_edp(encoder, &n_entries);
2242         else
2243                 ddi_translations = bxt_get_buf_trans_dp(encoder, &n_entries);
2244
2245         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
2246                 return;
2247         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
2248                 level = n_entries - 1;
2249
2250         bxt_ddi_phy_set_signal_level(dev_priv, port,
2251                                      ddi_translations[level].margin,
2252                                      ddi_translations[level].scale,
2253                                      ddi_translations[level].enable,
2254                                      ddi_translations[level].deemphasis);
2255 }
2256
2257 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp)
2258 {
2259         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2260         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2261         enum port port = encoder->port;
2262         enum phy phy = intel_port_to_phy(dev_priv, port);
2263         int n_entries;
2264
2265         if (INTEL_GEN(dev_priv) >= 12) {
2266                 if (intel_phy_is_combo(dev_priv, phy))
2267                         tgl_get_combo_buf_trans(encoder, encoder->type,
2268                                                 intel_dp->link_rate, &n_entries);
2269                 else
2270                         tgl_get_dkl_buf_trans(encoder, encoder->type,
2271                                               intel_dp->link_rate, &n_entries);
2272         } else if (INTEL_GEN(dev_priv) == 11) {
2273                 if (IS_ELKHARTLAKE(dev_priv))
2274                         ehl_get_combo_buf_trans(encoder, encoder->type,
2275                                                 intel_dp->link_rate, &n_entries);
2276                 else if (intel_phy_is_combo(dev_priv, phy))
2277                         icl_get_combo_buf_trans(encoder, encoder->type,
2278                                                 intel_dp->link_rate, &n_entries);
2279                 else
2280                         icl_get_mg_buf_trans(encoder, encoder->type,
2281                                              intel_dp->link_rate, &n_entries);
2282         } else if (IS_CANNONLAKE(dev_priv)) {
2283                 if (encoder->type == INTEL_OUTPUT_EDP)
2284                         cnl_get_buf_trans_edp(encoder, &n_entries);
2285                 else
2286                         cnl_get_buf_trans_dp(encoder, &n_entries);
2287         } else if (IS_GEN9_LP(dev_priv)) {
2288                 if (encoder->type == INTEL_OUTPUT_EDP)
2289                         bxt_get_buf_trans_edp(encoder, &n_entries);
2290                 else
2291                         bxt_get_buf_trans_dp(encoder, &n_entries);
2292         } else {
2293                 if (encoder->type == INTEL_OUTPUT_EDP)
2294                         intel_ddi_get_buf_trans_edp(encoder, &n_entries);
2295                 else
2296                         intel_ddi_get_buf_trans_dp(encoder, &n_entries);
2297         }
2298
2299         if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
2300                 n_entries = 1;
2301         if (drm_WARN_ON(&dev_priv->drm,
2302                         n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
2303                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
2304
2305         return index_to_dp_signal_levels[n_entries - 1] &
2306                 DP_TRAIN_VOLTAGE_SWING_MASK;
2307 }
2308
2309 /*
2310  * We assume that the full set of pre-emphasis values can be
2311  * used on all DDI platforms. Should that change we need to
2312  * rethink this code.
2313  */
2314 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
2315 {
2316         return DP_TRAIN_PRE_EMPH_LEVEL_3;
2317 }
2318
2319 static void cnl_ddi_vswing_program(struct intel_encoder *encoder,
2320                                    int level, enum intel_output_type type)
2321 {
2322         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2323         const struct cnl_ddi_buf_trans *ddi_translations;
2324         enum port port = encoder->port;
2325         int n_entries, ln;
2326         u32 val;
2327
2328         if (type == INTEL_OUTPUT_HDMI)
2329                 ddi_translations = cnl_get_buf_trans_hdmi(encoder, &n_entries);
2330         else if (type == INTEL_OUTPUT_EDP)
2331                 ddi_translations = cnl_get_buf_trans_edp(encoder, &n_entries);
2332         else
2333                 ddi_translations = cnl_get_buf_trans_dp(encoder, &n_entries);
2334
2335         if (drm_WARN_ON_ONCE(&dev_priv->drm, !ddi_translations))
2336                 return;
2337         if (drm_WARN_ON_ONCE(&dev_priv->drm, level >= n_entries))
2338                 level = n_entries - 1;
2339
2340         /* Set PORT_TX_DW5 Scaling Mode Sel to 010b. */
2341         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2342         val &= ~SCALING_MODE_SEL_MASK;
2343         val |= SCALING_MODE_SEL(2);
2344         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2345
2346         /* Program PORT_TX_DW2 */
2347         val = intel_de_read(dev_priv, CNL_PORT_TX_DW2_LN0(port));
2348         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2349                  RCOMP_SCALAR_MASK);
2350         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2351         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2352         /* Rcomp scalar is fixed as 0x98 for every table entry */
2353         val |= RCOMP_SCALAR(0x98);
2354         intel_de_write(dev_priv, CNL_PORT_TX_DW2_GRP(port), val);
2355
2356         /* Program PORT_TX_DW4 */
2357         /* We cannot write to GRP. It would overrite individual loadgen */
2358         for (ln = 0; ln < 4; ln++) {
2359                 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
2360                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2361                          CURSOR_COEFF_MASK);
2362                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2363                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2364                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2365                 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
2366         }
2367
2368         /* Program PORT_TX_DW5 */
2369         /* All DW5 values are fixed for every table entry */
2370         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2371         val &= ~RTERM_SELECT_MASK;
2372         val |= RTERM_SELECT(6);
2373         val |= TAP3_DISABLE;
2374         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2375
2376         /* Program PORT_TX_DW7 */
2377         val = intel_de_read(dev_priv, CNL_PORT_TX_DW7_LN0(port));
2378         val &= ~N_SCALAR_MASK;
2379         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2380         intel_de_write(dev_priv, CNL_PORT_TX_DW7_GRP(port), val);
2381 }
2382
2383 static void cnl_ddi_vswing_sequence(struct intel_encoder *encoder,
2384                                     int level, enum intel_output_type type)
2385 {
2386         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2387         enum port port = encoder->port;
2388         int width, rate, ln;
2389         u32 val;
2390
2391         if (type == INTEL_OUTPUT_HDMI) {
2392                 width = 4;
2393                 rate = 0; /* Rate is always < than 6GHz for HDMI */
2394         } else {
2395                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2396
2397                 width = intel_dp->lane_count;
2398                 rate = intel_dp->link_rate;
2399         }
2400
2401         /*
2402          * 1. If port type is eDP or DP,
2403          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2404          * else clear to 0b.
2405          */
2406         val = intel_de_read(dev_priv, CNL_PORT_PCS_DW1_LN0(port));
2407         if (type != INTEL_OUTPUT_HDMI)
2408                 val |= COMMON_KEEPER_EN;
2409         else
2410                 val &= ~COMMON_KEEPER_EN;
2411         intel_de_write(dev_priv, CNL_PORT_PCS_DW1_GRP(port), val);
2412
2413         /* 2. Program loadgen select */
2414         /*
2415          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2416          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2417          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2418          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2419          */
2420         for (ln = 0; ln <= 3; ln++) {
2421                 val = intel_de_read(dev_priv, CNL_PORT_TX_DW4_LN(ln, port));
2422                 val &= ~LOADGEN_SELECT;
2423
2424                 if ((rate <= 600000 && width == 4 && ln >= 1)  ||
2425                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2426                         val |= LOADGEN_SELECT;
2427                 }
2428                 intel_de_write(dev_priv, CNL_PORT_TX_DW4_LN(ln, port), val);
2429         }
2430
2431         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2432         val = intel_de_read(dev_priv, CNL_PORT_CL1CM_DW5);
2433         val |= SUS_CLOCK_CONFIG;
2434         intel_de_write(dev_priv, CNL_PORT_CL1CM_DW5, val);
2435
2436         /* 4. Clear training enable to change swing values */
2437         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2438         val &= ~TX_TRAINING_EN;
2439         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2440
2441         /* 5. Program swing and de-emphasis */
2442         cnl_ddi_vswing_program(encoder, level, type);
2443
2444         /* 6. Set training enable to trigger update */
2445         val = intel_de_read(dev_priv, CNL_PORT_TX_DW5_LN0(port));
2446         val |= TX_TRAINING_EN;
2447         intel_de_write(dev_priv, CNL_PORT_TX_DW5_GRP(port), val);
2448 }
2449
2450 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
2451                                          u32 level, int type, int rate)
2452 {
2453         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2454         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2455         const struct cnl_ddi_buf_trans *ddi_translations = NULL;
2456         u32 n_entries, val;
2457         int ln;
2458
2459         if (INTEL_GEN(dev_priv) >= 12)
2460                 ddi_translations = tgl_get_combo_buf_trans(encoder, type, rate,
2461                                                            &n_entries);
2462         else if (IS_ELKHARTLAKE(dev_priv))
2463                 ddi_translations = ehl_get_combo_buf_trans(encoder, type, rate,
2464                                                            &n_entries);
2465         else
2466                 ddi_translations = icl_get_combo_buf_trans(encoder, type, rate,
2467                                                            &n_entries);
2468         if (!ddi_translations)
2469                 return;
2470
2471         if (level >= n_entries) {
2472                 drm_dbg_kms(&dev_priv->drm,
2473                             "DDI translation not found for level %d. Using %d instead.",
2474                             level, n_entries - 1);
2475                 level = n_entries - 1;
2476         }
2477
2478         if (type == INTEL_OUTPUT_EDP) {
2479                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2480
2481                 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
2482                 intel_dp->hobl_active = is_hobl_buf_trans(ddi_translations);
2483                 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val,
2484                              intel_dp->hobl_active ? val : 0);
2485         }
2486
2487         /* Set PORT_TX_DW5 */
2488         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2489         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
2490                   TAP2_DISABLE | TAP3_DISABLE);
2491         val |= SCALING_MODE_SEL(0x2);
2492         val |= RTERM_SELECT(0x6);
2493         val |= TAP3_DISABLE;
2494         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2495
2496         /* Program PORT_TX_DW2 */
2497         val = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN0(phy));
2498         val &= ~(SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
2499                  RCOMP_SCALAR_MASK);
2500         val |= SWING_SEL_UPPER(ddi_translations[level].dw2_swing_sel);
2501         val |= SWING_SEL_LOWER(ddi_translations[level].dw2_swing_sel);
2502         /* Program Rcomp scalar for every table entry */
2503         val |= RCOMP_SCALAR(0x98);
2504         intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), val);
2505
2506         /* Program PORT_TX_DW4 */
2507         /* We cannot write to GRP. It would overwrite individual loadgen. */
2508         for (ln = 0; ln <= 3; ln++) {
2509                 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
2510                 val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
2511                          CURSOR_COEFF_MASK);
2512                 val |= POST_CURSOR_1(ddi_translations[level].dw4_post_cursor_1);
2513                 val |= POST_CURSOR_2(ddi_translations[level].dw4_post_cursor_2);
2514                 val |= CURSOR_COEFF(ddi_translations[level].dw4_cursor_coeff);
2515                 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
2516         }
2517
2518         /* Program PORT_TX_DW7 */
2519         val = intel_de_read(dev_priv, ICL_PORT_TX_DW7_LN0(phy));
2520         val &= ~N_SCALAR_MASK;
2521         val |= N_SCALAR(ddi_translations[level].dw7_n_scalar);
2522         intel_de_write(dev_priv, ICL_PORT_TX_DW7_GRP(phy), val);
2523 }
2524
2525 static void icl_combo_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2526                                               u32 level,
2527                                               enum intel_output_type type)
2528 {
2529         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2530         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2531         int width = 0;
2532         int rate = 0;
2533         u32 val;
2534         int ln = 0;
2535
2536         if (type == INTEL_OUTPUT_HDMI) {
2537                 width = 4;
2538                 /* Rate is always < than 6GHz for HDMI */
2539         } else {
2540                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2541
2542                 width = intel_dp->lane_count;
2543                 rate = intel_dp->link_rate;
2544         }
2545
2546         /*
2547          * 1. If port type is eDP or DP,
2548          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
2549          * else clear to 0b.
2550          */
2551         val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN0(phy));
2552         if (type == INTEL_OUTPUT_HDMI)
2553                 val &= ~COMMON_KEEPER_EN;
2554         else
2555                 val |= COMMON_KEEPER_EN;
2556         intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
2557
2558         /* 2. Program loadgen select */
2559         /*
2560          * Program PORT_TX_DW4_LN depending on Bit rate and used lanes
2561          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
2562          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
2563          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
2564          */
2565         for (ln = 0; ln <= 3; ln++) {
2566                 val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
2567                 val &= ~LOADGEN_SELECT;
2568
2569                 if ((rate <= 600000 && width == 4 && ln >= 1) ||
2570                     (rate <= 600000 && width < 4 && (ln == 1 || ln == 2))) {
2571                         val |= LOADGEN_SELECT;
2572                 }
2573                 intel_de_write(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy), val);
2574         }
2575
2576         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
2577         val = intel_de_read(dev_priv, ICL_PORT_CL_DW5(phy));
2578         val |= SUS_CLOCK_CONFIG;
2579         intel_de_write(dev_priv, ICL_PORT_CL_DW5(phy), val);
2580
2581         /* 4. Clear training enable to change swing values */
2582         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2583         val &= ~TX_TRAINING_EN;
2584         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2585
2586         /* 5. Program swing and de-emphasis */
2587         icl_ddi_combo_vswing_program(encoder, level, type, rate);
2588
2589         /* 6. Set training enable to trigger update */
2590         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN0(phy));
2591         val |= TX_TRAINING_EN;
2592         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
2593 }
2594
2595 static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
2596                                            int link_clock, u32 level,
2597                                            enum intel_output_type type)
2598 {
2599         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2600         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2601         const struct icl_mg_phy_ddi_buf_trans *ddi_translations;
2602         u32 n_entries, val;
2603         int ln, rate = 0;
2604
2605         if (type != INTEL_OUTPUT_HDMI) {
2606                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2607
2608                 rate = intel_dp->link_rate;
2609         }
2610
2611         ddi_translations = icl_get_mg_buf_trans(encoder, type, rate,
2612                                                 &n_entries);
2613         /* The table does not have values for level 3 and level 9. */
2614         if (level >= n_entries || level == 3 || level == 9) {
2615                 drm_dbg_kms(&dev_priv->drm,
2616                             "DDI translation not found for level %d. Using %d instead.",
2617                             level, n_entries - 2);
2618                 level = n_entries - 2;
2619         }
2620
2621         /* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
2622         for (ln = 0; ln < 2; ln++) {
2623                 val = intel_de_read(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port));
2624                 val &= ~CRI_USE_FS32;
2625                 intel_de_write(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port), val);
2626
2627                 val = intel_de_read(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port));
2628                 val &= ~CRI_USE_FS32;
2629                 intel_de_write(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port), val);
2630         }
2631
2632         /* Program MG_TX_SWINGCTRL with values from vswing table */
2633         for (ln = 0; ln < 2; ln++) {
2634                 val = intel_de_read(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port));
2635                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2636                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2637                         ddi_translations[level].cri_txdeemph_override_17_12);
2638                 intel_de_write(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port), val);
2639
2640                 val = intel_de_read(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port));
2641                 val &= ~CRI_TXDEEMPH_OVERRIDE_17_12_MASK;
2642                 val |= CRI_TXDEEMPH_OVERRIDE_17_12(
2643                         ddi_translations[level].cri_txdeemph_override_17_12);
2644                 intel_de_write(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port), val);
2645         }
2646
2647         /* Program MG_TX_DRVCTRL with values from vswing table */
2648         for (ln = 0; ln < 2; ln++) {
2649                 val = intel_de_read(dev_priv, MG_TX1_DRVCTRL(ln, tc_port));
2650                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2651                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2652                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2653                         ddi_translations[level].cri_txdeemph_override_5_0) |
2654                         CRI_TXDEEMPH_OVERRIDE_11_6(
2655                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2656                         CRI_TXDEEMPH_OVERRIDE_EN;
2657                 intel_de_write(dev_priv, MG_TX1_DRVCTRL(ln, tc_port), val);
2658
2659                 val = intel_de_read(dev_priv, MG_TX2_DRVCTRL(ln, tc_port));
2660                 val &= ~(CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
2661                          CRI_TXDEEMPH_OVERRIDE_5_0_MASK);
2662                 val |= CRI_TXDEEMPH_OVERRIDE_5_0(
2663                         ddi_translations[level].cri_txdeemph_override_5_0) |
2664                         CRI_TXDEEMPH_OVERRIDE_11_6(
2665                                 ddi_translations[level].cri_txdeemph_override_11_6) |
2666                         CRI_TXDEEMPH_OVERRIDE_EN;
2667                 intel_de_write(dev_priv, MG_TX2_DRVCTRL(ln, tc_port), val);
2668
2669                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
2670         }
2671
2672         /*
2673          * Program MG_CLKHUB<LN, port being used> with value from frequency table
2674          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
2675          * values from table for which TX1 and TX2 enabled.
2676          */
2677         for (ln = 0; ln < 2; ln++) {
2678                 val = intel_de_read(dev_priv, MG_CLKHUB(ln, tc_port));
2679                 if (link_clock < 300000)
2680                         val |= CFG_LOW_RATE_LKREN_EN;
2681                 else
2682                         val &= ~CFG_LOW_RATE_LKREN_EN;
2683                 intel_de_write(dev_priv, MG_CLKHUB(ln, tc_port), val);
2684         }
2685
2686         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
2687         for (ln = 0; ln < 2; ln++) {
2688                 val = intel_de_read(dev_priv, MG_TX1_DCC(ln, tc_port));
2689                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2690                 if (link_clock <= 500000) {
2691                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2692                 } else {
2693                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2694                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2695                 }
2696                 intel_de_write(dev_priv, MG_TX1_DCC(ln, tc_port), val);
2697
2698                 val = intel_de_read(dev_priv, MG_TX2_DCC(ln, tc_port));
2699                 val &= ~CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK;
2700                 if (link_clock <= 500000) {
2701                         val &= ~CFG_AMI_CK_DIV_OVERRIDE_EN;
2702                 } else {
2703                         val |= CFG_AMI_CK_DIV_OVERRIDE_EN |
2704                                 CFG_AMI_CK_DIV_OVERRIDE_VAL(1);
2705                 }
2706                 intel_de_write(dev_priv, MG_TX2_DCC(ln, tc_port), val);
2707         }
2708
2709         /* Program MG_TX_PISO_READLOAD with values from vswing table */
2710         for (ln = 0; ln < 2; ln++) {
2711                 val = intel_de_read(dev_priv,
2712                                     MG_TX1_PISO_READLOAD(ln, tc_port));
2713                 val |= CRI_CALCINIT;
2714                 intel_de_write(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
2715                                val);
2716
2717                 val = intel_de_read(dev_priv,
2718                                     MG_TX2_PISO_READLOAD(ln, tc_port));
2719                 val |= CRI_CALCINIT;
2720                 intel_de_write(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
2721                                val);
2722         }
2723 }
2724
2725 static void icl_ddi_vswing_sequence(struct intel_encoder *encoder,
2726                                     int link_clock,
2727                                     u32 level,
2728                                     enum intel_output_type type)
2729 {
2730         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2731         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2732
2733         if (intel_phy_is_combo(dev_priv, phy))
2734                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2735         else
2736                 icl_mg_phy_ddi_vswing_sequence(encoder, link_clock, level,
2737                                                type);
2738 }
2739
2740 static void
2741 tgl_dkl_phy_ddi_vswing_sequence(struct intel_encoder *encoder, int link_clock,
2742                                 u32 level, enum intel_output_type type)
2743 {
2744         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2745         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
2746         const struct tgl_dkl_phy_ddi_buf_trans *ddi_translations;
2747         u32 n_entries, val, ln, dpcnt_mask, dpcnt_val;
2748         int rate = 0;
2749
2750         if (type == INTEL_OUTPUT_HDMI) {
2751                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2752
2753                 rate = intel_dp->link_rate;
2754         }
2755
2756         ddi_translations = tgl_get_dkl_buf_trans(encoder, encoder->type, rate,
2757                                                  &n_entries);
2758
2759         if (level >= n_entries)
2760                 level = n_entries - 1;
2761
2762         dpcnt_mask = (DKL_TX_PRESHOOT_COEFF_MASK |
2763                       DKL_TX_DE_EMPAHSIS_COEFF_MASK |
2764                       DKL_TX_VSWING_CONTROL_MASK);
2765         dpcnt_val = DKL_TX_VSWING_CONTROL(ddi_translations[level].dkl_vswing_control);
2766         dpcnt_val |= DKL_TX_DE_EMPHASIS_COEFF(ddi_translations[level].dkl_de_emphasis_control);
2767         dpcnt_val |= DKL_TX_PRESHOOT_COEFF(ddi_translations[level].dkl_preshoot_control);
2768
2769         for (ln = 0; ln < 2; ln++) {
2770                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2771                                HIP_INDEX_VAL(tc_port, ln));
2772
2773                 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0);
2774
2775                 /* All the registers are RMW */
2776                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL0(tc_port));
2777                 val &= ~dpcnt_mask;
2778                 val |= dpcnt_val;
2779                 intel_de_write(dev_priv, DKL_TX_DPCNTL0(tc_port), val);
2780
2781                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL1(tc_port));
2782                 val &= ~dpcnt_mask;
2783                 val |= dpcnt_val;
2784                 intel_de_write(dev_priv, DKL_TX_DPCNTL1(tc_port), val);
2785
2786                 val = intel_de_read(dev_priv, DKL_TX_DPCNTL2(tc_port));
2787                 val &= ~DKL_TX_DP20BITMODE;
2788                 intel_de_write(dev_priv, DKL_TX_DPCNTL2(tc_port), val);
2789         }
2790 }
2791
2792 static void tgl_ddi_vswing_sequence(struct intel_encoder *encoder,
2793                                     int link_clock,
2794                                     u32 level,
2795                                     enum intel_output_type type)
2796 {
2797         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2798         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2799
2800         if (intel_phy_is_combo(dev_priv, phy))
2801                 icl_combo_phy_ddi_vswing_sequence(encoder, level, type);
2802         else
2803                 tgl_dkl_phy_ddi_vswing_sequence(encoder, link_clock, level, type);
2804 }
2805
2806 static u32 translate_signal_level(struct intel_dp *intel_dp, int signal_levels)
2807 {
2808         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2809         int i;
2810
2811         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
2812                 if (index_to_dp_signal_levels[i] == signal_levels)
2813                         return i;
2814         }
2815
2816         drm_WARN(&i915->drm, 1,
2817                  "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
2818                  signal_levels);
2819
2820         return 0;
2821 }
2822
2823 static u32 intel_ddi_dp_level(struct intel_dp *intel_dp)
2824 {
2825         u8 train_set = intel_dp->train_set[0];
2826         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
2827                                          DP_TRAIN_PRE_EMPHASIS_MASK);
2828
2829         return translate_signal_level(intel_dp, signal_levels);
2830 }
2831
2832 static void
2833 tgl_set_signal_levels(struct intel_dp *intel_dp)
2834 {
2835         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2836         int level = intel_ddi_dp_level(intel_dp);
2837
2838         tgl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2839                                 level, encoder->type);
2840 }
2841
2842 static void
2843 icl_set_signal_levels(struct intel_dp *intel_dp)
2844 {
2845         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2846         int level = intel_ddi_dp_level(intel_dp);
2847
2848         icl_ddi_vswing_sequence(encoder, intel_dp->link_rate,
2849                                 level, encoder->type);
2850 }
2851
2852 static void
2853 cnl_set_signal_levels(struct intel_dp *intel_dp)
2854 {
2855         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2856         int level = intel_ddi_dp_level(intel_dp);
2857
2858         cnl_ddi_vswing_sequence(encoder, level, encoder->type);
2859 }
2860
2861 static void
2862 bxt_set_signal_levels(struct intel_dp *intel_dp)
2863 {
2864         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2865         int level = intel_ddi_dp_level(intel_dp);
2866
2867         bxt_ddi_vswing_sequence(encoder, level, encoder->type);
2868 }
2869
2870 static void
2871 hsw_set_signal_levels(struct intel_dp *intel_dp)
2872 {
2873         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
2874         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2875         int level = intel_ddi_dp_level(intel_dp);
2876         enum port port = encoder->port;
2877         u32 signal_levels;
2878
2879         signal_levels = DDI_BUF_TRANS_SELECT(level);
2880
2881         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
2882                     signal_levels);
2883
2884         intel_dp->DP &= ~DDI_BUF_EMP_MASK;
2885         intel_dp->DP |= signal_levels;
2886
2887         if (IS_GEN9_BC(dev_priv))
2888                 skl_ddi_set_iboost(encoder, level, encoder->type);
2889
2890         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
2891         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
2892 }
2893
2894 static u32 icl_dpclka_cfgcr0_clk_off(struct drm_i915_private *dev_priv,
2895                                      enum phy phy)
2896 {
2897         if (IS_ROCKETLAKE(dev_priv)) {
2898                 return RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
2899         } else if (intel_phy_is_combo(dev_priv, phy)) {
2900                 return ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
2901         } else if (intel_phy_is_tc(dev_priv, phy)) {
2902                 enum tc_port tc_port = intel_port_to_tc(dev_priv,
2903                                                         (enum port)phy);
2904
2905                 return ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port);
2906         }
2907
2908         return 0;
2909 }
2910
2911 static void icl_map_plls_to_ports(struct intel_encoder *encoder,
2912                                   const struct intel_crtc_state *crtc_state)
2913 {
2914         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2915         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
2916         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2917         u32 val;
2918
2919         mutex_lock(&dev_priv->dpll.lock);
2920
2921         val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
2922         drm_WARN_ON(&dev_priv->drm,
2923                     (val & icl_dpclka_cfgcr0_clk_off(dev_priv, phy)) == 0);
2924
2925         if (intel_phy_is_combo(dev_priv, phy)) {
2926                 u32 mask, sel;
2927
2928                 if (IS_ROCKETLAKE(dev_priv)) {
2929                         mask = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
2930                         sel = RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
2931                 } else {
2932                         mask = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
2933                         sel = ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
2934                 }
2935
2936                 /*
2937                  * Even though this register references DDIs, note that we
2938                  * want to pass the PHY rather than the port (DDI).  For
2939                  * ICL, port=phy in all cases so it doesn't matter, but for
2940                  * EHL the bspec notes the following:
2941                  *
2942                  *   "DDID clock tied to DDIA clock, so DPCLKA_CFGCR0 DDIA
2943                  *   Clock Select chooses the PLL for both DDIA and DDID and
2944                  *   drives port A in all cases."
2945                  */
2946                 val &= ~mask;
2947                 val |= sel;
2948                 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2949                 intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
2950         }
2951
2952         val &= ~icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2953         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2954
2955         mutex_unlock(&dev_priv->dpll.lock);
2956 }
2957
2958 static void icl_unmap_plls_to_ports(struct intel_encoder *encoder)
2959 {
2960         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2961         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2962         u32 val;
2963
2964         mutex_lock(&dev_priv->dpll.lock);
2965
2966         val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
2967         val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2968         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
2969
2970         mutex_unlock(&dev_priv->dpll.lock);
2971 }
2972
2973 static void icl_sanitize_port_clk_off(struct drm_i915_private *dev_priv,
2974                                       u32 port_mask, bool ddi_clk_needed)
2975 {
2976         enum port port;
2977         u32 val;
2978
2979         val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
2980         for_each_port_masked(port, port_mask) {
2981                 enum phy phy = intel_port_to_phy(dev_priv, port);
2982                 bool ddi_clk_off = val & icl_dpclka_cfgcr0_clk_off(dev_priv,
2983                                                                    phy);
2984
2985                 if (ddi_clk_needed == !ddi_clk_off)
2986                         continue;
2987
2988                 /*
2989                  * Punt on the case now where clock is gated, but it would
2990                  * be needed by the port. Something else is really broken then.
2991                  */
2992                 if (drm_WARN_ON(&dev_priv->drm, ddi_clk_needed))
2993                         continue;
2994
2995                 drm_notice(&dev_priv->drm,
2996                            "PHY %c is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2997                            phy_name(phy));
2998                 val |= icl_dpclka_cfgcr0_clk_off(dev_priv, phy);
2999                 intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
3000         }
3001 }
3002
3003 void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
3004 {
3005         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3006         u32 port_mask;
3007         bool ddi_clk_needed;
3008
3009         /*
3010          * In case of DP MST, we sanitize the primary encoder only, not the
3011          * virtual ones.
3012          */
3013         if (encoder->type == INTEL_OUTPUT_DP_MST)
3014                 return;
3015
3016         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
3017                 u8 pipe_mask;
3018                 bool is_mst;
3019
3020                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
3021                 /*
3022                  * In the unlikely case that BIOS enables DP in MST mode, just
3023                  * warn since our MST HW readout is incomplete.
3024                  */
3025                 if (drm_WARN_ON(&dev_priv->drm, is_mst))
3026                         return;
3027         }
3028
3029         port_mask = BIT(encoder->port);
3030         ddi_clk_needed = encoder->base.crtc;
3031
3032         if (encoder->type == INTEL_OUTPUT_DSI) {
3033                 struct intel_encoder *other_encoder;
3034
3035                 port_mask = intel_dsi_encoder_ports(encoder);
3036                 /*
3037                  * Sanity check that we haven't incorrectly registered another
3038                  * encoder using any of the ports of this DSI encoder.
3039                  */
3040                 for_each_intel_encoder(&dev_priv->drm, other_encoder) {
3041                         if (other_encoder == encoder)
3042                                 continue;
3043
3044                         if (drm_WARN_ON(&dev_priv->drm,
3045                                         port_mask & BIT(other_encoder->port)))
3046                                 return;
3047                 }
3048                 /*
3049                  * For DSI we keep the ddi clocks gated
3050                  * except during enable/disable sequence.
3051                  */
3052                 ddi_clk_needed = false;
3053         }
3054
3055         icl_sanitize_port_clk_off(dev_priv, port_mask, ddi_clk_needed);
3056 }
3057
3058 static void intel_ddi_clk_select(struct intel_encoder *encoder,
3059                                  const struct intel_crtc_state *crtc_state)
3060 {
3061         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3062         enum port port = encoder->port;
3063         enum phy phy = intel_port_to_phy(dev_priv, port);
3064         u32 val;
3065         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
3066
3067         if (drm_WARN_ON(&dev_priv->drm, !pll))
3068                 return;
3069
3070         mutex_lock(&dev_priv->dpll.lock);
3071
3072         if (INTEL_GEN(dev_priv) >= 11) {
3073                 if (!intel_phy_is_combo(dev_priv, phy))
3074                         intel_de_write(dev_priv, DDI_CLK_SEL(port),
3075                                        icl_pll_to_ddi_clk_sel(encoder, crtc_state));
3076                 else if (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C)
3077                         /*
3078                          * MG does not exist but the programming is required
3079                          * to ungate DDIC and DDID
3080                          */
3081                         intel_de_write(dev_priv, DDI_CLK_SEL(port),
3082                                        DDI_CLK_SEL_MG);
3083         } else if (IS_CANNONLAKE(dev_priv)) {
3084                 /* Configure DPCLKA_CFGCR0 to map the DPLL to the DDI. */
3085                 val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
3086                 val &= ~DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port);
3087                 val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
3088                 intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
3089
3090                 /*
3091                  * Configure DPCLKA_CFGCR0 to turn on the clock for the DDI.
3092                  * This step and the step before must be done with separate
3093                  * register writes.
3094                  */
3095                 val = intel_de_read(dev_priv, DPCLKA_CFGCR0);
3096                 val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
3097                 intel_de_write(dev_priv, DPCLKA_CFGCR0, val);
3098         } else if (IS_GEN9_BC(dev_priv)) {
3099                 /* DDI -> PLL mapping  */
3100                 val = intel_de_read(dev_priv, DPLL_CTRL2);
3101
3102                 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
3103                          DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
3104                 val |= (DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
3105                         DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
3106
3107                 intel_de_write(dev_priv, DPLL_CTRL2, val);
3108
3109         } else if (INTEL_GEN(dev_priv) < 9) {
3110                 intel_de_write(dev_priv, PORT_CLK_SEL(port),
3111                                hsw_pll_to_ddi_pll_sel(pll));
3112         }
3113
3114         mutex_unlock(&dev_priv->dpll.lock);
3115 }
3116
3117 static void intel_ddi_clk_disable(struct intel_encoder *encoder)
3118 {
3119         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3120         enum port port = encoder->port;
3121         enum phy phy = intel_port_to_phy(dev_priv, port);
3122
3123         if (INTEL_GEN(dev_priv) >= 11) {
3124                 if (!intel_phy_is_combo(dev_priv, phy) ||
3125                     (IS_ELKHARTLAKE(dev_priv) && port >= PORT_C))
3126                         intel_de_write(dev_priv, DDI_CLK_SEL(port),
3127                                        DDI_CLK_SEL_NONE);
3128         } else if (IS_CANNONLAKE(dev_priv)) {
3129                 intel_de_write(dev_priv, DPCLKA_CFGCR0,
3130                                intel_de_read(dev_priv, DPCLKA_CFGCR0) | DPCLKA_CFGCR0_DDI_CLK_OFF(port));
3131         } else if (IS_GEN9_BC(dev_priv)) {
3132                 intel_de_write(dev_priv, DPLL_CTRL2,
3133                                intel_de_read(dev_priv, DPLL_CTRL2) | DPLL_CTRL2_DDI_CLK_OFF(port));
3134         } else if (INTEL_GEN(dev_priv) < 9) {
3135                 intel_de_write(dev_priv, PORT_CLK_SEL(port),
3136                                PORT_CLK_SEL_NONE);
3137         }
3138 }
3139
3140 static void
3141 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
3142                        const struct intel_crtc_state *crtc_state)
3143 {
3144         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3145         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
3146         u32 ln0, ln1, pin_assignment;
3147         u8 width;
3148
3149         if (dig_port->tc_mode == TC_PORT_TBT_ALT)
3150                 return;
3151
3152         if (INTEL_GEN(dev_priv) >= 12) {
3153                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3154                                HIP_INDEX_VAL(tc_port, 0x0));
3155                 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
3156                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3157                                HIP_INDEX_VAL(tc_port, 0x1));
3158                 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
3159         } else {
3160                 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
3161                 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
3162         }
3163
3164         ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3165         ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
3166
3167         /* DPPATC */
3168         pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port);
3169         width = crtc_state->lane_count;
3170
3171         switch (pin_assignment) {
3172         case 0x0:
3173                 drm_WARN_ON(&dev_priv->drm,
3174                             dig_port->tc_mode != TC_PORT_LEGACY);
3175                 if (width == 1) {
3176                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3177                 } else {
3178                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3179                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3180                 }
3181                 break;
3182         case 0x1:
3183                 if (width == 4) {
3184                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3185                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3186                 }
3187                 break;
3188         case 0x2:
3189                 if (width == 2) {
3190                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3191                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3192                 }
3193                 break;
3194         case 0x3:
3195         case 0x5:
3196                 if (width == 1) {
3197                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3198                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3199                 } else {
3200                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3201                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3202                 }
3203                 break;
3204         case 0x4:
3205         case 0x6:
3206                 if (width == 1) {
3207                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
3208                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
3209                 } else {
3210                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
3211                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
3212                 }
3213                 break;
3214         default:
3215                 MISSING_CASE(pin_assignment);
3216         }
3217
3218         if (INTEL_GEN(dev_priv) >= 12) {
3219                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3220                                HIP_INDEX_VAL(tc_port, 0x0));
3221                 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0);
3222                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
3223                                HIP_INDEX_VAL(tc_port, 0x1));
3224                 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1);
3225         } else {
3226                 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
3227                 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
3228         }
3229 }
3230
3231 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
3232                                         const struct intel_crtc_state *crtc_state)
3233 {
3234         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
3235
3236         if (!crtc_state->fec_enable)
3237                 return;
3238
3239         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
3240                 drm_dbg_kms(&i915->drm,
3241                             "Failed to set FEC_READY in the sink\n");
3242 }
3243
3244 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
3245                                  const struct intel_crtc_state *crtc_state)
3246 {
3247         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3248         struct intel_dp *intel_dp;
3249         u32 val;
3250
3251         if (!crtc_state->fec_enable)
3252                 return;
3253
3254         intel_dp = enc_to_intel_dp(encoder);
3255         val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3256         val |= DP_TP_CTL_FEC_ENABLE;
3257         intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
3258
3259         if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
3260                                   DP_TP_STATUS_FEC_ENABLE_LIVE, 1))
3261                 drm_err(&dev_priv->drm,
3262                         "Timed out waiting for FEC Enable Status\n");
3263 }
3264
3265 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
3266                                         const struct intel_crtc_state *crtc_state)
3267 {
3268         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3269         struct intel_dp *intel_dp;
3270         u32 val;
3271
3272         if (!crtc_state->fec_enable)
3273                 return;
3274
3275         intel_dp = enc_to_intel_dp(encoder);
3276         val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3277         val &= ~DP_TP_CTL_FEC_ENABLE;
3278         intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
3279         intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3280 }
3281
3282 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
3283                                   struct intel_encoder *encoder,
3284                                   const struct intel_crtc_state *crtc_state,
3285                                   const struct drm_connector_state *conn_state)
3286 {
3287         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3288         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3289         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3290         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3291         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3292         int level = intel_ddi_dp_level(intel_dp);
3293         enum transcoder transcoder = crtc_state->cpu_transcoder;
3294
3295         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3296                                  crtc_state->lane_count, is_mst);
3297
3298         intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
3299         intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
3300
3301         /*
3302          * 1. Enable Power Wells
3303          *
3304          * This was handled at the beginning of intel_atomic_commit_tail(),
3305          * before we called down into this function.
3306          */
3307
3308         /* 2. Enable Panel Power if PPS is required */
3309         intel_edp_panel_on(intel_dp);
3310
3311         /*
3312          * 3. For non-TBT Type-C ports, set FIA lane count
3313          * (DFLEXDPSP.DPX4TXLATC)
3314          *
3315          * This was done before tgl_ddi_pre_enable_dp by
3316          * hsw_crtc_enable()->intel_encoders_pre_pll_enable().
3317          */
3318
3319         /*
3320          * 4. Enable the port PLL.
3321          *
3322          * The PLL enabling itself was already done before this function by
3323          * hsw_crtc_enable()->intel_enable_shared_dpll().  We need only
3324          * configure the PLL to port mapping here.
3325          */
3326         intel_ddi_clk_select(encoder, crtc_state);
3327
3328         /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
3329         if (!intel_phy_is_tc(dev_priv, phy) ||
3330             dig_port->tc_mode != TC_PORT_TBT_ALT)
3331                 intel_display_power_get(dev_priv,
3332                                         dig_port->ddi_io_power_domain);
3333
3334         /* 6. Program DP_MODE */
3335         icl_program_mg_dp_mode(dig_port, crtc_state);
3336
3337         /*
3338          * 7. The rest of the below are substeps under the bspec's "Enable and
3339          * Train Display Port" step.  Note that steps that are specific to
3340          * MST will be handled by intel_mst_pre_enable_dp() before/after it
3341          * calls into this function.  Also intel_mst_pre_enable_dp() only calls
3342          * us when active_mst_links==0, so any steps designated for "single
3343          * stream or multi-stream master transcoder" can just be performed
3344          * unconditionally here.
3345          */
3346
3347         /*
3348          * 7.a Configure Transcoder Clock Select to direct the Port clock to the
3349          * Transcoder.
3350          */
3351         intel_ddi_enable_pipe_clock(encoder, crtc_state);
3352
3353         /*
3354          * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
3355          * Transport Select
3356          */
3357         intel_ddi_config_transcoder_func(encoder, crtc_state);
3358
3359         /*
3360          * 7.c Configure & enable DP_TP_CTL with link training pattern 1
3361          * selected
3362          *
3363          * This will be handled by the intel_dp_start_link_train() farther
3364          * down this function.
3365          */
3366
3367         /* 7.e Configure voltage swing and related IO settings */
3368         tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock, level,
3369                                 encoder->type);
3370
3371         /*
3372          * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
3373          * the used lanes of the DDI.
3374          */
3375         if (intel_phy_is_combo(dev_priv, phy)) {
3376                 bool lane_reversal =
3377                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3378
3379                 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3380                                                crtc_state->lane_count,
3381                                                lane_reversal);
3382         }
3383
3384         /*
3385          * 7.g Configure and enable DDI_BUF_CTL
3386          * 7.h Wait for DDI_BUF_CTL DDI Idle Status = 0b (Not Idle), timeout
3387          *     after 500 us.
3388          *
3389          * We only configure what the register value will be here.  Actual
3390          * enabling happens during link training farther down.
3391          */
3392         intel_ddi_init_dp_buf_reg(encoder);
3393
3394         if (!is_mst)
3395                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3396
3397         intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
3398         /*
3399          * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
3400          * in the FEC_CONFIGURATION register to 1 before initiating link
3401          * training
3402          */
3403         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3404
3405         /*
3406          * 7.i Follow DisplayPort specification training sequence (see notes for
3407          *     failure handling)
3408          * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
3409          *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
3410          *     (timeout after 800 us)
3411          */
3412         intel_dp_start_link_train(intel_dp);
3413
3414         /* 7.k Set DP_TP_CTL link training to Normal */
3415         if (!is_trans_port_sync_mode(crtc_state))
3416                 intel_dp_stop_link_train(intel_dp);
3417
3418         /* 7.l Configure and enable FEC if needed */
3419         intel_ddi_enable_fec(encoder, crtc_state);
3420         intel_dsc_enable(encoder, crtc_state);
3421 }
3422
3423 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
3424                                   struct intel_encoder *encoder,
3425                                   const struct intel_crtc_state *crtc_state,
3426                                   const struct drm_connector_state *conn_state)
3427 {
3428         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3429         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3430         enum port port = encoder->port;
3431         enum phy phy = intel_port_to_phy(dev_priv, port);
3432         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3433         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
3434         int level = intel_ddi_dp_level(intel_dp);
3435
3436         if (INTEL_GEN(dev_priv) < 11)
3437                 drm_WARN_ON(&dev_priv->drm,
3438                             is_mst && (port == PORT_A || port == PORT_E));
3439         else
3440                 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
3441
3442         intel_dp_set_link_params(intel_dp, crtc_state->port_clock,
3443                                  crtc_state->lane_count, is_mst);
3444
3445         intel_edp_panel_on(intel_dp);
3446
3447         intel_ddi_clk_select(encoder, crtc_state);
3448
3449         if (!intel_phy_is_tc(dev_priv, phy) ||
3450             dig_port->tc_mode != TC_PORT_TBT_ALT)
3451                 intel_display_power_get(dev_priv,
3452                                         dig_port->ddi_io_power_domain);
3453
3454         icl_program_mg_dp_mode(dig_port, crtc_state);
3455
3456         if (INTEL_GEN(dev_priv) >= 11)
3457                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3458                                         level, encoder->type);
3459         else if (IS_CANNONLAKE(dev_priv))
3460                 cnl_ddi_vswing_sequence(encoder, level, encoder->type);
3461         else if (IS_GEN9_LP(dev_priv))
3462                 bxt_ddi_vswing_sequence(encoder, level, encoder->type);
3463         else
3464                 intel_prepare_dp_ddi_buffers(encoder, crtc_state);
3465
3466         if (intel_phy_is_combo(dev_priv, phy)) {
3467                 bool lane_reversal =
3468                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
3469
3470                 intel_combo_phy_power_up_lanes(dev_priv, phy, false,
3471                                                crtc_state->lane_count,
3472                                                lane_reversal);
3473         }
3474
3475         intel_ddi_init_dp_buf_reg(encoder);
3476         if (!is_mst)
3477                 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
3478         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
3479                                               true);
3480         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
3481         intel_dp_start_link_train(intel_dp);
3482         if ((port != PORT_A || INTEL_GEN(dev_priv) >= 9) &&
3483             !is_trans_port_sync_mode(crtc_state))
3484                 intel_dp_stop_link_train(intel_dp);
3485
3486         intel_ddi_enable_fec(encoder, crtc_state);
3487
3488         if (!is_mst)
3489                 intel_ddi_enable_pipe_clock(encoder, crtc_state);
3490
3491         intel_dsc_enable(encoder, crtc_state);
3492 }
3493
3494 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
3495                                     struct intel_encoder *encoder,
3496                                     const struct intel_crtc_state *crtc_state,
3497                                     const struct drm_connector_state *conn_state)
3498 {
3499         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3500
3501         if (INTEL_GEN(dev_priv) >= 12)
3502                 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
3503         else
3504                 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
3505
3506         /* MST will call a setting of MSA after an allocating of Virtual Channel
3507          * from MST encoder pre_enable callback.
3508          */
3509         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3510                 intel_ddi_set_dp_msa(crtc_state, conn_state);
3511
3512                 intel_dp_set_m_n(crtc_state, M1_N1);
3513         }
3514 }
3515
3516 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
3517                                       struct intel_encoder *encoder,
3518                                       const struct intel_crtc_state *crtc_state,
3519                                       const struct drm_connector_state *conn_state)
3520 {
3521         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3522         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3523         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3524         int level = intel_ddi_hdmi_level(encoder);
3525
3526         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
3527         intel_ddi_clk_select(encoder, crtc_state);
3528
3529         intel_display_power_get(dev_priv, dig_port->ddi_io_power_domain);
3530
3531         icl_program_mg_dp_mode(dig_port, crtc_state);
3532
3533         if (INTEL_GEN(dev_priv) >= 12)
3534                 tgl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3535                                         level, INTEL_OUTPUT_HDMI);
3536         else if (INTEL_GEN(dev_priv) == 11)
3537                 icl_ddi_vswing_sequence(encoder, crtc_state->port_clock,
3538                                         level, INTEL_OUTPUT_HDMI);
3539         else if (IS_CANNONLAKE(dev_priv))
3540                 cnl_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3541         else if (IS_GEN9_LP(dev_priv))
3542                 bxt_ddi_vswing_sequence(encoder, level, INTEL_OUTPUT_HDMI);
3543         else
3544                 intel_prepare_hdmi_ddi_buffers(encoder, level);
3545
3546         if (IS_GEN9_BC(dev_priv))
3547                 skl_ddi_set_iboost(encoder, level, INTEL_OUTPUT_HDMI);
3548
3549         intel_ddi_enable_pipe_clock(encoder, crtc_state);
3550
3551         dig_port->set_infoframes(encoder,
3552                                  crtc_state->has_infoframe,
3553                                  crtc_state, conn_state);
3554 }
3555
3556 static void intel_ddi_pre_enable(struct intel_atomic_state *state,
3557                                  struct intel_encoder *encoder,
3558                                  const struct intel_crtc_state *crtc_state,
3559                                  const struct drm_connector_state *conn_state)
3560 {
3561         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3562         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3563         enum pipe pipe = crtc->pipe;
3564
3565         /*
3566          * When called from DP MST code:
3567          * - conn_state will be NULL
3568          * - encoder will be the main encoder (ie. mst->primary)
3569          * - the main connector associated with this port
3570          *   won't be active or linked to a crtc
3571          * - crtc_state will be the state of the first stream to
3572          *   be activated on this port, and it may not be the same
3573          *   stream that will be deactivated last, but each stream
3574          *   should have a state that is identical when it comes to
3575          *   the DP link parameteres
3576          */
3577
3578         drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
3579
3580         if (INTEL_GEN(dev_priv) >= 11)
3581                 icl_map_plls_to_ports(encoder, crtc_state);
3582
3583         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
3584
3585         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
3586                 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
3587                                           conn_state);
3588         } else {
3589                 struct intel_lspcon *lspcon =
3590                                 enc_to_intel_lspcon(encoder);
3591
3592                 intel_ddi_pre_enable_dp(state, encoder, crtc_state,
3593                                         conn_state);
3594                 if (lspcon->active) {
3595                         struct intel_digital_port *dig_port =
3596                                         enc_to_dig_port(encoder);
3597
3598                         dig_port->set_infoframes(encoder,
3599                                                  crtc_state->has_infoframe,
3600                                                  crtc_state, conn_state);
3601                 }
3602         }
3603 }
3604
3605 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
3606                                   const struct intel_crtc_state *crtc_state)
3607 {
3608         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3609         enum port port = encoder->port;
3610         bool wait = false;
3611         u32 val;
3612
3613         val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
3614         if (val & DDI_BUF_CTL_ENABLE) {
3615                 val &= ~DDI_BUF_CTL_ENABLE;
3616                 intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
3617                 wait = true;
3618         }
3619
3620         if (intel_crtc_has_dp_encoder(crtc_state)) {
3621                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3622
3623                 val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
3624                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3625                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
3626                 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
3627         }
3628
3629         /* Disable FEC in DP Sink */
3630         intel_ddi_disable_fec_state(encoder, crtc_state);
3631
3632         if (wait)
3633                 intel_wait_ddi_buf_idle(dev_priv, port);
3634 }
3635
3636 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
3637                                       struct intel_encoder *encoder,
3638                                       const struct intel_crtc_state *old_crtc_state,
3639                                       const struct drm_connector_state *old_conn_state)
3640 {
3641         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3642         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3643         struct intel_dp *intel_dp = &dig_port->dp;
3644         bool is_mst = intel_crtc_has_type(old_crtc_state,
3645                                           INTEL_OUTPUT_DP_MST);
3646         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3647
3648         if (!is_mst)
3649                 intel_dp_set_infoframes(encoder, false,
3650                                         old_crtc_state, old_conn_state);
3651
3652         /*
3653          * Power down sink before disabling the port, otherwise we end
3654          * up getting interrupts from the sink on detecting link loss.
3655          */
3656         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
3657
3658         if (INTEL_GEN(dev_priv) >= 12) {
3659                 if (is_mst) {
3660                         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
3661                         u32 val;
3662
3663                         val = intel_de_read(dev_priv,
3664                                             TRANS_DDI_FUNC_CTL(cpu_transcoder));
3665                         val &= ~(TGL_TRANS_DDI_PORT_MASK |
3666                                  TRANS_DDI_MODE_SELECT_MASK);
3667                         intel_de_write(dev_priv,
3668                                        TRANS_DDI_FUNC_CTL(cpu_transcoder),
3669                                        val);
3670                 }
3671         } else {
3672                 if (!is_mst)
3673                         intel_ddi_disable_pipe_clock(old_crtc_state);
3674         }
3675
3676         intel_disable_ddi_buf(encoder, old_crtc_state);
3677
3678         /*
3679          * From TGL spec: "If single stream or multi-stream master transcoder:
3680          * Configure Transcoder Clock select to direct no clock to the
3681          * transcoder"
3682          */
3683         if (INTEL_GEN(dev_priv) >= 12)
3684                 intel_ddi_disable_pipe_clock(old_crtc_state);
3685
3686         intel_edp_panel_vdd_on(intel_dp);
3687         intel_edp_panel_off(intel_dp);
3688
3689         if (!intel_phy_is_tc(dev_priv, phy) ||
3690             dig_port->tc_mode != TC_PORT_TBT_ALT)
3691                 intel_display_power_put_unchecked(dev_priv,
3692                                                   dig_port->ddi_io_power_domain);
3693
3694         intel_ddi_clk_disable(encoder);
3695 }
3696
3697 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
3698                                         struct intel_encoder *encoder,
3699                                         const struct intel_crtc_state *old_crtc_state,
3700                                         const struct drm_connector_state *old_conn_state)
3701 {
3702         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3703         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3704         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
3705
3706         dig_port->set_infoframes(encoder, false,
3707                                  old_crtc_state, old_conn_state);
3708
3709         intel_ddi_disable_pipe_clock(old_crtc_state);
3710
3711         intel_disable_ddi_buf(encoder, old_crtc_state);
3712
3713         intel_display_power_put_unchecked(dev_priv,
3714                                           dig_port->ddi_io_power_domain);
3715
3716         intel_ddi_clk_disable(encoder);
3717
3718         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
3719 }
3720
3721 static void intel_ddi_post_disable(struct intel_atomic_state *state,
3722                                    struct intel_encoder *encoder,
3723                                    const struct intel_crtc_state *old_crtc_state,
3724                                    const struct drm_connector_state *old_conn_state)
3725 {
3726         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3727         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3728         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3729         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3730
3731         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
3732                 intel_crtc_vblank_off(old_crtc_state);
3733
3734                 intel_disable_pipe(old_crtc_state);
3735
3736                 intel_ddi_disable_transcoder_func(old_crtc_state);
3737
3738                 intel_dsc_disable(old_crtc_state);
3739
3740                 if (INTEL_GEN(dev_priv) >= 9)
3741                         skl_scaler_disable(old_crtc_state);
3742                 else
3743                         ilk_pfit_disable(old_crtc_state);
3744         }
3745
3746         /*
3747          * When called from DP MST code:
3748          * - old_conn_state will be NULL
3749          * - encoder will be the main encoder (ie. mst->primary)
3750          * - the main connector associated with this port
3751          *   won't be active or linked to a crtc
3752          * - old_crtc_state will be the state of the last stream to
3753          *   be deactivated on this port, and it may not be the same
3754          *   stream that was activated last, but each stream
3755          *   should have a state that is identical when it comes to
3756          *   the DP link parameteres
3757          */
3758
3759         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3760                 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state,
3761                                             old_conn_state);
3762         else
3763                 intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
3764                                           old_conn_state);
3765
3766         if (INTEL_GEN(dev_priv) >= 11)
3767                 icl_unmap_plls_to_ports(encoder);
3768
3769         if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
3770                 intel_display_power_put_unchecked(dev_priv,
3771                                                   intel_ddi_main_link_aux_domain(dig_port));
3772
3773         if (is_tc_port)
3774                 intel_tc_port_put_link(dig_port);
3775 }
3776
3777 void intel_ddi_fdi_post_disable(struct intel_atomic_state *state,
3778                                 struct intel_encoder *encoder,
3779                                 const struct intel_crtc_state *old_crtc_state,
3780                                 const struct drm_connector_state *old_conn_state)
3781 {
3782         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3783         u32 val;
3784
3785         /*
3786          * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
3787          * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
3788          * step 13 is the correct place for it. Step 18 is where it was
3789          * originally before the BUN.
3790          */
3791         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
3792         val &= ~FDI_RX_ENABLE;
3793         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
3794
3795         intel_disable_ddi_buf(encoder, old_crtc_state);
3796         intel_ddi_clk_disable(encoder);
3797
3798         val = intel_de_read(dev_priv, FDI_RX_MISC(PIPE_A));
3799         val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
3800         val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
3801         intel_de_write(dev_priv, FDI_RX_MISC(PIPE_A), val);
3802
3803         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
3804         val &= ~FDI_PCDCLK;
3805         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
3806
3807         val = intel_de_read(dev_priv, FDI_RX_CTL(PIPE_A));
3808         val &= ~FDI_RX_PLL_ENABLE;
3809         intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), val);
3810 }
3811
3812 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
3813                                             struct intel_encoder *encoder,
3814                                             const struct intel_crtc_state *crtc_state)
3815 {
3816         const struct drm_connector_state *conn_state;
3817         struct drm_connector *conn;
3818         int i;
3819
3820         if (!crtc_state->sync_mode_slaves_mask)
3821                 return;
3822
3823         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
3824                 struct intel_encoder *slave_encoder =
3825                         to_intel_encoder(conn_state->best_encoder);
3826                 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);
3827                 const struct intel_crtc_state *slave_crtc_state;
3828
3829                 if (!slave_crtc)
3830                         continue;
3831
3832                 slave_crtc_state =
3833                         intel_atomic_get_new_crtc_state(state, slave_crtc);
3834
3835                 if (slave_crtc_state->master_transcoder !=
3836                     crtc_state->cpu_transcoder)
3837                         continue;
3838
3839                 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder));
3840         }
3841
3842         usleep_range(200, 400);
3843
3844         intel_dp_stop_link_train(enc_to_intel_dp(encoder));
3845 }
3846
3847 static void intel_enable_ddi_dp(struct intel_atomic_state *state,
3848                                 struct intel_encoder *encoder,
3849                                 const struct intel_crtc_state *crtc_state,
3850                                 const struct drm_connector_state *conn_state)
3851 {
3852         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3853         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3854         enum port port = encoder->port;
3855
3856         if (port == PORT_A && INTEL_GEN(dev_priv) < 9)
3857                 intel_dp_stop_link_train(intel_dp);
3858
3859         intel_edp_backlight_on(crtc_state, conn_state);
3860         intel_psr_enable(intel_dp, crtc_state, conn_state);
3861         intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
3862         intel_edp_drrs_enable(intel_dp, crtc_state);
3863
3864         if (crtc_state->has_audio)
3865                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3866
3867         trans_port_sync_stop_link_train(state, encoder, crtc_state);
3868 }
3869
3870 static i915_reg_t
3871 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
3872                                enum port port)
3873 {
3874         static const enum transcoder trans[] = {
3875                 [PORT_A] = TRANSCODER_EDP,
3876                 [PORT_B] = TRANSCODER_A,
3877                 [PORT_C] = TRANSCODER_B,
3878                 [PORT_D] = TRANSCODER_C,
3879                 [PORT_E] = TRANSCODER_A,
3880         };
3881
3882         drm_WARN_ON(&dev_priv->drm, INTEL_GEN(dev_priv) < 9);
3883
3884         if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E))
3885                 port = PORT_A;
3886
3887         return CHICKEN_TRANS(trans[port]);
3888 }
3889
3890 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
3891                                   struct intel_encoder *encoder,
3892                                   const struct intel_crtc_state *crtc_state,
3893                                   const struct drm_connector_state *conn_state)
3894 {
3895         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3896         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3897         struct drm_connector *connector = conn_state->connector;
3898         enum port port = encoder->port;
3899
3900         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
3901                                                crtc_state->hdmi_high_tmds_clock_ratio,
3902                                                crtc_state->hdmi_scrambling))
3903                 drm_dbg_kms(&dev_priv->drm,
3904                             "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
3905                             connector->base.id, connector->name);
3906
3907         /* Display WA #1143: skl,kbl,cfl */
3908         if (IS_GEN9_BC(dev_priv)) {
3909                 /*
3910                  * For some reason these chicken bits have been
3911                  * stuffed into a transcoder register, event though
3912                  * the bits affect a specific DDI port rather than
3913                  * a specific transcoder.
3914                  */
3915                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
3916                 u32 val;
3917
3918                 val = intel_de_read(dev_priv, reg);
3919
3920                 if (port == PORT_E)
3921                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
3922                                 DDIE_TRAINING_OVERRIDE_VALUE;
3923                 else
3924                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
3925                                 DDI_TRAINING_OVERRIDE_VALUE;
3926
3927                 intel_de_write(dev_priv, reg, val);
3928                 intel_de_posting_read(dev_priv, reg);
3929
3930                 udelay(1);
3931
3932                 if (port == PORT_E)
3933                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
3934                                  DDIE_TRAINING_OVERRIDE_VALUE);
3935                 else
3936                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
3937                                  DDI_TRAINING_OVERRIDE_VALUE);
3938
3939                 intel_de_write(dev_priv, reg, val);
3940         }
3941
3942         /* In HDMI/DVI mode, the port width, and swing/emphasis values
3943          * are ignored so nothing special needs to be done besides
3944          * enabling the port.
3945          */
3946         intel_de_write(dev_priv, DDI_BUF_CTL(port),
3947                        dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
3948
3949         if (crtc_state->has_audio)
3950                 intel_audio_codec_enable(encoder, crtc_state, conn_state);
3951 }
3952
3953 static void intel_enable_ddi(struct intel_atomic_state *state,
3954                              struct intel_encoder *encoder,
3955                              const struct intel_crtc_state *crtc_state,
3956                              const struct drm_connector_state *conn_state)
3957 {
3958         drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
3959
3960         intel_ddi_enable_transcoder_func(encoder, crtc_state);
3961
3962         intel_enable_pipe(crtc_state);
3963
3964         intel_crtc_vblank_on(crtc_state);
3965
3966         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
3967                 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state);
3968         else
3969                 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state);
3970
3971         /* Enable hdcp if it's desired */
3972         if (conn_state->content_protection ==
3973             DRM_MODE_CONTENT_PROTECTION_DESIRED)
3974                 intel_hdcp_enable(to_intel_connector(conn_state->connector),
3975                                   crtc_state->cpu_transcoder,
3976                                   (u8)conn_state->hdcp_content_type);
3977 }
3978
3979 static void intel_disable_ddi_dp(struct intel_atomic_state *state,
3980                                  struct intel_encoder *encoder,
3981                                  const struct intel_crtc_state *old_crtc_state,
3982                                  const struct drm_connector_state *old_conn_state)
3983 {
3984         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
3985
3986         intel_dp->link_trained = false;
3987
3988         if (old_crtc_state->has_audio)
3989                 intel_audio_codec_disable(encoder,
3990                                           old_crtc_state, old_conn_state);
3991
3992         intel_edp_drrs_disable(intel_dp, old_crtc_state);
3993         intel_psr_disable(intel_dp, old_crtc_state);
3994         intel_edp_backlight_off(old_conn_state);
3995         /* Disable the decompression in DP Sink */
3996         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
3997                                               false);
3998 }
3999
4000 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
4001                                    struct intel_encoder *encoder,
4002                                    const struct intel_crtc_state *old_crtc_state,
4003                                    const struct drm_connector_state *old_conn_state)
4004 {
4005         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4006         struct drm_connector *connector = old_conn_state->connector;
4007
4008         if (old_crtc_state->has_audio)
4009                 intel_audio_codec_disable(encoder,
4010                                           old_crtc_state, old_conn_state);
4011
4012         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
4013                                                false, false))
4014                 drm_dbg_kms(&i915->drm,
4015                             "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
4016                             connector->base.id, connector->name);
4017 }
4018
4019 static void intel_disable_ddi(struct intel_atomic_state *state,
4020                               struct intel_encoder *encoder,
4021                               const struct intel_crtc_state *old_crtc_state,
4022                               const struct drm_connector_state *old_conn_state)
4023 {
4024         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
4025
4026         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
4027                 intel_disable_ddi_hdmi(state, encoder, old_crtc_state,
4028                                        old_conn_state);
4029         else
4030                 intel_disable_ddi_dp(state, encoder, old_crtc_state,
4031                                      old_conn_state);
4032 }
4033
4034 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
4035                                      struct intel_encoder *encoder,
4036                                      const struct intel_crtc_state *crtc_state,
4037                                      const struct drm_connector_state *conn_state)
4038 {
4039         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4040
4041         intel_ddi_set_dp_msa(crtc_state, conn_state);
4042
4043         intel_psr_update(intel_dp, crtc_state, conn_state);
4044         intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
4045         intel_edp_drrs_update(intel_dp, crtc_state);
4046
4047         intel_panel_update_backlight(state, encoder, crtc_state, conn_state);
4048 }
4049
4050 static void intel_ddi_update_pipe(struct intel_atomic_state *state,
4051                                   struct intel_encoder *encoder,
4052                                   const struct intel_crtc_state *crtc_state,
4053                                   const struct drm_connector_state *conn_state)
4054 {
4055
4056         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
4057                 intel_ddi_update_pipe_dp(state, encoder, crtc_state,
4058                                          conn_state);
4059
4060         intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
4061 }
4062
4063 static void
4064 intel_ddi_update_prepare(struct intel_atomic_state *state,
4065                          struct intel_encoder *encoder,
4066                          struct intel_crtc *crtc)
4067 {
4068         struct intel_crtc_state *crtc_state =
4069                 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
4070         int required_lanes = crtc_state ? crtc_state->lane_count : 1;
4071
4072         drm_WARN_ON(state->base.dev, crtc && crtc->active);
4073
4074         intel_tc_port_get_link(enc_to_dig_port(encoder),
4075                                required_lanes);
4076         if (crtc_state && crtc_state->hw.active)
4077                 intel_update_active_dpll(state, crtc, encoder);
4078 }
4079
4080 static void
4081 intel_ddi_update_complete(struct intel_atomic_state *state,
4082                           struct intel_encoder *encoder,
4083                           struct intel_crtc *crtc)
4084 {
4085         intel_tc_port_put_link(enc_to_dig_port(encoder));
4086 }
4087
4088 static void
4089 intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
4090                          struct intel_encoder *encoder,
4091                          const struct intel_crtc_state *crtc_state,
4092                          const struct drm_connector_state *conn_state)
4093 {
4094         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4095         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4096         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
4097         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
4098
4099         if (is_tc_port)
4100                 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
4101
4102         if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port)
4103                 intel_display_power_get(dev_priv,
4104                                         intel_ddi_main_link_aux_domain(dig_port));
4105
4106         if (is_tc_port && dig_port->tc_mode != TC_PORT_TBT_ALT)
4107                 /*
4108                  * Program the lane count for static/dynamic connections on
4109                  * Type-C ports.  Skip this step for TBT.
4110                  */
4111                 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
4112         else if (IS_GEN9_LP(dev_priv))
4113                 bxt_ddi_phy_set_lane_optim_mask(encoder,
4114                                                 crtc_state->lane_lat_optim_mask);
4115 }
4116
4117 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
4118 {
4119         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4120         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4121         enum port port = dig_port->base.port;
4122         u32 dp_tp_ctl, ddi_buf_ctl;
4123         bool wait = false;
4124
4125         dp_tp_ctl = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
4126
4127         if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
4128                 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
4129                 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
4130                         intel_de_write(dev_priv, DDI_BUF_CTL(port),
4131                                        ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
4132                         wait = true;
4133                 }
4134
4135                 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
4136                 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
4137                 intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
4138                 intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
4139
4140                 if (wait)
4141                         intel_wait_ddi_buf_idle(dev_priv, port);
4142         }
4143
4144         dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
4145         if (intel_dp->link_mst)
4146                 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
4147         else {
4148                 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
4149                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
4150                         dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
4151         }
4152         intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, dp_tp_ctl);
4153         intel_de_posting_read(dev_priv, intel_dp->regs.dp_tp_ctl);
4154
4155         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
4156         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
4157         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
4158
4159         intel_wait_ddi_buf_active(dev_priv, port);
4160 }
4161
4162 static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
4163                                      u8 dp_train_pat)
4164 {
4165         struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
4166         u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd);
4167         u32 temp;
4168
4169         temp = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
4170
4171         temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
4172         switch (dp_train_pat & train_pat_mask) {
4173         case DP_TRAINING_PATTERN_DISABLE:
4174                 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
4175                 break;
4176         case DP_TRAINING_PATTERN_1:
4177                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
4178                 break;
4179         case DP_TRAINING_PATTERN_2:
4180                 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
4181                 break;
4182         case DP_TRAINING_PATTERN_3:
4183                 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
4184                 break;
4185         case DP_TRAINING_PATTERN_4:
4186                 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
4187                 break;
4188         }
4189
4190         intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, temp);
4191 }
4192
4193 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp)
4194 {
4195         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4196         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4197         enum port port = encoder->port;
4198         u32 val;
4199
4200         val = intel_de_read(dev_priv, intel_dp->regs.dp_tp_ctl);
4201         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
4202         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
4203         intel_de_write(dev_priv, intel_dp->regs.dp_tp_ctl, val);
4204
4205         /*
4206          * Until TGL on PORT_A we can have only eDP in SST mode. There the only
4207          * reason we need to set idle transmission mode is to work around a HW
4208          * issue where we enable the pipe while not in idle link-training mode.
4209          * In this case there is requirement to wait for a minimum number of
4210          * idle patterns to be sent.
4211          */
4212         if (port == PORT_A && INTEL_GEN(dev_priv) < 12)
4213                 return;
4214
4215         if (intel_de_wait_for_set(dev_priv, intel_dp->regs.dp_tp_status,
4216                                   DP_TP_STATUS_IDLE_DONE, 1))
4217                 drm_err(&dev_priv->drm,
4218                         "Timed out waiting for DP idle patterns\n");
4219 }
4220
4221 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
4222                                        enum transcoder cpu_transcoder)
4223 {
4224         if (cpu_transcoder == TRANSCODER_EDP)
4225                 return false;
4226
4227         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO))
4228                 return false;
4229
4230         return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &
4231                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
4232 }
4233
4234 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
4235                                          struct intel_crtc_state *crtc_state)
4236 {
4237         if (INTEL_GEN(dev_priv) >= 12 && crtc_state->port_clock > 594000)
4238                 crtc_state->min_voltage_level = 2;
4239         else if (IS_ELKHARTLAKE(dev_priv) && crtc_state->port_clock > 594000)
4240                 crtc_state->min_voltage_level = 3;
4241         else if (INTEL_GEN(dev_priv) >= 11 && crtc_state->port_clock > 594000)
4242                 crtc_state->min_voltage_level = 1;
4243         else if (IS_CANNONLAKE(dev_priv) && crtc_state->port_clock > 594000)
4244                 crtc_state->min_voltage_level = 2;
4245 }
4246
4247 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv,
4248                                                      enum transcoder cpu_transcoder)
4249 {
4250         u32 master_select;
4251
4252         if (INTEL_GEN(dev_priv) >= 11) {
4253                 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder));
4254
4255                 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
4256                         return INVALID_TRANSCODER;
4257
4258                 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
4259         } else {
4260                 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
4261
4262                 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0)
4263                         return INVALID_TRANSCODER;
4264
4265                 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl);
4266         }
4267
4268         if (master_select == 0)
4269                 return TRANSCODER_EDP;
4270         else
4271                 return master_select - 1;
4272 }
4273
4274 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
4275 {
4276         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4277         u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
4278                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
4279         enum transcoder cpu_transcoder;
4280
4281         crtc_state->master_transcoder =
4282                 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder);
4283
4284         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
4285                 enum intel_display_power_domain power_domain;
4286                 intel_wakeref_t trans_wakeref;
4287
4288                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
4289                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
4290                                                                    power_domain);
4291
4292                 if (!trans_wakeref)
4293                         continue;
4294
4295                 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) ==
4296                     crtc_state->cpu_transcoder)
4297                         crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
4298
4299                 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
4300         }
4301
4302         drm_WARN_ON(&dev_priv->drm,
4303                     crtc_state->master_transcoder != INVALID_TRANSCODER &&
4304                     crtc_state->sync_mode_slaves_mask);
4305 }
4306
4307 void intel_ddi_get_config(struct intel_encoder *encoder,
4308                           struct intel_crtc_state *pipe_config)
4309 {
4310         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4311         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->uapi.crtc);
4312         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4313         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4314         u32 temp, flags = 0;
4315
4316         /* XXX: DSI transcoder paranoia */
4317         if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
4318                 return;
4319
4320         intel_dsc_get_config(encoder, pipe_config);
4321
4322         temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
4323         if (temp & TRANS_DDI_PHSYNC)
4324                 flags |= DRM_MODE_FLAG_PHSYNC;
4325         else
4326                 flags |= DRM_MODE_FLAG_NHSYNC;
4327         if (temp & TRANS_DDI_PVSYNC)
4328                 flags |= DRM_MODE_FLAG_PVSYNC;
4329         else
4330                 flags |= DRM_MODE_FLAG_NVSYNC;
4331
4332         pipe_config->hw.adjusted_mode.flags |= flags;
4333
4334         switch (temp & TRANS_DDI_BPC_MASK) {
4335         case TRANS_DDI_BPC_6:
4336                 pipe_config->pipe_bpp = 18;
4337                 break;
4338         case TRANS_DDI_BPC_8:
4339                 pipe_config->pipe_bpp = 24;
4340                 break;
4341         case TRANS_DDI_BPC_10:
4342                 pipe_config->pipe_bpp = 30;
4343                 break;
4344         case TRANS_DDI_BPC_12:
4345                 pipe_config->pipe_bpp = 36;
4346                 break;
4347         default:
4348                 break;
4349         }
4350
4351         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
4352         case TRANS_DDI_MODE_SELECT_HDMI:
4353                 pipe_config->has_hdmi_sink = true;
4354
4355                 pipe_config->infoframes.enable |=
4356                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
4357
4358                 if (pipe_config->infoframes.enable)
4359                         pipe_config->has_infoframe = true;
4360
4361                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
4362                         pipe_config->hdmi_scrambling = true;
4363                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
4364                         pipe_config->hdmi_high_tmds_clock_ratio = true;
4365                 /* fall through */
4366         case TRANS_DDI_MODE_SELECT_DVI:
4367                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
4368                 pipe_config->lane_count = 4;
4369                 break;
4370         case TRANS_DDI_MODE_SELECT_FDI:
4371                 pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
4372                 break;
4373         case TRANS_DDI_MODE_SELECT_DP_SST:
4374                 if (encoder->type == INTEL_OUTPUT_EDP)
4375                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
4376                 else
4377                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
4378                 pipe_config->lane_count =
4379                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4380                 intel_dp_get_m_n(intel_crtc, pipe_config);
4381
4382                 if (INTEL_GEN(dev_priv) >= 11) {
4383                         i915_reg_t dp_tp_ctl;
4384
4385                         if (IS_GEN(dev_priv, 11))
4386                                 dp_tp_ctl = DP_TP_CTL(encoder->port);
4387                         else
4388                                 dp_tp_ctl = TGL_DP_TP_CTL(pipe_config->cpu_transcoder);
4389
4390                         pipe_config->fec_enable =
4391                                 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
4392
4393                         drm_dbg_kms(&dev_priv->drm,
4394                                     "[ENCODER:%d:%s] Fec status: %u\n",
4395                                     encoder->base.base.id, encoder->base.name,
4396                                     pipe_config->fec_enable);
4397                 }
4398
4399                 pipe_config->infoframes.enable |=
4400                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
4401
4402                 break;
4403         case TRANS_DDI_MODE_SELECT_DP_MST:
4404                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
4405                 pipe_config->lane_count =
4406                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
4407
4408                 if (INTEL_GEN(dev_priv) >= 12)
4409                         pipe_config->mst_master_transcoder =
4410                                         REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
4411
4412                 intel_dp_get_m_n(intel_crtc, pipe_config);
4413
4414                 pipe_config->infoframes.enable |=
4415                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
4416                 break;
4417         default:
4418                 break;
4419         }
4420
4421         if (INTEL_GEN(dev_priv) >= 12) {
4422                 enum transcoder transcoder =
4423                         intel_dp_mst_is_slave_trans(pipe_config) ?
4424                         pipe_config->mst_master_transcoder :
4425                         pipe_config->cpu_transcoder;
4426
4427                 intel_dp->regs.dp_tp_ctl = TGL_DP_TP_CTL(transcoder);
4428                 intel_dp->regs.dp_tp_status = TGL_DP_TP_STATUS(transcoder);
4429         }
4430
4431         pipe_config->has_audio =
4432                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
4433
4434         if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
4435             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
4436                 /*
4437                  * This is a big fat ugly hack.
4438                  *
4439                  * Some machines in UEFI boot mode provide us a VBT that has 18
4440                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
4441                  * unknown we fail to light up. Yet the same BIOS boots up with
4442                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
4443                  * max, not what it tells us to use.
4444                  *
4445                  * Note: This will still be broken if the eDP panel is not lit
4446                  * up by the BIOS, and thus we can't get the mode at module
4447                  * load.
4448                  */
4449                 drm_dbg_kms(&dev_priv->drm,
4450                             "pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
4451                             pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
4452                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
4453         }
4454
4455         intel_ddi_clock_get(encoder, pipe_config);
4456
4457         if (IS_GEN9_LP(dev_priv))
4458                 pipe_config->lane_lat_optim_mask =
4459                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
4460
4461         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4462
4463         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
4464
4465         intel_read_infoframe(encoder, pipe_config,
4466                              HDMI_INFOFRAME_TYPE_AVI,
4467                              &pipe_config->infoframes.avi);
4468         intel_read_infoframe(encoder, pipe_config,
4469                              HDMI_INFOFRAME_TYPE_SPD,
4470                              &pipe_config->infoframes.spd);
4471         intel_read_infoframe(encoder, pipe_config,
4472                              HDMI_INFOFRAME_TYPE_VENDOR,
4473                              &pipe_config->infoframes.hdmi);
4474         intel_read_infoframe(encoder, pipe_config,
4475                              HDMI_INFOFRAME_TYPE_DRM,
4476                              &pipe_config->infoframes.drm);
4477
4478         if (INTEL_GEN(dev_priv) >= 8)
4479                 bdw_get_trans_port_sync_config(pipe_config);
4480
4481         intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
4482         intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
4483 }
4484
4485 static enum intel_output_type
4486 intel_ddi_compute_output_type(struct intel_encoder *encoder,
4487                               struct intel_crtc_state *crtc_state,
4488                               struct drm_connector_state *conn_state)
4489 {
4490         switch (conn_state->connector->connector_type) {
4491         case DRM_MODE_CONNECTOR_HDMIA:
4492                 return INTEL_OUTPUT_HDMI;
4493         case DRM_MODE_CONNECTOR_eDP:
4494                 return INTEL_OUTPUT_EDP;
4495         case DRM_MODE_CONNECTOR_DisplayPort:
4496                 return INTEL_OUTPUT_DP;
4497         default:
4498                 MISSING_CASE(conn_state->connector->connector_type);
4499                 return INTEL_OUTPUT_UNUSED;
4500         }
4501 }
4502
4503 static int intel_ddi_compute_config(struct intel_encoder *encoder,
4504                                     struct intel_crtc_state *pipe_config,
4505                                     struct drm_connector_state *conn_state)
4506 {
4507         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
4508         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4509         enum port port = encoder->port;
4510         int ret;
4511
4512         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
4513                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
4514
4515         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
4516                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
4517         } else {
4518                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
4519         }
4520
4521         if (ret)
4522                 return ret;
4523
4524         if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
4525             pipe_config->cpu_transcoder == TRANSCODER_EDP)
4526                 pipe_config->pch_pfit.force_thru =
4527                         pipe_config->pch_pfit.enabled ||
4528                         pipe_config->crc_enabled;
4529
4530         if (IS_GEN9_LP(dev_priv))
4531                 pipe_config->lane_lat_optim_mask =
4532                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
4533
4534         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
4535
4536         return 0;
4537 }
4538
4539 static bool mode_equal(const struct drm_display_mode *mode1,
4540                        const struct drm_display_mode *mode2)
4541 {
4542         return drm_mode_match(mode1, mode2,
4543                               DRM_MODE_MATCH_TIMINGS |
4544                               DRM_MODE_MATCH_FLAGS |
4545                               DRM_MODE_MATCH_3D_FLAGS) &&
4546                 mode1->clock == mode2->clock; /* we want an exact match */
4547 }
4548
4549 static bool m_n_equal(const struct intel_link_m_n *m_n_1,
4550                       const struct intel_link_m_n *m_n_2)
4551 {
4552         return m_n_1->tu == m_n_2->tu &&
4553                 m_n_1->gmch_m == m_n_2->gmch_m &&
4554                 m_n_1->gmch_n == m_n_2->gmch_n &&
4555                 m_n_1->link_m == m_n_2->link_m &&
4556                 m_n_1->link_n == m_n_2->link_n;
4557 }
4558
4559 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
4560                                        const struct intel_crtc_state *crtc_state2)
4561 {
4562         return crtc_state1->hw.active && crtc_state2->hw.active &&
4563                 crtc_state1->output_types == crtc_state2->output_types &&
4564                 crtc_state1->output_format == crtc_state2->output_format &&
4565                 crtc_state1->lane_count == crtc_state2->lane_count &&
4566                 crtc_state1->port_clock == crtc_state2->port_clock &&
4567                 mode_equal(&crtc_state1->hw.adjusted_mode,
4568                            &crtc_state2->hw.adjusted_mode) &&
4569                 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n);
4570 }
4571
4572 static u8
4573 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state,
4574                                 int tile_group_id)
4575 {
4576         struct drm_connector *connector;
4577         const struct drm_connector_state *conn_state;
4578         struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev);
4579         struct intel_atomic_state *state =
4580                 to_intel_atomic_state(ref_crtc_state->uapi.state);
4581         u8 transcoders = 0;
4582         int i;
4583
4584         /*
4585          * We don't enable port sync on BDW due to missing w/as and
4586          * due to not having adjusted the modeset sequence appropriately.
4587          */
4588         if (INTEL_GEN(dev_priv) < 9)
4589                 return 0;
4590
4591         if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
4592                 return 0;
4593
4594         for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
4595                 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
4596                 const struct intel_crtc_state *crtc_state;
4597
4598                 if (!crtc)
4599                         continue;
4600
4601                 if (!connector->has_tile ||
4602                     connector->tile_group->id !=
4603                     tile_group_id)
4604                         continue;
4605                 crtc_state = intel_atomic_get_new_crtc_state(state,
4606                                                              crtc);
4607                 if (!crtcs_port_sync_compatible(ref_crtc_state,
4608                                                 crtc_state))
4609                         continue;
4610                 transcoders |= BIT(crtc_state->cpu_transcoder);
4611         }
4612
4613         return transcoders;
4614 }
4615
4616 static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
4617                                          struct intel_crtc_state *crtc_state,
4618                                          struct drm_connector_state *conn_state)
4619 {
4620         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4621         struct drm_connector *connector = conn_state->connector;
4622         u8 port_sync_transcoders = 0;
4623
4624         drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]",
4625                     encoder->base.base.id, encoder->base.name,
4626                     crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
4627
4628         if (connector->has_tile)
4629                 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state,
4630                                                                         connector->tile_group->id);
4631
4632         /*
4633          * EDP Transcoders cannot be ensalved
4634          * make them a master always when present
4635          */
4636         if (port_sync_transcoders & BIT(TRANSCODER_EDP))
4637                 crtc_state->master_transcoder = TRANSCODER_EDP;
4638         else
4639                 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;
4640
4641         if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {
4642                 crtc_state->master_transcoder = INVALID_TRANSCODER;
4643                 crtc_state->sync_mode_slaves_mask =
4644                         port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
4645         }
4646
4647         return 0;
4648 }
4649
4650 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
4651 {
4652         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
4653
4654         intel_dp_encoder_flush_work(encoder);
4655
4656         drm_encoder_cleanup(encoder);
4657         kfree(dig_port);
4658 }
4659
4660 static const struct drm_encoder_funcs intel_ddi_funcs = {
4661         .reset = intel_dp_encoder_reset,
4662         .destroy = intel_ddi_encoder_destroy,
4663 };
4664
4665 static struct intel_connector *
4666 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
4667 {
4668         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4669         struct intel_connector *connector;
4670         enum port port = dig_port->base.port;
4671
4672         connector = intel_connector_alloc();
4673         if (!connector)
4674                 return NULL;
4675
4676         dig_port->dp.output_reg = DDI_BUF_CTL(port);
4677         dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain;
4678         dig_port->dp.set_link_train = intel_ddi_set_link_train;
4679         dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
4680
4681         if (INTEL_GEN(dev_priv) >= 12)
4682                 dig_port->dp.set_signal_levels = tgl_set_signal_levels;
4683         else if (INTEL_GEN(dev_priv) >= 11)
4684                 dig_port->dp.set_signal_levels = icl_set_signal_levels;
4685         else if (IS_CANNONLAKE(dev_priv))
4686                 dig_port->dp.set_signal_levels = cnl_set_signal_levels;
4687         else if (IS_GEN9_LP(dev_priv))
4688                 dig_port->dp.set_signal_levels = bxt_set_signal_levels;
4689         else
4690                 dig_port->dp.set_signal_levels = hsw_set_signal_levels;
4691
4692         dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
4693         dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
4694
4695         if (INTEL_GEN(dev_priv) < 12) {
4696                 dig_port->dp.regs.dp_tp_ctl = DP_TP_CTL(port);
4697                 dig_port->dp.regs.dp_tp_status = DP_TP_STATUS(port);
4698         }
4699
4700         if (!intel_dp_init_connector(dig_port, connector)) {
4701                 kfree(connector);
4702                 return NULL;
4703         }
4704
4705         return connector;
4706 }
4707
4708 static int modeset_pipe(struct drm_crtc *crtc,
4709                         struct drm_modeset_acquire_ctx *ctx)
4710 {
4711         struct drm_atomic_state *state;
4712         struct drm_crtc_state *crtc_state;
4713         int ret;
4714
4715         state = drm_atomic_state_alloc(crtc->dev);
4716         if (!state)
4717                 return -ENOMEM;
4718
4719         state->acquire_ctx = ctx;
4720
4721         crtc_state = drm_atomic_get_crtc_state(state, crtc);
4722         if (IS_ERR(crtc_state)) {
4723                 ret = PTR_ERR(crtc_state);
4724                 goto out;
4725         }
4726
4727         crtc_state->connectors_changed = true;
4728
4729         ret = drm_atomic_commit(state);
4730 out:
4731         drm_atomic_state_put(state);
4732
4733         return ret;
4734 }
4735
4736 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
4737                                  struct drm_modeset_acquire_ctx *ctx)
4738 {
4739         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4740         struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
4741         struct intel_connector *connector = hdmi->attached_connector;
4742         struct i2c_adapter *adapter =
4743                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
4744         struct drm_connector_state *conn_state;
4745         struct intel_crtc_state *crtc_state;
4746         struct intel_crtc *crtc;
4747         u8 config;
4748         int ret;
4749
4750         if (!connector || connector->base.status != connector_status_connected)
4751                 return 0;
4752
4753         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
4754                                ctx);
4755         if (ret)
4756                 return ret;
4757
4758         conn_state = connector->base.state;
4759
4760         crtc = to_intel_crtc(conn_state->crtc);
4761         if (!crtc)
4762                 return 0;
4763
4764         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
4765         if (ret)
4766                 return ret;
4767
4768         crtc_state = to_intel_crtc_state(crtc->base.state);
4769
4770         drm_WARN_ON(&dev_priv->drm,
4771                     !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
4772
4773         if (!crtc_state->hw.active)
4774                 return 0;
4775
4776         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
4777             !crtc_state->hdmi_scrambling)
4778                 return 0;
4779
4780         if (conn_state->commit &&
4781             !try_wait_for_completion(&conn_state->commit->hw_done))
4782                 return 0;
4783
4784         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
4785         if (ret < 0) {
4786                 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n",
4787                         ret);
4788                 return 0;
4789         }
4790
4791         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
4792             crtc_state->hdmi_high_tmds_clock_ratio &&
4793             !!(config & SCDC_SCRAMBLING_ENABLE) ==
4794             crtc_state->hdmi_scrambling)
4795                 return 0;
4796
4797         /*
4798          * HDMI 2.0 says that one should not send scrambled data
4799          * prior to configuring the sink scrambling, and that
4800          * TMDS clock/data transmission should be suspended when
4801          * changing the TMDS clock rate in the sink. So let's
4802          * just do a full modeset here, even though some sinks
4803          * would be perfectly happy if were to just reconfigure
4804          * the SCDC settings on the fly.
4805          */
4806         return modeset_pipe(&crtc->base, ctx);
4807 }
4808
4809 static enum intel_hotplug_state
4810 intel_ddi_hotplug(struct intel_encoder *encoder,
4811                   struct intel_connector *connector)
4812 {
4813         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
4814         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
4815         enum phy phy = intel_port_to_phy(i915, encoder->port);
4816         bool is_tc = intel_phy_is_tc(i915, phy);
4817         struct drm_modeset_acquire_ctx ctx;
4818         enum intel_hotplug_state state;
4819         int ret;
4820
4821         state = intel_encoder_hotplug(encoder, connector);
4822
4823         drm_modeset_acquire_init(&ctx, 0);
4824
4825         for (;;) {
4826                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
4827                         ret = intel_hdmi_reset_link(encoder, &ctx);
4828                 else
4829                         ret = intel_dp_retrain_link(encoder, &ctx);
4830
4831                 if (ret == -EDEADLK) {
4832                         drm_modeset_backoff(&ctx);
4833                         continue;
4834                 }
4835
4836                 break;
4837         }
4838
4839         drm_modeset_drop_locks(&ctx);
4840         drm_modeset_acquire_fini(&ctx);
4841         drm_WARN(encoder->base.dev, ret,
4842                  "Acquiring modeset locks failed with %i\n", ret);
4843
4844         /*
4845          * Unpowered type-c dongles can take some time to boot and be
4846          * responsible, so here giving some time to those dongles to power up
4847          * and then retrying the probe.
4848          *
4849          * On many platforms the HDMI live state signal is known to be
4850          * unreliable, so we can't use it to detect if a sink is connected or
4851          * not. Instead we detect if it's connected based on whether we can
4852          * read the EDID or not. That in turn has a problem during disconnect,
4853          * since the HPD interrupt may be raised before the DDC lines get
4854          * disconnected (due to how the required length of DDC vs. HPD
4855          * connector pins are specified) and so we'll still be able to get a
4856          * valid EDID. To solve this schedule another detection cycle if this
4857          * time around we didn't detect any change in the sink's connection
4858          * status.
4859          *
4860          * Type-c connectors which get their HPD signal deasserted then
4861          * reasserted, without unplugging/replugging the sink from the
4862          * connector, introduce a delay until the AUX channel communication
4863          * becomes functional. Retry the detection for 5 seconds on type-c
4864          * connectors to account for this delay.
4865          */
4866         if (state == INTEL_HOTPLUG_UNCHANGED &&
4867             connector->hotplug_retries < (is_tc ? 5 : 1) &&
4868             !dig_port->dp.is_mst)
4869                 state = INTEL_HOTPLUG_RETRY;
4870
4871         return state;
4872 }
4873
4874 static bool lpt_digital_port_connected(struct intel_encoder *encoder)
4875 {
4876         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4877         u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
4878
4879         return intel_de_read(dev_priv, SDEISR) & bit;
4880 }
4881
4882 static bool hsw_digital_port_connected(struct intel_encoder *encoder)
4883 {
4884         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4885         u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
4886
4887         return intel_de_read(dev_priv, DEISR) & bit;
4888 }
4889
4890 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4891 {
4892         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4893         u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
4894
4895         return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
4896 }
4897
4898 static struct intel_connector *
4899 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port)
4900 {
4901         struct intel_connector *connector;
4902         enum port port = dig_port->base.port;
4903
4904         connector = intel_connector_alloc();
4905         if (!connector)
4906                 return NULL;
4907
4908         dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4909         intel_hdmi_init_connector(dig_port, connector);
4910
4911         return connector;
4912 }
4913
4914 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
4915 {
4916         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4917
4918         if (dig_port->base.port != PORT_A)
4919                 return false;
4920
4921         if (dig_port->saved_port_bits & DDI_A_4_LANES)
4922                 return false;
4923
4924         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4925          *                     supported configuration
4926          */
4927         if (IS_GEN9_LP(dev_priv))
4928                 return true;
4929
4930         /* Cannonlake: Most of SKUs don't support DDI_E, and the only
4931          *             one who does also have a full A/E split called
4932          *             DDI_F what makes DDI_E useless. However for this
4933          *             case let's trust VBT info.
4934          */
4935         if (IS_CANNONLAKE(dev_priv) &&
4936             !intel_bios_is_port_present(dev_priv, PORT_E))
4937                 return true;
4938
4939         return false;
4940 }
4941
4942 static int
4943 intel_ddi_max_lanes(struct intel_digital_port *dig_port)
4944 {
4945         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4946         enum port port = dig_port->base.port;
4947         int max_lanes = 4;
4948
4949         if (INTEL_GEN(dev_priv) >= 11)
4950                 return max_lanes;
4951
4952         if (port == PORT_A || port == PORT_E) {
4953                 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4954                         max_lanes = port == PORT_A ? 4 : 0;
4955                 else
4956                         /* Both A and E share 2 lanes */
4957                         max_lanes = 2;
4958         }
4959
4960         /*
4961          * Some BIOS might fail to set this bit on port A if eDP
4962          * wasn't lit up at boot.  Force this bit set when needed
4963          * so we use the proper lane count for our calculations.
4964          */
4965         if (intel_ddi_a_force_4_lanes(dig_port)) {
4966                 drm_dbg_kms(&dev_priv->drm,
4967                             "Forcing DDI_A_4_LANES for port A\n");
4968                 dig_port->saved_port_bits |= DDI_A_4_LANES;
4969                 max_lanes = 4;
4970         }
4971
4972         return max_lanes;
4973 }
4974
4975 static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
4976 {
4977         return i915->hti_state & HDPORT_ENABLED &&
4978                 (i915->hti_state & HDPORT_PHY_USED_DP(phy) ||
4979                  i915->hti_state & HDPORT_PHY_USED_HDMI(phy));
4980 }
4981
4982 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4983 {
4984         struct intel_digital_port *dig_port;
4985         struct intel_encoder *encoder;
4986         bool init_hdmi, init_dp, init_lspcon = false;
4987         enum phy phy = intel_port_to_phy(dev_priv, port);
4988
4989         /*
4990          * On platforms with HTI (aka HDPORT), if it's enabled at boot it may
4991          * have taken over some of the PHYs and made them unavailable to the
4992          * driver.  In that case we should skip initializing the corresponding
4993          * outputs.
4994          */
4995         if (hti_uses_phy(dev_priv, phy)) {
4996                 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n",
4997                             port_name(port), phy_name(phy));
4998                 return;
4999         }
5000
5001         init_hdmi = intel_bios_port_supports_dvi(dev_priv, port) ||
5002                 intel_bios_port_supports_hdmi(dev_priv, port);
5003         init_dp = intel_bios_port_supports_dp(dev_priv, port);
5004
5005         if (intel_bios_is_lspcon_present(dev_priv, port)) {
5006                 /*
5007                  * Lspcon device needs to be driven with DP connector
5008                  * with special detection sequence. So make sure DP
5009                  * is initialized before lspcon.
5010                  */
5011                 init_dp = true;
5012                 init_lspcon = true;
5013                 init_hdmi = false;
5014                 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n",
5015                             port_name(port));
5016         }
5017
5018         if (!init_dp && !init_hdmi) {
5019                 drm_dbg_kms(&dev_priv->drm,
5020                             "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
5021                             port_name(port));
5022                 return;
5023         }
5024
5025         dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
5026         if (!dig_port)
5027                 return;
5028
5029         encoder = &dig_port->base;
5030
5031         drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
5032                          DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
5033
5034         encoder->hotplug = intel_ddi_hotplug;
5035         encoder->compute_output_type = intel_ddi_compute_output_type;
5036         encoder->compute_config = intel_ddi_compute_config;
5037         encoder->compute_config_late = intel_ddi_compute_config_late;
5038         encoder->enable = intel_enable_ddi;
5039         encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
5040         encoder->pre_enable = intel_ddi_pre_enable;
5041         encoder->disable = intel_disable_ddi;
5042         encoder->post_disable = intel_ddi_post_disable;
5043         encoder->update_pipe = intel_ddi_update_pipe;
5044         encoder->get_hw_state = intel_ddi_get_hw_state;
5045         encoder->get_config = intel_ddi_get_config;
5046         encoder->suspend = intel_dp_encoder_suspend;
5047         encoder->get_power_domains = intel_ddi_get_power_domains;
5048
5049         encoder->type = INTEL_OUTPUT_DDI;
5050         encoder->power_domain = intel_port_to_power_domain(port);
5051         encoder->port = port;
5052         encoder->cloneable = 0;
5053         encoder->pipe_mask = ~0;
5054
5055         if (INTEL_GEN(dev_priv) >= 11)
5056                 dig_port->saved_port_bits =
5057                         intel_de_read(dev_priv, DDI_BUF_CTL(port))
5058                         & DDI_BUF_PORT_REVERSAL;
5059         else
5060                 dig_port->saved_port_bits =
5061                         intel_de_read(dev_priv, DDI_BUF_CTL(port))
5062                         & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
5063
5064         dig_port->dp.output_reg = INVALID_MMIO_REG;
5065         dig_port->max_lanes = intel_ddi_max_lanes(dig_port);
5066         dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
5067
5068         if (intel_phy_is_tc(dev_priv, phy)) {
5069                 bool is_legacy =
5070                         !intel_bios_port_supports_typec_usb(dev_priv, port) &&
5071                         !intel_bios_port_supports_tbt(dev_priv, port);
5072
5073                 intel_tc_port_init(dig_port, is_legacy);
5074
5075                 encoder->update_prepare = intel_ddi_update_prepare;
5076                 encoder->update_complete = intel_ddi_update_complete;
5077         }
5078
5079         drm_WARN_ON(&dev_priv->drm, port > PORT_I);
5080         dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +
5081                                               port - PORT_A;
5082
5083         if (init_dp) {
5084                 if (!intel_ddi_init_dp_connector(dig_port))
5085                         goto err;
5086
5087                 dig_port->hpd_pulse = intel_dp_hpd_pulse;
5088         }
5089
5090         /* In theory we don't need the encoder->type check, but leave it just in
5091          * case we have some really bad VBTs... */
5092         if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
5093                 if (!intel_ddi_init_hdmi_connector(dig_port))
5094                         goto err;
5095         }
5096
5097         if (init_lspcon) {
5098                 if (lspcon_init(dig_port))
5099                         /* TODO: handle hdmi info frame part */
5100                         drm_dbg_kms(&dev_priv->drm,
5101                                     "LSPCON init success on port %c\n",
5102                                     port_name(port));
5103                 else
5104                         /*
5105                          * LSPCON init faied, but DP init was success, so
5106                          * lets try to drive as DP++ port.
5107                          */
5108                         drm_err(&dev_priv->drm,
5109                                 "LSPCON init failed on port %c\n",
5110                                 port_name(port));
5111         }
5112
5113         if (INTEL_GEN(dev_priv) >= 11) {
5114                 if (intel_phy_is_tc(dev_priv, phy))
5115                         dig_port->connected = intel_tc_port_connected;
5116                 else
5117                         dig_port->connected = lpt_digital_port_connected;
5118         } else if (INTEL_GEN(dev_priv) >= 8) {
5119                 if (port == PORT_A || IS_GEN9_LP(dev_priv))
5120                         dig_port->connected = bdw_digital_port_connected;
5121                 else
5122                         dig_port->connected = lpt_digital_port_connected;
5123         } else {
5124                 if (port == PORT_A)
5125                         dig_port->connected = hsw_digital_port_connected;
5126                 else
5127                         dig_port->connected = lpt_digital_port_connected;
5128         }
5129
5130         intel_infoframe_init(dig_port);
5131
5132         return;
5133
5134 err:
5135         drm_encoder_cleanup(&encoder->base);
5136         kfree(dig_port);
5137 }