drivers/gpu/drm/i915/display/intel_ddi.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/string_helpers.h>
  29
  30 #include <drm/display/drm_scdc_helper.h>
  31 #include <drm/drm_privacy_screen_consumer.h>
  32
  33 #include "i915_drv.h"
  34 #include "intel_audio.h"
  35 #include "intel_audio_regs.h"
  36 #include "intel_backlight.h"
  37 #include "intel_combo_phy.h"
  38 #include "intel_combo_phy_regs.h"
  39 #include "intel_connector.h"
  40 #include "intel_crtc.h"
  41 #include "intel_ddi.h"
  42 #include "intel_ddi_buf_trans.h"
  43 #include "intel_de.h"
  44 #include "intel_display_power.h"
  45 #include "intel_display_types.h"
  46 #include "intel_dp.h"
  47 #include "intel_dp_link_training.h"
  48 #include "intel_dp_mst.h"
  49 #include "intel_dpio_phy.h"
  50 #include "intel_dsi.h"
  51 #include "intel_fdi.h"
  52 #include "intel_fifo_underrun.h"
  53 #include "intel_gmbus.h"
  54 #include "intel_hdcp.h"
  55 #include "intel_hdmi.h"
  56 #include "intel_hotplug.h"
  57 #include "intel_lspcon.h"
  58 #include "intel_pps.h"
  59 #include "intel_psr.h"
  60 #include "intel_snps_phy.h"
  61 #include "intel_sprite.h"
  62 #include "intel_tc.h"
  63 #include "intel_tc_phy_regs.h"
  64 #include "intel_vdsc.h"
  65 #include "intel_vrr.h"
  66 #include "skl_scaler.h"
  67 #include "skl_universal_plane.h"
  68
  69 static const u8 index_to_dp_signal_levels[] = {
  70         [0] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  71         [1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  72         [2] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  73         [3] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3,
  74         [4] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  75         [5] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  76         [6] = DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2,
  77         [7] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  78         [8] = DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1,
  79         [9] = DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0,
  80 };
  81
  82 static int intel_ddi_hdmi_level(struct intel_encoder *encoder,
  83                                 const struct intel_ddi_buf_trans *trans)
  84 {
  85         int level;
  86
  87         level = intel_bios_hdmi_level_shift(encoder);
  88         if (level < 0)
  89                 level = trans->hdmi_default_entry;
  90
  91         return level;
  92 }
  93
  94 static bool has_buf_trans_select(struct drm_i915_private *i915)
  95 {
  96         return DISPLAY_VER(i915) < 10 && !IS_BROXTON(i915);
  97 }
  98
  99 static bool has_iboost(struct drm_i915_private *i915)
 100 {
 101         return DISPLAY_VER(i915) == 9 && !IS_BROXTON(i915);
 102 }
 103
 104 /*
 105  * Starting with Haswell, DDI port buffers must be programmed with correct
 106  * values in advance. This function programs the correct values for
 107  * DP/eDP/FDI use cases.
 108  */
 109 void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,
 110                                 const struct intel_crtc_state *crtc_state)
 111 {
 112         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 113         u32 iboost_bit = 0;
 114         int i, n_entries;
 115         enum port port = encoder->port;
 116         const struct intel_ddi_buf_trans *trans;
 117
 118         trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
 119         if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
 120                 return;
 121
 122         /* If we're boosting the current, set bit 31 of trans1 */
 123         if (has_iboost(dev_priv) &&
 124             intel_bios_encoder_dp_boost_level(encoder->devdata))
 125                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 126
 127         for (i = 0; i < n_entries; i++) {
 128                 intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, i),
 129                                trans->entries[i].hsw.trans1 | iboost_bit);
 130                 intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, i),
 131                                trans->entries[i].hsw.trans2);
 132         }
 133 }
 134
 135 /*
 136  * Starting with Haswell, DDI port buffers must be programmed with correct
 137  * values in advance. This function programs the correct values for
 138  * HDMI/DVI use cases.
 139  */
 140 static void hsw_prepare_hdmi_ddi_buffers(struct intel_encoder *encoder,
 141                                          const struct intel_crtc_state *crtc_state)
 142 {
 143         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 144         int level = intel_ddi_level(encoder, crtc_state, 0);
 145         u32 iboost_bit = 0;
 146         int n_entries;
 147         enum port port = encoder->port;
 148         const struct intel_ddi_buf_trans *trans;
 149
 150         trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
 151         if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
 152                 return;
 153
 154         /* If we're boosting the current, set bit 31 of trans1 */
 155         if (has_iboost(dev_priv) &&
 156             intel_bios_encoder_hdmi_boost_level(encoder->devdata))
 157                 iboost_bit = DDI_BUF_BALANCE_LEG_ENABLE;
 158
 159         /* Entry 9 is for HDMI: */
 160         intel_de_write(dev_priv, DDI_BUF_TRANS_LO(port, 9),
 161                        trans->entries[level].hsw.trans1 | iboost_bit);
 162         intel_de_write(dev_priv, DDI_BUF_TRANS_HI(port, 9),
 163                        trans->entries[level].hsw.trans2);
 164 }
 165
 166 void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
 167                              enum port port)
 168 {
 169         if (IS_BROXTON(dev_priv)) {
 170                 udelay(16);
 171                 return;
 172         }
 173
 174         if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
 175                          DDI_BUF_IS_IDLE), 8))
 176                 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get idle\n",
 177                         port_name(port));
 178 }
 179
 180 static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
 181                                       enum port port)
 182 {
 183         int ret;
 184
 185         /* Wait > 518 usecs for DDI_BUF_CTL to be non idle */
 186         if (DISPLAY_VER(dev_priv) < 10) {
 187                 usleep_range(518, 1000);
 188                 return;
 189         }
 190
 191         ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
 192                           DDI_BUF_IS_IDLE), IS_DG2(dev_priv) ? 1200 : 500, 10, 10);
 193
 194         if (ret)
 195                 drm_err(&dev_priv->drm, "Timeout waiting for DDI BUF %c to get active\n",
 196                         port_name(port));
 197 }
 198
 199 static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)
 200 {
 201         switch (pll->info->id) {
 202         case DPLL_ID_WRPLL1:
 203                 return PORT_CLK_SEL_WRPLL1;
 204         case DPLL_ID_WRPLL2:
 205                 return PORT_CLK_SEL_WRPLL2;
 206         case DPLL_ID_SPLL:
 207                 return PORT_CLK_SEL_SPLL;
 208         case DPLL_ID_LCPLL_810:
 209                 return PORT_CLK_SEL_LCPLL_810;
 210         case DPLL_ID_LCPLL_1350:
 211                 return PORT_CLK_SEL_LCPLL_1350;
 212         case DPLL_ID_LCPLL_2700:
 213                 return PORT_CLK_SEL_LCPLL_2700;
 214         default:
 215                 MISSING_CASE(pll->info->id);
 216                 return PORT_CLK_SEL_NONE;
 217         }
 218 }
 219
 220 static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,
 221                                   const struct intel_crtc_state *crtc_state)
 222 {
 223         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 224         int clock = crtc_state->port_clock;
 225         const enum intel_dpll_id id = pll->info->id;
 226
 227         switch (id) {
 228         default:
 229                 /*
 230                  * DPLL_ID_ICL_DPLL0 and DPLL_ID_ICL_DPLL1 should not be used
 231                  * here, so do warn if this get passed in
 232                  */
 233                 MISSING_CASE(id);
 234                 return DDI_CLK_SEL_NONE;
 235         case DPLL_ID_ICL_TBTPLL:
 236                 switch (clock) {
 237                 case 162000:
 238                         return DDI_CLK_SEL_TBT_162;
 239                 case 270000:
 240                         return DDI_CLK_SEL_TBT_270;
 241                 case 540000:
 242                         return DDI_CLK_SEL_TBT_540;
 243                 case 810000:
 244                         return DDI_CLK_SEL_TBT_810;
 245                 default:
 246                         MISSING_CASE(clock);
 247                         return DDI_CLK_SEL_NONE;
 248                 }
 249         case DPLL_ID_ICL_MGPLL1:
 250         case DPLL_ID_ICL_MGPLL2:
 251         case DPLL_ID_ICL_MGPLL3:
 252         case DPLL_ID_ICL_MGPLL4:
 253         case DPLL_ID_TGL_MGPLL5:
 254         case DPLL_ID_TGL_MGPLL6:
 255                 return DDI_CLK_SEL_MG;
 256         }
 257 }
 258
 259 static u32 ddi_buf_phy_link_rate(int port_clock)
 260 {
 261         switch (port_clock) {
 262         case 162000:
 263                 return DDI_BUF_PHY_LINK_RATE(0);
 264         case 216000:
 265                 return DDI_BUF_PHY_LINK_RATE(4);
 266         case 243000:
 267                 return DDI_BUF_PHY_LINK_RATE(5);
 268         case 270000:
 269                 return DDI_BUF_PHY_LINK_RATE(1);
 270         case 324000:
 271                 return DDI_BUF_PHY_LINK_RATE(6);
 272         case 432000:
 273                 return DDI_BUF_PHY_LINK_RATE(7);
 274         case 540000:
 275                 return DDI_BUF_PHY_LINK_RATE(2);
 276         case 810000:
 277                 return DDI_BUF_PHY_LINK_RATE(3);
 278         default:
 279                 MISSING_CASE(port_clock);
 280                 return DDI_BUF_PHY_LINK_RATE(0);
 281         }
 282 }
 283
 284 static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
 285                                       const struct intel_crtc_state *crtc_state)
 286 {
 287         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 288         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 289         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 290         enum phy phy = intel_port_to_phy(i915, encoder->port);
 291
 292         /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
 293         intel_dp->DP = dig_port->saved_port_bits |
 294                 DDI_PORT_WIDTH(crtc_state->lane_count) |
 295                 DDI_BUF_TRANS_SELECT(0);
 296
 297         if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
 298                 intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
 299                 if (!intel_tc_port_in_tbt_alt_mode(dig_port))
 300                         intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
 301         }
 302 }
 303
 304 static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv,
 305                                  enum port port)
 306 {
 307         u32 val = intel_de_read(dev_priv, DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK;
 308
 309         switch (val) {
 310         case DDI_CLK_SEL_NONE:
 311                 return 0;
 312         case DDI_CLK_SEL_TBT_162:
 313                 return 162000;
 314         case DDI_CLK_SEL_TBT_270:
 315                 return 270000;
 316         case DDI_CLK_SEL_TBT_540:
 317                 return 540000;
 318         case DDI_CLK_SEL_TBT_810:
 319                 return 810000;
 320         default:
 321                 MISSING_CASE(val);
 322                 return 0;
 323         }
 324 }
 325
 326 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
 327 {
 328         int dotclock;
 329
 330         if (intel_crtc_has_dp_encoder(pipe_config))
 331                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
 332                                                     &pipe_config->dp_m_n);
 333         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
 334                 dotclock = pipe_config->port_clock * 24 / pipe_config->pipe_bpp;
 335         else
 336                 dotclock = pipe_config->port_clock;
 337
 338         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
 339             !intel_crtc_has_dp_encoder(pipe_config))
 340                 dotclock *= 2;
 341
 342         if (pipe_config->pixel_multiplier)
 343                 dotclock /= pipe_config->pixel_multiplier;
 344
 345         return dotclock;
 346 }
 347
 348 static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
 349 {
 350         /* CRT dotclock is determined via other means */
 351         if (pipe_config->has_pch_encoder)
 352                 return;
 353
 354         pipe_config->hw.adjusted_mode.crtc_clock =
 355                 intel_crtc_dotclock(pipe_config);
 356 }
 357
 358 void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state,
 359                           const struct drm_connector_state *conn_state)
 360 {
 361         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 362         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 363         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 364         u32 temp;
 365
 366         if (!intel_crtc_has_dp_encoder(crtc_state))
 367                 return;
 368
 369         drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder));
 370
 371         temp = DP_MSA_MISC_SYNC_CLOCK;
 372
 373         switch (crtc_state->pipe_bpp) {
 374         case 18:
 375                 temp |= DP_MSA_MISC_6_BPC;
 376                 break;
 377         case 24:
 378                 temp |= DP_MSA_MISC_8_BPC;
 379                 break;
 380         case 30:
 381                 temp |= DP_MSA_MISC_10_BPC;
 382                 break;
 383         case 36:
 384                 temp |= DP_MSA_MISC_12_BPC;
 385                 break;
 386         default:
 387                 MISSING_CASE(crtc_state->pipe_bpp);
 388                 break;
 389         }
 390
 391         /* nonsense combination */
 392         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
 393                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
 394
 395         if (crtc_state->limited_color_range)
 396                 temp |= DP_MSA_MISC_COLOR_CEA_RGB;
 397
 398         /*
 399          * As per DP 1.2 spec section 2.3.4.3 while sending
 400          * YCBCR 444 signals we should program MSA MISC1/0 fields with
 401          * colorspace information.
 402          */
 403         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
 404                 temp |= DP_MSA_MISC_COLOR_YCBCR_444_BT709;
 405
 406         /*
 407          * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication
 408          * of Color Encoding Format and Content Color Gamut] while sending
 409          * YCBCR 420, HDR BT.2020 signals we should program MSA MISC1 fields
 410          * which indicate VSC SDP for the Pixel Encoding/Colorimetry Format.
 411          */
 412         if (intel_dp_needs_vsc_sdp(crtc_state, conn_state))
 413                 temp |= DP_MSA_MISC_COLOR_VSC_SDP;
 414
 415         intel_de_write(dev_priv, TRANS_MSA_MISC(cpu_transcoder), temp);
 416 }
 417
 418 static u32 bdw_trans_port_sync_master_select(enum transcoder master_transcoder)
 419 {
 420         if (master_transcoder == TRANSCODER_EDP)
 421                 return 0;
 422         else
 423                 return master_transcoder + 1;
 424 }
 425
 426 static void
 427 intel_ddi_config_transcoder_dp2(struct intel_encoder *encoder,
 428                                 const struct intel_crtc_state *crtc_state)
 429 {
 430         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 431         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 432         u32 val = 0;
 433
 434         if (intel_dp_is_uhbr(crtc_state))
 435                 val = TRANS_DP2_128B132B_CHANNEL_CODING;
 436
 437         intel_de_write(i915, TRANS_DP2_CTL(cpu_transcoder), val);
 438 }
 439
 440 /*
 441  * Returns the TRANS_DDI_FUNC_CTL value based on CRTC state.
 442  *
 443  * Only intended to be used by intel_ddi_enable_transcoder_func() and
 444  * intel_ddi_config_transcoder_func().
 445  */
 446 static u32
 447 intel_ddi_transcoder_func_reg_val_get(struct intel_encoder *encoder,
 448                                       const struct intel_crtc_state *crtc_state)
 449 {
 450         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 451         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 452         enum pipe pipe = crtc->pipe;
 453         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 454         enum port port = encoder->port;
 455         u32 temp;
 456
 457         /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
 458         temp = TRANS_DDI_FUNC_ENABLE;
 459         if (DISPLAY_VER(dev_priv) >= 12)
 460                 temp |= TGL_TRANS_DDI_SELECT_PORT(port);
 461         else
 462                 temp |= TRANS_DDI_SELECT_PORT(port);
 463
 464         switch (crtc_state->pipe_bpp) {
 465         default:
 466                 MISSING_CASE(crtc_state->pipe_bpp);
 467                 fallthrough;
 468         case 18:
 469                 temp |= TRANS_DDI_BPC_6;
 470                 break;
 471         case 24:
 472                 temp |= TRANS_DDI_BPC_8;
 473                 break;
 474         case 30:
 475                 temp |= TRANS_DDI_BPC_10;
 476                 break;
 477         case 36:
 478                 temp |= TRANS_DDI_BPC_12;
 479                 break;
 480         }
 481
 482         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
 483                 temp |= TRANS_DDI_PVSYNC;
 484         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
 485                 temp |= TRANS_DDI_PHSYNC;
 486
 487         if (cpu_transcoder == TRANSCODER_EDP) {
 488                 switch (pipe) {
 489                 default:
 490                         MISSING_CASE(pipe);
 491                         fallthrough;
 492                 case PIPE_A:
 493                         /* On Haswell, can only use the always-on power well for
 494                          * eDP when not using the panel fitter, and when not
 495                          * using motion blur mitigation (which we don't
 496                          * support). */
 497                         if (crtc_state->pch_pfit.force_thru)
 498                                 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
 499                         else
 500                                 temp |= TRANS_DDI_EDP_INPUT_A_ON;
 501                         break;
 502                 case PIPE_B:
 503                         temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
 504                         break;
 505                 case PIPE_C:
 506                         temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 507                         break;
 508                 }
 509         }
 510
 511         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
 512                 if (crtc_state->has_hdmi_sink)
 513                         temp |= TRANS_DDI_MODE_SELECT_HDMI;
 514                 else
 515                         temp |= TRANS_DDI_MODE_SELECT_DVI;
 516
 517                 if (crtc_state->hdmi_scrambling)
 518                         temp |= TRANS_DDI_HDMI_SCRAMBLING;
 519                 if (crtc_state->hdmi_high_tmds_clock_ratio)
 520                         temp |= TRANS_DDI_HIGH_TMDS_CHAR_RATE;
 521         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
 522                 temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
 523                 temp |= (crtc_state->fdi_lanes - 1) << 1;
 524         } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
 525                 if (intel_dp_is_uhbr(crtc_state))
 526                         temp |= TRANS_DDI_MODE_SELECT_FDI_OR_128B132B;
 527                 else
 528                         temp |= TRANS_DDI_MODE_SELECT_DP_MST;
 529                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
 530
 531                 if (DISPLAY_VER(dev_priv) >= 12) {
 532                         enum transcoder master;
 533
 534                         master = crtc_state->mst_master_transcoder;
 535                         drm_WARN_ON(&dev_priv->drm,
 536                                     master == INVALID_TRANSCODER);
 537                         temp |= TRANS_DDI_MST_TRANSPORT_SELECT(master);
 538                 }
 539         } else {
 540                 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
 541                 temp |= DDI_PORT_WIDTH(crtc_state->lane_count);
 542         }
 543
 544         if (IS_DISPLAY_VER(dev_priv, 8, 10) &&
 545             crtc_state->master_transcoder != INVALID_TRANSCODER) {
 546                 u8 master_select =
 547                         bdw_trans_port_sync_master_select(crtc_state->master_transcoder);
 548
 549                 temp |= TRANS_DDI_PORT_SYNC_ENABLE |
 550                         TRANS_DDI_PORT_SYNC_MASTER_SELECT(master_select);
 551         }
 552
 553         return temp;
 554 }
 555
 556 void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder,
 557                                       const struct intel_crtc_state *crtc_state)
 558 {
 559         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 560         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 561         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 562
 563         if (DISPLAY_VER(dev_priv) >= 11) {
 564                 enum transcoder master_transcoder = crtc_state->master_transcoder;
 565                 u32 ctl2 = 0;
 566
 567                 if (master_transcoder != INVALID_TRANSCODER) {
 568                         u8 master_select =
 569                                 bdw_trans_port_sync_master_select(master_transcoder);
 570
 571                         ctl2 |= PORT_SYNC_MODE_ENABLE |
 572                                 PORT_SYNC_MODE_MASTER_SELECT(master_select);
 573                 }
 574
 575                 intel_de_write(dev_priv,
 576                                TRANS_DDI_FUNC_CTL2(cpu_transcoder), ctl2);
 577         }
 578
 579         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder),
 580                        intel_ddi_transcoder_func_reg_val_get(encoder,
 581                                                              crtc_state));
 582 }
 583
 584 /*
 585  * Same as intel_ddi_enable_transcoder_func(), but it does not set the enable
 586  * bit.
 587  */
 588 static void
 589 intel_ddi_config_transcoder_func(struct intel_encoder *encoder,
 590                                  const struct intel_crtc_state *crtc_state)
 591 {
 592         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 593         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 594         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 595         u32 ctl;
 596
 597         ctl = intel_ddi_transcoder_func_reg_val_get(encoder, crtc_state);
 598         ctl &= ~TRANS_DDI_FUNC_ENABLE;
 599         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
 600 }
 601
 602 void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state)
 603 {
 604         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 605         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 606         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 607         u32 ctl;
 608
 609         if (DISPLAY_VER(dev_priv) >= 11)
 610                 intel_de_write(dev_priv,
 611                                TRANS_DDI_FUNC_CTL2(cpu_transcoder), 0);
 612
 613         ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
 614
 615         drm_WARN_ON(crtc->base.dev, ctl & TRANS_DDI_HDCP_SIGNALLING);
 616
 617         ctl &= ~TRANS_DDI_FUNC_ENABLE;
 618
 619         if (IS_DISPLAY_VER(dev_priv, 8, 10))
 620                 ctl &= ~(TRANS_DDI_PORT_SYNC_ENABLE |
 621                          TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK);
 622
 623         if (DISPLAY_VER(dev_priv) >= 12) {
 624                 if (!intel_dp_mst_is_master_trans(crtc_state)) {
 625                         ctl &= ~(TGL_TRANS_DDI_PORT_MASK |
 626                                  TRANS_DDI_MODE_SELECT_MASK);
 627                 }
 628         } else {
 629                 ctl &= ~(TRANS_DDI_PORT_MASK | TRANS_DDI_MODE_SELECT_MASK);
 630         }
 631
 632         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), ctl);
 633
 634         if (dev_priv->quirks & QUIRK_INCREASE_DDI_DISABLED_TIME &&
 635             intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
 636                 drm_dbg_kms(&dev_priv->drm,
 637                             "Quirk Increase DDI disabled time\n");
 638                 /* Quirk time at 100ms for reliable operation */
 639                 msleep(100);
 640         }
 641 }
 642
 643 int intel_ddi_toggle_hdcp_bits(struct intel_encoder *intel_encoder,
 644                                enum transcoder cpu_transcoder,
 645                                bool enable, u32 hdcp_mask)
 646 {
 647         struct drm_device *dev = intel_encoder->base.dev;
 648         struct drm_i915_private *dev_priv = to_i915(dev);
 649         intel_wakeref_t wakeref;
 650         int ret = 0;
 651         u32 tmp;
 652
 653         wakeref = intel_display_power_get_if_enabled(dev_priv,
 654                                                      intel_encoder->power_domain);
 655         if (drm_WARN_ON(dev, !wakeref))
 656                 return -ENXIO;
 657
 658         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
 659         if (enable)
 660                 tmp |= hdcp_mask;
 661         else
 662                 tmp &= ~hdcp_mask;
 663         intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder), tmp);
 664         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
 665         return ret;
 666 }
 667
 668 bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
 669 {
 670         struct drm_device *dev = intel_connector->base.dev;
 671         struct drm_i915_private *dev_priv = to_i915(dev);
 672         struct intel_encoder *encoder = intel_attached_encoder(intel_connector);
 673         int type = intel_connector->base.connector_type;
 674         enum port port = encoder->port;
 675         enum transcoder cpu_transcoder;
 676         intel_wakeref_t wakeref;
 677         enum pipe pipe = 0;
 678         u32 tmp;
 679         bool ret;
 680
 681         wakeref = intel_display_power_get_if_enabled(dev_priv,
 682                                                      encoder->power_domain);
 683         if (!wakeref)
 684                 return false;
 685
 686         if (!encoder->get_hw_state(encoder, &pipe)) {
 687                 ret = false;
 688                 goto out;
 689         }
 690
 691         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
 692                 cpu_transcoder = TRANSCODER_EDP;
 693         else
 694                 cpu_transcoder = (enum transcoder) pipe;
 695
 696         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
 697
 698         switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
 699         case TRANS_DDI_MODE_SELECT_HDMI:
 700         case TRANS_DDI_MODE_SELECT_DVI:
 701                 ret = type == DRM_MODE_CONNECTOR_HDMIA;
 702                 break;
 703
 704         case TRANS_DDI_MODE_SELECT_DP_SST:
 705                 ret = type == DRM_MODE_CONNECTOR_eDP ||
 706                       type == DRM_MODE_CONNECTOR_DisplayPort;
 707                 break;
 708
 709         case TRANS_DDI_MODE_SELECT_DP_MST:
 710                 /* if the transcoder is in MST state then
 711                  * connector isn't connected */
 712                 ret = false;
 713                 break;
 714
 715         case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
 716                 if (HAS_DP20(dev_priv))
 717                         /* 128b/132b */
 718                         ret = false;
 719                 else
 720                         /* FDI */
 721                         ret = type == DRM_MODE_CONNECTOR_VGA;
 722                 break;
 723
 724         default:
 725                 ret = false;
 726                 break;
 727         }
 728
 729 out:
 730         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 731
 732         return ret;
 733 }
 734
 735 static void intel_ddi_get_encoder_pipes(struct intel_encoder *encoder,
 736                                         u8 *pipe_mask, bool *is_dp_mst)
 737 {
 738         struct drm_device *dev = encoder->base.dev;
 739         struct drm_i915_private *dev_priv = to_i915(dev);
 740         enum port port = encoder->port;
 741         intel_wakeref_t wakeref;
 742         enum pipe p;
 743         u32 tmp;
 744         u8 mst_pipe_mask;
 745
 746         *pipe_mask = 0;
 747         *is_dp_mst = false;
 748
 749         wakeref = intel_display_power_get_if_enabled(dev_priv,
 750                                                      encoder->power_domain);
 751         if (!wakeref)
 752                 return;
 753
 754         tmp = intel_de_read(dev_priv, DDI_BUF_CTL(port));
 755         if (!(tmp & DDI_BUF_CTL_ENABLE))
 756                 goto out;
 757
 758         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A) {
 759                 tmp = intel_de_read(dev_priv,
 760                                     TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
 761
 762                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
 763                 default:
 764                         MISSING_CASE(tmp & TRANS_DDI_EDP_INPUT_MASK);
 765                         fallthrough;
 766                 case TRANS_DDI_EDP_INPUT_A_ON:
 767                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
 768                         *pipe_mask = BIT(PIPE_A);
 769                         break;
 770                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
 771                         *pipe_mask = BIT(PIPE_B);
 772                         break;
 773                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
 774                         *pipe_mask = BIT(PIPE_C);
 775                         break;
 776                 }
 777
 778                 goto out;
 779         }
 780
 781         mst_pipe_mask = 0;
 782         for_each_pipe(dev_priv, p) {
 783                 enum transcoder cpu_transcoder = (enum transcoder)p;
 784                 unsigned int port_mask, ddi_select;
 785                 intel_wakeref_t trans_wakeref;
 786
 787                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
 788                                                                    POWER_DOMAIN_TRANSCODER(cpu_transcoder));
 789                 if (!trans_wakeref)
 790                         continue;
 791
 792                 if (DISPLAY_VER(dev_priv) >= 12) {
 793                         port_mask = TGL_TRANS_DDI_PORT_MASK;
 794                         ddi_select = TGL_TRANS_DDI_SELECT_PORT(port);
 795                 } else {
 796                         port_mask = TRANS_DDI_PORT_MASK;
 797                         ddi_select = TRANS_DDI_SELECT_PORT(port);
 798                 }
 799
 800                 tmp = intel_de_read(dev_priv,
 801                                     TRANS_DDI_FUNC_CTL(cpu_transcoder));
 802                 intel_display_power_put(dev_priv, POWER_DOMAIN_TRANSCODER(cpu_transcoder),
 803                                         trans_wakeref);
 804
 805                 if ((tmp & port_mask) != ddi_select)
 806                         continue;
 807
 808                 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST ||
 809                     (HAS_DP20(dev_priv) &&
 810                      (tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_FDI_OR_128B132B))
 811                         mst_pipe_mask |= BIT(p);
 812
 813                 *pipe_mask |= BIT(p);
 814         }
 815
 816         if (!*pipe_mask)
 817                 drm_dbg_kms(&dev_priv->drm,
 818                             "No pipe for [ENCODER:%d:%s] found\n",
 819                             encoder->base.base.id, encoder->base.name);
 820
 821         if (!mst_pipe_mask && hweight8(*pipe_mask) > 1) {
 822                 drm_dbg_kms(&dev_priv->drm,
 823                             "Multiple pipes for [ENCODER:%d:%s] (pipe_mask %02x)\n",
 824                             encoder->base.base.id, encoder->base.name,
 825                             *pipe_mask);
 826                 *pipe_mask = BIT(ffs(*pipe_mask) - 1);
 827         }
 828
 829         if (mst_pipe_mask && mst_pipe_mask != *pipe_mask)
 830                 drm_dbg_kms(&dev_priv->drm,
 831                             "Conflicting MST and non-MST state for [ENCODER:%d:%s] (pipe_mask %02x mst_pipe_mask %02x)\n",
 832                             encoder->base.base.id, encoder->base.name,
 833                             *pipe_mask, mst_pipe_mask);
 834         else
 835                 *is_dp_mst = mst_pipe_mask;
 836
 837 out:
 838         if (*pipe_mask && (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))) {
 839                 tmp = intel_de_read(dev_priv, BXT_PHY_CTL(port));
 840                 if ((tmp & (BXT_PHY_CMNLANE_POWERDOWN_ACK |
 841                             BXT_PHY_LANE_POWERDOWN_ACK |
 842                             BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
 843                         drm_err(&dev_priv->drm,
 844                                 "[ENCODER:%d:%s] enabled but PHY powered down? (PHY_CTL %08x)\n",
 845                                 encoder->base.base.id, encoder->base.name, tmp);
 846         }
 847
 848         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 849 }
 850
 851 bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
 852                             enum pipe *pipe)
 853 {
 854         u8 pipe_mask;
 855         bool is_mst;
 856
 857         intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
 858
 859         if (is_mst || !pipe_mask)
 860                 return false;
 861
 862         *pipe = ffs(pipe_mask) - 1;
 863
 864         return true;
 865 }
 866
 867 static enum intel_display_power_domain
 868 intel_ddi_main_link_aux_domain(struct intel_digital_port *dig_port)
 869 {
 870         /* ICL+ HW requires corresponding AUX IOs to be powered up for PSR with
 871          * DC states enabled at the same time, while for driver initiated AUX
 872          * transfers we need the same AUX IOs to be powered but with DC states
 873          * disabled. Accordingly use the AUX power domain here which leaves DC
 874          * states enabled.
 875          * However, for non-A AUX ports the corresponding non-EDP transcoders
 876          * would have already enabled power well 2 and DC_OFF. This means we can
 877          * acquire a wider POWER_DOMAIN_AUX_{B,C,D,F} reference instead of a
 878          * specific AUX_IO reference without powering up any extra wells.
 879          * Note that PSR is enabled only on Port A even though this function
 880          * returns the correct domain for other ports too.
 881          */
 882         return dig_port->aux_ch == AUX_CH_A ? POWER_DOMAIN_AUX_IO_A :
 883                                               intel_aux_power_domain(dig_port);
 884 }
 885
 886 static void intel_ddi_get_power_domains(struct intel_encoder *encoder,
 887                                         struct intel_crtc_state *crtc_state)
 888 {
 889         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 890         struct intel_digital_port *dig_port;
 891         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 892
 893         /*
 894          * TODO: Add support for MST encoders. Atm, the following should never
 895          * happen since fake-MST encoders don't set their get_power_domains()
 896          * hook.
 897          */
 898         if (drm_WARN_ON(&dev_priv->drm,
 899                         intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)))
 900                 return;
 901
 902         dig_port = enc_to_dig_port(encoder);
 903
 904         if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
 905                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
 906                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
 907                                                                    dig_port->ddi_io_power_domain);
 908         }
 909
 910         /*
 911          * AUX power is only needed for (e)DP mode, and for HDMI mode on TC
 912          * ports.
 913          */
 914         if (intel_crtc_has_dp_encoder(crtc_state) ||
 915             intel_phy_is_tc(dev_priv, phy)) {
 916                 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
 917                 dig_port->aux_wakeref =
 918                         intel_display_power_get(dev_priv,
 919                                                 intel_ddi_main_link_aux_domain(dig_port));
 920         }
 921 }
 922
 923 void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder,
 924                                  const struct intel_crtc_state *crtc_state)
 925 {
 926         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 927         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 928         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 929         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
 930         u32 val;
 931
 932         if (cpu_transcoder != TRANSCODER_EDP) {
 933                 if (DISPLAY_VER(dev_priv) >= 13)
 934                         val = TGL_TRANS_CLK_SEL_PORT(phy);
 935                 else if (DISPLAY_VER(dev_priv) >= 12)
 936                         val = TGL_TRANS_CLK_SEL_PORT(encoder->port);
 937                 else
 938                         val = TRANS_CLK_SEL_PORT(encoder->port);
 939
 940                 intel_de_write(dev_priv, TRANS_CLK_SEL(cpu_transcoder), val);
 941         }
 942 }
 943
 944 void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state)
 945 {
 946         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 947         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 948
 949         if (cpu_transcoder != TRANSCODER_EDP) {
 950                 if (DISPLAY_VER(dev_priv) >= 12)
 951                         intel_de_write(dev_priv,
 952                                        TRANS_CLK_SEL(cpu_transcoder),
 953                                        TGL_TRANS_CLK_SEL_DISABLED);
 954                 else
 955                         intel_de_write(dev_priv,
 956                                        TRANS_CLK_SEL(cpu_transcoder),
 957                                        TRANS_CLK_SEL_DISABLED);
 958         }
 959 }
 960
 961 static void _skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
 962                                 enum port port, u8 iboost)
 963 {
 964         u32 tmp;
 965
 966         tmp = intel_de_read(dev_priv, DISPIO_CR_TX_BMU_CR0);
 967         tmp &= ~(BALANCE_LEG_MASK(port) | BALANCE_LEG_DISABLE(port));
 968         if (iboost)
 969                 tmp |= iboost << BALANCE_LEG_SHIFT(port);
 970         else
 971                 tmp |= BALANCE_LEG_DISABLE(port);
 972         intel_de_write(dev_priv, DISPIO_CR_TX_BMU_CR0, tmp);
 973 }
 974
 975 static void skl_ddi_set_iboost(struct intel_encoder *encoder,
 976                                const struct intel_crtc_state *crtc_state,
 977                                int level)
 978 {
 979         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 980         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 981         u8 iboost;
 982
 983         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 984                 iboost = intel_bios_encoder_hdmi_boost_level(encoder->devdata);
 985         else
 986                 iboost = intel_bios_encoder_dp_boost_level(encoder->devdata);
 987
 988         if (iboost == 0) {
 989                 const struct intel_ddi_buf_trans *trans;
 990                 int n_entries;
 991
 992                 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
 993                 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
 994                         return;
 995
 996                 iboost = trans->entries[level].hsw.i_boost;
 997         }
 998
 999         /* Make sure that the requested I_boost is valid */
1000         if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1001                 drm_err(&dev_priv->drm, "Invalid I_boost value %u\n", iboost);
1002                 return;
1003         }
1004
1005         _skl_ddi_set_iboost(dev_priv, encoder->port, iboost);
1006
1007         if (encoder->port == PORT_A && dig_port->max_lanes == 4)
1008                 _skl_ddi_set_iboost(dev_priv, PORT_E, iboost);
1009 }
1010
1011 static u8 intel_ddi_dp_voltage_max(struct intel_dp *intel_dp,
1012                                    const struct intel_crtc_state *crtc_state)
1013 {
1014         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
1015         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1016         int n_entries;
1017
1018         encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1019
1020         if (drm_WARN_ON(&dev_priv->drm, n_entries < 1))
1021                 n_entries = 1;
1022         if (drm_WARN_ON(&dev_priv->drm,
1023                         n_entries > ARRAY_SIZE(index_to_dp_signal_levels)))
1024                 n_entries = ARRAY_SIZE(index_to_dp_signal_levels);
1025
1026         return index_to_dp_signal_levels[n_entries - 1] &
1027                 DP_TRAIN_VOLTAGE_SWING_MASK;
1028 }
1029
1030 /*
1031  * We assume that the full set of pre-emphasis values can be
1032  * used on all DDI platforms. Should that change we need to
1033  * rethink this code.
1034  */
1035 static u8 intel_ddi_dp_preemph_max(struct intel_dp *intel_dp)
1036 {
1037         return DP_TRAIN_PRE_EMPH_LEVEL_3;
1038 }
1039
1040 static u32 icl_combo_phy_loadgen_select(const struct intel_crtc_state *crtc_state,
1041                                         int lane)
1042 {
1043         if (crtc_state->port_clock > 600000)
1044                 return 0;
1045
1046         if (crtc_state->lane_count == 4)
1047                 return lane >= 1 ? LOADGEN_SELECT : 0;
1048         else
1049                 return lane == 1 || lane == 2 ? LOADGEN_SELECT : 0;
1050 }
1051
1052 static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
1053                                          const struct intel_crtc_state *crtc_state)
1054 {
1055         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1056         const struct intel_ddi_buf_trans *trans;
1057         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1058         int n_entries, ln;
1059         u32 val;
1060
1061         trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1062         if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
1063                 return;
1064
1065         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP)) {
1066                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1067
1068                 val = EDP4K2K_MODE_OVRD_EN | EDP4K2K_MODE_OVRD_OPTIMIZED;
1069                 intel_dp->hobl_active = is_hobl_buf_trans(trans);
1070                 intel_de_rmw(dev_priv, ICL_PORT_CL_DW10(phy), val,
1071                              intel_dp->hobl_active ? val : 0);
1072         }
1073
1074         /* Set PORT_TX_DW5 */
1075         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
1076         val &= ~(SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK |
1077                   TAP2_DISABLE | TAP3_DISABLE);
1078         val |= SCALING_MODE_SEL(0x2);
1079         val |= RTERM_SELECT(0x6);
1080         val |= TAP3_DISABLE;
1081         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1082
1083         /* Program PORT_TX_DW2 */
1084         for (ln = 0; ln < 4; ln++) {
1085                 int level = intel_ddi_level(encoder, crtc_state, ln);
1086
1087                 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_LN(ln, phy),
1088                              SWING_SEL_UPPER_MASK | SWING_SEL_LOWER_MASK | RCOMP_SCALAR_MASK,
1089                              SWING_SEL_UPPER(trans->entries[level].icl.dw2_swing_sel) |
1090                              SWING_SEL_LOWER(trans->entries[level].icl.dw2_swing_sel) |
1091                              RCOMP_SCALAR(0x98));
1092         }
1093
1094         /* Program PORT_TX_DW4 */
1095         /* We cannot write to GRP. It would overwrite individual loadgen. */
1096         for (ln = 0; ln < 4; ln++) {
1097                 int level = intel_ddi_level(encoder, crtc_state, ln);
1098
1099                 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),
1100                              POST_CURSOR_1_MASK | POST_CURSOR_2_MASK | CURSOR_COEFF_MASK,
1101                              POST_CURSOR_1(trans->entries[level].icl.dw4_post_cursor_1) |
1102                              POST_CURSOR_2(trans->entries[level].icl.dw4_post_cursor_2) |
1103                              CURSOR_COEFF(trans->entries[level].icl.dw4_cursor_coeff));
1104         }
1105
1106         /* Program PORT_TX_DW7 */
1107         for (ln = 0; ln < 4; ln++) {
1108                 int level = intel_ddi_level(encoder, crtc_state, ln);
1109
1110                 intel_de_rmw(dev_priv, ICL_PORT_TX_DW7_LN(ln, phy),
1111                              N_SCALAR_MASK,
1112                              N_SCALAR(trans->entries[level].icl.dw7_n_scalar));
1113         }
1114 }
1115
1116 static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
1117                                             const struct intel_crtc_state *crtc_state)
1118 {
1119         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1120         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
1121         u32 val;
1122         int ln;
1123
1124         /*
1125          * 1. If port type is eDP or DP,
1126          * set PORT_PCS_DW1 cmnkeeper_enable to 1b,
1127          * else clear to 0b.
1128          */
1129         val = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
1130         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1131                 val &= ~COMMON_KEEPER_EN;
1132         else
1133                 val |= COMMON_KEEPER_EN;
1134         intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), val);
1135
1136         /* 2. Program loadgen select */
1137         /*
1138          * Program PORT_TX_DW4 depending on Bit rate and used lanes
1139          * <= 6 GHz and 4 lanes (LN0=0, LN1=1, LN2=1, LN3=1)
1140          * <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
1141          * > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
1142          */
1143         for (ln = 0; ln < 4; ln++) {
1144                 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy),
1145                              LOADGEN_SELECT,
1146                              icl_combo_phy_loadgen_select(crtc_state, ln));
1147         }
1148
1149         /* 3. Set PORT_CL_DW5 SUS Clock Config to 11b */
1150         intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy),
1151                      0, SUS_CLOCK_CONFIG);
1152
1153         /* 4. Clear training enable to change swing values */
1154         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
1155         val &= ~TX_TRAINING_EN;
1156         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1157
1158         /* 5. Program swing and de-emphasis */
1159         icl_ddi_combo_vswing_program(encoder, crtc_state);
1160
1161         /* 6. Set training enable to trigger update */
1162         val = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
1163         val |= TX_TRAINING_EN;
1164         intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), val);
1165 }
1166
1167 static void icl_mg_phy_set_signal_levels(struct intel_encoder *encoder,
1168                                          const struct intel_crtc_state *crtc_state)
1169 {
1170         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1171         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
1172         const struct intel_ddi_buf_trans *trans;
1173         int n_entries, ln;
1174
1175         if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
1176                 return;
1177
1178         trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1179         if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
1180                 return;
1181
1182         for (ln = 0; ln < 2; ln++) {
1183                 intel_de_rmw(dev_priv, MG_TX1_LINK_PARAMS(ln, tc_port),
1184                              CRI_USE_FS32, 0);
1185                 intel_de_rmw(dev_priv, MG_TX2_LINK_PARAMS(ln, tc_port),
1186                              CRI_USE_FS32, 0);
1187         }
1188
1189         /* Program MG_TX_SWINGCTRL with values from vswing table */
1190         for (ln = 0; ln < 2; ln++) {
1191                 int level;
1192
1193                 level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1194
1195                 intel_de_rmw(dev_priv, MG_TX1_SWINGCTRL(ln, tc_port),
1196                              CRI_TXDEEMPH_OVERRIDE_17_12_MASK,
1197                              CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));
1198
1199                 level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1200
1201                 intel_de_rmw(dev_priv, MG_TX2_SWINGCTRL(ln, tc_port),
1202                              CRI_TXDEEMPH_OVERRIDE_17_12_MASK,
1203                              CRI_TXDEEMPH_OVERRIDE_17_12(trans->entries[level].mg.cri_txdeemph_override_17_12));
1204         }
1205
1206         /* Program MG_TX_DRVCTRL with values from vswing table */
1207         for (ln = 0; ln < 2; ln++) {
1208                 int level;
1209
1210                 level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1211
1212                 intel_de_rmw(dev_priv, MG_TX1_DRVCTRL(ln, tc_port),
1213                              CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1214                              CRI_TXDEEMPH_OVERRIDE_5_0_MASK,
1215                              CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |
1216                              CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |
1217                              CRI_TXDEEMPH_OVERRIDE_EN);
1218
1219                 level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1220
1221                 intel_de_rmw(dev_priv, MG_TX2_DRVCTRL(ln, tc_port),
1222                              CRI_TXDEEMPH_OVERRIDE_11_6_MASK |
1223                              CRI_TXDEEMPH_OVERRIDE_5_0_MASK,
1224                              CRI_TXDEEMPH_OVERRIDE_11_6(trans->entries[level].mg.cri_txdeemph_override_11_6) |
1225                              CRI_TXDEEMPH_OVERRIDE_5_0(trans->entries[level].mg.cri_txdeemph_override_5_0) |
1226                              CRI_TXDEEMPH_OVERRIDE_EN);
1227
1228                 /* FIXME: Program CRI_LOADGEN_SEL after the spec is updated */
1229         }
1230
1231         /*
1232          * Program MG_CLKHUB<LN, port being used> with value from frequency table
1233          * In case of Legacy mode on MG PHY, both TX1 and TX2 enabled so use the
1234          * values from table for which TX1 and TX2 enabled.
1235          */
1236         for (ln = 0; ln < 2; ln++) {
1237                 intel_de_rmw(dev_priv, MG_CLKHUB(ln, tc_port),
1238                              CFG_LOW_RATE_LKREN_EN,
1239                              crtc_state->port_clock < 300000 ? CFG_LOW_RATE_LKREN_EN : 0);
1240         }
1241
1242         /* Program the MG_TX_DCC<LN, port being used> based on the link frequency */
1243         for (ln = 0; ln < 2; ln++) {
1244                 intel_de_rmw(dev_priv, MG_TX1_DCC(ln, tc_port),
1245                              CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK |
1246                              CFG_AMI_CK_DIV_OVERRIDE_EN,
1247                              crtc_state->port_clock > 500000 ?
1248                              CFG_AMI_CK_DIV_OVERRIDE_VAL(1) |
1249                              CFG_AMI_CK_DIV_OVERRIDE_EN : 0);
1250
1251                 intel_de_rmw(dev_priv, MG_TX2_DCC(ln, tc_port),
1252                              CFG_AMI_CK_DIV_OVERRIDE_VAL_MASK |
1253                              CFG_AMI_CK_DIV_OVERRIDE_EN,
1254                              crtc_state->port_clock > 500000 ?
1255                              CFG_AMI_CK_DIV_OVERRIDE_VAL(1) |
1256                              CFG_AMI_CK_DIV_OVERRIDE_EN : 0);
1257         }
1258
1259         /* Program MG_TX_PISO_READLOAD with values from vswing table */
1260         for (ln = 0; ln < 2; ln++) {
1261                 intel_de_rmw(dev_priv, MG_TX1_PISO_READLOAD(ln, tc_port),
1262                              0, CRI_CALCINIT);
1263                 intel_de_rmw(dev_priv, MG_TX2_PISO_READLOAD(ln, tc_port),
1264                              0, CRI_CALCINIT);
1265         }
1266 }
1267
1268 static void tgl_dkl_phy_set_signal_levels(struct intel_encoder *encoder,
1269                                           const struct intel_crtc_state *crtc_state)
1270 {
1271         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1272         enum tc_port tc_port = intel_port_to_tc(dev_priv, encoder->port);
1273         const struct intel_ddi_buf_trans *trans;
1274         int n_entries, ln;
1275
1276         if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))
1277                 return;
1278
1279         trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1280         if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
1281                 return;
1282
1283         for (ln = 0; ln < 2; ln++) {
1284                 int level;
1285
1286                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
1287                                HIP_INDEX_VAL(tc_port, ln));
1288
1289                 intel_de_write(dev_priv, DKL_TX_PMD_LANE_SUS(tc_port), 0);
1290
1291                 level = intel_ddi_level(encoder, crtc_state, 2*ln+0);
1292
1293                 intel_de_rmw(dev_priv, DKL_TX_DPCNTL0(tc_port),
1294                              DKL_TX_PRESHOOT_COEFF_MASK |
1295                              DKL_TX_DE_EMPAHSIS_COEFF_MASK |
1296                              DKL_TX_VSWING_CONTROL_MASK,
1297                              DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
1298                              DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
1299                              DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
1300
1301                 level = intel_ddi_level(encoder, crtc_state, 2*ln+1);
1302
1303                 intel_de_rmw(dev_priv, DKL_TX_DPCNTL1(tc_port),
1304                              DKL_TX_PRESHOOT_COEFF_MASK |
1305                              DKL_TX_DE_EMPAHSIS_COEFF_MASK |
1306                              DKL_TX_VSWING_CONTROL_MASK,
1307                              DKL_TX_PRESHOOT_COEFF(trans->entries[level].dkl.preshoot) |
1308                              DKL_TX_DE_EMPHASIS_COEFF(trans->entries[level].dkl.de_emphasis) |
1309                              DKL_TX_VSWING_CONTROL(trans->entries[level].dkl.vswing));
1310
1311                 intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port),
1312                              DKL_TX_DP20BITMODE, 0);
1313
1314                 if (IS_ALDERLAKE_P(dev_priv)) {
1315                         u32 val;
1316
1317                         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
1318                                 if (ln == 0) {
1319                                         val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
1320                                         val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(2);
1321                                 } else {
1322                                         val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(3);
1323                                         val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(3);
1324                                 }
1325                         } else {
1326                                 val = DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1(0);
1327                                 val |= DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2(0);
1328                         }
1329
1330                         intel_de_rmw(dev_priv, DKL_TX_DPCNTL2(tc_port),
1331                                      DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX1_MASK |
1332                                      DKL_TX_DPCNTL2_CFG_LOADGENSELECT_TX2_MASK,
1333                                      val);
1334                 }
1335         }
1336 }
1337
1338 static int translate_signal_level(struct intel_dp *intel_dp,
1339                                   u8 signal_levels)
1340 {
1341         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
1342         int i;
1343
1344         for (i = 0; i < ARRAY_SIZE(index_to_dp_signal_levels); i++) {
1345                 if (index_to_dp_signal_levels[i] == signal_levels)
1346                         return i;
1347         }
1348
1349         drm_WARN(&i915->drm, 1,
1350                  "Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1351                  signal_levels);
1352
1353         return 0;
1354 }
1355
1356 static int intel_ddi_dp_level(struct intel_dp *intel_dp,
1357                               const struct intel_crtc_state *crtc_state,
1358                               int lane)
1359 {
1360         u8 train_set = intel_dp->train_set[lane];
1361
1362         if (intel_dp_is_uhbr(crtc_state)) {
1363                 return train_set & DP_TX_FFE_PRESET_VALUE_MASK;
1364         } else {
1365                 u8 signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1366                                                 DP_TRAIN_PRE_EMPHASIS_MASK);
1367
1368                 return translate_signal_level(intel_dp, signal_levels);
1369         }
1370 }
1371
1372 int intel_ddi_level(struct intel_encoder *encoder,
1373                     const struct intel_crtc_state *crtc_state,
1374                     int lane)
1375 {
1376         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1377         const struct intel_ddi_buf_trans *trans;
1378         int level, n_entries;
1379
1380         trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
1381         if (drm_WARN_ON_ONCE(&i915->drm, !trans))
1382                 return 0;
1383
1384         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1385                 level = intel_ddi_hdmi_level(encoder, trans);
1386         else
1387                 level = intel_ddi_dp_level(enc_to_intel_dp(encoder), crtc_state,
1388                                            lane);
1389
1390         if (drm_WARN_ON_ONCE(&i915->drm, level >= n_entries))
1391                 level = n_entries - 1;
1392
1393         return level;
1394 }
1395
1396 static void
1397 hsw_set_signal_levels(struct intel_encoder *encoder,
1398                       const struct intel_crtc_state *crtc_state)
1399 {
1400         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1401         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1402         int level = intel_ddi_level(encoder, crtc_state, 0);
1403         enum port port = encoder->port;
1404         u32 signal_levels;
1405
1406         if (has_iboost(dev_priv))
1407                 skl_ddi_set_iboost(encoder, crtc_state, level);
1408
1409         /* HDMI ignores the rest */
1410         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1411                 return;
1412
1413         signal_levels = DDI_BUF_TRANS_SELECT(level);
1414
1415         drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
1416                     signal_levels);
1417
1418         intel_dp->DP &= ~DDI_BUF_EMP_MASK;
1419         intel_dp->DP |= signal_levels;
1420
1421         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
1422         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
1423 }
1424
1425 static void _icl_ddi_enable_clock(struct drm_i915_private *i915, i915_reg_t reg,
1426                                   u32 clk_sel_mask, u32 clk_sel, u32 clk_off)
1427 {
1428         mutex_lock(&i915->dpll.lock);
1429
1430         intel_de_rmw(i915, reg, clk_sel_mask, clk_sel);
1431
1432         /*
1433          * "This step and the step before must be
1434          *  done with separate register writes."
1435          */
1436         intel_de_rmw(i915, reg, clk_off, 0);
1437
1438         mutex_unlock(&i915->dpll.lock);
1439 }
1440
1441 static void _icl_ddi_disable_clock(struct drm_i915_private *i915, i915_reg_t reg,
1442                                    u32 clk_off)
1443 {
1444         mutex_lock(&i915->dpll.lock);
1445
1446         intel_de_rmw(i915, reg, 0, clk_off);
1447
1448         mutex_unlock(&i915->dpll.lock);
1449 }
1450
1451 static bool _icl_ddi_is_clock_enabled(struct drm_i915_private *i915, i915_reg_t reg,
1452                                       u32 clk_off)
1453 {
1454         return !(intel_de_read(i915, reg) & clk_off);
1455 }
1456
1457 static struct intel_shared_dpll *
1458 _icl_ddi_get_pll(struct drm_i915_private *i915, i915_reg_t reg,
1459                  u32 clk_sel_mask, u32 clk_sel_shift)
1460 {
1461         enum intel_dpll_id id;
1462
1463         id = (intel_de_read(i915, reg) & clk_sel_mask) >> clk_sel_shift;
1464
1465         return intel_get_shared_dpll_by_id(i915, id);
1466 }
1467
1468 static void adls_ddi_enable_clock(struct intel_encoder *encoder,
1469                                   const struct intel_crtc_state *crtc_state)
1470 {
1471         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1472         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1473         enum phy phy = intel_port_to_phy(i915, encoder->port);
1474
1475         if (drm_WARN_ON(&i915->drm, !pll))
1476                 return;
1477
1478         _icl_ddi_enable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
1479                               ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1480                               pll->info->id << ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy),
1481                               ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1482 }
1483
1484 static void adls_ddi_disable_clock(struct intel_encoder *encoder)
1485 {
1486         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1487         enum phy phy = intel_port_to_phy(i915, encoder->port);
1488
1489         _icl_ddi_disable_clock(i915, ADLS_DPCLKA_CFGCR(phy),
1490                                ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1491 }
1492
1493 static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder)
1494 {
1495         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1496         enum phy phy = intel_port_to_phy(i915, encoder->port);
1497
1498         return _icl_ddi_is_clock_enabled(i915, ADLS_DPCLKA_CFGCR(phy),
1499                                          ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1500 }
1501
1502 static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)
1503 {
1504         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1505         enum phy phy = intel_port_to_phy(i915, encoder->port);
1506
1507         return _icl_ddi_get_pll(i915, ADLS_DPCLKA_CFGCR(phy),
1508                                 ADLS_DPCLKA_CFGCR_DDI_CLK_SEL_MASK(phy),
1509                                 ADLS_DPCLKA_CFGCR_DDI_SHIFT(phy));
1510 }
1511
1512 static void rkl_ddi_enable_clock(struct intel_encoder *encoder,
1513                                  const struct intel_crtc_state *crtc_state)
1514 {
1515         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1516         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1517         enum phy phy = intel_port_to_phy(i915, encoder->port);
1518
1519         if (drm_WARN_ON(&i915->drm, !pll))
1520                 return;
1521
1522         _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
1523                               RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1524                               RKL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1525                               RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1526 }
1527
1528 static void rkl_ddi_disable_clock(struct intel_encoder *encoder)
1529 {
1530         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1531         enum phy phy = intel_port_to_phy(i915, encoder->port);
1532
1533         _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
1534                                RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1535 }
1536
1537 static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1538 {
1539         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1540         enum phy phy = intel_port_to_phy(i915, encoder->port);
1541
1542         return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
1543                                          RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1544 }
1545
1546 static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)
1547 {
1548         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1549         enum phy phy = intel_port_to_phy(i915, encoder->port);
1550
1551         return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
1552                                 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1553                                 RKL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1554 }
1555
1556 static void dg1_ddi_enable_clock(struct intel_encoder *encoder,
1557                                  const struct intel_crtc_state *crtc_state)
1558 {
1559         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1560         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1561         enum phy phy = intel_port_to_phy(i915, encoder->port);
1562
1563         if (drm_WARN_ON(&i915->drm, !pll))
1564                 return;
1565
1566         /*
1567          * If we fail this, something went very wrong: first 2 PLLs should be
1568          * used by first 2 phys and last 2 PLLs by last phys
1569          */
1570         if (drm_WARN_ON(&i915->drm,
1571                         (pll->info->id < DPLL_ID_DG1_DPLL2 && phy >= PHY_C) ||
1572                         (pll->info->id >= DPLL_ID_DG1_DPLL2 && phy < PHY_C)))
1573                 return;
1574
1575         _icl_ddi_enable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
1576                               DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1577                               DG1_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1578                               DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1579 }
1580
1581 static void dg1_ddi_disable_clock(struct intel_encoder *encoder)
1582 {
1583         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1584         enum phy phy = intel_port_to_phy(i915, encoder->port);
1585
1586         _icl_ddi_disable_clock(i915, DG1_DPCLKA_CFGCR0(phy),
1587                                DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1588 }
1589
1590 static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder)
1591 {
1592         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1593         enum phy phy = intel_port_to_phy(i915, encoder->port);
1594
1595         return _icl_ddi_is_clock_enabled(i915, DG1_DPCLKA_CFGCR0(phy),
1596                                          DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1597 }
1598
1599 static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)
1600 {
1601         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1602         enum phy phy = intel_port_to_phy(i915, encoder->port);
1603         enum intel_dpll_id id;
1604         u32 val;
1605
1606         val = intel_de_read(i915, DG1_DPCLKA_CFGCR0(phy));
1607         val &= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
1608         val >>= DG1_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy);
1609         id = val;
1610
1611         /*
1612          * _DG1_DPCLKA0_CFGCR0 maps between DPLL 0 and 1 with one bit for phy A
1613          * and B while _DG1_DPCLKA1_CFGCR0 maps between DPLL 2 and 3 with one
1614          * bit for phy C and D.
1615          */
1616         if (phy >= PHY_C)
1617                 id += DPLL_ID_DG1_DPLL2;
1618
1619         return intel_get_shared_dpll_by_id(i915, id);
1620 }
1621
1622 static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder,
1623                                        const struct intel_crtc_state *crtc_state)
1624 {
1625         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1626         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1627         enum phy phy = intel_port_to_phy(i915, encoder->port);
1628
1629         if (drm_WARN_ON(&i915->drm, !pll))
1630                 return;
1631
1632         _icl_ddi_enable_clock(i915, ICL_DPCLKA_CFGCR0,
1633                               ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1634                               ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy),
1635                               ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1636 }
1637
1638 static void icl_ddi_combo_disable_clock(struct intel_encoder *encoder)
1639 {
1640         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1641         enum phy phy = intel_port_to_phy(i915, encoder->port);
1642
1643         _icl_ddi_disable_clock(i915, ICL_DPCLKA_CFGCR0,
1644                                ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1645 }
1646
1647 static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder)
1648 {
1649         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1650         enum phy phy = intel_port_to_phy(i915, encoder->port);
1651
1652         return _icl_ddi_is_clock_enabled(i915, ICL_DPCLKA_CFGCR0,
1653                                          ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));
1654 }
1655
1656 struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)
1657 {
1658         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1659         enum phy phy = intel_port_to_phy(i915, encoder->port);
1660
1661         return _icl_ddi_get_pll(i915, ICL_DPCLKA_CFGCR0,
1662                                 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy),
1663                                 ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(phy));
1664 }
1665
1666 static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1667                                     const struct intel_crtc_state *crtc_state)
1668 {
1669         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1670         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1671         enum port port = encoder->port;
1672
1673         if (drm_WARN_ON(&i915->drm, !pll))
1674                 return;
1675
1676         /*
1677          * "For DDIC and DDID, program DDI_CLK_SEL to map the MG clock to the port.
1678          *  MG does not exist, but the programming is required to ungate DDIC and DDID."
1679          */
1680         intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_MG);
1681
1682         icl_ddi_combo_enable_clock(encoder, crtc_state);
1683 }
1684
1685 static void jsl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1686 {
1687         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1688         enum port port = encoder->port;
1689
1690         icl_ddi_combo_disable_clock(encoder);
1691
1692         intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1693 }
1694
1695 static bool jsl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1696 {
1697         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1698         enum port port = encoder->port;
1699         u32 tmp;
1700
1701         tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1702
1703         if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1704                 return false;
1705
1706         return icl_ddi_combo_is_clock_enabled(encoder);
1707 }
1708
1709 static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder,
1710                                     const struct intel_crtc_state *crtc_state)
1711 {
1712         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1713         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1714         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1715         enum port port = encoder->port;
1716
1717         if (drm_WARN_ON(&i915->drm, !pll))
1718                 return;
1719
1720         intel_de_write(i915, DDI_CLK_SEL(port),
1721                        icl_pll_to_ddi_clk_sel(encoder, crtc_state));
1722
1723         mutex_lock(&i915->dpll.lock);
1724
1725         intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
1726                      ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port), 0);
1727
1728         mutex_unlock(&i915->dpll.lock);
1729 }
1730
1731 static void icl_ddi_tc_disable_clock(struct intel_encoder *encoder)
1732 {
1733         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1734         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1735         enum port port = encoder->port;
1736
1737         mutex_lock(&i915->dpll.lock);
1738
1739         intel_de_rmw(i915, ICL_DPCLKA_CFGCR0,
1740                      0, ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1741
1742         mutex_unlock(&i915->dpll.lock);
1743
1744         intel_de_write(i915, DDI_CLK_SEL(port), DDI_CLK_SEL_NONE);
1745 }
1746
1747 static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder)
1748 {
1749         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1750         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1751         enum port port = encoder->port;
1752         u32 tmp;
1753
1754         tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1755
1756         if ((tmp & DDI_CLK_SEL_MASK) == DDI_CLK_SEL_NONE)
1757                 return false;
1758
1759         tmp = intel_de_read(i915, ICL_DPCLKA_CFGCR0);
1760
1761         return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));
1762 }
1763
1764 static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)
1765 {
1766         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1767         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
1768         enum port port = encoder->port;
1769         enum intel_dpll_id id;
1770         u32 tmp;
1771
1772         tmp = intel_de_read(i915, DDI_CLK_SEL(port));
1773
1774         switch (tmp & DDI_CLK_SEL_MASK) {
1775         case DDI_CLK_SEL_TBT_162:
1776         case DDI_CLK_SEL_TBT_270:
1777         case DDI_CLK_SEL_TBT_540:
1778         case DDI_CLK_SEL_TBT_810:
1779                 id = DPLL_ID_ICL_TBTPLL;
1780                 break;
1781         case DDI_CLK_SEL_MG:
1782                 id = icl_tc_port_to_pll_id(tc_port);
1783                 break;
1784         default:
1785                 MISSING_CASE(tmp);
1786                 fallthrough;
1787         case DDI_CLK_SEL_NONE:
1788                 return NULL;
1789         }
1790
1791         return intel_get_shared_dpll_by_id(i915, id);
1792 }
1793
1794 static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)
1795 {
1796         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1797         enum intel_dpll_id id;
1798
1799         switch (encoder->port) {
1800         case PORT_A:
1801                 id = DPLL_ID_SKL_DPLL0;
1802                 break;
1803         case PORT_B:
1804                 id = DPLL_ID_SKL_DPLL1;
1805                 break;
1806         case PORT_C:
1807                 id = DPLL_ID_SKL_DPLL2;
1808                 break;
1809         default:
1810                 MISSING_CASE(encoder->port);
1811                 return NULL;
1812         }
1813
1814         return intel_get_shared_dpll_by_id(i915, id);
1815 }
1816
1817 static void skl_ddi_enable_clock(struct intel_encoder *encoder,
1818                                  const struct intel_crtc_state *crtc_state)
1819 {
1820         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1821         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1822         enum port port = encoder->port;
1823
1824         if (drm_WARN_ON(&i915->drm, !pll))
1825                 return;
1826
1827         mutex_lock(&i915->dpll.lock);
1828
1829         intel_de_rmw(i915, DPLL_CTRL2,
1830                      DPLL_CTRL2_DDI_CLK_OFF(port) |
1831                      DPLL_CTRL2_DDI_CLK_SEL_MASK(port),
1832                      DPLL_CTRL2_DDI_CLK_SEL(pll->info->id, port) |
1833                      DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1834
1835         mutex_unlock(&i915->dpll.lock);
1836 }
1837
1838 static void skl_ddi_disable_clock(struct intel_encoder *encoder)
1839 {
1840         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1841         enum port port = encoder->port;
1842
1843         mutex_lock(&i915->dpll.lock);
1844
1845         intel_de_rmw(i915, DPLL_CTRL2,
1846                      0, DPLL_CTRL2_DDI_CLK_OFF(port));
1847
1848         mutex_unlock(&i915->dpll.lock);
1849 }
1850
1851 static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder)
1852 {
1853         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1854         enum port port = encoder->port;
1855
1856         /*
1857          * FIXME Not sure if the override affects both
1858          * the PLL selection and the CLK_OFF bit.
1859          */
1860         return !(intel_de_read(i915, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));
1861 }
1862
1863 static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)
1864 {
1865         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1866         enum port port = encoder->port;
1867         enum intel_dpll_id id;
1868         u32 tmp;
1869
1870         tmp = intel_de_read(i915, DPLL_CTRL2);
1871
1872         /*
1873          * FIXME Not sure if the override affects both
1874          * the PLL selection and the CLK_OFF bit.
1875          */
1876         if ((tmp & DPLL_CTRL2_DDI_SEL_OVERRIDE(port)) == 0)
1877                 return NULL;
1878
1879         id = (tmp & DPLL_CTRL2_DDI_CLK_SEL_MASK(port)) >>
1880                 DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port);
1881
1882         return intel_get_shared_dpll_by_id(i915, id);
1883 }
1884
1885 void hsw_ddi_enable_clock(struct intel_encoder *encoder,
1886                           const struct intel_crtc_state *crtc_state)
1887 {
1888         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1889         const struct intel_shared_dpll *pll = crtc_state->shared_dpll;
1890         enum port port = encoder->port;
1891
1892         if (drm_WARN_ON(&i915->drm, !pll))
1893                 return;
1894
1895         intel_de_write(i915, PORT_CLK_SEL(port), hsw_pll_to_ddi_pll_sel(pll));
1896 }
1897
1898 void hsw_ddi_disable_clock(struct intel_encoder *encoder)
1899 {
1900         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1901         enum port port = encoder->port;
1902
1903         intel_de_write(i915, PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
1904 }
1905
1906 bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder)
1907 {
1908         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1909         enum port port = encoder->port;
1910
1911         return intel_de_read(i915, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;
1912 }
1913
1914 static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)
1915 {
1916         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1917         enum port port = encoder->port;
1918         enum intel_dpll_id id;
1919         u32 tmp;
1920
1921         tmp = intel_de_read(i915, PORT_CLK_SEL(port));
1922
1923         switch (tmp & PORT_CLK_SEL_MASK) {
1924         case PORT_CLK_SEL_WRPLL1:
1925                 id = DPLL_ID_WRPLL1;
1926                 break;
1927         case PORT_CLK_SEL_WRPLL2:
1928                 id = DPLL_ID_WRPLL2;
1929                 break;
1930         case PORT_CLK_SEL_SPLL:
1931                 id = DPLL_ID_SPLL;
1932                 break;
1933         case PORT_CLK_SEL_LCPLL_810:
1934                 id = DPLL_ID_LCPLL_810;
1935                 break;
1936         case PORT_CLK_SEL_LCPLL_1350:
1937                 id = DPLL_ID_LCPLL_1350;
1938                 break;
1939         case PORT_CLK_SEL_LCPLL_2700:
1940                 id = DPLL_ID_LCPLL_2700;
1941                 break;
1942         default:
1943                 MISSING_CASE(tmp);
1944                 fallthrough;
1945         case PORT_CLK_SEL_NONE:
1946                 return NULL;
1947         }
1948
1949         return intel_get_shared_dpll_by_id(i915, id);
1950 }
1951
1952 void intel_ddi_enable_clock(struct intel_encoder *encoder,
1953                             const struct intel_crtc_state *crtc_state)
1954 {
1955         if (encoder->enable_clock)
1956                 encoder->enable_clock(encoder, crtc_state);
1957 }
1958
1959 void intel_ddi_disable_clock(struct intel_encoder *encoder)
1960 {
1961         if (encoder->disable_clock)
1962                 encoder->disable_clock(encoder);
1963 }
1964
1965 void intel_ddi_sanitize_encoder_pll_mapping(struct intel_encoder *encoder)
1966 {
1967         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1968         u32 port_mask;
1969         bool ddi_clk_needed;
1970
1971         /*
1972          * In case of DP MST, we sanitize the primary encoder only, not the
1973          * virtual ones.
1974          */
1975         if (encoder->type == INTEL_OUTPUT_DP_MST)
1976                 return;
1977
1978         if (!encoder->base.crtc && intel_encoder_is_dp(encoder)) {
1979                 u8 pipe_mask;
1980                 bool is_mst;
1981
1982                 intel_ddi_get_encoder_pipes(encoder, &pipe_mask, &is_mst);
1983                 /*
1984                  * In the unlikely case that BIOS enables DP in MST mode, just
1985                  * warn since our MST HW readout is incomplete.
1986                  */
1987                 if (drm_WARN_ON(&i915->drm, is_mst))
1988                         return;
1989         }
1990
1991         port_mask = BIT(encoder->port);
1992         ddi_clk_needed = encoder->base.crtc;
1993
1994         if (encoder->type == INTEL_OUTPUT_DSI) {
1995                 struct intel_encoder *other_encoder;
1996
1997                 port_mask = intel_dsi_encoder_ports(encoder);
1998                 /*
1999                  * Sanity check that we haven't incorrectly registered another
2000                  * encoder using any of the ports of this DSI encoder.
2001                  */
2002                 for_each_intel_encoder(&i915->drm, other_encoder) {
2003                         if (other_encoder == encoder)
2004                                 continue;
2005
2006                         if (drm_WARN_ON(&i915->drm,
2007                                         port_mask & BIT(other_encoder->port)))
2008                                 return;
2009                 }
2010                 /*
2011                  * For DSI we keep the ddi clocks gated
2012                  * except during enable/disable sequence.
2013                  */
2014                 ddi_clk_needed = false;
2015         }
2016
2017         if (ddi_clk_needed || !encoder->is_clock_enabled ||
2018             !encoder->is_clock_enabled(encoder))
2019                 return;
2020
2021         drm_notice(&i915->drm,
2022                    "[ENCODER:%d:%s] is disabled/in DSI mode with an ungated DDI clock, gate it\n",
2023                    encoder->base.base.id, encoder->base.name);
2024
2025         encoder->disable_clock(encoder);
2026 }
2027
2028 static void
2029 icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
2030                        const struct intel_crtc_state *crtc_state)
2031 {
2032         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2033         enum tc_port tc_port = intel_port_to_tc(dev_priv, dig_port->base.port);
2034         enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port);
2035         u32 ln0, ln1, pin_assignment;
2036         u8 width;
2037
2038         if (!intel_phy_is_tc(dev_priv, phy) ||
2039             intel_tc_port_in_tbt_alt_mode(dig_port))
2040                 return;
2041
2042         if (DISPLAY_VER(dev_priv) >= 12) {
2043                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2044                                HIP_INDEX_VAL(tc_port, 0x0));
2045                 ln0 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
2046                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2047                                HIP_INDEX_VAL(tc_port, 0x1));
2048                 ln1 = intel_de_read(dev_priv, DKL_DP_MODE(tc_port));
2049         } else {
2050                 ln0 = intel_de_read(dev_priv, MG_DP_MODE(0, tc_port));
2051                 ln1 = intel_de_read(dev_priv, MG_DP_MODE(1, tc_port));
2052         }
2053
2054         ln0 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2055         ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
2056
2057         /* DPPATC */
2058         pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port);
2059         width = crtc_state->lane_count;
2060
2061         switch (pin_assignment) {
2062         case 0x0:
2063                 drm_WARN_ON(&dev_priv->drm,
2064                             !intel_tc_port_in_legacy_mode(dig_port));
2065                 if (width == 1) {
2066                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2067                 } else {
2068                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2069                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2070                 }
2071                 break;
2072         case 0x1:
2073                 if (width == 4) {
2074                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2075                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2076                 }
2077                 break;
2078         case 0x2:
2079                 if (width == 2) {
2080                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2081                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2082                 }
2083                 break;
2084         case 0x3:
2085         case 0x5:
2086                 if (width == 1) {
2087                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2088                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2089                 } else {
2090                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2091                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2092                 }
2093                 break;
2094         case 0x4:
2095         case 0x6:
2096                 if (width == 1) {
2097                         ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
2098                         ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
2099                 } else {
2100                         ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
2101                         ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
2102                 }
2103                 break;
2104         default:
2105                 MISSING_CASE(pin_assignment);
2106         }
2107
2108         if (DISPLAY_VER(dev_priv) >= 12) {
2109                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2110                                HIP_INDEX_VAL(tc_port, 0x0));
2111                 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln0);
2112                 intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
2113                                HIP_INDEX_VAL(tc_port, 0x1));
2114                 intel_de_write(dev_priv, DKL_DP_MODE(tc_port), ln1);
2115         } else {
2116                 intel_de_write(dev_priv, MG_DP_MODE(0, tc_port), ln0);
2117                 intel_de_write(dev_priv, MG_DP_MODE(1, tc_port), ln1);
2118         }
2119 }
2120
2121 static enum transcoder
2122 tgl_dp_tp_transcoder(const struct intel_crtc_state *crtc_state)
2123 {
2124         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
2125                 return crtc_state->mst_master_transcoder;
2126         else
2127                 return crtc_state->cpu_transcoder;
2128 }
2129
2130 i915_reg_t dp_tp_ctl_reg(struct intel_encoder *encoder,
2131                          const struct intel_crtc_state *crtc_state)
2132 {
2133         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2134
2135         if (DISPLAY_VER(dev_priv) >= 12)
2136                 return TGL_DP_TP_CTL(tgl_dp_tp_transcoder(crtc_state));
2137         else
2138                 return DP_TP_CTL(encoder->port);
2139 }
2140
2141 i915_reg_t dp_tp_status_reg(struct intel_encoder *encoder,
2142                             const struct intel_crtc_state *crtc_state)
2143 {
2144         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2145
2146         if (DISPLAY_VER(dev_priv) >= 12)
2147                 return TGL_DP_TP_STATUS(tgl_dp_tp_transcoder(crtc_state));
2148         else
2149                 return DP_TP_STATUS(encoder->port);
2150 }
2151
2152 static void intel_dp_sink_set_msa_timing_par_ignore_state(struct intel_dp *intel_dp,
2153                                                           const struct intel_crtc_state *crtc_state,
2154                                                           bool enable)
2155 {
2156         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2157
2158         if (!crtc_state->vrr.enable)
2159                 return;
2160
2161         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_DOWNSPREAD_CTRL,
2162                                enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0) <= 0)
2163                 drm_dbg_kms(&i915->drm,
2164                             "Failed to %s MSA_TIMING_PAR_IGNORE in the sink\n",
2165                             str_enable_disable(enable));
2166 }
2167
2168 static void intel_dp_sink_set_fec_ready(struct intel_dp *intel_dp,
2169                                         const struct intel_crtc_state *crtc_state)
2170 {
2171         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
2172
2173         if (!crtc_state->fec_enable)
2174                 return;
2175
2176         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_FEC_CONFIGURATION, DP_FEC_READY) <= 0)
2177                 drm_dbg_kms(&i915->drm,
2178                             "Failed to set FEC_READY in the sink\n");
2179 }
2180
2181 static void intel_ddi_enable_fec(struct intel_encoder *encoder,
2182                                  const struct intel_crtc_state *crtc_state)
2183 {
2184         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2185         struct intel_dp *intel_dp;
2186         u32 val;
2187
2188         if (!crtc_state->fec_enable)
2189                 return;
2190
2191         intel_dp = enc_to_intel_dp(encoder);
2192         val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2193         val |= DP_TP_CTL_FEC_ENABLE;
2194         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
2195 }
2196
2197 static void intel_ddi_disable_fec_state(struct intel_encoder *encoder,
2198                                         const struct intel_crtc_state *crtc_state)
2199 {
2200         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2201         struct intel_dp *intel_dp;
2202         u32 val;
2203
2204         if (!crtc_state->fec_enable)
2205                 return;
2206
2207         intel_dp = enc_to_intel_dp(encoder);
2208         val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2209         val &= ~DP_TP_CTL_FEC_ENABLE;
2210         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
2211         intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2212 }
2213
2214 static void intel_ddi_power_up_lanes(struct intel_encoder *encoder,
2215                                      const struct intel_crtc_state *crtc_state)
2216 {
2217         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2218         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2219         enum phy phy = intel_port_to_phy(i915, encoder->port);
2220
2221         if (intel_phy_is_combo(i915, phy)) {
2222                 bool lane_reversal =
2223                         dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
2224
2225                 intel_combo_phy_power_up_lanes(i915, phy, false,
2226                                                crtc_state->lane_count,
2227                                                lane_reversal);
2228         }
2229 }
2230
2231 /* Splitter enable for eDP MSO is limited to certain pipes. */
2232 static u8 intel_ddi_splitter_pipe_mask(struct drm_i915_private *i915)
2233 {
2234         if (IS_ALDERLAKE_P(i915))
2235                 return BIT(PIPE_A) | BIT(PIPE_B);
2236         else
2237                 return BIT(PIPE_A);
2238 }
2239
2240 static void intel_ddi_mso_get_config(struct intel_encoder *encoder,
2241                                      struct intel_crtc_state *pipe_config)
2242 {
2243         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
2244         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2245         enum pipe pipe = crtc->pipe;
2246         u32 dss1;
2247
2248         if (!HAS_MSO(i915))
2249                 return;
2250
2251         dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe));
2252
2253         pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE;
2254         if (!pipe_config->splitter.enable)
2255                 return;
2256
2257         if (drm_WARN_ON(&i915->drm, !(intel_ddi_splitter_pipe_mask(i915) & BIT(pipe)))) {
2258                 pipe_config->splitter.enable = false;
2259                 return;
2260         }
2261
2262         switch (dss1 & SPLITTER_CONFIGURATION_MASK) {
2263         default:
2264                 drm_WARN(&i915->drm, true,
2265                          "Invalid splitter configuration, dss1=0x%08x\n", dss1);
2266                 fallthrough;
2267         case SPLITTER_CONFIGURATION_2_SEGMENT:
2268                 pipe_config->splitter.link_count = 2;
2269                 break;
2270         case SPLITTER_CONFIGURATION_4_SEGMENT:
2271                 pipe_config->splitter.link_count = 4;
2272                 break;
2273         }
2274
2275         pipe_config->splitter.pixel_overlap = REG_FIELD_GET(OVERLAP_PIXELS_MASK, dss1);
2276 }
2277
2278 static void intel_ddi_mso_configure(const struct intel_crtc_state *crtc_state)
2279 {
2280         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2281         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2282         enum pipe pipe = crtc->pipe;
2283         u32 dss1 = 0;
2284
2285         if (!HAS_MSO(i915))
2286                 return;
2287
2288         if (crtc_state->splitter.enable) {
2289                 dss1 |= SPLITTER_ENABLE;
2290                 dss1 |= OVERLAP_PIXELS(crtc_state->splitter.pixel_overlap);
2291                 if (crtc_state->splitter.link_count == 2)
2292                         dss1 |= SPLITTER_CONFIGURATION_2_SEGMENT;
2293                 else
2294                         dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT;
2295         }
2296
2297         intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe),
2298                      SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
2299                      OVERLAP_PIXELS_MASK, dss1);
2300 }
2301
2302 static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
2303                                   struct intel_encoder *encoder,
2304                                   const struct intel_crtc_state *crtc_state,
2305                                   const struct drm_connector_state *conn_state)
2306 {
2307         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2308         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2309         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2310         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2311
2312         intel_dp_set_link_params(intel_dp,
2313                                  crtc_state->port_clock,
2314                                  crtc_state->lane_count);
2315
2316         /*
2317          * We only configure what the register value will be here.  Actual
2318          * enabling happens during link training farther down.
2319          */
2320         intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2321
2322         /*
2323          * 1. Enable Power Wells
2324          *
2325          * This was handled at the beginning of intel_atomic_commit_tail(),
2326          * before we called down into this function.
2327          */
2328
2329         /* 2. Enable Panel Power if PPS is required */
2330         intel_pps_on(intel_dp);
2331
2332         /*
2333          * 3. For non-TBT Type-C ports, set FIA lane count
2334          * (DFLEXDPSP.DPX4TXLATC)
2335          *
2336          * This was done before tgl_ddi_pre_enable_dp by
2337          * hsw_crtc_enable()->intel_encoders_pre_pll_enable().
2338          */
2339
2340         /*
2341          * 4. Enable the port PLL.
2342          *
2343          * The PLL enabling itself was already done before this function by
2344          * hsw_crtc_enable()->intel_enable_shared_dpll().  We need only
2345          * configure the PLL to port mapping here.
2346          */
2347         intel_ddi_enable_clock(encoder, crtc_state);
2348
2349         /* 5. If IO power is controlled through PWR_WELL_CTL, Enable IO Power */
2350         if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
2351                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2352                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2353                                                                    dig_port->ddi_io_power_domain);
2354         }
2355
2356         /* 6. Program DP_MODE */
2357         icl_program_mg_dp_mode(dig_port, crtc_state);
2358
2359         /*
2360          * 7. The rest of the below are substeps under the bspec's "Enable and
2361          * Train Display Port" step.  Note that steps that are specific to
2362          * MST will be handled by intel_mst_pre_enable_dp() before/after it
2363          * calls into this function.  Also intel_mst_pre_enable_dp() only calls
2364          * us when active_mst_links==0, so any steps designated for "single
2365          * stream or multi-stream master transcoder" can just be performed
2366          * unconditionally here.
2367          */
2368
2369         /*
2370          * 7.a Configure Transcoder Clock Select to direct the Port clock to the
2371          * Transcoder.
2372          */
2373         intel_ddi_enable_pipe_clock(encoder, crtc_state);
2374
2375         if (HAS_DP20(dev_priv))
2376                 intel_ddi_config_transcoder_dp2(encoder, crtc_state);
2377
2378         /*
2379          * 7.b Configure TRANS_DDI_FUNC_CTL DDI Select, DDI Mode Select & MST
2380          * Transport Select
2381          */
2382         intel_ddi_config_transcoder_func(encoder, crtc_state);
2383
2384         /*
2385          * 7.c Configure & enable DP_TP_CTL with link training pattern 1
2386          * selected
2387          *
2388          * This will be handled by the intel_dp_start_link_train() farther
2389          * down this function.
2390          */
2391
2392         /* 7.e Configure voltage swing and related IO settings */
2393         encoder->set_signal_levels(encoder, crtc_state);
2394
2395         /*
2396          * 7.f Combo PHY: Configure PORT_CL_DW10 Static Power Down to power up
2397          * the used lanes of the DDI.
2398          */
2399         intel_ddi_power_up_lanes(encoder, crtc_state);
2400
2401         /*
2402          * 7.g Program CoG/MSO configuration bits in DSS_CTL1 if selected.
2403          */
2404         intel_ddi_mso_configure(crtc_state);
2405
2406         if (!is_mst)
2407                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2408
2409         intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2410         intel_dp_sink_set_decompression_state(intel_dp, crtc_state, true);
2411         /*
2412          * DDI FEC: "anticipates enabling FEC encoding sets the FEC_READY bit
2413          * in the FEC_CONFIGURATION register to 1 before initiating link
2414          * training
2415          */
2416         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2417
2418         intel_dp_check_frl_training(intel_dp);
2419         intel_dp_pcon_dsc_configure(intel_dp, crtc_state);
2420
2421         /*
2422          * 7.i Follow DisplayPort specification training sequence (see notes for
2423          *     failure handling)
2424          * 7.j If DisplayPort multi-stream - Set DP_TP_CTL link training to Idle
2425          *     Pattern, wait for 5 idle patterns (DP_TP_STATUS Min_Idles_Sent)
2426          *     (timeout after 800 us)
2427          */
2428         intel_dp_start_link_train(intel_dp, crtc_state);
2429
2430         /* 7.k Set DP_TP_CTL link training to Normal */
2431         if (!is_trans_port_sync_mode(crtc_state))
2432                 intel_dp_stop_link_train(intel_dp, crtc_state);
2433
2434         /* 7.l Configure and enable FEC if needed */
2435         intel_ddi_enable_fec(encoder, crtc_state);
2436
2437         intel_dsc_dp_pps_write(encoder, crtc_state);
2438 }
2439
2440 static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
2441                                   struct intel_encoder *encoder,
2442                                   const struct intel_crtc_state *crtc_state,
2443                                   const struct drm_connector_state *conn_state)
2444 {
2445         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2446         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2447         enum port port = encoder->port;
2448         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2449         bool is_mst = intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST);
2450
2451         if (DISPLAY_VER(dev_priv) < 11)
2452                 drm_WARN_ON(&dev_priv->drm,
2453                             is_mst && (port == PORT_A || port == PORT_E));
2454         else
2455                 drm_WARN_ON(&dev_priv->drm, is_mst && port == PORT_A);
2456
2457         intel_dp_set_link_params(intel_dp,
2458                                  crtc_state->port_clock,
2459                                  crtc_state->lane_count);
2460
2461         /*
2462          * We only configure what the register value will be here.  Actual
2463          * enabling happens during link training farther down.
2464          */
2465         intel_ddi_init_dp_buf_reg(encoder, crtc_state);
2466
2467         intel_pps_on(intel_dp);
2468
2469         intel_ddi_enable_clock(encoder, crtc_state);
2470
2471         if (!intel_tc_port_in_tbt_alt_mode(dig_port)) {
2472                 drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2473                 dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2474                                                                    dig_port->ddi_io_power_domain);
2475         }
2476
2477         icl_program_mg_dp_mode(dig_port, crtc_state);
2478
2479         if (has_buf_trans_select(dev_priv))
2480                 hsw_prepare_dp_ddi_buffers(encoder, crtc_state);
2481
2482         encoder->set_signal_levels(encoder, crtc_state);
2483
2484         intel_ddi_power_up_lanes(encoder, crtc_state);
2485
2486         if (!is_mst)
2487                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
2488         intel_dp_configure_protocol_converter(intel_dp, crtc_state);
2489         intel_dp_sink_set_decompression_state(intel_dp, crtc_state,
2490                                               true);
2491         intel_dp_sink_set_fec_ready(intel_dp, crtc_state);
2492         intel_dp_start_link_train(intel_dp, crtc_state);
2493         if ((port != PORT_A || DISPLAY_VER(dev_priv) >= 9) &&
2494             !is_trans_port_sync_mode(crtc_state))
2495                 intel_dp_stop_link_train(intel_dp, crtc_state);
2496
2497         intel_ddi_enable_fec(encoder, crtc_state);
2498
2499         if (!is_mst)
2500                 intel_ddi_enable_pipe_clock(encoder, crtc_state);
2501
2502         intel_dsc_dp_pps_write(encoder, crtc_state);
2503 }
2504
2505 static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
2506                                     struct intel_encoder *encoder,
2507                                     const struct intel_crtc_state *crtc_state,
2508                                     const struct drm_connector_state *conn_state)
2509 {
2510         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2511
2512         if (DISPLAY_VER(dev_priv) >= 12)
2513                 tgl_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2514         else
2515                 hsw_ddi_pre_enable_dp(state, encoder, crtc_state, conn_state);
2516
2517         /* MST will call a setting of MSA after an allocating of Virtual Channel
2518          * from MST encoder pre_enable callback.
2519          */
2520         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
2521                 intel_ddi_set_dp_msa(crtc_state, conn_state);
2522 }
2523
2524 static void intel_ddi_pre_enable_hdmi(struct intel_atomic_state *state,
2525                                       struct intel_encoder *encoder,
2526                                       const struct intel_crtc_state *crtc_state,
2527                                       const struct drm_connector_state *conn_state)
2528 {
2529         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2530         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2531         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2532
2533         intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
2534         intel_ddi_enable_clock(encoder, crtc_state);
2535
2536         drm_WARN_ON(&dev_priv->drm, dig_port->ddi_io_wakeref);
2537         dig_port->ddi_io_wakeref = intel_display_power_get(dev_priv,
2538                                                            dig_port->ddi_io_power_domain);
2539
2540         icl_program_mg_dp_mode(dig_port, crtc_state);
2541
2542         intel_ddi_enable_pipe_clock(encoder, crtc_state);
2543
2544         dig_port->set_infoframes(encoder,
2545                                  crtc_state->has_infoframe,
2546                                  crtc_state, conn_state);
2547 }
2548
2549 static void intel_ddi_pre_enable(struct intel_atomic_state *state,
2550                                  struct intel_encoder *encoder,
2551                                  const struct intel_crtc_state *crtc_state,
2552                                  const struct drm_connector_state *conn_state)
2553 {
2554         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2555         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2556         enum pipe pipe = crtc->pipe;
2557
2558         /*
2559          * When called from DP MST code:
2560          * - conn_state will be NULL
2561          * - encoder will be the main encoder (ie. mst->primary)
2562          * - the main connector associated with this port
2563          *   won't be active or linked to a crtc
2564          * - crtc_state will be the state of the first stream to
2565          *   be activated on this port, and it may not be the same
2566          *   stream that will be deactivated last, but each stream
2567          *   should have a state that is identical when it comes to
2568          *   the DP link parameteres
2569          */
2570
2571         drm_WARN_ON(&dev_priv->drm, crtc_state->has_pch_encoder);
2572
2573         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2574
2575         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) {
2576                 intel_ddi_pre_enable_hdmi(state, encoder, crtc_state,
2577                                           conn_state);
2578         } else {
2579                 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2580
2581                 intel_ddi_pre_enable_dp(state, encoder, crtc_state,
2582                                         conn_state);
2583
2584                 /* FIXME precompute everything properly */
2585                 /* FIXME how do we turn infoframes off again? */
2586                 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
2587                         dig_port->set_infoframes(encoder,
2588                                                  crtc_state->has_infoframe,
2589                                                  crtc_state, conn_state);
2590         }
2591 }
2592
2593 static void intel_disable_ddi_buf(struct intel_encoder *encoder,
2594                                   const struct intel_crtc_state *crtc_state)
2595 {
2596         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2597         enum port port = encoder->port;
2598         bool wait = false;
2599         u32 val;
2600
2601         val = intel_de_read(dev_priv, DDI_BUF_CTL(port));
2602         if (val & DDI_BUF_CTL_ENABLE) {
2603                 val &= ~DDI_BUF_CTL_ENABLE;
2604                 intel_de_write(dev_priv, DDI_BUF_CTL(port), val);
2605                 wait = true;
2606         }
2607
2608         if (intel_crtc_has_dp_encoder(crtc_state)) {
2609                 val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
2610                 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2611                 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2612                 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
2613         }
2614
2615         /* Disable FEC in DP Sink */
2616         intel_ddi_disable_fec_state(encoder, crtc_state);
2617
2618         if (wait)
2619                 intel_wait_ddi_buf_idle(dev_priv, port);
2620 }
2621
2622 static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
2623                                       struct intel_encoder *encoder,
2624                                       const struct intel_crtc_state *old_crtc_state,
2625                                       const struct drm_connector_state *old_conn_state)
2626 {
2627         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2628         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2629         struct intel_dp *intel_dp = &dig_port->dp;
2630         bool is_mst = intel_crtc_has_type(old_crtc_state,
2631                                           INTEL_OUTPUT_DP_MST);
2632
2633         if (!is_mst)
2634                 intel_dp_set_infoframes(encoder, false,
2635                                         old_crtc_state, old_conn_state);
2636
2637         /*
2638          * Power down sink before disabling the port, otherwise we end
2639          * up getting interrupts from the sink on detecting link loss.
2640          */
2641         intel_dp_set_power(intel_dp, DP_SET_POWER_D3);
2642
2643         if (DISPLAY_VER(dev_priv) >= 12) {
2644                 if (is_mst) {
2645                         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
2646                         u32 val;
2647
2648                         val = intel_de_read(dev_priv,
2649                                             TRANS_DDI_FUNC_CTL(cpu_transcoder));
2650                         val &= ~(TGL_TRANS_DDI_PORT_MASK |
2651                                  TRANS_DDI_MODE_SELECT_MASK);
2652                         intel_de_write(dev_priv,
2653                                        TRANS_DDI_FUNC_CTL(cpu_transcoder),
2654                                        val);
2655                 }
2656         } else {
2657                 if (!is_mst)
2658                         intel_ddi_disable_pipe_clock(old_crtc_state);
2659         }
2660
2661         intel_disable_ddi_buf(encoder, old_crtc_state);
2662
2663         /*
2664          * From TGL spec: "If single stream or multi-stream master transcoder:
2665          * Configure Transcoder Clock select to direct no clock to the
2666          * transcoder"
2667          */
2668         if (DISPLAY_VER(dev_priv) >= 12)
2669                 intel_ddi_disable_pipe_clock(old_crtc_state);
2670
2671         intel_pps_vdd_on(intel_dp);
2672         intel_pps_off(intel_dp);
2673
2674         if (!intel_tc_port_in_tbt_alt_mode(dig_port))
2675                 intel_display_power_put(dev_priv,
2676                                         dig_port->ddi_io_power_domain,
2677                                         fetch_and_zero(&dig_port->ddi_io_wakeref));
2678
2679         intel_ddi_disable_clock(encoder);
2680 }
2681
2682 static void intel_ddi_post_disable_hdmi(struct intel_atomic_state *state,
2683                                         struct intel_encoder *encoder,
2684                                         const struct intel_crtc_state *old_crtc_state,
2685                                         const struct drm_connector_state *old_conn_state)
2686 {
2687         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2688         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2689         struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
2690
2691         dig_port->set_infoframes(encoder, false,
2692                                  old_crtc_state, old_conn_state);
2693
2694         intel_ddi_disable_pipe_clock(old_crtc_state);
2695
2696         intel_disable_ddi_buf(encoder, old_crtc_state);
2697
2698         intel_display_power_put(dev_priv,
2699                                 dig_port->ddi_io_power_domain,
2700                                 fetch_and_zero(&dig_port->ddi_io_wakeref));
2701
2702         intel_ddi_disable_clock(encoder);
2703
2704         intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
2705 }
2706
2707 static void intel_ddi_post_disable(struct intel_atomic_state *state,
2708                                    struct intel_encoder *encoder,
2709                                    const struct intel_crtc_state *old_crtc_state,
2710                                    const struct drm_connector_state *old_conn_state)
2711 {
2712         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2713         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2714         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
2715         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
2716         struct intel_crtc *slave_crtc;
2717
2718         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DP_MST)) {
2719                 intel_crtc_vblank_off(old_crtc_state);
2720
2721                 intel_disable_transcoder(old_crtc_state);
2722
2723                 intel_vrr_disable(old_crtc_state);
2724
2725                 intel_ddi_disable_transcoder_func(old_crtc_state);
2726
2727                 intel_dsc_disable(old_crtc_state);
2728
2729                 if (DISPLAY_VER(dev_priv) >= 9)
2730                         skl_scaler_disable(old_crtc_state);
2731                 else
2732                         ilk_pfit_disable(old_crtc_state);
2733         }
2734
2735         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, slave_crtc,
2736                                          intel_crtc_bigjoiner_slave_pipes(old_crtc_state)) {
2737                 const struct intel_crtc_state *old_slave_crtc_state =
2738                         intel_atomic_get_old_crtc_state(state, slave_crtc);
2739
2740                 intel_crtc_vblank_off(old_slave_crtc_state);
2741
2742                 intel_dsc_disable(old_slave_crtc_state);
2743                 skl_scaler_disable(old_slave_crtc_state);
2744         }
2745
2746         /*
2747          * When called from DP MST code:
2748          * - old_conn_state will be NULL
2749          * - encoder will be the main encoder (ie. mst->primary)
2750          * - the main connector associated with this port
2751          *   won't be active or linked to a crtc
2752          * - old_crtc_state will be the state of the last stream to
2753          *   be deactivated on this port, and it may not be the same
2754          *   stream that was activated last, but each stream
2755          *   should have a state that is identical when it comes to
2756          *   the DP link parameteres
2757          */
2758
2759         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
2760                 intel_ddi_post_disable_hdmi(state, encoder, old_crtc_state,
2761                                             old_conn_state);
2762         else
2763                 intel_ddi_post_disable_dp(state, encoder, old_crtc_state,
2764                                           old_conn_state);
2765
2766         if (intel_crtc_has_dp_encoder(old_crtc_state) || is_tc_port)
2767                 intel_display_power_put(dev_priv,
2768                                         intel_ddi_main_link_aux_domain(dig_port),
2769                                         fetch_and_zero(&dig_port->aux_wakeref));
2770
2771         if (is_tc_port)
2772                 intel_tc_port_put_link(dig_port);
2773 }
2774
2775 static void trans_port_sync_stop_link_train(struct intel_atomic_state *state,
2776                                             struct intel_encoder *encoder,
2777                                             const struct intel_crtc_state *crtc_state)
2778 {
2779         const struct drm_connector_state *conn_state;
2780         struct drm_connector *conn;
2781         int i;
2782
2783         if (!crtc_state->sync_mode_slaves_mask)
2784                 return;
2785
2786         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
2787                 struct intel_encoder *slave_encoder =
2788                         to_intel_encoder(conn_state->best_encoder);
2789                 struct intel_crtc *slave_crtc = to_intel_crtc(conn_state->crtc);
2790                 const struct intel_crtc_state *slave_crtc_state;
2791
2792                 if (!slave_crtc)
2793                         continue;
2794
2795                 slave_crtc_state =
2796                         intel_atomic_get_new_crtc_state(state, slave_crtc);
2797
2798                 if (slave_crtc_state->master_transcoder !=
2799                     crtc_state->cpu_transcoder)
2800                         continue;
2801
2802                 intel_dp_stop_link_train(enc_to_intel_dp(slave_encoder),
2803                                          slave_crtc_state);
2804         }
2805
2806         usleep_range(200, 400);
2807
2808         intel_dp_stop_link_train(enc_to_intel_dp(encoder),
2809                                  crtc_state);
2810 }
2811
2812 static void intel_enable_ddi_dp(struct intel_atomic_state *state,
2813                                 struct intel_encoder *encoder,
2814                                 const struct intel_crtc_state *crtc_state,
2815                                 const struct drm_connector_state *conn_state)
2816 {
2817         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2818         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2819         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2820         enum port port = encoder->port;
2821
2822         if (port == PORT_A && DISPLAY_VER(dev_priv) < 9)
2823                 intel_dp_stop_link_train(intel_dp, crtc_state);
2824
2825         drm_connector_update_privacy_screen(conn_state);
2826         intel_edp_backlight_on(crtc_state, conn_state);
2827
2828         if (!dig_port->lspcon.active || dig_port->dp.has_hdmi_sink)
2829                 intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
2830
2831         intel_audio_codec_enable(encoder, crtc_state, conn_state);
2832
2833         trans_port_sync_stop_link_train(state, encoder, crtc_state);
2834 }
2835
2836 static i915_reg_t
2837 gen9_chicken_trans_reg_by_port(struct drm_i915_private *dev_priv,
2838                                enum port port)
2839 {
2840         static const enum transcoder trans[] = {
2841                 [PORT_A] = TRANSCODER_EDP,
2842                 [PORT_B] = TRANSCODER_A,
2843                 [PORT_C] = TRANSCODER_B,
2844                 [PORT_D] = TRANSCODER_C,
2845                 [PORT_E] = TRANSCODER_A,
2846         };
2847
2848         drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) < 9);
2849
2850         if (drm_WARN_ON(&dev_priv->drm, port < PORT_A || port > PORT_E))
2851                 port = PORT_A;
2852
2853         return CHICKEN_TRANS(trans[port]);
2854 }
2855
2856 static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
2857                                   struct intel_encoder *encoder,
2858                                   const struct intel_crtc_state *crtc_state,
2859                                   const struct drm_connector_state *conn_state)
2860 {
2861         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2862         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
2863         struct drm_connector *connector = conn_state->connector;
2864         enum port port = encoder->port;
2865
2866         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
2867                                                crtc_state->hdmi_high_tmds_clock_ratio,
2868                                                crtc_state->hdmi_scrambling))
2869                 drm_dbg_kms(&dev_priv->drm,
2870                             "[CONNECTOR:%d:%s] Failed to configure sink scrambling/TMDS bit clock ratio\n",
2871                             connector->base.id, connector->name);
2872
2873         if (has_buf_trans_select(dev_priv))
2874                 hsw_prepare_hdmi_ddi_buffers(encoder, crtc_state);
2875
2876         encoder->set_signal_levels(encoder, crtc_state);
2877
2878         /* Display WA #1143: skl,kbl,cfl */
2879         if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv)) {
2880                 /*
2881                  * For some reason these chicken bits have been
2882                  * stuffed into a transcoder register, event though
2883                  * the bits affect a specific DDI port rather than
2884                  * a specific transcoder.
2885                  */
2886                 i915_reg_t reg = gen9_chicken_trans_reg_by_port(dev_priv, port);
2887                 u32 val;
2888
2889                 val = intel_de_read(dev_priv, reg);
2890
2891                 if (port == PORT_E)
2892                         val |= DDIE_TRAINING_OVERRIDE_ENABLE |
2893                                 DDIE_TRAINING_OVERRIDE_VALUE;
2894                 else
2895                         val |= DDI_TRAINING_OVERRIDE_ENABLE |
2896                                 DDI_TRAINING_OVERRIDE_VALUE;
2897
2898                 intel_de_write(dev_priv, reg, val);
2899                 intel_de_posting_read(dev_priv, reg);
2900
2901                 udelay(1);
2902
2903                 if (port == PORT_E)
2904                         val &= ~(DDIE_TRAINING_OVERRIDE_ENABLE |
2905                                  DDIE_TRAINING_OVERRIDE_VALUE);
2906                 else
2907                         val &= ~(DDI_TRAINING_OVERRIDE_ENABLE |
2908                                  DDI_TRAINING_OVERRIDE_VALUE);
2909
2910                 intel_de_write(dev_priv, reg, val);
2911         }
2912
2913         intel_ddi_power_up_lanes(encoder, crtc_state);
2914
2915         /* In HDMI/DVI mode, the port width, and swing/emphasis values
2916          * are ignored so nothing special needs to be done besides
2917          * enabling the port.
2918          *
2919          * On ADL_P the PHY link rate and lane count must be programmed but
2920          * these are both 0 for HDMI.
2921          */
2922         intel_de_write(dev_priv, DDI_BUF_CTL(port),
2923                        dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE);
2924
2925         intel_audio_codec_enable(encoder, crtc_state, conn_state);
2926 }
2927
2928 static void intel_enable_ddi(struct intel_atomic_state *state,
2929                              struct intel_encoder *encoder,
2930                              const struct intel_crtc_state *crtc_state,
2931                              const struct drm_connector_state *conn_state)
2932 {
2933         drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
2934
2935         if (!intel_crtc_is_bigjoiner_slave(crtc_state))
2936                 intel_ddi_enable_transcoder_func(encoder, crtc_state);
2937
2938         intel_vrr_enable(encoder, crtc_state);
2939
2940         intel_enable_transcoder(crtc_state);
2941
2942         intel_crtc_vblank_on(crtc_state);
2943
2944         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2945                 intel_enable_ddi_hdmi(state, encoder, crtc_state, conn_state);
2946         else
2947                 intel_enable_ddi_dp(state, encoder, crtc_state, conn_state);
2948
2949         /* Enable hdcp if it's desired */
2950         if (conn_state->content_protection ==
2951             DRM_MODE_CONTENT_PROTECTION_DESIRED)
2952                 intel_hdcp_enable(to_intel_connector(conn_state->connector),
2953                                   crtc_state,
2954                                   (u8)conn_state->hdcp_content_type);
2955 }
2956
2957 static void intel_disable_ddi_dp(struct intel_atomic_state *state,
2958                                  struct intel_encoder *encoder,
2959                                  const struct intel_crtc_state *old_crtc_state,
2960                                  const struct drm_connector_state *old_conn_state)
2961 {
2962         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2963
2964         intel_dp->link_trained = false;
2965
2966         intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
2967
2968         intel_psr_disable(intel_dp, old_crtc_state);
2969         intel_edp_backlight_off(old_conn_state);
2970         /* Disable the decompression in DP Sink */
2971         intel_dp_sink_set_decompression_state(intel_dp, old_crtc_state,
2972                                               false);
2973         /* Disable Ignore_MSA bit in DP Sink */
2974         intel_dp_sink_set_msa_timing_par_ignore_state(intel_dp, old_crtc_state,
2975                                                       false);
2976 }
2977
2978 static void intel_disable_ddi_hdmi(struct intel_atomic_state *state,
2979                                    struct intel_encoder *encoder,
2980                                    const struct intel_crtc_state *old_crtc_state,
2981                                    const struct drm_connector_state *old_conn_state)
2982 {
2983         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
2984         struct drm_connector *connector = old_conn_state->connector;
2985
2986         intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state);
2987
2988         if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
2989                                                false, false))
2990                 drm_dbg_kms(&i915->drm,
2991                             "[CONNECTOR:%d:%s] Failed to reset sink scrambling/TMDS bit clock ratio\n",
2992                             connector->base.id, connector->name);
2993 }
2994
2995 static void intel_disable_ddi(struct intel_atomic_state *state,
2996                               struct intel_encoder *encoder,
2997                               const struct intel_crtc_state *old_crtc_state,
2998                               const struct drm_connector_state *old_conn_state)
2999 {
3000         intel_hdcp_disable(to_intel_connector(old_conn_state->connector));
3001
3002         if (intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_HDMI))
3003                 intel_disable_ddi_hdmi(state, encoder, old_crtc_state,
3004                                        old_conn_state);
3005         else
3006                 intel_disable_ddi_dp(state, encoder, old_crtc_state,
3007                                      old_conn_state);
3008 }
3009
3010 static void intel_ddi_update_pipe_dp(struct intel_atomic_state *state,
3011                                      struct intel_encoder *encoder,
3012                                      const struct intel_crtc_state *crtc_state,
3013                                      const struct drm_connector_state *conn_state)
3014 {
3015         intel_ddi_set_dp_msa(crtc_state, conn_state);
3016
3017         intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
3018
3019         intel_backlight_update(state, encoder, crtc_state, conn_state);
3020         drm_connector_update_privacy_screen(conn_state);
3021 }
3022
3023 void intel_ddi_update_pipe(struct intel_atomic_state *state,
3024                            struct intel_encoder *encoder,
3025                            const struct intel_crtc_state *crtc_state,
3026                            const struct drm_connector_state *conn_state)
3027 {
3028
3029         if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
3030             !intel_encoder_is_mst(encoder))
3031                 intel_ddi_update_pipe_dp(state, encoder, crtc_state,
3032                                          conn_state);
3033
3034         intel_hdcp_update_pipe(state, encoder, crtc_state, conn_state);
3035 }
3036
3037 static void
3038 intel_ddi_update_prepare(struct intel_atomic_state *state,
3039                          struct intel_encoder *encoder,
3040                          struct intel_crtc *crtc)
3041 {
3042         struct drm_i915_private *i915 = to_i915(state->base.dev);
3043         struct intel_crtc_state *crtc_state =
3044                 crtc ? intel_atomic_get_new_crtc_state(state, crtc) : NULL;
3045         int required_lanes = crtc_state ? crtc_state->lane_count : 1;
3046
3047         drm_WARN_ON(state->base.dev, crtc && crtc->active);
3048
3049         intel_tc_port_get_link(enc_to_dig_port(encoder),
3050                                required_lanes);
3051         if (crtc_state && crtc_state->hw.active) {
3052                 struct intel_crtc *slave_crtc;
3053
3054                 intel_update_active_dpll(state, crtc, encoder);
3055
3056                 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
3057                                                  intel_crtc_bigjoiner_slave_pipes(crtc_state))
3058                         intel_update_active_dpll(state, slave_crtc, encoder);
3059         }
3060 }
3061
3062 static void
3063 intel_ddi_update_complete(struct intel_atomic_state *state,
3064                           struct intel_encoder *encoder,
3065                           struct intel_crtc *crtc)
3066 {
3067         intel_tc_port_put_link(enc_to_dig_port(encoder));
3068 }
3069
3070 static void
3071 intel_ddi_pre_pll_enable(struct intel_atomic_state *state,
3072                          struct intel_encoder *encoder,
3073                          const struct intel_crtc_state *crtc_state,
3074                          const struct drm_connector_state *conn_state)
3075 {
3076         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3077         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3078         enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3079         bool is_tc_port = intel_phy_is_tc(dev_priv, phy);
3080
3081         if (is_tc_port)
3082                 intel_tc_port_get_link(dig_port, crtc_state->lane_count);
3083
3084         if (intel_crtc_has_dp_encoder(crtc_state) || is_tc_port) {
3085                 drm_WARN_ON(&dev_priv->drm, dig_port->aux_wakeref);
3086                 dig_port->aux_wakeref =
3087                         intel_display_power_get(dev_priv,
3088                                                 intel_ddi_main_link_aux_domain(dig_port));
3089         }
3090
3091         if (is_tc_port && !intel_tc_port_in_tbt_alt_mode(dig_port))
3092                 /*
3093                  * Program the lane count for static/dynamic connections on
3094                  * Type-C ports.  Skip this step for TBT.
3095                  */
3096                 intel_tc_port_set_fia_lane_count(dig_port, crtc_state->lane_count);
3097         else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3098                 bxt_ddi_phy_set_lane_optim_mask(encoder,
3099                                                 crtc_state->lane_lat_optim_mask);
3100 }
3101
3102 static void adlp_tbt_to_dp_alt_switch_wa(struct intel_encoder *encoder)
3103 {
3104         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3105         enum tc_port tc_port = intel_port_to_tc(i915, encoder->port);
3106         int ln;
3107
3108         for (ln = 0; ln < 2; ln++) {
3109                 intel_de_write(i915, HIP_INDEX_REG(tc_port), HIP_INDEX_VAL(tc_port, ln));
3110                 intel_de_rmw(i915, DKL_PCS_DW5(tc_port), DKL_PCS_DW5_CORE_SOFTRESET, 0);
3111         }
3112 }
3113
3114 static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
3115                                            const struct intel_crtc_state *crtc_state)
3116 {
3117         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3118         struct intel_encoder *encoder = &dig_port->base;
3119         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3120         enum port port = encoder->port;
3121         u32 dp_tp_ctl, ddi_buf_ctl;
3122         bool wait = false;
3123
3124         dp_tp_ctl = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3125
3126         if (dp_tp_ctl & DP_TP_CTL_ENABLE) {
3127                 ddi_buf_ctl = intel_de_read(dev_priv, DDI_BUF_CTL(port));
3128                 if (ddi_buf_ctl & DDI_BUF_CTL_ENABLE) {
3129                         intel_de_write(dev_priv, DDI_BUF_CTL(port),
3130                                        ddi_buf_ctl & ~DDI_BUF_CTL_ENABLE);
3131                         wait = true;
3132                 }
3133
3134                 dp_tp_ctl &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
3135                 dp_tp_ctl |= DP_TP_CTL_LINK_TRAIN_PAT1;
3136                 intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3137                 intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3138
3139                 if (wait)
3140                         intel_wait_ddi_buf_idle(dev_priv, port);
3141         }
3142
3143         dp_tp_ctl = DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT1;
3144         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {
3145                 dp_tp_ctl |= DP_TP_CTL_MODE_MST;
3146         } else {
3147                 dp_tp_ctl |= DP_TP_CTL_MODE_SST;
3148                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
3149                         dp_tp_ctl |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
3150         }
3151         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), dp_tp_ctl);
3152         intel_de_posting_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3153
3154         if (IS_ALDERLAKE_P(dev_priv) &&
3155             (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port)))
3156                 adlp_tbt_to_dp_alt_switch_wa(encoder);
3157
3158         intel_dp->DP |= DDI_BUF_CTL_ENABLE;
3159         intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
3160         intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
3161
3162         intel_wait_ddi_buf_active(dev_priv, port);
3163 }
3164
3165 static void intel_ddi_set_link_train(struct intel_dp *intel_dp,
3166                                      const struct intel_crtc_state *crtc_state,
3167                                      u8 dp_train_pat)
3168 {
3169         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3170         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3171         u32 temp;
3172
3173         temp = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3174
3175         temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3176         switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
3177         case DP_TRAINING_PATTERN_DISABLE:
3178                 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
3179                 break;
3180         case DP_TRAINING_PATTERN_1:
3181                 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
3182                 break;
3183         case DP_TRAINING_PATTERN_2:
3184                 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
3185                 break;
3186         case DP_TRAINING_PATTERN_3:
3187                 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
3188                 break;
3189         case DP_TRAINING_PATTERN_4:
3190                 temp |= DP_TP_CTL_LINK_TRAIN_PAT4;
3191                 break;
3192         }
3193
3194         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), temp);
3195 }
3196
3197 static void intel_ddi_set_idle_link_train(struct intel_dp *intel_dp,
3198                                           const struct intel_crtc_state *crtc_state)
3199 {
3200         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3201         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3202         enum port port = encoder->port;
3203         u32 val;
3204
3205         val = intel_de_read(dev_priv, dp_tp_ctl_reg(encoder, crtc_state));
3206         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3207         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3208         intel_de_write(dev_priv, dp_tp_ctl_reg(encoder, crtc_state), val);
3209
3210         /*
3211          * Until TGL on PORT_A we can have only eDP in SST mode. There the only
3212          * reason we need to set idle transmission mode is to work around a HW
3213          * issue where we enable the pipe while not in idle link-training mode.
3214          * In this case there is requirement to wait for a minimum number of
3215          * idle patterns to be sent.
3216          */
3217         if (port == PORT_A && DISPLAY_VER(dev_priv) < 12)
3218                 return;
3219
3220         if (intel_de_wait_for_set(dev_priv,
3221                                   dp_tp_status_reg(encoder, crtc_state),
3222                                   DP_TP_STATUS_IDLE_DONE, 1))
3223                 drm_err(&dev_priv->drm,
3224                         "Timed out waiting for DP idle patterns\n");
3225 }
3226
3227 static bool intel_ddi_is_audio_enabled(struct drm_i915_private *dev_priv,
3228                                        enum transcoder cpu_transcoder)
3229 {
3230         if (cpu_transcoder == TRANSCODER_EDP)
3231                 return false;
3232
3233         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO_MMIO))
3234                 return false;
3235
3236         return intel_de_read(dev_priv, HSW_AUD_PIN_ELD_CP_VLD) &
3237                 AUDIO_OUTPUT_ENABLE(cpu_transcoder);
3238 }
3239
3240 void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv,
3241                                          struct intel_crtc_state *crtc_state)
3242 {
3243         if (DISPLAY_VER(dev_priv) >= 12 && crtc_state->port_clock > 594000)
3244                 crtc_state->min_voltage_level = 2;
3245         else if (IS_JSL_EHL(dev_priv) && crtc_state->port_clock > 594000)
3246                 crtc_state->min_voltage_level = 3;
3247         else if (DISPLAY_VER(dev_priv) >= 11 && crtc_state->port_clock > 594000)
3248                 crtc_state->min_voltage_level = 1;
3249 }
3250
3251 static enum transcoder bdw_transcoder_master_readout(struct drm_i915_private *dev_priv,
3252                                                      enum transcoder cpu_transcoder)
3253 {
3254         u32 master_select;
3255
3256         if (DISPLAY_VER(dev_priv) >= 11) {
3257                 u32 ctl2 = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL2(cpu_transcoder));
3258
3259                 if ((ctl2 & PORT_SYNC_MODE_ENABLE) == 0)
3260                         return INVALID_TRANSCODER;
3261
3262                 master_select = REG_FIELD_GET(PORT_SYNC_MODE_MASTER_SELECT_MASK, ctl2);
3263         } else {
3264                 u32 ctl = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3265
3266                 if ((ctl & TRANS_DDI_PORT_SYNC_ENABLE) == 0)
3267                         return INVALID_TRANSCODER;
3268
3269                 master_select = REG_FIELD_GET(TRANS_DDI_PORT_SYNC_MASTER_SELECT_MASK, ctl);
3270         }
3271
3272         if (master_select == 0)
3273                 return TRANSCODER_EDP;
3274         else
3275                 return master_select - 1;
3276 }
3277
3278 static void bdw_get_trans_port_sync_config(struct intel_crtc_state *crtc_state)
3279 {
3280         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3281         u32 transcoders = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
3282                 BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
3283         enum transcoder cpu_transcoder;
3284
3285         crtc_state->master_transcoder =
3286                 bdw_transcoder_master_readout(dev_priv, crtc_state->cpu_transcoder);
3287
3288         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder, transcoders) {
3289                 enum intel_display_power_domain power_domain;
3290                 intel_wakeref_t trans_wakeref;
3291
3292                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3293                 trans_wakeref = intel_display_power_get_if_enabled(dev_priv,
3294                                                                    power_domain);
3295
3296                 if (!trans_wakeref)
3297                         continue;
3298
3299                 if (bdw_transcoder_master_readout(dev_priv, cpu_transcoder) ==
3300                     crtc_state->cpu_transcoder)
3301                         crtc_state->sync_mode_slaves_mask |= BIT(cpu_transcoder);
3302
3303                 intel_display_power_put(dev_priv, power_domain, trans_wakeref);
3304         }
3305
3306         drm_WARN_ON(&dev_priv->drm,
3307                     crtc_state->master_transcoder != INVALID_TRANSCODER &&
3308                     crtc_state->sync_mode_slaves_mask);
3309 }
3310
3311 static void intel_ddi_read_func_ctl(struct intel_encoder *encoder,
3312                                     struct intel_crtc_state *pipe_config)
3313 {
3314         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3315         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3316         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3317         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3318         u32 temp, flags = 0;
3319
3320         temp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3321         if (temp & TRANS_DDI_PHSYNC)
3322                 flags |= DRM_MODE_FLAG_PHSYNC;
3323         else
3324                 flags |= DRM_MODE_FLAG_NHSYNC;
3325         if (temp & TRANS_DDI_PVSYNC)
3326                 flags |= DRM_MODE_FLAG_PVSYNC;
3327         else
3328                 flags |= DRM_MODE_FLAG_NVSYNC;
3329
3330         pipe_config->hw.adjusted_mode.flags |= flags;
3331
3332         switch (temp & TRANS_DDI_BPC_MASK) {
3333         case TRANS_DDI_BPC_6:
3334                 pipe_config->pipe_bpp = 18;
3335                 break;
3336         case TRANS_DDI_BPC_8:
3337                 pipe_config->pipe_bpp = 24;
3338                 break;
3339         case TRANS_DDI_BPC_10:
3340                 pipe_config->pipe_bpp = 30;
3341                 break;
3342         case TRANS_DDI_BPC_12:
3343                 pipe_config->pipe_bpp = 36;
3344                 break;
3345         default:
3346                 break;
3347         }
3348
3349         switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
3350         case TRANS_DDI_MODE_SELECT_HDMI:
3351                 pipe_config->has_hdmi_sink = true;
3352
3353                 pipe_config->infoframes.enable |=
3354                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
3355
3356                 if (pipe_config->infoframes.enable)
3357                         pipe_config->has_infoframe = true;
3358
3359                 if (temp & TRANS_DDI_HDMI_SCRAMBLING)
3360                         pipe_config->hdmi_scrambling = true;
3361                 if (temp & TRANS_DDI_HIGH_TMDS_CHAR_RATE)
3362                         pipe_config->hdmi_high_tmds_clock_ratio = true;
3363                 fallthrough;
3364         case TRANS_DDI_MODE_SELECT_DVI:
3365                 pipe_config->output_types |= BIT(INTEL_OUTPUT_HDMI);
3366                 pipe_config->lane_count = 4;
3367                 break;
3368         case TRANS_DDI_MODE_SELECT_DP_SST:
3369                 if (encoder->type == INTEL_OUTPUT_EDP)
3370                         pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP);
3371                 else
3372                         pipe_config->output_types |= BIT(INTEL_OUTPUT_DP);
3373                 pipe_config->lane_count =
3374                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3375
3376                 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder,
3377                                                &pipe_config->dp_m_n);
3378                 intel_cpu_transcoder_get_m2_n2(crtc, cpu_transcoder,
3379                                                &pipe_config->dp_m2_n2);
3380
3381                 if (DISPLAY_VER(dev_priv) >= 11) {
3382                         i915_reg_t dp_tp_ctl = dp_tp_ctl_reg(encoder, pipe_config);
3383
3384                         pipe_config->fec_enable =
3385                                 intel_de_read(dev_priv, dp_tp_ctl) & DP_TP_CTL_FEC_ENABLE;
3386
3387                         drm_dbg_kms(&dev_priv->drm,
3388                                     "[ENCODER:%d:%s] Fec status: %u\n",
3389                                     encoder->base.base.id, encoder->base.name,
3390                                     pipe_config->fec_enable);
3391                 }
3392
3393                 if (dig_port->lspcon.active && dig_port->dp.has_hdmi_sink)
3394                         pipe_config->infoframes.enable |=
3395                                 intel_lspcon_infoframes_enabled(encoder, pipe_config);
3396                 else
3397                         pipe_config->infoframes.enable |=
3398                                 intel_hdmi_infoframes_enabled(encoder, pipe_config);
3399                 break;
3400         case TRANS_DDI_MODE_SELECT_FDI_OR_128B132B:
3401                 if (!HAS_DP20(dev_priv)) {
3402                         /* FDI */
3403                         pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
3404                         break;
3405                 }
3406                 fallthrough; /* 128b/132b */
3407         case TRANS_DDI_MODE_SELECT_DP_MST:
3408                 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP_MST);
3409                 pipe_config->lane_count =
3410                         ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
3411
3412                 if (DISPLAY_VER(dev_priv) >= 12)
3413                         pipe_config->mst_master_transcoder =
3414                                         REG_FIELD_GET(TRANS_DDI_MST_TRANSPORT_SELECT_MASK, temp);
3415
3416                 intel_cpu_transcoder_get_m1_n1(crtc, cpu_transcoder,
3417                                                &pipe_config->dp_m_n);
3418
3419                 pipe_config->infoframes.enable |=
3420                         intel_hdmi_infoframes_enabled(encoder, pipe_config);
3421                 break;
3422         default:
3423                 break;
3424         }
3425 }
3426
3427 static void intel_ddi_get_config(struct intel_encoder *encoder,
3428                                  struct intel_crtc_state *pipe_config)
3429 {
3430         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3431         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
3432
3433         /* XXX: DSI transcoder paranoia */
3434         if (drm_WARN_ON(&dev_priv->drm, transcoder_is_dsi(cpu_transcoder)))
3435                 return;
3436
3437         intel_ddi_read_func_ctl(encoder, pipe_config);
3438
3439         intel_ddi_mso_get_config(encoder, pipe_config);
3440
3441         pipe_config->has_audio =
3442                 intel_ddi_is_audio_enabled(dev_priv, cpu_transcoder);
3443
3444         if (encoder->type == INTEL_OUTPUT_EDP)
3445                 intel_edp_fixup_vbt_bpp(encoder, pipe_config->pipe_bpp);
3446
3447         ddi_dotclock_get(pipe_config);
3448
3449         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3450                 pipe_config->lane_lat_optim_mask =
3451                         bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
3452
3453         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3454
3455         intel_hdmi_read_gcp_infoframe(encoder, pipe_config);
3456
3457         intel_read_infoframe(encoder, pipe_config,
3458                              HDMI_INFOFRAME_TYPE_AVI,
3459                              &pipe_config->infoframes.avi);
3460         intel_read_infoframe(encoder, pipe_config,
3461                              HDMI_INFOFRAME_TYPE_SPD,
3462                              &pipe_config->infoframes.spd);
3463         intel_read_infoframe(encoder, pipe_config,
3464                              HDMI_INFOFRAME_TYPE_VENDOR,
3465                              &pipe_config->infoframes.hdmi);
3466         intel_read_infoframe(encoder, pipe_config,
3467                              HDMI_INFOFRAME_TYPE_DRM,
3468                              &pipe_config->infoframes.drm);
3469
3470         if (DISPLAY_VER(dev_priv) >= 8)
3471                 bdw_get_trans_port_sync_config(pipe_config);
3472
3473         intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
3474         intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
3475
3476         intel_psr_get_config(encoder, pipe_config);
3477 }
3478
3479 void intel_ddi_get_clock(struct intel_encoder *encoder,
3480                          struct intel_crtc_state *crtc_state,
3481                          struct intel_shared_dpll *pll)
3482 {
3483         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3484         enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
3485         struct icl_port_dpll *port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
3486         bool pll_active;
3487
3488         if (drm_WARN_ON(&i915->drm, !pll))
3489                 return;
3490
3491         port_dpll->pll = pll;
3492         pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
3493         drm_WARN_ON(&i915->drm, !pll_active);
3494
3495         icl_set_active_port_dpll(crtc_state, port_dpll_id);
3496
3497         crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
3498                                                      &crtc_state->dpll_hw_state);
3499 }
3500
3501 static void dg2_ddi_get_config(struct intel_encoder *encoder,
3502                                 struct intel_crtc_state *crtc_state)
3503 {
3504         intel_mpllb_readout_hw_state(encoder, &crtc_state->mpllb_state);
3505         crtc_state->port_clock = intel_mpllb_calc_port_clock(encoder, &crtc_state->mpllb_state);
3506
3507         intel_ddi_get_config(encoder, crtc_state);
3508 }
3509
3510 static void adls_ddi_get_config(struct intel_encoder *encoder,
3511                                 struct intel_crtc_state *crtc_state)
3512 {
3513         intel_ddi_get_clock(encoder, crtc_state, adls_ddi_get_pll(encoder));
3514         intel_ddi_get_config(encoder, crtc_state);
3515 }
3516
3517 static void rkl_ddi_get_config(struct intel_encoder *encoder,
3518                                struct intel_crtc_state *crtc_state)
3519 {
3520         intel_ddi_get_clock(encoder, crtc_state, rkl_ddi_get_pll(encoder));
3521         intel_ddi_get_config(encoder, crtc_state);
3522 }
3523
3524 static void dg1_ddi_get_config(struct intel_encoder *encoder,
3525                                struct intel_crtc_state *crtc_state)
3526 {
3527         intel_ddi_get_clock(encoder, crtc_state, dg1_ddi_get_pll(encoder));
3528         intel_ddi_get_config(encoder, crtc_state);
3529 }
3530
3531 static void icl_ddi_combo_get_config(struct intel_encoder *encoder,
3532                                      struct intel_crtc_state *crtc_state)
3533 {
3534         intel_ddi_get_clock(encoder, crtc_state, icl_ddi_combo_get_pll(encoder));
3535         intel_ddi_get_config(encoder, crtc_state);
3536 }
3537
3538 static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,
3539                                  struct intel_crtc_state *crtc_state,
3540                                  struct intel_shared_dpll *pll)
3541 {
3542         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3543         enum icl_port_dpll_id port_dpll_id;
3544         struct icl_port_dpll *port_dpll;
3545         bool pll_active;
3546
3547         if (drm_WARN_ON(&i915->drm, !pll))
3548                 return;
3549
3550         if (intel_get_shared_dpll_id(i915, pll) == DPLL_ID_ICL_TBTPLL)
3551                 port_dpll_id = ICL_PORT_DPLL_DEFAULT;
3552         else
3553                 port_dpll_id = ICL_PORT_DPLL_MG_PHY;
3554
3555         port_dpll = &crtc_state->icl_port_dplls[port_dpll_id];
3556
3557         port_dpll->pll = pll;
3558         pll_active = intel_dpll_get_hw_state(i915, pll, &port_dpll->hw_state);
3559         drm_WARN_ON(&i915->drm, !pll_active);
3560
3561         icl_set_active_port_dpll(crtc_state, port_dpll_id);
3562
3563         if (intel_get_shared_dpll_id(i915, crtc_state->shared_dpll) == DPLL_ID_ICL_TBTPLL)
3564                 crtc_state->port_clock = icl_calc_tbt_pll_link(i915, encoder->port);
3565         else
3566                 crtc_state->port_clock = intel_dpll_get_freq(i915, crtc_state->shared_dpll,
3567                                                              &crtc_state->dpll_hw_state);
3568 }
3569
3570 static void icl_ddi_tc_get_config(struct intel_encoder *encoder,
3571                                   struct intel_crtc_state *crtc_state)
3572 {
3573         icl_ddi_tc_get_clock(encoder, crtc_state, icl_ddi_tc_get_pll(encoder));
3574         intel_ddi_get_config(encoder, crtc_state);
3575 }
3576
3577 static void bxt_ddi_get_config(struct intel_encoder *encoder,
3578                                struct intel_crtc_state *crtc_state)
3579 {
3580         intel_ddi_get_clock(encoder, crtc_state, bxt_ddi_get_pll(encoder));
3581         intel_ddi_get_config(encoder, crtc_state);
3582 }
3583
3584 static void skl_ddi_get_config(struct intel_encoder *encoder,
3585                                struct intel_crtc_state *crtc_state)
3586 {
3587         intel_ddi_get_clock(encoder, crtc_state, skl_ddi_get_pll(encoder));
3588         intel_ddi_get_config(encoder, crtc_state);
3589 }
3590
3591 void hsw_ddi_get_config(struct intel_encoder *encoder,
3592                         struct intel_crtc_state *crtc_state)
3593 {
3594         intel_ddi_get_clock(encoder, crtc_state, hsw_ddi_get_pll(encoder));
3595         intel_ddi_get_config(encoder, crtc_state);
3596 }
3597
3598 static void intel_ddi_sync_state(struct intel_encoder *encoder,
3599                                  const struct intel_crtc_state *crtc_state)
3600 {
3601         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3602         enum phy phy = intel_port_to_phy(i915, encoder->port);
3603
3604         if (intel_phy_is_tc(i915, phy))
3605                 intel_tc_port_sanitize(enc_to_dig_port(encoder));
3606
3607         if (crtc_state && intel_crtc_has_dp_encoder(crtc_state))
3608                 intel_dp_sync_state(encoder, crtc_state);
3609 }
3610
3611 static bool intel_ddi_initial_fastset_check(struct intel_encoder *encoder,
3612                                             struct intel_crtc_state *crtc_state)
3613 {
3614         if (intel_crtc_has_dp_encoder(crtc_state))
3615                 return intel_dp_initial_fastset_check(encoder, crtc_state);
3616
3617         return true;
3618 }
3619
3620 static enum intel_output_type
3621 intel_ddi_compute_output_type(struct intel_encoder *encoder,
3622                               struct intel_crtc_state *crtc_state,
3623                               struct drm_connector_state *conn_state)
3624 {
3625         switch (conn_state->connector->connector_type) {
3626         case DRM_MODE_CONNECTOR_HDMIA:
3627                 return INTEL_OUTPUT_HDMI;
3628         case DRM_MODE_CONNECTOR_eDP:
3629                 return INTEL_OUTPUT_EDP;
3630         case DRM_MODE_CONNECTOR_DisplayPort:
3631                 return INTEL_OUTPUT_DP;
3632         default:
3633                 MISSING_CASE(conn_state->connector->connector_type);
3634                 return INTEL_OUTPUT_UNUSED;
3635         }
3636 }
3637
3638 static int intel_ddi_compute_config(struct intel_encoder *encoder,
3639                                     struct intel_crtc_state *pipe_config,
3640                                     struct drm_connector_state *conn_state)
3641 {
3642         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
3643         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3644         enum port port = encoder->port;
3645         int ret;
3646
3647         if (HAS_TRANSCODER(dev_priv, TRANSCODER_EDP) && port == PORT_A)
3648                 pipe_config->cpu_transcoder = TRANSCODER_EDP;
3649
3650         if (intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) {
3651                 ret = intel_hdmi_compute_config(encoder, pipe_config, conn_state);
3652         } else {
3653                 ret = intel_dp_compute_config(encoder, pipe_config, conn_state);
3654         }
3655
3656         if (ret)
3657                 return ret;
3658
3659         if (IS_HASWELL(dev_priv) && crtc->pipe == PIPE_A &&
3660             pipe_config->cpu_transcoder == TRANSCODER_EDP)
3661                 pipe_config->pch_pfit.force_thru =
3662                         pipe_config->pch_pfit.enabled ||
3663                         pipe_config->crc_enabled;
3664
3665         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
3666                 pipe_config->lane_lat_optim_mask =
3667                         bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
3668
3669         intel_ddi_compute_min_voltage_level(dev_priv, pipe_config);
3670
3671         return 0;
3672 }
3673
3674 static bool mode_equal(const struct drm_display_mode *mode1,
3675                        const struct drm_display_mode *mode2)
3676 {
3677         return drm_mode_match(mode1, mode2,
3678                               DRM_MODE_MATCH_TIMINGS |
3679                               DRM_MODE_MATCH_FLAGS |
3680                               DRM_MODE_MATCH_3D_FLAGS) &&
3681                 mode1->clock == mode2->clock; /* we want an exact match */
3682 }
3683
3684 static bool m_n_equal(const struct intel_link_m_n *m_n_1,
3685                       const struct intel_link_m_n *m_n_2)
3686 {
3687         return m_n_1->tu == m_n_2->tu &&
3688                 m_n_1->data_m == m_n_2->data_m &&
3689                 m_n_1->data_n == m_n_2->data_n &&
3690                 m_n_1->link_m == m_n_2->link_m &&
3691                 m_n_1->link_n == m_n_2->link_n;
3692 }
3693
3694 static bool crtcs_port_sync_compatible(const struct intel_crtc_state *crtc_state1,
3695                                        const struct intel_crtc_state *crtc_state2)
3696 {
3697         return crtc_state1->hw.active && crtc_state2->hw.active &&
3698                 crtc_state1->output_types == crtc_state2->output_types &&
3699                 crtc_state1->output_format == crtc_state2->output_format &&
3700                 crtc_state1->lane_count == crtc_state2->lane_count &&
3701                 crtc_state1->port_clock == crtc_state2->port_clock &&
3702                 mode_equal(&crtc_state1->hw.adjusted_mode,
3703                            &crtc_state2->hw.adjusted_mode) &&
3704                 m_n_equal(&crtc_state1->dp_m_n, &crtc_state2->dp_m_n);
3705 }
3706
3707 static u8
3708 intel_ddi_port_sync_transcoders(const struct intel_crtc_state *ref_crtc_state,
3709                                 int tile_group_id)
3710 {
3711         struct drm_connector *connector;
3712         const struct drm_connector_state *conn_state;
3713         struct drm_i915_private *dev_priv = to_i915(ref_crtc_state->uapi.crtc->dev);
3714         struct intel_atomic_state *state =
3715                 to_intel_atomic_state(ref_crtc_state->uapi.state);
3716         u8 transcoders = 0;
3717         int i;
3718
3719         /*
3720          * We don't enable port sync on BDW due to missing w/as and
3721          * due to not having adjusted the modeset sequence appropriately.
3722          */
3723         if (DISPLAY_VER(dev_priv) < 9)
3724                 return 0;
3725
3726         if (!intel_crtc_has_type(ref_crtc_state, INTEL_OUTPUT_DP))
3727                 return 0;
3728
3729         for_each_new_connector_in_state(&state->base, connector, conn_state, i) {
3730                 struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
3731                 const struct intel_crtc_state *crtc_state;
3732
3733                 if (!crtc)
3734                         continue;
3735
3736                 if (!connector->has_tile ||
3737                     connector->tile_group->id !=
3738                     tile_group_id)
3739                         continue;
3740                 crtc_state = intel_atomic_get_new_crtc_state(state,
3741                                                              crtc);
3742                 if (!crtcs_port_sync_compatible(ref_crtc_state,
3743                                                 crtc_state))
3744                         continue;
3745                 transcoders |= BIT(crtc_state->cpu_transcoder);
3746         }
3747
3748         return transcoders;
3749 }
3750
3751 static int intel_ddi_compute_config_late(struct intel_encoder *encoder,
3752                                          struct intel_crtc_state *crtc_state,
3753                                          struct drm_connector_state *conn_state)
3754 {
3755         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3756         struct drm_connector *connector = conn_state->connector;
3757         u8 port_sync_transcoders = 0;
3758
3759         drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]",
3760                     encoder->base.base.id, encoder->base.name,
3761                     crtc_state->uapi.crtc->base.id, crtc_state->uapi.crtc->name);
3762
3763         if (connector->has_tile)
3764                 port_sync_transcoders = intel_ddi_port_sync_transcoders(crtc_state,
3765                                                                         connector->tile_group->id);
3766
3767         /*
3768          * EDP Transcoders cannot be ensalved
3769          * make them a master always when present
3770          */
3771         if (port_sync_transcoders & BIT(TRANSCODER_EDP))
3772                 crtc_state->master_transcoder = TRANSCODER_EDP;
3773         else
3774                 crtc_state->master_transcoder = ffs(port_sync_transcoders) - 1;
3775
3776         if (crtc_state->master_transcoder == crtc_state->cpu_transcoder) {
3777                 crtc_state->master_transcoder = INVALID_TRANSCODER;
3778                 crtc_state->sync_mode_slaves_mask =
3779                         port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder);
3780         }
3781
3782         return 0;
3783 }
3784
3785 static void intel_ddi_encoder_destroy(struct drm_encoder *encoder)
3786 {
3787         struct drm_i915_private *i915 = to_i915(encoder->dev);
3788         struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder));
3789         enum phy phy = intel_port_to_phy(i915, dig_port->base.port);
3790
3791         intel_dp_encoder_flush_work(encoder);
3792         if (intel_phy_is_tc(i915, phy))
3793                 intel_tc_port_flush_work(dig_port);
3794         intel_display_power_flush_work(i915);
3795
3796         drm_encoder_cleanup(encoder);
3797         kfree(dig_port->hdcp_port_data.streams);
3798         kfree(dig_port);
3799 }
3800
3801 static void intel_ddi_encoder_reset(struct drm_encoder *encoder)
3802 {
3803         struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
3804
3805         intel_dp->reset_link_params = true;
3806
3807         intel_pps_encoder_reset(intel_dp);
3808 }
3809
3810 static const struct drm_encoder_funcs intel_ddi_funcs = {
3811         .reset = intel_ddi_encoder_reset,
3812         .destroy = intel_ddi_encoder_destroy,
3813 };
3814
3815 static struct intel_connector *
3816 intel_ddi_init_dp_connector(struct intel_digital_port *dig_port)
3817 {
3818         struct intel_connector *connector;
3819         enum port port = dig_port->base.port;
3820
3821         connector = intel_connector_alloc();
3822         if (!connector)
3823                 return NULL;
3824
3825         dig_port->dp.output_reg = DDI_BUF_CTL(port);
3826         dig_port->dp.prepare_link_retrain = intel_ddi_prepare_link_retrain;
3827         dig_port->dp.set_link_train = intel_ddi_set_link_train;
3828         dig_port->dp.set_idle_link_train = intel_ddi_set_idle_link_train;
3829
3830         dig_port->dp.voltage_max = intel_ddi_dp_voltage_max;
3831         dig_port->dp.preemph_max = intel_ddi_dp_preemph_max;
3832
3833         if (!intel_dp_init_connector(dig_port, connector)) {
3834                 kfree(connector);
3835                 return NULL;
3836         }
3837
3838         if (dig_port->base.type == INTEL_OUTPUT_EDP) {
3839                 struct drm_device *dev = dig_port->base.base.dev;
3840                 struct drm_privacy_screen *privacy_screen;
3841
3842                 privacy_screen = drm_privacy_screen_get(dev->dev, NULL);
3843                 if (!IS_ERR(privacy_screen)) {
3844                         drm_connector_attach_privacy_screen_provider(&connector->base,
3845                                                                      privacy_screen);
3846                 } else if (PTR_ERR(privacy_screen) != -ENODEV) {
3847                         drm_warn(dev, "Error getting privacy-screen\n");
3848                 }
3849         }
3850
3851         return connector;
3852 }
3853
3854 static int modeset_pipe(struct drm_crtc *crtc,
3855                         struct drm_modeset_acquire_ctx *ctx)
3856 {
3857         struct drm_atomic_state *state;
3858         struct drm_crtc_state *crtc_state;
3859         int ret;
3860
3861         state = drm_atomic_state_alloc(crtc->dev);
3862         if (!state)
3863                 return -ENOMEM;
3864
3865         state->acquire_ctx = ctx;
3866
3867         crtc_state = drm_atomic_get_crtc_state(state, crtc);
3868         if (IS_ERR(crtc_state)) {
3869                 ret = PTR_ERR(crtc_state);
3870                 goto out;
3871         }
3872
3873         crtc_state->connectors_changed = true;
3874
3875         ret = drm_atomic_commit(state);
3876 out:
3877         drm_atomic_state_put(state);
3878
3879         return ret;
3880 }
3881
3882 static int intel_hdmi_reset_link(struct intel_encoder *encoder,
3883                                  struct drm_modeset_acquire_ctx *ctx)
3884 {
3885         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3886         struct intel_hdmi *hdmi = enc_to_intel_hdmi(encoder);
3887         struct intel_connector *connector = hdmi->attached_connector;
3888         struct i2c_adapter *adapter =
3889                 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
3890         struct drm_connector_state *conn_state;
3891         struct intel_crtc_state *crtc_state;
3892         struct intel_crtc *crtc;
3893         u8 config;
3894         int ret;
3895
3896         if (!connector || connector->base.status != connector_status_connected)
3897                 return 0;
3898
3899         ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex,
3900                                ctx);
3901         if (ret)
3902                 return ret;
3903
3904         conn_state = connector->base.state;
3905
3906         crtc = to_intel_crtc(conn_state->crtc);
3907         if (!crtc)
3908                 return 0;
3909
3910         ret = drm_modeset_lock(&crtc->base.mutex, ctx);
3911         if (ret)
3912                 return ret;
3913
3914         crtc_state = to_intel_crtc_state(crtc->base.state);
3915
3916         drm_WARN_ON(&dev_priv->drm,
3917                     !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI));
3918
3919         if (!crtc_state->hw.active)
3920                 return 0;
3921
3922         if (!crtc_state->hdmi_high_tmds_clock_ratio &&
3923             !crtc_state->hdmi_scrambling)
3924                 return 0;
3925
3926         if (conn_state->commit &&
3927             !try_wait_for_completion(&conn_state->commit->hw_done))
3928                 return 0;
3929
3930         ret = drm_scdc_readb(adapter, SCDC_TMDS_CONFIG, &config);
3931         if (ret < 0) {
3932                 drm_err(&dev_priv->drm, "Failed to read TMDS config: %d\n",
3933                         ret);
3934                 return 0;
3935         }
3936
3937         if (!!(config & SCDC_TMDS_BIT_CLOCK_RATIO_BY_40) ==
3938             crtc_state->hdmi_high_tmds_clock_ratio &&
3939             !!(config & SCDC_SCRAMBLING_ENABLE) ==
3940             crtc_state->hdmi_scrambling)
3941                 return 0;
3942
3943         /*
3944          * HDMI 2.0 says that one should not send scrambled data
3945          * prior to configuring the sink scrambling, and that
3946          * TMDS clock/data transmission should be suspended when
3947          * changing the TMDS clock rate in the sink. So let's
3948          * just do a full modeset here, even though some sinks
3949          * would be perfectly happy if were to just reconfigure
3950          * the SCDC settings on the fly.
3951          */
3952         return modeset_pipe(&crtc->base, ctx);
3953 }
3954
3955 static enum intel_hotplug_state
3956 intel_ddi_hotplug(struct intel_encoder *encoder,
3957                   struct intel_connector *connector)
3958 {
3959         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
3960         struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
3961         struct intel_dp *intel_dp = &dig_port->dp;
3962         enum phy phy = intel_port_to_phy(i915, encoder->port);
3963         bool is_tc = intel_phy_is_tc(i915, phy);
3964         struct drm_modeset_acquire_ctx ctx;
3965         enum intel_hotplug_state state;
3966         int ret;
3967
3968         if (intel_dp->compliance.test_active &&
3969             intel_dp->compliance.test_type == DP_TEST_LINK_PHY_TEST_PATTERN) {
3970                 intel_dp_phy_test(encoder);
3971                 /* just do the PHY test and nothing else */
3972                 return INTEL_HOTPLUG_UNCHANGED;
3973         }
3974
3975         state = intel_encoder_hotplug(encoder, connector);
3976
3977         drm_modeset_acquire_init(&ctx, 0);
3978
3979         for (;;) {
3980                 if (connector->base.connector_type == DRM_MODE_CONNECTOR_HDMIA)
3981                         ret = intel_hdmi_reset_link(encoder, &ctx);
3982                 else
3983                         ret = intel_dp_retrain_link(encoder, &ctx);
3984
3985                 if (ret == -EDEADLK) {
3986                         drm_modeset_backoff(&ctx);
3987                         continue;
3988                 }
3989
3990                 break;
3991         }
3992
3993         drm_modeset_drop_locks(&ctx);
3994         drm_modeset_acquire_fini(&ctx);
3995         drm_WARN(encoder->base.dev, ret,
3996                  "Acquiring modeset locks failed with %i\n", ret);
3997
3998         /*
3999          * Unpowered type-c dongles can take some time to boot and be
4000          * responsible, so here giving some time to those dongles to power up
4001          * and then retrying the probe.
4002          *
4003          * On many platforms the HDMI live state signal is known to be
4004          * unreliable, so we can't use it to detect if a sink is connected or
4005          * not. Instead we detect if it's connected based on whether we can
4006          * read the EDID or not. That in turn has a problem during disconnect,
4007          * since the HPD interrupt may be raised before the DDC lines get
4008          * disconnected (due to how the required length of DDC vs. HPD
4009          * connector pins are specified) and so we'll still be able to get a
4010          * valid EDID. To solve this schedule another detection cycle if this
4011          * time around we didn't detect any change in the sink's connection
4012          * status.
4013          *
4014          * Type-c connectors which get their HPD signal deasserted then
4015          * reasserted, without unplugging/replugging the sink from the
4016          * connector, introduce a delay until the AUX channel communication
4017          * becomes functional. Retry the detection for 5 seconds on type-c
4018          * connectors to account for this delay.
4019          */
4020         if (state == INTEL_HOTPLUG_UNCHANGED &&
4021             connector->hotplug_retries < (is_tc ? 5 : 1) &&
4022             !dig_port->dp.is_mst)
4023                 state = INTEL_HOTPLUG_RETRY;
4024
4025         return state;
4026 }
4027
4028 static bool lpt_digital_port_connected(struct intel_encoder *encoder)
4029 {
4030         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4031         u32 bit = dev_priv->hotplug.pch_hpd[encoder->hpd_pin];
4032
4033         return intel_de_read(dev_priv, SDEISR) & bit;
4034 }
4035
4036 static bool hsw_digital_port_connected(struct intel_encoder *encoder)
4037 {
4038         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4039         u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
4040
4041         return intel_de_read(dev_priv, DEISR) & bit;
4042 }
4043
4044 static bool bdw_digital_port_connected(struct intel_encoder *encoder)
4045 {
4046         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4047         u32 bit = dev_priv->hotplug.hpd[encoder->hpd_pin];
4048
4049         return intel_de_read(dev_priv, GEN8_DE_PORT_ISR) & bit;
4050 }
4051
4052 static struct intel_connector *
4053 intel_ddi_init_hdmi_connector(struct intel_digital_port *dig_port)
4054 {
4055         struct intel_connector *connector;
4056         enum port port = dig_port->base.port;
4057
4058         connector = intel_connector_alloc();
4059         if (!connector)
4060                 return NULL;
4061
4062         dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
4063         intel_hdmi_init_connector(dig_port, connector);
4064
4065         return connector;
4066 }
4067
4068 static bool intel_ddi_a_force_4_lanes(struct intel_digital_port *dig_port)
4069 {
4070         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4071
4072         if (dig_port->base.port != PORT_A)
4073                 return false;
4074
4075         if (dig_port->saved_port_bits & DDI_A_4_LANES)
4076                 return false;
4077
4078         /* Broxton/Geminilake: Bspec says that DDI_A_4_LANES is the only
4079          *                     supported configuration
4080          */
4081         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
4082                 return true;
4083
4084         return false;
4085 }
4086
4087 static int
4088 intel_ddi_max_lanes(struct intel_digital_port *dig_port)
4089 {
4090         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
4091         enum port port = dig_port->base.port;
4092         int max_lanes = 4;
4093
4094         if (DISPLAY_VER(dev_priv) >= 11)
4095                 return max_lanes;
4096
4097         if (port == PORT_A || port == PORT_E) {
4098                 if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
4099                         max_lanes = port == PORT_A ? 4 : 0;
4100                 else
4101                         /* Both A and E share 2 lanes */
4102                         max_lanes = 2;
4103         }
4104
4105         /*
4106          * Some BIOS might fail to set this bit on port A if eDP
4107          * wasn't lit up at boot.  Force this bit set when needed
4108          * so we use the proper lane count for our calculations.
4109          */
4110         if (intel_ddi_a_force_4_lanes(dig_port)) {
4111                 drm_dbg_kms(&dev_priv->drm,
4112                             "Forcing DDI_A_4_LANES for port A\n");
4113                 dig_port->saved_port_bits |= DDI_A_4_LANES;
4114                 max_lanes = 4;
4115         }
4116
4117         return max_lanes;
4118 }
4119
4120 static bool hti_uses_phy(struct drm_i915_private *i915, enum phy phy)
4121 {
4122         return i915->hti_state & HDPORT_ENABLED &&
4123                i915->hti_state & HDPORT_DDI_USED(phy);
4124 }
4125
4126 static enum hpd_pin xelpd_hpd_pin(struct drm_i915_private *dev_priv,
4127                                   enum port port)
4128 {
4129         if (port >= PORT_D_XELPD)
4130                 return HPD_PORT_D + port - PORT_D_XELPD;
4131         else if (port >= PORT_TC1)
4132                 return HPD_PORT_TC1 + port - PORT_TC1;
4133         else
4134                 return HPD_PORT_A + port - PORT_A;
4135 }
4136
4137 static enum hpd_pin dg1_hpd_pin(struct drm_i915_private *dev_priv,
4138                                 enum port port)
4139 {
4140         if (port >= PORT_TC1)
4141                 return HPD_PORT_C + port - PORT_TC1;
4142         else
4143                 return HPD_PORT_A + port - PORT_A;
4144 }
4145
4146 static enum hpd_pin tgl_hpd_pin(struct drm_i915_private *dev_priv,
4147                                 enum port port)
4148 {
4149         if (port >= PORT_TC1)
4150                 return HPD_PORT_TC1 + port - PORT_TC1;
4151         else
4152                 return HPD_PORT_A + port - PORT_A;
4153 }
4154
4155 static enum hpd_pin rkl_hpd_pin(struct drm_i915_private *dev_priv,
4156                                 enum port port)
4157 {
4158         if (HAS_PCH_TGP(dev_priv))
4159                 return tgl_hpd_pin(dev_priv, port);
4160
4161         if (port >= PORT_TC1)
4162                 return HPD_PORT_C + port - PORT_TC1;
4163         else
4164                 return HPD_PORT_A + port - PORT_A;
4165 }
4166
4167 static enum hpd_pin icl_hpd_pin(struct drm_i915_private *dev_priv,
4168                                 enum port port)
4169 {
4170         if (port >= PORT_C)
4171                 return HPD_PORT_TC1 + port - PORT_C;
4172         else
4173                 return HPD_PORT_A + port - PORT_A;
4174 }
4175
4176 static enum hpd_pin ehl_hpd_pin(struct drm_i915_private *dev_priv,
4177                                 enum port port)
4178 {
4179         if (port == PORT_D)
4180                 return HPD_PORT_A;
4181
4182         if (HAS_PCH_MCC(dev_priv))
4183                 return icl_hpd_pin(dev_priv, port);
4184
4185         return HPD_PORT_A + port - PORT_A;
4186 }
4187
4188 static enum hpd_pin skl_hpd_pin(struct drm_i915_private *dev_priv, enum port port)
4189 {
4190         if (HAS_PCH_TGP(dev_priv))
4191                 return icl_hpd_pin(dev_priv, port);
4192
4193         return HPD_PORT_A + port - PORT_A;
4194 }
4195
4196 static bool intel_ddi_is_tc(struct drm_i915_private *i915, enum port port)
4197 {
4198         if (DISPLAY_VER(i915) >= 12)
4199                 return port >= PORT_TC1;
4200         else if (DISPLAY_VER(i915) >= 11)
4201                 return port >= PORT_C;
4202         else
4203                 return false;
4204 }
4205
4206 static void intel_ddi_encoder_suspend(struct intel_encoder *encoder)
4207 {
4208         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4209         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4210         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4211         enum phy phy = intel_port_to_phy(i915, encoder->port);
4212
4213         intel_dp_encoder_suspend(encoder);
4214
4215         if (!intel_phy_is_tc(i915, phy))
4216                 return;
4217
4218         intel_tc_port_flush_work(dig_port);
4219 }
4220
4221 static void intel_ddi_encoder_shutdown(struct intel_encoder *encoder)
4222 {
4223         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4224         struct drm_i915_private *i915 = dp_to_i915(intel_dp);
4225         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4226         enum phy phy = intel_port_to_phy(i915, encoder->port);
4227
4228         intel_dp_encoder_shutdown(encoder);
4229         intel_hdmi_encoder_shutdown(encoder);
4230
4231         if (!intel_phy_is_tc(i915, phy))
4232                 return;
4233
4234         intel_tc_port_flush_work(dig_port);
4235 }
4236
4237 #define port_tc_name(port) ((port) - PORT_TC1 + '1')
4238 #define tc_port_name(tc_port) ((tc_port) - TC_PORT_1 + '1')
4239
4240 void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
4241 {
4242         struct intel_digital_port *dig_port;
4243         struct intel_encoder *encoder;
4244         const struct intel_bios_encoder_data *devdata;
4245         bool init_hdmi, init_dp;
4246         enum phy phy = intel_port_to_phy(dev_priv, port);
4247
4248         /*
4249          * On platforms with HTI (aka HDPORT), if it's enabled at boot it may
4250          * have taken over some of the PHYs and made them unavailable to the
4251          * driver.  In that case we should skip initializing the corresponding
4252          * outputs.
4253          */
4254         if (hti_uses_phy(dev_priv, phy)) {
4255                 drm_dbg_kms(&dev_priv->drm, "PORT %c / PHY %c reserved by HTI\n",
4256                             port_name(port), phy_name(phy));
4257                 return;
4258         }
4259
4260         devdata = intel_bios_encoder_data_lookup(dev_priv, port);
4261         if (!devdata) {
4262                 drm_dbg_kms(&dev_priv->drm,
4263                             "VBT says port %c is not present\n",
4264                             port_name(port));
4265                 return;
4266         }
4267
4268         init_hdmi = intel_bios_encoder_supports_dvi(devdata) ||
4269                 intel_bios_encoder_supports_hdmi(devdata);
4270         init_dp = intel_bios_encoder_supports_dp(devdata);
4271
4272         if (intel_bios_is_lspcon_present(dev_priv, port)) {
4273                 /*
4274                  * Lspcon device needs to be driven with DP connector
4275                  * with special detection sequence. So make sure DP
4276                  * is initialized before lspcon.
4277                  */
4278                 init_dp = true;
4279                 init_hdmi = false;
4280                 drm_dbg_kms(&dev_priv->drm, "VBT says port %c has lspcon\n",
4281                             port_name(port));
4282         }
4283
4284         if (!init_dp && !init_hdmi) {
4285                 drm_dbg_kms(&dev_priv->drm,
4286                             "VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
4287                             port_name(port));
4288                 return;
4289         }
4290
4291         if (intel_phy_is_snps(dev_priv, phy) &&
4292             dev_priv->snps_phy_failed_calibration & BIT(phy)) {
4293                 drm_dbg_kms(&dev_priv->drm,
4294                             "SNPS PHY %c failed to calibrate, proceeding anyway\n",
4295                             phy_name(phy));
4296         }
4297
4298         dig_port = kzalloc(sizeof(*dig_port), GFP_KERNEL);
4299         if (!dig_port)
4300                 return;
4301
4302         encoder = &dig_port->base;
4303         encoder->devdata = devdata;
4304
4305         if (DISPLAY_VER(dev_priv) >= 13 && port >= PORT_D_XELPD) {
4306                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4307                                  DRM_MODE_ENCODER_TMDS,
4308                                  "DDI %c/PHY %c",
4309                                  port_name(port - PORT_D_XELPD + PORT_D),
4310                                  phy_name(phy));
4311         } else if (DISPLAY_VER(dev_priv) >= 12) {
4312                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4313
4314                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4315                                  DRM_MODE_ENCODER_TMDS,
4316                                  "DDI %s%c/PHY %s%c",
4317                                  port >= PORT_TC1 ? "TC" : "",
4318                                  port >= PORT_TC1 ? port_tc_name(port) : port_name(port),
4319                                  tc_port != TC_PORT_NONE ? "TC" : "",
4320                                  tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
4321         } else if (DISPLAY_VER(dev_priv) >= 11) {
4322                 enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
4323
4324                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4325                                  DRM_MODE_ENCODER_TMDS,
4326                                  "DDI %c%s/PHY %s%c",
4327                                  port_name(port),
4328                                  port >= PORT_C ? " (TC)" : "",
4329                                  tc_port != TC_PORT_NONE ? "TC" : "",
4330                                  tc_port != TC_PORT_NONE ? tc_port_name(tc_port) : phy_name(phy));
4331         } else {
4332                 drm_encoder_init(&dev_priv->drm, &encoder->base, &intel_ddi_funcs,
4333                                  DRM_MODE_ENCODER_TMDS,
4334                                  "DDI %c/PHY %c", port_name(port),  phy_name(phy));
4335         }
4336
4337         mutex_init(&dig_port->hdcp_mutex);
4338         dig_port->num_hdcp_streams = 0;
4339
4340         encoder->hotplug = intel_ddi_hotplug;
4341         encoder->compute_output_type = intel_ddi_compute_output_type;
4342         encoder->compute_config = intel_ddi_compute_config;
4343         encoder->compute_config_late = intel_ddi_compute_config_late;
4344         encoder->enable = intel_enable_ddi;
4345         encoder->pre_pll_enable = intel_ddi_pre_pll_enable;
4346         encoder->pre_enable = intel_ddi_pre_enable;
4347         encoder->disable = intel_disable_ddi;
4348         encoder->post_disable = intel_ddi_post_disable;
4349         encoder->update_pipe = intel_ddi_update_pipe;
4350         encoder->get_hw_state = intel_ddi_get_hw_state;
4351         encoder->sync_state = intel_ddi_sync_state;
4352         encoder->initial_fastset_check = intel_ddi_initial_fastset_check;
4353         encoder->suspend = intel_ddi_encoder_suspend;
4354         encoder->shutdown = intel_ddi_encoder_shutdown;
4355         encoder->get_power_domains = intel_ddi_get_power_domains;
4356
4357         encoder->type = INTEL_OUTPUT_DDI;
4358         encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port);
4359         encoder->port = port;
4360         encoder->cloneable = 0;
4361         encoder->pipe_mask = ~0;
4362
4363         if (IS_DG2(dev_priv)) {
4364                 encoder->enable_clock = intel_mpllb_enable;
4365                 encoder->disable_clock = intel_mpllb_disable;
4366                 encoder->get_config = dg2_ddi_get_config;
4367         } else if (IS_ALDERLAKE_S(dev_priv)) {
4368                 encoder->enable_clock = adls_ddi_enable_clock;
4369                 encoder->disable_clock = adls_ddi_disable_clock;
4370                 encoder->is_clock_enabled = adls_ddi_is_clock_enabled;
4371                 encoder->get_config = adls_ddi_get_config;
4372         } else if (IS_ROCKETLAKE(dev_priv)) {
4373                 encoder->enable_clock = rkl_ddi_enable_clock;
4374                 encoder->disable_clock = rkl_ddi_disable_clock;
4375                 encoder->is_clock_enabled = rkl_ddi_is_clock_enabled;
4376                 encoder->get_config = rkl_ddi_get_config;
4377         } else if (IS_DG1(dev_priv)) {
4378                 encoder->enable_clock = dg1_ddi_enable_clock;
4379                 encoder->disable_clock = dg1_ddi_disable_clock;
4380                 encoder->is_clock_enabled = dg1_ddi_is_clock_enabled;
4381                 encoder->get_config = dg1_ddi_get_config;
4382         } else if (IS_JSL_EHL(dev_priv)) {
4383                 if (intel_ddi_is_tc(dev_priv, port)) {
4384                         encoder->enable_clock = jsl_ddi_tc_enable_clock;
4385                         encoder->disable_clock = jsl_ddi_tc_disable_clock;
4386                         encoder->is_clock_enabled = jsl_ddi_tc_is_clock_enabled;
4387                         encoder->get_config = icl_ddi_combo_get_config;
4388                 } else {
4389                         encoder->enable_clock = icl_ddi_combo_enable_clock;
4390                         encoder->disable_clock = icl_ddi_combo_disable_clock;
4391                         encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
4392                         encoder->get_config = icl_ddi_combo_get_config;
4393                 }
4394         } else if (DISPLAY_VER(dev_priv) >= 11) {
4395                 if (intel_ddi_is_tc(dev_priv, port)) {
4396                         encoder->enable_clock = icl_ddi_tc_enable_clock;
4397                         encoder->disable_clock = icl_ddi_tc_disable_clock;
4398                         encoder->is_clock_enabled = icl_ddi_tc_is_clock_enabled;
4399                         encoder->get_config = icl_ddi_tc_get_config;
4400                 } else {
4401                         encoder->enable_clock = icl_ddi_combo_enable_clock;
4402                         encoder->disable_clock = icl_ddi_combo_disable_clock;
4403                         encoder->is_clock_enabled = icl_ddi_combo_is_clock_enabled;
4404                         encoder->get_config = icl_ddi_combo_get_config;
4405                 }
4406         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
4407                 /* BXT/GLK have fixed PLL->port mapping */
4408                 encoder->get_config = bxt_ddi_get_config;
4409         } else if (DISPLAY_VER(dev_priv) == 9) {
4410                 encoder->enable_clock = skl_ddi_enable_clock;
4411                 encoder->disable_clock = skl_ddi_disable_clock;
4412                 encoder->is_clock_enabled = skl_ddi_is_clock_enabled;
4413                 encoder->get_config = skl_ddi_get_config;
4414         } else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
4415                 encoder->enable_clock = hsw_ddi_enable_clock;
4416                 encoder->disable_clock = hsw_ddi_disable_clock;
4417                 encoder->is_clock_enabled = hsw_ddi_is_clock_enabled;
4418                 encoder->get_config = hsw_ddi_get_config;
4419         }
4420
4421         if (IS_DG2(dev_priv)) {
4422                 encoder->set_signal_levels = intel_snps_phy_set_signal_levels;
4423         } else if (DISPLAY_VER(dev_priv) >= 12) {
4424                 if (intel_phy_is_combo(dev_priv, phy))
4425                         encoder->set_signal_levels = icl_combo_phy_set_signal_levels;
4426                 else
4427                         encoder->set_signal_levels = tgl_dkl_phy_set_signal_levels;
4428         } else if (DISPLAY_VER(dev_priv) >= 11) {
4429                 if (intel_phy_is_combo(dev_priv, phy))
4430                         encoder->set_signal_levels = icl_combo_phy_set_signal_levels;
4431                 else
4432                         encoder->set_signal_levels = icl_mg_phy_set_signal_levels;
4433         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
4434                 encoder->set_signal_levels = bxt_ddi_phy_set_signal_levels;
4435         } else {
4436                 encoder->set_signal_levels = hsw_set_signal_levels;
4437         }
4438
4439         intel_ddi_buf_trans_init(encoder);
4440
4441         if (DISPLAY_VER(dev_priv) >= 13)
4442                 encoder->hpd_pin = xelpd_hpd_pin(dev_priv, port);
4443         else if (IS_DG1(dev_priv))
4444                 encoder->hpd_pin = dg1_hpd_pin(dev_priv, port);
4445         else if (IS_ROCKETLAKE(dev_priv))
4446                 encoder->hpd_pin = rkl_hpd_pin(dev_priv, port);
4447         else if (DISPLAY_VER(dev_priv) >= 12)
4448                 encoder->hpd_pin = tgl_hpd_pin(dev_priv, port);
4449         else if (IS_JSL_EHL(dev_priv))
4450                 encoder->hpd_pin = ehl_hpd_pin(dev_priv, port);
4451         else if (DISPLAY_VER(dev_priv) == 11)
4452                 encoder->hpd_pin = icl_hpd_pin(dev_priv, port);
4453         else if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
4454                 encoder->hpd_pin = skl_hpd_pin(dev_priv, port);
4455         else
4456                 encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port);
4457
4458         if (DISPLAY_VER(dev_priv) >= 11)
4459                 dig_port->saved_port_bits =
4460                         intel_de_read(dev_priv, DDI_BUF_CTL(port))
4461                         & DDI_BUF_PORT_REVERSAL;
4462         else
4463                 dig_port->saved_port_bits =
4464                         intel_de_read(dev_priv, DDI_BUF_CTL(port))
4465                         & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
4466
4467         if (intel_bios_is_lane_reversal_needed(dev_priv, port))
4468                 dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL;
4469
4470         dig_port->dp.output_reg = INVALID_MMIO_REG;
4471         dig_port->max_lanes = intel_ddi_max_lanes(dig_port);
4472         dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port);
4473
4474         if (intel_phy_is_tc(dev_priv, phy)) {
4475                 bool is_legacy =
4476                         !intel_bios_encoder_supports_typec_usb(devdata) &&
4477                         !intel_bios_encoder_supports_tbt(devdata);
4478
4479                 intel_tc_port_init(dig_port, is_legacy);
4480
4481                 encoder->update_prepare = intel_ddi_update_prepare;
4482                 encoder->update_complete = intel_ddi_update_complete;
4483         }
4484
4485         drm_WARN_ON(&dev_priv->drm, port > PORT_I);
4486         dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port);
4487
4488         if (init_dp) {
4489                 if (!intel_ddi_init_dp_connector(dig_port))
4490                         goto err;
4491
4492                 dig_port->hpd_pulse = intel_dp_hpd_pulse;
4493
4494                 if (dig_port->dp.mso_link_count)
4495                         encoder->pipe_mask = intel_ddi_splitter_pipe_mask(dev_priv);
4496         }
4497
4498         /* In theory we don't need the encoder->type check, but leave it just in
4499          * case we have some really bad VBTs... */
4500         if (encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
4501                 if (!intel_ddi_init_hdmi_connector(dig_port))
4502                         goto err;
4503         }
4504
4505         if (DISPLAY_VER(dev_priv) >= 11) {
4506                 if (intel_phy_is_tc(dev_priv, phy))
4507                         dig_port->connected = intel_tc_port_connected;
4508                 else
4509                         dig_port->connected = lpt_digital_port_connected;
4510         } else if (DISPLAY_VER(dev_priv) >= 8) {
4511                 if (port == PORT_A || IS_GEMINILAKE(dev_priv) ||
4512                     IS_BROXTON(dev_priv))
4513                         dig_port->connected = bdw_digital_port_connected;
4514                 else
4515                         dig_port->connected = lpt_digital_port_connected;
4516         } else {
4517                 if (port == PORT_A)
4518                         dig_port->connected = hsw_digital_port_connected;
4519                 else
4520                         dig_port->connected = lpt_digital_port_connected;
4521         }
4522
4523         intel_infoframe_init(dig_port);
4524
4525         return;
4526
4527 err:
4528         drm_encoder_cleanup(&encoder->base);
4529         kfree(dig_port);
4530 }