drivers/gpu/drm/i915/display/intel_atomic.c

   1 /*
   2  * Copyright © 2015 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: atomic modeset support
  26  *
  27  * The functions here implement the state management and hardware programming
  28  * dispatch required by the atomic modeset infrastructure.
  29  * See intel_atomic_plane.c for the plane-specific atomic functionality.
  30  */
  31
  32 #include <drm/drm_atomic.h>
  33 #include <drm/drm_atomic_helper.h>
  34 #include <drm/drm_fourcc.h>
  35 #include <drm/drm_plane_helper.h>
  36
  37 #include "intel_atomic.h"
  38 #include "intel_cdclk.h"
  39 #include "intel_display_types.h"
  40 #include "intel_global_state.h"
  41 #include "intel_hdcp.h"
  42 #include "intel_psr.h"
  43 #include "skl_universal_plane.h"
  44
  45 /**
  46  * intel_digital_connector_atomic_get_property - hook for connector->atomic_get_property.
  47  * @connector: Connector to get the property for.
  48  * @state: Connector state to retrieve the property from.
  49  * @property: Property to retrieve.
  50  * @val: Return value for the property.
  51  *
  52  * Returns the atomic property value for a digital connector.
  53  */
  54 int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
  55                                                 const struct drm_connector_state *state,
  56                                                 struct drm_property *property,
  57                                                 u64 *val)
  58 {
  59         struct drm_device *dev = connector->dev;
  60         struct drm_i915_private *dev_priv = to_i915(dev);
  61         struct intel_digital_connector_state *intel_conn_state =
  62                 to_intel_digital_connector_state(state);
  63
  64         if (property == dev_priv->force_audio_property)
  65                 *val = intel_conn_state->force_audio;
  66         else if (property == dev_priv->broadcast_rgb_property)
  67                 *val = intel_conn_state->broadcast_rgb;
  68         else {
  69                 drm_dbg_atomic(&dev_priv->drm,
  70                                "Unknown property [PROP:%d:%s]\n",
  71                                property->base.id, property->name);
  72                 return -EINVAL;
  73         }
  74
  75         return 0;
  76 }
  77
  78 /**
  79  * intel_digital_connector_atomic_set_property - hook for connector->atomic_set_property.
  80  * @connector: Connector to set the property for.
  81  * @state: Connector state to set the property on.
  82  * @property: Property to set.
  83  * @val: New value for the property.
  84  *
  85  * Sets the atomic property value for a digital connector.
  86  */
  87 int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
  88                                                 struct drm_connector_state *state,
  89                                                 struct drm_property *property,
  90                                                 u64 val)
  91 {
  92         struct drm_device *dev = connector->dev;
  93         struct drm_i915_private *dev_priv = to_i915(dev);
  94         struct intel_digital_connector_state *intel_conn_state =
  95                 to_intel_digital_connector_state(state);
  96
  97         if (property == dev_priv->force_audio_property) {
  98                 intel_conn_state->force_audio = val;
  99                 return 0;
 100         }
 101
 102         if (property == dev_priv->broadcast_rgb_property) {
 103                 intel_conn_state->broadcast_rgb = val;
 104                 return 0;
 105         }
 106
 107         drm_dbg_atomic(&dev_priv->drm, "Unknown property [PROP:%d:%s]\n",
 108                        property->base.id, property->name);
 109         return -EINVAL;
 110 }
 111
 112 int intel_digital_connector_atomic_check(struct drm_connector *conn,
 113                                          struct drm_atomic_state *state)
 114 {
 115         struct drm_connector_state *new_state =
 116                 drm_atomic_get_new_connector_state(state, conn);
 117         struct intel_digital_connector_state *new_conn_state =
 118                 to_intel_digital_connector_state(new_state);
 119         struct drm_connector_state *old_state =
 120                 drm_atomic_get_old_connector_state(state, conn);
 121         struct intel_digital_connector_state *old_conn_state =
 122                 to_intel_digital_connector_state(old_state);
 123         struct drm_crtc_state *crtc_state;
 124
 125         intel_hdcp_atomic_check(conn, old_state, new_state);
 126
 127         if (!new_state->crtc)
 128                 return 0;
 129
 130         crtc_state = drm_atomic_get_new_crtc_state(state, new_state->crtc);
 131
 132         /*
 133          * These properties are handled by fastset, and might not end
 134          * up in a modeset.
 135          */
 136         if (new_conn_state->force_audio != old_conn_state->force_audio ||
 137             new_conn_state->broadcast_rgb != old_conn_state->broadcast_rgb ||
 138             new_conn_state->base.colorspace != old_conn_state->base.colorspace ||
 139             new_conn_state->base.picture_aspect_ratio != old_conn_state->base.picture_aspect_ratio ||
 140             new_conn_state->base.content_type != old_conn_state->base.content_type ||
 141             new_conn_state->base.scaling_mode != old_conn_state->base.scaling_mode ||
 142             !drm_connector_atomic_hdr_metadata_equal(old_state, new_state))
 143                 crtc_state->mode_changed = true;
 144
 145         return 0;
 146 }
 147
 148 /**
 149  * intel_digital_connector_duplicate_state - duplicate connector state
 150  * @connector: digital connector
 151  *
 152  * Allocates and returns a copy of the connector state (both common and
 153  * digital connector specific) for the specified connector.
 154  *
 155  * Returns: The newly allocated connector state, or NULL on failure.
 156  */
 157 struct drm_connector_state *
 158 intel_digital_connector_duplicate_state(struct drm_connector *connector)
 159 {
 160         struct intel_digital_connector_state *state;
 161
 162         state = kmemdup(connector->state, sizeof(*state), GFP_KERNEL);
 163         if (!state)
 164                 return NULL;
 165
 166         __drm_atomic_helper_connector_duplicate_state(connector, &state->base);
 167         return &state->base;
 168 }
 169
 170 /**
 171  * intel_connector_needs_modeset - check if connector needs a modeset
 172  * @state: the atomic state corresponding to this modeset
 173  * @connector: the connector
 174  */
 175 bool
 176 intel_connector_needs_modeset(struct intel_atomic_state *state,
 177                               struct drm_connector *connector)
 178 {
 179         const struct drm_connector_state *old_conn_state, *new_conn_state;
 180
 181         old_conn_state = drm_atomic_get_old_connector_state(&state->base, connector);
 182         new_conn_state = drm_atomic_get_new_connector_state(&state->base, connector);
 183
 184         return old_conn_state->crtc != new_conn_state->crtc ||
 185                (new_conn_state->crtc &&
 186                 drm_atomic_crtc_needs_modeset(drm_atomic_get_new_crtc_state(&state->base,
 187                                                                             new_conn_state->crtc)));
 188 }
 189
 190 struct intel_digital_connector_state *
 191 intel_atomic_get_digital_connector_state(struct intel_atomic_state *state,
 192                                          struct intel_connector *connector)
 193 {
 194         struct drm_connector_state *conn_state;
 195
 196         conn_state = drm_atomic_get_connector_state(&state->base,
 197                                                     &connector->base);
 198         if (IS_ERR(conn_state))
 199                 return ERR_CAST(conn_state);
 200
 201         return to_intel_digital_connector_state(conn_state);
 202 }
 203
 204 /**
 205  * intel_crtc_duplicate_state - duplicate crtc state
 206  * @crtc: drm crtc
 207  *
 208  * Allocates and returns a copy of the crtc state (both common and
 209  * Intel-specific) for the specified crtc.
 210  *
 211  * Returns: The newly allocated crtc state, or NULL on failure.
 212  */
 213 struct drm_crtc_state *
 214 intel_crtc_duplicate_state(struct drm_crtc *crtc)
 215 {
 216         const struct intel_crtc_state *old_crtc_state = to_intel_crtc_state(crtc->state);
 217         struct intel_crtc_state *crtc_state;
 218
 219         crtc_state = kmemdup(old_crtc_state, sizeof(*crtc_state), GFP_KERNEL);
 220         if (!crtc_state)
 221                 return NULL;
 222
 223         __drm_atomic_helper_crtc_duplicate_state(crtc, &crtc_state->uapi);
 224
 225         /* copy color blobs */
 226         if (crtc_state->hw.degamma_lut)
 227                 drm_property_blob_get(crtc_state->hw.degamma_lut);
 228         if (crtc_state->hw.ctm)
 229                 drm_property_blob_get(crtc_state->hw.ctm);
 230         if (crtc_state->hw.gamma_lut)
 231                 drm_property_blob_get(crtc_state->hw.gamma_lut);
 232
 233         crtc_state->update_pipe = false;
 234         crtc_state->disable_lp_wm = false;
 235         crtc_state->disable_cxsr = false;
 236         crtc_state->update_wm_pre = false;
 237         crtc_state->update_wm_post = false;
 238         crtc_state->fifo_changed = false;
 239         crtc_state->preload_luts = false;
 240         crtc_state->inherited = false;
 241         crtc_state->wm.need_postvbl_update = false;
 242         crtc_state->fb_bits = 0;
 243         crtc_state->update_planes = 0;
 244         crtc_state->dsb = NULL;
 245
 246         return &crtc_state->uapi;
 247 }
 248
 249 static void intel_crtc_put_color_blobs(struct intel_crtc_state *crtc_state)
 250 {
 251         drm_property_blob_put(crtc_state->hw.degamma_lut);
 252         drm_property_blob_put(crtc_state->hw.gamma_lut);
 253         drm_property_blob_put(crtc_state->hw.ctm);
 254 }
 255
 256 void intel_crtc_free_hw_state(struct intel_crtc_state *crtc_state)
 257 {
 258         intel_crtc_put_color_blobs(crtc_state);
 259 }
 260
 261 void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state,
 262                                  const struct intel_crtc_state *from_crtc_state)
 263 {
 264         drm_property_replace_blob(&crtc_state->hw.degamma_lut,
 265                                   from_crtc_state->uapi.degamma_lut);
 266         drm_property_replace_blob(&crtc_state->hw.gamma_lut,
 267                                   from_crtc_state->uapi.gamma_lut);
 268         drm_property_replace_blob(&crtc_state->hw.ctm,
 269                                   from_crtc_state->uapi.ctm);
 270 }
 271
 272 /**
 273  * intel_crtc_destroy_state - destroy crtc state
 274  * @crtc: drm crtc
 275  * @state: the state to destroy
 276  *
 277  * Destroys the crtc state (both common and Intel-specific) for the
 278  * specified crtc.
 279  */
 280 void
 281 intel_crtc_destroy_state(struct drm_crtc *crtc,
 282                          struct drm_crtc_state *state)
 283 {
 284         struct intel_crtc_state *crtc_state = to_intel_crtc_state(state);
 285
 286         drm_WARN_ON(crtc->dev, crtc_state->dsb);
 287
 288         __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
 289         intel_crtc_free_hw_state(crtc_state);
 290         kfree(crtc_state);
 291 }
 292
 293 static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
 294                                       int num_scalers_need, struct intel_crtc *intel_crtc,
 295                                       const char *name, int idx,
 296                                       struct intel_plane_state *plane_state,
 297                                       int *scaler_id)
 298 {
 299         struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
 300         int j;
 301         u32 mode;
 302
 303         if (*scaler_id < 0) {
 304                 /* find a free scaler */
 305                 for (j = 0; j < intel_crtc->num_scalers; j++) {
 306                         if (scaler_state->scalers[j].in_use)
 307                                 continue;
 308
 309                         *scaler_id = j;
 310                         scaler_state->scalers[*scaler_id].in_use = 1;
 311                         break;
 312                 }
 313         }
 314
 315         if (drm_WARN(&dev_priv->drm, *scaler_id < 0,
 316                      "Cannot find scaler for %s:%d\n", name, idx))
 317                 return;
 318
 319         /* set scaler mode */
 320         if (plane_state && plane_state->hw.fb &&
 321             plane_state->hw.fb->format->is_yuv &&
 322             plane_state->hw.fb->format->num_planes > 1) {
 323                 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 324                 if (DISPLAY_VER(dev_priv) == 9) {
 325                         mode = SKL_PS_SCALER_MODE_NV12;
 326                 } else if (icl_is_hdr_plane(dev_priv, plane->id)) {
 327                         /*
 328                          * On gen11+'s HDR planes we only use the scaler for
 329                          * scaling. They have a dedicated chroma upsampler, so
 330                          * we don't need the scaler to upsample the UV plane.
 331                          */
 332                         mode = PS_SCALER_MODE_NORMAL;
 333                 } else {
 334                         struct intel_plane *linked =
 335                                 plane_state->planar_linked_plane;
 336
 337                         mode = PS_SCALER_MODE_PLANAR;
 338
 339                         if (linked)
 340                                 mode |= PS_PLANE_Y_SEL(linked->id);
 341                 }
 342         } else if (DISPLAY_VER(dev_priv) >= 10) {
 343                 mode = PS_SCALER_MODE_NORMAL;
 344         } else if (num_scalers_need == 1 && intel_crtc->num_scalers > 1) {
 345                 /*
 346                  * when only 1 scaler is in use on a pipe with 2 scalers
 347                  * scaler 0 operates in high quality (HQ) mode.
 348                  * In this case use scaler 0 to take advantage of HQ mode
 349                  */
 350                 scaler_state->scalers[*scaler_id].in_use = 0;
 351                 *scaler_id = 0;
 352                 scaler_state->scalers[0].in_use = 1;
 353                 mode = SKL_PS_SCALER_MODE_HQ;
 354         } else {
 355                 mode = SKL_PS_SCALER_MODE_DYN;
 356         }
 357
 358         drm_dbg_kms(&dev_priv->drm, "Attached scaler id %u.%u to %s:%d\n",
 359                     intel_crtc->pipe, *scaler_id, name, idx);
 360         scaler_state->scalers[*scaler_id].mode = mode;
 361 }
 362
 363 /**
 364  * intel_atomic_setup_scalers() - setup scalers for crtc per staged requests
 365  * @dev_priv: i915 device
 366  * @intel_crtc: intel crtc
 367  * @crtc_state: incoming crtc_state to validate and setup scalers
 368  *
 369  * This function sets up scalers based on staged scaling requests for
 370  * a @crtc and its planes. It is called from crtc level check path. If request
 371  * is a supportable request, it attaches scalers to requested planes and crtc.
 372  *
 373  * This function takes into account the current scaler(s) in use by any planes
 374  * not being part of this atomic state
 375  *
 376  *  Returns:
 377  *         0 - scalers were setup succesfully
 378  *         error code - otherwise
 379  */
 380 int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
 381                                struct intel_crtc *intel_crtc,
 382                                struct intel_crtc_state *crtc_state)
 383 {
 384         struct drm_plane *plane = NULL;
 385         struct intel_plane *intel_plane;
 386         struct intel_plane_state *plane_state = NULL;
 387         struct intel_crtc_scaler_state *scaler_state =
 388                 &crtc_state->scaler_state;
 389         struct drm_atomic_state *drm_state = crtc_state->uapi.state;
 390         struct intel_atomic_state *intel_state = to_intel_atomic_state(drm_state);
 391         int num_scalers_need;
 392         int i;
 393
 394         num_scalers_need = hweight32(scaler_state->scaler_users);
 395
 396         /*
 397          * High level flow:
 398          * - staged scaler requests are already in scaler_state->scaler_users
 399          * - check whether staged scaling requests can be supported
 400          * - add planes using scalers that aren't in current transaction
 401          * - assign scalers to requested users
 402          * - as part of plane commit, scalers will be committed
 403          *   (i.e., either attached or detached) to respective planes in hw
 404          * - as part of crtc_commit, scaler will be either attached or detached
 405          *   to crtc in hw
 406          */
 407
 408         /* fail if required scalers > available scalers */
 409         if (num_scalers_need > intel_crtc->num_scalers){
 410                 drm_dbg_kms(&dev_priv->drm,
 411                             "Too many scaling requests %d > %d\n",
 412                             num_scalers_need, intel_crtc->num_scalers);
 413                 return -EINVAL;
 414         }
 415
 416         /* walkthrough scaler_users bits and start assigning scalers */
 417         for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
 418                 int *scaler_id;
 419                 const char *name;
 420                 int idx;
 421
 422                 /* skip if scaler not required */
 423                 if (!(scaler_state->scaler_users & (1 << i)))
 424                         continue;
 425
 426                 if (i == SKL_CRTC_INDEX) {
 427                         name = "CRTC";
 428                         idx = intel_crtc->base.base.id;
 429
 430                         /* panel fitter case: assign as a crtc scaler */
 431                         scaler_id = &scaler_state->scaler_id;
 432                 } else {
 433                         name = "PLANE";
 434
 435                         /* plane scaler case: assign as a plane scaler */
 436                         /* find the plane that set the bit as scaler_user */
 437                         plane = drm_state->planes[i].ptr;
 438
 439                         /*
 440                          * to enable/disable hq mode, add planes that are using scaler
 441                          * into this transaction
 442                          */
 443                         if (!plane) {
 444                                 struct drm_plane_state *state;
 445
 446                                 /*
 447                                  * GLK+ scalers don't have a HQ mode so it
 448                                  * isn't necessary to change between HQ and dyn mode
 449                                  * on those platforms.
 450                                  */
 451                                 if (DISPLAY_VER(dev_priv) >= 10)
 452                                         continue;
 453
 454                                 plane = drm_plane_from_index(&dev_priv->drm, i);
 455                                 state = drm_atomic_get_plane_state(drm_state, plane);
 456                                 if (IS_ERR(state)) {
 457                                         drm_dbg_kms(&dev_priv->drm,
 458                                                     "Failed to add [PLANE:%d] to drm_state\n",
 459                                                     plane->base.id);
 460                                         return PTR_ERR(state);
 461                                 }
 462                         }
 463
 464                         intel_plane = to_intel_plane(plane);
 465                         idx = plane->base.id;
 466
 467                         /* plane on different crtc cannot be a scaler user of this crtc */
 468                         if (drm_WARN_ON(&dev_priv->drm,
 469                                         intel_plane->pipe != intel_crtc->pipe))
 470                                 continue;
 471
 472                         plane_state = intel_atomic_get_new_plane_state(intel_state,
 473                                                                        intel_plane);
 474                         scaler_id = &plane_state->scaler_id;
 475                 }
 476
 477                 intel_atomic_setup_scaler(scaler_state, num_scalers_need,
 478                                           intel_crtc, name, idx,
 479                                           plane_state, scaler_id);
 480         }
 481
 482         return 0;
 483 }
 484
 485 struct drm_atomic_state *
 486 intel_atomic_state_alloc(struct drm_device *dev)
 487 {
 488         struct intel_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
 489
 490         if (!state || drm_atomic_state_init(dev, &state->base) < 0) {
 491                 kfree(state);
 492                 return NULL;
 493         }
 494
 495         return &state->base;
 496 }
 497
 498 void intel_atomic_state_free(struct drm_atomic_state *_state)
 499 {
 500         struct intel_atomic_state *state = to_intel_atomic_state(_state);
 501
 502         drm_atomic_state_default_release(&state->base);
 503         kfree(state->global_objs);
 504
 505         i915_sw_fence_fini(&state->commit_ready);
 506
 507         kfree(state);
 508 }
 509
 510 void intel_atomic_state_clear(struct drm_atomic_state *s)
 511 {
 512         struct intel_atomic_state *state = to_intel_atomic_state(s);
 513
 514         drm_atomic_state_default_clear(&state->base);
 515         intel_atomic_clear_global_state(state);
 516
 517         state->dpll_set = state->modeset = false;
 518 }
 519
 520 struct intel_crtc_state *
 521 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
 522                             struct intel_crtc *crtc)
 523 {
 524         struct drm_crtc_state *crtc_state;
 525         crtc_state = drm_atomic_get_crtc_state(state, &crtc->base);
 526         if (IS_ERR(crtc_state))
 527                 return ERR_CAST(crtc_state);
 528
 529         return to_intel_crtc_state(crtc_state);
 530 }