drivers/gpu/drm/etnaviv/etnaviv_gpu.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2015-2018 Etnaviv Project
   4  */
   5
   6 #include <linux/component.h>
   7 #include <linux/dma-fence.h>
   8 #include <linux/moduleparam.h>
   9 #include <linux/of_device.h>
  10 #include <linux/thermal.h>
  11
  12 #include "etnaviv_cmdbuf.h"
  13 #include "etnaviv_dump.h"
  14 #include "etnaviv_gpu.h"
  15 #include "etnaviv_gem.h"
  16 #include "etnaviv_mmu.h"
  17 #include "etnaviv_perfmon.h"
  18 #include "etnaviv_sched.h"
  19 #include "common.xml.h"
  20 #include "state.xml.h"
  21 #include "state_hi.xml.h"
  22 #include "cmdstream.xml.h"
  23
  24 #ifndef PHYS_OFFSET
  25 #define PHYS_OFFSET 0
  26 #endif
  27
  28 static const struct platform_device_id gpu_ids[] = {
  29         { .name = "etnaviv-gpu,2d" },
  30         { },
  31 };
  32
  33 /*
  34  * Driver functions:
  35  */
  36
  37 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
  38 {
  39         switch (param) {
  40         case ETNAVIV_PARAM_GPU_MODEL:
  41                 *value = gpu->identity.model;
  42                 break;
  43
  44         case ETNAVIV_PARAM_GPU_REVISION:
  45                 *value = gpu->identity.revision;
  46                 break;
  47
  48         case ETNAVIV_PARAM_GPU_FEATURES_0:
  49                 *value = gpu->identity.features;
  50                 break;
  51
  52         case ETNAVIV_PARAM_GPU_FEATURES_1:
  53                 *value = gpu->identity.minor_features0;
  54                 break;
  55
  56         case ETNAVIV_PARAM_GPU_FEATURES_2:
  57                 *value = gpu->identity.minor_features1;
  58                 break;
  59
  60         case ETNAVIV_PARAM_GPU_FEATURES_3:
  61                 *value = gpu->identity.minor_features2;
  62                 break;
  63
  64         case ETNAVIV_PARAM_GPU_FEATURES_4:
  65                 *value = gpu->identity.minor_features3;
  66                 break;
  67
  68         case ETNAVIV_PARAM_GPU_FEATURES_5:
  69                 *value = gpu->identity.minor_features4;
  70                 break;
  71
  72         case ETNAVIV_PARAM_GPU_FEATURES_6:
  73                 *value = gpu->identity.minor_features5;
  74                 break;
  75
  76         case ETNAVIV_PARAM_GPU_FEATURES_7:
  77                 *value = gpu->identity.minor_features6;
  78                 break;
  79
  80         case ETNAVIV_PARAM_GPU_FEATURES_8:
  81                 *value = gpu->identity.minor_features7;
  82                 break;
  83
  84         case ETNAVIV_PARAM_GPU_FEATURES_9:
  85                 *value = gpu->identity.minor_features8;
  86                 break;
  87
  88         case ETNAVIV_PARAM_GPU_FEATURES_10:
  89                 *value = gpu->identity.minor_features9;
  90                 break;
  91
  92         case ETNAVIV_PARAM_GPU_FEATURES_11:
  93                 *value = gpu->identity.minor_features10;
  94                 break;
  95
  96         case ETNAVIV_PARAM_GPU_FEATURES_12:
  97                 *value = gpu->identity.minor_features11;
  98                 break;
  99
 100         case ETNAVIV_PARAM_GPU_STREAM_COUNT:
 101                 *value = gpu->identity.stream_count;
 102                 break;
 103
 104         case ETNAVIV_PARAM_GPU_REGISTER_MAX:
 105                 *value = gpu->identity.register_max;
 106                 break;
 107
 108         case ETNAVIV_PARAM_GPU_THREAD_COUNT:
 109                 *value = gpu->identity.thread_count;
 110                 break;
 111
 112         case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
 113                 *value = gpu->identity.vertex_cache_size;
 114                 break;
 115
 116         case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
 117                 *value = gpu->identity.shader_core_count;
 118                 break;
 119
 120         case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
 121                 *value = gpu->identity.pixel_pipes;
 122                 break;
 123
 124         case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
 125                 *value = gpu->identity.vertex_output_buffer_size;
 126                 break;
 127
 128         case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
 129                 *value = gpu->identity.buffer_size;
 130                 break;
 131
 132         case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
 133                 *value = gpu->identity.instruction_count;
 134                 break;
 135
 136         case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
 137                 *value = gpu->identity.num_constants;
 138                 break;
 139
 140         case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
 141                 *value = gpu->identity.varyings_count;
 142                 break;
 143
 144         default:
 145                 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
 146                 return -EINVAL;
 147         }
 148
 149         return 0;
 150 }
 151
 152
 153 #define etnaviv_is_model_rev(gpu, mod, rev) \
 154         ((gpu)->identity.model == chipModel_##mod && \
 155          (gpu)->identity.revision == rev)
 156 #define etnaviv_field(val, field) \
 157         (((val) & field##__MASK) >> field##__SHIFT)
 158
 159 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
 160 {
 161         if (gpu->identity.minor_features0 &
 162             chipMinorFeatures0_MORE_MINOR_FEATURES) {
 163                 u32 specs[4];
 164                 unsigned int streams;
 165
 166                 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
 167                 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
 168                 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
 169                 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
 170
 171                 gpu->identity.stream_count = etnaviv_field(specs[0],
 172                                         VIVS_HI_CHIP_SPECS_STREAM_COUNT);
 173                 gpu->identity.register_max = etnaviv_field(specs[0],
 174                                         VIVS_HI_CHIP_SPECS_REGISTER_MAX);
 175                 gpu->identity.thread_count = etnaviv_field(specs[0],
 176                                         VIVS_HI_CHIP_SPECS_THREAD_COUNT);
 177                 gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
 178                                         VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
 179                 gpu->identity.shader_core_count = etnaviv_field(specs[0],
 180                                         VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
 181                 gpu->identity.pixel_pipes = etnaviv_field(specs[0],
 182                                         VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
 183                 gpu->identity.vertex_output_buffer_size =
 184                         etnaviv_field(specs[0],
 185                                 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
 186
 187                 gpu->identity.buffer_size = etnaviv_field(specs[1],
 188                                         VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
 189                 gpu->identity.instruction_count = etnaviv_field(specs[1],
 190                                         VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
 191                 gpu->identity.num_constants = etnaviv_field(specs[1],
 192                                         VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
 193
 194                 gpu->identity.varyings_count = etnaviv_field(specs[2],
 195                                         VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
 196
 197                 /* This overrides the value from older register if non-zero */
 198                 streams = etnaviv_field(specs[3],
 199                                         VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
 200                 if (streams)
 201                         gpu->identity.stream_count = streams;
 202         }
 203
 204         /* Fill in the stream count if not specified */
 205         if (gpu->identity.stream_count == 0) {
 206                 if (gpu->identity.model >= 0x1000)
 207                         gpu->identity.stream_count = 4;
 208                 else
 209                         gpu->identity.stream_count = 1;
 210         }
 211
 212         /* Convert the register max value */
 213         if (gpu->identity.register_max)
 214                 gpu->identity.register_max = 1 << gpu->identity.register_max;
 215         else if (gpu->identity.model == chipModel_GC400)
 216                 gpu->identity.register_max = 32;
 217         else
 218                 gpu->identity.register_max = 64;
 219
 220         /* Convert thread count */
 221         if (gpu->identity.thread_count)
 222                 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
 223         else if (gpu->identity.model == chipModel_GC400)
 224                 gpu->identity.thread_count = 64;
 225         else if (gpu->identity.model == chipModel_GC500 ||
 226                  gpu->identity.model == chipModel_GC530)
 227                 gpu->identity.thread_count = 128;
 228         else
 229                 gpu->identity.thread_count = 256;
 230
 231         if (gpu->identity.vertex_cache_size == 0)
 232                 gpu->identity.vertex_cache_size = 8;
 233
 234         if (gpu->identity.shader_core_count == 0) {
 235                 if (gpu->identity.model >= 0x1000)
 236                         gpu->identity.shader_core_count = 2;
 237                 else
 238                         gpu->identity.shader_core_count = 1;
 239         }
 240
 241         if (gpu->identity.pixel_pipes == 0)
 242                 gpu->identity.pixel_pipes = 1;
 243
 244         /* Convert virtex buffer size */
 245         if (gpu->identity.vertex_output_buffer_size) {
 246                 gpu->identity.vertex_output_buffer_size =
 247                         1 << gpu->identity.vertex_output_buffer_size;
 248         } else if (gpu->identity.model == chipModel_GC400) {
 249                 if (gpu->identity.revision < 0x4000)
 250                         gpu->identity.vertex_output_buffer_size = 512;
 251                 else if (gpu->identity.revision < 0x4200)
 252                         gpu->identity.vertex_output_buffer_size = 256;
 253                 else
 254                         gpu->identity.vertex_output_buffer_size = 128;
 255         } else {
 256                 gpu->identity.vertex_output_buffer_size = 512;
 257         }
 258
 259         switch (gpu->identity.instruction_count) {
 260         case 0:
 261                 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
 262                     gpu->identity.model == chipModel_GC880)
 263                         gpu->identity.instruction_count = 512;
 264                 else
 265                         gpu->identity.instruction_count = 256;
 266                 break;
 267
 268         case 1:
 269                 gpu->identity.instruction_count = 1024;
 270                 break;
 271
 272         case 2:
 273                 gpu->identity.instruction_count = 2048;
 274                 break;
 275
 276         default:
 277                 gpu->identity.instruction_count = 256;
 278                 break;
 279         }
 280
 281         if (gpu->identity.num_constants == 0)
 282                 gpu->identity.num_constants = 168;
 283
 284         if (gpu->identity.varyings_count == 0) {
 285                 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
 286                         gpu->identity.varyings_count = 12;
 287                 else
 288                         gpu->identity.varyings_count = 8;
 289         }
 290
 291         /*
 292          * For some cores, two varyings are consumed for position, so the
 293          * maximum varying count needs to be reduced by one.
 294          */
 295         if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
 296             etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
 297             etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
 298             etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
 299             etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
 300             etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
 301             etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
 302             etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
 303             etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
 304             etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
 305             etnaviv_is_model_rev(gpu, GC880, 0x5106))
 306                 gpu->identity.varyings_count -= 1;
 307 }
 308
 309 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
 310 {
 311         u32 chipIdentity;
 312
 313         chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
 314
 315         /* Special case for older graphic cores. */
 316         if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
 317                 gpu->identity.model    = chipModel_GC500;
 318                 gpu->identity.revision = etnaviv_field(chipIdentity,
 319                                          VIVS_HI_CHIP_IDENTITY_REVISION);
 320         } else {
 321
 322                 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
 323                 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
 324
 325                 /*
 326                  * !!!! HACK ALERT !!!!
 327                  * Because people change device IDs without letting software
 328                  * know about it - here is the hack to make it all look the
 329                  * same.  Only for GC400 family.
 330                  */
 331                 if ((gpu->identity.model & 0xff00) == 0x0400 &&
 332                     gpu->identity.model != chipModel_GC420) {
 333                         gpu->identity.model = gpu->identity.model & 0x0400;
 334                 }
 335
 336                 /* Another special case */
 337                 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
 338                         u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
 339                         u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
 340
 341                         if (chipDate == 0x20080814 && chipTime == 0x12051100) {
 342                                 /*
 343                                  * This IP has an ECO; put the correct
 344                                  * revision in it.
 345                                  */
 346                                 gpu->identity.revision = 0x1051;
 347                         }
 348                 }
 349
 350                 /*
 351                  * NXP likes to call the GPU on the i.MX6QP GC2000+, but in
 352                  * reality it's just a re-branded GC3000. We can identify this
 353                  * core by the upper half of the revision register being all 1.
 354                  * Fix model/rev here, so all other places can refer to this
 355                  * core by its real identity.
 356                  */
 357                 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
 358                         gpu->identity.model = chipModel_GC3000;
 359                         gpu->identity.revision &= 0xffff;
 360                 }
 361         }
 362
 363         dev_info(gpu->dev, "model: GC%x, revision: %x\n",
 364                  gpu->identity.model, gpu->identity.revision);
 365
 366         /*
 367          * If there is a match in the HWDB, we aren't interested in the
 368          * remaining register values, as they might be wrong.
 369          */
 370         if (etnaviv_fill_identity_from_hwdb(gpu))
 371                 return;
 372
 373         gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
 374
 375         /* Disable fast clear on GC700. */
 376         if (gpu->identity.model == chipModel_GC700)
 377                 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
 378
 379         if ((gpu->identity.model == chipModel_GC500 &&
 380              gpu->identity.revision < 2) ||
 381             (gpu->identity.model == chipModel_GC300 &&
 382              gpu->identity.revision < 0x2000)) {
 383
 384                 /*
 385                  * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
 386                  * registers.
 387                  */
 388                 gpu->identity.minor_features0 = 0;
 389                 gpu->identity.minor_features1 = 0;
 390                 gpu->identity.minor_features2 = 0;
 391                 gpu->identity.minor_features3 = 0;
 392                 gpu->identity.minor_features4 = 0;
 393                 gpu->identity.minor_features5 = 0;
 394         } else
 395                 gpu->identity.minor_features0 =
 396                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
 397
 398         if (gpu->identity.minor_features0 &
 399             chipMinorFeatures0_MORE_MINOR_FEATURES) {
 400                 gpu->identity.minor_features1 =
 401                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
 402                 gpu->identity.minor_features2 =
 403                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
 404                 gpu->identity.minor_features3 =
 405                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
 406                 gpu->identity.minor_features4 =
 407                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
 408                 gpu->identity.minor_features5 =
 409                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
 410         }
 411
 412         /* GC600 idle register reports zero bits where modules aren't present */
 413         if (gpu->identity.model == chipModel_GC600) {
 414                 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
 415                                  VIVS_HI_IDLE_STATE_RA |
 416                                  VIVS_HI_IDLE_STATE_SE |
 417                                  VIVS_HI_IDLE_STATE_PA |
 418                                  VIVS_HI_IDLE_STATE_SH |
 419                                  VIVS_HI_IDLE_STATE_PE |
 420                                  VIVS_HI_IDLE_STATE_DE |
 421                                  VIVS_HI_IDLE_STATE_FE;
 422         } else {
 423                 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
 424         }
 425
 426         etnaviv_hw_specs(gpu);
 427 }
 428
 429 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
 430 {
 431         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
 432                   VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
 433         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
 434 }
 435
 436 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
 437 {
 438         if (gpu->identity.minor_features2 &
 439             chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) {
 440                 clk_set_rate(gpu->clk_core,
 441                              gpu->base_rate_core >> gpu->freq_scale);
 442                 clk_set_rate(gpu->clk_shader,
 443                              gpu->base_rate_shader >> gpu->freq_scale);
 444         } else {
 445                 unsigned int fscale = 1 << (6 - gpu->freq_scale);
 446                 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 447
 448                 clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK;
 449                 clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
 450                 etnaviv_gpu_load_clock(gpu, clock);
 451         }
 452 }
 453
 454 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
 455 {
 456         u32 control, idle;
 457         unsigned long timeout;
 458         bool failed = true;
 459
 460         /* We hope that the GPU resets in under one second */
 461         timeout = jiffies + msecs_to_jiffies(1000);
 462
 463         while (time_is_after_jiffies(timeout)) {
 464                 /* enable clock */
 465                 unsigned int fscale = 1 << (6 - gpu->freq_scale);
 466                 control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
 467                 etnaviv_gpu_load_clock(gpu, control);
 468
 469                 /* isolate the GPU. */
 470                 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
 471                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 472
 473                 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
 474                         gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL,
 475                                   VIVS_MMUv2_AHB_CONTROL_RESET);
 476                 } else {
 477                         /* set soft reset. */
 478                         control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
 479                         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 480                 }
 481
 482                 /* wait for reset. */
 483                 usleep_range(10, 20);
 484
 485                 /* reset soft reset bit. */
 486                 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
 487                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 488
 489                 /* reset GPU isolation. */
 490                 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
 491                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 492
 493                 /* read idle register. */
 494                 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 495
 496                 /* try reseting again if FE it not idle */
 497                 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
 498                         dev_dbg(gpu->dev, "FE is not idle\n");
 499                         continue;
 500                 }
 501
 502                 /* read reset register. */
 503                 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 504
 505                 /* is the GPU idle? */
 506                 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
 507                     ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
 508                         dev_dbg(gpu->dev, "GPU is not idle\n");
 509                         continue;
 510                 }
 511
 512                 /* disable debug registers, as they are not normally needed */
 513                 control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
 514                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 515
 516                 failed = false;
 517                 break;
 518         }
 519
 520         if (failed) {
 521                 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 522                 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 523
 524                 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
 525                         idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
 526                         control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
 527                         control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
 528
 529                 return -EBUSY;
 530         }
 531
 532         /* We rely on the GPU running, so program the clock */
 533         etnaviv_gpu_update_clock(gpu);
 534
 535         return 0;
 536 }
 537
 538 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
 539 {
 540         u32 pmc, ppc;
 541
 542         /* enable clock gating */
 543         ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
 544         ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
 545
 546         /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
 547         if (gpu->identity.revision == 0x4301 ||
 548             gpu->identity.revision == 0x4302)
 549                 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
 550
 551         gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc);
 552
 553         pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS);
 554
 555         /* Disable PA clock gating for GC400+ without bugfix except for GC420 */
 556         if (gpu->identity.model >= chipModel_GC400 &&
 557             gpu->identity.model != chipModel_GC420 &&
 558             !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12))
 559                 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
 560
 561         /*
 562          * Disable PE clock gating on revs < 5.0.0.0 when HZ is
 563          * present without a bug fix.
 564          */
 565         if (gpu->identity.revision < 0x5000 &&
 566             gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
 567             !(gpu->identity.minor_features1 &
 568               chipMinorFeatures1_DISABLE_PE_GATING))
 569                 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
 570
 571         if (gpu->identity.revision < 0x5422)
 572                 pmc |= BIT(15); /* Unknown bit */
 573
 574         /* Disable TX clock gating on affected core revisions. */
 575         if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
 576             etnaviv_is_model_rev(gpu, GC2000, 0x5108))
 577                 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
 578
 579         pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
 580         pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
 581
 582         gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
 583 }
 584
 585 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
 586 {
 587         gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
 588         gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
 589                   VIVS_FE_COMMAND_CONTROL_ENABLE |
 590                   VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
 591
 592         if (gpu->sec_mode == ETNA_SEC_KERNEL) {
 593                 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL,
 594                           VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE |
 595                           VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch));
 596         }
 597 }
 598
 599 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
 600 {
 601         /*
 602          * Base value for VIVS_PM_PULSE_EATER register on models where it
 603          * cannot be read, extracted from vivante kernel driver.
 604          */
 605         u32 pulse_eater = 0x01590880;
 606
 607         if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
 608             etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {
 609                 pulse_eater |= BIT(23);
 610
 611         }
 612
 613         if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||
 614             etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {
 615                 pulse_eater &= ~BIT(16);
 616                 pulse_eater |= BIT(17);
 617         }
 618
 619         if ((gpu->identity.revision > 0x5420) &&
 620             (gpu->identity.features & chipFeatures_PIPE_3D))
 621         {
 622                 /* Performance fix: disable internal DFS */
 623                 pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER);
 624                 pulse_eater |= BIT(18);
 625         }
 626
 627         gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
 628 }
 629
 630 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
 631 {
 632         u16 prefetch;
 633
 634         if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
 635              etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
 636             gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
 637                 u32 mc_memory_debug;
 638
 639                 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
 640
 641                 if (gpu->identity.revision == 0x5007)
 642                         mc_memory_debug |= 0x0c;
 643                 else
 644                         mc_memory_debug |= 0x08;
 645
 646                 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
 647         }
 648
 649         /* enable module-level clock gating */
 650         etnaviv_gpu_enable_mlcg(gpu);
 651
 652         /*
 653          * Update GPU AXI cache atttribute to "cacheable, no allocate".
 654          * This is necessary to prevent the iMX6 SoC locking up.
 655          */
 656         gpu_write(gpu, VIVS_HI_AXI_CONFIG,
 657                   VIVS_HI_AXI_CONFIG_AWCACHE(2) |
 658                   VIVS_HI_AXI_CONFIG_ARCACHE(2));
 659
 660         /* GC2000 rev 5108 needs a special bus config */
 661         if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
 662                 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
 663                 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
 664                                 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
 665                 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
 666                               VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
 667                 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
 668         }
 669
 670         if (gpu->sec_mode == ETNA_SEC_KERNEL) {
 671                 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);
 672                 val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS;
 673                 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val);
 674         }
 675
 676         /* setup the pulse eater */
 677         etnaviv_gpu_setup_pulse_eater(gpu);
 678
 679         /* setup the MMU */
 680         etnaviv_iommu_restore(gpu);
 681
 682         /* Start command processor */
 683         prefetch = etnaviv_buffer_init(gpu);
 684
 685         gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
 686         etnaviv_gpu_start_fe(gpu, etnaviv_cmdbuf_get_va(&gpu->buffer),
 687                              prefetch);
 688 }
 689
 690 int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
 691 {
 692         int ret, i;
 693
 694         ret = pm_runtime_get_sync(gpu->dev);
 695         if (ret < 0) {
 696                 dev_err(gpu->dev, "Failed to enable GPU power domain\n");
 697                 return ret;
 698         }
 699
 700         etnaviv_hw_identify(gpu);
 701
 702         if (gpu->identity.model == 0) {
 703                 dev_err(gpu->dev, "Unknown GPU model\n");
 704                 ret = -ENXIO;
 705                 goto fail;
 706         }
 707
 708         /* Exclude VG cores with FE2.0 */
 709         if (gpu->identity.features & chipFeatures_PIPE_VG &&
 710             gpu->identity.features & chipFeatures_FE20) {
 711                 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
 712                 ret = -ENXIO;
 713                 goto fail;
 714         }
 715
 716         /*
 717          * Set the GPU linear window to be at the end of the DMA window, where
 718          * the CMA area is likely to reside. This ensures that we are able to
 719          * map the command buffers while having the linear window overlap as
 720          * much RAM as possible, so we can optimize mappings for other buffers.
 721          *
 722          * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads
 723          * to different views of the memory on the individual engines.
 724          */
 725         if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
 726             (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
 727                 u32 dma_mask = (u32)dma_get_required_mask(gpu->dev);
 728                 if (dma_mask < PHYS_OFFSET + SZ_2G)
 729                         gpu->memory_base = PHYS_OFFSET;
 730                 else
 731                         gpu->memory_base = dma_mask - SZ_2G + 1;
 732         } else if (PHYS_OFFSET >= SZ_2G) {
 733                 dev_info(gpu->dev, "Need to move linear window on MC1.0, disabling TS\n");
 734                 gpu->memory_base = PHYS_OFFSET;
 735                 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
 736         }
 737
 738         /*
 739          * On cores with security features supported, we claim control over the
 740          * security states.
 741          */
 742         if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) &&
 743             (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB))
 744                 gpu->sec_mode = ETNA_SEC_KERNEL;
 745
 746         ret = etnaviv_hw_reset(gpu);
 747         if (ret) {
 748                 dev_err(gpu->dev, "GPU reset failed\n");
 749                 goto fail;
 750         }
 751
 752         gpu->mmu = etnaviv_iommu_new(gpu);
 753         if (IS_ERR(gpu->mmu)) {
 754                 dev_err(gpu->dev, "Failed to instantiate GPU IOMMU\n");
 755                 ret = PTR_ERR(gpu->mmu);
 756                 goto fail;
 757         }
 758
 759         gpu->cmdbuf_suballoc = etnaviv_cmdbuf_suballoc_new(gpu);
 760         if (IS_ERR(gpu->cmdbuf_suballoc)) {
 761                 dev_err(gpu->dev, "Failed to create cmdbuf suballocator\n");
 762                 ret = PTR_ERR(gpu->cmdbuf_suballoc);
 763                 goto fail;
 764         }
 765
 766         /* Create buffer: */
 767         ret = etnaviv_cmdbuf_init(gpu->cmdbuf_suballoc, &gpu->buffer,
 768                                   PAGE_SIZE);
 769         if (ret) {
 770                 dev_err(gpu->dev, "could not create command buffer\n");
 771                 goto destroy_iommu;
 772         }
 773
 774         if (gpu->mmu->version == ETNAVIV_IOMMU_V1 &&
 775             etnaviv_cmdbuf_get_va(&gpu->buffer) > 0x80000000) {
 776                 ret = -EINVAL;
 777                 dev_err(gpu->dev,
 778                         "command buffer outside valid memory window\n");
 779                 goto free_buffer;
 780         }
 781
 782         /* Setup event management */
 783         spin_lock_init(&gpu->event_spinlock);
 784         init_completion(&gpu->event_free);
 785         bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
 786         for (i = 0; i < ARRAY_SIZE(gpu->event); i++)
 787                 complete(&gpu->event_free);
 788
 789         /* Now program the hardware */
 790         mutex_lock(&gpu->lock);
 791         etnaviv_gpu_hw_init(gpu);
 792         gpu->exec_state = -1;
 793         mutex_unlock(&gpu->lock);
 794
 795         pm_runtime_mark_last_busy(gpu->dev);
 796         pm_runtime_put_autosuspend(gpu->dev);
 797
 798         return 0;
 799
 800 free_buffer:
 801         etnaviv_cmdbuf_free(&gpu->buffer);
 802         gpu->buffer.suballoc = NULL;
 803 destroy_iommu:
 804         etnaviv_iommu_destroy(gpu->mmu);
 805         gpu->mmu = NULL;
 806 fail:
 807         pm_runtime_mark_last_busy(gpu->dev);
 808         pm_runtime_put_autosuspend(gpu->dev);
 809
 810         return ret;
 811 }
 812
 813 #ifdef CONFIG_DEBUG_FS
 814 struct dma_debug {
 815         u32 address[2];
 816         u32 state[2];
 817 };
 818
 819 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
 820 {
 821         u32 i;
 822
 823         debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 824         debug->state[0]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
 825
 826         for (i = 0; i < 500; i++) {
 827                 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 828                 debug->state[1]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
 829
 830                 if (debug->address[0] != debug->address[1])
 831                         break;
 832
 833                 if (debug->state[0] != debug->state[1])
 834                         break;
 835         }
 836 }
 837
 838 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
 839 {
 840         struct dma_debug debug;
 841         u32 dma_lo, dma_hi, axi, idle;
 842         int ret;
 843
 844         seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
 845
 846         ret = pm_runtime_get_sync(gpu->dev);
 847         if (ret < 0)
 848                 return ret;
 849
 850         dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
 851         dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
 852         axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
 853         idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 854
 855         verify_dma(gpu, &debug);
 856
 857         seq_puts(m, "\tfeatures\n");
 858         seq_printf(m, "\t major_features: 0x%08x\n",
 859                    gpu->identity.features);
 860         seq_printf(m, "\t minor_features0: 0x%08x\n",
 861                    gpu->identity.minor_features0);
 862         seq_printf(m, "\t minor_features1: 0x%08x\n",
 863                    gpu->identity.minor_features1);
 864         seq_printf(m, "\t minor_features2: 0x%08x\n",
 865                    gpu->identity.minor_features2);
 866         seq_printf(m, "\t minor_features3: 0x%08x\n",
 867                    gpu->identity.minor_features3);
 868         seq_printf(m, "\t minor_features4: 0x%08x\n",
 869                    gpu->identity.minor_features4);
 870         seq_printf(m, "\t minor_features5: 0x%08x\n",
 871                    gpu->identity.minor_features5);
 872         seq_printf(m, "\t minor_features6: 0x%08x\n",
 873                    gpu->identity.minor_features6);
 874         seq_printf(m, "\t minor_features7: 0x%08x\n",
 875                    gpu->identity.minor_features7);
 876         seq_printf(m, "\t minor_features8: 0x%08x\n",
 877                    gpu->identity.minor_features8);
 878         seq_printf(m, "\t minor_features9: 0x%08x\n",
 879                    gpu->identity.minor_features9);
 880         seq_printf(m, "\t minor_features10: 0x%08x\n",
 881                    gpu->identity.minor_features10);
 882         seq_printf(m, "\t minor_features11: 0x%08x\n",
 883                    gpu->identity.minor_features11);
 884
 885         seq_puts(m, "\tspecs\n");
 886         seq_printf(m, "\t stream_count:  %d\n",
 887                         gpu->identity.stream_count);
 888         seq_printf(m, "\t register_max: %d\n",
 889                         gpu->identity.register_max);
 890         seq_printf(m, "\t thread_count: %d\n",
 891                         gpu->identity.thread_count);
 892         seq_printf(m, "\t vertex_cache_size: %d\n",
 893                         gpu->identity.vertex_cache_size);
 894         seq_printf(m, "\t shader_core_count: %d\n",
 895                         gpu->identity.shader_core_count);
 896         seq_printf(m, "\t pixel_pipes: %d\n",
 897                         gpu->identity.pixel_pipes);
 898         seq_printf(m, "\t vertex_output_buffer_size: %d\n",
 899                         gpu->identity.vertex_output_buffer_size);
 900         seq_printf(m, "\t buffer_size: %d\n",
 901                         gpu->identity.buffer_size);
 902         seq_printf(m, "\t instruction_count: %d\n",
 903                         gpu->identity.instruction_count);
 904         seq_printf(m, "\t num_constants: %d\n",
 905                         gpu->identity.num_constants);
 906         seq_printf(m, "\t varyings_count: %d\n",
 907                         gpu->identity.varyings_count);
 908
 909         seq_printf(m, "\taxi: 0x%08x\n", axi);
 910         seq_printf(m, "\tidle: 0x%08x\n", idle);
 911         idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
 912         if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
 913                 seq_puts(m, "\t FE is not idle\n");
 914         if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
 915                 seq_puts(m, "\t DE is not idle\n");
 916         if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
 917                 seq_puts(m, "\t PE is not idle\n");
 918         if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
 919                 seq_puts(m, "\t SH is not idle\n");
 920         if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
 921                 seq_puts(m, "\t PA is not idle\n");
 922         if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
 923                 seq_puts(m, "\t SE is not idle\n");
 924         if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
 925                 seq_puts(m, "\t RA is not idle\n");
 926         if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
 927                 seq_puts(m, "\t TX is not idle\n");
 928         if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
 929                 seq_puts(m, "\t VG is not idle\n");
 930         if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
 931                 seq_puts(m, "\t IM is not idle\n");
 932         if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
 933                 seq_puts(m, "\t FP is not idle\n");
 934         if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
 935                 seq_puts(m, "\t TS is not idle\n");
 936         if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
 937                 seq_puts(m, "\t AXI low power mode\n");
 938
 939         if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
 940                 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
 941                 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
 942                 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
 943
 944                 seq_puts(m, "\tMC\n");
 945                 seq_printf(m, "\t read0: 0x%08x\n", read0);
 946                 seq_printf(m, "\t read1: 0x%08x\n", read1);
 947                 seq_printf(m, "\t write: 0x%08x\n", write);
 948         }
 949
 950         seq_puts(m, "\tDMA ");
 951
 952         if (debug.address[0] == debug.address[1] &&
 953             debug.state[0] == debug.state[1]) {
 954                 seq_puts(m, "seems to be stuck\n");
 955         } else if (debug.address[0] == debug.address[1]) {
 956                 seq_puts(m, "address is constant\n");
 957         } else {
 958                 seq_puts(m, "is running\n");
 959         }
 960
 961         seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
 962         seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
 963         seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
 964         seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
 965         seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
 966                    dma_lo, dma_hi);
 967
 968         ret = 0;
 969
 970         pm_runtime_mark_last_busy(gpu->dev);
 971         pm_runtime_put_autosuspend(gpu->dev);
 972
 973         return ret;
 974 }
 975 #endif
 976
 977 void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu)
 978 {
 979         unsigned long flags;
 980         unsigned int i = 0;
 981
 982         dev_err(gpu->dev, "recover hung GPU!\n");
 983
 984         if (pm_runtime_get_sync(gpu->dev) < 0)
 985                 return;
 986
 987         mutex_lock(&gpu->lock);
 988
 989         etnaviv_hw_reset(gpu);
 990
 991         /* complete all events, the GPU won't do it after the reset */
 992         spin_lock_irqsave(&gpu->event_spinlock, flags);
 993         for_each_set_bit_from(i, gpu->event_bitmap, ETNA_NR_EVENTS)
 994                 complete(&gpu->event_free);
 995         bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
 996         spin_unlock_irqrestore(&gpu->event_spinlock, flags);
 997         gpu->completed_fence = gpu->active_fence;
 998
 999         etnaviv_gpu_hw_init(gpu);
1000         gpu->lastctx = NULL;
1001         gpu->exec_state = -1;
1002
1003         mutex_unlock(&gpu->lock);
1004         pm_runtime_mark_last_busy(gpu->dev);
1005         pm_runtime_put_autosuspend(gpu->dev);
1006 }
1007
1008 /* fence object management */
1009 struct etnaviv_fence {
1010         struct etnaviv_gpu *gpu;
1011         struct dma_fence base;
1012 };
1013
1014 static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence)
1015 {
1016         return container_of(fence, struct etnaviv_fence, base);
1017 }
1018
1019 static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence)
1020 {
1021         return "etnaviv";
1022 }
1023
1024 static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence)
1025 {
1026         struct etnaviv_fence *f = to_etnaviv_fence(fence);
1027
1028         return dev_name(f->gpu->dev);
1029 }
1030
1031 static bool etnaviv_fence_signaled(struct dma_fence *fence)
1032 {
1033         struct etnaviv_fence *f = to_etnaviv_fence(fence);
1034
1035         return fence_completed(f->gpu, f->base.seqno);
1036 }
1037
1038 static void etnaviv_fence_release(struct dma_fence *fence)
1039 {
1040         struct etnaviv_fence *f = to_etnaviv_fence(fence);
1041
1042         kfree_rcu(f, base.rcu);
1043 }
1044
1045 static const struct dma_fence_ops etnaviv_fence_ops = {
1046         .get_driver_name = etnaviv_fence_get_driver_name,
1047         .get_timeline_name = etnaviv_fence_get_timeline_name,
1048         .signaled = etnaviv_fence_signaled,
1049         .release = etnaviv_fence_release,
1050 };
1051
1052 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
1053 {
1054         struct etnaviv_fence *f;
1055
1056         /*
1057          * GPU lock must already be held, otherwise fence completion order might
1058          * not match the seqno order assigned here.
1059          */
1060         lockdep_assert_held(&gpu->lock);
1061
1062         f = kzalloc(sizeof(*f), GFP_KERNEL);
1063         if (!f)
1064                 return NULL;
1065
1066         f->gpu = gpu;
1067
1068         dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1069                        gpu->fence_context, ++gpu->next_fence);
1070
1071         return &f->base;
1072 }
1073
1074 /*
1075  * event management:
1076  */
1077
1078 static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
1079         unsigned int *events)
1080 {
1081         unsigned long flags, timeout = msecs_to_jiffies(10 * 10000);
1082         unsigned i, acquired = 0;
1083
1084         for (i = 0; i < nr_events; i++) {
1085                 unsigned long ret;
1086
1087                 ret = wait_for_completion_timeout(&gpu->event_free, timeout);
1088
1089                 if (!ret) {
1090                         dev_err(gpu->dev, "wait_for_completion_timeout failed");
1091                         goto out;
1092                 }
1093
1094                 acquired++;
1095                 timeout = ret;
1096         }
1097
1098         spin_lock_irqsave(&gpu->event_spinlock, flags);
1099
1100         for (i = 0; i < nr_events; i++) {
1101                 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
1102
1103                 events[i] = event;
1104                 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));
1105                 set_bit(event, gpu->event_bitmap);
1106         }
1107
1108         spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1109
1110         return 0;
1111
1112 out:
1113         for (i = 0; i < acquired; i++)
1114                 complete(&gpu->event_free);
1115
1116         return -EBUSY;
1117 }
1118
1119 static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1120 {
1121         unsigned long flags;
1122
1123         spin_lock_irqsave(&gpu->event_spinlock, flags);
1124
1125         if (!test_bit(event, gpu->event_bitmap)) {
1126                 dev_warn(gpu->dev, "event %u is already marked as free",
1127                          event);
1128                 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1129         } else {
1130                 clear_bit(event, gpu->event_bitmap);
1131                 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1132
1133                 complete(&gpu->event_free);
1134         }
1135 }
1136
1137 /*
1138  * Cmdstream submission/retirement:
1139  */
1140 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1141         u32 id, struct timespec *timeout)
1142 {
1143         struct dma_fence *fence;
1144         int ret;
1145
1146         /*
1147          * Look up the fence and take a reference. We might still find a fence
1148          * whose refcount has already dropped to zero. dma_fence_get_rcu
1149          * pretends we didn't find a fence in that case.
1150          */
1151         rcu_read_lock();
1152         fence = idr_find(&gpu->fence_idr, id);
1153         if (fence)
1154                 fence = dma_fence_get_rcu(fence);
1155         rcu_read_unlock();
1156
1157         if (!fence)
1158                 return 0;
1159
1160         if (!timeout) {
1161                 /* No timeout was requested: just test for completion */
1162                 ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;
1163         } else {
1164                 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1165
1166                 ret = dma_fence_wait_timeout(fence, true, remaining);
1167                 if (ret == 0)
1168                         ret = -ETIMEDOUT;
1169                 else if (ret != -ERESTARTSYS)
1170                         ret = 0;
1171
1172         }
1173
1174         dma_fence_put(fence);
1175         return ret;
1176 }
1177
1178 /*
1179  * Wait for an object to become inactive.  This, on it's own, is not race
1180  * free: the object is moved by the scheduler off the active list, and
1181  * then the iova is put.  Moreover, the object could be re-submitted just
1182  * after we notice that it's become inactive.
1183  *
1184  * Although the retirement happens under the gpu lock, we don't want to hold
1185  * that lock in this function while waiting.
1186  */
1187 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1188         struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout)
1189 {
1190         unsigned long remaining;
1191         long ret;
1192
1193         if (!timeout)
1194                 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1195
1196         remaining = etnaviv_timeout_to_jiffies(timeout);
1197
1198         ret = wait_event_interruptible_timeout(gpu->fence_event,
1199                                                !is_active(etnaviv_obj),
1200                                                remaining);
1201         if (ret > 0)
1202                 return 0;
1203         else if (ret == -ERESTARTSYS)
1204                 return -ERESTARTSYS;
1205         else
1206                 return -ETIMEDOUT;
1207 }
1208
1209 static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
1210         struct etnaviv_event *event, unsigned int flags)
1211 {
1212         const struct etnaviv_gem_submit *submit = event->submit;
1213         unsigned int i;
1214
1215         for (i = 0; i < submit->nr_pmrs; i++) {
1216                 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1217
1218                 if (pmr->flags == flags)
1219                         etnaviv_perfmon_process(gpu, pmr, submit->exec_state);
1220         }
1221 }
1222
1223 static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
1224         struct etnaviv_event *event)
1225 {
1226         u32 val;
1227
1228         /* disable clock gating */
1229         val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1230         val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1231         gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1232
1233         /* enable debug register */
1234         val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1235         val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1236         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1237
1238         sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
1239 }
1240
1241 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
1242         struct etnaviv_event *event)
1243 {
1244         const struct etnaviv_gem_submit *submit = event->submit;
1245         unsigned int i;
1246         u32 val;
1247
1248         sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
1249
1250         for (i = 0; i < submit->nr_pmrs; i++) {
1251                 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1252
1253                 *pmr->bo_vma = pmr->sequence;
1254         }
1255
1256         /* disable debug register */
1257         val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1258         val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1259         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1260
1261         /* enable clock gating */
1262         val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1263         val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1264         gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1265 }
1266
1267
1268 /* add bo's to gpu's ring, and kick gpu: */
1269 struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit)
1270 {
1271         struct etnaviv_gpu *gpu = submit->gpu;
1272         struct dma_fence *gpu_fence;
1273         unsigned int i, nr_events = 1, event[3];
1274         int ret;
1275
1276         if (!submit->runtime_resumed) {
1277                 ret = pm_runtime_get_sync(gpu->dev);
1278                 if (ret < 0)
1279                         return NULL;
1280                 submit->runtime_resumed = true;
1281         }
1282
1283         /*
1284          * if there are performance monitor requests we need to have
1285          * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE
1286          *   requests.
1287          * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests
1288          *   and update the sequence number for userspace.
1289          */
1290         if (submit->nr_pmrs)
1291                 nr_events = 3;
1292
1293         ret = event_alloc(gpu, nr_events, event);
1294         if (ret) {
1295                 DRM_ERROR("no free events\n");
1296                 return NULL;
1297         }
1298
1299         mutex_lock(&gpu->lock);
1300
1301         gpu_fence = etnaviv_gpu_fence_alloc(gpu);
1302         if (!gpu_fence) {
1303                 for (i = 0; i < nr_events; i++)
1304                         event_free(gpu, event[i]);
1305
1306                 goto out_unlock;
1307         }
1308
1309         gpu->active_fence = gpu_fence->seqno;
1310
1311         if (submit->nr_pmrs) {
1312                 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
1313                 kref_get(&submit->refcount);
1314                 gpu->event[event[1]].submit = submit;
1315                 etnaviv_sync_point_queue(gpu, event[1]);
1316         }
1317
1318         gpu->event[event[0]].fence = gpu_fence;
1319         submit->cmdbuf.user_size = submit->cmdbuf.size - 8;
1320         etnaviv_buffer_queue(gpu, submit->exec_state, event[0],
1321                              &submit->cmdbuf);
1322
1323         if (submit->nr_pmrs) {
1324                 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post;
1325                 kref_get(&submit->refcount);
1326                 gpu->event[event[2]].submit = submit;
1327                 etnaviv_sync_point_queue(gpu, event[2]);
1328         }
1329
1330 out_unlock:
1331         mutex_unlock(&gpu->lock);
1332
1333         return gpu_fence;
1334 }
1335
1336 static void sync_point_worker(struct work_struct *work)
1337 {
1338         struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1339                                                sync_point_work);
1340         struct etnaviv_event *event = &gpu->event[gpu->sync_point_event];
1341         u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
1342
1343         event->sync_point(gpu, event);
1344         etnaviv_submit_put(event->submit);
1345         event_free(gpu, gpu->sync_point_event);
1346
1347         /* restart FE last to avoid GPU and IRQ racing against this worker */
1348         etnaviv_gpu_start_fe(gpu, addr + 2, 2);
1349 }
1350
1351 static void dump_mmu_fault(struct etnaviv_gpu *gpu)
1352 {
1353         u32 status_reg, status;
1354         int i;
1355
1356         if (gpu->sec_mode == ETNA_SEC_NONE)
1357                 status_reg = VIVS_MMUv2_STATUS;
1358         else
1359                 status_reg = VIVS_MMUv2_SEC_STATUS;
1360
1361         status = gpu_read(gpu, status_reg);
1362         dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status);
1363
1364         for (i = 0; i < 4; i++) {
1365                 u32 address_reg;
1366
1367                 if (!(status & (VIVS_MMUv2_STATUS_EXCEPTION0__MASK << (i * 4))))
1368                         continue;
1369
1370                 if (gpu->sec_mode == ETNA_SEC_NONE)
1371                         address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i);
1372                 else
1373                         address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR;
1374
1375                 dev_err_ratelimited(gpu->dev, "MMU %d fault addr 0x%08x\n", i,
1376                                     gpu_read(gpu, address_reg));
1377         }
1378 }
1379
1380 static irqreturn_t irq_handler(int irq, void *data)
1381 {
1382         struct etnaviv_gpu *gpu = data;
1383         irqreturn_t ret = IRQ_NONE;
1384
1385         u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1386
1387         if (intr != 0) {
1388                 int event;
1389
1390                 pm_runtime_mark_last_busy(gpu->dev);
1391
1392                 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1393
1394                 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1395                         dev_err(gpu->dev, "AXI bus error\n");
1396                         intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1397                 }
1398
1399                 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
1400                         dump_mmu_fault(gpu);
1401                         intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
1402                 }
1403
1404                 while ((event = ffs(intr)) != 0) {
1405                         struct dma_fence *fence;
1406
1407                         event -= 1;
1408
1409                         intr &= ~(1 << event);
1410
1411                         dev_dbg(gpu->dev, "event %u\n", event);
1412
1413                         if (gpu->event[event].sync_point) {
1414                                 gpu->sync_point_event = event;
1415                                 queue_work(gpu->wq, &gpu->sync_point_work);
1416                         }
1417
1418                         fence = gpu->event[event].fence;
1419                         if (!fence)
1420                                 continue;
1421
1422                         gpu->event[event].fence = NULL;
1423
1424                         /*
1425                          * Events can be processed out of order.  Eg,
1426                          * - allocate and queue event 0
1427                          * - allocate event 1
1428                          * - event 0 completes, we process it
1429                          * - allocate and queue event 0
1430                          * - event 1 and event 0 complete
1431                          * we can end up processing event 0 first, then 1.
1432                          */
1433                         if (fence_after(fence->seqno, gpu->completed_fence))
1434                                 gpu->completed_fence = fence->seqno;
1435                         dma_fence_signal(fence);
1436
1437                         event_free(gpu, event);
1438                 }
1439
1440                 ret = IRQ_HANDLED;
1441         }
1442
1443         return ret;
1444 }
1445
1446 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1447 {
1448         int ret;
1449
1450         if (gpu->clk_reg) {
1451                 ret = clk_prepare_enable(gpu->clk_reg);
1452                 if (ret)
1453                         return ret;
1454         }
1455
1456         if (gpu->clk_bus) {
1457                 ret = clk_prepare_enable(gpu->clk_bus);
1458                 if (ret)
1459                         return ret;
1460         }
1461
1462         if (gpu->clk_core) {
1463                 ret = clk_prepare_enable(gpu->clk_core);
1464                 if (ret)
1465                         goto disable_clk_bus;
1466         }
1467
1468         if (gpu->clk_shader) {
1469                 ret = clk_prepare_enable(gpu->clk_shader);
1470                 if (ret)
1471                         goto disable_clk_core;
1472         }
1473
1474         return 0;
1475
1476 disable_clk_core:
1477         if (gpu->clk_core)
1478                 clk_disable_unprepare(gpu->clk_core);
1479 disable_clk_bus:
1480         if (gpu->clk_bus)
1481                 clk_disable_unprepare(gpu->clk_bus);
1482
1483         return ret;
1484 }
1485
1486 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1487 {
1488         if (gpu->clk_shader)
1489                 clk_disable_unprepare(gpu->clk_shader);
1490         if (gpu->clk_core)
1491                 clk_disable_unprepare(gpu->clk_core);
1492         if (gpu->clk_bus)
1493                 clk_disable_unprepare(gpu->clk_bus);
1494         if (gpu->clk_reg)
1495                 clk_disable_unprepare(gpu->clk_reg);
1496
1497         return 0;
1498 }
1499
1500 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
1501 {
1502         unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
1503
1504         do {
1505                 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1506
1507                 if ((idle & gpu->idle_mask) == gpu->idle_mask)
1508                         return 0;
1509
1510                 if (time_is_before_jiffies(timeout)) {
1511                         dev_warn(gpu->dev,
1512                                  "timed out waiting for idle: idle=0x%x\n",
1513                                  idle);
1514                         return -ETIMEDOUT;
1515                 }
1516
1517                 udelay(5);
1518         } while (1);
1519 }
1520
1521 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1522 {
1523         if (gpu->buffer.suballoc) {
1524                 /* Replace the last WAIT with END */
1525                 mutex_lock(&gpu->lock);
1526                 etnaviv_buffer_end(gpu);
1527                 mutex_unlock(&gpu->lock);
1528
1529                 /*
1530                  * We know that only the FE is busy here, this should
1531                  * happen quickly (as the WAIT is only 200 cycles).  If
1532                  * we fail, just warn and continue.
1533                  */
1534                 etnaviv_gpu_wait_idle(gpu, 100);
1535         }
1536
1537         return etnaviv_gpu_clk_disable(gpu);
1538 }
1539
1540 #ifdef CONFIG_PM
1541 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1542 {
1543         int ret;
1544
1545         ret = mutex_lock_killable(&gpu->lock);
1546         if (ret)
1547                 return ret;
1548
1549         etnaviv_gpu_update_clock(gpu);
1550         etnaviv_gpu_hw_init(gpu);
1551
1552         gpu->lastctx = NULL;
1553         gpu->exec_state = -1;
1554
1555         mutex_unlock(&gpu->lock);
1556
1557         return 0;
1558 }
1559 #endif
1560
1561 static int
1562 etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev,
1563                                   unsigned long *state)
1564 {
1565         *state = 6;
1566
1567         return 0;
1568 }
1569
1570 static int
1571 etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev,
1572                                   unsigned long *state)
1573 {
1574         struct etnaviv_gpu *gpu = cdev->devdata;
1575
1576         *state = gpu->freq_scale;
1577
1578         return 0;
1579 }
1580
1581 static int
1582 etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev,
1583                                   unsigned long state)
1584 {
1585         struct etnaviv_gpu *gpu = cdev->devdata;
1586
1587         mutex_lock(&gpu->lock);
1588         gpu->freq_scale = state;
1589         if (!pm_runtime_suspended(gpu->dev))
1590                 etnaviv_gpu_update_clock(gpu);
1591         mutex_unlock(&gpu->lock);
1592
1593         return 0;
1594 }
1595
1596 static struct thermal_cooling_device_ops cooling_ops = {
1597         .get_max_state = etnaviv_gpu_cooling_get_max_state,
1598         .get_cur_state = etnaviv_gpu_cooling_get_cur_state,
1599         .set_cur_state = etnaviv_gpu_cooling_set_cur_state,
1600 };
1601
1602 static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1603         void *data)
1604 {
1605         struct drm_device *drm = data;
1606         struct etnaviv_drm_private *priv = drm->dev_private;
1607         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1608         int ret;
1609
1610         if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) {
1611                 gpu->cooling = thermal_of_cooling_device_register(dev->of_node,
1612                                 (char *)dev_name(dev), gpu, &cooling_ops);
1613                 if (IS_ERR(gpu->cooling))
1614                         return PTR_ERR(gpu->cooling);
1615         }
1616
1617         gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0);
1618         if (!gpu->wq) {
1619                 ret = -ENOMEM;
1620                 goto out_thermal;
1621         }
1622
1623         ret = etnaviv_sched_init(gpu);
1624         if (ret)
1625                 goto out_workqueue;
1626
1627 #ifdef CONFIG_PM
1628         ret = pm_runtime_get_sync(gpu->dev);
1629 #else
1630         ret = etnaviv_gpu_clk_enable(gpu);
1631 #endif
1632         if (ret < 0)
1633                 goto out_sched;
1634
1635
1636         gpu->drm = drm;
1637         gpu->fence_context = dma_fence_context_alloc(1);
1638         idr_init(&gpu->fence_idr);
1639         spin_lock_init(&gpu->fence_spinlock);
1640
1641         INIT_WORK(&gpu->sync_point_work, sync_point_worker);
1642         init_waitqueue_head(&gpu->fence_event);
1643
1644         priv->gpu[priv->num_gpus++] = gpu;
1645
1646         pm_runtime_mark_last_busy(gpu->dev);
1647         pm_runtime_put_autosuspend(gpu->dev);
1648
1649         return 0;
1650
1651 out_sched:
1652         etnaviv_sched_fini(gpu);
1653
1654 out_workqueue:
1655         destroy_workqueue(gpu->wq);
1656
1657 out_thermal:
1658         if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1659                 thermal_cooling_device_unregister(gpu->cooling);
1660
1661         return ret;
1662 }
1663
1664 static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1665         void *data)
1666 {
1667         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1668
1669         DBG("%s", dev_name(gpu->dev));
1670
1671         flush_workqueue(gpu->wq);
1672         destroy_workqueue(gpu->wq);
1673
1674         etnaviv_sched_fini(gpu);
1675
1676 #ifdef CONFIG_PM
1677         pm_runtime_get_sync(gpu->dev);
1678         pm_runtime_put_sync_suspend(gpu->dev);
1679 #else
1680         etnaviv_gpu_hw_suspend(gpu);
1681 #endif
1682
1683         if (gpu->buffer.suballoc)
1684                 etnaviv_cmdbuf_free(&gpu->buffer);
1685
1686         if (gpu->cmdbuf_suballoc) {
1687                 etnaviv_cmdbuf_suballoc_destroy(gpu->cmdbuf_suballoc);
1688                 gpu->cmdbuf_suballoc = NULL;
1689         }
1690
1691         if (gpu->mmu) {
1692                 etnaviv_iommu_destroy(gpu->mmu);
1693                 gpu->mmu = NULL;
1694         }
1695
1696         gpu->drm = NULL;
1697         idr_destroy(&gpu->fence_idr);
1698
1699         if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1700                 thermal_cooling_device_unregister(gpu->cooling);
1701         gpu->cooling = NULL;
1702 }
1703
1704 static const struct component_ops gpu_ops = {
1705         .bind = etnaviv_gpu_bind,
1706         .unbind = etnaviv_gpu_unbind,
1707 };
1708
1709 static const struct of_device_id etnaviv_gpu_match[] = {
1710         {
1711                 .compatible = "vivante,gc"
1712         },
1713         { /* sentinel */ }
1714 };
1715 MODULE_DEVICE_TABLE(of, etnaviv_gpu_match);
1716
1717 static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1718 {
1719         struct device *dev = &pdev->dev;
1720         struct etnaviv_gpu *gpu;
1721         struct resource *res;
1722         int err;
1723
1724         gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1725         if (!gpu)
1726                 return -ENOMEM;
1727
1728         gpu->dev = &pdev->dev;
1729         mutex_init(&gpu->lock);
1730         mutex_init(&gpu->fence_lock);
1731
1732         /* Map registers: */
1733         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1734         gpu->mmio = devm_ioremap_resource(&pdev->dev, res);
1735         if (IS_ERR(gpu->mmio))
1736                 return PTR_ERR(gpu->mmio);
1737
1738         /* Get Interrupt: */
1739         gpu->irq = platform_get_irq(pdev, 0);
1740         if (gpu->irq < 0) {
1741                 dev_err(dev, "failed to get irq: %d\n", gpu->irq);
1742                 return gpu->irq;
1743         }
1744
1745         err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1746                                dev_name(gpu->dev), gpu);
1747         if (err) {
1748                 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1749                 return err;
1750         }
1751
1752         /* Get Clocks: */
1753         gpu->clk_reg = devm_clk_get(&pdev->dev, "reg");
1754         DBG("clk_reg: %p", gpu->clk_reg);
1755         if (IS_ERR(gpu->clk_reg))
1756                 gpu->clk_reg = NULL;
1757
1758         gpu->clk_bus = devm_clk_get(&pdev->dev, "bus");
1759         DBG("clk_bus: %p", gpu->clk_bus);
1760         if (IS_ERR(gpu->clk_bus))
1761                 gpu->clk_bus = NULL;
1762
1763         gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1764         DBG("clk_core: %p", gpu->clk_core);
1765         if (IS_ERR(gpu->clk_core))
1766                 gpu->clk_core = NULL;
1767         gpu->base_rate_core = clk_get_rate(gpu->clk_core);
1768
1769         gpu->clk_shader = devm_clk_get(&pdev->dev, "shader");
1770         DBG("clk_shader: %p", gpu->clk_shader);
1771         if (IS_ERR(gpu->clk_shader))
1772                 gpu->clk_shader = NULL;
1773         gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
1774
1775         /* TODO: figure out max mapped size */
1776         dev_set_drvdata(dev, gpu);
1777
1778         /*
1779          * We treat the device as initially suspended.  The runtime PM
1780          * autosuspend delay is rather arbitary: no measurements have
1781          * yet been performed to determine an appropriate value.
1782          */
1783         pm_runtime_use_autosuspend(gpu->dev);
1784         pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1785         pm_runtime_enable(gpu->dev);
1786
1787         err = component_add(&pdev->dev, &gpu_ops);
1788         if (err < 0) {
1789                 dev_err(&pdev->dev, "failed to register component: %d\n", err);
1790                 return err;
1791         }
1792
1793         return 0;
1794 }
1795
1796 static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1797 {
1798         component_del(&pdev->dev, &gpu_ops);
1799         pm_runtime_disable(&pdev->dev);
1800         return 0;
1801 }
1802
1803 #ifdef CONFIG_PM
1804 static int etnaviv_gpu_rpm_suspend(struct device *dev)
1805 {
1806         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1807         u32 idle, mask;
1808
1809         /* If we have outstanding fences, we're not idle */
1810         if (gpu->completed_fence != gpu->active_fence)
1811                 return -EBUSY;
1812
1813         /* Check whether the hardware (except FE) is idle */
1814         mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE;
1815         idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1816         if (idle != mask)
1817                 return -EBUSY;
1818
1819         return etnaviv_gpu_hw_suspend(gpu);
1820 }
1821
1822 static int etnaviv_gpu_rpm_resume(struct device *dev)
1823 {
1824         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1825         int ret;
1826
1827         ret = etnaviv_gpu_clk_enable(gpu);
1828         if (ret)
1829                 return ret;
1830
1831         /* Re-initialise the basic hardware state */
1832         if (gpu->drm && gpu->buffer.suballoc) {
1833                 ret = etnaviv_gpu_hw_resume(gpu);
1834                 if (ret) {
1835                         etnaviv_gpu_clk_disable(gpu);
1836                         return ret;
1837                 }
1838         }
1839
1840         return 0;
1841 }
1842 #endif
1843
1844 static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1845         SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
1846                            NULL)
1847 };
1848
1849 struct platform_driver etnaviv_gpu_driver = {
1850         .driver = {
1851                 .name = "etnaviv-gpu",
1852                 .owner = THIS_MODULE,
1853                 .pm = &etnaviv_gpu_pm_ops,
1854                 .of_match_table = etnaviv_gpu_match,
1855         },
1856         .probe = etnaviv_gpu_platform_probe,
1857         .remove = etnaviv_gpu_platform_remove,
1858         .id_table = gpu_ids,
1859 };