drivers/gpu/drm/etnaviv/etnaviv_gpu.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2015-2018 Etnaviv Project
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/component.h>
   8 #include <linux/dma-fence.h>
   9 #include <linux/moduleparam.h>
  10 #include <linux/of_device.h>
  11 #include <linux/regulator/consumer.h>
  12 #include <linux/thermal.h>
  13
  14 #include "etnaviv_cmdbuf.h"
  15 #include "etnaviv_dump.h"
  16 #include "etnaviv_gpu.h"
  17 #include "etnaviv_gem.h"
  18 #include "etnaviv_mmu.h"
  19 #include "etnaviv_perfmon.h"
  20 #include "etnaviv_sched.h"
  21 #include "common.xml.h"
  22 #include "state.xml.h"
  23 #include "state_hi.xml.h"
  24 #include "cmdstream.xml.h"
  25
  26 #ifndef PHYS_OFFSET
  27 #define PHYS_OFFSET 0
  28 #endif
  29
  30 static const struct platform_device_id gpu_ids[] = {
  31         { .name = "etnaviv-gpu,2d" },
  32         { },
  33 };
  34
  35 /*
  36  * Driver functions:
  37  */
  38
  39 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
  40 {
  41         switch (param) {
  42         case ETNAVIV_PARAM_GPU_MODEL:
  43                 *value = gpu->identity.model;
  44                 break;
  45
  46         case ETNAVIV_PARAM_GPU_REVISION:
  47                 *value = gpu->identity.revision;
  48                 break;
  49
  50         case ETNAVIV_PARAM_GPU_FEATURES_0:
  51                 *value = gpu->identity.features;
  52                 break;
  53
  54         case ETNAVIV_PARAM_GPU_FEATURES_1:
  55                 *value = gpu->identity.minor_features0;
  56                 break;
  57
  58         case ETNAVIV_PARAM_GPU_FEATURES_2:
  59                 *value = gpu->identity.minor_features1;
  60                 break;
  61
  62         case ETNAVIV_PARAM_GPU_FEATURES_3:
  63                 *value = gpu->identity.minor_features2;
  64                 break;
  65
  66         case ETNAVIV_PARAM_GPU_FEATURES_4:
  67                 *value = gpu->identity.minor_features3;
  68                 break;
  69
  70         case ETNAVIV_PARAM_GPU_FEATURES_5:
  71                 *value = gpu->identity.minor_features4;
  72                 break;
  73
  74         case ETNAVIV_PARAM_GPU_FEATURES_6:
  75                 *value = gpu->identity.minor_features5;
  76                 break;
  77
  78         case ETNAVIV_PARAM_GPU_FEATURES_7:
  79                 *value = gpu->identity.minor_features6;
  80                 break;
  81
  82         case ETNAVIV_PARAM_GPU_FEATURES_8:
  83                 *value = gpu->identity.minor_features7;
  84                 break;
  85
  86         case ETNAVIV_PARAM_GPU_FEATURES_9:
  87                 *value = gpu->identity.minor_features8;
  88                 break;
  89
  90         case ETNAVIV_PARAM_GPU_FEATURES_10:
  91                 *value = gpu->identity.minor_features9;
  92                 break;
  93
  94         case ETNAVIV_PARAM_GPU_FEATURES_11:
  95                 *value = gpu->identity.minor_features10;
  96                 break;
  97
  98         case ETNAVIV_PARAM_GPU_FEATURES_12:
  99                 *value = gpu->identity.minor_features11;
 100                 break;
 101
 102         case ETNAVIV_PARAM_GPU_STREAM_COUNT:
 103                 *value = gpu->identity.stream_count;
 104                 break;
 105
 106         case ETNAVIV_PARAM_GPU_REGISTER_MAX:
 107                 *value = gpu->identity.register_max;
 108                 break;
 109
 110         case ETNAVIV_PARAM_GPU_THREAD_COUNT:
 111                 *value = gpu->identity.thread_count;
 112                 break;
 113
 114         case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
 115                 *value = gpu->identity.vertex_cache_size;
 116                 break;
 117
 118         case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
 119                 *value = gpu->identity.shader_core_count;
 120                 break;
 121
 122         case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
 123                 *value = gpu->identity.pixel_pipes;
 124                 break;
 125
 126         case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
 127                 *value = gpu->identity.vertex_output_buffer_size;
 128                 break;
 129
 130         case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
 131                 *value = gpu->identity.buffer_size;
 132                 break;
 133
 134         case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
 135                 *value = gpu->identity.instruction_count;
 136                 break;
 137
 138         case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
 139                 *value = gpu->identity.num_constants;
 140                 break;
 141
 142         case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
 143                 *value = gpu->identity.varyings_count;
 144                 break;
 145
 146         default:
 147                 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
 148                 return -EINVAL;
 149         }
 150
 151         return 0;
 152 }
 153
 154
 155 #define etnaviv_is_model_rev(gpu, mod, rev) \
 156         ((gpu)->identity.model == chipModel_##mod && \
 157          (gpu)->identity.revision == rev)
 158 #define etnaviv_field(val, field) \
 159         (((val) & field##__MASK) >> field##__SHIFT)
 160
 161 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
 162 {
 163         if (gpu->identity.minor_features0 &
 164             chipMinorFeatures0_MORE_MINOR_FEATURES) {
 165                 u32 specs[4];
 166                 unsigned int streams;
 167
 168                 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
 169                 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
 170                 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
 171                 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
 172
 173                 gpu->identity.stream_count = etnaviv_field(specs[0],
 174                                         VIVS_HI_CHIP_SPECS_STREAM_COUNT);
 175                 gpu->identity.register_max = etnaviv_field(specs[0],
 176                                         VIVS_HI_CHIP_SPECS_REGISTER_MAX);
 177                 gpu->identity.thread_count = etnaviv_field(specs[0],
 178                                         VIVS_HI_CHIP_SPECS_THREAD_COUNT);
 179                 gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
 180                                         VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
 181                 gpu->identity.shader_core_count = etnaviv_field(specs[0],
 182                                         VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
 183                 gpu->identity.pixel_pipes = etnaviv_field(specs[0],
 184                                         VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
 185                 gpu->identity.vertex_output_buffer_size =
 186                         etnaviv_field(specs[0],
 187                                 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
 188
 189                 gpu->identity.buffer_size = etnaviv_field(specs[1],
 190                                         VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
 191                 gpu->identity.instruction_count = etnaviv_field(specs[1],
 192                                         VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
 193                 gpu->identity.num_constants = etnaviv_field(specs[1],
 194                                         VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
 195
 196                 gpu->identity.varyings_count = etnaviv_field(specs[2],
 197                                         VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
 198
 199                 /* This overrides the value from older register if non-zero */
 200                 streams = etnaviv_field(specs[3],
 201                                         VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
 202                 if (streams)
 203                         gpu->identity.stream_count = streams;
 204         }
 205
 206         /* Fill in the stream count if not specified */
 207         if (gpu->identity.stream_count == 0) {
 208                 if (gpu->identity.model >= 0x1000)
 209                         gpu->identity.stream_count = 4;
 210                 else
 211                         gpu->identity.stream_count = 1;
 212         }
 213
 214         /* Convert the register max value */
 215         if (gpu->identity.register_max)
 216                 gpu->identity.register_max = 1 << gpu->identity.register_max;
 217         else if (gpu->identity.model == chipModel_GC400)
 218                 gpu->identity.register_max = 32;
 219         else
 220                 gpu->identity.register_max = 64;
 221
 222         /* Convert thread count */
 223         if (gpu->identity.thread_count)
 224                 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
 225         else if (gpu->identity.model == chipModel_GC400)
 226                 gpu->identity.thread_count = 64;
 227         else if (gpu->identity.model == chipModel_GC500 ||
 228                  gpu->identity.model == chipModel_GC530)
 229                 gpu->identity.thread_count = 128;
 230         else
 231                 gpu->identity.thread_count = 256;
 232
 233         if (gpu->identity.vertex_cache_size == 0)
 234                 gpu->identity.vertex_cache_size = 8;
 235
 236         if (gpu->identity.shader_core_count == 0) {
 237                 if (gpu->identity.model >= 0x1000)
 238                         gpu->identity.shader_core_count = 2;
 239                 else
 240                         gpu->identity.shader_core_count = 1;
 241         }
 242
 243         if (gpu->identity.pixel_pipes == 0)
 244                 gpu->identity.pixel_pipes = 1;
 245
 246         /* Convert virtex buffer size */
 247         if (gpu->identity.vertex_output_buffer_size) {
 248                 gpu->identity.vertex_output_buffer_size =
 249                         1 << gpu->identity.vertex_output_buffer_size;
 250         } else if (gpu->identity.model == chipModel_GC400) {
 251                 if (gpu->identity.revision < 0x4000)
 252                         gpu->identity.vertex_output_buffer_size = 512;
 253                 else if (gpu->identity.revision < 0x4200)
 254                         gpu->identity.vertex_output_buffer_size = 256;
 255                 else
 256                         gpu->identity.vertex_output_buffer_size = 128;
 257         } else {
 258                 gpu->identity.vertex_output_buffer_size = 512;
 259         }
 260
 261         switch (gpu->identity.instruction_count) {
 262         case 0:
 263                 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
 264                     gpu->identity.model == chipModel_GC880)
 265                         gpu->identity.instruction_count = 512;
 266                 else
 267                         gpu->identity.instruction_count = 256;
 268                 break;
 269
 270         case 1:
 271                 gpu->identity.instruction_count = 1024;
 272                 break;
 273
 274         case 2:
 275                 gpu->identity.instruction_count = 2048;
 276                 break;
 277
 278         default:
 279                 gpu->identity.instruction_count = 256;
 280                 break;
 281         }
 282
 283         if (gpu->identity.num_constants == 0)
 284                 gpu->identity.num_constants = 168;
 285
 286         if (gpu->identity.varyings_count == 0) {
 287                 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
 288                         gpu->identity.varyings_count = 12;
 289                 else
 290                         gpu->identity.varyings_count = 8;
 291         }
 292
 293         /*
 294          * For some cores, two varyings are consumed for position, so the
 295          * maximum varying count needs to be reduced by one.
 296          */
 297         if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
 298             etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
 299             etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
 300             etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
 301             etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
 302             etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
 303             etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
 304             etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
 305             etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
 306             etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
 307             etnaviv_is_model_rev(gpu, GC880, 0x5106))
 308                 gpu->identity.varyings_count -= 1;
 309 }
 310
 311 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
 312 {
 313         u32 chipIdentity;
 314
 315         chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
 316
 317         /* Special case for older graphic cores. */
 318         if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
 319                 gpu->identity.model    = chipModel_GC500;
 320                 gpu->identity.revision = etnaviv_field(chipIdentity,
 321                                          VIVS_HI_CHIP_IDENTITY_REVISION);
 322         } else {
 323
 324                 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
 325                 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
 326
 327                 /*
 328                  * !!!! HACK ALERT !!!!
 329                  * Because people change device IDs without letting software
 330                  * know about it - here is the hack to make it all look the
 331                  * same.  Only for GC400 family.
 332                  */
 333                 if ((gpu->identity.model & 0xff00) == 0x0400 &&
 334                     gpu->identity.model != chipModel_GC420) {
 335                         gpu->identity.model = gpu->identity.model & 0x0400;
 336                 }
 337
 338                 /* Another special case */
 339                 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
 340                         u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
 341                         u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
 342
 343                         if (chipDate == 0x20080814 && chipTime == 0x12051100) {
 344                                 /*
 345                                  * This IP has an ECO; put the correct
 346                                  * revision in it.
 347                                  */
 348                                 gpu->identity.revision = 0x1051;
 349                         }
 350                 }
 351
 352                 /*
 353                  * NXP likes to call the GPU on the i.MX6QP GC2000+, but in
 354                  * reality it's just a re-branded GC3000. We can identify this
 355                  * core by the upper half of the revision register being all 1.
 356                  * Fix model/rev here, so all other places can refer to this
 357                  * core by its real identity.
 358                  */
 359                 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
 360                         gpu->identity.model = chipModel_GC3000;
 361                         gpu->identity.revision &= 0xffff;
 362                 }
 363         }
 364
 365         dev_info(gpu->dev, "model: GC%x, revision: %x\n",
 366                  gpu->identity.model, gpu->identity.revision);
 367
 368         /*
 369          * If there is a match in the HWDB, we aren't interested in the
 370          * remaining register values, as they might be wrong.
 371          */
 372         if (etnaviv_fill_identity_from_hwdb(gpu))
 373                 return;
 374
 375         gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
 376
 377         /* Disable fast clear on GC700. */
 378         if (gpu->identity.model == chipModel_GC700)
 379                 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
 380
 381         if ((gpu->identity.model == chipModel_GC500 &&
 382              gpu->identity.revision < 2) ||
 383             (gpu->identity.model == chipModel_GC300 &&
 384              gpu->identity.revision < 0x2000)) {
 385
 386                 /*
 387                  * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
 388                  * registers.
 389                  */
 390                 gpu->identity.minor_features0 = 0;
 391                 gpu->identity.minor_features1 = 0;
 392                 gpu->identity.minor_features2 = 0;
 393                 gpu->identity.minor_features3 = 0;
 394                 gpu->identity.minor_features4 = 0;
 395                 gpu->identity.minor_features5 = 0;
 396         } else
 397                 gpu->identity.minor_features0 =
 398                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
 399
 400         if (gpu->identity.minor_features0 &
 401             chipMinorFeatures0_MORE_MINOR_FEATURES) {
 402                 gpu->identity.minor_features1 =
 403                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
 404                 gpu->identity.minor_features2 =
 405                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
 406                 gpu->identity.minor_features3 =
 407                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
 408                 gpu->identity.minor_features4 =
 409                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
 410                 gpu->identity.minor_features5 =
 411                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
 412         }
 413
 414         /* GC600 idle register reports zero bits where modules aren't present */
 415         if (gpu->identity.model == chipModel_GC600) {
 416                 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
 417                                  VIVS_HI_IDLE_STATE_RA |
 418                                  VIVS_HI_IDLE_STATE_SE |
 419                                  VIVS_HI_IDLE_STATE_PA |
 420                                  VIVS_HI_IDLE_STATE_SH |
 421                                  VIVS_HI_IDLE_STATE_PE |
 422                                  VIVS_HI_IDLE_STATE_DE |
 423                                  VIVS_HI_IDLE_STATE_FE;
 424         } else {
 425                 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
 426         }
 427
 428         etnaviv_hw_specs(gpu);
 429 }
 430
 431 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
 432 {
 433         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
 434                   VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
 435         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
 436 }
 437
 438 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
 439 {
 440         if (gpu->identity.minor_features2 &
 441             chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) {
 442                 clk_set_rate(gpu->clk_core,
 443                              gpu->base_rate_core >> gpu->freq_scale);
 444                 clk_set_rate(gpu->clk_shader,
 445                              gpu->base_rate_shader >> gpu->freq_scale);
 446         } else {
 447                 unsigned int fscale = 1 << (6 - gpu->freq_scale);
 448                 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 449
 450                 clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK;
 451                 clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
 452                 etnaviv_gpu_load_clock(gpu, clock);
 453         }
 454 }
 455
 456 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
 457 {
 458         u32 control, idle;
 459         unsigned long timeout;
 460         bool failed = true;
 461
 462         /* We hope that the GPU resets in under one second */
 463         timeout = jiffies + msecs_to_jiffies(1000);
 464
 465         while (time_is_after_jiffies(timeout)) {
 466                 /* enable clock */
 467                 unsigned int fscale = 1 << (6 - gpu->freq_scale);
 468                 control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
 469                 etnaviv_gpu_load_clock(gpu, control);
 470
 471                 /* isolate the GPU. */
 472                 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
 473                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 474
 475                 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
 476                         gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL,
 477                                   VIVS_MMUv2_AHB_CONTROL_RESET);
 478                 } else {
 479                         /* set soft reset. */
 480                         control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
 481                         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 482                 }
 483
 484                 /* wait for reset. */
 485                 usleep_range(10, 20);
 486
 487                 /* reset soft reset bit. */
 488                 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
 489                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 490
 491                 /* reset GPU isolation. */
 492                 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
 493                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 494
 495                 /* read idle register. */
 496                 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 497
 498                 /* try reseting again if FE it not idle */
 499                 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
 500                         dev_dbg(gpu->dev, "FE is not idle\n");
 501                         continue;
 502                 }
 503
 504                 /* read reset register. */
 505                 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 506
 507                 /* is the GPU idle? */
 508                 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
 509                     ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
 510                         dev_dbg(gpu->dev, "GPU is not idle\n");
 511                         continue;
 512                 }
 513
 514                 /* disable debug registers, as they are not normally needed */
 515                 control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
 516                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 517
 518                 failed = false;
 519                 break;
 520         }
 521
 522         if (failed) {
 523                 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 524                 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 525
 526                 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
 527                         idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
 528                         control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
 529                         control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
 530
 531                 return -EBUSY;
 532         }
 533
 534         /* We rely on the GPU running, so program the clock */
 535         etnaviv_gpu_update_clock(gpu);
 536
 537         return 0;
 538 }
 539
 540 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
 541 {
 542         u32 pmc, ppc;
 543
 544         /* enable clock gating */
 545         ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
 546         ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
 547
 548         /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
 549         if (gpu->identity.revision == 0x4301 ||
 550             gpu->identity.revision == 0x4302)
 551                 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
 552
 553         gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc);
 554
 555         pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS);
 556
 557         /* Disable PA clock gating for GC400+ without bugfix except for GC420 */
 558         if (gpu->identity.model >= chipModel_GC400 &&
 559             gpu->identity.model != chipModel_GC420 &&
 560             !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12))
 561                 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
 562
 563         /*
 564          * Disable PE clock gating on revs < 5.0.0.0 when HZ is
 565          * present without a bug fix.
 566          */
 567         if (gpu->identity.revision < 0x5000 &&
 568             gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
 569             !(gpu->identity.minor_features1 &
 570               chipMinorFeatures1_DISABLE_PE_GATING))
 571                 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
 572
 573         if (gpu->identity.revision < 0x5422)
 574                 pmc |= BIT(15); /* Unknown bit */
 575
 576         /* Disable TX clock gating on affected core revisions. */
 577         if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
 578             etnaviv_is_model_rev(gpu, GC2000, 0x5108))
 579                 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
 580
 581         pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
 582         pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
 583
 584         gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
 585 }
 586
 587 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
 588 {
 589         gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
 590         gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
 591                   VIVS_FE_COMMAND_CONTROL_ENABLE |
 592                   VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
 593
 594         if (gpu->sec_mode == ETNA_SEC_KERNEL) {
 595                 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL,
 596                           VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE |
 597                           VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch));
 598         }
 599 }
 600
 601 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
 602 {
 603         /*
 604          * Base value for VIVS_PM_PULSE_EATER register on models where it
 605          * cannot be read, extracted from vivante kernel driver.
 606          */
 607         u32 pulse_eater = 0x01590880;
 608
 609         if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
 610             etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {
 611                 pulse_eater |= BIT(23);
 612
 613         }
 614
 615         if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||
 616             etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {
 617                 pulse_eater &= ~BIT(16);
 618                 pulse_eater |= BIT(17);
 619         }
 620
 621         if ((gpu->identity.revision > 0x5420) &&
 622             (gpu->identity.features & chipFeatures_PIPE_3D))
 623         {
 624                 /* Performance fix: disable internal DFS */
 625                 pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER);
 626                 pulse_eater |= BIT(18);
 627         }
 628
 629         gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
 630 }
 631
 632 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
 633 {
 634         u16 prefetch;
 635
 636         if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
 637              etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
 638             gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
 639                 u32 mc_memory_debug;
 640
 641                 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
 642
 643                 if (gpu->identity.revision == 0x5007)
 644                         mc_memory_debug |= 0x0c;
 645                 else
 646                         mc_memory_debug |= 0x08;
 647
 648                 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
 649         }
 650
 651         /* enable module-level clock gating */
 652         etnaviv_gpu_enable_mlcg(gpu);
 653
 654         /*
 655          * Update GPU AXI cache atttribute to "cacheable, no allocate".
 656          * This is necessary to prevent the iMX6 SoC locking up.
 657          */
 658         gpu_write(gpu, VIVS_HI_AXI_CONFIG,
 659                   VIVS_HI_AXI_CONFIG_AWCACHE(2) |
 660                   VIVS_HI_AXI_CONFIG_ARCACHE(2));
 661
 662         /* GC2000 rev 5108 needs a special bus config */
 663         if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
 664                 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
 665                 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
 666                                 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
 667                 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
 668                               VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
 669                 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
 670         }
 671
 672         if (gpu->sec_mode == ETNA_SEC_KERNEL) {
 673                 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);
 674                 val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS;
 675                 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val);
 676         }
 677
 678         /* setup the pulse eater */
 679         etnaviv_gpu_setup_pulse_eater(gpu);
 680
 681         /* setup the MMU */
 682         etnaviv_iommu_restore(gpu);
 683
 684         /* Start command processor */
 685         prefetch = etnaviv_buffer_init(gpu);
 686
 687         gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
 688         etnaviv_gpu_start_fe(gpu, etnaviv_cmdbuf_get_va(&gpu->buffer),
 689                              prefetch);
 690 }
 691
 692 int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
 693 {
 694         int ret, i;
 695
 696         ret = pm_runtime_get_sync(gpu->dev);
 697         if (ret < 0) {
 698                 dev_err(gpu->dev, "Failed to enable GPU power domain\n");
 699                 return ret;
 700         }
 701
 702         etnaviv_hw_identify(gpu);
 703
 704         if (gpu->identity.model == 0) {
 705                 dev_err(gpu->dev, "Unknown GPU model\n");
 706                 ret = -ENXIO;
 707                 goto fail;
 708         }
 709
 710         /* Exclude VG cores with FE2.0 */
 711         if (gpu->identity.features & chipFeatures_PIPE_VG &&
 712             gpu->identity.features & chipFeatures_FE20) {
 713                 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
 714                 ret = -ENXIO;
 715                 goto fail;
 716         }
 717
 718         /*
 719          * Set the GPU linear window to be at the end of the DMA window, where
 720          * the CMA area is likely to reside. This ensures that we are able to
 721          * map the command buffers while having the linear window overlap as
 722          * much RAM as possible, so we can optimize mappings for other buffers.
 723          *
 724          * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads
 725          * to different views of the memory on the individual engines.
 726          */
 727         if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
 728             (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
 729                 u32 dma_mask = (u32)dma_get_required_mask(gpu->dev);
 730                 if (dma_mask < PHYS_OFFSET + SZ_2G)
 731                         gpu->memory_base = PHYS_OFFSET;
 732                 else
 733                         gpu->memory_base = dma_mask - SZ_2G + 1;
 734         } else if (PHYS_OFFSET >= SZ_2G) {
 735                 dev_info(gpu->dev, "Need to move linear window on MC1.0, disabling TS\n");
 736                 gpu->memory_base = PHYS_OFFSET;
 737                 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
 738         }
 739
 740         /*
 741          * On cores with security features supported, we claim control over the
 742          * security states.
 743          */
 744         if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) &&
 745             (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB))
 746                 gpu->sec_mode = ETNA_SEC_KERNEL;
 747
 748         ret = etnaviv_hw_reset(gpu);
 749         if (ret) {
 750                 dev_err(gpu->dev, "GPU reset failed\n");
 751                 goto fail;
 752         }
 753
 754         gpu->mmu = etnaviv_iommu_new(gpu);
 755         if (IS_ERR(gpu->mmu)) {
 756                 dev_err(gpu->dev, "Failed to instantiate GPU IOMMU\n");
 757                 ret = PTR_ERR(gpu->mmu);
 758                 goto fail;
 759         }
 760
 761         gpu->cmdbuf_suballoc = etnaviv_cmdbuf_suballoc_new(gpu);
 762         if (IS_ERR(gpu->cmdbuf_suballoc)) {
 763                 dev_err(gpu->dev, "Failed to create cmdbuf suballocator\n");
 764                 ret = PTR_ERR(gpu->cmdbuf_suballoc);
 765                 goto fail;
 766         }
 767
 768         /* Create buffer: */
 769         ret = etnaviv_cmdbuf_init(gpu->cmdbuf_suballoc, &gpu->buffer,
 770                                   PAGE_SIZE);
 771         if (ret) {
 772                 dev_err(gpu->dev, "could not create command buffer\n");
 773                 goto destroy_iommu;
 774         }
 775
 776         if (gpu->mmu->version == ETNAVIV_IOMMU_V1 &&
 777             etnaviv_cmdbuf_get_va(&gpu->buffer) > 0x80000000) {
 778                 ret = -EINVAL;
 779                 dev_err(gpu->dev,
 780                         "command buffer outside valid memory window\n");
 781                 goto free_buffer;
 782         }
 783
 784         /* Setup event management */
 785         spin_lock_init(&gpu->event_spinlock);
 786         init_completion(&gpu->event_free);
 787         bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
 788         for (i = 0; i < ARRAY_SIZE(gpu->event); i++)
 789                 complete(&gpu->event_free);
 790
 791         /* Now program the hardware */
 792         mutex_lock(&gpu->lock);
 793         etnaviv_gpu_hw_init(gpu);
 794         gpu->exec_state = -1;
 795         mutex_unlock(&gpu->lock);
 796
 797         pm_runtime_mark_last_busy(gpu->dev);
 798         pm_runtime_put_autosuspend(gpu->dev);
 799
 800         return 0;
 801
 802 free_buffer:
 803         etnaviv_cmdbuf_free(&gpu->buffer);
 804         gpu->buffer.suballoc = NULL;
 805 destroy_iommu:
 806         etnaviv_iommu_destroy(gpu->mmu);
 807         gpu->mmu = NULL;
 808 fail:
 809         pm_runtime_mark_last_busy(gpu->dev);
 810         pm_runtime_put_autosuspend(gpu->dev);
 811
 812         return ret;
 813 }
 814
 815 #ifdef CONFIG_DEBUG_FS
 816 struct dma_debug {
 817         u32 address[2];
 818         u32 state[2];
 819 };
 820
 821 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
 822 {
 823         u32 i;
 824
 825         debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 826         debug->state[0]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
 827
 828         for (i = 0; i < 500; i++) {
 829                 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 830                 debug->state[1]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
 831
 832                 if (debug->address[0] != debug->address[1])
 833                         break;
 834
 835                 if (debug->state[0] != debug->state[1])
 836                         break;
 837         }
 838 }
 839
 840 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
 841 {
 842         struct dma_debug debug;
 843         u32 dma_lo, dma_hi, axi, idle;
 844         int ret;
 845
 846         seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
 847
 848         ret = pm_runtime_get_sync(gpu->dev);
 849         if (ret < 0)
 850                 return ret;
 851
 852         dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
 853         dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
 854         axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
 855         idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 856
 857         verify_dma(gpu, &debug);
 858
 859         seq_puts(m, "\tfeatures\n");
 860         seq_printf(m, "\t major_features: 0x%08x\n",
 861                    gpu->identity.features);
 862         seq_printf(m, "\t minor_features0: 0x%08x\n",
 863                    gpu->identity.minor_features0);
 864         seq_printf(m, "\t minor_features1: 0x%08x\n",
 865                    gpu->identity.minor_features1);
 866         seq_printf(m, "\t minor_features2: 0x%08x\n",
 867                    gpu->identity.minor_features2);
 868         seq_printf(m, "\t minor_features3: 0x%08x\n",
 869                    gpu->identity.minor_features3);
 870         seq_printf(m, "\t minor_features4: 0x%08x\n",
 871                    gpu->identity.minor_features4);
 872         seq_printf(m, "\t minor_features5: 0x%08x\n",
 873                    gpu->identity.minor_features5);
 874         seq_printf(m, "\t minor_features6: 0x%08x\n",
 875                    gpu->identity.minor_features6);
 876         seq_printf(m, "\t minor_features7: 0x%08x\n",
 877                    gpu->identity.minor_features7);
 878         seq_printf(m, "\t minor_features8: 0x%08x\n",
 879                    gpu->identity.minor_features8);
 880         seq_printf(m, "\t minor_features9: 0x%08x\n",
 881                    gpu->identity.minor_features9);
 882         seq_printf(m, "\t minor_features10: 0x%08x\n",
 883                    gpu->identity.minor_features10);
 884         seq_printf(m, "\t minor_features11: 0x%08x\n",
 885                    gpu->identity.minor_features11);
 886
 887         seq_puts(m, "\tspecs\n");
 888         seq_printf(m, "\t stream_count:  %d\n",
 889                         gpu->identity.stream_count);
 890         seq_printf(m, "\t register_max: %d\n",
 891                         gpu->identity.register_max);
 892         seq_printf(m, "\t thread_count: %d\n",
 893                         gpu->identity.thread_count);
 894         seq_printf(m, "\t vertex_cache_size: %d\n",
 895                         gpu->identity.vertex_cache_size);
 896         seq_printf(m, "\t shader_core_count: %d\n",
 897                         gpu->identity.shader_core_count);
 898         seq_printf(m, "\t pixel_pipes: %d\n",
 899                         gpu->identity.pixel_pipes);
 900         seq_printf(m, "\t vertex_output_buffer_size: %d\n",
 901                         gpu->identity.vertex_output_buffer_size);
 902         seq_printf(m, "\t buffer_size: %d\n",
 903                         gpu->identity.buffer_size);
 904         seq_printf(m, "\t instruction_count: %d\n",
 905                         gpu->identity.instruction_count);
 906         seq_printf(m, "\t num_constants: %d\n",
 907                         gpu->identity.num_constants);
 908         seq_printf(m, "\t varyings_count: %d\n",
 909                         gpu->identity.varyings_count);
 910
 911         seq_printf(m, "\taxi: 0x%08x\n", axi);
 912         seq_printf(m, "\tidle: 0x%08x\n", idle);
 913         idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
 914         if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
 915                 seq_puts(m, "\t FE is not idle\n");
 916         if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
 917                 seq_puts(m, "\t DE is not idle\n");
 918         if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
 919                 seq_puts(m, "\t PE is not idle\n");
 920         if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
 921                 seq_puts(m, "\t SH is not idle\n");
 922         if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
 923                 seq_puts(m, "\t PA is not idle\n");
 924         if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
 925                 seq_puts(m, "\t SE is not idle\n");
 926         if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
 927                 seq_puts(m, "\t RA is not idle\n");
 928         if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
 929                 seq_puts(m, "\t TX is not idle\n");
 930         if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
 931                 seq_puts(m, "\t VG is not idle\n");
 932         if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
 933                 seq_puts(m, "\t IM is not idle\n");
 934         if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
 935                 seq_puts(m, "\t FP is not idle\n");
 936         if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
 937                 seq_puts(m, "\t TS is not idle\n");
 938         if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
 939                 seq_puts(m, "\t AXI low power mode\n");
 940
 941         if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
 942                 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
 943                 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
 944                 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
 945
 946                 seq_puts(m, "\tMC\n");
 947                 seq_printf(m, "\t read0: 0x%08x\n", read0);
 948                 seq_printf(m, "\t read1: 0x%08x\n", read1);
 949                 seq_printf(m, "\t write: 0x%08x\n", write);
 950         }
 951
 952         seq_puts(m, "\tDMA ");
 953
 954         if (debug.address[0] == debug.address[1] &&
 955             debug.state[0] == debug.state[1]) {
 956                 seq_puts(m, "seems to be stuck\n");
 957         } else if (debug.address[0] == debug.address[1]) {
 958                 seq_puts(m, "address is constant\n");
 959         } else {
 960                 seq_puts(m, "is running\n");
 961         }
 962
 963         seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
 964         seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
 965         seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
 966         seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
 967         seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
 968                    dma_lo, dma_hi);
 969
 970         ret = 0;
 971
 972         pm_runtime_mark_last_busy(gpu->dev);
 973         pm_runtime_put_autosuspend(gpu->dev);
 974
 975         return ret;
 976 }
 977 #endif
 978
 979 void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu)
 980 {
 981         unsigned int i = 0;
 982
 983         dev_err(gpu->dev, "recover hung GPU!\n");
 984
 985         if (pm_runtime_get_sync(gpu->dev) < 0)
 986                 return;
 987
 988         mutex_lock(&gpu->lock);
 989
 990         etnaviv_hw_reset(gpu);
 991
 992         /* complete all events, the GPU won't do it after the reset */
 993         spin_lock(&gpu->event_spinlock);
 994         for_each_set_bit_from(i, gpu->event_bitmap, ETNA_NR_EVENTS)
 995                 complete(&gpu->event_free);
 996         bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
 997         spin_unlock(&gpu->event_spinlock);
 998
 999         etnaviv_gpu_hw_init(gpu);
1000         gpu->exec_state = -1;
1001
1002         mutex_unlock(&gpu->lock);
1003         pm_runtime_mark_last_busy(gpu->dev);
1004         pm_runtime_put_autosuspend(gpu->dev);
1005 }
1006
1007 /* fence object management */
1008 struct etnaviv_fence {
1009         struct etnaviv_gpu *gpu;
1010         struct dma_fence base;
1011 };
1012
1013 static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence)
1014 {
1015         return container_of(fence, struct etnaviv_fence, base);
1016 }
1017
1018 static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence)
1019 {
1020         return "etnaviv";
1021 }
1022
1023 static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence)
1024 {
1025         struct etnaviv_fence *f = to_etnaviv_fence(fence);
1026
1027         return dev_name(f->gpu->dev);
1028 }
1029
1030 static bool etnaviv_fence_signaled(struct dma_fence *fence)
1031 {
1032         struct etnaviv_fence *f = to_etnaviv_fence(fence);
1033
1034         return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0;
1035 }
1036
1037 static void etnaviv_fence_release(struct dma_fence *fence)
1038 {
1039         struct etnaviv_fence *f = to_etnaviv_fence(fence);
1040
1041         kfree_rcu(f, base.rcu);
1042 }
1043
1044 static const struct dma_fence_ops etnaviv_fence_ops = {
1045         .get_driver_name = etnaviv_fence_get_driver_name,
1046         .get_timeline_name = etnaviv_fence_get_timeline_name,
1047         .signaled = etnaviv_fence_signaled,
1048         .release = etnaviv_fence_release,
1049 };
1050
1051 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
1052 {
1053         struct etnaviv_fence *f;
1054
1055         /*
1056          * GPU lock must already be held, otherwise fence completion order might
1057          * not match the seqno order assigned here.
1058          */
1059         lockdep_assert_held(&gpu->lock);
1060
1061         f = kzalloc(sizeof(*f), GFP_KERNEL);
1062         if (!f)
1063                 return NULL;
1064
1065         f->gpu = gpu;
1066
1067         dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1068                        gpu->fence_context, ++gpu->next_fence);
1069
1070         return &f->base;
1071 }
1072
1073 /* returns true if fence a comes after fence b */
1074 static inline bool fence_after(u32 a, u32 b)
1075 {
1076         return (s32)(a - b) > 0;
1077 }
1078
1079 /*
1080  * event management:
1081  */
1082
1083 static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
1084         unsigned int *events)
1085 {
1086         unsigned long timeout = msecs_to_jiffies(10 * 10000);
1087         unsigned i, acquired = 0;
1088
1089         for (i = 0; i < nr_events; i++) {
1090                 unsigned long ret;
1091
1092                 ret = wait_for_completion_timeout(&gpu->event_free, timeout);
1093
1094                 if (!ret) {
1095                         dev_err(gpu->dev, "wait_for_completion_timeout failed");
1096                         goto out;
1097                 }
1098
1099                 acquired++;
1100                 timeout = ret;
1101         }
1102
1103         spin_lock(&gpu->event_spinlock);
1104
1105         for (i = 0; i < nr_events; i++) {
1106                 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
1107
1108                 events[i] = event;
1109                 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));
1110                 set_bit(event, gpu->event_bitmap);
1111         }
1112
1113         spin_unlock(&gpu->event_spinlock);
1114
1115         return 0;
1116
1117 out:
1118         for (i = 0; i < acquired; i++)
1119                 complete(&gpu->event_free);
1120
1121         return -EBUSY;
1122 }
1123
1124 static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1125 {
1126         if (!test_bit(event, gpu->event_bitmap)) {
1127                 dev_warn(gpu->dev, "event %u is already marked as free",
1128                          event);
1129         } else {
1130                 clear_bit(event, gpu->event_bitmap);
1131                 complete(&gpu->event_free);
1132         }
1133 }
1134
1135 /*
1136  * Cmdstream submission/retirement:
1137  */
1138 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1139         u32 id, struct timespec *timeout)
1140 {
1141         struct dma_fence *fence;
1142         int ret;
1143
1144         /*
1145          * Look up the fence and take a reference. We might still find a fence
1146          * whose refcount has already dropped to zero. dma_fence_get_rcu
1147          * pretends we didn't find a fence in that case.
1148          */
1149         rcu_read_lock();
1150         fence = idr_find(&gpu->fence_idr, id);
1151         if (fence)
1152                 fence = dma_fence_get_rcu(fence);
1153         rcu_read_unlock();
1154
1155         if (!fence)
1156                 return 0;
1157
1158         if (!timeout) {
1159                 /* No timeout was requested: just test for completion */
1160                 ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;
1161         } else {
1162                 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1163
1164                 ret = dma_fence_wait_timeout(fence, true, remaining);
1165                 if (ret == 0)
1166                         ret = -ETIMEDOUT;
1167                 else if (ret != -ERESTARTSYS)
1168                         ret = 0;
1169
1170         }
1171
1172         dma_fence_put(fence);
1173         return ret;
1174 }
1175
1176 /*
1177  * Wait for an object to become inactive.  This, on it's own, is not race
1178  * free: the object is moved by the scheduler off the active list, and
1179  * then the iova is put.  Moreover, the object could be re-submitted just
1180  * after we notice that it's become inactive.
1181  *
1182  * Although the retirement happens under the gpu lock, we don't want to hold
1183  * that lock in this function while waiting.
1184  */
1185 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1186         struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout)
1187 {
1188         unsigned long remaining;
1189         long ret;
1190
1191         if (!timeout)
1192                 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1193
1194         remaining = etnaviv_timeout_to_jiffies(timeout);
1195
1196         ret = wait_event_interruptible_timeout(gpu->fence_event,
1197                                                !is_active(etnaviv_obj),
1198                                                remaining);
1199         if (ret > 0)
1200                 return 0;
1201         else if (ret == -ERESTARTSYS)
1202                 return -ERESTARTSYS;
1203         else
1204                 return -ETIMEDOUT;
1205 }
1206
1207 static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
1208         struct etnaviv_event *event, unsigned int flags)
1209 {
1210         const struct etnaviv_gem_submit *submit = event->submit;
1211         unsigned int i;
1212
1213         for (i = 0; i < submit->nr_pmrs; i++) {
1214                 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1215
1216                 if (pmr->flags == flags)
1217                         etnaviv_perfmon_process(gpu, pmr, submit->exec_state);
1218         }
1219 }
1220
1221 static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
1222         struct etnaviv_event *event)
1223 {
1224         u32 val;
1225
1226         /* disable clock gating */
1227         val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1228         val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1229         gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1230
1231         /* enable debug register */
1232         val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1233         val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1234         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1235
1236         sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
1237 }
1238
1239 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
1240         struct etnaviv_event *event)
1241 {
1242         const struct etnaviv_gem_submit *submit = event->submit;
1243         unsigned int i;
1244         u32 val;
1245
1246         sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
1247
1248         for (i = 0; i < submit->nr_pmrs; i++) {
1249                 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1250
1251                 *pmr->bo_vma = pmr->sequence;
1252         }
1253
1254         /* disable debug register */
1255         val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1256         val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1257         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1258
1259         /* enable clock gating */
1260         val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1261         val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1262         gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1263 }
1264
1265
1266 /* add bo's to gpu's ring, and kick gpu: */
1267 struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit)
1268 {
1269         struct etnaviv_gpu *gpu = submit->gpu;
1270         struct dma_fence *gpu_fence;
1271         unsigned int i, nr_events = 1, event[3];
1272         int ret;
1273
1274         if (!submit->runtime_resumed) {
1275                 ret = pm_runtime_get_sync(gpu->dev);
1276                 if (ret < 0)
1277                         return NULL;
1278                 submit->runtime_resumed = true;
1279         }
1280
1281         /*
1282          * if there are performance monitor requests we need to have
1283          * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE
1284          *   requests.
1285          * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests
1286          *   and update the sequence number for userspace.
1287          */
1288         if (submit->nr_pmrs)
1289                 nr_events = 3;
1290
1291         ret = event_alloc(gpu, nr_events, event);
1292         if (ret) {
1293                 DRM_ERROR("no free events\n");
1294                 return NULL;
1295         }
1296
1297         mutex_lock(&gpu->lock);
1298
1299         gpu_fence = etnaviv_gpu_fence_alloc(gpu);
1300         if (!gpu_fence) {
1301                 for (i = 0; i < nr_events; i++)
1302                         event_free(gpu, event[i]);
1303
1304                 goto out_unlock;
1305         }
1306
1307         if (submit->nr_pmrs) {
1308                 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
1309                 kref_get(&submit->refcount);
1310                 gpu->event[event[1]].submit = submit;
1311                 etnaviv_sync_point_queue(gpu, event[1]);
1312         }
1313
1314         gpu->event[event[0]].fence = gpu_fence;
1315         submit->cmdbuf.user_size = submit->cmdbuf.size - 8;
1316         etnaviv_buffer_queue(gpu, submit->exec_state, event[0],
1317                              &submit->cmdbuf);
1318
1319         if (submit->nr_pmrs) {
1320                 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post;
1321                 kref_get(&submit->refcount);
1322                 gpu->event[event[2]].submit = submit;
1323                 etnaviv_sync_point_queue(gpu, event[2]);
1324         }
1325
1326 out_unlock:
1327         mutex_unlock(&gpu->lock);
1328
1329         return gpu_fence;
1330 }
1331
1332 static void sync_point_worker(struct work_struct *work)
1333 {
1334         struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1335                                                sync_point_work);
1336         struct etnaviv_event *event = &gpu->event[gpu->sync_point_event];
1337         u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
1338
1339         event->sync_point(gpu, event);
1340         etnaviv_submit_put(event->submit);
1341         event_free(gpu, gpu->sync_point_event);
1342
1343         /* restart FE last to avoid GPU and IRQ racing against this worker */
1344         etnaviv_gpu_start_fe(gpu, addr + 2, 2);
1345 }
1346
1347 static void dump_mmu_fault(struct etnaviv_gpu *gpu)
1348 {
1349         u32 status_reg, status;
1350         int i;
1351
1352         if (gpu->sec_mode == ETNA_SEC_NONE)
1353                 status_reg = VIVS_MMUv2_STATUS;
1354         else
1355                 status_reg = VIVS_MMUv2_SEC_STATUS;
1356
1357         status = gpu_read(gpu, status_reg);
1358         dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status);
1359
1360         for (i = 0; i < 4; i++) {
1361                 u32 address_reg;
1362
1363                 if (!(status & (VIVS_MMUv2_STATUS_EXCEPTION0__MASK << (i * 4))))
1364                         continue;
1365
1366                 if (gpu->sec_mode == ETNA_SEC_NONE)
1367                         address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i);
1368                 else
1369                         address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR;
1370
1371                 dev_err_ratelimited(gpu->dev, "MMU %d fault addr 0x%08x\n", i,
1372                                     gpu_read(gpu, address_reg));
1373         }
1374 }
1375
1376 static irqreturn_t irq_handler(int irq, void *data)
1377 {
1378         struct etnaviv_gpu *gpu = data;
1379         irqreturn_t ret = IRQ_NONE;
1380
1381         u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1382
1383         if (intr != 0) {
1384                 int event;
1385
1386                 pm_runtime_mark_last_busy(gpu->dev);
1387
1388                 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1389
1390                 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1391                         dev_err(gpu->dev, "AXI bus error\n");
1392                         intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1393                 }
1394
1395                 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
1396                         dump_mmu_fault(gpu);
1397                         intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
1398                 }
1399
1400                 while ((event = ffs(intr)) != 0) {
1401                         struct dma_fence *fence;
1402
1403                         event -= 1;
1404
1405                         intr &= ~(1 << event);
1406
1407                         dev_dbg(gpu->dev, "event %u\n", event);
1408
1409                         if (gpu->event[event].sync_point) {
1410                                 gpu->sync_point_event = event;
1411                                 queue_work(gpu->wq, &gpu->sync_point_work);
1412                         }
1413
1414                         fence = gpu->event[event].fence;
1415                         if (!fence)
1416                                 continue;
1417
1418                         gpu->event[event].fence = NULL;
1419
1420                         /*
1421                          * Events can be processed out of order.  Eg,
1422                          * - allocate and queue event 0
1423                          * - allocate event 1
1424                          * - event 0 completes, we process it
1425                          * - allocate and queue event 0
1426                          * - event 1 and event 0 complete
1427                          * we can end up processing event 0 first, then 1.
1428                          */
1429                         if (fence_after(fence->seqno, gpu->completed_fence))
1430                                 gpu->completed_fence = fence->seqno;
1431                         dma_fence_signal(fence);
1432
1433                         event_free(gpu, event);
1434                 }
1435
1436                 ret = IRQ_HANDLED;
1437         }
1438
1439         return ret;
1440 }
1441
1442 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1443 {
1444         int ret;
1445
1446         if (gpu->clk_reg) {
1447                 ret = clk_prepare_enable(gpu->clk_reg);
1448                 if (ret)
1449                         return ret;
1450         }
1451
1452         if (gpu->clk_bus) {
1453                 ret = clk_prepare_enable(gpu->clk_bus);
1454                 if (ret)
1455                         return ret;
1456         }
1457
1458         if (gpu->clk_core) {
1459                 ret = clk_prepare_enable(gpu->clk_core);
1460                 if (ret)
1461                         goto disable_clk_bus;
1462         }
1463
1464         if (gpu->clk_shader) {
1465                 ret = clk_prepare_enable(gpu->clk_shader);
1466                 if (ret)
1467                         goto disable_clk_core;
1468         }
1469
1470         return 0;
1471
1472 disable_clk_core:
1473         if (gpu->clk_core)
1474                 clk_disable_unprepare(gpu->clk_core);
1475 disable_clk_bus:
1476         if (gpu->clk_bus)
1477                 clk_disable_unprepare(gpu->clk_bus);
1478
1479         return ret;
1480 }
1481
1482 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1483 {
1484         if (gpu->clk_shader)
1485                 clk_disable_unprepare(gpu->clk_shader);
1486         if (gpu->clk_core)
1487                 clk_disable_unprepare(gpu->clk_core);
1488         if (gpu->clk_bus)
1489                 clk_disable_unprepare(gpu->clk_bus);
1490         if (gpu->clk_reg)
1491                 clk_disable_unprepare(gpu->clk_reg);
1492
1493         return 0;
1494 }
1495
1496 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
1497 {
1498         unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
1499
1500         do {
1501                 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1502
1503                 if ((idle & gpu->idle_mask) == gpu->idle_mask)
1504                         return 0;
1505
1506                 if (time_is_before_jiffies(timeout)) {
1507                         dev_warn(gpu->dev,
1508                                  "timed out waiting for idle: idle=0x%x\n",
1509                                  idle);
1510                         return -ETIMEDOUT;
1511                 }
1512
1513                 udelay(5);
1514         } while (1);
1515 }
1516
1517 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1518 {
1519         if (gpu->buffer.suballoc) {
1520                 /* Replace the last WAIT with END */
1521                 mutex_lock(&gpu->lock);
1522                 etnaviv_buffer_end(gpu);
1523                 mutex_unlock(&gpu->lock);
1524
1525                 /*
1526                  * We know that only the FE is busy here, this should
1527                  * happen quickly (as the WAIT is only 200 cycles).  If
1528                  * we fail, just warn and continue.
1529                  */
1530                 etnaviv_gpu_wait_idle(gpu, 100);
1531         }
1532
1533         return etnaviv_gpu_clk_disable(gpu);
1534 }
1535
1536 #ifdef CONFIG_PM
1537 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1538 {
1539         int ret;
1540
1541         ret = mutex_lock_killable(&gpu->lock);
1542         if (ret)
1543                 return ret;
1544
1545         etnaviv_gpu_update_clock(gpu);
1546         etnaviv_gpu_hw_init(gpu);
1547
1548         gpu->exec_state = -1;
1549
1550         mutex_unlock(&gpu->lock);
1551
1552         return 0;
1553 }
1554 #endif
1555
1556 static int
1557 etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev,
1558                                   unsigned long *state)
1559 {
1560         *state = 6;
1561
1562         return 0;
1563 }
1564
1565 static int
1566 etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev,
1567                                   unsigned long *state)
1568 {
1569         struct etnaviv_gpu *gpu = cdev->devdata;
1570
1571         *state = gpu->freq_scale;
1572
1573         return 0;
1574 }
1575
1576 static int
1577 etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev,
1578                                   unsigned long state)
1579 {
1580         struct etnaviv_gpu *gpu = cdev->devdata;
1581
1582         mutex_lock(&gpu->lock);
1583         gpu->freq_scale = state;
1584         if (!pm_runtime_suspended(gpu->dev))
1585                 etnaviv_gpu_update_clock(gpu);
1586         mutex_unlock(&gpu->lock);
1587
1588         return 0;
1589 }
1590
1591 static struct thermal_cooling_device_ops cooling_ops = {
1592         .get_max_state = etnaviv_gpu_cooling_get_max_state,
1593         .get_cur_state = etnaviv_gpu_cooling_get_cur_state,
1594         .set_cur_state = etnaviv_gpu_cooling_set_cur_state,
1595 };
1596
1597 static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1598         void *data)
1599 {
1600         struct drm_device *drm = data;
1601         struct etnaviv_drm_private *priv = drm->dev_private;
1602         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1603         int ret;
1604
1605         if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) {
1606                 gpu->cooling = thermal_of_cooling_device_register(dev->of_node,
1607                                 (char *)dev_name(dev), gpu, &cooling_ops);
1608                 if (IS_ERR(gpu->cooling))
1609                         return PTR_ERR(gpu->cooling);
1610         }
1611
1612         gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0);
1613         if (!gpu->wq) {
1614                 ret = -ENOMEM;
1615                 goto out_thermal;
1616         }
1617
1618         ret = etnaviv_sched_init(gpu);
1619         if (ret)
1620                 goto out_workqueue;
1621
1622 #ifdef CONFIG_PM
1623         ret = pm_runtime_get_sync(gpu->dev);
1624 #else
1625         ret = etnaviv_gpu_clk_enable(gpu);
1626 #endif
1627         if (ret < 0)
1628                 goto out_sched;
1629
1630
1631         gpu->drm = drm;
1632         gpu->fence_context = dma_fence_context_alloc(1);
1633         idr_init(&gpu->fence_idr);
1634         spin_lock_init(&gpu->fence_spinlock);
1635
1636         INIT_WORK(&gpu->sync_point_work, sync_point_worker);
1637         init_waitqueue_head(&gpu->fence_event);
1638
1639         priv->gpu[priv->num_gpus++] = gpu;
1640
1641         pm_runtime_mark_last_busy(gpu->dev);
1642         pm_runtime_put_autosuspend(gpu->dev);
1643
1644         return 0;
1645
1646 out_sched:
1647         etnaviv_sched_fini(gpu);
1648
1649 out_workqueue:
1650         destroy_workqueue(gpu->wq);
1651
1652 out_thermal:
1653         if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1654                 thermal_cooling_device_unregister(gpu->cooling);
1655
1656         return ret;
1657 }
1658
1659 static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1660         void *data)
1661 {
1662         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1663
1664         DBG("%s", dev_name(gpu->dev));
1665
1666         flush_workqueue(gpu->wq);
1667         destroy_workqueue(gpu->wq);
1668
1669         etnaviv_sched_fini(gpu);
1670
1671 #ifdef CONFIG_PM
1672         pm_runtime_get_sync(gpu->dev);
1673         pm_runtime_put_sync_suspend(gpu->dev);
1674 #else
1675         etnaviv_gpu_hw_suspend(gpu);
1676 #endif
1677
1678         if (gpu->buffer.suballoc)
1679                 etnaviv_cmdbuf_free(&gpu->buffer);
1680
1681         if (gpu->cmdbuf_suballoc) {
1682                 etnaviv_cmdbuf_suballoc_destroy(gpu->cmdbuf_suballoc);
1683                 gpu->cmdbuf_suballoc = NULL;
1684         }
1685
1686         if (gpu->mmu) {
1687                 etnaviv_iommu_destroy(gpu->mmu);
1688                 gpu->mmu = NULL;
1689         }
1690
1691         gpu->drm = NULL;
1692         idr_destroy(&gpu->fence_idr);
1693
1694         if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1695                 thermal_cooling_device_unregister(gpu->cooling);
1696         gpu->cooling = NULL;
1697 }
1698
1699 static const struct component_ops gpu_ops = {
1700         .bind = etnaviv_gpu_bind,
1701         .unbind = etnaviv_gpu_unbind,
1702 };
1703
1704 static const struct of_device_id etnaviv_gpu_match[] = {
1705         {
1706                 .compatible = "vivante,gc"
1707         },
1708         { /* sentinel */ }
1709 };
1710 MODULE_DEVICE_TABLE(of, etnaviv_gpu_match);
1711
1712 static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1713 {
1714         struct device *dev = &pdev->dev;
1715         struct etnaviv_gpu *gpu;
1716         struct resource *res;
1717         int err;
1718
1719         gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1720         if (!gpu)
1721                 return -ENOMEM;
1722
1723         gpu->dev = &pdev->dev;
1724         mutex_init(&gpu->lock);
1725         mutex_init(&gpu->fence_lock);
1726
1727         /* Map registers: */
1728         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1729         gpu->mmio = devm_ioremap_resource(&pdev->dev, res);
1730         if (IS_ERR(gpu->mmio))
1731                 return PTR_ERR(gpu->mmio);
1732
1733         /* Get Interrupt: */
1734         gpu->irq = platform_get_irq(pdev, 0);
1735         if (gpu->irq < 0) {
1736                 dev_err(dev, "failed to get irq: %d\n", gpu->irq);
1737                 return gpu->irq;
1738         }
1739
1740         err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1741                                dev_name(gpu->dev), gpu);
1742         if (err) {
1743                 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1744                 return err;
1745         }
1746
1747         /* Get Clocks: */
1748         gpu->clk_reg = devm_clk_get(&pdev->dev, "reg");
1749         DBG("clk_reg: %p", gpu->clk_reg);
1750         if (IS_ERR(gpu->clk_reg))
1751                 gpu->clk_reg = NULL;
1752
1753         gpu->clk_bus = devm_clk_get(&pdev->dev, "bus");
1754         DBG("clk_bus: %p", gpu->clk_bus);
1755         if (IS_ERR(gpu->clk_bus))
1756                 gpu->clk_bus = NULL;
1757
1758         gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1759         DBG("clk_core: %p", gpu->clk_core);
1760         if (IS_ERR(gpu->clk_core))
1761                 gpu->clk_core = NULL;
1762         gpu->base_rate_core = clk_get_rate(gpu->clk_core);
1763
1764         gpu->clk_shader = devm_clk_get(&pdev->dev, "shader");
1765         DBG("clk_shader: %p", gpu->clk_shader);
1766         if (IS_ERR(gpu->clk_shader))
1767                 gpu->clk_shader = NULL;
1768         gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
1769
1770         /* TODO: figure out max mapped size */
1771         dev_set_drvdata(dev, gpu);
1772
1773         /*
1774          * We treat the device as initially suspended.  The runtime PM
1775          * autosuspend delay is rather arbitary: no measurements have
1776          * yet been performed to determine an appropriate value.
1777          */
1778         pm_runtime_use_autosuspend(gpu->dev);
1779         pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1780         pm_runtime_enable(gpu->dev);
1781
1782         err = component_add(&pdev->dev, &gpu_ops);
1783         if (err < 0) {
1784                 dev_err(&pdev->dev, "failed to register component: %d\n", err);
1785                 return err;
1786         }
1787
1788         return 0;
1789 }
1790
1791 static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1792 {
1793         component_del(&pdev->dev, &gpu_ops);
1794         pm_runtime_disable(&pdev->dev);
1795         return 0;
1796 }
1797
1798 #ifdef CONFIG_PM
1799 static int etnaviv_gpu_rpm_suspend(struct device *dev)
1800 {
1801         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1802         u32 idle, mask;
1803
1804         /* If there are any jobs in the HW queue, we're not idle */
1805         if (atomic_read(&gpu->sched.hw_rq_count))
1806                 return -EBUSY;
1807
1808         /* Check whether the hardware (except FE) is idle */
1809         mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE;
1810         idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1811         if (idle != mask)
1812                 return -EBUSY;
1813
1814         return etnaviv_gpu_hw_suspend(gpu);
1815 }
1816
1817 static int etnaviv_gpu_rpm_resume(struct device *dev)
1818 {
1819         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1820         int ret;
1821
1822         ret = etnaviv_gpu_clk_enable(gpu);
1823         if (ret)
1824                 return ret;
1825
1826         /* Re-initialise the basic hardware state */
1827         if (gpu->drm && gpu->buffer.suballoc) {
1828                 ret = etnaviv_gpu_hw_resume(gpu);
1829                 if (ret) {
1830                         etnaviv_gpu_clk_disable(gpu);
1831                         return ret;
1832                 }
1833         }
1834
1835         return 0;
1836 }
1837 #endif
1838
1839 static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1840         SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
1841                            NULL)
1842 };
1843
1844 struct platform_driver etnaviv_gpu_driver = {
1845         .driver = {
1846                 .name = "etnaviv-gpu",
1847                 .owner = THIS_MODULE,
1848                 .pm = &etnaviv_gpu_pm_ops,
1849                 .of_match_table = etnaviv_gpu_match,
1850         },
1851         .probe = etnaviv_gpu_platform_probe,
1852         .remove = etnaviv_gpu_platform_remove,
1853         .id_table = gpu_ids,
1854 };