drivers/gpu/drm/etnaviv/etnaviv_gpu.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2015-2018 Etnaviv Project
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/component.h>
   8 #include <linux/delay.h>
   9 #include <linux/dma-fence.h>
  10 #include <linux/dma-mapping.h>
  11 #include <linux/module.h>
  12 #include <linux/of_device.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/regulator/consumer.h>
  16 #include <linux/thermal.h>
  17
  18 #include "etnaviv_cmdbuf.h"
  19 #include "etnaviv_dump.h"
  20 #include "etnaviv_gpu.h"
  21 #include "etnaviv_gem.h"
  22 #include "etnaviv_mmu.h"
  23 #include "etnaviv_perfmon.h"
  24 #include "etnaviv_sched.h"
  25 #include "common.xml.h"
  26 #include "state.xml.h"
  27 #include "state_hi.xml.h"
  28 #include "cmdstream.xml.h"
  29
  30 #ifndef PHYS_OFFSET
  31 #define PHYS_OFFSET 0
  32 #endif
  33
  34 static const struct platform_device_id gpu_ids[] = {
  35         { .name = "etnaviv-gpu,2d" },
  36         { },
  37 };
  38
  39 /*
  40  * Driver functions:
  41  */
  42
  43 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
  44 {
  45         switch (param) {
  46         case ETNAVIV_PARAM_GPU_MODEL:
  47                 *value = gpu->identity.model;
  48                 break;
  49
  50         case ETNAVIV_PARAM_GPU_REVISION:
  51                 *value = gpu->identity.revision;
  52                 break;
  53
  54         case ETNAVIV_PARAM_GPU_FEATURES_0:
  55                 *value = gpu->identity.features;
  56                 break;
  57
  58         case ETNAVIV_PARAM_GPU_FEATURES_1:
  59                 *value = gpu->identity.minor_features0;
  60                 break;
  61
  62         case ETNAVIV_PARAM_GPU_FEATURES_2:
  63                 *value = gpu->identity.minor_features1;
  64                 break;
  65
  66         case ETNAVIV_PARAM_GPU_FEATURES_3:
  67                 *value = gpu->identity.minor_features2;
  68                 break;
  69
  70         case ETNAVIV_PARAM_GPU_FEATURES_4:
  71                 *value = gpu->identity.minor_features3;
  72                 break;
  73
  74         case ETNAVIV_PARAM_GPU_FEATURES_5:
  75                 *value = gpu->identity.minor_features4;
  76                 break;
  77
  78         case ETNAVIV_PARAM_GPU_FEATURES_6:
  79                 *value = gpu->identity.minor_features5;
  80                 break;
  81
  82         case ETNAVIV_PARAM_GPU_FEATURES_7:
  83                 *value = gpu->identity.minor_features6;
  84                 break;
  85
  86         case ETNAVIV_PARAM_GPU_FEATURES_8:
  87                 *value = gpu->identity.minor_features7;
  88                 break;
  89
  90         case ETNAVIV_PARAM_GPU_FEATURES_9:
  91                 *value = gpu->identity.minor_features8;
  92                 break;
  93
  94         case ETNAVIV_PARAM_GPU_FEATURES_10:
  95                 *value = gpu->identity.minor_features9;
  96                 break;
  97
  98         case ETNAVIV_PARAM_GPU_FEATURES_11:
  99                 *value = gpu->identity.minor_features10;
 100                 break;
 101
 102         case ETNAVIV_PARAM_GPU_FEATURES_12:
 103                 *value = gpu->identity.minor_features11;
 104                 break;
 105
 106         case ETNAVIV_PARAM_GPU_STREAM_COUNT:
 107                 *value = gpu->identity.stream_count;
 108                 break;
 109
 110         case ETNAVIV_PARAM_GPU_REGISTER_MAX:
 111                 *value = gpu->identity.register_max;
 112                 break;
 113
 114         case ETNAVIV_PARAM_GPU_THREAD_COUNT:
 115                 *value = gpu->identity.thread_count;
 116                 break;
 117
 118         case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
 119                 *value = gpu->identity.vertex_cache_size;
 120                 break;
 121
 122         case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
 123                 *value = gpu->identity.shader_core_count;
 124                 break;
 125
 126         case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
 127                 *value = gpu->identity.pixel_pipes;
 128                 break;
 129
 130         case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
 131                 *value = gpu->identity.vertex_output_buffer_size;
 132                 break;
 133
 134         case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
 135                 *value = gpu->identity.buffer_size;
 136                 break;
 137
 138         case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
 139                 *value = gpu->identity.instruction_count;
 140                 break;
 141
 142         case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
 143                 *value = gpu->identity.num_constants;
 144                 break;
 145
 146         case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
 147                 *value = gpu->identity.varyings_count;
 148                 break;
 149
 150         default:
 151                 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
 152                 return -EINVAL;
 153         }
 154
 155         return 0;
 156 }
 157
 158
 159 #define etnaviv_is_model_rev(gpu, mod, rev) \
 160         ((gpu)->identity.model == chipModel_##mod && \
 161          (gpu)->identity.revision == rev)
 162 #define etnaviv_field(val, field) \
 163         (((val) & field##__MASK) >> field##__SHIFT)
 164
 165 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
 166 {
 167         if (gpu->identity.minor_features0 &
 168             chipMinorFeatures0_MORE_MINOR_FEATURES) {
 169                 u32 specs[4];
 170                 unsigned int streams;
 171
 172                 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
 173                 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
 174                 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
 175                 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
 176
 177                 gpu->identity.stream_count = etnaviv_field(specs[0],
 178                                         VIVS_HI_CHIP_SPECS_STREAM_COUNT);
 179                 gpu->identity.register_max = etnaviv_field(specs[0],
 180                                         VIVS_HI_CHIP_SPECS_REGISTER_MAX);
 181                 gpu->identity.thread_count = etnaviv_field(specs[0],
 182                                         VIVS_HI_CHIP_SPECS_THREAD_COUNT);
 183                 gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
 184                                         VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
 185                 gpu->identity.shader_core_count = etnaviv_field(specs[0],
 186                                         VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
 187                 gpu->identity.pixel_pipes = etnaviv_field(specs[0],
 188                                         VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
 189                 gpu->identity.vertex_output_buffer_size =
 190                         etnaviv_field(specs[0],
 191                                 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
 192
 193                 gpu->identity.buffer_size = etnaviv_field(specs[1],
 194                                         VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
 195                 gpu->identity.instruction_count = etnaviv_field(specs[1],
 196                                         VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
 197                 gpu->identity.num_constants = etnaviv_field(specs[1],
 198                                         VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
 199
 200                 gpu->identity.varyings_count = etnaviv_field(specs[2],
 201                                         VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
 202
 203                 /* This overrides the value from older register if non-zero */
 204                 streams = etnaviv_field(specs[3],
 205                                         VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
 206                 if (streams)
 207                         gpu->identity.stream_count = streams;
 208         }
 209
 210         /* Fill in the stream count if not specified */
 211         if (gpu->identity.stream_count == 0) {
 212                 if (gpu->identity.model >= 0x1000)
 213                         gpu->identity.stream_count = 4;
 214                 else
 215                         gpu->identity.stream_count = 1;
 216         }
 217
 218         /* Convert the register max value */
 219         if (gpu->identity.register_max)
 220                 gpu->identity.register_max = 1 << gpu->identity.register_max;
 221         else if (gpu->identity.model == chipModel_GC400)
 222                 gpu->identity.register_max = 32;
 223         else
 224                 gpu->identity.register_max = 64;
 225
 226         /* Convert thread count */
 227         if (gpu->identity.thread_count)
 228                 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
 229         else if (gpu->identity.model == chipModel_GC400)
 230                 gpu->identity.thread_count = 64;
 231         else if (gpu->identity.model == chipModel_GC500 ||
 232                  gpu->identity.model == chipModel_GC530)
 233                 gpu->identity.thread_count = 128;
 234         else
 235                 gpu->identity.thread_count = 256;
 236
 237         if (gpu->identity.vertex_cache_size == 0)
 238                 gpu->identity.vertex_cache_size = 8;
 239
 240         if (gpu->identity.shader_core_count == 0) {
 241                 if (gpu->identity.model >= 0x1000)
 242                         gpu->identity.shader_core_count = 2;
 243                 else
 244                         gpu->identity.shader_core_count = 1;
 245         }
 246
 247         if (gpu->identity.pixel_pipes == 0)
 248                 gpu->identity.pixel_pipes = 1;
 249
 250         /* Convert virtex buffer size */
 251         if (gpu->identity.vertex_output_buffer_size) {
 252                 gpu->identity.vertex_output_buffer_size =
 253                         1 << gpu->identity.vertex_output_buffer_size;
 254         } else if (gpu->identity.model == chipModel_GC400) {
 255                 if (gpu->identity.revision < 0x4000)
 256                         gpu->identity.vertex_output_buffer_size = 512;
 257                 else if (gpu->identity.revision < 0x4200)
 258                         gpu->identity.vertex_output_buffer_size = 256;
 259                 else
 260                         gpu->identity.vertex_output_buffer_size = 128;
 261         } else {
 262                 gpu->identity.vertex_output_buffer_size = 512;
 263         }
 264
 265         switch (gpu->identity.instruction_count) {
 266         case 0:
 267                 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
 268                     gpu->identity.model == chipModel_GC880)
 269                         gpu->identity.instruction_count = 512;
 270                 else
 271                         gpu->identity.instruction_count = 256;
 272                 break;
 273
 274         case 1:
 275                 gpu->identity.instruction_count = 1024;
 276                 break;
 277
 278         case 2:
 279                 gpu->identity.instruction_count = 2048;
 280                 break;
 281
 282         default:
 283                 gpu->identity.instruction_count = 256;
 284                 break;
 285         }
 286
 287         if (gpu->identity.num_constants == 0)
 288                 gpu->identity.num_constants = 168;
 289
 290         if (gpu->identity.varyings_count == 0) {
 291                 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
 292                         gpu->identity.varyings_count = 12;
 293                 else
 294                         gpu->identity.varyings_count = 8;
 295         }
 296
 297         /*
 298          * For some cores, two varyings are consumed for position, so the
 299          * maximum varying count needs to be reduced by one.
 300          */
 301         if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
 302             etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
 303             etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
 304             etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
 305             etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
 306             etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
 307             etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
 308             etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
 309             etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
 310             etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
 311             etnaviv_is_model_rev(gpu, GC880, 0x5106))
 312                 gpu->identity.varyings_count -= 1;
 313 }
 314
 315 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
 316 {
 317         u32 chipIdentity;
 318
 319         chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
 320
 321         /* Special case for older graphic cores. */
 322         if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
 323                 gpu->identity.model    = chipModel_GC500;
 324                 gpu->identity.revision = etnaviv_field(chipIdentity,
 325                                          VIVS_HI_CHIP_IDENTITY_REVISION);
 326         } else {
 327
 328                 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
 329                 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
 330
 331                 /*
 332                  * !!!! HACK ALERT !!!!
 333                  * Because people change device IDs without letting software
 334                  * know about it - here is the hack to make it all look the
 335                  * same.  Only for GC400 family.
 336                  */
 337                 if ((gpu->identity.model & 0xff00) == 0x0400 &&
 338                     gpu->identity.model != chipModel_GC420) {
 339                         gpu->identity.model = gpu->identity.model & 0x0400;
 340                 }
 341
 342                 /* Another special case */
 343                 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
 344                         u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
 345                         u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
 346
 347                         if (chipDate == 0x20080814 && chipTime == 0x12051100) {
 348                                 /*
 349                                  * This IP has an ECO; put the correct
 350                                  * revision in it.
 351                                  */
 352                                 gpu->identity.revision = 0x1051;
 353                         }
 354                 }
 355
 356                 /*
 357                  * NXP likes to call the GPU on the i.MX6QP GC2000+, but in
 358                  * reality it's just a re-branded GC3000. We can identify this
 359                  * core by the upper half of the revision register being all 1.
 360                  * Fix model/rev here, so all other places can refer to this
 361                  * core by its real identity.
 362                  */
 363                 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
 364                         gpu->identity.model = chipModel_GC3000;
 365                         gpu->identity.revision &= 0xffff;
 366                 }
 367         }
 368
 369         dev_info(gpu->dev, "model: GC%x, revision: %x\n",
 370                  gpu->identity.model, gpu->identity.revision);
 371
 372         gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
 373         /*
 374          * If there is a match in the HWDB, we aren't interested in the
 375          * remaining register values, as they might be wrong.
 376          */
 377         if (etnaviv_fill_identity_from_hwdb(gpu))
 378                 return;
 379
 380         gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
 381
 382         /* Disable fast clear on GC700. */
 383         if (gpu->identity.model == chipModel_GC700)
 384                 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
 385
 386         if ((gpu->identity.model == chipModel_GC500 &&
 387              gpu->identity.revision < 2) ||
 388             (gpu->identity.model == chipModel_GC300 &&
 389              gpu->identity.revision < 0x2000)) {
 390
 391                 /*
 392                  * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
 393                  * registers.
 394                  */
 395                 gpu->identity.minor_features0 = 0;
 396                 gpu->identity.minor_features1 = 0;
 397                 gpu->identity.minor_features2 = 0;
 398                 gpu->identity.minor_features3 = 0;
 399                 gpu->identity.minor_features4 = 0;
 400                 gpu->identity.minor_features5 = 0;
 401         } else
 402                 gpu->identity.minor_features0 =
 403                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
 404
 405         if (gpu->identity.minor_features0 &
 406             chipMinorFeatures0_MORE_MINOR_FEATURES) {
 407                 gpu->identity.minor_features1 =
 408                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
 409                 gpu->identity.minor_features2 =
 410                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
 411                 gpu->identity.minor_features3 =
 412                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
 413                 gpu->identity.minor_features4 =
 414                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
 415                 gpu->identity.minor_features5 =
 416                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
 417         }
 418
 419         /* GC600 idle register reports zero bits where modules aren't present */
 420         if (gpu->identity.model == chipModel_GC600)
 421                 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
 422                                  VIVS_HI_IDLE_STATE_RA |
 423                                  VIVS_HI_IDLE_STATE_SE |
 424                                  VIVS_HI_IDLE_STATE_PA |
 425                                  VIVS_HI_IDLE_STATE_SH |
 426                                  VIVS_HI_IDLE_STATE_PE |
 427                                  VIVS_HI_IDLE_STATE_DE |
 428                                  VIVS_HI_IDLE_STATE_FE;
 429
 430         etnaviv_hw_specs(gpu);
 431 }
 432
 433 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
 434 {
 435         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
 436                   VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
 437         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
 438 }
 439
 440 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
 441 {
 442         if (gpu->identity.minor_features2 &
 443             chipMinorFeatures2_DYNAMIC_FREQUENCY_SCALING) {
 444                 clk_set_rate(gpu->clk_core,
 445                              gpu->base_rate_core >> gpu->freq_scale);
 446                 clk_set_rate(gpu->clk_shader,
 447                              gpu->base_rate_shader >> gpu->freq_scale);
 448         } else {
 449                 unsigned int fscale = 1 << (6 - gpu->freq_scale);
 450                 u32 clock = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 451
 452                 clock &= ~VIVS_HI_CLOCK_CONTROL_FSCALE_VAL__MASK;
 453                 clock |= VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
 454                 etnaviv_gpu_load_clock(gpu, clock);
 455         }
 456 }
 457
 458 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
 459 {
 460         u32 control, idle;
 461         unsigned long timeout;
 462         bool failed = true;
 463
 464         /* We hope that the GPU resets in under one second */
 465         timeout = jiffies + msecs_to_jiffies(1000);
 466
 467         while (time_is_after_jiffies(timeout)) {
 468                 /* enable clock */
 469                 unsigned int fscale = 1 << (6 - gpu->freq_scale);
 470                 control = VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
 471                 etnaviv_gpu_load_clock(gpu, control);
 472
 473                 /* isolate the GPU. */
 474                 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
 475                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 476
 477                 if (gpu->sec_mode == ETNA_SEC_KERNEL) {
 478                         gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL,
 479                                   VIVS_MMUv2_AHB_CONTROL_RESET);
 480                 } else {
 481                         /* set soft reset. */
 482                         control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
 483                         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 484                 }
 485
 486                 /* wait for reset. */
 487                 usleep_range(10, 20);
 488
 489                 /* reset soft reset bit. */
 490                 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
 491                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 492
 493                 /* reset GPU isolation. */
 494                 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
 495                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 496
 497                 /* read idle register. */
 498                 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 499
 500                 /* try reseting again if FE it not idle */
 501                 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
 502                         dev_dbg(gpu->dev, "FE is not idle\n");
 503                         continue;
 504                 }
 505
 506                 /* read reset register. */
 507                 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 508
 509                 /* is the GPU idle? */
 510                 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
 511                     ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
 512                         dev_dbg(gpu->dev, "GPU is not idle\n");
 513                         continue;
 514                 }
 515
 516                 /* disable debug registers, as they are not normally needed */
 517                 control |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
 518                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 519
 520                 failed = false;
 521                 break;
 522         }
 523
 524         if (failed) {
 525                 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 526                 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 527
 528                 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
 529                         idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
 530                         control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
 531                         control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
 532
 533                 return -EBUSY;
 534         }
 535
 536         /* We rely on the GPU running, so program the clock */
 537         etnaviv_gpu_update_clock(gpu);
 538
 539         return 0;
 540 }
 541
 542 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
 543 {
 544         u32 pmc, ppc;
 545
 546         /* enable clock gating */
 547         ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
 548         ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
 549
 550         /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
 551         if (gpu->identity.revision == 0x4301 ||
 552             gpu->identity.revision == 0x4302)
 553                 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
 554
 555         gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc);
 556
 557         pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS);
 558
 559         /* Disable PA clock gating for GC400+ without bugfix except for GC420 */
 560         if (gpu->identity.model >= chipModel_GC400 &&
 561             gpu->identity.model != chipModel_GC420 &&
 562             !(gpu->identity.minor_features3 & chipMinorFeatures3_BUG_FIXES12))
 563                 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
 564
 565         /*
 566          * Disable PE clock gating on revs < 5.0.0.0 when HZ is
 567          * present without a bug fix.
 568          */
 569         if (gpu->identity.revision < 0x5000 &&
 570             gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
 571             !(gpu->identity.minor_features1 &
 572               chipMinorFeatures1_DISABLE_PE_GATING))
 573                 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
 574
 575         if (gpu->identity.revision < 0x5422)
 576                 pmc |= BIT(15); /* Unknown bit */
 577
 578         /* Disable TX clock gating on affected core revisions. */
 579         if (etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
 580             etnaviv_is_model_rev(gpu, GC2000, 0x5108))
 581                 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_TX;
 582
 583         pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
 584         pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
 585
 586         gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
 587 }
 588
 589 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
 590 {
 591         gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
 592         gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
 593                   VIVS_FE_COMMAND_CONTROL_ENABLE |
 594                   VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
 595
 596         if (gpu->sec_mode == ETNA_SEC_KERNEL) {
 597                 gpu_write(gpu, VIVS_MMUv2_SEC_COMMAND_CONTROL,
 598                           VIVS_MMUv2_SEC_COMMAND_CONTROL_ENABLE |
 599                           VIVS_MMUv2_SEC_COMMAND_CONTROL_PREFETCH(prefetch));
 600         }
 601 }
 602
 603 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
 604 {
 605         /*
 606          * Base value for VIVS_PM_PULSE_EATER register on models where it
 607          * cannot be read, extracted from vivante kernel driver.
 608          */
 609         u32 pulse_eater = 0x01590880;
 610
 611         if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
 612             etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {
 613                 pulse_eater |= BIT(23);
 614
 615         }
 616
 617         if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||
 618             etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {
 619                 pulse_eater &= ~BIT(16);
 620                 pulse_eater |= BIT(17);
 621         }
 622
 623         if ((gpu->identity.revision > 0x5420) &&
 624             (gpu->identity.features & chipFeatures_PIPE_3D))
 625         {
 626                 /* Performance fix: disable internal DFS */
 627                 pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER);
 628                 pulse_eater |= BIT(18);
 629         }
 630
 631         gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
 632 }
 633
 634 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
 635 {
 636         u16 prefetch;
 637
 638         if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
 639              etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
 640             gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
 641                 u32 mc_memory_debug;
 642
 643                 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
 644
 645                 if (gpu->identity.revision == 0x5007)
 646                         mc_memory_debug |= 0x0c;
 647                 else
 648                         mc_memory_debug |= 0x08;
 649
 650                 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
 651         }
 652
 653         /* enable module-level clock gating */
 654         etnaviv_gpu_enable_mlcg(gpu);
 655
 656         /*
 657          * Update GPU AXI cache atttribute to "cacheable, no allocate".
 658          * This is necessary to prevent the iMX6 SoC locking up.
 659          */
 660         gpu_write(gpu, VIVS_HI_AXI_CONFIG,
 661                   VIVS_HI_AXI_CONFIG_AWCACHE(2) |
 662                   VIVS_HI_AXI_CONFIG_ARCACHE(2));
 663
 664         /* GC2000 rev 5108 needs a special bus config */
 665         if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
 666                 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
 667                 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
 668                                 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
 669                 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
 670                               VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
 671                 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
 672         }
 673
 674         if (gpu->sec_mode == ETNA_SEC_KERNEL) {
 675                 u32 val = gpu_read(gpu, VIVS_MMUv2_AHB_CONTROL);
 676                 val |= VIVS_MMUv2_AHB_CONTROL_NONSEC_ACCESS;
 677                 gpu_write(gpu, VIVS_MMUv2_AHB_CONTROL, val);
 678         }
 679
 680         /* setup the pulse eater */
 681         etnaviv_gpu_setup_pulse_eater(gpu);
 682
 683         /* setup the MMU */
 684         etnaviv_iommu_restore(gpu);
 685
 686         /* Start command processor */
 687         prefetch = etnaviv_buffer_init(gpu);
 688
 689         gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
 690         etnaviv_gpu_start_fe(gpu, etnaviv_cmdbuf_get_va(&gpu->buffer),
 691                              prefetch);
 692 }
 693
 694 int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
 695 {
 696         int ret, i;
 697
 698         ret = pm_runtime_get_sync(gpu->dev);
 699         if (ret < 0) {
 700                 dev_err(gpu->dev, "Failed to enable GPU power domain\n");
 701                 return ret;
 702         }
 703
 704         etnaviv_hw_identify(gpu);
 705
 706         if (gpu->identity.model == 0) {
 707                 dev_err(gpu->dev, "Unknown GPU model\n");
 708                 ret = -ENXIO;
 709                 goto fail;
 710         }
 711
 712         /* Exclude VG cores with FE2.0 */
 713         if (gpu->identity.features & chipFeatures_PIPE_VG &&
 714             gpu->identity.features & chipFeatures_FE20) {
 715                 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
 716                 ret = -ENXIO;
 717                 goto fail;
 718         }
 719
 720         /*
 721          * Set the GPU linear window to be at the end of the DMA window, where
 722          * the CMA area is likely to reside. This ensures that we are able to
 723          * map the command buffers while having the linear window overlap as
 724          * much RAM as possible, so we can optimize mappings for other buffers.
 725          *
 726          * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads
 727          * to different views of the memory on the individual engines.
 728          */
 729         if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
 730             (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
 731                 u32 dma_mask = (u32)dma_get_required_mask(gpu->dev);
 732                 if (dma_mask < PHYS_OFFSET + SZ_2G)
 733                         gpu->memory_base = PHYS_OFFSET;
 734                 else
 735                         gpu->memory_base = dma_mask - SZ_2G + 1;
 736         } else if (PHYS_OFFSET >= SZ_2G) {
 737                 dev_info(gpu->dev, "Need to move linear window on MC1.0, disabling TS\n");
 738                 gpu->memory_base = PHYS_OFFSET;
 739                 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
 740         }
 741
 742         /*
 743          * On cores with security features supported, we claim control over the
 744          * security states.
 745          */
 746         if ((gpu->identity.minor_features7 & chipMinorFeatures7_BIT_SECURITY) &&
 747             (gpu->identity.minor_features10 & chipMinorFeatures10_SECURITY_AHB))
 748                 gpu->sec_mode = ETNA_SEC_KERNEL;
 749
 750         ret = etnaviv_hw_reset(gpu);
 751         if (ret) {
 752                 dev_err(gpu->dev, "GPU reset failed\n");
 753                 goto fail;
 754         }
 755
 756         gpu->mmu = etnaviv_iommu_new(gpu);
 757         if (IS_ERR(gpu->mmu)) {
 758                 dev_err(gpu->dev, "Failed to instantiate GPU IOMMU\n");
 759                 ret = PTR_ERR(gpu->mmu);
 760                 goto fail;
 761         }
 762
 763         gpu->cmdbuf_suballoc = etnaviv_cmdbuf_suballoc_new(gpu);
 764         if (IS_ERR(gpu->cmdbuf_suballoc)) {
 765                 dev_err(gpu->dev, "Failed to create cmdbuf suballocator\n");
 766                 ret = PTR_ERR(gpu->cmdbuf_suballoc);
 767                 goto destroy_iommu;
 768         }
 769
 770         /* Create buffer: */
 771         ret = etnaviv_cmdbuf_init(gpu->cmdbuf_suballoc, &gpu->buffer,
 772                                   PAGE_SIZE);
 773         if (ret) {
 774                 dev_err(gpu->dev, "could not create command buffer\n");
 775                 goto destroy_suballoc;
 776         }
 777
 778         if (gpu->mmu->version == ETNAVIV_IOMMU_V1 &&
 779             etnaviv_cmdbuf_get_va(&gpu->buffer) > 0x80000000) {
 780                 ret = -EINVAL;
 781                 dev_err(gpu->dev,
 782                         "command buffer outside valid memory window\n");
 783                 goto free_buffer;
 784         }
 785
 786         /* Setup event management */
 787         spin_lock_init(&gpu->event_spinlock);
 788         init_completion(&gpu->event_free);
 789         bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
 790         for (i = 0; i < ARRAY_SIZE(gpu->event); i++)
 791                 complete(&gpu->event_free);
 792
 793         /* Now program the hardware */
 794         mutex_lock(&gpu->lock);
 795         etnaviv_gpu_hw_init(gpu);
 796         gpu->exec_state = -1;
 797         mutex_unlock(&gpu->lock);
 798
 799         pm_runtime_mark_last_busy(gpu->dev);
 800         pm_runtime_put_autosuspend(gpu->dev);
 801
 802         return 0;
 803
 804 free_buffer:
 805         etnaviv_cmdbuf_free(&gpu->buffer);
 806         gpu->buffer.suballoc = NULL;
 807 destroy_suballoc:
 808         etnaviv_cmdbuf_suballoc_destroy(gpu->cmdbuf_suballoc);
 809         gpu->cmdbuf_suballoc = NULL;
 810 destroy_iommu:
 811         etnaviv_iommu_destroy(gpu->mmu);
 812         gpu->mmu = NULL;
 813 fail:
 814         pm_runtime_mark_last_busy(gpu->dev);
 815         pm_runtime_put_autosuspend(gpu->dev);
 816
 817         return ret;
 818 }
 819
 820 #ifdef CONFIG_DEBUG_FS
 821 struct dma_debug {
 822         u32 address[2];
 823         u32 state[2];
 824 };
 825
 826 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
 827 {
 828         u32 i;
 829
 830         debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 831         debug->state[0]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
 832
 833         for (i = 0; i < 500; i++) {
 834                 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 835                 debug->state[1]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
 836
 837                 if (debug->address[0] != debug->address[1])
 838                         break;
 839
 840                 if (debug->state[0] != debug->state[1])
 841                         break;
 842         }
 843 }
 844
 845 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
 846 {
 847         struct dma_debug debug;
 848         u32 dma_lo, dma_hi, axi, idle;
 849         int ret;
 850
 851         seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
 852
 853         ret = pm_runtime_get_sync(gpu->dev);
 854         if (ret < 0)
 855                 return ret;
 856
 857         dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
 858         dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
 859         axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
 860         idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 861
 862         verify_dma(gpu, &debug);
 863
 864         seq_puts(m, "\tfeatures\n");
 865         seq_printf(m, "\t major_features: 0x%08x\n",
 866                    gpu->identity.features);
 867         seq_printf(m, "\t minor_features0: 0x%08x\n",
 868                    gpu->identity.minor_features0);
 869         seq_printf(m, "\t minor_features1: 0x%08x\n",
 870                    gpu->identity.minor_features1);
 871         seq_printf(m, "\t minor_features2: 0x%08x\n",
 872                    gpu->identity.minor_features2);
 873         seq_printf(m, "\t minor_features3: 0x%08x\n",
 874                    gpu->identity.minor_features3);
 875         seq_printf(m, "\t minor_features4: 0x%08x\n",
 876                    gpu->identity.minor_features4);
 877         seq_printf(m, "\t minor_features5: 0x%08x\n",
 878                    gpu->identity.minor_features5);
 879         seq_printf(m, "\t minor_features6: 0x%08x\n",
 880                    gpu->identity.minor_features6);
 881         seq_printf(m, "\t minor_features7: 0x%08x\n",
 882                    gpu->identity.minor_features7);
 883         seq_printf(m, "\t minor_features8: 0x%08x\n",
 884                    gpu->identity.minor_features8);
 885         seq_printf(m, "\t minor_features9: 0x%08x\n",
 886                    gpu->identity.minor_features9);
 887         seq_printf(m, "\t minor_features10: 0x%08x\n",
 888                    gpu->identity.minor_features10);
 889         seq_printf(m, "\t minor_features11: 0x%08x\n",
 890                    gpu->identity.minor_features11);
 891
 892         seq_puts(m, "\tspecs\n");
 893         seq_printf(m, "\t stream_count:  %d\n",
 894                         gpu->identity.stream_count);
 895         seq_printf(m, "\t register_max: %d\n",
 896                         gpu->identity.register_max);
 897         seq_printf(m, "\t thread_count: %d\n",
 898                         gpu->identity.thread_count);
 899         seq_printf(m, "\t vertex_cache_size: %d\n",
 900                         gpu->identity.vertex_cache_size);
 901         seq_printf(m, "\t shader_core_count: %d\n",
 902                         gpu->identity.shader_core_count);
 903         seq_printf(m, "\t pixel_pipes: %d\n",
 904                         gpu->identity.pixel_pipes);
 905         seq_printf(m, "\t vertex_output_buffer_size: %d\n",
 906                         gpu->identity.vertex_output_buffer_size);
 907         seq_printf(m, "\t buffer_size: %d\n",
 908                         gpu->identity.buffer_size);
 909         seq_printf(m, "\t instruction_count: %d\n",
 910                         gpu->identity.instruction_count);
 911         seq_printf(m, "\t num_constants: %d\n",
 912                         gpu->identity.num_constants);
 913         seq_printf(m, "\t varyings_count: %d\n",
 914                         gpu->identity.varyings_count);
 915
 916         seq_printf(m, "\taxi: 0x%08x\n", axi);
 917         seq_printf(m, "\tidle: 0x%08x\n", idle);
 918         idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
 919         if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
 920                 seq_puts(m, "\t FE is not idle\n");
 921         if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
 922                 seq_puts(m, "\t DE is not idle\n");
 923         if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
 924                 seq_puts(m, "\t PE is not idle\n");
 925         if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
 926                 seq_puts(m, "\t SH is not idle\n");
 927         if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
 928                 seq_puts(m, "\t PA is not idle\n");
 929         if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
 930                 seq_puts(m, "\t SE is not idle\n");
 931         if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
 932                 seq_puts(m, "\t RA is not idle\n");
 933         if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
 934                 seq_puts(m, "\t TX is not idle\n");
 935         if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
 936                 seq_puts(m, "\t VG is not idle\n");
 937         if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
 938                 seq_puts(m, "\t IM is not idle\n");
 939         if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
 940                 seq_puts(m, "\t FP is not idle\n");
 941         if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
 942                 seq_puts(m, "\t TS is not idle\n");
 943         if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
 944                 seq_puts(m, "\t AXI low power mode\n");
 945
 946         if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
 947                 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
 948                 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
 949                 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
 950
 951                 seq_puts(m, "\tMC\n");
 952                 seq_printf(m, "\t read0: 0x%08x\n", read0);
 953                 seq_printf(m, "\t read1: 0x%08x\n", read1);
 954                 seq_printf(m, "\t write: 0x%08x\n", write);
 955         }
 956
 957         seq_puts(m, "\tDMA ");
 958
 959         if (debug.address[0] == debug.address[1] &&
 960             debug.state[0] == debug.state[1]) {
 961                 seq_puts(m, "seems to be stuck\n");
 962         } else if (debug.address[0] == debug.address[1]) {
 963                 seq_puts(m, "address is constant\n");
 964         } else {
 965                 seq_puts(m, "is running\n");
 966         }
 967
 968         seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
 969         seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
 970         seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
 971         seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
 972         seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
 973                    dma_lo, dma_hi);
 974
 975         ret = 0;
 976
 977         pm_runtime_mark_last_busy(gpu->dev);
 978         pm_runtime_put_autosuspend(gpu->dev);
 979
 980         return ret;
 981 }
 982 #endif
 983
 984 void etnaviv_gpu_recover_hang(struct etnaviv_gpu *gpu)
 985 {
 986         unsigned int i = 0;
 987
 988         dev_err(gpu->dev, "recover hung GPU!\n");
 989
 990         if (pm_runtime_get_sync(gpu->dev) < 0)
 991                 return;
 992
 993         mutex_lock(&gpu->lock);
 994
 995         etnaviv_hw_reset(gpu);
 996
 997         /* complete all events, the GPU won't do it after the reset */
 998         spin_lock(&gpu->event_spinlock);
 999         for_each_set_bit_from(i, gpu->event_bitmap, ETNA_NR_EVENTS)
1000                 complete(&gpu->event_free);
1001         bitmap_zero(gpu->event_bitmap, ETNA_NR_EVENTS);
1002         spin_unlock(&gpu->event_spinlock);
1003
1004         etnaviv_gpu_hw_init(gpu);
1005         gpu->exec_state = -1;
1006
1007         mutex_unlock(&gpu->lock);
1008         pm_runtime_mark_last_busy(gpu->dev);
1009         pm_runtime_put_autosuspend(gpu->dev);
1010 }
1011
1012 /* fence object management */
1013 struct etnaviv_fence {
1014         struct etnaviv_gpu *gpu;
1015         struct dma_fence base;
1016 };
1017
1018 static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence)
1019 {
1020         return container_of(fence, struct etnaviv_fence, base);
1021 }
1022
1023 static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence)
1024 {
1025         return "etnaviv";
1026 }
1027
1028 static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence)
1029 {
1030         struct etnaviv_fence *f = to_etnaviv_fence(fence);
1031
1032         return dev_name(f->gpu->dev);
1033 }
1034
1035 static bool etnaviv_fence_signaled(struct dma_fence *fence)
1036 {
1037         struct etnaviv_fence *f = to_etnaviv_fence(fence);
1038
1039         return (s32)(f->gpu->completed_fence - f->base.seqno) >= 0;
1040 }
1041
1042 static void etnaviv_fence_release(struct dma_fence *fence)
1043 {
1044         struct etnaviv_fence *f = to_etnaviv_fence(fence);
1045
1046         kfree_rcu(f, base.rcu);
1047 }
1048
1049 static const struct dma_fence_ops etnaviv_fence_ops = {
1050         .get_driver_name = etnaviv_fence_get_driver_name,
1051         .get_timeline_name = etnaviv_fence_get_timeline_name,
1052         .signaled = etnaviv_fence_signaled,
1053         .release = etnaviv_fence_release,
1054 };
1055
1056 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
1057 {
1058         struct etnaviv_fence *f;
1059
1060         /*
1061          * GPU lock must already be held, otherwise fence completion order might
1062          * not match the seqno order assigned here.
1063          */
1064         lockdep_assert_held(&gpu->lock);
1065
1066         f = kzalloc(sizeof(*f), GFP_KERNEL);
1067         if (!f)
1068                 return NULL;
1069
1070         f->gpu = gpu;
1071
1072         dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1073                        gpu->fence_context, ++gpu->next_fence);
1074
1075         return &f->base;
1076 }
1077
1078 /* returns true if fence a comes after fence b */
1079 static inline bool fence_after(u32 a, u32 b)
1080 {
1081         return (s32)(a - b) > 0;
1082 }
1083
1084 /*
1085  * event management:
1086  */
1087
1088 static int event_alloc(struct etnaviv_gpu *gpu, unsigned nr_events,
1089         unsigned int *events)
1090 {
1091         unsigned long timeout = msecs_to_jiffies(10 * 10000);
1092         unsigned i, acquired = 0;
1093
1094         for (i = 0; i < nr_events; i++) {
1095                 unsigned long ret;
1096
1097                 ret = wait_for_completion_timeout(&gpu->event_free, timeout);
1098
1099                 if (!ret) {
1100                         dev_err(gpu->dev, "wait_for_completion_timeout failed");
1101                         goto out;
1102                 }
1103
1104                 acquired++;
1105                 timeout = ret;
1106         }
1107
1108         spin_lock(&gpu->event_spinlock);
1109
1110         for (i = 0; i < nr_events; i++) {
1111                 int event = find_first_zero_bit(gpu->event_bitmap, ETNA_NR_EVENTS);
1112
1113                 events[i] = event;
1114                 memset(&gpu->event[event], 0, sizeof(struct etnaviv_event));
1115                 set_bit(event, gpu->event_bitmap);
1116         }
1117
1118         spin_unlock(&gpu->event_spinlock);
1119
1120         return 0;
1121
1122 out:
1123         for (i = 0; i < acquired; i++)
1124                 complete(&gpu->event_free);
1125
1126         return -EBUSY;
1127 }
1128
1129 static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1130 {
1131         if (!test_bit(event, gpu->event_bitmap)) {
1132                 dev_warn(gpu->dev, "event %u is already marked as free",
1133                          event);
1134         } else {
1135                 clear_bit(event, gpu->event_bitmap);
1136                 complete(&gpu->event_free);
1137         }
1138 }
1139
1140 /*
1141  * Cmdstream submission/retirement:
1142  */
1143 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1144         u32 id, struct timespec *timeout)
1145 {
1146         struct dma_fence *fence;
1147         int ret;
1148
1149         /*
1150          * Look up the fence and take a reference. We might still find a fence
1151          * whose refcount has already dropped to zero. dma_fence_get_rcu
1152          * pretends we didn't find a fence in that case.
1153          */
1154         rcu_read_lock();
1155         fence = idr_find(&gpu->fence_idr, id);
1156         if (fence)
1157                 fence = dma_fence_get_rcu(fence);
1158         rcu_read_unlock();
1159
1160         if (!fence)
1161                 return 0;
1162
1163         if (!timeout) {
1164                 /* No timeout was requested: just test for completion */
1165                 ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;
1166         } else {
1167                 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1168
1169                 ret = dma_fence_wait_timeout(fence, true, remaining);
1170                 if (ret == 0)
1171                         ret = -ETIMEDOUT;
1172                 else if (ret != -ERESTARTSYS)
1173                         ret = 0;
1174
1175         }
1176
1177         dma_fence_put(fence);
1178         return ret;
1179 }
1180
1181 /*
1182  * Wait for an object to become inactive.  This, on it's own, is not race
1183  * free: the object is moved by the scheduler off the active list, and
1184  * then the iova is put.  Moreover, the object could be re-submitted just
1185  * after we notice that it's become inactive.
1186  *
1187  * Although the retirement happens under the gpu lock, we don't want to hold
1188  * that lock in this function while waiting.
1189  */
1190 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1191         struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout)
1192 {
1193         unsigned long remaining;
1194         long ret;
1195
1196         if (!timeout)
1197                 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1198
1199         remaining = etnaviv_timeout_to_jiffies(timeout);
1200
1201         ret = wait_event_interruptible_timeout(gpu->fence_event,
1202                                                !is_active(etnaviv_obj),
1203                                                remaining);
1204         if (ret > 0)
1205                 return 0;
1206         else if (ret == -ERESTARTSYS)
1207                 return -ERESTARTSYS;
1208         else
1209                 return -ETIMEDOUT;
1210 }
1211
1212 static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu,
1213         struct etnaviv_event *event, unsigned int flags)
1214 {
1215         const struct etnaviv_gem_submit *submit = event->submit;
1216         unsigned int i;
1217
1218         for (i = 0; i < submit->nr_pmrs; i++) {
1219                 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1220
1221                 if (pmr->flags == flags)
1222                         etnaviv_perfmon_process(gpu, pmr, submit->exec_state);
1223         }
1224 }
1225
1226 static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu,
1227         struct etnaviv_event *event)
1228 {
1229         u32 val;
1230
1231         /* disable clock gating */
1232         val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1233         val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1234         gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1235
1236         /* enable debug register */
1237         val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1238         val &= ~VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1239         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1240
1241         sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE);
1242 }
1243
1244 static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu,
1245         struct etnaviv_event *event)
1246 {
1247         const struct etnaviv_gem_submit *submit = event->submit;
1248         unsigned int i;
1249         u32 val;
1250
1251         sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST);
1252
1253         for (i = 0; i < submit->nr_pmrs; i++) {
1254                 const struct etnaviv_perfmon_request *pmr = submit->pmrs + i;
1255
1256                 *pmr->bo_vma = pmr->sequence;
1257         }
1258
1259         /* disable debug register */
1260         val = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
1261         val |= VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS;
1262         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, val);
1263
1264         /* enable clock gating */
1265         val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
1266         val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
1267         gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val);
1268 }
1269
1270
1271 /* add bo's to gpu's ring, and kick gpu: */
1272 struct dma_fence *etnaviv_gpu_submit(struct etnaviv_gem_submit *submit)
1273 {
1274         struct etnaviv_gpu *gpu = submit->gpu;
1275         struct dma_fence *gpu_fence;
1276         unsigned int i, nr_events = 1, event[3];
1277         int ret;
1278
1279         if (!submit->runtime_resumed) {
1280                 ret = pm_runtime_get_sync(gpu->dev);
1281                 if (ret < 0)
1282                         return NULL;
1283                 submit->runtime_resumed = true;
1284         }
1285
1286         /*
1287          * if there are performance monitor requests we need to have
1288          * - a sync point to re-configure gpu and process ETNA_PM_PROCESS_PRE
1289          *   requests.
1290          * - a sync point to re-configure gpu, process ETNA_PM_PROCESS_POST requests
1291          *   and update the sequence number for userspace.
1292          */
1293         if (submit->nr_pmrs)
1294                 nr_events = 3;
1295
1296         ret = event_alloc(gpu, nr_events, event);
1297         if (ret) {
1298                 DRM_ERROR("no free events\n");
1299                 return NULL;
1300         }
1301
1302         mutex_lock(&gpu->lock);
1303
1304         gpu_fence = etnaviv_gpu_fence_alloc(gpu);
1305         if (!gpu_fence) {
1306                 for (i = 0; i < nr_events; i++)
1307                         event_free(gpu, event[i]);
1308
1309                 goto out_unlock;
1310         }
1311
1312         if (submit->nr_pmrs) {
1313                 gpu->event[event[1]].sync_point = &sync_point_perfmon_sample_pre;
1314                 kref_get(&submit->refcount);
1315                 gpu->event[event[1]].submit = submit;
1316                 etnaviv_sync_point_queue(gpu, event[1]);
1317         }
1318
1319         gpu->event[event[0]].fence = gpu_fence;
1320         submit->cmdbuf.user_size = submit->cmdbuf.size - 8;
1321         etnaviv_buffer_queue(gpu, submit->exec_state, event[0],
1322                              &submit->cmdbuf);
1323
1324         if (submit->nr_pmrs) {
1325                 gpu->event[event[2]].sync_point = &sync_point_perfmon_sample_post;
1326                 kref_get(&submit->refcount);
1327                 gpu->event[event[2]].submit = submit;
1328                 etnaviv_sync_point_queue(gpu, event[2]);
1329         }
1330
1331 out_unlock:
1332         mutex_unlock(&gpu->lock);
1333
1334         return gpu_fence;
1335 }
1336
1337 static void sync_point_worker(struct work_struct *work)
1338 {
1339         struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1340                                                sync_point_work);
1341         struct etnaviv_event *event = &gpu->event[gpu->sync_point_event];
1342         u32 addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
1343
1344         event->sync_point(gpu, event);
1345         etnaviv_submit_put(event->submit);
1346         event_free(gpu, gpu->sync_point_event);
1347
1348         /* restart FE last to avoid GPU and IRQ racing against this worker */
1349         etnaviv_gpu_start_fe(gpu, addr + 2, 2);
1350 }
1351
1352 static void dump_mmu_fault(struct etnaviv_gpu *gpu)
1353 {
1354         u32 status_reg, status;
1355         int i;
1356
1357         if (gpu->sec_mode == ETNA_SEC_NONE)
1358                 status_reg = VIVS_MMUv2_STATUS;
1359         else
1360                 status_reg = VIVS_MMUv2_SEC_STATUS;
1361
1362         status = gpu_read(gpu, status_reg);
1363         dev_err_ratelimited(gpu->dev, "MMU fault status 0x%08x\n", status);
1364
1365         for (i = 0; i < 4; i++) {
1366                 u32 address_reg;
1367
1368                 if (!(status & (VIVS_MMUv2_STATUS_EXCEPTION0__MASK << (i * 4))))
1369                         continue;
1370
1371                 if (gpu->sec_mode == ETNA_SEC_NONE)
1372                         address_reg = VIVS_MMUv2_EXCEPTION_ADDR(i);
1373                 else
1374                         address_reg = VIVS_MMUv2_SEC_EXCEPTION_ADDR;
1375
1376                 dev_err_ratelimited(gpu->dev, "MMU %d fault addr 0x%08x\n", i,
1377                                     gpu_read(gpu, address_reg));
1378         }
1379 }
1380
1381 static irqreturn_t irq_handler(int irq, void *data)
1382 {
1383         struct etnaviv_gpu *gpu = data;
1384         irqreturn_t ret = IRQ_NONE;
1385
1386         u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1387
1388         if (intr != 0) {
1389                 int event;
1390
1391                 pm_runtime_mark_last_busy(gpu->dev);
1392
1393                 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1394
1395                 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1396                         dev_err(gpu->dev, "AXI bus error\n");
1397                         intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1398                 }
1399
1400                 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
1401                         dump_mmu_fault(gpu);
1402                         intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
1403                 }
1404
1405                 while ((event = ffs(intr)) != 0) {
1406                         struct dma_fence *fence;
1407
1408                         event -= 1;
1409
1410                         intr &= ~(1 << event);
1411
1412                         dev_dbg(gpu->dev, "event %u\n", event);
1413
1414                         if (gpu->event[event].sync_point) {
1415                                 gpu->sync_point_event = event;
1416                                 queue_work(gpu->wq, &gpu->sync_point_work);
1417                         }
1418
1419                         fence = gpu->event[event].fence;
1420                         if (!fence)
1421                                 continue;
1422
1423                         gpu->event[event].fence = NULL;
1424
1425                         /*
1426                          * Events can be processed out of order.  Eg,
1427                          * - allocate and queue event 0
1428                          * - allocate event 1
1429                          * - event 0 completes, we process it
1430                          * - allocate and queue event 0
1431                          * - event 1 and event 0 complete
1432                          * we can end up processing event 0 first, then 1.
1433                          */
1434                         if (fence_after(fence->seqno, gpu->completed_fence))
1435                                 gpu->completed_fence = fence->seqno;
1436                         dma_fence_signal(fence);
1437
1438                         event_free(gpu, event);
1439                 }
1440
1441                 ret = IRQ_HANDLED;
1442         }
1443
1444         return ret;
1445 }
1446
1447 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1448 {
1449         int ret;
1450
1451         if (gpu->clk_reg) {
1452                 ret = clk_prepare_enable(gpu->clk_reg);
1453                 if (ret)
1454                         return ret;
1455         }
1456
1457         if (gpu->clk_bus) {
1458                 ret = clk_prepare_enable(gpu->clk_bus);
1459                 if (ret)
1460                         return ret;
1461         }
1462
1463         if (gpu->clk_core) {
1464                 ret = clk_prepare_enable(gpu->clk_core);
1465                 if (ret)
1466                         goto disable_clk_bus;
1467         }
1468
1469         if (gpu->clk_shader) {
1470                 ret = clk_prepare_enable(gpu->clk_shader);
1471                 if (ret)
1472                         goto disable_clk_core;
1473         }
1474
1475         return 0;
1476
1477 disable_clk_core:
1478         if (gpu->clk_core)
1479                 clk_disable_unprepare(gpu->clk_core);
1480 disable_clk_bus:
1481         if (gpu->clk_bus)
1482                 clk_disable_unprepare(gpu->clk_bus);
1483
1484         return ret;
1485 }
1486
1487 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1488 {
1489         if (gpu->clk_shader)
1490                 clk_disable_unprepare(gpu->clk_shader);
1491         if (gpu->clk_core)
1492                 clk_disable_unprepare(gpu->clk_core);
1493         if (gpu->clk_bus)
1494                 clk_disable_unprepare(gpu->clk_bus);
1495         if (gpu->clk_reg)
1496                 clk_disable_unprepare(gpu->clk_reg);
1497
1498         return 0;
1499 }
1500
1501 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
1502 {
1503         unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
1504
1505         do {
1506                 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1507
1508                 if ((idle & gpu->idle_mask) == gpu->idle_mask)
1509                         return 0;
1510
1511                 if (time_is_before_jiffies(timeout)) {
1512                         dev_warn(gpu->dev,
1513                                  "timed out waiting for idle: idle=0x%x\n",
1514                                  idle);
1515                         return -ETIMEDOUT;
1516                 }
1517
1518                 udelay(5);
1519         } while (1);
1520 }
1521
1522 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1523 {
1524         if (gpu->buffer.suballoc) {
1525                 /* Replace the last WAIT with END */
1526                 mutex_lock(&gpu->lock);
1527                 etnaviv_buffer_end(gpu);
1528                 mutex_unlock(&gpu->lock);
1529
1530                 /*
1531                  * We know that only the FE is busy here, this should
1532                  * happen quickly (as the WAIT is only 200 cycles).  If
1533                  * we fail, just warn and continue.
1534                  */
1535                 etnaviv_gpu_wait_idle(gpu, 100);
1536         }
1537
1538         return etnaviv_gpu_clk_disable(gpu);
1539 }
1540
1541 #ifdef CONFIG_PM
1542 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1543 {
1544         int ret;
1545
1546         ret = mutex_lock_killable(&gpu->lock);
1547         if (ret)
1548                 return ret;
1549
1550         etnaviv_gpu_update_clock(gpu);
1551         etnaviv_gpu_hw_init(gpu);
1552
1553         gpu->exec_state = -1;
1554
1555         mutex_unlock(&gpu->lock);
1556
1557         return 0;
1558 }
1559 #endif
1560
1561 static int
1562 etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev,
1563                                   unsigned long *state)
1564 {
1565         *state = 6;
1566
1567         return 0;
1568 }
1569
1570 static int
1571 etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev,
1572                                   unsigned long *state)
1573 {
1574         struct etnaviv_gpu *gpu = cdev->devdata;
1575
1576         *state = gpu->freq_scale;
1577
1578         return 0;
1579 }
1580
1581 static int
1582 etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev,
1583                                   unsigned long state)
1584 {
1585         struct etnaviv_gpu *gpu = cdev->devdata;
1586
1587         mutex_lock(&gpu->lock);
1588         gpu->freq_scale = state;
1589         if (!pm_runtime_suspended(gpu->dev))
1590                 etnaviv_gpu_update_clock(gpu);
1591         mutex_unlock(&gpu->lock);
1592
1593         return 0;
1594 }
1595
1596 static struct thermal_cooling_device_ops cooling_ops = {
1597         .get_max_state = etnaviv_gpu_cooling_get_max_state,
1598         .get_cur_state = etnaviv_gpu_cooling_get_cur_state,
1599         .set_cur_state = etnaviv_gpu_cooling_set_cur_state,
1600 };
1601
1602 static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1603         void *data)
1604 {
1605         struct drm_device *drm = data;
1606         struct etnaviv_drm_private *priv = drm->dev_private;
1607         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1608         int ret;
1609
1610         if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL)) {
1611                 gpu->cooling = thermal_of_cooling_device_register(dev->of_node,
1612                                 (char *)dev_name(dev), gpu, &cooling_ops);
1613                 if (IS_ERR(gpu->cooling))
1614                         return PTR_ERR(gpu->cooling);
1615         }
1616
1617         gpu->wq = alloc_ordered_workqueue(dev_name(dev), 0);
1618         if (!gpu->wq) {
1619                 ret = -ENOMEM;
1620                 goto out_thermal;
1621         }
1622
1623         ret = etnaviv_sched_init(gpu);
1624         if (ret)
1625                 goto out_workqueue;
1626
1627 #ifdef CONFIG_PM
1628         ret = pm_runtime_get_sync(gpu->dev);
1629 #else
1630         ret = etnaviv_gpu_clk_enable(gpu);
1631 #endif
1632         if (ret < 0)
1633                 goto out_sched;
1634
1635
1636         gpu->drm = drm;
1637         gpu->fence_context = dma_fence_context_alloc(1);
1638         idr_init(&gpu->fence_idr);
1639         spin_lock_init(&gpu->fence_spinlock);
1640
1641         INIT_WORK(&gpu->sync_point_work, sync_point_worker);
1642         init_waitqueue_head(&gpu->fence_event);
1643
1644         priv->gpu[priv->num_gpus++] = gpu;
1645
1646         pm_runtime_mark_last_busy(gpu->dev);
1647         pm_runtime_put_autosuspend(gpu->dev);
1648
1649         return 0;
1650
1651 out_sched:
1652         etnaviv_sched_fini(gpu);
1653
1654 out_workqueue:
1655         destroy_workqueue(gpu->wq);
1656
1657 out_thermal:
1658         if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1659                 thermal_cooling_device_unregister(gpu->cooling);
1660
1661         return ret;
1662 }
1663
1664 static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1665         void *data)
1666 {
1667         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1668
1669         DBG("%s", dev_name(gpu->dev));
1670
1671         flush_workqueue(gpu->wq);
1672         destroy_workqueue(gpu->wq);
1673
1674         etnaviv_sched_fini(gpu);
1675
1676 #ifdef CONFIG_PM
1677         pm_runtime_get_sync(gpu->dev);
1678         pm_runtime_put_sync_suspend(gpu->dev);
1679 #else
1680         etnaviv_gpu_hw_suspend(gpu);
1681 #endif
1682
1683         if (gpu->buffer.suballoc)
1684                 etnaviv_cmdbuf_free(&gpu->buffer);
1685
1686         if (gpu->cmdbuf_suballoc) {
1687                 etnaviv_cmdbuf_suballoc_destroy(gpu->cmdbuf_suballoc);
1688                 gpu->cmdbuf_suballoc = NULL;
1689         }
1690
1691         if (gpu->mmu) {
1692                 etnaviv_iommu_destroy(gpu->mmu);
1693                 gpu->mmu = NULL;
1694         }
1695
1696         gpu->drm = NULL;
1697         idr_destroy(&gpu->fence_idr);
1698
1699         if (IS_ENABLED(CONFIG_DRM_ETNAVIV_THERMAL))
1700                 thermal_cooling_device_unregister(gpu->cooling);
1701         gpu->cooling = NULL;
1702 }
1703
1704 static const struct component_ops gpu_ops = {
1705         .bind = etnaviv_gpu_bind,
1706         .unbind = etnaviv_gpu_unbind,
1707 };
1708
1709 static const struct of_device_id etnaviv_gpu_match[] = {
1710         {
1711                 .compatible = "vivante,gc"
1712         },
1713         { /* sentinel */ }
1714 };
1715 MODULE_DEVICE_TABLE(of, etnaviv_gpu_match);
1716
1717 static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1718 {
1719         struct device *dev = &pdev->dev;
1720         struct etnaviv_gpu *gpu;
1721         int err;
1722
1723         gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1724         if (!gpu)
1725                 return -ENOMEM;
1726
1727         gpu->dev = &pdev->dev;
1728         mutex_init(&gpu->lock);
1729         mutex_init(&gpu->fence_lock);
1730
1731         /* Map registers: */
1732         gpu->mmio = devm_platform_ioremap_resource(pdev, 0);
1733         if (IS_ERR(gpu->mmio))
1734                 return PTR_ERR(gpu->mmio);
1735
1736         /* Get Interrupt: */
1737         gpu->irq = platform_get_irq(pdev, 0);
1738         if (gpu->irq < 0) {
1739                 dev_err(dev, "failed to get irq: %d\n", gpu->irq);
1740                 return gpu->irq;
1741         }
1742
1743         err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1744                                dev_name(gpu->dev), gpu);
1745         if (err) {
1746                 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1747                 return err;
1748         }
1749
1750         /* Get Clocks: */
1751         gpu->clk_reg = devm_clk_get(&pdev->dev, "reg");
1752         DBG("clk_reg: %p", gpu->clk_reg);
1753         if (IS_ERR(gpu->clk_reg))
1754                 gpu->clk_reg = NULL;
1755
1756         gpu->clk_bus = devm_clk_get(&pdev->dev, "bus");
1757         DBG("clk_bus: %p", gpu->clk_bus);
1758         if (IS_ERR(gpu->clk_bus))
1759                 gpu->clk_bus = NULL;
1760
1761         gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1762         DBG("clk_core: %p", gpu->clk_core);
1763         if (IS_ERR(gpu->clk_core))
1764                 gpu->clk_core = NULL;
1765         gpu->base_rate_core = clk_get_rate(gpu->clk_core);
1766
1767         gpu->clk_shader = devm_clk_get(&pdev->dev, "shader");
1768         DBG("clk_shader: %p", gpu->clk_shader);
1769         if (IS_ERR(gpu->clk_shader))
1770                 gpu->clk_shader = NULL;
1771         gpu->base_rate_shader = clk_get_rate(gpu->clk_shader);
1772
1773         /* TODO: figure out max mapped size */
1774         dev_set_drvdata(dev, gpu);
1775
1776         /*
1777          * We treat the device as initially suspended.  The runtime PM
1778          * autosuspend delay is rather arbitary: no measurements have
1779          * yet been performed to determine an appropriate value.
1780          */
1781         pm_runtime_use_autosuspend(gpu->dev);
1782         pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1783         pm_runtime_enable(gpu->dev);
1784
1785         err = component_add(&pdev->dev, &gpu_ops);
1786         if (err < 0) {
1787                 dev_err(&pdev->dev, "failed to register component: %d\n", err);
1788                 return err;
1789         }
1790
1791         return 0;
1792 }
1793
1794 static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1795 {
1796         component_del(&pdev->dev, &gpu_ops);
1797         pm_runtime_disable(&pdev->dev);
1798         return 0;
1799 }
1800
1801 #ifdef CONFIG_PM
1802 static int etnaviv_gpu_rpm_suspend(struct device *dev)
1803 {
1804         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1805         u32 idle, mask;
1806
1807         /* If there are any jobs in the HW queue, we're not idle */
1808         if (atomic_read(&gpu->sched.hw_rq_count))
1809                 return -EBUSY;
1810
1811         /* Check whether the hardware (except FE) is idle */
1812         mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE;
1813         idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1814         if (idle != mask)
1815                 return -EBUSY;
1816
1817         return etnaviv_gpu_hw_suspend(gpu);
1818 }
1819
1820 static int etnaviv_gpu_rpm_resume(struct device *dev)
1821 {
1822         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1823         int ret;
1824
1825         ret = etnaviv_gpu_clk_enable(gpu);
1826         if (ret)
1827                 return ret;
1828
1829         /* Re-initialise the basic hardware state */
1830         if (gpu->drm && gpu->buffer.suballoc) {
1831                 ret = etnaviv_gpu_hw_resume(gpu);
1832                 if (ret) {
1833                         etnaviv_gpu_clk_disable(gpu);
1834                         return ret;
1835                 }
1836         }
1837
1838         return 0;
1839 }
1840 #endif
1841
1842 static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1843         SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
1844                            NULL)
1845 };
1846
1847 struct platform_driver etnaviv_gpu_driver = {
1848         .driver = {
1849                 .name = "etnaviv-gpu",
1850                 .owner = THIS_MODULE,
1851                 .pm = &etnaviv_gpu_pm_ops,
1852                 .of_match_table = etnaviv_gpu_match,
1853         },
1854         .probe = etnaviv_gpu_platform_probe,
1855         .remove = etnaviv_gpu_platform_remove,
1856         .id_table = gpu_ids,
1857 };