drivers/gpu/drm/drm_dp_helper.c

   1 /*
   2  * Copyright © 2009 Keith Packard
   3  *
   4  * Permission to use, copy, modify, distribute, and sell this software and its
   5  * documentation for any purpose is hereby granted without fee, provided that
   6  * the above copyright notice appear in all copies and that both that copyright
   7  * notice and this permission notice appear in supporting documentation, and
   8  * that the name of the copyright holders not be used in advertising or
   9  * publicity pertaining to distribution of the software without specific,
  10  * written prior permission.  The copyright holders make no representations
  11  * about the suitability of this software for any purpose.  It is provided "as
  12  * is" without express or implied warranty.
  13  *
  14  * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
  15  * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
  16  * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
  17  * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
  18  * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  19  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
  20  * OF THIS SOFTWARE.
  21  */
  22
  23 #include <linux/delay.h>
  24 #include <linux/errno.h>
  25 #include <linux/i2c.h>
  26 #include <linux/init.h>
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/sched.h>
  30 #include <linux/seq_file.h>
  31
  32 #include <drm/drm_dp_helper.h>
  33 #include <drm/drm_print.h>
  34 #include <drm/drm_vblank.h>
  35 #include <drm/drm_dp_mst_helper.h>
  36
  37 #include "drm_crtc_helper_internal.h"
  38
  39 /**
  40  * DOC: dp helpers
  41  *
  42  * These functions contain some common logic and helpers at various abstraction
  43  * levels to deal with Display Port sink devices and related things like DP aux
  44  * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
  45  * blocks, ...
  46  */
  47
  48 /* Helpers for DP link training */
  49 static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
  50 {
  51         return link_status[r - DP_LANE0_1_STATUS];
  52 }
  53
  54 static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
  55                              int lane)
  56 {
  57         int i = DP_LANE0_1_STATUS + (lane >> 1);
  58         int s = (lane & 1) * 4;
  59         u8 l = dp_link_status(link_status, i);
  60
  61         return (l >> s) & 0xf;
  62 }
  63
  64 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
  65                           int lane_count)
  66 {
  67         u8 lane_align;
  68         u8 lane_status;
  69         int lane;
  70
  71         lane_align = dp_link_status(link_status,
  72                                     DP_LANE_ALIGN_STATUS_UPDATED);
  73         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
  74                 return false;
  75         for (lane = 0; lane < lane_count; lane++) {
  76                 lane_status = dp_get_lane_status(link_status, lane);
  77                 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
  78                         return false;
  79         }
  80         return true;
  81 }
  82 EXPORT_SYMBOL(drm_dp_channel_eq_ok);
  83
  84 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
  85                               int lane_count)
  86 {
  87         int lane;
  88         u8 lane_status;
  89
  90         for (lane = 0; lane < lane_count; lane++) {
  91                 lane_status = dp_get_lane_status(link_status, lane);
  92                 if ((lane_status & DP_LANE_CR_DONE) == 0)
  93                         return false;
  94         }
  95         return true;
  96 }
  97 EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
  98
  99 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
 100                                      int lane)
 101 {
 102         int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 103         int s = ((lane & 1) ?
 104                  DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
 105                  DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
 106         u8 l = dp_link_status(link_status, i);
 107
 108         return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
 109 }
 110 EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
 111
 112 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
 113                                           int lane)
 114 {
 115         int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 116         int s = ((lane & 1) ?
 117                  DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
 118                  DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
 119         u8 l = dp_link_status(link_status, i);
 120
 121         return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
 122 }
 123 EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
 124
 125 u8 drm_dp_get_adjust_request_post_cursor(const u8 link_status[DP_LINK_STATUS_SIZE],
 126                                          unsigned int lane)
 127 {
 128         unsigned int offset = DP_ADJUST_REQUEST_POST_CURSOR2;
 129         u8 value = dp_link_status(link_status, offset);
 130
 131         return (value >> (lane << 1)) & 0x3;
 132 }
 133 EXPORT_SYMBOL(drm_dp_get_adjust_request_post_cursor);
 134
 135 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
 136                                             const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 137 {
 138         unsigned long rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
 139                                          DP_TRAINING_AUX_RD_MASK;
 140
 141         if (rd_interval > 4)
 142                 drm_dbg_kms(aux->drm_dev, "%s: AUX interval %lu, out of range (max 4)\n",
 143                             aux->name, rd_interval);
 144
 145         if (rd_interval == 0 || dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
 146                 rd_interval = 100;
 147         else
 148                 rd_interval *= 4 * USEC_PER_MSEC;
 149
 150         usleep_range(rd_interval, rd_interval * 2);
 151 }
 152 EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
 153
 154 static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
 155                                                  unsigned long rd_interval)
 156 {
 157         if (rd_interval > 4)
 158                 drm_dbg_kms(aux->drm_dev, "%s: AUX interval %lu, out of range (max 4)\n",
 159                             aux->name, rd_interval);
 160
 161         if (rd_interval == 0)
 162                 rd_interval = 400;
 163         else
 164                 rd_interval *= 4 * USEC_PER_MSEC;
 165
 166         usleep_range(rd_interval, rd_interval * 2);
 167 }
 168
 169 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
 170                                         const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 171 {
 172         __drm_dp_link_train_channel_eq_delay(aux,
 173                                              dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
 174                                              DP_TRAINING_AUX_RD_MASK);
 175 }
 176 EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
 177
 178 void drm_dp_lttpr_link_train_clock_recovery_delay(void)
 179 {
 180         usleep_range(100, 200);
 181 }
 182 EXPORT_SYMBOL(drm_dp_lttpr_link_train_clock_recovery_delay);
 183
 184 static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r)
 185 {
 186         return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1];
 187 }
 188
 189 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
 190                                               const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE])
 191 {
 192         u8 interval = dp_lttpr_phy_cap(phy_cap,
 193                                        DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) &
 194                       DP_TRAINING_AUX_RD_MASK;
 195
 196         __drm_dp_link_train_channel_eq_delay(aux, interval);
 197 }
 198 EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay);
 199
 200 u8 drm_dp_link_rate_to_bw_code(int link_rate)
 201 {
 202         /* Spec says link_bw = link_rate / 0.27Gbps */
 203         return link_rate / 27000;
 204 }
 205 EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
 206
 207 int drm_dp_bw_code_to_link_rate(u8 link_bw)
 208 {
 209         /* Spec says link_rate = link_bw * 0.27Gbps */
 210         return link_bw * 27000;
 211 }
 212 EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
 213
 214 #define AUX_RETRY_INTERVAL 500 /* us */
 215
 216 static inline void
 217 drm_dp_dump_access(const struct drm_dp_aux *aux,
 218                    u8 request, uint offset, void *buffer, int ret)
 219 {
 220         const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-";
 221
 222         if (ret > 0)
 223                 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d) %*ph\n",
 224                            aux->name, offset, arrow, ret, min(ret, 20), buffer);
 225         else
 226                 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d)\n",
 227                            aux->name, offset, arrow, ret);
 228 }
 229
 230 /**
 231  * DOC: dp helpers
 232  *
 233  * The DisplayPort AUX channel is an abstraction to allow generic, driver-
 234  * independent access to AUX functionality. Drivers can take advantage of
 235  * this by filling in the fields of the drm_dp_aux structure.
 236  *
 237  * Transactions are described using a hardware-independent drm_dp_aux_msg
 238  * structure, which is passed into a driver's .transfer() implementation.
 239  * Both native and I2C-over-AUX transactions are supported.
 240  */
 241
 242 static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
 243                               unsigned int offset, void *buffer, size_t size)
 244 {
 245         struct drm_dp_aux_msg msg;
 246         unsigned int retry, native_reply;
 247         int err = 0, ret = 0;
 248
 249         memset(&msg, 0, sizeof(msg));
 250         msg.address = offset;
 251         msg.request = request;
 252         msg.buffer = buffer;
 253         msg.size = size;
 254
 255         mutex_lock(&aux->hw_mutex);
 256
 257         /*
 258          * The specification doesn't give any recommendation on how often to
 259          * retry native transactions. We used to retry 7 times like for
 260          * aux i2c transactions but real world devices this wasn't
 261          * sufficient, bump to 32 which makes Dell 4k monitors happier.
 262          */
 263         for (retry = 0; retry < 32; retry++) {
 264                 if (ret != 0 && ret != -ETIMEDOUT) {
 265                         usleep_range(AUX_RETRY_INTERVAL,
 266                                      AUX_RETRY_INTERVAL + 100);
 267                 }
 268
 269                 ret = aux->transfer(aux, &msg);
 270                 if (ret >= 0) {
 271                         native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK;
 272                         if (native_reply == DP_AUX_NATIVE_REPLY_ACK) {
 273                                 if (ret == size)
 274                                         goto unlock;
 275
 276                                 ret = -EPROTO;
 277                         } else
 278                                 ret = -EIO;
 279                 }
 280
 281                 /*
 282                  * We want the error we return to be the error we received on
 283                  * the first transaction, since we may get a different error the
 284                  * next time we retry
 285                  */
 286                 if (!err)
 287                         err = ret;
 288         }
 289
 290         drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up. First error: %d\n",
 291                     aux->name, err);
 292         ret = err;
 293
 294 unlock:
 295         mutex_unlock(&aux->hw_mutex);
 296         return ret;
 297 }
 298
 299 /**
 300  * drm_dp_dpcd_read() - read a series of bytes from the DPCD
 301  * @aux: DisplayPort AUX channel (SST or MST)
 302  * @offset: address of the (first) register to read
 303  * @buffer: buffer to store the register values
 304  * @size: number of bytes in @buffer
 305  *
 306  * Returns the number of bytes transferred on success, or a negative error
 307  * code on failure. -EIO is returned if the request was NAKed by the sink or
 308  * if the retry count was exceeded. If not all bytes were transferred, this
 309  * function returns -EPROTO. Errors from the underlying AUX channel transfer
 310  * function, with the exception of -EBUSY (which causes the transaction to
 311  * be retried), are propagated to the caller.
 312  */
 313 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
 314                          void *buffer, size_t size)
 315 {
 316         int ret;
 317
 318         /*
 319          * HP ZR24w corrupts the first DPCD access after entering power save
 320          * mode. Eg. on a read, the entire buffer will be filled with the same
 321          * byte. Do a throw away read to avoid corrupting anything we care
 322          * about. Afterwards things will work correctly until the monitor
 323          * gets woken up and subsequently re-enters power save mode.
 324          *
 325          * The user pressing any button on the monitor is enough to wake it
 326          * up, so there is no particularly good place to do the workaround.
 327          * We just have to do it before any DPCD access and hope that the
 328          * monitor doesn't power down exactly after the throw away read.
 329          */
 330         if (!aux->is_remote) {
 331                 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, DP_DPCD_REV,
 332                                          buffer, 1);
 333                 if (ret != 1)
 334                         goto out;
 335         }
 336
 337         if (aux->is_remote)
 338                 ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size);
 339         else
 340                 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset,
 341                                          buffer, size);
 342
 343 out:
 344         drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret);
 345         return ret;
 346 }
 347 EXPORT_SYMBOL(drm_dp_dpcd_read);
 348
 349 /**
 350  * drm_dp_dpcd_write() - write a series of bytes to the DPCD
 351  * @aux: DisplayPort AUX channel (SST or MST)
 352  * @offset: address of the (first) register to write
 353  * @buffer: buffer containing the values to write
 354  * @size: number of bytes in @buffer
 355  *
 356  * Returns the number of bytes transferred on success, or a negative error
 357  * code on failure. -EIO is returned if the request was NAKed by the sink or
 358  * if the retry count was exceeded. If not all bytes were transferred, this
 359  * function returns -EPROTO. Errors from the underlying AUX channel transfer
 360  * function, with the exception of -EBUSY (which causes the transaction to
 361  * be retried), are propagated to the caller.
 362  */
 363 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
 364                           void *buffer, size_t size)
 365 {
 366         int ret;
 367
 368         if (aux->is_remote)
 369                 ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size);
 370         else
 371                 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset,
 372                                          buffer, size);
 373
 374         drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret);
 375         return ret;
 376 }
 377 EXPORT_SYMBOL(drm_dp_dpcd_write);
 378
 379 /**
 380  * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
 381  * @aux: DisplayPort AUX channel
 382  * @status: buffer to store the link status in (must be at least 6 bytes)
 383  *
 384  * Returns the number of bytes transferred on success or a negative error
 385  * code on failure.
 386  */
 387 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
 388                                  u8 status[DP_LINK_STATUS_SIZE])
 389 {
 390         return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status,
 391                                 DP_LINK_STATUS_SIZE);
 392 }
 393 EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
 394
 395 /**
 396  * drm_dp_dpcd_read_phy_link_status - get the link status information for a DP PHY
 397  * @aux: DisplayPort AUX channel
 398  * @dp_phy: the DP PHY to get the link status for
 399  * @link_status: buffer to return the status in
 400  *
 401  * Fetch the AUX DPCD registers for the DPRX or an LTTPR PHY link status. The
 402  * layout of the returned @link_status matches the DPCD register layout of the
 403  * DPRX PHY link status.
 404  *
 405  * Returns 0 if the information was read successfully or a negative error code
 406  * on failure.
 407  */
 408 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
 409                                      enum drm_dp_phy dp_phy,
 410                                      u8 link_status[DP_LINK_STATUS_SIZE])
 411 {
 412         int ret;
 413
 414         if (dp_phy == DP_PHY_DPRX) {
 415                 ret = drm_dp_dpcd_read(aux,
 416                                        DP_LANE0_1_STATUS,
 417                                        link_status,
 418                                        DP_LINK_STATUS_SIZE);
 419
 420                 if (ret < 0)
 421                         return ret;
 422
 423                 WARN_ON(ret != DP_LINK_STATUS_SIZE);
 424
 425                 return 0;
 426         }
 427
 428         ret = drm_dp_dpcd_read(aux,
 429                                DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy),
 430                                link_status,
 431                                DP_LINK_STATUS_SIZE - 1);
 432
 433         if (ret < 0)
 434                 return ret;
 435
 436         WARN_ON(ret != DP_LINK_STATUS_SIZE - 1);
 437
 438         /* Convert the LTTPR to the sink PHY link status layout */
 439         memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1],
 440                 &link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS],
 441                 DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1);
 442         link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS] = 0;
 443
 444         return 0;
 445 }
 446 EXPORT_SYMBOL(drm_dp_dpcd_read_phy_link_status);
 447
 448 static bool is_edid_digital_input_dp(const struct edid *edid)
 449 {
 450         return edid && edid->revision >= 4 &&
 451                 edid->input & DRM_EDID_INPUT_DIGITAL &&
 452                 (edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_DP;
 453 }
 454
 455 /**
 456  * drm_dp_downstream_is_type() - is the downstream facing port of certain type?
 457  * @dpcd: DisplayPort configuration data
 458  * @port_cap: port capabilities
 459  * @type: port type to be checked. Can be:
 460  *        %DP_DS_PORT_TYPE_DP, %DP_DS_PORT_TYPE_VGA, %DP_DS_PORT_TYPE_DVI,
 461  *        %DP_DS_PORT_TYPE_HDMI, %DP_DS_PORT_TYPE_NON_EDID,
 462  *        %DP_DS_PORT_TYPE_DP_DUALMODE or %DP_DS_PORT_TYPE_WIRELESS.
 463  *
 464  * Caveat: Only works with DPCD 1.1+ port caps.
 465  *
 466  * Returns: whether the downstream facing port matches the type.
 467  */
 468 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 469                                const u8 port_cap[4], u8 type)
 470 {
 471         return drm_dp_is_branch(dpcd) &&
 472                 dpcd[DP_DPCD_REV] >= 0x11 &&
 473                 (port_cap[0] & DP_DS_PORT_TYPE_MASK) == type;
 474 }
 475 EXPORT_SYMBOL(drm_dp_downstream_is_type);
 476
 477 /**
 478  * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS?
 479  * @dpcd: DisplayPort configuration data
 480  * @port_cap: port capabilities
 481  * @edid: EDID
 482  *
 483  * Returns: whether the downstream facing port is TMDS (HDMI/DVI).
 484  */
 485 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 486                                const u8 port_cap[4],
 487                                const struct edid *edid)
 488 {
 489         if (dpcd[DP_DPCD_REV] < 0x11) {
 490                 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
 491                 case DP_DWN_STRM_PORT_TYPE_TMDS:
 492                         return true;
 493                 default:
 494                         return false;
 495                 }
 496         }
 497
 498         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
 499         case DP_DS_PORT_TYPE_DP_DUALMODE:
 500                 if (is_edid_digital_input_dp(edid))
 501                         return false;
 502                 fallthrough;
 503         case DP_DS_PORT_TYPE_DVI:
 504         case DP_DS_PORT_TYPE_HDMI:
 505                 return true;
 506         default:
 507                 return false;
 508         }
 509 }
 510 EXPORT_SYMBOL(drm_dp_downstream_is_tmds);
 511
 512 /**
 513  * drm_dp_send_real_edid_checksum() - send back real edid checksum value
 514  * @aux: DisplayPort AUX channel
 515  * @real_edid_checksum: real edid checksum for the last block
 516  *
 517  * Returns:
 518  * True on success
 519  */
 520 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
 521                                     u8 real_edid_checksum)
 522 {
 523         u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0;
 524
 525         if (drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
 526                              &auto_test_req, 1) < 1) {
 527                 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n",
 528                         aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
 529                 return false;
 530         }
 531         auto_test_req &= DP_AUTOMATED_TEST_REQUEST;
 532
 533         if (drm_dp_dpcd_read(aux, DP_TEST_REQUEST, &link_edid_read, 1) < 1) {
 534                 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n",
 535                         aux->name, DP_TEST_REQUEST);
 536                 return false;
 537         }
 538         link_edid_read &= DP_TEST_LINK_EDID_READ;
 539
 540         if (!auto_test_req || !link_edid_read) {
 541                 drm_dbg_kms(aux->drm_dev, "%s: Source DUT does not support TEST_EDID_READ\n",
 542                             aux->name);
 543                 return false;
 544         }
 545
 546         if (drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
 547                               &auto_test_req, 1) < 1) {
 548                 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
 549                         aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
 550                 return false;
 551         }
 552
 553         /* send back checksum for the last edid extension block data */
 554         if (drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM,
 555                               &real_edid_checksum, 1) < 1) {
 556                 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
 557                         aux->name, DP_TEST_EDID_CHECKSUM);
 558                 return false;
 559         }
 560
 561         test_resp |= DP_TEST_EDID_CHECKSUM_WRITE;
 562         if (drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, &test_resp, 1) < 1) {
 563                 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
 564                         aux->name, DP_TEST_RESPONSE);
 565                 return false;
 566         }
 567
 568         return true;
 569 }
 570 EXPORT_SYMBOL(drm_dp_send_real_edid_checksum);
 571
 572 static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
 573 {
 574         u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK;
 575
 576         if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4)
 577                 port_count = 4;
 578
 579         return port_count;
 580 }
 581
 582 static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux,
 583                                           u8 dpcd[DP_RECEIVER_CAP_SIZE])
 584 {
 585         u8 dpcd_ext[6];
 586         int ret;
 587
 588         /*
 589          * Prior to DP1.3 the bit represented by
 590          * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
 591          * If it is set DP_DPCD_REV at 0000h could be at a value less than
 592          * the true capability of the panel. The only way to check is to
 593          * then compare 0000h and 2200h.
 594          */
 595         if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
 596               DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
 597                 return 0;
 598
 599         ret = drm_dp_dpcd_read(aux, DP_DP13_DPCD_REV, &dpcd_ext,
 600                                sizeof(dpcd_ext));
 601         if (ret < 0)
 602                 return ret;
 603         if (ret != sizeof(dpcd_ext))
 604                 return -EIO;
 605
 606         if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
 607                 drm_dbg_kms(aux->drm_dev,
 608                             "%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n",
 609                             aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]);
 610                 return 0;
 611         }
 612
 613         if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext)))
 614                 return 0;
 615
 616         drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
 617
 618         memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext));
 619
 620         return 0;
 621 }
 622
 623 /**
 624  * drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if
 625  * available
 626  * @aux: DisplayPort AUX channel
 627  * @dpcd: Buffer to store the resulting DPCD in
 628  *
 629  * Attempts to read the base DPCD caps for @aux. Additionally, this function
 630  * checks for and reads the extended DPRX caps (%DP_DP13_DPCD_REV) if
 631  * present.
 632  *
 633  * Returns: %0 if the DPCD was read successfully, negative error code
 634  * otherwise.
 635  */
 636 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
 637                           u8 dpcd[DP_RECEIVER_CAP_SIZE])
 638 {
 639         int ret;
 640
 641         ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE);
 642         if (ret < 0)
 643                 return ret;
 644         if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0)
 645                 return -EIO;
 646
 647         ret = drm_dp_read_extended_dpcd_caps(aux, dpcd);
 648         if (ret < 0)
 649                 return ret;
 650
 651         drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
 652
 653         return ret;
 654 }
 655 EXPORT_SYMBOL(drm_dp_read_dpcd_caps);
 656
 657 /**
 658  * drm_dp_read_downstream_info() - read DPCD downstream port info if available
 659  * @aux: DisplayPort AUX channel
 660  * @dpcd: A cached copy of the port's DPCD
 661  * @downstream_ports: buffer to store the downstream port info in
 662  *
 663  * See also:
 664  * drm_dp_downstream_max_clock()
 665  * drm_dp_downstream_max_bpc()
 666  *
 667  * Returns: 0 if either the downstream port info was read successfully or
 668  * there was no downstream info to read, or a negative error code otherwise.
 669  */
 670 int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
 671                                 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 672                                 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS])
 673 {
 674         int ret;
 675         u8 len;
 676
 677         memset(downstream_ports, 0, DP_MAX_DOWNSTREAM_PORTS);
 678
 679         /* No downstream info to read */
 680         if (!drm_dp_is_branch(dpcd) || dpcd[DP_DPCD_REV] == DP_DPCD_REV_10)
 681                 return 0;
 682
 683         /* Some branches advertise having 0 downstream ports, despite also advertising they have a
 684          * downstream port present. The DP spec isn't clear on if this is allowed or not, but since
 685          * some branches do it we need to handle it regardless.
 686          */
 687         len = drm_dp_downstream_port_count(dpcd);
 688         if (!len)
 689                 return 0;
 690
 691         if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE)
 692                 len *= 4;
 693
 694         ret = drm_dp_dpcd_read(aux, DP_DOWNSTREAM_PORT_0, downstream_ports, len);
 695         if (ret < 0)
 696                 return ret;
 697         if (ret != len)
 698                 return -EIO;
 699
 700         drm_dbg_kms(aux->drm_dev, "%s: DPCD DFP: %*ph\n", aux->name, len, downstream_ports);
 701
 702         return 0;
 703 }
 704 EXPORT_SYMBOL(drm_dp_read_downstream_info);
 705
 706 /**
 707  * drm_dp_downstream_max_dotclock() - extract downstream facing port max dot clock
 708  * @dpcd: DisplayPort configuration data
 709  * @port_cap: port capabilities
 710  *
 711  * Returns: Downstream facing port max dot clock in kHz on success,
 712  * or 0 if max clock not defined
 713  */
 714 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 715                                    const u8 port_cap[4])
 716 {
 717         if (!drm_dp_is_branch(dpcd))
 718                 return 0;
 719
 720         if (dpcd[DP_DPCD_REV] < 0x11)
 721                 return 0;
 722
 723         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
 724         case DP_DS_PORT_TYPE_VGA:
 725                 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
 726                         return 0;
 727                 return port_cap[1] * 8000;
 728         default:
 729                 return 0;
 730         }
 731 }
 732 EXPORT_SYMBOL(drm_dp_downstream_max_dotclock);
 733
 734 /**
 735  * drm_dp_downstream_max_tmds_clock() - extract downstream facing port max TMDS clock
 736  * @dpcd: DisplayPort configuration data
 737  * @port_cap: port capabilities
 738  * @edid: EDID
 739  *
 740  * Returns: HDMI/DVI downstream facing port max TMDS clock in kHz on success,
 741  * or 0 if max TMDS clock not defined
 742  */
 743 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 744                                      const u8 port_cap[4],
 745                                      const struct edid *edid)
 746 {
 747         if (!drm_dp_is_branch(dpcd))
 748                 return 0;
 749
 750         if (dpcd[DP_DPCD_REV] < 0x11) {
 751                 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
 752                 case DP_DWN_STRM_PORT_TYPE_TMDS:
 753                         return 165000;
 754                 default:
 755                         return 0;
 756                 }
 757         }
 758
 759         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
 760         case DP_DS_PORT_TYPE_DP_DUALMODE:
 761                 if (is_edid_digital_input_dp(edid))
 762                         return 0;
 763                 /*
 764                  * It's left up to the driver to check the
 765                  * DP dual mode adapter's max TMDS clock.
 766                  *
 767                  * Unfortunatley it looks like branch devices
 768                  * may not fordward that the DP dual mode i2c
 769                  * access so we just usually get i2c nak :(
 770                  */
 771                 fallthrough;
 772         case DP_DS_PORT_TYPE_HDMI:
 773                  /*
 774                   * We should perhaps assume 165 MHz when detailed cap
 775                   * info is not available. But looks like many typical
 776                   * branch devices fall into that category and so we'd
 777                   * probably end up with users complaining that they can't
 778                   * get high resolution modes with their favorite dongle.
 779                   *
 780                   * So let's limit to 300 MHz instead since DPCD 1.4
 781                   * HDMI 2.0 DFPs are required to have the detailed cap
 782                   * info. So it's more likely we're dealing with a HDMI 1.4
 783                   * compatible* device here.
 784                   */
 785                 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
 786                         return 300000;
 787                 return port_cap[1] * 2500;
 788         case DP_DS_PORT_TYPE_DVI:
 789                 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
 790                         return 165000;
 791                 /* FIXME what to do about DVI dual link? */
 792                 return port_cap[1] * 2500;
 793         default:
 794                 return 0;
 795         }
 796 }
 797 EXPORT_SYMBOL(drm_dp_downstream_max_tmds_clock);
 798
 799 /**
 800  * drm_dp_downstream_min_tmds_clock() - extract downstream facing port min TMDS clock
 801  * @dpcd: DisplayPort configuration data
 802  * @port_cap: port capabilities
 803  * @edid: EDID
 804  *
 805  * Returns: HDMI/DVI downstream facing port min TMDS clock in kHz on success,
 806  * or 0 if max TMDS clock not defined
 807  */
 808 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 809                                      const u8 port_cap[4],
 810                                      const struct edid *edid)
 811 {
 812         if (!drm_dp_is_branch(dpcd))
 813                 return 0;
 814
 815         if (dpcd[DP_DPCD_REV] < 0x11) {
 816                 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
 817                 case DP_DWN_STRM_PORT_TYPE_TMDS:
 818                         return 25000;
 819                 default:
 820                         return 0;
 821                 }
 822         }
 823
 824         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
 825         case DP_DS_PORT_TYPE_DP_DUALMODE:
 826                 if (is_edid_digital_input_dp(edid))
 827                         return 0;
 828                 fallthrough;
 829         case DP_DS_PORT_TYPE_DVI:
 830         case DP_DS_PORT_TYPE_HDMI:
 831                 /*
 832                  * Unclear whether the protocol converter could
 833                  * utilize pixel replication. Assume it won't.
 834                  */
 835                 return 25000;
 836         default:
 837                 return 0;
 838         }
 839 }
 840 EXPORT_SYMBOL(drm_dp_downstream_min_tmds_clock);
 841
 842 /**
 843  * drm_dp_downstream_max_bpc() - extract downstream facing port max
 844  *                               bits per component
 845  * @dpcd: DisplayPort configuration data
 846  * @port_cap: downstream facing port capabilities
 847  * @edid: EDID
 848  *
 849  * Returns: Max bpc on success or 0 if max bpc not defined
 850  */
 851 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 852                               const u8 port_cap[4],
 853                               const struct edid *edid)
 854 {
 855         if (!drm_dp_is_branch(dpcd))
 856                 return 0;
 857
 858         if (dpcd[DP_DPCD_REV] < 0x11) {
 859                 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
 860                 case DP_DWN_STRM_PORT_TYPE_DP:
 861                         return 0;
 862                 default:
 863                         return 8;
 864                 }
 865         }
 866
 867         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
 868         case DP_DS_PORT_TYPE_DP:
 869                 return 0;
 870         case DP_DS_PORT_TYPE_DP_DUALMODE:
 871                 if (is_edid_digital_input_dp(edid))
 872                         return 0;
 873                 fallthrough;
 874         case DP_DS_PORT_TYPE_HDMI:
 875         case DP_DS_PORT_TYPE_DVI:
 876         case DP_DS_PORT_TYPE_VGA:
 877                 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
 878                         return 8;
 879
 880                 switch (port_cap[2] & DP_DS_MAX_BPC_MASK) {
 881                 case DP_DS_8BPC:
 882                         return 8;
 883                 case DP_DS_10BPC:
 884                         return 10;
 885                 case DP_DS_12BPC:
 886                         return 12;
 887                 case DP_DS_16BPC:
 888                         return 16;
 889                 default:
 890                         return 8;
 891                 }
 892                 break;
 893         default:
 894                 return 8;
 895         }
 896 }
 897 EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
 898
 899 /**
 900  * drm_dp_downstream_420_passthrough() - determine downstream facing port
 901  *                                       YCbCr 4:2:0 pass-through capability
 902  * @dpcd: DisplayPort configuration data
 903  * @port_cap: downstream facing port capabilities
 904  *
 905  * Returns: whether the downstream facing port can pass through YCbCr 4:2:0
 906  */
 907 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 908                                        const u8 port_cap[4])
 909 {
 910         if (!drm_dp_is_branch(dpcd))
 911                 return false;
 912
 913         if (dpcd[DP_DPCD_REV] < 0x13)
 914                 return false;
 915
 916         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
 917         case DP_DS_PORT_TYPE_DP:
 918                 return true;
 919         case DP_DS_PORT_TYPE_HDMI:
 920                 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
 921                         return false;
 922
 923                 return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH;
 924         default:
 925                 return false;
 926         }
 927 }
 928 EXPORT_SYMBOL(drm_dp_downstream_420_passthrough);
 929
 930 /**
 931  * drm_dp_downstream_444_to_420_conversion() - determine downstream facing port
 932  *                                             YCbCr 4:4:4->4:2:0 conversion capability
 933  * @dpcd: DisplayPort configuration data
 934  * @port_cap: downstream facing port capabilities
 935  *
 936  * Returns: whether the downstream facing port can convert YCbCr 4:4:4 to 4:2:0
 937  */
 938 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 939                                              const u8 port_cap[4])
 940 {
 941         if (!drm_dp_is_branch(dpcd))
 942                 return false;
 943
 944         if (dpcd[DP_DPCD_REV] < 0x13)
 945                 return false;
 946
 947         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
 948         case DP_DS_PORT_TYPE_HDMI:
 949                 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
 950                         return false;
 951
 952                 return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV;
 953         default:
 954                 return false;
 955         }
 956 }
 957 EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion);
 958
 959 /**
 960  * drm_dp_downstream_rgb_to_ycbcr_conversion() - determine downstream facing port
 961  *                                               RGB->YCbCr conversion capability
 962  * @dpcd: DisplayPort configuration data
 963  * @port_cap: downstream facing port capabilities
 964  * @color_spc: Colorspace for which conversion cap is sought
 965  *
 966  * Returns: whether the downstream facing port can convert RGB->YCbCr for a given
 967  * colorspace.
 968  */
 969 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
 970                                                const u8 port_cap[4],
 971                                                u8 color_spc)
 972 {
 973         if (!drm_dp_is_branch(dpcd))
 974                 return false;
 975
 976         if (dpcd[DP_DPCD_REV] < 0x13)
 977                 return false;
 978
 979         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
 980         case DP_DS_PORT_TYPE_HDMI:
 981                 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
 982                         return false;
 983
 984                 return port_cap[3] & color_spc;
 985         default:
 986                 return false;
 987         }
 988 }
 989 EXPORT_SYMBOL(drm_dp_downstream_rgb_to_ycbcr_conversion);
 990
 991 /**
 992  * drm_dp_downstream_mode() - return a mode for downstream facing port
 993  * @dev: DRM device
 994  * @dpcd: DisplayPort configuration data
 995  * @port_cap: port capabilities
 996  *
 997  * Provides a suitable mode for downstream facing ports without EDID.
 998  *
 999  * Returns: A new drm_display_mode on success or NULL on failure
1000  */
1001 struct drm_display_mode *
1002 drm_dp_downstream_mode(struct drm_device *dev,
1003                        const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1004                        const u8 port_cap[4])
1005
1006 {
1007         u8 vic;
1008
1009         if (!drm_dp_is_branch(dpcd))
1010                 return NULL;
1011
1012         if (dpcd[DP_DPCD_REV] < 0x11)
1013                 return NULL;
1014
1015         switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1016         case DP_DS_PORT_TYPE_NON_EDID:
1017                 switch (port_cap[0] & DP_DS_NON_EDID_MASK) {
1018                 case DP_DS_NON_EDID_720x480i_60:
1019                         vic = 6;
1020                         break;
1021                 case DP_DS_NON_EDID_720x480i_50:
1022                         vic = 21;
1023                         break;
1024                 case DP_DS_NON_EDID_1920x1080i_60:
1025                         vic = 5;
1026                         break;
1027                 case DP_DS_NON_EDID_1920x1080i_50:
1028                         vic = 20;
1029                         break;
1030                 case DP_DS_NON_EDID_1280x720_60:
1031                         vic = 4;
1032                         break;
1033                 case DP_DS_NON_EDID_1280x720_50:
1034                         vic = 19;
1035                         break;
1036                 default:
1037                         return NULL;
1038                 }
1039                 return drm_display_mode_from_cea_vic(dev, vic);
1040         default:
1041                 return NULL;
1042         }
1043 }
1044 EXPORT_SYMBOL(drm_dp_downstream_mode);
1045
1046 /**
1047  * drm_dp_downstream_id() - identify branch device
1048  * @aux: DisplayPort AUX channel
1049  * @id: DisplayPort branch device id
1050  *
1051  * Returns branch device id on success or NULL on failure
1052  */
1053 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6])
1054 {
1055         return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6);
1056 }
1057 EXPORT_SYMBOL(drm_dp_downstream_id);
1058
1059 /**
1060  * drm_dp_downstream_debug() - debug DP branch devices
1061  * @m: pointer for debugfs file
1062  * @dpcd: DisplayPort configuration data
1063  * @port_cap: port capabilities
1064  * @edid: EDID
1065  * @aux: DisplayPort AUX channel
1066  *
1067  */
1068 void drm_dp_downstream_debug(struct seq_file *m,
1069                              const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1070                              const u8 port_cap[4],
1071                              const struct edid *edid,
1072                              struct drm_dp_aux *aux)
1073 {
1074         bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1075                                  DP_DETAILED_CAP_INFO_AVAILABLE;
1076         int clk;
1077         int bpc;
1078         char id[7];
1079         int len;
1080         uint8_t rev[2];
1081         int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
1082         bool branch_device = drm_dp_is_branch(dpcd);
1083
1084         seq_printf(m, "\tDP branch device present: %s\n",
1085                    branch_device ? "yes" : "no");
1086
1087         if (!branch_device)
1088                 return;
1089
1090         switch (type) {
1091         case DP_DS_PORT_TYPE_DP:
1092                 seq_puts(m, "\t\tType: DisplayPort\n");
1093                 break;
1094         case DP_DS_PORT_TYPE_VGA:
1095                 seq_puts(m, "\t\tType: VGA\n");
1096                 break;
1097         case DP_DS_PORT_TYPE_DVI:
1098                 seq_puts(m, "\t\tType: DVI\n");
1099                 break;
1100         case DP_DS_PORT_TYPE_HDMI:
1101                 seq_puts(m, "\t\tType: HDMI\n");
1102                 break;
1103         case DP_DS_PORT_TYPE_NON_EDID:
1104                 seq_puts(m, "\t\tType: others without EDID support\n");
1105                 break;
1106         case DP_DS_PORT_TYPE_DP_DUALMODE:
1107                 seq_puts(m, "\t\tType: DP++\n");
1108                 break;
1109         case DP_DS_PORT_TYPE_WIRELESS:
1110                 seq_puts(m, "\t\tType: Wireless\n");
1111                 break;
1112         default:
1113                 seq_puts(m, "\t\tType: N/A\n");
1114         }
1115
1116         memset(id, 0, sizeof(id));
1117         drm_dp_downstream_id(aux, id);
1118         seq_printf(m, "\t\tID: %s\n", id);
1119
1120         len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1);
1121         if (len > 0)
1122                 seq_printf(m, "\t\tHW: %d.%d\n",
1123                            (rev[0] & 0xf0) >> 4, rev[0] & 0xf);
1124
1125         len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2);
1126         if (len > 0)
1127                 seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);
1128
1129         if (detailed_cap_info) {
1130                 clk = drm_dp_downstream_max_dotclock(dpcd, port_cap);
1131                 if (clk > 0)
1132                         seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);
1133
1134                 clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, edid);
1135                 if (clk > 0)
1136                         seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk);
1137
1138                 clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, edid);
1139                 if (clk > 0)
1140                         seq_printf(m, "\t\tMin TMDS clock: %d kHz\n", clk);
1141
1142                 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid);
1143
1144                 if (bpc > 0)
1145                         seq_printf(m, "\t\tMax bpc: %d\n", bpc);
1146         }
1147 }
1148 EXPORT_SYMBOL(drm_dp_downstream_debug);
1149
1150 /**
1151  * drm_dp_subconnector_type() - get DP branch device type
1152  * @dpcd: DisplayPort configuration data
1153  * @port_cap: port capabilities
1154  */
1155 enum drm_mode_subconnector
1156 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1157                          const u8 port_cap[4])
1158 {
1159         int type;
1160         if (!drm_dp_is_branch(dpcd))
1161                 return DRM_MODE_SUBCONNECTOR_Native;
1162         /* DP 1.0 approach */
1163         if (dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) {
1164                 type = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1165                        DP_DWN_STRM_PORT_TYPE_MASK;
1166
1167                 switch (type) {
1168                 case DP_DWN_STRM_PORT_TYPE_TMDS:
1169                         /* Can be HDMI or DVI-D, DVI-D is a safer option */
1170                         return DRM_MODE_SUBCONNECTOR_DVID;
1171                 case DP_DWN_STRM_PORT_TYPE_ANALOG:
1172                         /* Can be VGA or DVI-A, VGA is more popular */
1173                         return DRM_MODE_SUBCONNECTOR_VGA;
1174                 case DP_DWN_STRM_PORT_TYPE_DP:
1175                         return DRM_MODE_SUBCONNECTOR_DisplayPort;
1176                 case DP_DWN_STRM_PORT_TYPE_OTHER:
1177                 default:
1178                         return DRM_MODE_SUBCONNECTOR_Unknown;
1179                 }
1180         }
1181         type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
1182
1183         switch (type) {
1184         case DP_DS_PORT_TYPE_DP:
1185         case DP_DS_PORT_TYPE_DP_DUALMODE:
1186                 return DRM_MODE_SUBCONNECTOR_DisplayPort;
1187         case DP_DS_PORT_TYPE_VGA:
1188                 return DRM_MODE_SUBCONNECTOR_VGA;
1189         case DP_DS_PORT_TYPE_DVI:
1190                 return DRM_MODE_SUBCONNECTOR_DVID;
1191         case DP_DS_PORT_TYPE_HDMI:
1192                 return DRM_MODE_SUBCONNECTOR_HDMIA;
1193         case DP_DS_PORT_TYPE_WIRELESS:
1194                 return DRM_MODE_SUBCONNECTOR_Wireless;
1195         case DP_DS_PORT_TYPE_NON_EDID:
1196         default:
1197                 return DRM_MODE_SUBCONNECTOR_Unknown;
1198         }
1199 }
1200 EXPORT_SYMBOL(drm_dp_subconnector_type);
1201
1202 /**
1203  * drm_dp_set_subconnector_property - set subconnector for DP connector
1204  * @connector: connector to set property on
1205  * @status: connector status
1206  * @dpcd: DisplayPort configuration data
1207  * @port_cap: port capabilities
1208  *
1209  * Called by a driver on every detect event.
1210  */
1211 void drm_dp_set_subconnector_property(struct drm_connector *connector,
1212                                       enum drm_connector_status status,
1213                                       const u8 *dpcd,
1214                                       const u8 port_cap[4])
1215 {
1216         enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
1217
1218         if (status == connector_status_connected)
1219                 subconnector = drm_dp_subconnector_type(dpcd, port_cap);
1220         drm_object_property_set_value(&connector->base,
1221                         connector->dev->mode_config.dp_subconnector_property,
1222                         subconnector);
1223 }
1224 EXPORT_SYMBOL(drm_dp_set_subconnector_property);
1225
1226 /**
1227  * drm_dp_read_sink_count_cap() - Check whether a given connector has a valid sink
1228  * count
1229  * @connector: The DRM connector to check
1230  * @dpcd: A cached copy of the connector's DPCD RX capabilities
1231  * @desc: A cached copy of the connector's DP descriptor
1232  *
1233  * See also: drm_dp_read_sink_count()
1234  *
1235  * Returns: %True if the (e)DP connector has a valid sink count that should
1236  * be probed, %false otherwise.
1237  */
1238 bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
1239                                 const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1240                                 const struct drm_dp_desc *desc)
1241 {
1242         /* Some eDP panels don't set a valid value for the sink count */
1243         return connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
1244                 dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 &&
1245                 dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
1246                 !drm_dp_has_quirk(desc, DP_DPCD_QUIRK_NO_SINK_COUNT);
1247 }
1248 EXPORT_SYMBOL(drm_dp_read_sink_count_cap);
1249
1250 /**
1251  * drm_dp_read_sink_count() - Retrieve the sink count for a given sink
1252  * @aux: The DP AUX channel to use
1253  *
1254  * See also: drm_dp_read_sink_count_cap()
1255  *
1256  * Returns: The current sink count reported by @aux, or a negative error code
1257  * otherwise.
1258  */
1259 int drm_dp_read_sink_count(struct drm_dp_aux *aux)
1260 {
1261         u8 count;
1262         int ret;
1263
1264         ret = drm_dp_dpcd_readb(aux, DP_SINK_COUNT, &count);
1265         if (ret < 0)
1266                 return ret;
1267         if (ret != 1)
1268                 return -EIO;
1269
1270         return DP_GET_SINK_COUNT(count);
1271 }
1272 EXPORT_SYMBOL(drm_dp_read_sink_count);
1273
1274 /*
1275  * I2C-over-AUX implementation
1276  */
1277
1278 static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter)
1279 {
1280         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
1281                I2C_FUNC_SMBUS_READ_BLOCK_DATA |
1282                I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
1283                I2C_FUNC_10BIT_ADDR;
1284 }
1285
1286 static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg)
1287 {
1288         /*
1289          * In case of i2c defer or short i2c ack reply to a write,
1290          * we need to switch to WRITE_STATUS_UPDATE to drain the
1291          * rest of the message
1292          */
1293         if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) {
1294                 msg->request &= DP_AUX_I2C_MOT;
1295                 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE;
1296         }
1297 }
1298
1299 #define AUX_PRECHARGE_LEN 10 /* 10 to 16 */
1300 #define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */
1301 #define AUX_STOP_LEN 4
1302 #define AUX_CMD_LEN 4
1303 #define AUX_ADDRESS_LEN 20
1304 #define AUX_REPLY_PAD_LEN 4
1305 #define AUX_LENGTH_LEN 8
1306
1307 /*
1308  * Calculate the duration of the AUX request/reply in usec. Gives the
1309  * "best" case estimate, ie. successful while as short as possible.
1310  */
1311 static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg)
1312 {
1313         int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
1314                 AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN;
1315
1316         if ((msg->request & DP_AUX_I2C_READ) == 0)
1317                 len += msg->size * 8;
1318
1319         return len;
1320 }
1321
1322 static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg)
1323 {
1324         int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
1325                 AUX_CMD_LEN + AUX_REPLY_PAD_LEN;
1326
1327         /*
1328          * For read we expect what was asked. For writes there will
1329          * be 0 or 1 data bytes. Assume 0 for the "best" case.
1330          */
1331         if (msg->request & DP_AUX_I2C_READ)
1332                 len += msg->size * 8;
1333
1334         return len;
1335 }
1336
1337 #define I2C_START_LEN 1
1338 #define I2C_STOP_LEN 1
1339 #define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */
1340 #define I2C_DATA_LEN 9 /* DATA + ACK/NACK */
1341
1342 /*
1343  * Calculate the length of the i2c transfer in usec, assuming
1344  * the i2c bus speed is as specified. Gives the the "worst"
1345  * case estimate, ie. successful while as long as possible.
1346  * Doesn't account the the "MOT" bit, and instead assumes each
1347  * message includes a START, ADDRESS and STOP. Neither does it
1348  * account for additional random variables such as clock stretching.
1349  */
1350 static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg,
1351                                    int i2c_speed_khz)
1352 {
1353         /* AUX bitrate is 1MHz, i2c bitrate as specified */
1354         return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN +
1355                              msg->size * I2C_DATA_LEN +
1356                              I2C_STOP_LEN) * 1000, i2c_speed_khz);
1357 }
1358
1359 /*
1360  * Deterine how many retries should be attempted to successfully transfer
1361  * the specified message, based on the estimated durations of the
1362  * i2c and AUX transfers.
1363  */
1364 static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg,
1365                               int i2c_speed_khz)
1366 {
1367         int aux_time_us = drm_dp_aux_req_duration(msg) +
1368                 drm_dp_aux_reply_duration(msg);
1369         int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz);
1370
1371         return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL);
1372 }
1373
1374 /*
1375  * FIXME currently assumes 10 kHz as some real world devices seem
1376  * to require it. We should query/set the speed via DPCD if supported.
1377  */
1378 static int dp_aux_i2c_speed_khz __read_mostly = 10;
1379 module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644);
1380 MODULE_PARM_DESC(dp_aux_i2c_speed_khz,
1381                  "Assumed speed of the i2c bus in kHz, (1-400, default 10)");
1382
1383 /*
1384  * Transfer a single I2C-over-AUX message and handle various error conditions,
1385  * retrying the transaction as appropriate.  It is assumed that the
1386  * &drm_dp_aux.transfer function does not modify anything in the msg other than the
1387  * reply field.
1388  *
1389  * Returns bytes transferred on success, or a negative error code on failure.
1390  */
1391 static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1392 {
1393         unsigned int retry, defer_i2c;
1394         int ret;
1395         /*
1396          * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device
1397          * is required to retry at least seven times upon receiving AUX_DEFER
1398          * before giving up the AUX transaction.
1399          *
1400          * We also try to account for the i2c bus speed.
1401          */
1402         int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz));
1403
1404         for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) {
1405                 ret = aux->transfer(aux, msg);
1406                 if (ret < 0) {
1407                         if (ret == -EBUSY)
1408                                 continue;
1409
1410                         /*
1411                          * While timeouts can be errors, they're usually normal
1412                          * behavior (for instance, when a driver tries to
1413                          * communicate with a non-existant DisplayPort device).
1414                          * Avoid spamming the kernel log with timeout errors.
1415                          */
1416                         if (ret == -ETIMEDOUT)
1417                                 drm_dbg_kms_ratelimited(aux->drm_dev, "%s: transaction timed out\n",
1418                                                         aux->name);
1419                         else
1420                                 drm_dbg_kms(aux->drm_dev, "%s: transaction failed: %d\n",
1421                                             aux->name, ret);
1422                         return ret;
1423                 }
1424
1425
1426                 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) {
1427                 case DP_AUX_NATIVE_REPLY_ACK:
1428                         /*
1429                          * For I2C-over-AUX transactions this isn't enough, we
1430                          * need to check for the I2C ACK reply.
1431                          */
1432                         break;
1433
1434                 case DP_AUX_NATIVE_REPLY_NACK:
1435                         drm_dbg_kms(aux->drm_dev, "%s: native nack (result=%d, size=%zu)\n",
1436                                     aux->name, ret, msg->size);
1437                         return -EREMOTEIO;
1438
1439                 case DP_AUX_NATIVE_REPLY_DEFER:
1440                         drm_dbg_kms(aux->drm_dev, "%s: native defer\n", aux->name);
1441                         /*
1442                          * We could check for I2C bit rate capabilities and if
1443                          * available adjust this interval. We could also be
1444                          * more careful with DP-to-legacy adapters where a
1445                          * long legacy cable may force very low I2C bit rates.
1446                          *
1447                          * For now just defer for long enough to hopefully be
1448                          * safe for all use-cases.
1449                          */
1450                         usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
1451                         continue;
1452
1453                 default:
1454                         drm_err(aux->drm_dev, "%s: invalid native reply %#04x\n",
1455                                 aux->name, msg->reply);
1456                         return -EREMOTEIO;
1457                 }
1458
1459                 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) {
1460                 case DP_AUX_I2C_REPLY_ACK:
1461                         /*
1462                          * Both native ACK and I2C ACK replies received. We
1463                          * can assume the transfer was successful.
1464                          */
1465                         if (ret != msg->size)
1466                                 drm_dp_i2c_msg_write_status_update(msg);
1467                         return ret;
1468
1469                 case DP_AUX_I2C_REPLY_NACK:
1470                         drm_dbg_kms(aux->drm_dev, "%s: I2C nack (result=%d, size=%zu)\n",
1471                                     aux->name, ret, msg->size);
1472                         aux->i2c_nack_count++;
1473                         return -EREMOTEIO;
1474
1475                 case DP_AUX_I2C_REPLY_DEFER:
1476                         drm_dbg_kms(aux->drm_dev, "%s: I2C defer\n", aux->name);
1477                         /* DP Compliance Test 4.2.2.5 Requirement:
1478                          * Must have at least 7 retries for I2C defers on the
1479                          * transaction to pass this test
1480                          */
1481                         aux->i2c_defer_count++;
1482                         if (defer_i2c < 7)
1483                                 defer_i2c++;
1484                         usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
1485                         drm_dp_i2c_msg_write_status_update(msg);
1486
1487                         continue;
1488
1489                 default:
1490                         drm_err(aux->drm_dev, "%s: invalid I2C reply %#04x\n",
1491                                 aux->name, msg->reply);
1492                         return -EREMOTEIO;
1493                 }
1494         }
1495
1496         drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up\n", aux->name);
1497         return -EREMOTEIO;
1498 }
1499
1500 static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg,
1501                                        const struct i2c_msg *i2c_msg)
1502 {
1503         msg->request = (i2c_msg->flags & I2C_M_RD) ?
1504                 DP_AUX_I2C_READ : DP_AUX_I2C_WRITE;
1505         if (!(i2c_msg->flags & I2C_M_STOP))
1506                 msg->request |= DP_AUX_I2C_MOT;
1507 }
1508
1509 /*
1510  * Keep retrying drm_dp_i2c_do_msg until all data has been transferred.
1511  *
1512  * Returns an error code on failure, or a recommended transfer size on success.
1513  */
1514 static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg)
1515 {
1516         int err, ret = orig_msg->size;
1517         struct drm_dp_aux_msg msg = *orig_msg;
1518
1519         while (msg.size > 0) {
1520                 err = drm_dp_i2c_do_msg(aux, &msg);
1521                 if (err <= 0)
1522                         return err == 0 ? -EPROTO : err;
1523
1524                 if (err < msg.size && err < ret) {
1525                         drm_dbg_kms(aux->drm_dev,
1526                                     "%s: Partial I2C reply: requested %zu bytes got %d bytes\n",
1527                                     aux->name, msg.size, err);
1528                         ret = err;
1529                 }
1530
1531                 msg.size -= err;
1532                 msg.buffer += err;
1533         }
1534
1535         return ret;
1536 }
1537
1538 /*
1539  * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX
1540  * packets to be as large as possible. If not, the I2C transactions never
1541  * succeed. Hence the default is maximum.
1542  */
1543 static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES;
1544 module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644);
1545 MODULE_PARM_DESC(dp_aux_i2c_transfer_size,
1546                  "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");
1547
1548 static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
1549                            int num)
1550 {
1551         struct drm_dp_aux *aux = adapter->algo_data;
1552         unsigned int i, j;
1553         unsigned transfer_size;
1554         struct drm_dp_aux_msg msg;
1555         int err = 0;
1556
1557         dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES);
1558
1559         memset(&msg, 0, sizeof(msg));
1560
1561         for (i = 0; i < num; i++) {
1562                 msg.address = msgs[i].addr;
1563                 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1564                 /* Send a bare address packet to start the transaction.
1565                  * Zero sized messages specify an address only (bare
1566                  * address) transaction.
1567                  */
1568                 msg.buffer = NULL;
1569                 msg.size = 0;
1570                 err = drm_dp_i2c_do_msg(aux, &msg);
1571
1572                 /*
1573                  * Reset msg.request in case in case it got
1574                  * changed into a WRITE_STATUS_UPDATE.
1575                  */
1576                 drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1577
1578                 if (err < 0)
1579                         break;
1580                 /* We want each transaction to be as large as possible, but
1581                  * we'll go to smaller sizes if the hardware gives us a
1582                  * short reply.
1583                  */
1584                 transfer_size = dp_aux_i2c_transfer_size;
1585                 for (j = 0; j < msgs[i].len; j += msg.size) {
1586                         msg.buffer = msgs[i].buf + j;
1587                         msg.size = min(transfer_size, msgs[i].len - j);
1588
1589                         err = drm_dp_i2c_drain_msg(aux, &msg);
1590
1591                         /*
1592                          * Reset msg.request in case in case it got
1593                          * changed into a WRITE_STATUS_UPDATE.
1594                          */
1595                         drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1596
1597                         if (err < 0)
1598                                 break;
1599                         transfer_size = err;
1600                 }
1601                 if (err < 0)
1602                         break;
1603         }
1604         if (err >= 0)
1605                 err = num;
1606         /* Send a bare address packet to close out the transaction.
1607          * Zero sized messages specify an address only (bare
1608          * address) transaction.
1609          */
1610         msg.request &= ~DP_AUX_I2C_MOT;
1611         msg.buffer = NULL;
1612         msg.size = 0;
1613         (void)drm_dp_i2c_do_msg(aux, &msg);
1614
1615         return err;
1616 }
1617
1618 static const struct i2c_algorithm drm_dp_i2c_algo = {
1619         .functionality = drm_dp_i2c_functionality,
1620         .master_xfer = drm_dp_i2c_xfer,
1621 };
1622
1623 static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c)
1624 {
1625         return container_of(i2c, struct drm_dp_aux, ddc);
1626 }
1627
1628 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
1629 {
1630         mutex_lock(&i2c_to_aux(i2c)->hw_mutex);
1631 }
1632
1633 static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
1634 {
1635         return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex);
1636 }
1637
1638 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
1639 {
1640         mutex_unlock(&i2c_to_aux(i2c)->hw_mutex);
1641 }
1642
1643 static const struct i2c_lock_operations drm_dp_i2c_lock_ops = {
1644         .lock_bus = lock_bus,
1645         .trylock_bus = trylock_bus,
1646         .unlock_bus = unlock_bus,
1647 };
1648
1649 static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc)
1650 {
1651         u8 buf, count;
1652         int ret;
1653
1654         ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1655         if (ret < 0)
1656                 return ret;
1657
1658         WARN_ON(!(buf & DP_TEST_SINK_START));
1659
1660         ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf);
1661         if (ret < 0)
1662                 return ret;
1663
1664         count = buf & DP_TEST_COUNT_MASK;
1665         if (count == aux->crc_count)
1666                 return -EAGAIN; /* No CRC yet */
1667
1668         aux->crc_count = count;
1669
1670         /*
1671          * At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes
1672          * per component (RGB or CrYCb).
1673          */
1674         ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6);
1675         if (ret < 0)
1676                 return ret;
1677
1678         return 0;
1679 }
1680
1681 static void drm_dp_aux_crc_work(struct work_struct *work)
1682 {
1683         struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux,
1684                                               crc_work);
1685         struct drm_crtc *crtc;
1686         u8 crc_bytes[6];
1687         uint32_t crcs[3];
1688         int ret;
1689
1690         if (WARN_ON(!aux->crtc))
1691                 return;
1692
1693         crtc = aux->crtc;
1694         while (crtc->crc.opened) {
1695                 drm_crtc_wait_one_vblank(crtc);
1696                 if (!crtc->crc.opened)
1697                         break;
1698
1699                 ret = drm_dp_aux_get_crc(aux, crc_bytes);
1700                 if (ret == -EAGAIN) {
1701                         usleep_range(1000, 2000);
1702                         ret = drm_dp_aux_get_crc(aux, crc_bytes);
1703                 }
1704
1705                 if (ret == -EAGAIN) {
1706                         drm_dbg_kms(aux->drm_dev, "%s: Get CRC failed after retrying: %d\n",
1707                                     aux->name, ret);
1708                         continue;
1709                 } else if (ret) {
1710                         drm_dbg_kms(aux->drm_dev, "%s: Failed to get a CRC: %d\n", aux->name, ret);
1711                         continue;
1712                 }
1713
1714                 crcs[0] = crc_bytes[0] | crc_bytes[1] << 8;
1715                 crcs[1] = crc_bytes[2] | crc_bytes[3] << 8;
1716                 crcs[2] = crc_bytes[4] | crc_bytes[5] << 8;
1717                 drm_crtc_add_crc_entry(crtc, false, 0, crcs);
1718         }
1719 }
1720
1721 /**
1722  * drm_dp_remote_aux_init() - minimally initialise a remote aux channel
1723  * @aux: DisplayPort AUX channel
1724  *
1725  * Used for remote aux channel in general. Merely initialize the crc work
1726  * struct.
1727  */
1728 void drm_dp_remote_aux_init(struct drm_dp_aux *aux)
1729 {
1730         INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
1731 }
1732 EXPORT_SYMBOL(drm_dp_remote_aux_init);
1733
1734 /**
1735  * drm_dp_aux_init() - minimally initialise an aux channel
1736  * @aux: DisplayPort AUX channel
1737  *
1738  * If you need to use the drm_dp_aux's i2c adapter prior to registering it with
1739  * the outside world, call drm_dp_aux_init() first. For drivers which are
1740  * grandparents to their AUX adapters (e.g. the AUX adapter is parented by a
1741  * &drm_connector), you must still call drm_dp_aux_register() once the connector
1742  * has been registered to allow userspace access to the auxiliary DP channel.
1743  * Likewise, for such drivers you should also assign &drm_dp_aux.drm_dev as
1744  * early as possible so that the &drm_device that corresponds to the AUX adapter
1745  * may be mentioned in debugging output from the DRM DP helpers.
1746  *
1747  * For devices which use a separate platform device for their AUX adapters, this
1748  * may be called as early as required by the driver.
1749  *
1750  */
1751 void drm_dp_aux_init(struct drm_dp_aux *aux)
1752 {
1753         mutex_init(&aux->hw_mutex);
1754         mutex_init(&aux->cec.lock);
1755         INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
1756
1757         aux->ddc.algo = &drm_dp_i2c_algo;
1758         aux->ddc.algo_data = aux;
1759         aux->ddc.retries = 3;
1760
1761         aux->ddc.lock_ops = &drm_dp_i2c_lock_ops;
1762 }
1763 EXPORT_SYMBOL(drm_dp_aux_init);
1764
1765 /**
1766  * drm_dp_aux_register() - initialise and register aux channel
1767  * @aux: DisplayPort AUX channel
1768  *
1769  * Automatically calls drm_dp_aux_init() if this hasn't been done yet. This
1770  * should only be called once the parent of @aux, &drm_dp_aux.dev, is
1771  * initialized. For devices which are grandparents of their AUX channels,
1772  * &drm_dp_aux.dev will typically be the &drm_connector &device which
1773  * corresponds to @aux. For these devices, it's advised to call
1774  * drm_dp_aux_register() in &drm_connector_funcs.late_register, and likewise to
1775  * call drm_dp_aux_unregister() in &drm_connector_funcs.early_unregister.
1776  * Functions which don't follow this will likely Oops when
1777  * %CONFIG_DRM_DP_AUX_CHARDEV is enabled.
1778  *
1779  * For devices where the AUX channel is a device that exists independently of
1780  * the &drm_device that uses it, such as SoCs and bridge devices, it is
1781  * recommended to call drm_dp_aux_register() after a &drm_device has been
1782  * assigned to &drm_dp_aux.drm_dev, and likewise to call
1783  * drm_dp_aux_unregister() once the &drm_device should no longer be associated
1784  * with the AUX channel (e.g. on bridge detach).
1785  *
1786  * Drivers which need to use the aux channel before either of the two points
1787  * mentioned above need to call drm_dp_aux_init() in order to use the AUX
1788  * channel before registration.
1789  *
1790  * Returns 0 on success or a negative error code on failure.
1791  */
1792 int drm_dp_aux_register(struct drm_dp_aux *aux)
1793 {
1794         int ret;
1795
1796         WARN_ON_ONCE(!aux->drm_dev);
1797
1798         if (!aux->ddc.algo)
1799                 drm_dp_aux_init(aux);
1800
1801         aux->ddc.class = I2C_CLASS_DDC;
1802         aux->ddc.owner = THIS_MODULE;
1803         aux->ddc.dev.parent = aux->dev;
1804
1805         strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev),
1806                 sizeof(aux->ddc.name));
1807
1808         ret = drm_dp_aux_register_devnode(aux);
1809         if (ret)
1810                 return ret;
1811
1812         ret = i2c_add_adapter(&aux->ddc);
1813         if (ret) {
1814                 drm_dp_aux_unregister_devnode(aux);
1815                 return ret;
1816         }
1817
1818         return 0;
1819 }
1820 EXPORT_SYMBOL(drm_dp_aux_register);
1821
1822 /**
1823  * drm_dp_aux_unregister() - unregister an AUX adapter
1824  * @aux: DisplayPort AUX channel
1825  */
1826 void drm_dp_aux_unregister(struct drm_dp_aux *aux)
1827 {
1828         drm_dp_aux_unregister_devnode(aux);
1829         i2c_del_adapter(&aux->ddc);
1830 }
1831 EXPORT_SYMBOL(drm_dp_aux_unregister);
1832
1833 #define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x)
1834
1835 /**
1836  * drm_dp_psr_setup_time() - PSR setup in time usec
1837  * @psr_cap: PSR capabilities from DPCD
1838  *
1839  * Returns:
1840  * PSR setup time for the panel in microseconds,  negative
1841  * error code on failure.
1842  */
1843 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
1844 {
1845         static const u16 psr_setup_time_us[] = {
1846                 PSR_SETUP_TIME(330),
1847                 PSR_SETUP_TIME(275),
1848                 PSR_SETUP_TIME(220),
1849                 PSR_SETUP_TIME(165),
1850                 PSR_SETUP_TIME(110),
1851                 PSR_SETUP_TIME(55),
1852                 PSR_SETUP_TIME(0),
1853         };
1854         int i;
1855
1856         i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT;
1857         if (i >= ARRAY_SIZE(psr_setup_time_us))
1858                 return -EINVAL;
1859
1860         return psr_setup_time_us[i];
1861 }
1862 EXPORT_SYMBOL(drm_dp_psr_setup_time);
1863
1864 #undef PSR_SETUP_TIME
1865
1866 /**
1867  * drm_dp_start_crc() - start capture of frame CRCs
1868  * @aux: DisplayPort AUX channel
1869  * @crtc: CRTC displaying the frames whose CRCs are to be captured
1870  *
1871  * Returns 0 on success or a negative error code on failure.
1872  */
1873 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc)
1874 {
1875         u8 buf;
1876         int ret;
1877
1878         ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1879         if (ret < 0)
1880                 return ret;
1881
1882         ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START);
1883         if (ret < 0)
1884                 return ret;
1885
1886         aux->crc_count = 0;
1887         aux->crtc = crtc;
1888         schedule_work(&aux->crc_work);
1889
1890         return 0;
1891 }
1892 EXPORT_SYMBOL(drm_dp_start_crc);
1893
1894 /**
1895  * drm_dp_stop_crc() - stop capture of frame CRCs
1896  * @aux: DisplayPort AUX channel
1897  *
1898  * Returns 0 on success or a negative error code on failure.
1899  */
1900 int drm_dp_stop_crc(struct drm_dp_aux *aux)
1901 {
1902         u8 buf;
1903         int ret;
1904
1905         ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1906         if (ret < 0)
1907                 return ret;
1908
1909         ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START);
1910         if (ret < 0)
1911                 return ret;
1912
1913         flush_work(&aux->crc_work);
1914         aux->crtc = NULL;
1915
1916         return 0;
1917 }
1918 EXPORT_SYMBOL(drm_dp_stop_crc);
1919
1920 struct dpcd_quirk {
1921         u8 oui[3];
1922         u8 device_id[6];
1923         bool is_branch;
1924         u32 quirks;
1925 };
1926
1927 #define OUI(first, second, third) { (first), (second), (third) }
1928 #define DEVICE_ID(first, second, third, fourth, fifth, sixth) \
1929         { (first), (second), (third), (fourth), (fifth), (sixth) }
1930
1931 #define DEVICE_ID_ANY   DEVICE_ID(0, 0, 0, 0, 0, 0)
1932
1933 static const struct dpcd_quirk dpcd_quirk_list[] = {
1934         /* Analogix 7737 needs reduced M and N at HBR2 link rates */
1935         { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
1936         /* LG LP140WF6-SPM1 eDP panel */
1937         { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
1938         /* Apple panels need some additional handling to support PSR */
1939         { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) },
1940         /* CH7511 seems to leave SINK_COUNT zeroed */
1941         { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
1942         /* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
1943         { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
1944         /* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */
1945         { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
1946 };
1947
1948 #undef OUI
1949
1950 /*
1951  * Get a bit mask of DPCD quirks for the sink/branch device identified by
1952  * ident. The quirk data is shared but it's up to the drivers to act on the
1953  * data.
1954  *
1955  * For now, only the OUI (first three bytes) is used, but this may be extended
1956  * to device identification string and hardware/firmware revisions later.
1957  */
1958 static u32
1959 drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch)
1960 {
1961         const struct dpcd_quirk *quirk;
1962         u32 quirks = 0;
1963         int i;
1964         u8 any_device[] = DEVICE_ID_ANY;
1965
1966         for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
1967                 quirk = &dpcd_quirk_list[i];
1968
1969                 if (quirk->is_branch != is_branch)
1970                         continue;
1971
1972                 if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0)
1973                         continue;
1974
1975                 if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 &&
1976                     memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0)
1977                         continue;
1978
1979                 quirks |= quirk->quirks;
1980         }
1981
1982         return quirks;
1983 }
1984
1985 #undef DEVICE_ID_ANY
1986 #undef DEVICE_ID
1987
1988 /**
1989  * drm_dp_read_desc - read sink/branch descriptor from DPCD
1990  * @aux: DisplayPort AUX channel
1991  * @desc: Device descriptor to fill from DPCD
1992  * @is_branch: true for branch devices, false for sink devices
1993  *
1994  * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the
1995  * identification.
1996  *
1997  * Returns 0 on success or a negative error code on failure.
1998  */
1999 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
2000                      bool is_branch)
2001 {
2002         struct drm_dp_dpcd_ident *ident = &desc->ident;
2003         unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI;
2004         int ret, dev_id_len;
2005
2006         ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident));
2007         if (ret < 0)
2008                 return ret;
2009
2010         desc->quirks = drm_dp_get_quirks(ident, is_branch);
2011
2012         dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id));
2013
2014         drm_dbg_kms(aux->drm_dev,
2015                     "%s: DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n",
2016                     aux->name, is_branch ? "branch" : "sink",
2017                     (int)sizeof(ident->oui), ident->oui, dev_id_len,
2018                     ident->device_id, ident->hw_rev >> 4, ident->hw_rev & 0xf,
2019                     ident->sw_major_rev, ident->sw_minor_rev, desc->quirks);
2020
2021         return 0;
2022 }
2023 EXPORT_SYMBOL(drm_dp_read_desc);
2024
2025 /**
2026  * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
2027  * supported by the DSC sink.
2028  * @dsc_dpcd: DSC capabilities from DPCD
2029  * @is_edp: true if its eDP, false for DP
2030  *
2031  * Read the slice capabilities DPCD register from DSC sink to get
2032  * the maximum slice count supported. This is used to populate
2033  * the DSC parameters in the &struct drm_dsc_config by the driver.
2034  * Driver creates an infoframe using these parameters to populate
2035  * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2036  * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2037  *
2038  * Returns:
2039  * Maximum slice count supported by DSC sink or 0 its invalid
2040  */
2041 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
2042                                    bool is_edp)
2043 {
2044         u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
2045
2046         if (is_edp) {
2047                 /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */
2048                 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
2049                         return 4;
2050                 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
2051                         return 2;
2052                 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
2053                         return 1;
2054         } else {
2055                 /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */
2056                 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
2057
2058                 if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
2059                         return 24;
2060                 if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
2061                         return 20;
2062                 if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
2063                         return 16;
2064                 if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
2065                         return 12;
2066                 if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
2067                         return 10;
2068                 if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
2069                         return 8;
2070                 if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
2071                         return 6;
2072                 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
2073                         return 4;
2074                 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
2075                         return 2;
2076                 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
2077                         return 1;
2078         }
2079
2080         return 0;
2081 }
2082 EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
2083
2084 /**
2085  * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits
2086  * @dsc_dpcd: DSC capabilities from DPCD
2087  *
2088  * Read the DSC DPCD register to parse the line buffer depth in bits which is
2089  * number of bits of precision within the decoder line buffer supported by
2090  * the DSC sink. This is used to populate the DSC parameters in the
2091  * &struct drm_dsc_config by the driver.
2092  * Driver creates an infoframe using these parameters to populate
2093  * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2094  * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2095  *
2096  * Returns:
2097  * Line buffer depth supported by DSC panel or 0 its invalid
2098  */
2099 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
2100 {
2101         u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT];
2102
2103         switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) {
2104         case DP_DSC_LINE_BUF_BIT_DEPTH_9:
2105                 return 9;
2106         case DP_DSC_LINE_BUF_BIT_DEPTH_10:
2107                 return 10;
2108         case DP_DSC_LINE_BUF_BIT_DEPTH_11:
2109                 return 11;
2110         case DP_DSC_LINE_BUF_BIT_DEPTH_12:
2111                 return 12;
2112         case DP_DSC_LINE_BUF_BIT_DEPTH_13:
2113                 return 13;
2114         case DP_DSC_LINE_BUF_BIT_DEPTH_14:
2115                 return 14;
2116         case DP_DSC_LINE_BUF_BIT_DEPTH_15:
2117                 return 15;
2118         case DP_DSC_LINE_BUF_BIT_DEPTH_16:
2119                 return 16;
2120         case DP_DSC_LINE_BUF_BIT_DEPTH_8:
2121                 return 8;
2122         }
2123
2124         return 0;
2125 }
2126 EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
2127
2128 /**
2129  * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component
2130  * values supported by the DSC sink.
2131  * @dsc_dpcd: DSC capabilities from DPCD
2132  * @dsc_bpc: An array to be filled by this helper with supported
2133  *           input bpcs.
2134  *
2135  * Read the DSC DPCD from the sink device to parse the supported bits per
2136  * component values. This is used to populate the DSC parameters
2137  * in the &struct drm_dsc_config by the driver.
2138  * Driver creates an infoframe using these parameters to populate
2139  * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2140  * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2141  *
2142  * Returns:
2143  * Number of input BPC values parsed from the DPCD
2144  */
2145 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
2146                                          u8 dsc_bpc[3])
2147 {
2148         int num_bpc = 0;
2149         u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
2150
2151         if (color_depth & DP_DSC_12_BPC)
2152                 dsc_bpc[num_bpc++] = 12;
2153         if (color_depth & DP_DSC_10_BPC)
2154                 dsc_bpc[num_bpc++] = 10;
2155         if (color_depth & DP_DSC_8_BPC)
2156                 dsc_bpc[num_bpc++] = 8;
2157
2158         return num_bpc;
2159 }
2160 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
2161
2162 /**
2163  * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
2164  * @aux: DisplayPort AUX channel
2165  * @caps: buffer to return the capability info in
2166  *
2167  * Read capabilities common to all LTTPRs.
2168  *
2169  * Returns 0 on success or a negative error code on failure.
2170  */
2171 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
2172                                   u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2173 {
2174         int ret;
2175
2176         ret = drm_dp_dpcd_read(aux,
2177                                DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
2178                                caps, DP_LTTPR_COMMON_CAP_SIZE);
2179         if (ret < 0)
2180                 return ret;
2181
2182         WARN_ON(ret != DP_LTTPR_COMMON_CAP_SIZE);
2183
2184         return 0;
2185 }
2186 EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
2187
2188 /**
2189  * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY
2190  * @aux: DisplayPort AUX channel
2191  * @dp_phy: LTTPR PHY to read the capabilities for
2192  * @caps: buffer to return the capability info in
2193  *
2194  * Read the capabilities for the given LTTPR PHY.
2195  *
2196  * Returns 0 on success or a negative error code on failure.
2197  */
2198 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
2199                                enum drm_dp_phy dp_phy,
2200                                u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2201 {
2202         int ret;
2203
2204         ret = drm_dp_dpcd_read(aux,
2205                                DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
2206                                caps, DP_LTTPR_PHY_CAP_SIZE);
2207         if (ret < 0)
2208                 return ret;
2209
2210         WARN_ON(ret != DP_LTTPR_PHY_CAP_SIZE);
2211
2212         return 0;
2213 }
2214 EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps);
2215
2216 static u8 dp_lttpr_common_cap(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE], int r)
2217 {
2218         return caps[r - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
2219 }
2220
2221 /**
2222  * drm_dp_lttpr_count - get the number of detected LTTPRs
2223  * @caps: LTTPR common capabilities
2224  *
2225  * Get the number of detected LTTPRs from the LTTPR common capabilities info.
2226  *
2227  * Returns:
2228  *   -ERANGE if more than supported number (8) of LTTPRs are detected
2229  *   -EINVAL if the DP_PHY_REPEATER_CNT register contains an invalid value
2230  *   otherwise the number of detected LTTPRs
2231  */
2232 int drm_dp_lttpr_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2233 {
2234         u8 count = dp_lttpr_common_cap(caps, DP_PHY_REPEATER_CNT);
2235
2236         switch (hweight8(count)) {
2237         case 0:
2238                 return 0;
2239         case 1:
2240                 return 8 - ilog2(count);
2241         case 8:
2242                 return -ERANGE;
2243         default:
2244                 return -EINVAL;
2245         }
2246 }
2247 EXPORT_SYMBOL(drm_dp_lttpr_count);
2248
2249 /**
2250  * drm_dp_lttpr_max_link_rate - get the maximum link rate supported by all LTTPRs
2251  * @caps: LTTPR common capabilities
2252  *
2253  * Returns the maximum link rate supported by all detected LTTPRs.
2254  */
2255 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2256 {
2257         u8 rate = dp_lttpr_common_cap(caps, DP_MAX_LINK_RATE_PHY_REPEATER);
2258
2259         return drm_dp_bw_code_to_link_rate(rate);
2260 }
2261 EXPORT_SYMBOL(drm_dp_lttpr_max_link_rate);
2262
2263 /**
2264  * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs
2265  * @caps: LTTPR common capabilities
2266  *
2267  * Returns the maximum lane count supported by all detected LTTPRs.
2268  */
2269 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2270 {
2271         u8 max_lanes = dp_lttpr_common_cap(caps, DP_MAX_LANE_COUNT_PHY_REPEATER);
2272
2273         return max_lanes & DP_MAX_LANE_COUNT_MASK;
2274 }
2275 EXPORT_SYMBOL(drm_dp_lttpr_max_lane_count);
2276
2277 /**
2278  * drm_dp_lttpr_voltage_swing_level_3_supported - check for LTTPR vswing3 support
2279  * @caps: LTTPR PHY capabilities
2280  *
2281  * Returns true if the @caps for an LTTPR TX PHY indicate support for
2282  * voltage swing level 3.
2283  */
2284 bool
2285 drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2286 {
2287         u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
2288
2289         return txcap & DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED;
2290 }
2291 EXPORT_SYMBOL(drm_dp_lttpr_voltage_swing_level_3_supported);
2292
2293 /**
2294  * drm_dp_lttpr_pre_emphasis_level_3_supported - check for LTTPR preemph3 support
2295  * @caps: LTTPR PHY capabilities
2296  *
2297  * Returns true if the @caps for an LTTPR TX PHY indicate support for
2298  * pre-emphasis level 3.
2299  */
2300 bool
2301 drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2302 {
2303         u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
2304
2305         return txcap & DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED;
2306 }
2307 EXPORT_SYMBOL(drm_dp_lttpr_pre_emphasis_level_3_supported);
2308
2309 /**
2310  * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
2311  * @aux: DisplayPort AUX channel
2312  * @data: DP phy compliance test parameters.
2313  *
2314  * Returns 0 on success or a negative error code on failure.
2315  */
2316 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
2317                                 struct drm_dp_phy_test_params *data)
2318 {
2319         int err;
2320         u8 rate, lanes;
2321
2322         err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
2323         if (err < 0)
2324                 return err;
2325         data->link_rate = drm_dp_bw_code_to_link_rate(rate);
2326
2327         err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
2328         if (err < 0)
2329                 return err;
2330         data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
2331
2332         if (lanes & DP_ENHANCED_FRAME_CAP)
2333                 data->enhanced_frame_cap = true;
2334
2335         err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern);
2336         if (err < 0)
2337                 return err;
2338
2339         switch (data->phy_pattern) {
2340         case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
2341                 err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
2342                                        &data->custom80, sizeof(data->custom80));
2343                 if (err < 0)
2344                         return err;
2345
2346                 break;
2347         case DP_PHY_TEST_PATTERN_CP2520:
2348                 err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
2349                                        &data->hbr2_reset,
2350                                        sizeof(data->hbr2_reset));
2351                 if (err < 0)
2352                         return err;
2353         }
2354
2355         return 0;
2356 }
2357 EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
2358
2359 /**
2360  * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
2361  * @aux: DisplayPort AUX channel
2362  * @data: DP phy compliance test parameters.
2363  * @dp_rev: DP revision to use for compliance testing
2364  *
2365  * Returns 0 on success or a negative error code on failure.
2366  */
2367 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
2368                                 struct drm_dp_phy_test_params *data, u8 dp_rev)
2369 {
2370         int err, i;
2371         u8 link_config[2];
2372         u8 test_pattern;
2373
2374         link_config[0] = drm_dp_link_rate_to_bw_code(data->link_rate);
2375         link_config[1] = data->num_lanes;
2376         if (data->enhanced_frame_cap)
2377                 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
2378         err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, link_config, 2);
2379         if (err < 0)
2380                 return err;
2381
2382         test_pattern = data->phy_pattern;
2383         if (dp_rev < 0x12) {
2384                 test_pattern = (test_pattern << 2) &
2385                                DP_LINK_QUAL_PATTERN_11_MASK;
2386                 err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
2387                                          test_pattern);
2388                 if (err < 0)
2389                         return err;
2390         } else {
2391                 for (i = 0; i < data->num_lanes; i++) {
2392                         err = drm_dp_dpcd_writeb(aux,
2393                                                  DP_LINK_QUAL_LANE0_SET + i,
2394                                                  test_pattern);
2395                         if (err < 0)
2396                                 return err;
2397                 }
2398         }
2399
2400         return 0;
2401 }
2402 EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
2403
2404 static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat)
2405 {
2406         if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
2407                 return "Invalid";
2408
2409         switch (pixelformat) {
2410         case DP_PIXELFORMAT_RGB:
2411                 return "RGB";
2412         case DP_PIXELFORMAT_YUV444:
2413                 return "YUV444";
2414         case DP_PIXELFORMAT_YUV422:
2415                 return "YUV422";
2416         case DP_PIXELFORMAT_YUV420:
2417                 return "YUV420";
2418         case DP_PIXELFORMAT_Y_ONLY:
2419                 return "Y_ONLY";
2420         case DP_PIXELFORMAT_RAW:
2421                 return "RAW";
2422         default:
2423                 return "Reserved";
2424         }
2425 }
2426
2427 static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat,
2428                                            enum dp_colorimetry colorimetry)
2429 {
2430         if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
2431                 return "Invalid";
2432
2433         switch (colorimetry) {
2434         case DP_COLORIMETRY_DEFAULT:
2435                 switch (pixelformat) {
2436                 case DP_PIXELFORMAT_RGB:
2437                         return "sRGB";
2438                 case DP_PIXELFORMAT_YUV444:
2439                 case DP_PIXELFORMAT_YUV422:
2440                 case DP_PIXELFORMAT_YUV420:
2441                         return "BT.601";
2442                 case DP_PIXELFORMAT_Y_ONLY:
2443                         return "DICOM PS3.14";
2444                 case DP_PIXELFORMAT_RAW:
2445                         return "Custom Color Profile";
2446                 default:
2447                         return "Reserved";
2448                 }
2449         case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */
2450                 switch (pixelformat) {
2451                 case DP_PIXELFORMAT_RGB:
2452                         return "Wide Fixed";
2453                 case DP_PIXELFORMAT_YUV444:
2454                 case DP_PIXELFORMAT_YUV422:
2455                 case DP_PIXELFORMAT_YUV420:
2456                         return "BT.709";
2457                 default:
2458                         return "Reserved";
2459                 }
2460         case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */
2461                 switch (pixelformat) {
2462                 case DP_PIXELFORMAT_RGB:
2463                         return "Wide Float";
2464                 case DP_PIXELFORMAT_YUV444:
2465                 case DP_PIXELFORMAT_YUV422:
2466                 case DP_PIXELFORMAT_YUV420:
2467                         return "xvYCC 601";
2468                 default:
2469                         return "Reserved";
2470                 }
2471         case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
2472                 switch (pixelformat) {
2473                 case DP_PIXELFORMAT_RGB:
2474                         return "OpRGB";
2475                 case DP_PIXELFORMAT_YUV444:
2476                 case DP_PIXELFORMAT_YUV422:
2477                 case DP_PIXELFORMAT_YUV420:
2478                         return "xvYCC 709";
2479                 default:
2480                         return "Reserved";
2481                 }
2482         case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */
2483                 switch (pixelformat) {
2484                 case DP_PIXELFORMAT_RGB:
2485                         return "DCI-P3";
2486                 case DP_PIXELFORMAT_YUV444:
2487                 case DP_PIXELFORMAT_YUV422:
2488                 case DP_PIXELFORMAT_YUV420:
2489                         return "sYCC 601";
2490                 default:
2491                         return "Reserved";
2492                 }
2493         case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */
2494                 switch (pixelformat) {
2495                 case DP_PIXELFORMAT_RGB:
2496                         return "Custom Profile";
2497                 case DP_PIXELFORMAT_YUV444:
2498                 case DP_PIXELFORMAT_YUV422:
2499                 case DP_PIXELFORMAT_YUV420:
2500                         return "OpYCC 601";
2501                 default:
2502                         return "Reserved";
2503                 }
2504         case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */
2505                 switch (pixelformat) {
2506                 case DP_PIXELFORMAT_RGB:
2507                         return "BT.2020 RGB";
2508                 case DP_PIXELFORMAT_YUV444:
2509                 case DP_PIXELFORMAT_YUV422:
2510                 case DP_PIXELFORMAT_YUV420:
2511                         return "BT.2020 CYCC";
2512                 default:
2513                         return "Reserved";
2514                 }
2515         case DP_COLORIMETRY_BT2020_YCC:
2516                 switch (pixelformat) {
2517                 case DP_PIXELFORMAT_YUV444:
2518                 case DP_PIXELFORMAT_YUV422:
2519                 case DP_PIXELFORMAT_YUV420:
2520                         return "BT.2020 YCC";
2521                 default:
2522                         return "Reserved";
2523                 }
2524         default:
2525                 return "Invalid";
2526         }
2527 }
2528
2529 static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range)
2530 {
2531         switch (dynamic_range) {
2532         case DP_DYNAMIC_RANGE_VESA:
2533                 return "VESA range";
2534         case DP_DYNAMIC_RANGE_CTA:
2535                 return "CTA range";
2536         default:
2537                 return "Invalid";
2538         }
2539 }
2540
2541 static const char *dp_content_type_get_name(enum dp_content_type content_type)
2542 {
2543         switch (content_type) {
2544         case DP_CONTENT_TYPE_NOT_DEFINED:
2545                 return "Not defined";
2546         case DP_CONTENT_TYPE_GRAPHICS:
2547                 return "Graphics";
2548         case DP_CONTENT_TYPE_PHOTO:
2549                 return "Photo";
2550         case DP_CONTENT_TYPE_VIDEO:
2551                 return "Video";
2552         case DP_CONTENT_TYPE_GAME:
2553                 return "Game";
2554         default:
2555                 return "Reserved";
2556         }
2557 }
2558
2559 void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
2560                         const struct drm_dp_vsc_sdp *vsc)
2561 {
2562 #define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__)
2563         DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC",
2564                    vsc->revision, vsc->length);
2565         DP_SDP_LOG("    pixelformat: %s\n",
2566                    dp_pixelformat_get_name(vsc->pixelformat));
2567         DP_SDP_LOG("    colorimetry: %s\n",
2568                    dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry));
2569         DP_SDP_LOG("    bpc: %u\n", vsc->bpc);
2570         DP_SDP_LOG("    dynamic range: %s\n",
2571                    dp_dynamic_range_get_name(vsc->dynamic_range));
2572         DP_SDP_LOG("    content type: %s\n",
2573                    dp_content_type_get_name(vsc->content_type));
2574 #undef DP_SDP_LOG
2575 }
2576 EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
2577
2578 /**
2579  * drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON
2580  * @dpcd: DisplayPort configuration data
2581  * @port_cap: port capabilities
2582  *
2583  * Returns maximum frl bandwidth supported by PCON in GBPS,
2584  * returns 0 if not supported.
2585  */
2586 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2587                                const u8 port_cap[4])
2588 {
2589         int bw;
2590         u8 buf;
2591
2592         buf = port_cap[2];
2593         bw = buf & DP_PCON_MAX_FRL_BW;
2594
2595         switch (bw) {
2596         case DP_PCON_MAX_9GBPS:
2597                 return 9;
2598         case DP_PCON_MAX_18GBPS:
2599                 return 18;
2600         case DP_PCON_MAX_24GBPS:
2601                 return 24;
2602         case DP_PCON_MAX_32GBPS:
2603                 return 32;
2604         case DP_PCON_MAX_40GBPS:
2605                 return 40;
2606         case DP_PCON_MAX_48GBPS:
2607                 return 48;
2608         case DP_PCON_MAX_0GBPS:
2609         default:
2610                 return 0;
2611         }
2612
2613         return 0;
2614 }
2615 EXPORT_SYMBOL(drm_dp_get_pcon_max_frl_bw);
2616
2617 /**
2618  * drm_dp_pcon_frl_prepare() - Prepare PCON for FRL.
2619  * @aux: DisplayPort AUX channel
2620  * @enable_frl_ready_hpd: Configure DP_PCON_ENABLE_HPD_READY.
2621  *
2622  * Returns 0 if success, else returns negative error code.
2623  */
2624 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd)
2625 {
2626         int ret;
2627         u8 buf = DP_PCON_ENABLE_SOURCE_CTL_MODE |
2628                  DP_PCON_ENABLE_LINK_FRL_MODE;
2629
2630         if (enable_frl_ready_hpd)
2631                 buf |= DP_PCON_ENABLE_HPD_READY;
2632
2633         ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2634
2635         return ret;
2636 }
2637 EXPORT_SYMBOL(drm_dp_pcon_frl_prepare);
2638
2639 /**
2640  * drm_dp_pcon_is_frl_ready() - Is PCON ready for FRL
2641  * @aux: DisplayPort AUX channel
2642  *
2643  * Returns true if success, else returns false.
2644  */
2645 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux)
2646 {
2647         int ret;
2648         u8 buf;
2649
2650         ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf);
2651         if (ret < 0)
2652                 return false;
2653
2654         if (buf & DP_PCON_FRL_READY)
2655                 return true;
2656
2657         return false;
2658 }
2659 EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready);
2660
2661 /**
2662  * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
2663  * @aux: DisplayPort AUX channel
2664  * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink
2665  * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential.
2666  * In Concurrent Mode, the FRL link bring up can be done along with
2667  * DP Link training. In Sequential mode, the FRL link bring up is done prior to
2668  * the DP Link training.
2669  *
2670  * Returns 0 if success, else returns negative error code.
2671  */
2672
2673 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
2674                                 u8 frl_mode)
2675 {
2676         int ret;
2677         u8 buf;
2678
2679         ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf);
2680         if (ret < 0)
2681                 return ret;
2682
2683         if (frl_mode == DP_PCON_ENABLE_CONCURRENT_LINK)
2684                 buf |= DP_PCON_ENABLE_CONCURRENT_LINK;
2685         else
2686                 buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK;
2687
2688         switch (max_frl_gbps) {
2689         case 9:
2690                 buf |=  DP_PCON_ENABLE_MAX_BW_9GBPS;
2691                 break;
2692         case 18:
2693                 buf |=  DP_PCON_ENABLE_MAX_BW_18GBPS;
2694                 break;
2695         case 24:
2696                 buf |=  DP_PCON_ENABLE_MAX_BW_24GBPS;
2697                 break;
2698         case 32:
2699                 buf |=  DP_PCON_ENABLE_MAX_BW_32GBPS;
2700                 break;
2701         case 40:
2702                 buf |=  DP_PCON_ENABLE_MAX_BW_40GBPS;
2703                 break;
2704         case 48:
2705                 buf |=  DP_PCON_ENABLE_MAX_BW_48GBPS;
2706                 break;
2707         case 0:
2708                 buf |=  DP_PCON_ENABLE_MAX_BW_0GBPS;
2709                 break;
2710         default:
2711                 return -EINVAL;
2712         }
2713
2714         ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2715         if (ret < 0)
2716                 return ret;
2717
2718         return 0;
2719 }
2720 EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1);
2721
2722 /**
2723  * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
2724  * @aux: DisplayPort AUX channel
2725  * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink
2726  * @frl_type : FRL training type, can be Extended, or Normal.
2727  * In Normal FRL training, the PCON tries each frl bw from the max_frl_mask
2728  * starting from min, and stops when link training is successful. In Extended
2729  * FRL training, all frl bw selected in the mask are trained by the PCON.
2730  *
2731  * Returns 0 if success, else returns negative error code.
2732  */
2733 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
2734                                 u8 frl_type)
2735 {
2736         int ret;
2737         u8 buf = max_frl_mask;
2738
2739         if (frl_type == DP_PCON_FRL_LINK_TRAIN_EXTENDED)
2740                 buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED;
2741         else
2742                 buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED;
2743
2744         ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf);
2745         if (ret < 0)
2746                 return ret;
2747
2748         return 0;
2749 }
2750 EXPORT_SYMBOL(drm_dp_pcon_frl_configure_2);
2751
2752 /**
2753  * drm_dp_pcon_reset_frl_config() - Re-Set HDMI Link configuration.
2754  * @aux: DisplayPort AUX channel
2755  *
2756  * Returns 0 if success, else returns negative error code.
2757  */
2758 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux)
2759 {
2760         int ret;
2761
2762         ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, 0x0);
2763         if (ret < 0)
2764                 return ret;
2765
2766         return 0;
2767 }
2768 EXPORT_SYMBOL(drm_dp_pcon_reset_frl_config);
2769
2770 /**
2771  * drm_dp_pcon_frl_enable() - Enable HDMI link through FRL
2772  * @aux: DisplayPort AUX channel
2773  *
2774  * Returns 0 if success, else returns negative error code.
2775  */
2776 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux)
2777 {
2778         int ret;
2779         u8 buf = 0;
2780
2781         ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf);
2782         if (ret < 0)
2783                 return ret;
2784         if (!(buf & DP_PCON_ENABLE_SOURCE_CTL_MODE)) {
2785                 drm_dbg_kms(aux->drm_dev, "%s: PCON in Autonomous mode, can't enable FRL\n",
2786                             aux->name);
2787                 return -EINVAL;
2788         }
2789         buf |= DP_PCON_ENABLE_HDMI_LINK;
2790         ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2791         if (ret < 0)
2792                 return ret;
2793
2794         return 0;
2795 }
2796 EXPORT_SYMBOL(drm_dp_pcon_frl_enable);
2797
2798 /**
2799  * drm_dp_pcon_hdmi_link_active() - check if the PCON HDMI LINK status is active.
2800  * @aux: DisplayPort AUX channel
2801  *
2802  * Returns true if link is active else returns false.
2803  */
2804 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux)
2805 {
2806         u8 buf;
2807         int ret;
2808
2809         ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf);
2810         if (ret < 0)
2811                 return false;
2812
2813         return buf & DP_PCON_HDMI_TX_LINK_ACTIVE;
2814 }
2815 EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_active);
2816
2817 /**
2818  * drm_dp_pcon_hdmi_link_mode() - get the PCON HDMI LINK MODE
2819  * @aux: DisplayPort AUX channel
2820  * @frl_trained_mask: pointer to store bitmask of the trained bw configuration.
2821  * Valid only if the MODE returned is FRL. For Normal Link training mode
2822  * only 1 of the bits will be set, but in case of Extended mode, more than
2823  * one bits can be set.
2824  *
2825  * Returns the link mode : TMDS or FRL on success, else returns negative error
2826  * code.
2827  */
2828 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask)
2829 {
2830         u8 buf;
2831         int mode;
2832         int ret;
2833
2834         ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_POST_FRL_STATUS, &buf);
2835         if (ret < 0)
2836                 return ret;
2837
2838         mode = buf & DP_PCON_HDMI_LINK_MODE;
2839
2840         if (frl_trained_mask && DP_PCON_HDMI_MODE_FRL == mode)
2841                 *frl_trained_mask = (buf & DP_PCON_HDMI_FRL_TRAINED_BW) >> 1;
2842
2843         return mode;
2844 }
2845 EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_mode);
2846
2847 /**
2848  * drm_dp_pcon_hdmi_frl_link_error_count() - print the error count per lane
2849  * during link failure between PCON and HDMI sink
2850  * @aux: DisplayPort AUX channel
2851  * @connector: DRM connector
2852  * code.
2853  **/
2854
2855 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
2856                                            struct drm_connector *connector)
2857 {
2858         u8 buf, error_count;
2859         int i, num_error;
2860         struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
2861
2862         for (i = 0; i < hdmi->max_lanes; i++) {
2863                 if (drm_dp_dpcd_readb(aux, DP_PCON_HDMI_ERROR_STATUS_LN0 + i, &buf) < 0)
2864                         return;
2865
2866                 error_count = buf & DP_PCON_HDMI_ERROR_COUNT_MASK;
2867                 switch (error_count) {
2868                 case DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS:
2869                         num_error = 100;
2870                         break;
2871                 case DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS:
2872                         num_error = 10;
2873                         break;
2874                 case DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS:
2875                         num_error = 3;
2876                         break;
2877                 default:
2878                         num_error = 0;
2879                 }
2880
2881                 drm_err(aux->drm_dev, "%s: More than %d errors since the last read for lane %d",
2882                         aux->name, num_error, i);
2883         }
2884 }
2885 EXPORT_SYMBOL(drm_dp_pcon_hdmi_frl_link_error_count);
2886
2887 /*
2888  * drm_dp_pcon_enc_is_dsc_1_2 - Does PCON Encoder supports DSC 1.2
2889  * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
2890  *
2891  * Returns true is PCON encoder is DSC 1.2 else returns false.
2892  */
2893 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
2894 {
2895         u8 buf;
2896         u8 major_v, minor_v;
2897
2898         buf = pcon_dsc_dpcd[DP_PCON_DSC_VERSION - DP_PCON_DSC_ENCODER];
2899         major_v = (buf & DP_PCON_DSC_MAJOR_MASK) >> DP_PCON_DSC_MAJOR_SHIFT;
2900         minor_v = (buf & DP_PCON_DSC_MINOR_MASK) >> DP_PCON_DSC_MINOR_SHIFT;
2901
2902         if (major_v == 1 && minor_v == 2)
2903                 return true;
2904
2905         return false;
2906 }
2907 EXPORT_SYMBOL(drm_dp_pcon_enc_is_dsc_1_2);
2908
2909 /*
2910  * drm_dp_pcon_dsc_max_slices - Get max slices supported by PCON DSC Encoder
2911  * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
2912  *
2913  * Returns maximum no. of slices supported by the PCON DSC Encoder.
2914  */
2915 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
2916 {
2917         u8 slice_cap1, slice_cap2;
2918
2919         slice_cap1 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_1 - DP_PCON_DSC_ENCODER];
2920         slice_cap2 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_2 - DP_PCON_DSC_ENCODER];
2921
2922         if (slice_cap2 & DP_PCON_DSC_24_PER_DSC_ENC)
2923                 return 24;
2924         if (slice_cap2 & DP_PCON_DSC_20_PER_DSC_ENC)
2925                 return 20;
2926         if (slice_cap2 & DP_PCON_DSC_16_PER_DSC_ENC)
2927                 return 16;
2928         if (slice_cap1 & DP_PCON_DSC_12_PER_DSC_ENC)
2929                 return 12;
2930         if (slice_cap1 & DP_PCON_DSC_10_PER_DSC_ENC)
2931                 return 10;
2932         if (slice_cap1 & DP_PCON_DSC_8_PER_DSC_ENC)
2933                 return 8;
2934         if (slice_cap1 & DP_PCON_DSC_6_PER_DSC_ENC)
2935                 return 6;
2936         if (slice_cap1 & DP_PCON_DSC_4_PER_DSC_ENC)
2937                 return 4;
2938         if (slice_cap1 & DP_PCON_DSC_2_PER_DSC_ENC)
2939                 return 2;
2940         if (slice_cap1 & DP_PCON_DSC_1_PER_DSC_ENC)
2941                 return 1;
2942
2943         return 0;
2944 }
2945 EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slices);
2946
2947 /*
2948  * drm_dp_pcon_dsc_max_slice_width() - Get max slice width for Pcon DSC encoder
2949  * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
2950  *
2951  * Returns maximum width of the slices in pixel width i.e. no. of pixels x 320.
2952  */
2953 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
2954 {
2955         u8 buf;
2956
2957         buf = pcon_dsc_dpcd[DP_PCON_DSC_MAX_SLICE_WIDTH - DP_PCON_DSC_ENCODER];
2958
2959         return buf * DP_DSC_SLICE_WIDTH_MULTIPLIER;
2960 }
2961 EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slice_width);
2962
2963 /*
2964  * drm_dp_pcon_dsc_bpp_incr() - Get bits per pixel increment for PCON DSC encoder
2965  * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
2966  *
2967  * Returns the bpp precision supported by the PCON encoder.
2968  */
2969 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
2970 {
2971         u8 buf;
2972
2973         buf = pcon_dsc_dpcd[DP_PCON_DSC_BPP_INCR - DP_PCON_DSC_ENCODER];
2974
2975         switch (buf & DP_PCON_DSC_BPP_INCR_MASK) {
2976         case DP_PCON_DSC_ONE_16TH_BPP:
2977                 return 16;
2978         case DP_PCON_DSC_ONE_8TH_BPP:
2979                 return 8;
2980         case DP_PCON_DSC_ONE_4TH_BPP:
2981                 return 4;
2982         case DP_PCON_DSC_ONE_HALF_BPP:
2983                 return 2;
2984         case DP_PCON_DSC_ONE_BPP:
2985                 return 1;
2986         }
2987
2988         return 0;
2989 }
2990 EXPORT_SYMBOL(drm_dp_pcon_dsc_bpp_incr);
2991
2992 static
2993 int drm_dp_pcon_configure_dsc_enc(struct drm_dp_aux *aux, u8 pps_buf_config)
2994 {
2995         u8 buf;
2996         int ret;
2997
2998         ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf);
2999         if (ret < 0)
3000                 return ret;
3001
3002         buf |= DP_PCON_ENABLE_DSC_ENCODER;
3003
3004         if (pps_buf_config <= DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER) {
3005                 buf &= ~DP_PCON_ENCODER_PPS_OVERRIDE_MASK;
3006                 buf |= pps_buf_config << 2;
3007         }
3008
3009         ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf);
3010         if (ret < 0)
3011                 return ret;
3012
3013         return 0;
3014 }
3015
3016 /**
3017  * drm_dp_pcon_pps_default() - Let PCON fill the default pps parameters
3018  * for DSC1.2 between PCON & HDMI2.1 sink
3019  * @aux: DisplayPort AUX channel
3020  *
3021  * Returns 0 on success, else returns negative error code.
3022  */
3023 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux)
3024 {
3025         int ret;
3026
3027         ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_DISABLED);
3028         if (ret < 0)
3029                 return ret;
3030
3031         return 0;
3032 }
3033 EXPORT_SYMBOL(drm_dp_pcon_pps_default);
3034
3035 /**
3036  * drm_dp_pcon_pps_override_buf() - Configure PPS encoder override buffer for
3037  * HDMI sink
3038  * @aux: DisplayPort AUX channel
3039  * @pps_buf: 128 bytes to be written into PPS buffer for HDMI sink by PCON.
3040  *
3041  * Returns 0 on success, else returns negative error code.
3042  */
3043 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128])
3044 {
3045         int ret;
3046
3047         ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVERRIDE_BASE, &pps_buf, 128);
3048         if (ret < 0)
3049                 return ret;
3050
3051         ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
3052         if (ret < 0)
3053                 return ret;
3054
3055         return 0;
3056 }
3057 EXPORT_SYMBOL(drm_dp_pcon_pps_override_buf);
3058
3059 /*
3060  * drm_dp_pcon_pps_override_param() - Write PPS parameters to DSC encoder
3061  * override registers
3062  * @aux: DisplayPort AUX channel
3063  * @pps_param: 3 Parameters (2 Bytes each) : Slice Width, Slice Height,
3064  * bits_per_pixel.
3065  *
3066  * Returns 0 on success, else returns negative error code.
3067  */
3068 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6])
3069 {
3070         int ret;
3071
3072         ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT, &pps_param[0], 2);
3073         if (ret < 0)
3074                 return ret;
3075         ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH, &pps_param[2], 2);
3076         if (ret < 0)
3077                 return ret;
3078         ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_BPP, &pps_param[4], 2);
3079         if (ret < 0)
3080                 return ret;
3081
3082         ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
3083         if (ret < 0)
3084                 return ret;
3085
3086         return 0;
3087 }
3088 EXPORT_SYMBOL(drm_dp_pcon_pps_override_param);
3089
3090 /*
3091  * drm_dp_pcon_convert_rgb_to_ycbcr() - Configure the PCon to convert RGB to Ycbcr
3092  * @aux: displayPort AUX channel
3093  * @color_spc: Color-space/s for which conversion is to be enabled, 0 for disable.
3094  *
3095  * Returns 0 on success, else returns negative error code.
3096  */
3097 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc)
3098 {
3099         int ret;
3100         u8 buf;
3101
3102         ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf);
3103         if (ret < 0)
3104                 return ret;
3105
3106         if (color_spc & DP_CONVERSION_RGB_YCBCR_MASK)
3107                 buf |= (color_spc & DP_CONVERSION_RGB_YCBCR_MASK);
3108         else
3109                 buf &= ~DP_CONVERSION_RGB_YCBCR_MASK;
3110
3111         ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf);
3112         if (ret < 0)
3113                 return ret;
3114
3115         return 0;
3116 }
3117 EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr);