1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright(c) 2020, Analogix Semiconductor. All rights reserved.
7 #include <linux/gpio/consumer.h>
9 #include <linux/interrupt.h>
10 #include <linux/iopoll.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/mutex.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/slab.h>
17 #include <linux/types.h>
18 #include <linux/workqueue.h>
20 #include <linux/of_gpio.h>
21 #include <linux/of_graph.h>
22 #include <linux/of_platform.h>
24 #include <drm/drm_atomic_helper.h>
25 #include <drm/drm_bridge.h>
26 #include <drm/drm_crtc_helper.h>
27 #include <drm/drm_dp_helper.h>
28 #include <drm/drm_edid.h>
29 #include <drm/drm_mipi_dsi.h>
30 #include <drm/drm_of.h>
31 #include <drm/drm_panel.h>
32 #include <drm/drm_print.h>
33 #include <drm/drm_probe_helper.h>
35 #include <video/display_timing.h>
40 * There is a sync issue while access I2C register between AP(CPU) and
41 * internal firmware(OCM), to avoid the race condition, AP should access
42 * the reserved slave address before slave address occurs changes.
44 static int i2c_access_workaround(struct anx7625_data *ctx,
45 struct i2c_client *client)
48 struct device *dev = &client->dev;
51 if (client == ctx->last_client)
54 ctx->last_client = client;
56 if (client == ctx->i2c.tcpc_client)
57 offset = RSVD_00_ADDR;
58 else if (client == ctx->i2c.tx_p0_client)
59 offset = RSVD_D1_ADDR;
60 else if (client == ctx->i2c.tx_p1_client)
61 offset = RSVD_60_ADDR;
62 else if (client == ctx->i2c.rx_p0_client)
63 offset = RSVD_39_ADDR;
64 else if (client == ctx->i2c.rx_p1_client)
65 offset = RSVD_7F_ADDR;
67 offset = RSVD_00_ADDR;
69 ret = i2c_smbus_write_byte_data(client, offset, 0x00);
72 "fail to access i2c id=%x\n:%x",
73 client->addr, offset);
78 static int anx7625_reg_read(struct anx7625_data *ctx,
79 struct i2c_client *client, u8 reg_addr)
82 struct device *dev = &client->dev;
84 i2c_access_workaround(ctx, client);
86 ret = i2c_smbus_read_byte_data(client, reg_addr);
88 DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n",
89 client->addr, reg_addr);
94 static int anx7625_reg_block_read(struct anx7625_data *ctx,
95 struct i2c_client *client,
96 u8 reg_addr, u8 len, u8 *buf)
99 struct device *dev = &client->dev;
101 i2c_access_workaround(ctx, client);
103 ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf);
105 DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n",
106 client->addr, reg_addr);
111 static int anx7625_reg_write(struct anx7625_data *ctx,
112 struct i2c_client *client,
113 u8 reg_addr, u8 reg_val)
116 struct device *dev = &client->dev;
118 i2c_access_workaround(ctx, client);
120 ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val);
123 DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x",
124 client->addr, reg_addr);
129 static int anx7625_write_or(struct anx7625_data *ctx,
130 struct i2c_client *client,
135 val = anx7625_reg_read(ctx, client, offset);
139 return anx7625_reg_write(ctx, client, offset, (val | (mask)));
142 static int anx7625_write_and(struct anx7625_data *ctx,
143 struct i2c_client *client,
148 val = anx7625_reg_read(ctx, client, offset);
152 return anx7625_reg_write(ctx, client, offset, (val & (mask)));
155 static int anx7625_write_and_or(struct anx7625_data *ctx,
156 struct i2c_client *client,
157 u8 offset, u8 and_mask, u8 or_mask)
161 val = anx7625_reg_read(ctx, client, offset);
165 return anx7625_reg_write(ctx, client,
166 offset, (val & and_mask) | (or_mask));
169 static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx)
171 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS);
174 static int wait_aux_op_finish(struct anx7625_data *ctx)
176 struct device *dev = &ctx->client->dev;
180 ret = readx_poll_timeout(anx7625_read_ctrl_status_p0,
182 (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)),
186 DRM_DEV_ERROR(dev, "aux operation fail!\n");
190 val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
192 if (val < 0 || (val & 0x0F)) {
193 DRM_DEV_ERROR(dev, "aux status %02x\n", val);
200 static int anx7625_video_mute_control(struct anx7625_data *ctx,
206 /* Set mute on flag */
207 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
208 AP_AV_STATUS, AP_MIPI_MUTE);
209 /* Clear mipi RX en */
210 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
211 AP_AV_STATUS, (u8)~AP_MIPI_RX_EN);
214 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
215 AP_AV_STATUS, (u8)~AP_MIPI_MUTE);
217 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
218 AP_AV_STATUS, AP_MIPI_RX_EN);
224 static int anx7625_config_audio_input(struct anx7625_data *ctx)
226 struct device *dev = &ctx->client->dev;
230 ret = anx7625_reg_write(ctx, ctx->i2c.tx_p2_client,
231 AUDIO_CHANNEL_STATUS_6, I2S_CH_2 << 5);
234 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
235 AUDIO_CHANNEL_STATUS_4,
238 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client,
239 AUDIO_CHANNEL_STATUS_5,
240 0xf0, AUDIO_W_LEN_24_24MAX);
242 ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client,
243 AUDIO_CHANNEL_STATUS_6, I2S_SLAVE_MODE);
244 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client,
245 AUDIO_CONTROL_REGISTER, ~TDM_TIMING_MODE);
246 /* Audio change flag */
247 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
248 AP_AV_STATUS, AP_AUDIO_CHG);
251 DRM_DEV_ERROR(dev, "fail to config audio.\n");
256 /* Reduction of fraction a/b */
257 static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b)
259 unsigned long gcd_num;
260 unsigned long tmp_a, tmp_b;
263 gcd_num = gcd(*a, *b);
270 while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) {
277 * In the end, make a, b larger to have higher ODFC PLL
278 * output frequency accuracy
280 while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) {
289 static int anx7625_calculate_m_n(u32 pixelclock,
294 if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) {
295 /* Pixel clock frequency is too high */
296 DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n",
298 PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN);
302 if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) {
303 /* Pixel clock frequency is too low */
304 DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n",
306 PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX);
310 for (*post_divider = 1;
311 pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));)
314 if (*post_divider > POST_DIVIDER_MAX) {
315 for (*post_divider = 1;
317 (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));)
320 if (*post_divider > POST_DIVIDER_MAX) {
321 DRM_ERROR("cannot find property post_divider(%d)\n",
327 /* Patch to improve the accuracy */
328 if (*post_divider == 7) {
329 /* 27,000,000 is not divisible by 7 */
331 } else if (*post_divider == 11) {
332 /* 27,000,000 is not divisible by 11 */
334 } else if ((*post_divider == 13) || (*post_divider == 14)) {
335 /* 27,000,000 is not divisible by 13 or 14 */
339 if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) {
340 DRM_ERROR("act clock(%u) large than maximum(%lu)\n",
341 pixelclock * (*post_divider),
342 PLL_OUT_FREQ_ABS_MAX);
347 *n = XTAL_FRQ / (*post_divider);
349 anx7625_reduction_of_a_fraction(m, n);
354 static int anx7625_odfc_config(struct anx7625_data *ctx,
358 struct device *dev = &ctx->client->dev;
360 /* Config input reference clock frequency 27MHz/19.2MHz */
361 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16,
362 ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND));
363 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16,
364 (REF_CLK_27000KHZ << MIPI_FREF_D_IND));
366 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client,
367 MIPI_DIGITAL_PLL_8, 0x0f);
368 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8,
371 /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */
372 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
373 ~MIPI_PLL_VCO_TUNE_REG_VAL);
376 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
378 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7,
382 DRM_DEV_ERROR(dev, "IO error.\n");
387 static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx)
389 struct device *dev = &ctx->client->dev;
395 ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000,
396 &m, &n, &post_divider);
399 DRM_DEV_ERROR(dev, "cannot get property m n value.\n");
403 DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n",
406 /* Configure pixel clock */
407 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L,
408 (ctx->dt.pixelclock.min / 1000) & 0xFF);
409 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H,
410 (ctx->dt.pixelclock.min / 1000) >> 8);
412 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client,
413 MIPI_LANE_CTRL_0, 0xfc);
414 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client,
415 MIPI_LANE_CTRL_0, 3);
418 htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min +
419 ctx->dt.hback_porch.min + ctx->dt.hsync_len.min;
420 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
421 HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF);
422 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
423 HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8);
425 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
426 HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF);
427 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
428 HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8);
430 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
431 HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min);
432 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
433 HORIZONTAL_FRONT_PORCH_H,
434 ctx->dt.hfront_porch.min >> 8);
436 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
437 HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min);
438 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
439 HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8);
441 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
442 HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min);
443 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
444 HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8);
446 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L,
447 ctx->dt.vactive.min);
448 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H,
449 ctx->dt.vactive.min >> 8);
451 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
452 VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min);
454 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
455 VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min);
457 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client,
458 VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min);
460 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
461 MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff);
462 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
463 MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff);
464 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
465 MIPI_PLL_M_NUM_7_0, (m & 0xff));
467 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
468 MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff);
469 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
470 MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff);
471 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0,
474 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
475 MIPI_DIGITAL_ADJ_1, 0x3D);
477 ret |= anx7625_odfc_config(ctx, post_divider - 1);
480 DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n");
485 static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx)
488 struct device *dev = &ctx->client->dev;
490 /* Swap MIPI-DSI data lane 3 P and N */
491 val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP);
493 DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n");
497 val |= (1 << MIPI_SWAP_CH3);
498 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val);
501 static int anx7625_api_dsi_config(struct anx7625_data *ctx)
505 struct device *dev = &ctx->client->dev;
507 /* Swap MIPI-DSI data lane 3 P and N */
508 ret = anx7625_swap_dsi_lane3(ctx);
510 DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n");
514 /* DSI clock settings */
515 val = (0 << MIPI_HS_PWD_CLK) |
516 (0 << MIPI_HS_RT_CLK) |
518 (1 << MIPI_CLK_RT_MANUAL_PD_EN) |
519 (1 << MIPI_CLK_HS_MANUAL_PD_EN) |
520 (0 << MIPI_CLK_DET_DET_BYPASS) |
521 (0 << MIPI_CLK_MISS_CTRL) |
522 (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN);
523 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
524 MIPI_PHY_CONTROL_3, val);
527 * Decreased HS prepare timing delay from 160ns to 80ns work with
528 * a) Dragon board 810 series (Qualcomm AP)
529 * b) Moving Pixel DSI source (PG3A pattern generator +
530 * P332 D-PHY Probe) default D-PHY timing
533 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
534 MIPI_TIME_HS_PRPR, 0x10);
537 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18,
538 SELECT_DSI << MIPI_DPI_SELECT);
540 ret |= anx7625_dsi_video_timing_config(ctx);
542 DRM_DEV_ERROR(dev, "dsi video timing config fail\n");
546 /* Toggle m, n ready */
547 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6,
548 ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY));
549 usleep_range(1000, 1100);
550 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6,
551 MIPI_M_NUM_READY | MIPI_N_NUM_READY);
553 /* Configure integer stable register */
554 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
555 MIPI_VIDEO_STABLE_CNT, 0x02);
556 /* Power on MIPI RX */
557 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
558 MIPI_LANE_CTRL_10, 0x00);
559 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client,
560 MIPI_LANE_CTRL_10, 0x80);
563 DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n");
568 static int anx7625_dsi_config(struct anx7625_data *ctx)
570 struct device *dev = &ctx->client->dev;
573 DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n");
576 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
577 R_DSC_CTRL_0, ~DSC_EN);
579 ret |= anx7625_api_dsi_config(ctx);
582 DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n");
587 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
588 AP_AV_STATUS, AP_MIPI_RX_EN);
589 /* Clear mute flag */
590 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
591 AP_AV_STATUS, (u8)~AP_MIPI_MUTE);
593 DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n");
595 DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n");
600 static void anx7625_dp_start(struct anx7625_data *ctx)
603 struct device *dev = &ctx->client->dev;
605 if (!ctx->display_timing_valid) {
606 DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n");
610 anx7625_config_audio_input(ctx);
612 ret = anx7625_dsi_config(ctx);
615 DRM_DEV_ERROR(dev, "MIPI phy setup error.\n");
618 static void anx7625_dp_stop(struct anx7625_data *ctx)
620 struct device *dev = &ctx->client->dev;
623 DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n");
626 * Video disable: 0x72:08 bit 7 = 0;
627 * Audio disable: 0x70:87 bit 0 = 0;
629 ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe);
630 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f);
632 ret |= anx7625_video_mute_control(ctx, 1);
634 DRM_DEV_ERROR(dev, "IO error : mute video fail\n");
637 static int sp_tx_rst_aux(struct anx7625_data *ctx)
641 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2,
643 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2,
648 static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset)
652 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
653 AP_AUX_BUFF_START, offset);
654 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
655 AP_AUX_COMMAND, 0x04);
656 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
657 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
658 return (ret | wait_aux_op_finish(ctx));
661 static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd)
665 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
666 AP_AUX_COMMAND, len_cmd);
667 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client,
668 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN);
669 return (ret | wait_aux_op_finish(ctx));
672 static int sp_tx_get_edid_block(struct anx7625_data *ctx)
675 struct device *dev = &ctx->client->dev;
677 sp_tx_aux_wr(ctx, 0x7e);
678 sp_tx_aux_rd(ctx, 0x01);
679 c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START);
681 DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n");
685 DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1);
687 if (c > MAX_EDID_BLOCK)
693 static int edid_read(struct anx7625_data *ctx,
694 u8 offset, u8 *pblock_buf)
697 struct device *dev = &ctx->client->dev;
699 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) {
700 sp_tx_aux_wr(ctx, offset);
701 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */
702 ret = sp_tx_aux_rd(ctx, 0xf1);
706 DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n");
708 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
710 MAX_DPCD_BUFFER_SIZE,
717 if (cnt > EDID_TRY_CNT)
723 static int segments_edid_read(struct anx7625_data *ctx,
724 u8 segment, u8 *buf, u8 offset)
728 struct device *dev = &ctx->client->dev;
730 /* Write address only */
731 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
732 AP_AUX_ADDR_7_0, 0x30);
733 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
734 AP_AUX_COMMAND, 0x04);
735 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
737 AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN);
739 ret |= wait_aux_op_finish(ctx);
740 /* Write segment address */
741 ret |= sp_tx_aux_wr(ctx, segment);
743 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
744 AP_AUX_ADDR_7_0, 0x50);
746 DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n");
750 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) {
751 sp_tx_aux_wr(ctx, offset);
752 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */
753 ret = sp_tx_aux_rd(ctx, 0xf1);
756 ret = sp_tx_rst_aux(ctx);
757 DRM_DEV_ERROR(dev, "segment read fail, reset!\n");
759 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client,
761 MAX_DPCD_BUFFER_SIZE, buf);
767 if (cnt > EDID_TRY_CNT)
773 static int sp_tx_edid_read(struct anx7625_data *ctx,
774 u8 *pedid_blocks_buf)
777 int count, blocks_num;
778 u8 pblock_buf[MAX_DPCD_BUFFER_SIZE];
782 struct device *dev = &ctx->client->dev;
784 /* Address initial */
785 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
786 AP_AUX_ADDR_7_0, 0x50);
787 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
788 AP_AUX_ADDR_15_8, 0);
789 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client,
790 AP_AUX_ADDR_19_16, 0xf0);
792 DRM_DEV_ERROR(dev, "access aux channel IO error.\n");
796 blocks_num = sp_tx_get_edid_block(ctx);
806 for (i = 0; i < 8; i++) {
807 offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE;
808 g_edid_break = edid_read(ctx, offset,
814 memcpy(&pedid_blocks_buf[offset],
816 MAX_DPCD_BUFFER_SIZE);
823 for (j = 0; j < 8; j++) {
824 edid_pos = (j + count * 8) *
825 MAX_DPCD_BUFFER_SIZE;
827 if (g_edid_break == 1)
830 segments_edid_read(ctx, count / 2,
832 memcpy(&pedid_blocks_buf[edid_pos],
834 MAX_DPCD_BUFFER_SIZE);
835 offset = offset + 0x10;
842 for (j = 0; j < 8; j++) {
843 edid_pos = (j + count * 8) *
844 MAX_DPCD_BUFFER_SIZE;
845 if (g_edid_break == 1)
848 segments_edid_read(ctx, count / 2,
850 memcpy(&pedid_blocks_buf[edid_pos],
852 MAX_DPCD_BUFFER_SIZE);
853 offset = offset + 0x10;
863 } while (blocks_num >= count);
865 /* Check edid data */
866 if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) {
867 DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n");
871 /* Reset aux channel */
874 return (blocks_num + 1);
877 static void anx7625_power_on(struct anx7625_data *ctx)
879 struct device *dev = &ctx->client->dev;
882 if (!ctx->pdata.low_power_mode) {
883 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n");
887 for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) {
888 ret = regulator_enable(ctx->pdata.supplies[i].consumer);
890 DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n",
894 usleep_range(2000, 2100);
897 usleep_range(11000, 12000);
899 /* Power on pin enable */
900 gpiod_set_value(ctx->pdata.gpio_p_on, 1);
901 usleep_range(10000, 11000);
902 /* Power reset pin enable */
903 gpiod_set_value(ctx->pdata.gpio_reset, 1);
904 usleep_range(10000, 11000);
906 DRM_DEV_DEBUG_DRIVER(dev, "power on !\n");
909 for (--i; i >= 0; i--)
910 regulator_disable(ctx->pdata.supplies[i].consumer);
913 static void anx7625_power_standby(struct anx7625_data *ctx)
915 struct device *dev = &ctx->client->dev;
918 if (!ctx->pdata.low_power_mode) {
919 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n");
923 gpiod_set_value(ctx->pdata.gpio_reset, 0);
924 usleep_range(1000, 1100);
925 gpiod_set_value(ctx->pdata.gpio_p_on, 0);
926 usleep_range(1000, 1100);
928 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies),
929 ctx->pdata.supplies);
931 DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret);
933 DRM_DEV_DEBUG_DRIVER(dev, "power down\n");
936 /* Basic configurations of ANX7625 */
937 static void anx7625_config(struct anx7625_data *ctx)
939 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
940 XTAL_FRQ_SEL, XTAL_FRQ_27M);
943 static void anx7625_disable_pd_protocol(struct anx7625_data *ctx)
945 struct device *dev = &ctx->client->dev;
949 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40);
951 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
952 AP_AV_STATUS, AP_DISABLE_PD);
953 /* Release main ocm */
954 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00);
957 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n");
959 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n");
962 static int anx7625_ocm_loading_check(struct anx7625_data *ctx)
965 struct device *dev = &ctx->client->dev;
967 /* Check interface workable */
968 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
971 DRM_DEV_ERROR(dev, "IO error : access flash load.\n");
974 if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK)
977 anx7625_disable_pd_protocol(ctx);
979 DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,",
980 anx7625_reg_read(ctx,
981 ctx->i2c.rx_p0_client,
983 anx7625_reg_read(ctx,
984 ctx->i2c.rx_p0_client,
986 DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n",
987 ANX7625_DRV_VERSION);
992 static void anx7625_power_on_init(struct anx7625_data *ctx)
996 for (retry_count = 0; retry_count < 3; retry_count++) {
997 anx7625_power_on(ctx);
1000 for (i = 0; i < OCM_LOADING_TIME; i++) {
1001 if (!anx7625_ocm_loading_check(ctx))
1003 usleep_range(1000, 1100);
1005 anx7625_power_standby(ctx);
1009 static void anx7625_init_gpio(struct anx7625_data *platform)
1011 struct device *dev = &platform->client->dev;
1013 DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n");
1015 /* Gpio for chip power enable */
1016 platform->pdata.gpio_p_on =
1017 devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW);
1018 /* Gpio for chip reset */
1019 platform->pdata.gpio_reset =
1020 devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1022 if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) {
1023 platform->pdata.low_power_mode = 1;
1024 DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n",
1025 desc_to_gpio(platform->pdata.gpio_p_on),
1026 desc_to_gpio(platform->pdata.gpio_reset));
1028 platform->pdata.low_power_mode = 0;
1029 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n");
1033 static void anx7625_stop_dp_work(struct anx7625_data *ctx)
1035 ctx->hpd_status = 0;
1036 ctx->hpd_high_cnt = 0;
1037 ctx->display_timing_valid = 0;
1040 static void anx7625_start_dp_work(struct anx7625_data *ctx)
1043 struct device *dev = &ctx->client->dev;
1045 if (ctx->hpd_high_cnt >= 2) {
1046 DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n");
1050 ctx->hpd_high_cnt++;
1052 /* Not support HDCP */
1053 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f);
1056 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10);
1057 /* Interrupt for DRM */
1058 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01);
1062 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86);
1066 DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret);
1069 static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx)
1071 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS);
1074 static void anx7625_hpd_polling(struct anx7625_data *ctx)
1077 struct device *dev = &ctx->client->dev;
1079 ret = readx_poll_timeout(anx7625_read_hpd_status_p0,
1081 ((val & HPD_STATUS) || (val < 0)),
1085 DRM_DEV_ERROR(dev, "no hpd.\n");
1089 DRM_DEV_DEBUG_DRIVER(dev, "system status: 0x%x. HPD raise up.\n", val);
1090 anx7625_reg_write(ctx, ctx->i2c.tcpc_client,
1091 INTR_ALERT_1, 0xFF);
1092 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1093 INTERFACE_CHANGE_INT, 0);
1095 anx7625_start_dp_work(ctx);
1097 if (!ctx->pdata.panel_bridge && ctx->bridge_attached)
1098 drm_helper_hpd_irq_event(ctx->bridge.dev);
1101 static void anx7625_remove_edid(struct anx7625_data *ctx)
1103 ctx->slimport_edid_p.edid_block_num = -1;
1106 static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on)
1108 struct device *dev = &ctx->client->dev;
1111 DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n",
1115 DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n");
1116 anx7625_remove_edid(ctx);
1117 anx7625_stop_dp_work(ctx);
1119 DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n");
1120 anx7625_start_dp_work(ctx);
1123 ctx->hpd_status = 1;
1126 static int anx7625_hpd_change_detect(struct anx7625_data *ctx)
1128 int intr_vector, status;
1129 struct device *dev = &ctx->client->dev;
1131 status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client,
1132 INTR_ALERT_1, 0xFF);
1134 DRM_DEV_ERROR(dev, "cannot clear alert reg.\n");
1138 intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
1139 INTERFACE_CHANGE_INT);
1140 if (intr_vector < 0) {
1141 DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n");
1144 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector);
1145 status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client,
1146 INTERFACE_CHANGE_INT,
1147 intr_vector & (~intr_vector));
1149 DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n");
1153 if (!(intr_vector & HPD_STATUS_CHANGE))
1156 status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client,
1159 DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n");
1163 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status);
1164 dp_hpd_change_handler(ctx, status & HPD_STATUS);
1169 static void anx7625_work_func(struct work_struct *work)
1172 struct anx7625_data *ctx = container_of(work,
1173 struct anx7625_data, work);
1175 mutex_lock(&ctx->lock);
1177 if (pm_runtime_suspended(&ctx->client->dev))
1180 event = anx7625_hpd_change_detect(ctx);
1184 if (ctx->bridge_attached)
1185 drm_helper_hpd_irq_event(ctx->bridge.dev);
1188 mutex_unlock(&ctx->lock);
1191 static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data)
1193 struct anx7625_data *ctx = (struct anx7625_data *)data;
1195 queue_work(ctx->workqueue, &ctx->work);
1200 static int anx7625_parse_dt(struct device *dev,
1201 struct anx7625_platform_data *pdata)
1203 struct device_node *np = dev->of_node;
1204 struct drm_panel *panel;
1207 pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0);
1208 if (!pdata->mipi_host_node) {
1209 DRM_DEV_ERROR(dev, "fail to get internal panel.\n");
1213 DRM_DEV_DEBUG_DRIVER(dev, "found dsi host node.\n");
1215 ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL);
1224 pdata->panel_bridge = devm_drm_panel_bridge_add(dev, panel);
1225 if (IS_ERR(pdata->panel_bridge))
1226 return PTR_ERR(pdata->panel_bridge);
1227 DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n");
1232 static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge)
1234 return container_of(bridge, struct anx7625_data, bridge);
1237 static struct edid *anx7625_get_edid(struct anx7625_data *ctx)
1239 struct device *dev = &ctx->client->dev;
1240 struct s_edid_data *p_edid = &ctx->slimport_edid_p;
1244 edid = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL);
1246 DRM_DEV_ERROR(dev, "Fail to allocate buffer\n");
1250 if (ctx->slimport_edid_p.edid_block_num > 0) {
1251 memcpy(edid, ctx->slimport_edid_p.edid_raw_data,
1253 return (struct edid *)edid;
1256 pm_runtime_get_sync(dev);
1257 edid_num = sp_tx_edid_read(ctx, p_edid->edid_raw_data);
1258 pm_runtime_put_sync(dev);
1261 DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num);
1266 p_edid->edid_block_num = edid_num;
1268 memcpy(edid, ctx->slimport_edid_p.edid_raw_data, FOUR_BLOCK_SIZE);
1269 return (struct edid *)edid;
1272 static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx)
1274 struct device *dev = &ctx->client->dev;
1276 DRM_DEV_DEBUG_DRIVER(dev, "sink detect, return connected\n");
1278 return connector_status_connected;
1281 static int anx7625_attach_dsi(struct anx7625_data *ctx)
1283 struct mipi_dsi_device *dsi;
1284 struct device *dev = &ctx->client->dev;
1285 struct mipi_dsi_host *host;
1286 const struct mipi_dsi_device_info info = {
1292 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n");
1294 host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node);
1296 DRM_DEV_ERROR(dev, "fail to find dsi host.\n");
1300 dsi = mipi_dsi_device_register_full(host, &info);
1302 DRM_DEV_ERROR(dev, "fail to create dsi device.\n");
1307 dsi->format = MIPI_DSI_FMT_RGB888;
1308 dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
1309 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
1310 MIPI_DSI_MODE_NO_EOT_PACKET |
1311 MIPI_DSI_MODE_VIDEO_HSE;
1313 if (mipi_dsi_attach(dsi) < 0) {
1314 DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n");
1315 mipi_dsi_device_unregister(dsi);
1321 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n");
1326 static void anx7625_bridge_detach(struct drm_bridge *bridge)
1328 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
1331 mipi_dsi_detach(ctx->dsi);
1332 mipi_dsi_device_unregister(ctx->dsi);
1336 static int anx7625_bridge_attach(struct drm_bridge *bridge,
1337 enum drm_bridge_attach_flags flags)
1339 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
1341 struct device *dev = &ctx->client->dev;
1343 DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n");
1344 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
1347 if (!bridge->encoder) {
1348 DRM_DEV_ERROR(dev, "Parent encoder object not found");
1352 err = anx7625_attach_dsi(ctx);
1354 DRM_DEV_ERROR(dev, "Fail to attach to dsi : %d\n", err);
1358 if (ctx->pdata.panel_bridge) {
1359 err = drm_bridge_attach(bridge->encoder,
1360 ctx->pdata.panel_bridge,
1361 &ctx->bridge, flags);
1366 ctx->bridge_attached = 1;
1371 static enum drm_mode_status
1372 anx7625_bridge_mode_valid(struct drm_bridge *bridge,
1373 const struct drm_display_info *info,
1374 const struct drm_display_mode *mode)
1376 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
1377 struct device *dev = &ctx->client->dev;
1379 DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n");
1381 /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */
1382 if (mode->clock > SUPPORT_PIXEL_CLOCK) {
1383 DRM_DEV_DEBUG_DRIVER(dev,
1384 "drm mode invalid, pixelclock too high.\n");
1385 return MODE_CLOCK_HIGH;
1388 DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n");
1393 static void anx7625_bridge_mode_set(struct drm_bridge *bridge,
1394 const struct drm_display_mode *old_mode,
1395 const struct drm_display_mode *mode)
1397 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
1398 struct device *dev = &ctx->client->dev;
1400 DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n");
1402 ctx->dt.pixelclock.min = mode->clock;
1403 ctx->dt.hactive.min = mode->hdisplay;
1404 ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start;
1405 ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay;
1406 ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end;
1407 ctx->dt.vactive.min = mode->vdisplay;
1408 ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start;
1409 ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay;
1410 ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end;
1412 ctx->display_timing_valid = 1;
1414 DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min);
1415 DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n",
1416 ctx->dt.hactive.min,
1417 ctx->dt.hsync_len.min,
1418 ctx->dt.hfront_porch.min,
1419 ctx->dt.hback_porch.min);
1420 DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n",
1421 ctx->dt.vactive.min,
1422 ctx->dt.vsync_len.min,
1423 ctx->dt.vfront_porch.min,
1424 ctx->dt.vback_porch.min);
1425 DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n",
1428 DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n",
1431 DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n",
1434 DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n",
1439 static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge,
1440 const struct drm_display_mode *mode,
1441 struct drm_display_mode *adj)
1443 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
1444 struct device *dev = &ctx->client->dev;
1445 u32 hsync, hfp, hbp, hblanking;
1446 u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj;
1447 u32 vref, adj_clock;
1449 DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n");
1451 hsync = mode->hsync_end - mode->hsync_start;
1452 hfp = mode->hsync_start - mode->hdisplay;
1453 hbp = mode->htotal - mode->hsync_end;
1454 hblanking = mode->htotal - mode->hdisplay;
1456 DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n");
1457 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n",
1458 hsync, hfp, hbp, adj->clock);
1459 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n",
1460 adj->hsync_start, adj->hsync_end, adj->htotal);
1465 adj_hblanking = hblanking;
1467 /* HFP needs to be even */
1473 /* HBP needs to be even */
1479 /* HSYNC needs to be even */
1481 if (adj_hblanking < hblanking)
1488 * Once illegal timing detected, use default HFP, HSYNC, HBP
1489 * This adjusting made for built-in eDP panel, for the externel
1490 * DP monitor, may need return false.
1492 if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) {
1493 adj_hsync = SYNC_LEN_DEF;
1494 adj_hfp = HFP_HBP_DEF;
1495 adj_hbp = HFP_HBP_DEF;
1496 vref = adj->clock * 1000 / (adj->htotal * adj->vtotal);
1497 if (hblanking < HBLANKING_MIN) {
1498 delta_adj = HBLANKING_MIN - hblanking;
1499 adj_clock = vref * delta_adj * adj->vtotal;
1500 adj->clock += DIV_ROUND_UP(adj_clock, 1000);
1502 delta_adj = hblanking - HBLANKING_MIN;
1503 adj_clock = vref * delta_adj * adj->vtotal;
1504 adj->clock -= DIV_ROUND_UP(adj_clock, 1000);
1507 DRM_WARN("illegal hblanking timing, use default.\n");
1508 DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync);
1509 } else if (adj_hfp < HP_MIN) {
1510 /* Adjust hfp if hfp less than HP_MIN */
1511 delta_adj = HP_MIN - adj_hfp;
1515 * Balance total HBlanking pixel, if HBP does not have enough
1516 * space, adjust HSYNC length, otherwise adjust HBP
1518 if ((adj_hbp - delta_adj) < HP_MIN)
1519 /* HBP not enough space */
1520 adj_hsync -= delta_adj;
1522 adj_hbp -= delta_adj;
1523 } else if (adj_hbp < HP_MIN) {
1524 delta_adj = HP_MIN - adj_hbp;
1528 * Balance total HBlanking pixel, if HBP hasn't enough space,
1529 * adjust HSYNC length, otherwize adjust HBP
1531 if ((adj_hfp - delta_adj) < HP_MIN)
1532 /* HFP not enough space */
1533 adj_hsync -= delta_adj;
1535 adj_hfp -= delta_adj;
1538 DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n");
1539 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n",
1540 adj_hsync, adj_hfp, adj_hbp, adj->clock);
1542 /* Reconstruct timing */
1543 adj->hsync_start = adj->hdisplay + adj_hfp;
1544 adj->hsync_end = adj->hsync_start + adj_hsync;
1545 adj->htotal = adj->hsync_end + adj_hbp;
1546 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n",
1547 adj->hsync_start, adj->hsync_end, adj->htotal);
1552 static void anx7625_bridge_enable(struct drm_bridge *bridge)
1554 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
1555 struct device *dev = &ctx->client->dev;
1557 DRM_DEV_DEBUG_DRIVER(dev, "drm enable\n");
1559 pm_runtime_get_sync(dev);
1561 anx7625_dp_start(ctx);
1564 static void anx7625_bridge_disable(struct drm_bridge *bridge)
1566 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
1567 struct device *dev = &ctx->client->dev;
1569 DRM_DEV_DEBUG_DRIVER(dev, "drm disable\n");
1571 anx7625_dp_stop(ctx);
1573 pm_runtime_put_sync(dev);
1576 static enum drm_connector_status
1577 anx7625_bridge_detect(struct drm_bridge *bridge)
1579 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
1580 struct device *dev = &ctx->client->dev;
1582 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n");
1584 return anx7625_sink_detect(ctx);
1587 static struct edid *anx7625_bridge_get_edid(struct drm_bridge *bridge,
1588 struct drm_connector *connector)
1590 struct anx7625_data *ctx = bridge_to_anx7625(bridge);
1591 struct device *dev = &ctx->client->dev;
1593 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n");
1595 return anx7625_get_edid(ctx);
1598 static const struct drm_bridge_funcs anx7625_bridge_funcs = {
1599 .attach = anx7625_bridge_attach,
1600 .detach = anx7625_bridge_detach,
1601 .disable = anx7625_bridge_disable,
1602 .mode_valid = anx7625_bridge_mode_valid,
1603 .mode_set = anx7625_bridge_mode_set,
1604 .mode_fixup = anx7625_bridge_mode_fixup,
1605 .enable = anx7625_bridge_enable,
1606 .detect = anx7625_bridge_detect,
1607 .get_edid = anx7625_bridge_get_edid,
1610 static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx,
1611 struct i2c_client *client)
1613 ctx->i2c.tx_p0_client = i2c_new_dummy_device(client->adapter,
1615 if (!ctx->i2c.tx_p0_client)
1618 ctx->i2c.tx_p1_client = i2c_new_dummy_device(client->adapter,
1620 if (!ctx->i2c.tx_p1_client)
1623 ctx->i2c.tx_p2_client = i2c_new_dummy_device(client->adapter,
1625 if (!ctx->i2c.tx_p2_client)
1628 ctx->i2c.rx_p0_client = i2c_new_dummy_device(client->adapter,
1630 if (!ctx->i2c.rx_p0_client)
1633 ctx->i2c.rx_p1_client = i2c_new_dummy_device(client->adapter,
1635 if (!ctx->i2c.rx_p1_client)
1638 ctx->i2c.rx_p2_client = i2c_new_dummy_device(client->adapter,
1640 if (!ctx->i2c.rx_p2_client)
1643 ctx->i2c.tcpc_client = i2c_new_dummy_device(client->adapter,
1644 TCPC_INTERFACE_ADDR >> 1);
1645 if (!ctx->i2c.tcpc_client)
1651 i2c_unregister_device(ctx->i2c.rx_p2_client);
1653 i2c_unregister_device(ctx->i2c.rx_p1_client);
1655 i2c_unregister_device(ctx->i2c.rx_p0_client);
1657 i2c_unregister_device(ctx->i2c.tx_p2_client);
1659 i2c_unregister_device(ctx->i2c.tx_p1_client);
1661 i2c_unregister_device(ctx->i2c.tx_p0_client);
1666 static void anx7625_unregister_i2c_dummy_clients(struct anx7625_data *ctx)
1668 i2c_unregister_device(ctx->i2c.tx_p0_client);
1669 i2c_unregister_device(ctx->i2c.tx_p1_client);
1670 i2c_unregister_device(ctx->i2c.tx_p2_client);
1671 i2c_unregister_device(ctx->i2c.rx_p0_client);
1672 i2c_unregister_device(ctx->i2c.rx_p1_client);
1673 i2c_unregister_device(ctx->i2c.rx_p2_client);
1674 i2c_unregister_device(ctx->i2c.tcpc_client);
1677 static int __maybe_unused anx7625_runtime_pm_suspend(struct device *dev)
1679 struct anx7625_data *ctx = dev_get_drvdata(dev);
1681 mutex_lock(&ctx->lock);
1683 anx7625_stop_dp_work(ctx);
1684 anx7625_power_standby(ctx);
1686 mutex_unlock(&ctx->lock);
1691 static int __maybe_unused anx7625_runtime_pm_resume(struct device *dev)
1693 struct anx7625_data *ctx = dev_get_drvdata(dev);
1695 mutex_lock(&ctx->lock);
1697 anx7625_power_on_init(ctx);
1698 anx7625_hpd_polling(ctx);
1700 mutex_unlock(&ctx->lock);
1705 static int __maybe_unused anx7625_resume(struct device *dev)
1707 struct anx7625_data *ctx = dev_get_drvdata(dev);
1709 if (!ctx->pdata.intp_irq)
1712 if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) {
1713 enable_irq(ctx->pdata.intp_irq);
1714 anx7625_runtime_pm_resume(dev);
1720 static int __maybe_unused anx7625_suspend(struct device *dev)
1722 struct anx7625_data *ctx = dev_get_drvdata(dev);
1724 if (!ctx->pdata.intp_irq)
1727 if (!pm_runtime_enabled(dev) || !pm_runtime_suspended(dev)) {
1728 anx7625_runtime_pm_suspend(dev);
1729 disable_irq(ctx->pdata.intp_irq);
1735 static const struct dev_pm_ops anx7625_pm_ops = {
1736 SET_SYSTEM_SLEEP_PM_OPS(anx7625_suspend, anx7625_resume)
1737 SET_RUNTIME_PM_OPS(anx7625_runtime_pm_suspend,
1738 anx7625_runtime_pm_resume, NULL)
1741 static int anx7625_i2c_probe(struct i2c_client *client,
1742 const struct i2c_device_id *id)
1744 struct anx7625_data *platform;
1745 struct anx7625_platform_data *pdata;
1747 struct device *dev = &client->dev;
1749 if (!i2c_check_functionality(client->adapter,
1750 I2C_FUNC_SMBUS_I2C_BLOCK)) {
1751 DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n");
1755 platform = kzalloc(sizeof(*platform), GFP_KERNEL);
1757 DRM_DEV_ERROR(dev, "fail to allocate driver data\n");
1761 pdata = &platform->pdata;
1763 ret = anx7625_parse_dt(dev, pdata);
1765 if (ret != -EPROBE_DEFER)
1766 DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret);
1770 platform->client = client;
1771 i2c_set_clientdata(client, platform);
1773 pdata->supplies[0].supply = "vdd10";
1774 pdata->supplies[1].supply = "vdd18";
1775 pdata->supplies[2].supply = "vdd33";
1776 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies),
1779 DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret);
1782 anx7625_init_gpio(platform);
1784 mutex_init(&platform->lock);
1786 platform->pdata.intp_irq = client->irq;
1787 if (platform->pdata.intp_irq) {
1788 INIT_WORK(&platform->work, anx7625_work_func);
1789 platform->workqueue = alloc_workqueue("anx7625_work",
1790 WQ_FREEZABLE | WQ_MEM_RECLAIM, 1);
1791 if (!platform->workqueue) {
1792 DRM_DEV_ERROR(dev, "fail to create work queue\n");
1797 ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq,
1798 NULL, anx7625_intr_hpd_isr,
1799 IRQF_TRIGGER_FALLING |
1801 "anx7625-intp", platform);
1803 DRM_DEV_ERROR(dev, "fail to request irq\n");
1808 if (anx7625_register_i2c_dummy_clients(platform, client) != 0) {
1810 DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n");
1814 pm_runtime_enable(dev);
1816 if (!platform->pdata.low_power_mode) {
1817 anx7625_disable_pd_protocol(platform);
1818 pm_runtime_get_sync(dev);
1821 /* Add work function */
1822 if (platform->pdata.intp_irq)
1823 queue_work(platform->workqueue, &platform->work);
1825 platform->bridge.funcs = &anx7625_bridge_funcs;
1826 platform->bridge.of_node = client->dev.of_node;
1827 platform->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_HPD;
1828 platform->bridge.type = DRM_MODE_CONNECTOR_eDP;
1829 drm_bridge_add(&platform->bridge);
1831 DRM_DEV_DEBUG_DRIVER(dev, "probe done\n");
1836 if (platform->workqueue)
1837 destroy_workqueue(platform->workqueue);
1845 static int anx7625_i2c_remove(struct i2c_client *client)
1847 struct anx7625_data *platform = i2c_get_clientdata(client);
1849 drm_bridge_remove(&platform->bridge);
1851 if (platform->pdata.intp_irq)
1852 destroy_workqueue(platform->workqueue);
1854 if (!platform->pdata.low_power_mode)
1855 pm_runtime_put_sync_suspend(&client->dev);
1857 anx7625_unregister_i2c_dummy_clients(platform);
1863 static const struct i2c_device_id anx7625_id[] = {
1868 MODULE_DEVICE_TABLE(i2c, anx7625_id);
1870 static const struct of_device_id anx_match_table[] = {
1871 {.compatible = "analogix,anx7625",},
1874 MODULE_DEVICE_TABLE(of, anx_match_table);
1876 static struct i2c_driver anx7625_driver = {
1879 .of_match_table = anx_match_table,
1880 .pm = &anx7625_pm_ops,
1882 .probe = anx7625_i2c_probe,
1883 .remove = anx7625_i2c_remove,
1885 .id_table = anx7625_id,
1888 module_i2c_driver(anx7625_driver);
1890 MODULE_DESCRIPTION("MIPI2DP anx7625 driver");
1891 MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>");
1892 MODULE_LICENSE("GPL v2");
1893 MODULE_VERSION(ANX7625_DRV_VERSION);