2 * Copyright 2012 Red Hat Inc.
3 * Parts based on xf86-video-ast
4 * Copyright (c) 2005 ASPEED Technology Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
28 * Authors: Dave Airlie <airlied@redhat.com>
31 #include <linux/export.h>
32 #include <linux/pci.h>
34 #include <drm/drm_atomic.h>
35 #include <drm/drm_atomic_helper.h>
36 #include <drm/drm_atomic_state_helper.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_crtc_helper.h>
39 #include <drm/drm_fourcc.h>
40 #include <drm/drm_gem_atomic_helper.h>
41 #include <drm/drm_gem_framebuffer_helper.h>
42 #include <drm/drm_gem_vram_helper.h>
43 #include <drm/drm_plane_helper.h>
44 #include <drm/drm_probe_helper.h>
45 #include <drm/drm_simple_kms_helper.h>
48 #include "ast_tables.h"
50 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev);
51 static void ast_i2c_destroy(struct ast_i2c_chan *i2c);
53 static inline void ast_load_palette_index(struct ast_private *ast,
54 u8 index, u8 red, u8 green,
57 ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index);
58 ast_io_read8(ast, AST_IO_SEQ_PORT);
59 ast_io_write8(ast, AST_IO_DAC_DATA, red);
60 ast_io_read8(ast, AST_IO_SEQ_PORT);
61 ast_io_write8(ast, AST_IO_DAC_DATA, green);
62 ast_io_read8(ast, AST_IO_SEQ_PORT);
63 ast_io_write8(ast, AST_IO_DAC_DATA, blue);
64 ast_io_read8(ast, AST_IO_SEQ_PORT);
67 static void ast_crtc_load_lut(struct ast_private *ast, struct drm_crtc *crtc)
75 r = crtc->gamma_store;
76 g = r + crtc->gamma_size;
77 b = g + crtc->gamma_size;
79 for (i = 0; i < 256; i++)
80 ast_load_palette_index(ast, i, *r++ >> 8, *g++ >> 8, *b++ >> 8);
83 static bool ast_get_vbios_mode_info(const struct drm_format_info *format,
84 const struct drm_display_mode *mode,
85 struct drm_display_mode *adjusted_mode,
86 struct ast_vbios_mode_info *vbios_mode)
88 u32 refresh_rate_index = 0, refresh_rate;
89 const struct ast_vbios_enhtable *best = NULL;
93 switch (format->cpp[0] * 8) {
95 vbios_mode->std_table = &vbios_stdtable[VGAModeIndex];
98 vbios_mode->std_table = &vbios_stdtable[HiCModeIndex];
102 vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex];
108 switch (mode->crtc_hdisplay) {
110 vbios_mode->enh_table = &res_640x480[refresh_rate_index];
113 vbios_mode->enh_table = &res_800x600[refresh_rate_index];
116 vbios_mode->enh_table = &res_1024x768[refresh_rate_index];
119 if (mode->crtc_vdisplay == 800)
120 vbios_mode->enh_table = &res_1280x800[refresh_rate_index];
122 vbios_mode->enh_table = &res_1280x1024[refresh_rate_index];
125 vbios_mode->enh_table = &res_1360x768[refresh_rate_index];
128 vbios_mode->enh_table = &res_1440x900[refresh_rate_index];
131 if (mode->crtc_vdisplay == 900)
132 vbios_mode->enh_table = &res_1600x900[refresh_rate_index];
134 vbios_mode->enh_table = &res_1600x1200[refresh_rate_index];
137 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index];
140 if (mode->crtc_vdisplay == 1080)
141 vbios_mode->enh_table = &res_1920x1080[refresh_rate_index];
143 vbios_mode->enh_table = &res_1920x1200[refresh_rate_index];
149 refresh_rate = drm_mode_vrefresh(mode);
150 check_sync = vbios_mode->enh_table->flags & WideScreenMode;
153 const struct ast_vbios_enhtable *loop = vbios_mode->enh_table;
155 while (loop->refresh_rate != 0xff) {
157 (((mode->flags & DRM_MODE_FLAG_NVSYNC) &&
158 (loop->flags & PVSync)) ||
159 ((mode->flags & DRM_MODE_FLAG_PVSYNC) &&
160 (loop->flags & NVSync)) ||
161 ((mode->flags & DRM_MODE_FLAG_NHSYNC) &&
162 (loop->flags & PHSync)) ||
163 ((mode->flags & DRM_MODE_FLAG_PHSYNC) &&
164 (loop->flags & NHSync)))) {
168 if (loop->refresh_rate <= refresh_rate
169 && (!best || loop->refresh_rate > best->refresh_rate))
173 if (best || !check_sync)
179 vbios_mode->enh_table = best;
181 hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0;
182 vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0;
184 adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht;
185 adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder;
186 adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder;
187 adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder +
188 vbios_mode->enh_table->hfp;
189 adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder +
190 vbios_mode->enh_table->hfp +
191 vbios_mode->enh_table->hsync);
193 adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt;
194 adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder;
195 adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder;
196 adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder +
197 vbios_mode->enh_table->vfp;
198 adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder +
199 vbios_mode->enh_table->vfp +
200 vbios_mode->enh_table->vsync);
205 static void ast_set_vbios_color_reg(struct ast_private *ast,
206 const struct drm_format_info *format,
207 const struct ast_vbios_mode_info *vbios_mode)
211 switch (format->cpp[0]) {
213 color_index = VGAModeIndex - 1;
216 color_index = HiCModeIndex;
220 color_index = TrueCModeIndex;
226 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0x0f) << 4));
228 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
230 if (vbios_mode->enh_table->flags & NewModeInfo) {
231 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
232 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, format->cpp[0] * 8);
236 static void ast_set_vbios_mode_reg(struct ast_private *ast,
237 const struct drm_display_mode *adjusted_mode,
238 const struct ast_vbios_mode_info *vbios_mode)
240 u32 refresh_rate_index, mode_id;
242 refresh_rate_index = vbios_mode->enh_table->refresh_rate_index;
243 mode_id = vbios_mode->enh_table->mode_id;
245 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff);
246 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff);
248 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
250 if (vbios_mode->enh_table->flags & NewModeInfo) {
251 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
252 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000);
253 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay);
254 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8);
255 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay);
256 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8);
260 static void ast_set_std_reg(struct ast_private *ast,
261 struct drm_display_mode *mode,
262 struct ast_vbios_mode_info *vbios_mode)
264 const struct ast_vbios_stdtable *stdtable;
268 stdtable = vbios_mode->std_table;
270 jreg = stdtable->misc;
271 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
273 /* Set SEQ; except Screen Disable field */
274 ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03);
275 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x01, 0xdf, stdtable->seq[0]);
276 for (i = 1; i < 4; i++) {
277 jreg = stdtable->seq[i];
278 ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg);
281 /* Set CRTC; except base address and offset */
282 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
283 for (i = 0; i < 12; i++)
284 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
285 for (i = 14; i < 19; i++)
286 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
287 for (i = 20; i < 25; i++)
288 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
291 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
292 for (i = 0; i < 20; i++) {
293 jreg = stdtable->ar[i];
294 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i);
295 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg);
297 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14);
298 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00);
300 jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
301 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20);
304 for (i = 0; i < 9; i++)
305 ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]);
308 static void ast_set_crtc_reg(struct ast_private *ast,
309 struct drm_display_mode *mode,
310 struct ast_vbios_mode_info *vbios_mode)
312 u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0;
313 u16 temp, precache = 0;
315 if ((ast->chip == AST2500) &&
316 (vbios_mode->enh_table->flags & AST2500PreCatchCRT))
319 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
321 temp = (mode->crtc_htotal >> 3) - 5;
323 jregAC |= 0x01; /* HT D[8] */
324 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp);
326 temp = (mode->crtc_hdisplay >> 3) - 1;
328 jregAC |= 0x04; /* HDE D[8] */
329 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp);
331 temp = (mode->crtc_hblank_start >> 3) - 1;
333 jregAC |= 0x10; /* HBS D[8] */
334 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp);
336 temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f;
338 jreg05 |= 0x80; /* HBE D[5] */
340 jregAD |= 0x01; /* HBE D[5] */
341 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f));
343 temp = ((mode->crtc_hsync_start-precache) >> 3) - 1;
345 jregAC |= 0x40; /* HRS D[5] */
346 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp);
348 temp = (((mode->crtc_hsync_end-precache) >> 3) - 1) & 0x3f;
350 jregAD |= 0x04; /* HRE D[5] */
351 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05));
353 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC);
354 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD);
357 temp = (mode->crtc_vtotal) - 2;
364 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp);
366 temp = (mode->crtc_vsync_start) - 1;
373 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp);
375 temp = (mode->crtc_vsync_end - 1) & 0x3f;
380 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf);
382 temp = mode->crtc_vdisplay - 1;
389 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp);
391 temp = mode->crtc_vblank_start - 1;
398 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp);
400 temp = mode->crtc_vblank_end - 1;
403 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp);
405 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07);
406 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09);
407 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80));
410 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80);
412 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00);
414 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80);
417 static void ast_set_offset_reg(struct ast_private *ast,
418 struct drm_framebuffer *fb)
422 offset = fb->pitches[0] >> 3;
423 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff));
424 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f);
427 static void ast_set_dclk_reg(struct ast_private *ast,
428 struct drm_display_mode *mode,
429 struct ast_vbios_mode_info *vbios_mode)
431 const struct ast_vbios_dclk_info *clk_info;
433 if (ast->chip == AST2500)
434 clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index];
436 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index];
438 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1);
439 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2);
440 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f,
441 (clk_info->param3 & 0xc0) |
442 ((clk_info->param3 & 0x3) << 4));
445 static void ast_set_color_reg(struct ast_private *ast,
446 const struct drm_format_info *format)
448 u8 jregA0 = 0, jregA3 = 0, jregA8 = 0;
450 switch (format->cpp[0] * 8) {
469 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0);
470 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3);
471 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8);
474 static void ast_set_crtthd_reg(struct ast_private *ast)
477 if (ast->chip == AST2300 || ast->chip == AST2400 ||
478 ast->chip == AST2500) {
479 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78);
480 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60);
481 } else if (ast->chip == AST2100 ||
482 ast->chip == AST1100 ||
483 ast->chip == AST2200 ||
484 ast->chip == AST2150) {
485 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f);
486 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f);
488 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f);
489 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f);
493 static void ast_set_sync_reg(struct ast_private *ast,
494 struct drm_display_mode *mode,
495 struct ast_vbios_mode_info *vbios_mode)
499 jreg = ast_io_read8(ast, AST_IO_MISC_PORT_READ);
501 if (vbios_mode->enh_table->flags & NVSync) jreg |= 0x80;
502 if (vbios_mode->enh_table->flags & NHSync) jreg |= 0x40;
503 ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
506 static void ast_set_start_address_crt1(struct ast_private *ast,
512 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff));
513 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff));
514 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff));
518 static void ast_wait_for_vretrace(struct ast_private *ast)
520 unsigned long timeout = jiffies + HZ;
524 vgair1 = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
525 } while (!(vgair1 & AST_IO_VGAIR1_VREFRESH) && time_before(jiffies, timeout));
532 static const uint32_t ast_primary_plane_formats[] = {
538 static int ast_primary_plane_helper_atomic_check(struct drm_plane *plane,
539 struct drm_atomic_state *state)
541 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
543 struct drm_crtc_state *crtc_state;
544 struct ast_crtc_state *ast_crtc_state;
547 if (!new_plane_state->crtc)
550 crtc_state = drm_atomic_get_new_crtc_state(state,
551 new_plane_state->crtc);
553 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
554 DRM_PLANE_HELPER_NO_SCALING,
555 DRM_PLANE_HELPER_NO_SCALING,
560 if (!new_plane_state->visible)
563 ast_crtc_state = to_ast_crtc_state(crtc_state);
565 ast_crtc_state->format = new_plane_state->fb->format;
571 ast_primary_plane_helper_atomic_update(struct drm_plane *plane,
572 struct drm_atomic_state *state)
574 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
576 struct drm_device *dev = plane->dev;
577 struct ast_private *ast = to_ast_private(dev);
578 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
580 struct drm_gem_vram_object *gbo;
582 struct drm_framebuffer *fb = new_state->fb;
583 struct drm_framebuffer *old_fb = old_state->fb;
585 if (!old_fb || (fb->format != old_fb->format)) {
586 struct drm_crtc_state *crtc_state = new_state->crtc->state;
587 struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);
588 struct ast_vbios_mode_info *vbios_mode_info = &ast_crtc_state->vbios_mode_info;
590 ast_set_color_reg(ast, fb->format);
591 ast_set_vbios_color_reg(ast, fb->format, vbios_mode_info);
594 gbo = drm_gem_vram_of_gem(fb->obj[0]);
595 gpu_addr = drm_gem_vram_offset(gbo);
596 if (drm_WARN_ON_ONCE(dev, gpu_addr < 0))
597 return; /* Bug: we didn't pin the BO to VRAM in prepare_fb. */
599 ast_set_offset_reg(ast, fb);
600 ast_set_start_address_crt1(ast, (u32)gpu_addr);
602 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x00);
606 ast_primary_plane_helper_atomic_disable(struct drm_plane *plane,
607 struct drm_atomic_state *state)
609 struct ast_private *ast = to_ast_private(plane->dev);
611 ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20);
614 static const struct drm_plane_helper_funcs ast_primary_plane_helper_funcs = {
615 DRM_GEM_VRAM_PLANE_HELPER_FUNCS,
616 .atomic_check = ast_primary_plane_helper_atomic_check,
617 .atomic_update = ast_primary_plane_helper_atomic_update,
618 .atomic_disable = ast_primary_plane_helper_atomic_disable,
621 static const struct drm_plane_funcs ast_primary_plane_funcs = {
622 .update_plane = drm_atomic_helper_update_plane,
623 .disable_plane = drm_atomic_helper_disable_plane,
624 .destroy = drm_plane_cleanup,
625 .reset = drm_atomic_helper_plane_reset,
626 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
627 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
630 static int ast_primary_plane_init(struct ast_private *ast)
632 struct drm_device *dev = &ast->base;
633 struct drm_plane *primary_plane = &ast->primary_plane;
636 ret = drm_universal_plane_init(dev, primary_plane, 0x01,
637 &ast_primary_plane_funcs,
638 ast_primary_plane_formats,
639 ARRAY_SIZE(ast_primary_plane_formats),
640 NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
642 drm_err(dev, "drm_universal_plane_init() failed: %d\n", ret);
645 drm_plane_helper_add(primary_plane, &ast_primary_plane_helper_funcs);
654 static void ast_update_cursor_image(u8 __iomem *dst, const u8 *src, int width, int height)
659 } srcdata32[2], data32;
665 s32 alpha_dst_delta, last_alpha_dst_delta;
669 u32 per_pixel_copy, two_pixel_copy;
671 alpha_dst_delta = AST_MAX_HWC_WIDTH << 1;
672 last_alpha_dst_delta = alpha_dst_delta - (width << 1);
675 dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta;
676 per_pixel_copy = width & 1;
677 two_pixel_copy = width >> 1;
679 for (j = 0; j < height; j++) {
680 for (i = 0; i < two_pixel_copy; i++) {
681 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
682 srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0;
683 data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
684 data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
685 data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4);
686 data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4);
688 writel(data32.ul, dstxor);
696 for (i = 0; i < per_pixel_copy; i++) {
697 srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
698 data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
699 data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
700 writew(data16.us, dstxor);
701 csum += (u32)data16.us;
706 dstxor += last_alpha_dst_delta;
709 /* write checksum + signature */
712 writel(width, dst + AST_HWC_SIGNATURE_SizeX);
713 writel(height, dst + AST_HWC_SIGNATURE_SizeY);
714 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX);
715 writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY);
718 static void ast_set_cursor_base(struct ast_private *ast, u64 address)
720 u8 addr0 = (address >> 3) & 0xff;
721 u8 addr1 = (address >> 11) & 0xff;
722 u8 addr2 = (address >> 19) & 0xff;
724 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, addr0);
725 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, addr1);
726 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, addr2);
729 static void ast_set_cursor_location(struct ast_private *ast, u16 x, u16 y,
730 u8 x_offset, u8 y_offset)
732 u8 x0 = (x & 0x00ff);
733 u8 x1 = (x & 0x0f00) >> 8;
734 u8 y0 = (y & 0x00ff);
735 u8 y1 = (y & 0x0700) >> 8;
737 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset);
738 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset);
739 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, x0);
740 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, x1);
741 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, y0);
742 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, y1);
745 static void ast_set_cursor_enabled(struct ast_private *ast, bool enabled)
747 static const u8 mask = (u8)~(AST_IO_VGACRCB_HWC_16BPP |
748 AST_IO_VGACRCB_HWC_ENABLED);
750 u8 vgacrcb = AST_IO_VGACRCB_HWC_16BPP;
753 vgacrcb |= AST_IO_VGACRCB_HWC_ENABLED;
755 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, mask, vgacrcb);
758 static const uint32_t ast_cursor_plane_formats[] = {
762 static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane,
763 struct drm_atomic_state *state)
765 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
767 struct drm_framebuffer *fb = new_plane_state->fb;
768 struct drm_crtc_state *crtc_state;
771 if (!new_plane_state->crtc)
774 crtc_state = drm_atomic_get_new_crtc_state(state,
775 new_plane_state->crtc);
777 ret = drm_atomic_helper_check_plane_state(new_plane_state, crtc_state,
778 DRM_PLANE_HELPER_NO_SCALING,
779 DRM_PLANE_HELPER_NO_SCALING,
784 if (!new_plane_state->visible)
787 if (fb->width > AST_MAX_HWC_WIDTH || fb->height > AST_MAX_HWC_HEIGHT)
794 ast_cursor_plane_helper_atomic_update(struct drm_plane *plane,
795 struct drm_atomic_state *state)
797 struct ast_cursor_plane *ast_cursor_plane = to_ast_cursor_plane(plane);
798 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
800 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
802 struct drm_shadow_plane_state *shadow_plane_state = to_drm_shadow_plane_state(new_state);
803 struct drm_framebuffer *fb = new_state->fb;
804 struct ast_private *ast = to_ast_private(plane->dev);
805 struct dma_buf_map dst_map =
806 ast_cursor_plane->hwc[ast_cursor_plane->next_hwc_index].map;
808 ast_cursor_plane->hwc[ast_cursor_plane->next_hwc_index].off;
809 struct dma_buf_map src_map = shadow_plane_state->map[0];
810 unsigned int offset_x, offset_y;
812 u8 x_offset, y_offset;
817 src = src_map.vaddr; /* TODO: Use mapping abstraction properly */
818 dst = dst_map.vaddr_iomem; /* TODO: Use mapping abstraction properly */
819 sig = dst + AST_HWC_SIZE; /* TODO: Use mapping abstraction properly */
822 * Do data transfer to HW cursor BO. If a new cursor image was installed,
823 * point the scanout engine to dst_gbo's offset and page-flip the HWC buffers.
826 ast_update_cursor_image(dst, src, fb->width, fb->height);
828 if (new_state->fb != old_state->fb) {
829 ast_set_cursor_base(ast, dst_off);
831 ++ast_cursor_plane->next_hwc_index;
832 ast_cursor_plane->next_hwc_index %= ARRAY_SIZE(ast_cursor_plane->hwc);
836 * Update location in HWC signature and registers.
839 writel(new_state->crtc_x, sig + AST_HWC_SIGNATURE_X);
840 writel(new_state->crtc_y, sig + AST_HWC_SIGNATURE_Y);
842 offset_x = AST_MAX_HWC_WIDTH - fb->width;
843 offset_y = AST_MAX_HWC_HEIGHT - fb->height;
845 if (new_state->crtc_x < 0) {
846 x_offset = (-new_state->crtc_x) + offset_x;
850 x = new_state->crtc_x;
852 if (new_state->crtc_y < 0) {
853 y_offset = (-new_state->crtc_y) + offset_y;
857 y = new_state->crtc_y;
860 ast_set_cursor_location(ast, x, y, x_offset, y_offset);
862 /* Dummy write to enable HWC and make the HW pick-up the changes. */
863 ast_set_cursor_enabled(ast, true);
867 ast_cursor_plane_helper_atomic_disable(struct drm_plane *plane,
868 struct drm_atomic_state *state)
870 struct ast_private *ast = to_ast_private(plane->dev);
872 ast_set_cursor_enabled(ast, false);
875 static const struct drm_plane_helper_funcs ast_cursor_plane_helper_funcs = {
876 DRM_GEM_SHADOW_PLANE_HELPER_FUNCS,
877 .atomic_check = ast_cursor_plane_helper_atomic_check,
878 .atomic_update = ast_cursor_plane_helper_atomic_update,
879 .atomic_disable = ast_cursor_plane_helper_atomic_disable,
882 static void ast_cursor_plane_destroy(struct drm_plane *plane)
884 struct ast_cursor_plane *ast_cursor_plane = to_ast_cursor_plane(plane);
886 struct drm_gem_vram_object *gbo;
887 struct dma_buf_map map;
889 for (i = 0; i < ARRAY_SIZE(ast_cursor_plane->hwc); ++i) {
890 gbo = ast_cursor_plane->hwc[i].gbo;
891 map = ast_cursor_plane->hwc[i].map;
892 drm_gem_vram_vunmap(gbo, &map);
893 drm_gem_vram_unpin(gbo);
894 drm_gem_vram_put(gbo);
897 drm_plane_cleanup(plane);
900 static const struct drm_plane_funcs ast_cursor_plane_funcs = {
901 .update_plane = drm_atomic_helper_update_plane,
902 .disable_plane = drm_atomic_helper_disable_plane,
903 .destroy = ast_cursor_plane_destroy,
904 DRM_GEM_SHADOW_PLANE_FUNCS,
907 static int ast_cursor_plane_init(struct ast_private *ast)
909 struct drm_device *dev = &ast->base;
910 struct ast_cursor_plane *ast_cursor_plane = &ast->cursor_plane;
911 struct drm_plane *cursor_plane = &ast_cursor_plane->base;
913 struct drm_gem_vram_object *gbo;
914 struct dma_buf_map map;
919 * Allocate backing storage for cursors. The BOs are permanently
920 * pinned to the top end of the VRAM.
923 size = roundup(AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE, PAGE_SIZE);
925 for (i = 0; i < ARRAY_SIZE(ast_cursor_plane->hwc); ++i) {
926 gbo = drm_gem_vram_create(dev, size, 0);
931 ret = drm_gem_vram_pin(gbo, DRM_GEM_VRAM_PL_FLAG_VRAM |
932 DRM_GEM_VRAM_PL_FLAG_TOPDOWN);
934 goto err_drm_gem_vram_put;
935 ret = drm_gem_vram_vmap(gbo, &map);
937 goto err_drm_gem_vram_unpin;
938 off = drm_gem_vram_offset(gbo);
941 goto err_drm_gem_vram_vunmap;
943 ast_cursor_plane->hwc[i].gbo = gbo;
944 ast_cursor_plane->hwc[i].map = map;
945 ast_cursor_plane->hwc[i].off = off;
949 * Create the cursor plane. The plane's destroy callback will release
950 * the backing storages' BO memory.
953 ret = drm_universal_plane_init(dev, cursor_plane, 0x01,
954 &ast_cursor_plane_funcs,
955 ast_cursor_plane_formats,
956 ARRAY_SIZE(ast_cursor_plane_formats),
957 NULL, DRM_PLANE_TYPE_CURSOR, NULL);
959 drm_err(dev, "drm_universal_plane failed(): %d\n", ret);
962 drm_plane_helper_add(cursor_plane, &ast_cursor_plane_helper_funcs);
969 gbo = ast_cursor_plane->hwc[i].gbo;
970 map = ast_cursor_plane->hwc[i].map;
971 err_drm_gem_vram_vunmap:
972 drm_gem_vram_vunmap(gbo, &map);
973 err_drm_gem_vram_unpin:
974 drm_gem_vram_unpin(gbo);
975 err_drm_gem_vram_put:
976 drm_gem_vram_put(gbo);
985 static void ast_crtc_dpms(struct drm_crtc *crtc, int mode)
987 struct ast_private *ast = to_ast_private(crtc->dev);
989 /* TODO: Maybe control display signal generation with
990 * Sync Enable (bit CR17.7).
993 case DRM_MODE_DPMS_ON:
994 case DRM_MODE_DPMS_STANDBY:
995 case DRM_MODE_DPMS_SUSPEND:
996 if (ast->tx_chip_type == AST_TX_DP501)
997 ast_set_dp501_video_output(crtc->dev, 1);
999 case DRM_MODE_DPMS_OFF:
1000 if (ast->tx_chip_type == AST_TX_DP501)
1001 ast_set_dp501_video_output(crtc->dev, 0);
1006 static int ast_crtc_helper_atomic_check(struct drm_crtc *crtc,
1007 struct drm_atomic_state *state)
1009 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1011 struct drm_device *dev = crtc->dev;
1012 struct ast_crtc_state *ast_state;
1013 const struct drm_format_info *format;
1016 if (!crtc_state->enable)
1017 return 0; /* no mode checks if CRTC is being disabled */
1019 ast_state = to_ast_crtc_state(crtc_state);
1021 format = ast_state->format;
1022 if (drm_WARN_ON_ONCE(dev, !format))
1023 return -EINVAL; /* BUG: We didn't set format in primary check(). */
1025 succ = ast_get_vbios_mode_info(format, &crtc_state->mode,
1026 &crtc_state->adjusted_mode,
1027 &ast_state->vbios_mode_info);
1035 ast_crtc_helper_atomic_flush(struct drm_crtc *crtc,
1036 struct drm_atomic_state *state)
1038 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1040 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1042 struct ast_private *ast = to_ast_private(crtc->dev);
1043 struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);
1044 struct ast_crtc_state *old_ast_crtc_state = to_ast_crtc_state(old_crtc_state);
1047 * The gamma LUT has to be reloaded after changing the primary
1048 * plane's color format.
1050 if (old_ast_crtc_state->format != ast_crtc_state->format)
1051 ast_crtc_load_lut(ast, crtc);
1055 ast_crtc_helper_atomic_enable(struct drm_crtc *crtc,
1056 struct drm_atomic_state *state)
1058 struct drm_device *dev = crtc->dev;
1059 struct ast_private *ast = to_ast_private(dev);
1060 struct drm_crtc_state *crtc_state = crtc->state;
1061 struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);
1062 struct ast_vbios_mode_info *vbios_mode_info =
1063 &ast_crtc_state->vbios_mode_info;
1064 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1066 ast_set_vbios_mode_reg(ast, adjusted_mode, vbios_mode_info);
1067 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06);
1068 ast_set_std_reg(ast, adjusted_mode, vbios_mode_info);
1069 ast_set_crtc_reg(ast, adjusted_mode, vbios_mode_info);
1070 ast_set_dclk_reg(ast, adjusted_mode, vbios_mode_info);
1071 ast_set_crtthd_reg(ast);
1072 ast_set_sync_reg(ast, adjusted_mode, vbios_mode_info);
1074 ast_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1078 ast_crtc_helper_atomic_disable(struct drm_crtc *crtc,
1079 struct drm_atomic_state *state)
1081 struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1083 struct drm_device *dev = crtc->dev;
1084 struct ast_private *ast = to_ast_private(dev);
1086 ast_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1089 * HW cursors require the underlying primary plane and CRTC to
1090 * display a valid mode and image. This is not the case during
1091 * full modeset operations. So we temporarily disable any active
1092 * plane, including the HW cursor. Each plane's atomic_update()
1093 * helper will re-enable it if necessary.
1095 * We only do this during *full* modesets. It does not affect
1096 * simple pageflips on the planes.
1098 drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, false);
1101 * Ensure that no scanout takes place before reprogramming mode
1102 * and format registers.
1104 ast_wait_for_vretrace(ast);
1107 static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = {
1108 .atomic_check = ast_crtc_helper_atomic_check,
1109 .atomic_flush = ast_crtc_helper_atomic_flush,
1110 .atomic_enable = ast_crtc_helper_atomic_enable,
1111 .atomic_disable = ast_crtc_helper_atomic_disable,
1114 static void ast_crtc_reset(struct drm_crtc *crtc)
1116 struct ast_crtc_state *ast_state =
1117 kzalloc(sizeof(*ast_state), GFP_KERNEL);
1120 crtc->funcs->atomic_destroy_state(crtc, crtc->state);
1122 __drm_atomic_helper_crtc_reset(crtc, &ast_state->base);
1125 static struct drm_crtc_state *
1126 ast_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1128 struct ast_crtc_state *new_ast_state, *ast_state;
1129 struct drm_device *dev = crtc->dev;
1131 if (drm_WARN_ON(dev, !crtc->state))
1134 new_ast_state = kmalloc(sizeof(*new_ast_state), GFP_KERNEL);
1137 __drm_atomic_helper_crtc_duplicate_state(crtc, &new_ast_state->base);
1139 ast_state = to_ast_crtc_state(crtc->state);
1141 new_ast_state->format = ast_state->format;
1142 memcpy(&new_ast_state->vbios_mode_info, &ast_state->vbios_mode_info,
1143 sizeof(new_ast_state->vbios_mode_info));
1145 return &new_ast_state->base;
1148 static void ast_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1149 struct drm_crtc_state *state)
1151 struct ast_crtc_state *ast_state = to_ast_crtc_state(state);
1153 __drm_atomic_helper_crtc_destroy_state(&ast_state->base);
1157 static const struct drm_crtc_funcs ast_crtc_funcs = {
1158 .reset = ast_crtc_reset,
1159 .destroy = drm_crtc_cleanup,
1160 .set_config = drm_atomic_helper_set_config,
1161 .page_flip = drm_atomic_helper_page_flip,
1162 .atomic_duplicate_state = ast_crtc_atomic_duplicate_state,
1163 .atomic_destroy_state = ast_crtc_atomic_destroy_state,
1166 static int ast_crtc_init(struct drm_device *dev)
1168 struct ast_private *ast = to_ast_private(dev);
1169 struct drm_crtc *crtc = &ast->crtc;
1172 ret = drm_crtc_init_with_planes(dev, crtc, &ast->primary_plane,
1173 &ast->cursor_plane.base, &ast_crtc_funcs,
1178 drm_mode_crtc_set_gamma_size(crtc, 256);
1179 drm_crtc_helper_add(crtc, &ast_crtc_helper_funcs);
1188 static int ast_encoder_init(struct drm_device *dev)
1190 struct ast_private *ast = to_ast_private(dev);
1191 struct drm_encoder *encoder = &ast->encoder;
1194 ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_DAC);
1198 encoder->possible_crtcs = 1;
1207 static int ast_get_modes(struct drm_connector *connector)
1209 struct ast_connector *ast_connector = to_ast_connector(connector);
1210 struct ast_private *ast = to_ast_private(connector->dev);
1214 if (ast->tx_chip_type == AST_TX_DP501) {
1215 ast->dp501_maxclk = 0xff;
1216 edid = kmalloc(128, GFP_KERNEL);
1220 flags = ast_dp501_read_edid(connector->dev, (u8 *)edid);
1222 ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev);
1227 edid = drm_get_edid(connector, &ast_connector->i2c->adapter);
1229 drm_connector_update_edid_property(&ast_connector->base, edid);
1230 ret = drm_add_edid_modes(connector, edid);
1234 drm_connector_update_edid_property(&ast_connector->base, NULL);
1238 static enum drm_mode_status ast_mode_valid(struct drm_connector *connector,
1239 struct drm_display_mode *mode)
1241 struct ast_private *ast = to_ast_private(connector->dev);
1242 int flags = MODE_NOMODE;
1245 if (ast->support_wide_screen) {
1246 if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050))
1248 if ((mode->hdisplay == 1280) && (mode->vdisplay == 800))
1250 if ((mode->hdisplay == 1440) && (mode->vdisplay == 900))
1252 if ((mode->hdisplay == 1360) && (mode->vdisplay == 768))
1254 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900))
1257 if ((ast->chip == AST2100) || (ast->chip == AST2200) ||
1258 (ast->chip == AST2300) || (ast->chip == AST2400) ||
1259 (ast->chip == AST2500)) {
1260 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080))
1263 if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) {
1264 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
1272 switch (mode->hdisplay) {
1274 if (mode->vdisplay == 480) flags = MODE_OK;
1277 if (mode->vdisplay == 600) flags = MODE_OK;
1280 if (mode->vdisplay == 768) flags = MODE_OK;
1283 if (mode->vdisplay == 1024) flags = MODE_OK;
1286 if (mode->vdisplay == 1200) flags = MODE_OK;
1295 static enum drm_connector_status ast_connector_detect(struct drm_connector
1296 *connector, bool force)
1300 r = ast_get_modes(connector);
1302 return connector_status_disconnected;
1304 return connector_status_connected;
1307 static void ast_connector_destroy(struct drm_connector *connector)
1309 struct ast_connector *ast_connector = to_ast_connector(connector);
1310 ast_i2c_destroy(ast_connector->i2c);
1311 drm_connector_cleanup(connector);
1314 static const struct drm_connector_helper_funcs ast_connector_helper_funcs = {
1315 .get_modes = ast_get_modes,
1316 .mode_valid = ast_mode_valid,
1319 static const struct drm_connector_funcs ast_connector_funcs = {
1320 .reset = drm_atomic_helper_connector_reset,
1321 .detect = ast_connector_detect,
1322 .fill_modes = drm_helper_probe_single_connector_modes,
1323 .destroy = ast_connector_destroy,
1324 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1325 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1328 static int ast_connector_init(struct drm_device *dev)
1330 struct ast_private *ast = to_ast_private(dev);
1331 struct ast_connector *ast_connector = &ast->connector;
1332 struct drm_connector *connector = &ast_connector->base;
1333 struct drm_encoder *encoder = &ast->encoder;
1335 ast_connector->i2c = ast_i2c_create(dev);
1336 if (!ast_connector->i2c)
1337 drm_err(dev, "failed to add ddc bus for connector\n");
1339 drm_connector_init_with_ddc(dev, connector,
1340 &ast_connector_funcs,
1341 DRM_MODE_CONNECTOR_VGA,
1342 &ast_connector->i2c->adapter);
1344 drm_connector_helper_add(connector, &ast_connector_helper_funcs);
1346 connector->interlace_allowed = 0;
1347 connector->doublescan_allowed = 0;
1349 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1350 DRM_CONNECTOR_POLL_DISCONNECT;
1352 drm_connector_attach_encoder(connector, encoder);
1361 static const struct drm_mode_config_helper_funcs
1362 ast_mode_config_helper_funcs = {
1363 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
1366 static const struct drm_mode_config_funcs ast_mode_config_funcs = {
1367 .fb_create = drm_gem_fb_create,
1368 .mode_valid = drm_vram_helper_mode_valid,
1369 .atomic_check = drm_atomic_helper_check,
1370 .atomic_commit = drm_atomic_helper_commit,
1373 int ast_mode_config_init(struct ast_private *ast)
1375 struct drm_device *dev = &ast->base;
1376 struct pci_dev *pdev = to_pci_dev(dev->dev);
1379 ret = drmm_mode_config_init(dev);
1383 dev->mode_config.funcs = &ast_mode_config_funcs;
1384 dev->mode_config.min_width = 0;
1385 dev->mode_config.min_height = 0;
1386 dev->mode_config.preferred_depth = 24;
1387 dev->mode_config.prefer_shadow = 1;
1388 dev->mode_config.fb_base = pci_resource_start(pdev, 0);
1390 if (ast->chip == AST2100 ||
1391 ast->chip == AST2200 ||
1392 ast->chip == AST2300 ||
1393 ast->chip == AST2400 ||
1394 ast->chip == AST2500) {
1395 dev->mode_config.max_width = 1920;
1396 dev->mode_config.max_height = 2048;
1398 dev->mode_config.max_width = 1600;
1399 dev->mode_config.max_height = 1200;
1402 dev->mode_config.helper_private = &ast_mode_config_helper_funcs;
1405 ret = ast_primary_plane_init(ast);
1409 ret = ast_cursor_plane_init(ast);
1414 ast_encoder_init(dev);
1415 ast_connector_init(dev);
1417 drm_mode_config_reset(dev);
1419 drm_kms_helper_poll_init(dev);
1424 static int get_clock(void *i2c_priv)
1426 struct ast_i2c_chan *i2c = i2c_priv;
1427 struct ast_private *ast = to_ast_private(i2c->dev);
1428 uint32_t val, val2, count, pass;
1432 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
1434 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
1439 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
1441 } while ((pass < 5) && (count++ < 0x10000));
1443 return val & 1 ? 1 : 0;
1446 static int get_data(void *i2c_priv)
1448 struct ast_i2c_chan *i2c = i2c_priv;
1449 struct ast_private *ast = to_ast_private(i2c->dev);
1450 uint32_t val, val2, count, pass;
1454 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
1456 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
1461 val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
1463 } while ((pass < 5) && (count++ < 0x10000));
1465 return val & 1 ? 1 : 0;
1468 static void set_clock(void *i2c_priv, int clock)
1470 struct ast_i2c_chan *i2c = i2c_priv;
1471 struct ast_private *ast = to_ast_private(i2c->dev);
1475 for (i = 0; i < 0x10000; i++) {
1476 ujcrb7 = ((clock & 0x01) ? 0 : 1);
1477 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf4, ujcrb7);
1478 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01);
1479 if (ujcrb7 == jtemp)
1484 static void set_data(void *i2c_priv, int data)
1486 struct ast_i2c_chan *i2c = i2c_priv;
1487 struct ast_private *ast = to_ast_private(i2c->dev);
1491 for (i = 0; i < 0x10000; i++) {
1492 ujcrb7 = ((data & 0x01) ? 0 : 1) << 2;
1493 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf1, ujcrb7);
1494 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04);
1495 if (ujcrb7 == jtemp)
1500 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev)
1502 struct ast_i2c_chan *i2c;
1505 i2c = kzalloc(sizeof(struct ast_i2c_chan), GFP_KERNEL);
1509 i2c->adapter.owner = THIS_MODULE;
1510 i2c->adapter.class = I2C_CLASS_DDC;
1511 i2c->adapter.dev.parent = dev->dev;
1513 i2c_set_adapdata(&i2c->adapter, i2c);
1514 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
1516 i2c->adapter.algo_data = &i2c->bit;
1518 i2c->bit.udelay = 20;
1519 i2c->bit.timeout = 2;
1520 i2c->bit.data = i2c;
1521 i2c->bit.setsda = set_data;
1522 i2c->bit.setscl = set_clock;
1523 i2c->bit.getsda = get_data;
1524 i2c->bit.getscl = get_clock;
1525 ret = i2c_bit_add_bus(&i2c->adapter);
1527 drm_err(dev, "Failed to register bit i2c\n");
1537 static void ast_i2c_destroy(struct ast_i2c_chan *i2c)
1541 i2c_del_adapter(&i2c->adapter);