drivers/gpu/drm/ast/ast_mode.c

   1 /*
   2  * Copyright 2012 Red Hat Inc.
   3  * Parts based on xf86-video-ast
   4  * Copyright (c) 2005 ASPEED Technology Inc.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  18  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  19  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  20  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * The above copyright notice and this permission notice (including the
  23  * next paragraph) shall be included in all copies or substantial portions
  24  * of the Software.
  25  *
  26  */
  27 /*
  28  * Authors: Dave Airlie <airlied@redhat.com>
  29  */
  30
  31 #include <linux/export.h>
  32 #include <linux/pci.h>
  33
  34 #include <drm/drm_atomic.h>
  35 #include <drm/drm_atomic_helper.h>
  36 #include <drm/drm_atomic_state_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_crtc_helper.h>
  39 #include <drm/drm_fourcc.h>
  40 #include <drm/drm_gem_framebuffer_helper.h>
  41 #include <drm/drm_gem_vram_helper.h>
  42 #include <drm/drm_plane_helper.h>
  43 #include <drm/drm_probe_helper.h>
  44 #include <drm/drm_simple_kms_helper.h>
  45
  46 #include "ast_drv.h"
  47 #include "ast_tables.h"
  48
  49 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev);
  50 static void ast_i2c_destroy(struct ast_i2c_chan *i2c);
  51
  52 static inline void ast_load_palette_index(struct ast_private *ast,
  53                                      u8 index, u8 red, u8 green,
  54                                      u8 blue)
  55 {
  56         ast_io_write8(ast, AST_IO_DAC_INDEX_WRITE, index);
  57         ast_io_read8(ast, AST_IO_SEQ_PORT);
  58         ast_io_write8(ast, AST_IO_DAC_DATA, red);
  59         ast_io_read8(ast, AST_IO_SEQ_PORT);
  60         ast_io_write8(ast, AST_IO_DAC_DATA, green);
  61         ast_io_read8(ast, AST_IO_SEQ_PORT);
  62         ast_io_write8(ast, AST_IO_DAC_DATA, blue);
  63         ast_io_read8(ast, AST_IO_SEQ_PORT);
  64 }
  65
  66 static void ast_crtc_load_lut(struct ast_private *ast, struct drm_crtc *crtc)
  67 {
  68         u16 *r, *g, *b;
  69         int i;
  70
  71         if (!crtc->enabled)
  72                 return;
  73
  74         r = crtc->gamma_store;
  75         g = r + crtc->gamma_size;
  76         b = g + crtc->gamma_size;
  77
  78         for (i = 0; i < 256; i++)
  79                 ast_load_palette_index(ast, i, *r++ >> 8, *g++ >> 8, *b++ >> 8);
  80 }
  81
  82 static bool ast_get_vbios_mode_info(const struct drm_format_info *format,
  83                                     const struct drm_display_mode *mode,
  84                                     struct drm_display_mode *adjusted_mode,
  85                                     struct ast_vbios_mode_info *vbios_mode)
  86 {
  87         u32 refresh_rate_index = 0, refresh_rate;
  88         const struct ast_vbios_enhtable *best = NULL;
  89         u32 hborder, vborder;
  90         bool check_sync;
  91
  92         switch (format->cpp[0] * 8) {
  93         case 8:
  94                 vbios_mode->std_table = &vbios_stdtable[VGAModeIndex];
  95                 break;
  96         case 16:
  97                 vbios_mode->std_table = &vbios_stdtable[HiCModeIndex];
  98                 break;
  99         case 24:
 100         case 32:
 101                 vbios_mode->std_table = &vbios_stdtable[TrueCModeIndex];
 102                 break;
 103         default:
 104                 return false;
 105         }
 106
 107         switch (mode->crtc_hdisplay) {
 108         case 640:
 109                 vbios_mode->enh_table = &res_640x480[refresh_rate_index];
 110                 break;
 111         case 800:
 112                 vbios_mode->enh_table = &res_800x600[refresh_rate_index];
 113                 break;
 114         case 1024:
 115                 vbios_mode->enh_table = &res_1024x768[refresh_rate_index];
 116                 break;
 117         case 1280:
 118                 if (mode->crtc_vdisplay == 800)
 119                         vbios_mode->enh_table = &res_1280x800[refresh_rate_index];
 120                 else
 121                         vbios_mode->enh_table = &res_1280x1024[refresh_rate_index];
 122                 break;
 123         case 1360:
 124                 vbios_mode->enh_table = &res_1360x768[refresh_rate_index];
 125                 break;
 126         case 1440:
 127                 vbios_mode->enh_table = &res_1440x900[refresh_rate_index];
 128                 break;
 129         case 1600:
 130                 if (mode->crtc_vdisplay == 900)
 131                         vbios_mode->enh_table = &res_1600x900[refresh_rate_index];
 132                 else
 133                         vbios_mode->enh_table = &res_1600x1200[refresh_rate_index];
 134                 break;
 135         case 1680:
 136                 vbios_mode->enh_table = &res_1680x1050[refresh_rate_index];
 137                 break;
 138         case 1920:
 139                 if (mode->crtc_vdisplay == 1080)
 140                         vbios_mode->enh_table = &res_1920x1080[refresh_rate_index];
 141                 else
 142                         vbios_mode->enh_table = &res_1920x1200[refresh_rate_index];
 143                 break;
 144         default:
 145                 return false;
 146         }
 147
 148         refresh_rate = drm_mode_vrefresh(mode);
 149         check_sync = vbios_mode->enh_table->flags & WideScreenMode;
 150
 151         while (1) {
 152                 const struct ast_vbios_enhtable *loop = vbios_mode->enh_table;
 153
 154                 while (loop->refresh_rate != 0xff) {
 155                         if ((check_sync) &&
 156                             (((mode->flags & DRM_MODE_FLAG_NVSYNC)  &&
 157                               (loop->flags & PVSync))  ||
 158                              ((mode->flags & DRM_MODE_FLAG_PVSYNC)  &&
 159                               (loop->flags & NVSync))  ||
 160                              ((mode->flags & DRM_MODE_FLAG_NHSYNC)  &&
 161                               (loop->flags & PHSync))  ||
 162                              ((mode->flags & DRM_MODE_FLAG_PHSYNC)  &&
 163                               (loop->flags & NHSync)))) {
 164                                 loop++;
 165                                 continue;
 166                         }
 167                         if (loop->refresh_rate <= refresh_rate
 168                             && (!best || loop->refresh_rate > best->refresh_rate))
 169                                 best = loop;
 170                         loop++;
 171                 }
 172                 if (best || !check_sync)
 173                         break;
 174                 check_sync = 0;
 175         }
 176
 177         if (best)
 178                 vbios_mode->enh_table = best;
 179
 180         hborder = (vbios_mode->enh_table->flags & HBorder) ? 8 : 0;
 181         vborder = (vbios_mode->enh_table->flags & VBorder) ? 8 : 0;
 182
 183         adjusted_mode->crtc_htotal = vbios_mode->enh_table->ht;
 184         adjusted_mode->crtc_hblank_start = vbios_mode->enh_table->hde + hborder;
 185         adjusted_mode->crtc_hblank_end = vbios_mode->enh_table->ht - hborder;
 186         adjusted_mode->crtc_hsync_start = vbios_mode->enh_table->hde + hborder +
 187                 vbios_mode->enh_table->hfp;
 188         adjusted_mode->crtc_hsync_end = (vbios_mode->enh_table->hde + hborder +
 189                                          vbios_mode->enh_table->hfp +
 190                                          vbios_mode->enh_table->hsync);
 191
 192         adjusted_mode->crtc_vtotal = vbios_mode->enh_table->vt;
 193         adjusted_mode->crtc_vblank_start = vbios_mode->enh_table->vde + vborder;
 194         adjusted_mode->crtc_vblank_end = vbios_mode->enh_table->vt - vborder;
 195         adjusted_mode->crtc_vsync_start = vbios_mode->enh_table->vde + vborder +
 196                 vbios_mode->enh_table->vfp;
 197         adjusted_mode->crtc_vsync_end = (vbios_mode->enh_table->vde + vborder +
 198                                          vbios_mode->enh_table->vfp +
 199                                          vbios_mode->enh_table->vsync);
 200
 201         return true;
 202 }
 203
 204 static void ast_set_vbios_color_reg(struct ast_private *ast,
 205                                     const struct drm_format_info *format,
 206                                     const struct ast_vbios_mode_info *vbios_mode)
 207 {
 208         u32 color_index;
 209
 210         switch (format->cpp[0]) {
 211         case 1:
 212                 color_index = VGAModeIndex - 1;
 213                 break;
 214         case 2:
 215                 color_index = HiCModeIndex;
 216                 break;
 217         case 3:
 218         case 4:
 219                 color_index = TrueCModeIndex;
 220                 break;
 221         default:
 222                 return;
 223         }
 224
 225         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8c, (u8)((color_index & 0x0f) << 4));
 226
 227         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
 228
 229         if (vbios_mode->enh_table->flags & NewModeInfo) {
 230                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
 231                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x92, format->cpp[0] * 8);
 232         }
 233 }
 234
 235 static void ast_set_vbios_mode_reg(struct ast_private *ast,
 236                                    const struct drm_display_mode *adjusted_mode,
 237                                    const struct ast_vbios_mode_info *vbios_mode)
 238 {
 239         u32 refresh_rate_index, mode_id;
 240
 241         refresh_rate_index = vbios_mode->enh_table->refresh_rate_index;
 242         mode_id = vbios_mode->enh_table->mode_id;
 243
 244         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8d, refresh_rate_index & 0xff);
 245         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x8e, mode_id & 0xff);
 246
 247         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0x00);
 248
 249         if (vbios_mode->enh_table->flags & NewModeInfo) {
 250                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x91, 0xa8);
 251                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x93, adjusted_mode->clock / 1000);
 252                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x94, adjusted_mode->crtc_hdisplay);
 253                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x95, adjusted_mode->crtc_hdisplay >> 8);
 254                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x96, adjusted_mode->crtc_vdisplay);
 255                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x97, adjusted_mode->crtc_vdisplay >> 8);
 256         }
 257 }
 258
 259 static void ast_set_std_reg(struct ast_private *ast,
 260                             struct drm_display_mode *mode,
 261                             struct ast_vbios_mode_info *vbios_mode)
 262 {
 263         const struct ast_vbios_stdtable *stdtable;
 264         u32 i;
 265         u8 jreg;
 266
 267         stdtable = vbios_mode->std_table;
 268
 269         jreg = stdtable->misc;
 270         ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
 271
 272         /* Set SEQ; except Screen Disable field */
 273         ast_set_index_reg(ast, AST_IO_SEQ_PORT, 0x00, 0x03);
 274         ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x01, 0xdf, stdtable->seq[0]);
 275         for (i = 1; i < 4; i++) {
 276                 jreg = stdtable->seq[i];
 277                 ast_set_index_reg(ast, AST_IO_SEQ_PORT, (i + 1) , jreg);
 278         }
 279
 280         /* Set CRTC; except base address and offset */
 281         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
 282         for (i = 0; i < 12; i++)
 283                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
 284         for (i = 14; i < 19; i++)
 285                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
 286         for (i = 20; i < 25; i++)
 287                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, i, stdtable->crtc[i]);
 288
 289         /* set AR */
 290         jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
 291         for (i = 0; i < 20; i++) {
 292                 jreg = stdtable->ar[i];
 293                 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, (u8)i);
 294                 ast_io_write8(ast, AST_IO_AR_PORT_WRITE, jreg);
 295         }
 296         ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x14);
 297         ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x00);
 298
 299         jreg = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
 300         ast_io_write8(ast, AST_IO_AR_PORT_WRITE, 0x20);
 301
 302         /* Set GR */
 303         for (i = 0; i < 9; i++)
 304                 ast_set_index_reg(ast, AST_IO_GR_PORT, i, stdtable->gr[i]);
 305 }
 306
 307 static void ast_set_crtc_reg(struct ast_private *ast,
 308                              struct drm_display_mode *mode,
 309                              struct ast_vbios_mode_info *vbios_mode)
 310 {
 311         u8 jreg05 = 0, jreg07 = 0, jreg09 = 0, jregAC = 0, jregAD = 0, jregAE = 0;
 312         u16 temp, precache = 0;
 313
 314         if ((ast->chip == AST2500) &&
 315             (vbios_mode->enh_table->flags & AST2500PreCatchCRT))
 316                 precache = 40;
 317
 318         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x00);
 319
 320         temp = (mode->crtc_htotal >> 3) - 5;
 321         if (temp & 0x100)
 322                 jregAC |= 0x01; /* HT D[8] */
 323         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x00, 0x00, temp);
 324
 325         temp = (mode->crtc_hdisplay >> 3) - 1;
 326         if (temp & 0x100)
 327                 jregAC |= 0x04; /* HDE D[8] */
 328         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x01, 0x00, temp);
 329
 330         temp = (mode->crtc_hblank_start >> 3) - 1;
 331         if (temp & 0x100)
 332                 jregAC |= 0x10; /* HBS D[8] */
 333         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x02, 0x00, temp);
 334
 335         temp = ((mode->crtc_hblank_end >> 3) - 1) & 0x7f;
 336         if (temp & 0x20)
 337                 jreg05 |= 0x80;  /* HBE D[5] */
 338         if (temp & 0x40)
 339                 jregAD |= 0x01;  /* HBE D[5] */
 340         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x03, 0xE0, (temp & 0x1f));
 341
 342         temp = ((mode->crtc_hsync_start-precache) >> 3) - 1;
 343         if (temp & 0x100)
 344                 jregAC |= 0x40; /* HRS D[5] */
 345         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x04, 0x00, temp);
 346
 347         temp = (((mode->crtc_hsync_end-precache) >> 3) - 1) & 0x3f;
 348         if (temp & 0x20)
 349                 jregAD |= 0x04; /* HRE D[5] */
 350         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x05, 0x60, (u8)((temp & 0x1f) | jreg05));
 351
 352         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAC, 0x00, jregAC);
 353         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAD, 0x00, jregAD);
 354
 355         /* vert timings */
 356         temp = (mode->crtc_vtotal) - 2;
 357         if (temp & 0x100)
 358                 jreg07 |= 0x01;
 359         if (temp & 0x200)
 360                 jreg07 |= 0x20;
 361         if (temp & 0x400)
 362                 jregAE |= 0x01;
 363         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x06, 0x00, temp);
 364
 365         temp = (mode->crtc_vsync_start) - 1;
 366         if (temp & 0x100)
 367                 jreg07 |= 0x04;
 368         if (temp & 0x200)
 369                 jreg07 |= 0x80;
 370         if (temp & 0x400)
 371                 jregAE |= 0x08;
 372         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x10, 0x00, temp);
 373
 374         temp = (mode->crtc_vsync_end - 1) & 0x3f;
 375         if (temp & 0x10)
 376                 jregAE |= 0x20;
 377         if (temp & 0x20)
 378                 jregAE |= 0x40;
 379         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x70, temp & 0xf);
 380
 381         temp = mode->crtc_vdisplay - 1;
 382         if (temp & 0x100)
 383                 jreg07 |= 0x02;
 384         if (temp & 0x200)
 385                 jreg07 |= 0x40;
 386         if (temp & 0x400)
 387                 jregAE |= 0x02;
 388         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x12, 0x00, temp);
 389
 390         temp = mode->crtc_vblank_start - 1;
 391         if (temp & 0x100)
 392                 jreg07 |= 0x08;
 393         if (temp & 0x200)
 394                 jreg09 |= 0x20;
 395         if (temp & 0x400)
 396                 jregAE |= 0x04;
 397         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x15, 0x00, temp);
 398
 399         temp = mode->crtc_vblank_end - 1;
 400         if (temp & 0x100)
 401                 jregAE |= 0x10;
 402         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x16, 0x00, temp);
 403
 404         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x07, 0x00, jreg07);
 405         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x09, 0xdf, jreg09);
 406         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xAE, 0x00, (jregAE | 0x80));
 407
 408         if (precache)
 409                 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x80);
 410         else
 411                 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb6, 0x3f, 0x00);
 412
 413         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0x11, 0x7f, 0x80);
 414 }
 415
 416 static void ast_set_offset_reg(struct ast_private *ast,
 417                                struct drm_framebuffer *fb)
 418 {
 419         u16 offset;
 420
 421         offset = fb->pitches[0] >> 3;
 422         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x13, (offset & 0xff));
 423         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xb0, (offset >> 8) & 0x3f);
 424 }
 425
 426 static void ast_set_dclk_reg(struct ast_private *ast,
 427                              struct drm_display_mode *mode,
 428                              struct ast_vbios_mode_info *vbios_mode)
 429 {
 430         const struct ast_vbios_dclk_info *clk_info;
 431
 432         if (ast->chip == AST2500)
 433                 clk_info = &dclk_table_ast2500[vbios_mode->enh_table->dclk_index];
 434         else
 435                 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index];
 436
 437         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc0, 0x00, clk_info->param1);
 438         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xc1, 0x00, clk_info->param2);
 439         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xbb, 0x0f,
 440                                (clk_info->param3 & 0xc0) |
 441                                ((clk_info->param3 & 0x3) << 4));
 442 }
 443
 444 static void ast_set_color_reg(struct ast_private *ast,
 445                               const struct drm_format_info *format)
 446 {
 447         u8 jregA0 = 0, jregA3 = 0, jregA8 = 0;
 448
 449         switch (format->cpp[0] * 8) {
 450         case 8:
 451                 jregA0 = 0x70;
 452                 jregA3 = 0x01;
 453                 jregA8 = 0x00;
 454                 break;
 455         case 15:
 456         case 16:
 457                 jregA0 = 0x70;
 458                 jregA3 = 0x04;
 459                 jregA8 = 0x02;
 460                 break;
 461         case 32:
 462                 jregA0 = 0x70;
 463                 jregA3 = 0x08;
 464                 jregA8 = 0x02;
 465                 break;
 466         }
 467
 468         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa0, 0x8f, jregA0);
 469         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa3, 0xf0, jregA3);
 470         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xa8, 0xfd, jregA8);
 471 }
 472
 473 static void ast_set_crtthd_reg(struct ast_private *ast)
 474 {
 475         /* Set Threshold */
 476         if (ast->chip == AST2300 || ast->chip == AST2400 ||
 477             ast->chip == AST2500) {
 478                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x78);
 479                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x60);
 480         } else if (ast->chip == AST2100 ||
 481                    ast->chip == AST1100 ||
 482                    ast->chip == AST2200 ||
 483                    ast->chip == AST2150) {
 484                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x3f);
 485                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x2f);
 486         } else {
 487                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa7, 0x2f);
 488                 ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa6, 0x1f);
 489         }
 490 }
 491
 492 static void ast_set_sync_reg(struct ast_private *ast,
 493                              struct drm_display_mode *mode,
 494                              struct ast_vbios_mode_info *vbios_mode)
 495 {
 496         u8 jreg;
 497
 498         jreg  = ast_io_read8(ast, AST_IO_MISC_PORT_READ);
 499         jreg &= ~0xC0;
 500         if (vbios_mode->enh_table->flags & NVSync) jreg |= 0x80;
 501         if (vbios_mode->enh_table->flags & NHSync) jreg |= 0x40;
 502         ast_io_write8(ast, AST_IO_MISC_PORT_WRITE, jreg);
 503 }
 504
 505 static void ast_set_start_address_crt1(struct ast_private *ast,
 506                                        unsigned offset)
 507 {
 508         u32 addr;
 509
 510         addr = offset >> 2;
 511         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0d, (u8)(addr & 0xff));
 512         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x0c, (u8)((addr >> 8) & 0xff));
 513         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xaf, (u8)((addr >> 16) & 0xff));
 514
 515 }
 516
 517 static void ast_wait_for_vretrace(struct ast_private *ast)
 518 {
 519         unsigned long timeout = jiffies + HZ;
 520         u8 vgair1;
 521
 522         do {
 523                 vgair1 = ast_io_read8(ast, AST_IO_INPUT_STATUS1_READ);
 524         } while (!(vgair1 & AST_IO_VGAIR1_VREFRESH) && time_before(jiffies, timeout));
 525 }
 526
 527 /*
 528  * Primary plane
 529  */
 530
 531 static const uint32_t ast_primary_plane_formats[] = {
 532         DRM_FORMAT_XRGB8888,
 533         DRM_FORMAT_RGB565,
 534         DRM_FORMAT_C8,
 535 };
 536
 537 static int ast_primary_plane_helper_atomic_check(struct drm_plane *plane,
 538                                                  struct drm_plane_state *state)
 539 {
 540         struct drm_crtc_state *crtc_state;
 541         struct ast_crtc_state *ast_crtc_state;
 542         int ret;
 543
 544         if (!state->crtc)
 545                 return 0;
 546
 547         crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc);
 548
 549         ret = drm_atomic_helper_check_plane_state(state, crtc_state,
 550                                                   DRM_PLANE_HELPER_NO_SCALING,
 551                                                   DRM_PLANE_HELPER_NO_SCALING,
 552                                                   false, true);
 553         if (ret)
 554                 return ret;
 555
 556         if (!state->visible)
 557                 return 0;
 558
 559         ast_crtc_state = to_ast_crtc_state(crtc_state);
 560
 561         ast_crtc_state->format = state->fb->format;
 562
 563         return 0;
 564 }
 565
 566 static void
 567 ast_primary_plane_helper_atomic_update(struct drm_plane *plane,
 568                                        struct drm_plane_state *old_state)
 569 {
 570         struct drm_device *dev = plane->dev;
 571         struct ast_private *ast = to_ast_private(dev);
 572         struct drm_plane_state *state = plane->state;
 573         struct drm_gem_vram_object *gbo;
 574         s64 gpu_addr;
 575         struct drm_framebuffer *fb = state->fb;
 576         struct drm_framebuffer *old_fb = old_state->fb;
 577
 578         if (!old_fb || (fb->format != old_fb->format)) {
 579                 struct drm_crtc_state *crtc_state = state->crtc->state;
 580                 struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);
 581                 struct ast_vbios_mode_info *vbios_mode_info = &ast_crtc_state->vbios_mode_info;
 582
 583                 ast_set_color_reg(ast, fb->format);
 584                 ast_set_vbios_color_reg(ast, fb->format, vbios_mode_info);
 585         }
 586
 587         gbo = drm_gem_vram_of_gem(fb->obj[0]);
 588         gpu_addr = drm_gem_vram_offset(gbo);
 589         if (drm_WARN_ON_ONCE(dev, gpu_addr < 0))
 590                 return; /* Bug: we didn't pin the BO to VRAM in prepare_fb. */
 591
 592         ast_set_offset_reg(ast, fb);
 593         ast_set_start_address_crt1(ast, (u32)gpu_addr);
 594
 595         ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x00);
 596 }
 597
 598 static void
 599 ast_primary_plane_helper_atomic_disable(struct drm_plane *plane,
 600                                         struct drm_plane_state *old_state)
 601 {
 602         struct ast_private *ast = to_ast_private(plane->dev);
 603
 604         ast_set_index_reg_mask(ast, AST_IO_SEQ_PORT, 0x1, 0xdf, 0x20);
 605 }
 606
 607 static const struct drm_plane_helper_funcs ast_primary_plane_helper_funcs = {
 608         .prepare_fb = drm_gem_vram_plane_helper_prepare_fb,
 609         .cleanup_fb = drm_gem_vram_plane_helper_cleanup_fb,
 610         .atomic_check = ast_primary_plane_helper_atomic_check,
 611         .atomic_update = ast_primary_plane_helper_atomic_update,
 612         .atomic_disable = ast_primary_plane_helper_atomic_disable,
 613 };
 614
 615 static const struct drm_plane_funcs ast_primary_plane_funcs = {
 616         .update_plane = drm_atomic_helper_update_plane,
 617         .disable_plane = drm_atomic_helper_disable_plane,
 618         .destroy = drm_plane_cleanup,
 619         .reset = drm_atomic_helper_plane_reset,
 620         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 621         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
 622 };
 623
 624 static int ast_primary_plane_init(struct ast_private *ast)
 625 {
 626         struct drm_device *dev = &ast->base;
 627         struct drm_plane *primary_plane = &ast->primary_plane;
 628         int ret;
 629
 630         ret = drm_universal_plane_init(dev, primary_plane, 0x01,
 631                                        &ast_primary_plane_funcs,
 632                                        ast_primary_plane_formats,
 633                                        ARRAY_SIZE(ast_primary_plane_formats),
 634                                        NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
 635         if (ret) {
 636                 drm_err(dev, "drm_universal_plane_init() failed: %d\n", ret);
 637                 return ret;
 638         }
 639         drm_plane_helper_add(primary_plane, &ast_primary_plane_helper_funcs);
 640
 641         return 0;
 642 }
 643
 644 /*
 645  * Cursor plane
 646  */
 647
 648 static void ast_update_cursor_image(u8 __iomem *dst, const u8 *src, int width, int height)
 649 {
 650         union {
 651                 u32 ul;
 652                 u8 b[4];
 653         } srcdata32[2], data32;
 654         union {
 655                 u16 us;
 656                 u8 b[2];
 657         } data16;
 658         u32 csum = 0;
 659         s32 alpha_dst_delta, last_alpha_dst_delta;
 660         u8 __iomem *dstxor;
 661         const u8 *srcxor;
 662         int i, j;
 663         u32 per_pixel_copy, two_pixel_copy;
 664
 665         alpha_dst_delta = AST_MAX_HWC_WIDTH << 1;
 666         last_alpha_dst_delta = alpha_dst_delta - (width << 1);
 667
 668         srcxor = src;
 669         dstxor = (u8 *)dst + last_alpha_dst_delta + (AST_MAX_HWC_HEIGHT - height) * alpha_dst_delta;
 670         per_pixel_copy = width & 1;
 671         two_pixel_copy = width >> 1;
 672
 673         for (j = 0; j < height; j++) {
 674                 for (i = 0; i < two_pixel_copy; i++) {
 675                         srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
 676                         srcdata32[1].ul = *((u32 *)(srcxor + 4)) & 0xf0f0f0f0;
 677                         data32.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
 678                         data32.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
 679                         data32.b[2] = srcdata32[1].b[1] | (srcdata32[1].b[0] >> 4);
 680                         data32.b[3] = srcdata32[1].b[3] | (srcdata32[1].b[2] >> 4);
 681
 682                         writel(data32.ul, dstxor);
 683                         csum += data32.ul;
 684
 685                         dstxor += 4;
 686                         srcxor += 8;
 687
 688                 }
 689
 690                 for (i = 0; i < per_pixel_copy; i++) {
 691                         srcdata32[0].ul = *((u32 *)srcxor) & 0xf0f0f0f0;
 692                         data16.b[0] = srcdata32[0].b[1] | (srcdata32[0].b[0] >> 4);
 693                         data16.b[1] = srcdata32[0].b[3] | (srcdata32[0].b[2] >> 4);
 694                         writew(data16.us, dstxor);
 695                         csum += (u32)data16.us;
 696
 697                         dstxor += 2;
 698                         srcxor += 4;
 699                 }
 700                 dstxor += last_alpha_dst_delta;
 701         }
 702
 703         /* write checksum + signature */
 704         dst += AST_HWC_SIZE;
 705         writel(csum, dst);
 706         writel(width, dst + AST_HWC_SIGNATURE_SizeX);
 707         writel(height, dst + AST_HWC_SIGNATURE_SizeY);
 708         writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTX);
 709         writel(0, dst + AST_HWC_SIGNATURE_HOTSPOTY);
 710 }
 711
 712 static void ast_set_cursor_base(struct ast_private *ast, u64 address)
 713 {
 714         u8 addr0 = (address >> 3) & 0xff;
 715         u8 addr1 = (address >> 11) & 0xff;
 716         u8 addr2 = (address >> 19) & 0xff;
 717
 718         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc8, addr0);
 719         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc9, addr1);
 720         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xca, addr2);
 721 }
 722
 723 static void ast_set_cursor_location(struct ast_private *ast, u16 x, u16 y,
 724                                     u8 x_offset, u8 y_offset)
 725 {
 726         u8 x0 = (x & 0x00ff);
 727         u8 x1 = (x & 0x0f00) >> 8;
 728         u8 y0 = (y & 0x00ff);
 729         u8 y1 = (y & 0x0700) >> 8;
 730
 731         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc2, x_offset);
 732         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc3, y_offset);
 733         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc4, x0);
 734         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc5, x1);
 735         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc6, y0);
 736         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xc7, y1);
 737 }
 738
 739 static void ast_set_cursor_enabled(struct ast_private *ast, bool enabled)
 740 {
 741         static const u8 mask = (u8)~(AST_IO_VGACRCB_HWC_16BPP |
 742                                      AST_IO_VGACRCB_HWC_ENABLED);
 743
 744         u8 vgacrcb = AST_IO_VGACRCB_HWC_16BPP;
 745
 746         if (enabled)
 747                 vgacrcb |= AST_IO_VGACRCB_HWC_ENABLED;
 748
 749         ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xcb, mask, vgacrcb);
 750 }
 751
 752 static const uint32_t ast_cursor_plane_formats[] = {
 753         DRM_FORMAT_ARGB8888,
 754 };
 755
 756 static int
 757 ast_cursor_plane_helper_prepare_fb(struct drm_plane *plane,
 758                                    struct drm_plane_state *new_state)
 759 {
 760         struct drm_framebuffer *fb = new_state->fb;
 761         struct ast_private *ast = to_ast_private(plane->dev);
 762         struct drm_gem_vram_object *dst_gbo = ast->cursor.gbo[ast->cursor.next_index];
 763         struct drm_gem_vram_object *src_gbo;
 764         struct dma_buf_map src_map, dst_map;
 765         void __iomem *dst;
 766         void *src;
 767         int ret;
 768
 769         if (!fb)
 770                 return 0;
 771
 772         src_gbo = drm_gem_vram_of_gem(fb->obj[0]);
 773
 774         ret = drm_gem_vram_vmap(src_gbo, &src_map);
 775         if (ret)
 776                 return ret;
 777         src = src_map.vaddr; /* TODO: Use mapping abstraction properly */
 778
 779         ret = drm_gem_vram_vmap(dst_gbo, &dst_map);
 780         if (ret)
 781                 goto err_drm_gem_vram_vunmap;
 782         dst = dst_map.vaddr_iomem; /* TODO: Use mapping abstraction properly */
 783
 784         /* do data transfer to cursor BO */
 785         ast_update_cursor_image(dst, src, fb->width, fb->height);
 786
 787         drm_gem_vram_vunmap(dst_gbo, &dst_map);
 788         drm_gem_vram_vunmap(src_gbo, &src_map);
 789
 790         return 0;
 791
 792 err_drm_gem_vram_vunmap:
 793         drm_gem_vram_vunmap(src_gbo, &src_map);
 794         return ret;
 795 }
 796
 797 static int ast_cursor_plane_helper_atomic_check(struct drm_plane *plane,
 798                                                 struct drm_plane_state *state)
 799 {
 800         struct drm_framebuffer *fb = state->fb;
 801         struct drm_crtc_state *crtc_state;
 802         int ret;
 803
 804         if (!state->crtc)
 805                 return 0;
 806
 807         crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc);
 808
 809         ret = drm_atomic_helper_check_plane_state(state, crtc_state,
 810                                                   DRM_PLANE_HELPER_NO_SCALING,
 811                                                   DRM_PLANE_HELPER_NO_SCALING,
 812                                                   true, true);
 813         if (ret)
 814                 return ret;
 815
 816         if (!state->visible)
 817                 return 0;
 818
 819         if (fb->width > AST_MAX_HWC_WIDTH || fb->height > AST_MAX_HWC_HEIGHT)
 820                 return -EINVAL;
 821
 822         return 0;
 823 }
 824
 825 static void
 826 ast_cursor_plane_helper_atomic_update(struct drm_plane *plane,
 827                                       struct drm_plane_state *old_state)
 828 {
 829         struct drm_plane_state *state = plane->state;
 830         struct drm_framebuffer *fb = state->fb;
 831         struct ast_private *ast = to_ast_private(plane->dev);
 832         struct drm_device *dev = &ast->base;
 833         struct drm_gem_vram_object *gbo = ast->cursor.gbo[ast->cursor.next_index];
 834         unsigned int offset_x, offset_y;
 835         s64 off;
 836         struct dma_buf_map map;
 837         u16 x, y;
 838         u8 x_offset, y_offset;
 839         u8 __iomem *dst;
 840         u8 __iomem *sig;
 841         int ret;
 842
 843         gbo = ast->cursor.gbo[ast->cursor.next_index];
 844
 845         if (state->fb != old_state->fb) {
 846                 /* A new cursor image was installed. */
 847                 off = drm_gem_vram_offset(gbo);
 848                 if (drm_WARN_ON_ONCE(dev, off < 0))
 849                         return; /* Bug: we didn't pin the cursor HW BO to VRAM. */
 850                 ast_set_cursor_base(ast, off);
 851
 852                 ++ast->cursor.next_index;
 853                 ast->cursor.next_index %= ARRAY_SIZE(ast->cursor.gbo);
 854         }
 855
 856         ret = drm_gem_vram_vmap(gbo, &map);
 857         if (drm_WARN_ONCE(dev, ret, "drm_gem_vram_vmap() failed, ret=%d\n", ret))
 858                 return;
 859         dst = map.vaddr_iomem; /* TODO: Use mapping abstraction properly */
 860
 861         sig = dst + AST_HWC_SIZE;
 862         writel(state->crtc_x, sig + AST_HWC_SIGNATURE_X);
 863         writel(state->crtc_y, sig + AST_HWC_SIGNATURE_Y);
 864
 865         drm_gem_vram_vunmap(gbo, &map);
 866
 867         offset_x = AST_MAX_HWC_WIDTH - fb->width;
 868         offset_y = AST_MAX_HWC_HEIGHT - fb->height;
 869
 870         if (state->crtc_x < 0) {
 871                 x_offset = (-state->crtc_x) + offset_x;
 872                 x = 0;
 873         } else {
 874                 x_offset = offset_x;
 875                 x = state->crtc_x;
 876         }
 877         if (state->crtc_y < 0) {
 878                 y_offset = (-state->crtc_y) + offset_y;
 879                 y = 0;
 880         } else {
 881                 y_offset = offset_y;
 882                 y = state->crtc_y;
 883         }
 884
 885         ast_set_cursor_location(ast, x, y, x_offset, y_offset);
 886
 887         /* dummy write to fire HWC */
 888         ast_set_cursor_enabled(ast, true);
 889 }
 890
 891 static void
 892 ast_cursor_plane_helper_atomic_disable(struct drm_plane *plane,
 893                                        struct drm_plane_state *old_state)
 894 {
 895         struct ast_private *ast = to_ast_private(plane->dev);
 896
 897         ast_set_cursor_enabled(ast, false);
 898 }
 899
 900 static const struct drm_plane_helper_funcs ast_cursor_plane_helper_funcs = {
 901         .prepare_fb = ast_cursor_plane_helper_prepare_fb,
 902         .cleanup_fb = NULL, /* not required for cursor plane */
 903         .atomic_check = ast_cursor_plane_helper_atomic_check,
 904         .atomic_update = ast_cursor_plane_helper_atomic_update,
 905         .atomic_disable = ast_cursor_plane_helper_atomic_disable,
 906 };
 907
 908 static void ast_cursor_plane_destroy(struct drm_plane *plane)
 909 {
 910         struct ast_private *ast = to_ast_private(plane->dev);
 911         size_t i;
 912         struct drm_gem_vram_object *gbo;
 913
 914         for (i = 0; i < ARRAY_SIZE(ast->cursor.gbo); ++i) {
 915                 gbo = ast->cursor.gbo[i];
 916                 drm_gem_vram_unpin(gbo);
 917                 drm_gem_vram_put(gbo);
 918         }
 919
 920         drm_plane_cleanup(plane);
 921 }
 922
 923 static const struct drm_plane_funcs ast_cursor_plane_funcs = {
 924         .update_plane = drm_atomic_helper_update_plane,
 925         .disable_plane = drm_atomic_helper_disable_plane,
 926         .destroy = ast_cursor_plane_destroy,
 927         .reset = drm_atomic_helper_plane_reset,
 928         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 929         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
 930 };
 931
 932 static int ast_cursor_plane_init(struct ast_private *ast)
 933 {
 934         struct drm_device *dev = &ast->base;
 935         struct drm_plane *cursor_plane = &ast->cursor_plane;
 936         size_t size, i;
 937         struct drm_gem_vram_object *gbo;
 938         int ret;
 939
 940         /*
 941          * Allocate backing storage for cursors. The BOs are permanently
 942          * pinned to the top end of the VRAM.
 943          */
 944
 945         size = roundup(AST_HWC_SIZE + AST_HWC_SIGNATURE_SIZE, PAGE_SIZE);
 946
 947         for (i = 0; i < ARRAY_SIZE(ast->cursor.gbo); ++i) {
 948                 gbo = drm_gem_vram_create(dev, size, 0);
 949                 if (IS_ERR(gbo)) {
 950                         ret = PTR_ERR(gbo);
 951                         goto err_hwc;
 952                 }
 953                 ret = drm_gem_vram_pin(gbo, DRM_GEM_VRAM_PL_FLAG_VRAM |
 954                                             DRM_GEM_VRAM_PL_FLAG_TOPDOWN);
 955                 if (ret)
 956                         goto err_drm_gem_vram_put;
 957                 ast->cursor.gbo[i] = gbo;
 958         }
 959
 960         /*
 961          * Create the cursor plane. The plane's destroy callback will release
 962          * the backing storages' BO memory.
 963          */
 964
 965         ret = drm_universal_plane_init(dev, cursor_plane, 0x01,
 966                                        &ast_cursor_plane_funcs,
 967                                        ast_cursor_plane_formats,
 968                                        ARRAY_SIZE(ast_cursor_plane_formats),
 969                                        NULL, DRM_PLANE_TYPE_CURSOR, NULL);
 970         if (ret) {
 971                 drm_err(dev, "drm_universal_plane failed(): %d\n", ret);
 972                 goto err_hwc;
 973         }
 974         drm_plane_helper_add(cursor_plane, &ast_cursor_plane_helper_funcs);
 975
 976         return 0;
 977
 978 err_hwc:
 979         while (i) {
 980                 --i;
 981                 gbo = ast->cursor.gbo[i];
 982                 drm_gem_vram_unpin(gbo);
 983 err_drm_gem_vram_put:
 984                 drm_gem_vram_put(gbo);
 985         }
 986         return ret;
 987 }
 988
 989 /*
 990  * CRTC
 991  */
 992
 993 static void ast_crtc_dpms(struct drm_crtc *crtc, int mode)
 994 {
 995         struct ast_private *ast = to_ast_private(crtc->dev);
 996
 997         /* TODO: Maybe control display signal generation with
 998          *       Sync Enable (bit CR17.7).
 999          */
1000         switch (mode) {
1001         case DRM_MODE_DPMS_ON:
1002         case DRM_MODE_DPMS_STANDBY:
1003         case DRM_MODE_DPMS_SUSPEND:
1004                 if (ast->tx_chip_type == AST_TX_DP501)
1005                         ast_set_dp501_video_output(crtc->dev, 1);
1006                 break;
1007         case DRM_MODE_DPMS_OFF:
1008                 if (ast->tx_chip_type == AST_TX_DP501)
1009                         ast_set_dp501_video_output(crtc->dev, 0);
1010                 break;
1011         }
1012 }
1013
1014 static int ast_crtc_helper_atomic_check(struct drm_crtc *crtc,
1015                                         struct drm_atomic_state *state)
1016 {
1017         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1018                                                                           crtc);
1019         struct drm_device *dev = crtc->dev;
1020         struct ast_crtc_state *ast_state;
1021         const struct drm_format_info *format;
1022         bool succ;
1023
1024         if (!crtc_state->enable)
1025                 return 0; /* no mode checks if CRTC is being disabled */
1026
1027         ast_state = to_ast_crtc_state(crtc_state);
1028
1029         format = ast_state->format;
1030         if (drm_WARN_ON_ONCE(dev, !format))
1031                 return -EINVAL; /* BUG: We didn't set format in primary check(). */
1032
1033         succ = ast_get_vbios_mode_info(format, &crtc_state->mode,
1034                                        &crtc_state->adjusted_mode,
1035                                        &ast_state->vbios_mode_info);
1036         if (!succ)
1037                 return -EINVAL;
1038
1039         return 0;
1040 }
1041
1042 static void
1043 ast_crtc_helper_atomic_flush(struct drm_crtc *crtc,
1044                              struct drm_atomic_state *state)
1045 {
1046         struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
1047                                                                           crtc);
1048         struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1049                                                                               crtc);
1050         struct ast_private *ast = to_ast_private(crtc->dev);
1051         struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);
1052         struct ast_crtc_state *old_ast_crtc_state = to_ast_crtc_state(old_crtc_state);
1053
1054         /*
1055          * The gamma LUT has to be reloaded after changing the primary
1056          * plane's color format.
1057          */
1058         if (old_ast_crtc_state->format != ast_crtc_state->format)
1059                 ast_crtc_load_lut(ast, crtc);
1060 }
1061
1062 static void
1063 ast_crtc_helper_atomic_enable(struct drm_crtc *crtc,
1064                               struct drm_atomic_state *state)
1065 {
1066         struct drm_device *dev = crtc->dev;
1067         struct ast_private *ast = to_ast_private(dev);
1068         struct drm_crtc_state *crtc_state = crtc->state;
1069         struct ast_crtc_state *ast_crtc_state = to_ast_crtc_state(crtc_state);
1070         struct ast_vbios_mode_info *vbios_mode_info =
1071                 &ast_crtc_state->vbios_mode_info;
1072         struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode;
1073
1074         ast_set_vbios_mode_reg(ast, adjusted_mode, vbios_mode_info);
1075         ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0xa1, 0x06);
1076         ast_set_std_reg(ast, adjusted_mode, vbios_mode_info);
1077         ast_set_crtc_reg(ast, adjusted_mode, vbios_mode_info);
1078         ast_set_dclk_reg(ast, adjusted_mode, vbios_mode_info);
1079         ast_set_crtthd_reg(ast);
1080         ast_set_sync_reg(ast, adjusted_mode, vbios_mode_info);
1081
1082         ast_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1083 }
1084
1085 static void
1086 ast_crtc_helper_atomic_disable(struct drm_crtc *crtc,
1087                                struct drm_atomic_state *state)
1088 {
1089         struct drm_crtc_state *old_crtc_state = drm_atomic_get_old_crtc_state(state,
1090                                                                               crtc);
1091         struct drm_device *dev = crtc->dev;
1092         struct ast_private *ast = to_ast_private(dev);
1093
1094         ast_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1095
1096         /*
1097          * HW cursors require the underlying primary plane and CRTC to
1098          * display a valid mode and image. This is not the case during
1099          * full modeset operations. So we temporarily disable any active
1100          * plane, including the HW cursor. Each plane's atomic_update()
1101          * helper will re-enable it if necessary.
1102          *
1103          * We only do this during *full* modesets. It does not affect
1104          * simple pageflips on the planes.
1105          */
1106         drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, false);
1107
1108         /*
1109          * Ensure that no scanout takes place before reprogramming mode
1110          * and format registers.
1111          */
1112         ast_wait_for_vretrace(ast);
1113 }
1114
1115 static const struct drm_crtc_helper_funcs ast_crtc_helper_funcs = {
1116         .atomic_check = ast_crtc_helper_atomic_check,
1117         .atomic_flush = ast_crtc_helper_atomic_flush,
1118         .atomic_enable = ast_crtc_helper_atomic_enable,
1119         .atomic_disable = ast_crtc_helper_atomic_disable,
1120 };
1121
1122 static void ast_crtc_reset(struct drm_crtc *crtc)
1123 {
1124         struct ast_crtc_state *ast_state =
1125                 kzalloc(sizeof(*ast_state), GFP_KERNEL);
1126
1127         if (crtc->state)
1128                 crtc->funcs->atomic_destroy_state(crtc, crtc->state);
1129
1130         __drm_atomic_helper_crtc_reset(crtc, &ast_state->base);
1131 }
1132
1133 static struct drm_crtc_state *
1134 ast_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1135 {
1136         struct ast_crtc_state *new_ast_state, *ast_state;
1137         struct drm_device *dev = crtc->dev;
1138
1139         if (drm_WARN_ON(dev, !crtc->state))
1140                 return NULL;
1141
1142         new_ast_state = kmalloc(sizeof(*new_ast_state), GFP_KERNEL);
1143         if (!new_ast_state)
1144                 return NULL;
1145         __drm_atomic_helper_crtc_duplicate_state(crtc, &new_ast_state->base);
1146
1147         ast_state = to_ast_crtc_state(crtc->state);
1148
1149         new_ast_state->format = ast_state->format;
1150         memcpy(&new_ast_state->vbios_mode_info, &ast_state->vbios_mode_info,
1151                sizeof(new_ast_state->vbios_mode_info));
1152
1153         return &new_ast_state->base;
1154 }
1155
1156 static void ast_crtc_atomic_destroy_state(struct drm_crtc *crtc,
1157                                           struct drm_crtc_state *state)
1158 {
1159         struct ast_crtc_state *ast_state = to_ast_crtc_state(state);
1160
1161         __drm_atomic_helper_crtc_destroy_state(&ast_state->base);
1162         kfree(ast_state);
1163 }
1164
1165 static const struct drm_crtc_funcs ast_crtc_funcs = {
1166         .reset = ast_crtc_reset,
1167         .destroy = drm_crtc_cleanup,
1168         .set_config = drm_atomic_helper_set_config,
1169         .page_flip = drm_atomic_helper_page_flip,
1170         .atomic_duplicate_state = ast_crtc_atomic_duplicate_state,
1171         .atomic_destroy_state = ast_crtc_atomic_destroy_state,
1172 };
1173
1174 static int ast_crtc_init(struct drm_device *dev)
1175 {
1176         struct ast_private *ast = to_ast_private(dev);
1177         struct drm_crtc *crtc = &ast->crtc;
1178         int ret;
1179
1180         ret = drm_crtc_init_with_planes(dev, crtc, &ast->primary_plane,
1181                                         &ast->cursor_plane, &ast_crtc_funcs,
1182                                         NULL);
1183         if (ret)
1184                 return ret;
1185
1186         drm_mode_crtc_set_gamma_size(crtc, 256);
1187         drm_crtc_helper_add(crtc, &ast_crtc_helper_funcs);
1188
1189         return 0;
1190 }
1191
1192 /*
1193  * Encoder
1194  */
1195
1196 static int ast_encoder_init(struct drm_device *dev)
1197 {
1198         struct ast_private *ast = to_ast_private(dev);
1199         struct drm_encoder *encoder = &ast->encoder;
1200         int ret;
1201
1202         ret = drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_DAC);
1203         if (ret)
1204                 return ret;
1205
1206         encoder->possible_crtcs = 1;
1207
1208         return 0;
1209 }
1210
1211 /*
1212  * Connector
1213  */
1214
1215 static int ast_get_modes(struct drm_connector *connector)
1216 {
1217         struct ast_connector *ast_connector = to_ast_connector(connector);
1218         struct ast_private *ast = to_ast_private(connector->dev);
1219         struct edid *edid;
1220         int ret;
1221         bool flags = false;
1222         if (ast->tx_chip_type == AST_TX_DP501) {
1223                 ast->dp501_maxclk = 0xff;
1224                 edid = kmalloc(128, GFP_KERNEL);
1225                 if (!edid)
1226                         return -ENOMEM;
1227
1228                 flags = ast_dp501_read_edid(connector->dev, (u8 *)edid);
1229                 if (flags)
1230                         ast->dp501_maxclk = ast_get_dp501_max_clk(connector->dev);
1231                 else
1232                         kfree(edid);
1233         }
1234         if (!flags)
1235                 edid = drm_get_edid(connector, &ast_connector->i2c->adapter);
1236         if (edid) {
1237                 drm_connector_update_edid_property(&ast_connector->base, edid);
1238                 ret = drm_add_edid_modes(connector, edid);
1239                 kfree(edid);
1240                 return ret;
1241         } else
1242                 drm_connector_update_edid_property(&ast_connector->base, NULL);
1243         return 0;
1244 }
1245
1246 static enum drm_mode_status ast_mode_valid(struct drm_connector *connector,
1247                           struct drm_display_mode *mode)
1248 {
1249         struct ast_private *ast = to_ast_private(connector->dev);
1250         int flags = MODE_NOMODE;
1251         uint32_t jtemp;
1252
1253         if (ast->support_wide_screen) {
1254                 if ((mode->hdisplay == 1680) && (mode->vdisplay == 1050))
1255                         return MODE_OK;
1256                 if ((mode->hdisplay == 1280) && (mode->vdisplay == 800))
1257                         return MODE_OK;
1258                 if ((mode->hdisplay == 1440) && (mode->vdisplay == 900))
1259                         return MODE_OK;
1260                 if ((mode->hdisplay == 1360) && (mode->vdisplay == 768))
1261                         return MODE_OK;
1262                 if ((mode->hdisplay == 1600) && (mode->vdisplay == 900))
1263                         return MODE_OK;
1264
1265                 if ((ast->chip == AST2100) || (ast->chip == AST2200) ||
1266                     (ast->chip == AST2300) || (ast->chip == AST2400) ||
1267                     (ast->chip == AST2500)) {
1268                         if ((mode->hdisplay == 1920) && (mode->vdisplay == 1080))
1269                                 return MODE_OK;
1270
1271                         if ((mode->hdisplay == 1920) && (mode->vdisplay == 1200)) {
1272                                 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xd1, 0xff);
1273                                 if (jtemp & 0x01)
1274                                         return MODE_NOMODE;
1275                                 else
1276                                         return MODE_OK;
1277                         }
1278                 }
1279         }
1280         switch (mode->hdisplay) {
1281         case 640:
1282                 if (mode->vdisplay == 480) flags = MODE_OK;
1283                 break;
1284         case 800:
1285                 if (mode->vdisplay == 600) flags = MODE_OK;
1286                 break;
1287         case 1024:
1288                 if (mode->vdisplay == 768) flags = MODE_OK;
1289                 break;
1290         case 1280:
1291                 if (mode->vdisplay == 1024) flags = MODE_OK;
1292                 break;
1293         case 1600:
1294                 if (mode->vdisplay == 1200) flags = MODE_OK;
1295                 break;
1296         default:
1297                 return flags;
1298         }
1299
1300         return flags;
1301 }
1302
1303 static void ast_connector_destroy(struct drm_connector *connector)
1304 {
1305         struct ast_connector *ast_connector = to_ast_connector(connector);
1306         ast_i2c_destroy(ast_connector->i2c);
1307         drm_connector_cleanup(connector);
1308 }
1309
1310 static const struct drm_connector_helper_funcs ast_connector_helper_funcs = {
1311         .get_modes = ast_get_modes,
1312         .mode_valid = ast_mode_valid,
1313 };
1314
1315 static const struct drm_connector_funcs ast_connector_funcs = {
1316         .reset = drm_atomic_helper_connector_reset,
1317         .fill_modes = drm_helper_probe_single_connector_modes,
1318         .destroy = ast_connector_destroy,
1319         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1320         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1321 };
1322
1323 static int ast_connector_init(struct drm_device *dev)
1324 {
1325         struct ast_private *ast = to_ast_private(dev);
1326         struct ast_connector *ast_connector = &ast->connector;
1327         struct drm_connector *connector = &ast_connector->base;
1328         struct drm_encoder *encoder = &ast->encoder;
1329
1330         ast_connector->i2c = ast_i2c_create(dev);
1331         if (!ast_connector->i2c)
1332                 drm_err(dev, "failed to add ddc bus for connector\n");
1333
1334         drm_connector_init_with_ddc(dev, connector,
1335                                     &ast_connector_funcs,
1336                                     DRM_MODE_CONNECTOR_VGA,
1337                                     &ast_connector->i2c->adapter);
1338
1339         drm_connector_helper_add(connector, &ast_connector_helper_funcs);
1340
1341         connector->interlace_allowed = 0;
1342         connector->doublescan_allowed = 0;
1343
1344         connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1345
1346         drm_connector_attach_encoder(connector, encoder);
1347
1348         return 0;
1349 }
1350
1351 /*
1352  * Mode config
1353  */
1354
1355 static const struct drm_mode_config_helper_funcs
1356 ast_mode_config_helper_funcs = {
1357         .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm,
1358 };
1359
1360 static const struct drm_mode_config_funcs ast_mode_config_funcs = {
1361         .fb_create = drm_gem_fb_create,
1362         .mode_valid = drm_vram_helper_mode_valid,
1363         .atomic_check = drm_atomic_helper_check,
1364         .atomic_commit = drm_atomic_helper_commit,
1365 };
1366
1367 int ast_mode_config_init(struct ast_private *ast)
1368 {
1369         struct drm_device *dev = &ast->base;
1370         struct pci_dev *pdev = to_pci_dev(dev->dev);
1371         int ret;
1372
1373         ret = drmm_mode_config_init(dev);
1374         if (ret)
1375                 return ret;
1376
1377         dev->mode_config.funcs = &ast_mode_config_funcs;
1378         dev->mode_config.min_width = 0;
1379         dev->mode_config.min_height = 0;
1380         dev->mode_config.preferred_depth = 24;
1381         dev->mode_config.prefer_shadow = 1;
1382         dev->mode_config.fb_base = pci_resource_start(pdev, 0);
1383
1384         if (ast->chip == AST2100 ||
1385             ast->chip == AST2200 ||
1386             ast->chip == AST2300 ||
1387             ast->chip == AST2400 ||
1388             ast->chip == AST2500) {
1389                 dev->mode_config.max_width = 1920;
1390                 dev->mode_config.max_height = 2048;
1391         } else {
1392                 dev->mode_config.max_width = 1600;
1393                 dev->mode_config.max_height = 1200;
1394         }
1395
1396         dev->mode_config.helper_private = &ast_mode_config_helper_funcs;
1397
1398
1399         ret = ast_primary_plane_init(ast);
1400         if (ret)
1401                 return ret;
1402
1403         ret = ast_cursor_plane_init(ast);
1404         if (ret)
1405                 return ret;
1406
1407         ast_crtc_init(dev);
1408         ast_encoder_init(dev);
1409         ast_connector_init(dev);
1410
1411         drm_mode_config_reset(dev);
1412
1413         return 0;
1414 }
1415
1416 static int get_clock(void *i2c_priv)
1417 {
1418         struct ast_i2c_chan *i2c = i2c_priv;
1419         struct ast_private *ast = to_ast_private(i2c->dev);
1420         uint32_t val, val2, count, pass;
1421
1422         count = 0;
1423         pass = 0;
1424         val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
1425         do {
1426                 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
1427                 if (val == val2) {
1428                         pass++;
1429                 } else {
1430                         pass = 0;
1431                         val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x10) >> 4) & 0x01;
1432                 }
1433         } while ((pass < 5) && (count++ < 0x10000));
1434
1435         return val & 1 ? 1 : 0;
1436 }
1437
1438 static int get_data(void *i2c_priv)
1439 {
1440         struct ast_i2c_chan *i2c = i2c_priv;
1441         struct ast_private *ast = to_ast_private(i2c->dev);
1442         uint32_t val, val2, count, pass;
1443
1444         count = 0;
1445         pass = 0;
1446         val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
1447         do {
1448                 val2 = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
1449                 if (val == val2) {
1450                         pass++;
1451                 } else {
1452                         pass = 0;
1453                         val = (ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x20) >> 5) & 0x01;
1454                 }
1455         } while ((pass < 5) && (count++ < 0x10000));
1456
1457         return val & 1 ? 1 : 0;
1458 }
1459
1460 static void set_clock(void *i2c_priv, int clock)
1461 {
1462         struct ast_i2c_chan *i2c = i2c_priv;
1463         struct ast_private *ast = to_ast_private(i2c->dev);
1464         int i;
1465         u8 ujcrb7, jtemp;
1466
1467         for (i = 0; i < 0x10000; i++) {
1468                 ujcrb7 = ((clock & 0x01) ? 0 : 1);
1469                 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf4, ujcrb7);
1470                 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x01);
1471                 if (ujcrb7 == jtemp)
1472                         break;
1473         }
1474 }
1475
1476 static void set_data(void *i2c_priv, int data)
1477 {
1478         struct ast_i2c_chan *i2c = i2c_priv;
1479         struct ast_private *ast = to_ast_private(i2c->dev);
1480         int i;
1481         u8 ujcrb7, jtemp;
1482
1483         for (i = 0; i < 0x10000; i++) {
1484                 ujcrb7 = ((data & 0x01) ? 0 : 1) << 2;
1485                 ast_set_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0xf1, ujcrb7);
1486                 jtemp = ast_get_index_reg_mask(ast, AST_IO_CRTC_PORT, 0xb7, 0x04);
1487                 if (ujcrb7 == jtemp)
1488                         break;
1489         }
1490 }
1491
1492 static struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev)
1493 {
1494         struct ast_i2c_chan *i2c;
1495         int ret;
1496
1497         i2c = kzalloc(sizeof(struct ast_i2c_chan), GFP_KERNEL);
1498         if (!i2c)
1499                 return NULL;
1500
1501         i2c->adapter.owner = THIS_MODULE;
1502         i2c->adapter.class = I2C_CLASS_DDC;
1503         i2c->adapter.dev.parent = dev->dev;
1504         i2c->dev = dev;
1505         i2c_set_adapdata(&i2c->adapter, i2c);
1506         snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
1507                  "AST i2c bit bus");
1508         i2c->adapter.algo_data = &i2c->bit;
1509
1510         i2c->bit.udelay = 20;
1511         i2c->bit.timeout = 2;
1512         i2c->bit.data = i2c;
1513         i2c->bit.setsda = set_data;
1514         i2c->bit.setscl = set_clock;
1515         i2c->bit.getsda = get_data;
1516         i2c->bit.getscl = get_clock;
1517         ret = i2c_bit_add_bus(&i2c->adapter);
1518         if (ret) {
1519                 drm_err(dev, "Failed to register bit i2c\n");
1520                 goto out_free;
1521         }
1522
1523         return i2c;
1524 out_free:
1525         kfree(i2c);
1526         return NULL;
1527 }
1528
1529 static void ast_i2c_destroy(struct ast_i2c_chan *i2c)
1530 {
1531         if (!i2c)
1532                 return;
1533         i2c_del_adapter(&i2c->adapter);
1534         kfree(i2c);
1535 }