drivers/gpu/drm/arm/malidp_drv.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
   4  * Author: Liviu Dudau <Liviu.Dudau@arm.com>
   5  *
   6  * ARM Mali DP500/DP550/DP650 KMS/DRM driver
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/clk.h>
  11 #include <linux/component.h>
  12 #include <linux/of_device.h>
  13 #include <linux/of_graph.h>
  14 #include <linux/of_reserved_mem.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/debugfs.h>
  17
  18 #include <drm/drmP.h>
  19 #include <drm/drm_atomic.h>
  20 #include <drm/drm_atomic_helper.h>
  21 #include <drm/drm_crtc.h>
  22 #include <drm/drm_probe_helper.h>
  23 #include <drm/drm_fb_helper.h>
  24 #include <drm/drm_fb_cma_helper.h>
  25 #include <drm/drm_gem_cma_helper.h>
  26 #include <drm/drm_gem_framebuffer_helper.h>
  27 #include <drm/drm_modeset_helper.h>
  28 #include <drm/drm_of.h>
  29
  30 #include "malidp_drv.h"
  31 #include "malidp_mw.h"
  32 #include "malidp_regs.h"
  33 #include "malidp_hw.h"
  34
  35 #define MALIDP_CONF_VALID_TIMEOUT       250
  36 #define AFBC_HEADER_SIZE                16
  37 #define AFBC_SUPERBLK_ALIGNMENT         128
  38
  39 static void malidp_write_gamma_table(struct malidp_hw_device *hwdev,
  40                                      u32 data[MALIDP_COEFFTAB_NUM_COEFFS])
  41 {
  42         int i;
  43         /* Update all channels with a single gamma curve. */
  44         const u32 gamma_write_mask = GENMASK(18, 16);
  45         /*
  46          * Always write an entire table, so the address field in
  47          * DE_COEFFTAB_ADDR is 0 and we can use the gamma_write_mask bitmask
  48          * directly.
  49          */
  50         malidp_hw_write(hwdev, gamma_write_mask,
  51                         hwdev->hw->map.coeffs_base + MALIDP_COEF_TABLE_ADDR);
  52         for (i = 0; i < MALIDP_COEFFTAB_NUM_COEFFS; ++i)
  53                 malidp_hw_write(hwdev, data[i],
  54                                 hwdev->hw->map.coeffs_base +
  55                                 MALIDP_COEF_TABLE_DATA);
  56 }
  57
  58 static void malidp_atomic_commit_update_gamma(struct drm_crtc *crtc,
  59                                               struct drm_crtc_state *old_state)
  60 {
  61         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  62         struct malidp_hw_device *hwdev = malidp->dev;
  63
  64         if (!crtc->state->color_mgmt_changed)
  65                 return;
  66
  67         if (!crtc->state->gamma_lut) {
  68                 malidp_hw_clearbits(hwdev,
  69                                     MALIDP_DISP_FUNC_GAMMA,
  70                                     MALIDP_DE_DISPLAY_FUNC);
  71         } else {
  72                 struct malidp_crtc_state *mc =
  73                         to_malidp_crtc_state(crtc->state);
  74
  75                 if (!old_state->gamma_lut || (crtc->state->gamma_lut->base.id !=
  76                                               old_state->gamma_lut->base.id))
  77                         malidp_write_gamma_table(hwdev, mc->gamma_coeffs);
  78
  79                 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_GAMMA,
  80                                   MALIDP_DE_DISPLAY_FUNC);
  81         }
  82 }
  83
  84 static
  85 void malidp_atomic_commit_update_coloradj(struct drm_crtc *crtc,
  86                                           struct drm_crtc_state *old_state)
  87 {
  88         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  89         struct malidp_hw_device *hwdev = malidp->dev;
  90         int i;
  91
  92         if (!crtc->state->color_mgmt_changed)
  93                 return;
  94
  95         if (!crtc->state->ctm) {
  96                 malidp_hw_clearbits(hwdev, MALIDP_DISP_FUNC_CADJ,
  97                                     MALIDP_DE_DISPLAY_FUNC);
  98         } else {
  99                 struct malidp_crtc_state *mc =
 100                         to_malidp_crtc_state(crtc->state);
 101
 102                 if (!old_state->ctm || (crtc->state->ctm->base.id !=
 103                                         old_state->ctm->base.id))
 104                         for (i = 0; i < MALIDP_COLORADJ_NUM_COEFFS; ++i)
 105                                 malidp_hw_write(hwdev,
 106                                                 mc->coloradj_coeffs[i],
 107                                                 hwdev->hw->map.coeffs_base +
 108                                                 MALIDP_COLOR_ADJ_COEF + 4 * i);
 109
 110                 malidp_hw_setbits(hwdev, MALIDP_DISP_FUNC_CADJ,
 111                                   MALIDP_DE_DISPLAY_FUNC);
 112         }
 113 }
 114
 115 static void malidp_atomic_commit_se_config(struct drm_crtc *crtc,
 116                                            struct drm_crtc_state *old_state)
 117 {
 118         struct malidp_crtc_state *cs = to_malidp_crtc_state(crtc->state);
 119         struct malidp_crtc_state *old_cs = to_malidp_crtc_state(old_state);
 120         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
 121         struct malidp_hw_device *hwdev = malidp->dev;
 122         struct malidp_se_config *s = &cs->scaler_config;
 123         struct malidp_se_config *old_s = &old_cs->scaler_config;
 124         u32 se_control = hwdev->hw->map.se_base +
 125                          ((hwdev->hw->map.features & MALIDP_REGMAP_HAS_CLEARIRQ) ?
 126                          0x10 : 0xC);
 127         u32 layer_control = se_control + MALIDP_SE_LAYER_CONTROL;
 128         u32 scr = se_control + MALIDP_SE_SCALING_CONTROL;
 129         u32 val;
 130
 131         /* Set SE_CONTROL */
 132         if (!s->scale_enable) {
 133                 val = malidp_hw_read(hwdev, se_control);
 134                 val &= ~MALIDP_SE_SCALING_EN;
 135                 malidp_hw_write(hwdev, val, se_control);
 136                 return;
 137         }
 138
 139         hwdev->hw->se_set_scaling_coeffs(hwdev, s, old_s);
 140         val = malidp_hw_read(hwdev, se_control);
 141         val |= MALIDP_SE_SCALING_EN | MALIDP_SE_ALPHA_EN;
 142
 143         val &= ~MALIDP_SE_ENH(MALIDP_SE_ENH_MASK);
 144         val |= s->enhancer_enable ? MALIDP_SE_ENH(3) : 0;
 145
 146         val |= MALIDP_SE_RGBO_IF_EN;
 147         malidp_hw_write(hwdev, val, se_control);
 148
 149         /* Set IN_SIZE & OUT_SIZE. */
 150         val = MALIDP_SE_SET_V_SIZE(s->input_h) |
 151               MALIDP_SE_SET_H_SIZE(s->input_w);
 152         malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_IN_SIZE);
 153         val = MALIDP_SE_SET_V_SIZE(s->output_h) |
 154               MALIDP_SE_SET_H_SIZE(s->output_w);
 155         malidp_hw_write(hwdev, val, layer_control + MALIDP_SE_L0_OUT_SIZE);
 156
 157         /* Set phase regs. */
 158         malidp_hw_write(hwdev, s->h_init_phase, scr + MALIDP_SE_H_INIT_PH);
 159         malidp_hw_write(hwdev, s->h_delta_phase, scr + MALIDP_SE_H_DELTA_PH);
 160         malidp_hw_write(hwdev, s->v_init_phase, scr + MALIDP_SE_V_INIT_PH);
 161         malidp_hw_write(hwdev, s->v_delta_phase, scr + MALIDP_SE_V_DELTA_PH);
 162 }
 163
 164 /*
 165  * set the "config valid" bit and wait until the hardware acts on it
 166  */
 167 static int malidp_set_and_wait_config_valid(struct drm_device *drm)
 168 {
 169         struct malidp_drm *malidp = drm->dev_private;
 170         struct malidp_hw_device *hwdev = malidp->dev;
 171         int ret;
 172
 173         hwdev->hw->set_config_valid(hwdev, 1);
 174         /* don't wait for config_valid flag if we are in config mode */
 175         if (hwdev->hw->in_config_mode(hwdev)) {
 176                 atomic_set(&malidp->config_valid, MALIDP_CONFIG_VALID_DONE);
 177                 return 0;
 178         }
 179
 180         ret = wait_event_interruptible_timeout(malidp->wq,
 181                         atomic_read(&malidp->config_valid) == MALIDP_CONFIG_VALID_DONE,
 182                         msecs_to_jiffies(MALIDP_CONF_VALID_TIMEOUT));
 183
 184         return (ret > 0) ? 0 : -ETIMEDOUT;
 185 }
 186
 187 static void malidp_atomic_commit_hw_done(struct drm_atomic_state *state)
 188 {
 189         struct drm_device *drm = state->dev;
 190         struct malidp_drm *malidp = drm->dev_private;
 191         int loop = 5;
 192
 193         malidp->event = malidp->crtc.state->event;
 194         malidp->crtc.state->event = NULL;
 195
 196         if (malidp->crtc.state->active) {
 197                 /*
 198                  * if we have an event to deliver to userspace, make sure
 199                  * the vblank is enabled as we are sending it from the IRQ
 200                  * handler.
 201                  */
 202                 if (malidp->event)
 203                         drm_crtc_vblank_get(&malidp->crtc);
 204
 205                 /* only set config_valid if the CRTC is enabled */
 206                 if (malidp_set_and_wait_config_valid(drm) < 0) {
 207                         /*
 208                          * make a loop around the second CVAL setting and
 209                          * try 5 times before giving up.
 210                          */
 211                         while (loop--) {
 212                                 if (!malidp_set_and_wait_config_valid(drm))
 213                                         break;
 214                         }
 215                         DRM_DEBUG_DRIVER("timed out waiting for updated configuration\n");
 216                 }
 217
 218         } else if (malidp->event) {
 219                 /* CRTC inactive means vblank IRQ is disabled, send event directly */
 220                 spin_lock_irq(&drm->event_lock);
 221                 drm_crtc_send_vblank_event(&malidp->crtc, malidp->event);
 222                 malidp->event = NULL;
 223                 spin_unlock_irq(&drm->event_lock);
 224         }
 225         drm_atomic_helper_commit_hw_done(state);
 226 }
 227
 228 static void malidp_atomic_commit_tail(struct drm_atomic_state *state)
 229 {
 230         struct drm_device *drm = state->dev;
 231         struct malidp_drm *malidp = drm->dev_private;
 232         struct drm_crtc *crtc;
 233         struct drm_crtc_state *old_crtc_state;
 234         int i;
 235
 236         pm_runtime_get_sync(drm->dev);
 237
 238         /*
 239          * set config_valid to a special value to let IRQ handlers
 240          * know that we are updating registers
 241          */
 242         atomic_set(&malidp->config_valid, MALIDP_CONFIG_START);
 243         malidp->dev->hw->set_config_valid(malidp->dev, 0);
 244
 245         drm_atomic_helper_commit_modeset_disables(drm, state);
 246
 247         for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
 248                 malidp_atomic_commit_update_gamma(crtc, old_crtc_state);
 249                 malidp_atomic_commit_update_coloradj(crtc, old_crtc_state);
 250                 malidp_atomic_commit_se_config(crtc, old_crtc_state);
 251         }
 252
 253         drm_atomic_helper_commit_planes(drm, state, DRM_PLANE_COMMIT_ACTIVE_ONLY);
 254
 255         malidp_mw_atomic_commit(drm, state);
 256
 257         drm_atomic_helper_commit_modeset_enables(drm, state);
 258
 259         malidp_atomic_commit_hw_done(state);
 260
 261         pm_runtime_put(drm->dev);
 262
 263         drm_atomic_helper_cleanup_planes(drm, state);
 264 }
 265
 266 static const struct drm_mode_config_helper_funcs malidp_mode_config_helpers = {
 267         .atomic_commit_tail = malidp_atomic_commit_tail,
 268 };
 269
 270 static bool
 271 malidp_verify_afbc_framebuffer_caps(struct drm_device *dev,
 272                                     const struct drm_mode_fb_cmd2 *mode_cmd)
 273 {
 274         if (malidp_format_mod_supported(dev, mode_cmd->pixel_format,
 275                                         mode_cmd->modifier[0]) == false)
 276                 return false;
 277
 278         if (mode_cmd->offsets[0] != 0) {
 279                 DRM_DEBUG_KMS("AFBC buffers' plane offset should be 0\n");
 280                 return false;
 281         }
 282
 283         switch (mode_cmd->modifier[0] & AFBC_SIZE_MASK) {
 284         case AFBC_SIZE_16X16:
 285                 if ((mode_cmd->width % 16) || (mode_cmd->height % 16)) {
 286                         DRM_DEBUG_KMS("AFBC buffers must be aligned to 16 pixels\n");
 287                         return false;
 288                 }
 289                 break;
 290         default:
 291                 DRM_DEBUG_KMS("Unsupported AFBC block size\n");
 292                 return false;
 293         }
 294
 295         return true;
 296 }
 297
 298 static bool
 299 malidp_verify_afbc_framebuffer_size(struct drm_device *dev,
 300                                     struct drm_file *file,
 301                                     const struct drm_mode_fb_cmd2 *mode_cmd)
 302 {
 303         int n_superblocks = 0;
 304         const struct drm_format_info *info;
 305         struct drm_gem_object *objs = NULL;
 306         u32 afbc_superblock_size = 0, afbc_superblock_height = 0;
 307         u32 afbc_superblock_width = 0, afbc_size = 0;
 308         int bpp = 0;
 309
 310         switch (mode_cmd->modifier[0] & AFBC_SIZE_MASK) {
 311         case AFBC_SIZE_16X16:
 312                 afbc_superblock_height = 16;
 313                 afbc_superblock_width = 16;
 314                 break;
 315         default:
 316                 DRM_DEBUG_KMS("AFBC superblock size is not supported\n");
 317                 return false;
 318         }
 319
 320         info = drm_get_format_info(dev, mode_cmd);
 321
 322         n_superblocks = (mode_cmd->width / afbc_superblock_width) *
 323                 (mode_cmd->height / afbc_superblock_height);
 324
 325         bpp = malidp_format_get_bpp(info->format);
 326
 327         afbc_superblock_size = (bpp * afbc_superblock_width * afbc_superblock_height)
 328                                 / BITS_PER_BYTE;
 329
 330         afbc_size = ALIGN(n_superblocks * AFBC_HEADER_SIZE, AFBC_SUPERBLK_ALIGNMENT);
 331         afbc_size += n_superblocks * ALIGN(afbc_superblock_size, AFBC_SUPERBLK_ALIGNMENT);
 332
 333         if ((mode_cmd->width * bpp) != (mode_cmd->pitches[0] * BITS_PER_BYTE)) {
 334                 DRM_DEBUG_KMS("Invalid value of (pitch * BITS_PER_BYTE) (=%u) "
 335                               "should be same as width (=%u) * bpp (=%u)\n",
 336                               (mode_cmd->pitches[0] * BITS_PER_BYTE),
 337                               mode_cmd->width, bpp);
 338                 return false;
 339         }
 340
 341         objs = drm_gem_object_lookup(file, mode_cmd->handles[0]);
 342         if (!objs) {
 343                 DRM_DEBUG_KMS("Failed to lookup GEM object\n");
 344                 return false;
 345         }
 346
 347         if (objs->size < afbc_size) {
 348                 DRM_DEBUG_KMS("buffer size (%zu) too small for AFBC buffer size = %u\n",
 349                               objs->size, afbc_size);
 350                 drm_gem_object_put_unlocked(objs);
 351                 return false;
 352         }
 353
 354         drm_gem_object_put_unlocked(objs);
 355
 356         return true;
 357 }
 358
 359 static bool
 360 malidp_verify_afbc_framebuffer(struct drm_device *dev, struct drm_file *file,
 361                                const struct drm_mode_fb_cmd2 *mode_cmd)
 362 {
 363         if (malidp_verify_afbc_framebuffer_caps(dev, mode_cmd))
 364                 return malidp_verify_afbc_framebuffer_size(dev, file, mode_cmd);
 365
 366         return false;
 367 }
 368
 369 struct drm_framebuffer *
 370 malidp_fb_create(struct drm_device *dev, struct drm_file *file,
 371                  const struct drm_mode_fb_cmd2 *mode_cmd)
 372 {
 373         if (mode_cmd->modifier[0]) {
 374                 if (!malidp_verify_afbc_framebuffer(dev, file, mode_cmd))
 375                         return ERR_PTR(-EINVAL);
 376         }
 377
 378         return drm_gem_fb_create(dev, file, mode_cmd);
 379 }
 380
 381 static const struct drm_mode_config_funcs malidp_mode_config_funcs = {
 382         .fb_create = malidp_fb_create,
 383         .atomic_check = drm_atomic_helper_check,
 384         .atomic_commit = drm_atomic_helper_commit,
 385 };
 386
 387 static int malidp_init(struct drm_device *drm)
 388 {
 389         int ret;
 390         struct malidp_drm *malidp = drm->dev_private;
 391         struct malidp_hw_device *hwdev = malidp->dev;
 392
 393         drm_mode_config_init(drm);
 394
 395         drm->mode_config.min_width = hwdev->min_line_size;
 396         drm->mode_config.min_height = hwdev->min_line_size;
 397         drm->mode_config.max_width = hwdev->max_line_size;
 398         drm->mode_config.max_height = hwdev->max_line_size;
 399         drm->mode_config.funcs = &malidp_mode_config_funcs;
 400         drm->mode_config.helper_private = &malidp_mode_config_helpers;
 401         drm->mode_config.allow_fb_modifiers = true;
 402
 403         ret = malidp_crtc_init(drm);
 404         if (ret)
 405                 goto crtc_fail;
 406
 407         ret = malidp_mw_connector_init(drm);
 408         if (ret)
 409                 goto crtc_fail;
 410
 411         return 0;
 412
 413 crtc_fail:
 414         drm_mode_config_cleanup(drm);
 415         return ret;
 416 }
 417
 418 static void malidp_fini(struct drm_device *drm)
 419 {
 420         drm_mode_config_cleanup(drm);
 421 }
 422
 423 static int malidp_irq_init(struct platform_device *pdev)
 424 {
 425         int irq_de, irq_se, ret = 0;
 426         struct drm_device *drm = dev_get_drvdata(&pdev->dev);
 427         struct malidp_drm *malidp = drm->dev_private;
 428         struct malidp_hw_device *hwdev = malidp->dev;
 429
 430         /* fetch the interrupts from DT */
 431         irq_de = platform_get_irq_byname(pdev, "DE");
 432         if (irq_de < 0) {
 433                 DRM_ERROR("no 'DE' IRQ specified!\n");
 434                 return irq_de;
 435         }
 436         irq_se = platform_get_irq_byname(pdev, "SE");
 437         if (irq_se < 0) {
 438                 DRM_ERROR("no 'SE' IRQ specified!\n");
 439                 return irq_se;
 440         }
 441
 442         ret = malidp_de_irq_init(drm, irq_de);
 443         if (ret)
 444                 return ret;
 445
 446         ret = malidp_se_irq_init(drm, irq_se);
 447         if (ret) {
 448                 malidp_de_irq_fini(hwdev);
 449                 return ret;
 450         }
 451
 452         return 0;
 453 }
 454
 455 DEFINE_DRM_GEM_CMA_FOPS(fops);
 456
 457 static int malidp_dumb_create(struct drm_file *file_priv,
 458                               struct drm_device *drm,
 459                               struct drm_mode_create_dumb *args)
 460 {
 461         struct malidp_drm *malidp = drm->dev_private;
 462         /* allocate for the worst case scenario, i.e. rotated buffers */
 463         u8 alignment = malidp_hw_get_pitch_align(malidp->dev, 1);
 464
 465         args->pitch = ALIGN(DIV_ROUND_UP(args->width * args->bpp, 8), alignment);
 466
 467         return drm_gem_cma_dumb_create_internal(file_priv, drm, args);
 468 }
 469
 470 #ifdef CONFIG_DEBUG_FS
 471
 472 static void malidp_error_stats_init(struct malidp_error_stats *error_stats)
 473 {
 474         error_stats->num_errors = 0;
 475         error_stats->last_error_status = 0;
 476         error_stats->last_error_vblank = -1;
 477 }
 478
 479 void malidp_error(struct malidp_drm *malidp,
 480                   struct malidp_error_stats *error_stats, u32 status,
 481                   u64 vblank)
 482 {
 483         unsigned long irqflags;
 484
 485         spin_lock_irqsave(&malidp->errors_lock, irqflags);
 486         error_stats->last_error_status = status;
 487         error_stats->last_error_vblank = vblank;
 488         error_stats->num_errors++;
 489         spin_unlock_irqrestore(&malidp->errors_lock, irqflags);
 490 }
 491
 492 void malidp_error_stats_dump(const char *prefix,
 493                              struct malidp_error_stats error_stats,
 494                              struct seq_file *m)
 495 {
 496         seq_printf(m, "[%s] num_errors : %d\n", prefix,
 497                    error_stats.num_errors);
 498         seq_printf(m, "[%s] last_error_status  : 0x%08x\n", prefix,
 499                    error_stats.last_error_status);
 500         seq_printf(m, "[%s] last_error_vblank : %lld\n", prefix,
 501                    error_stats.last_error_vblank);
 502 }
 503
 504 static int malidp_show_stats(struct seq_file *m, void *arg)
 505 {
 506         struct drm_device *drm = m->private;
 507         struct malidp_drm *malidp = drm->dev_private;
 508         unsigned long irqflags;
 509         struct malidp_error_stats de_errors, se_errors;
 510
 511         spin_lock_irqsave(&malidp->errors_lock, irqflags);
 512         de_errors = malidp->de_errors;
 513         se_errors = malidp->se_errors;
 514         spin_unlock_irqrestore(&malidp->errors_lock, irqflags);
 515         malidp_error_stats_dump("DE", de_errors, m);
 516         malidp_error_stats_dump("SE", se_errors, m);
 517         return 0;
 518 }
 519
 520 static int malidp_debugfs_open(struct inode *inode, struct file *file)
 521 {
 522         return single_open(file, malidp_show_stats, inode->i_private);
 523 }
 524
 525 static ssize_t malidp_debugfs_write(struct file *file, const char __user *ubuf,
 526                                     size_t len, loff_t *offp)
 527 {
 528         struct seq_file *m = file->private_data;
 529         struct drm_device *drm = m->private;
 530         struct malidp_drm *malidp = drm->dev_private;
 531         unsigned long irqflags;
 532
 533         spin_lock_irqsave(&malidp->errors_lock, irqflags);
 534         malidp_error_stats_init(&malidp->de_errors);
 535         malidp_error_stats_init(&malidp->se_errors);
 536         spin_unlock_irqrestore(&malidp->errors_lock, irqflags);
 537         return len;
 538 }
 539
 540 static const struct file_operations malidp_debugfs_fops = {
 541         .owner = THIS_MODULE,
 542         .open = malidp_debugfs_open,
 543         .read = seq_read,
 544         .write = malidp_debugfs_write,
 545         .llseek = seq_lseek,
 546         .release = single_release,
 547 };
 548
 549 static int malidp_debugfs_init(struct drm_minor *minor)
 550 {
 551         struct malidp_drm *malidp = minor->dev->dev_private;
 552
 553         malidp_error_stats_init(&malidp->de_errors);
 554         malidp_error_stats_init(&malidp->se_errors);
 555         spin_lock_init(&malidp->errors_lock);
 556         debugfs_create_file("debug", S_IRUGO | S_IWUSR, minor->debugfs_root,
 557                             minor->dev, &malidp_debugfs_fops);
 558         return 0;
 559 }
 560
 561 #endif //CONFIG_DEBUG_FS
 562
 563 static struct drm_driver malidp_driver = {
 564         .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
 565         .gem_free_object_unlocked = drm_gem_cma_free_object,
 566         .gem_vm_ops = &drm_gem_cma_vm_ops,
 567         .dumb_create = malidp_dumb_create,
 568         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
 569         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
 570         .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
 571         .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
 572         .gem_prime_vmap = drm_gem_cma_prime_vmap,
 573         .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
 574         .gem_prime_mmap = drm_gem_cma_prime_mmap,
 575 #ifdef CONFIG_DEBUG_FS
 576         .debugfs_init = malidp_debugfs_init,
 577 #endif
 578         .fops = &fops,
 579         .name = "mali-dp",
 580         .desc = "ARM Mali Display Processor driver",
 581         .date = "20160106",
 582         .major = 1,
 583         .minor = 0,
 584 };
 585
 586 static const struct of_device_id  malidp_drm_of_match[] = {
 587         {
 588                 .compatible = "arm,mali-dp500",
 589                 .data = &malidp_device[MALIDP_500]
 590         },
 591         {
 592                 .compatible = "arm,mali-dp550",
 593                 .data = &malidp_device[MALIDP_550]
 594         },
 595         {
 596                 .compatible = "arm,mali-dp650",
 597                 .data = &malidp_device[MALIDP_650]
 598         },
 599         {},
 600 };
 601 MODULE_DEVICE_TABLE(of, malidp_drm_of_match);
 602
 603 static bool malidp_is_compatible_hw_id(struct malidp_hw_device *hwdev,
 604                                        const struct of_device_id *dev_id)
 605 {
 606         u32 core_id;
 607         const char *compatstr_dp500 = "arm,mali-dp500";
 608         bool is_dp500;
 609         bool dt_is_dp500;
 610
 611         /*
 612          * The DP500 CORE_ID register is in a different location, so check it
 613          * first. If the product id field matches, then this is DP500, otherwise
 614          * check the DP550/650 CORE_ID register.
 615          */
 616         core_id = malidp_hw_read(hwdev, MALIDP500_DC_BASE + MALIDP_DE_CORE_ID);
 617         /* Offset 0x18 will never read 0x500 on products other than DP500. */
 618         is_dp500 = (MALIDP_PRODUCT_ID(core_id) == 0x500);
 619         dt_is_dp500 = strnstr(dev_id->compatible, compatstr_dp500,
 620                               sizeof(dev_id->compatible)) != NULL;
 621         if (is_dp500 != dt_is_dp500) {
 622                 DRM_ERROR("Device-tree expects %s, but hardware %s DP500.\n",
 623                           dev_id->compatible, is_dp500 ? "is" : "is not");
 624                 return false;
 625         } else if (!dt_is_dp500) {
 626                 u16 product_id;
 627                 char buf[32];
 628
 629                 core_id = malidp_hw_read(hwdev,
 630                                          MALIDP550_DC_BASE + MALIDP_DE_CORE_ID);
 631                 product_id = MALIDP_PRODUCT_ID(core_id);
 632                 snprintf(buf, sizeof(buf), "arm,mali-dp%X", product_id);
 633                 if (!strnstr(dev_id->compatible, buf,
 634                              sizeof(dev_id->compatible))) {
 635                         DRM_ERROR("Device-tree expects %s, but hardware is DP%03X.\n",
 636                                   dev_id->compatible, product_id);
 637                         return false;
 638                 }
 639         }
 640         return true;
 641 }
 642
 643 static bool malidp_has_sufficient_address_space(const struct resource *res,
 644                                                 const struct of_device_id *dev_id)
 645 {
 646         resource_size_t res_size = resource_size(res);
 647         const char *compatstr_dp500 = "arm,mali-dp500";
 648
 649         if (!strnstr(dev_id->compatible, compatstr_dp500,
 650                      sizeof(dev_id->compatible)))
 651                 return res_size >= MALIDP550_ADDR_SPACE_SIZE;
 652         else if (res_size < MALIDP500_ADDR_SPACE_SIZE)
 653                 return false;
 654         return true;
 655 }
 656
 657 static ssize_t core_id_show(struct device *dev, struct device_attribute *attr,
 658                             char *buf)
 659 {
 660         struct drm_device *drm = dev_get_drvdata(dev);
 661         struct malidp_drm *malidp = drm->dev_private;
 662
 663         return snprintf(buf, PAGE_SIZE, "%08x\n", malidp->core_id);
 664 }
 665
 666 DEVICE_ATTR_RO(core_id);
 667
 668 static int malidp_init_sysfs(struct device *dev)
 669 {
 670         int ret = device_create_file(dev, &dev_attr_core_id);
 671
 672         if (ret)
 673                 DRM_ERROR("failed to create device file for core_id\n");
 674
 675         return ret;
 676 }
 677
 678 static void malidp_fini_sysfs(struct device *dev)
 679 {
 680         device_remove_file(dev, &dev_attr_core_id);
 681 }
 682
 683 #define MAX_OUTPUT_CHANNELS     3
 684
 685 static int malidp_runtime_pm_suspend(struct device *dev)
 686 {
 687         struct drm_device *drm = dev_get_drvdata(dev);
 688         struct malidp_drm *malidp = drm->dev_private;
 689         struct malidp_hw_device *hwdev = malidp->dev;
 690
 691         /* we can only suspend if the hardware is in config mode */
 692         WARN_ON(!hwdev->hw->in_config_mode(hwdev));
 693
 694         malidp_se_irq_fini(hwdev);
 695         malidp_de_irq_fini(hwdev);
 696         hwdev->pm_suspended = true;
 697         clk_disable_unprepare(hwdev->mclk);
 698         clk_disable_unprepare(hwdev->aclk);
 699         clk_disable_unprepare(hwdev->pclk);
 700
 701         return 0;
 702 }
 703
 704 static int malidp_runtime_pm_resume(struct device *dev)
 705 {
 706         struct drm_device *drm = dev_get_drvdata(dev);
 707         struct malidp_drm *malidp = drm->dev_private;
 708         struct malidp_hw_device *hwdev = malidp->dev;
 709
 710         clk_prepare_enable(hwdev->pclk);
 711         clk_prepare_enable(hwdev->aclk);
 712         clk_prepare_enable(hwdev->mclk);
 713         hwdev->pm_suspended = false;
 714         malidp_de_irq_hw_init(hwdev);
 715         malidp_se_irq_hw_init(hwdev);
 716
 717         return 0;
 718 }
 719
 720 static int malidp_bind(struct device *dev)
 721 {
 722         struct resource *res;
 723         struct drm_device *drm;
 724         struct malidp_drm *malidp;
 725         struct malidp_hw_device *hwdev;
 726         struct platform_device *pdev = to_platform_device(dev);
 727         struct of_device_id const *dev_id;
 728         struct drm_encoder *encoder;
 729         /* number of lines for the R, G and B output */
 730         u8 output_width[MAX_OUTPUT_CHANNELS];
 731         int ret = 0, i;
 732         u32 version, out_depth = 0;
 733
 734         malidp = devm_kzalloc(dev, sizeof(*malidp), GFP_KERNEL);
 735         if (!malidp)
 736                 return -ENOMEM;
 737
 738         hwdev = devm_kzalloc(dev, sizeof(*hwdev), GFP_KERNEL);
 739         if (!hwdev)
 740                 return -ENOMEM;
 741
 742         hwdev->hw = (struct malidp_hw *)of_device_get_match_data(dev);
 743         malidp->dev = hwdev;
 744
 745         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 746         hwdev->regs = devm_ioremap_resource(dev, res);
 747         if (IS_ERR(hwdev->regs))
 748                 return PTR_ERR(hwdev->regs);
 749
 750         hwdev->pclk = devm_clk_get(dev, "pclk");
 751         if (IS_ERR(hwdev->pclk))
 752                 return PTR_ERR(hwdev->pclk);
 753
 754         hwdev->aclk = devm_clk_get(dev, "aclk");
 755         if (IS_ERR(hwdev->aclk))
 756                 return PTR_ERR(hwdev->aclk);
 757
 758         hwdev->mclk = devm_clk_get(dev, "mclk");
 759         if (IS_ERR(hwdev->mclk))
 760                 return PTR_ERR(hwdev->mclk);
 761
 762         hwdev->pxlclk = devm_clk_get(dev, "pxlclk");
 763         if (IS_ERR(hwdev->pxlclk))
 764                 return PTR_ERR(hwdev->pxlclk);
 765
 766         /* Get the optional framebuffer memory resource */
 767         ret = of_reserved_mem_device_init(dev);
 768         if (ret && ret != -ENODEV)
 769                 return ret;
 770
 771         drm = drm_dev_alloc(&malidp_driver, dev);
 772         if (IS_ERR(drm)) {
 773                 ret = PTR_ERR(drm);
 774                 goto alloc_fail;
 775         }
 776
 777         drm->dev_private = malidp;
 778         dev_set_drvdata(dev, drm);
 779
 780         /* Enable power management */
 781         pm_runtime_enable(dev);
 782
 783         /* Resume device to enable the clocks */
 784         if (pm_runtime_enabled(dev))
 785                 pm_runtime_get_sync(dev);
 786         else
 787                 malidp_runtime_pm_resume(dev);
 788
 789         dev_id = of_match_device(malidp_drm_of_match, dev);
 790         if (!dev_id) {
 791                 ret = -EINVAL;
 792                 goto query_hw_fail;
 793         }
 794
 795         if (!malidp_has_sufficient_address_space(res, dev_id)) {
 796                 DRM_ERROR("Insufficient address space in device-tree.\n");
 797                 ret = -EINVAL;
 798                 goto query_hw_fail;
 799         }
 800
 801         if (!malidp_is_compatible_hw_id(hwdev, dev_id)) {
 802                 ret = -EINVAL;
 803                 goto query_hw_fail;
 804         }
 805
 806         ret = hwdev->hw->query_hw(hwdev);
 807         if (ret) {
 808                 DRM_ERROR("Invalid HW configuration\n");
 809                 goto query_hw_fail;
 810         }
 811
 812         version = malidp_hw_read(hwdev, hwdev->hw->map.dc_base + MALIDP_DE_CORE_ID);
 813         DRM_INFO("found ARM Mali-DP%3x version r%dp%d\n", version >> 16,
 814                  (version >> 12) & 0xf, (version >> 8) & 0xf);
 815
 816         malidp->core_id = version;
 817
 818         /* set the number of lines used for output of RGB data */
 819         ret = of_property_read_u8_array(dev->of_node,
 820                                         "arm,malidp-output-port-lines",
 821                                         output_width, MAX_OUTPUT_CHANNELS);
 822         if (ret)
 823                 goto query_hw_fail;
 824
 825         for (i = 0; i < MAX_OUTPUT_CHANNELS; i++)
 826                 out_depth = (out_depth << 8) | (output_width[i] & 0xf);
 827         malidp_hw_write(hwdev, out_depth, hwdev->hw->map.out_depth_base);
 828         hwdev->output_color_depth = out_depth;
 829
 830         atomic_set(&malidp->config_valid, MALIDP_CONFIG_VALID_INIT);
 831         init_waitqueue_head(&malidp->wq);
 832
 833         ret = malidp_init(drm);
 834         if (ret < 0)
 835                 goto query_hw_fail;
 836
 837         ret = malidp_init_sysfs(dev);
 838         if (ret)
 839                 goto init_fail;
 840
 841         /* Set the CRTC's port so that the encoder component can find it */
 842         malidp->crtc.port = of_graph_get_port_by_id(dev->of_node, 0);
 843
 844         ret = component_bind_all(dev, drm);
 845         if (ret) {
 846                 DRM_ERROR("Failed to bind all components\n");
 847                 goto bind_fail;
 848         }
 849
 850         /* We expect to have a maximum of two encoders one for the actual
 851          * display and a virtual one for the writeback connector
 852          */
 853         WARN_ON(drm->mode_config.num_encoder > 2);
 854         list_for_each_entry(encoder, &drm->mode_config.encoder_list, head) {
 855                 encoder->possible_clones =
 856                                 (1 << drm->mode_config.num_encoder) -  1;
 857         }
 858
 859         ret = malidp_irq_init(pdev);
 860         if (ret < 0)
 861                 goto irq_init_fail;
 862
 863         drm->irq_enabled = true;
 864
 865         ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
 866         drm_crtc_vblank_reset(&malidp->crtc);
 867         if (ret < 0) {
 868                 DRM_ERROR("failed to initialise vblank\n");
 869                 goto vblank_fail;
 870         }
 871         pm_runtime_put(dev);
 872
 873         drm_mode_config_reset(drm);
 874
 875         drm_kms_helper_poll_init(drm);
 876
 877         ret = drm_dev_register(drm, 0);
 878         if (ret)
 879                 goto register_fail;
 880
 881         drm_fbdev_generic_setup(drm, 32);
 882
 883         return 0;
 884
 885 register_fail:
 886         drm_kms_helper_poll_fini(drm);
 887         pm_runtime_get_sync(dev);
 888 vblank_fail:
 889         malidp_se_irq_fini(hwdev);
 890         malidp_de_irq_fini(hwdev);
 891         drm->irq_enabled = false;
 892 irq_init_fail:
 893         drm_atomic_helper_shutdown(drm);
 894         component_unbind_all(dev, drm);
 895 bind_fail:
 896         of_node_put(malidp->crtc.port);
 897         malidp->crtc.port = NULL;
 898 init_fail:
 899         malidp_fini_sysfs(dev);
 900         malidp_fini(drm);
 901 query_hw_fail:
 902         pm_runtime_put(dev);
 903         if (pm_runtime_enabled(dev))
 904                 pm_runtime_disable(dev);
 905         else
 906                 malidp_runtime_pm_suspend(dev);
 907         drm->dev_private = NULL;
 908         dev_set_drvdata(dev, NULL);
 909         drm_dev_put(drm);
 910 alloc_fail:
 911         of_reserved_mem_device_release(dev);
 912
 913         return ret;
 914 }
 915
 916 static void malidp_unbind(struct device *dev)
 917 {
 918         struct drm_device *drm = dev_get_drvdata(dev);
 919         struct malidp_drm *malidp = drm->dev_private;
 920         struct malidp_hw_device *hwdev = malidp->dev;
 921
 922         drm_dev_unregister(drm);
 923         drm_kms_helper_poll_fini(drm);
 924         pm_runtime_get_sync(dev);
 925         drm_crtc_vblank_off(&malidp->crtc);
 926         malidp_se_irq_fini(hwdev);
 927         malidp_de_irq_fini(hwdev);
 928         drm->irq_enabled = false;
 929         drm_atomic_helper_shutdown(drm);
 930         component_unbind_all(dev, drm);
 931         of_node_put(malidp->crtc.port);
 932         malidp->crtc.port = NULL;
 933         malidp_fini_sysfs(dev);
 934         malidp_fini(drm);
 935         pm_runtime_put(dev);
 936         if (pm_runtime_enabled(dev))
 937                 pm_runtime_disable(dev);
 938         else
 939                 malidp_runtime_pm_suspend(dev);
 940         drm->dev_private = NULL;
 941         dev_set_drvdata(dev, NULL);
 942         drm_dev_put(drm);
 943         of_reserved_mem_device_release(dev);
 944 }
 945
 946 static const struct component_master_ops malidp_master_ops = {
 947         .bind = malidp_bind,
 948         .unbind = malidp_unbind,
 949 };
 950
 951 static int malidp_compare_dev(struct device *dev, void *data)
 952 {
 953         struct device_node *np = data;
 954
 955         return dev->of_node == np;
 956 }
 957
 958 static int malidp_platform_probe(struct platform_device *pdev)
 959 {
 960         struct device_node *port;
 961         struct component_match *match = NULL;
 962
 963         if (!pdev->dev.of_node)
 964                 return -ENODEV;
 965
 966         /* there is only one output port inside each device, find it */
 967         port = of_graph_get_remote_node(pdev->dev.of_node, 0, 0);
 968         if (!port)
 969                 return -ENODEV;
 970
 971         drm_of_component_match_add(&pdev->dev, &match, malidp_compare_dev,
 972                                    port);
 973         of_node_put(port);
 974         return component_master_add_with_match(&pdev->dev, &malidp_master_ops,
 975                                                match);
 976 }
 977
 978 static int malidp_platform_remove(struct platform_device *pdev)
 979 {
 980         component_master_del(&pdev->dev, &malidp_master_ops);
 981         return 0;
 982 }
 983
 984 static int __maybe_unused malidp_pm_suspend(struct device *dev)
 985 {
 986         struct drm_device *drm = dev_get_drvdata(dev);
 987
 988         return drm_mode_config_helper_suspend(drm);
 989 }
 990
 991 static int __maybe_unused malidp_pm_resume(struct device *dev)
 992 {
 993         struct drm_device *drm = dev_get_drvdata(dev);
 994
 995         drm_mode_config_helper_resume(drm);
 996
 997         return 0;
 998 }
 999
1000 static int __maybe_unused malidp_pm_suspend_late(struct device *dev)
1001 {
1002         if (!pm_runtime_status_suspended(dev)) {
1003                 malidp_runtime_pm_suspend(dev);
1004                 pm_runtime_set_suspended(dev);
1005         }
1006         return 0;
1007 }
1008
1009 static int __maybe_unused malidp_pm_resume_early(struct device *dev)
1010 {
1011         malidp_runtime_pm_resume(dev);
1012         pm_runtime_set_active(dev);
1013         return 0;
1014 }
1015
1016 static const struct dev_pm_ops malidp_pm_ops = {
1017         SET_SYSTEM_SLEEP_PM_OPS(malidp_pm_suspend, malidp_pm_resume) \
1018         SET_LATE_SYSTEM_SLEEP_PM_OPS(malidp_pm_suspend_late, malidp_pm_resume_early) \
1019         SET_RUNTIME_PM_OPS(malidp_runtime_pm_suspend, malidp_runtime_pm_resume, NULL)
1020 };
1021
1022 static struct platform_driver malidp_platform_driver = {
1023         .probe          = malidp_platform_probe,
1024         .remove         = malidp_platform_remove,
1025         .driver = {
1026                 .name = "mali-dp",
1027                 .pm = &malidp_pm_ops,
1028                 .of_match_table = malidp_drm_of_match,
1029         },
1030 };
1031
1032 module_platform_driver(malidp_platform_driver);
1033
1034 MODULE_AUTHOR("Liviu Dudau <Liviu.Dudau@arm.com>");
1035 MODULE_DESCRIPTION("ARM Mali DP DRM driver");
1036 MODULE_LICENSE("GPL v2");