drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "smu_v13_0_1.h"
  29 #include "smu13_driver_if_yellow_carp.h"
  30 #include "yellow_carp_ppt.h"
  31 #include "smu_v13_0_1_ppsmc.h"
  32 #include "smu_v13_0_1_pmfw.h"
  33 #include "smu_cmn.h"
  34
  35 /*
  36  * DO NOT use these for err/warn/info/debug messages.
  37  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  38  * They are more MGPU friendly.
  39  */
  40 #undef pr_err
  41 #undef pr_warn
  42 #undef pr_info
  43 #undef pr_debug
  44
  45 #define FEATURE_MASK(feature) (1ULL << feature)
  46 #define SMC_DPM_FEATURE ( \
  47         FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
  48         FEATURE_MASK(FEATURE_VCN_DPM_BIT)        | \
  49         FEATURE_MASK(FEATURE_FCLK_DPM_BIT)       | \
  50         FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT)     | \
  51         FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT)     | \
  52         FEATURE_MASK(FEATURE_LCLK_DPM_BIT)       | \
  53         FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT)    | \
  54         FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \
  55         FEATURE_MASK(FEATURE_GFX_DPM_BIT))
  56
  57 static struct cmn2asic_msg_mapping yellow_carp_message_map[SMU_MSG_MAX_COUNT] = {
  58         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                  1),
  59         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,                1),
  60         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,           1),
  61         MSG_MAP(EnableGfxOff,                   PPSMC_MSG_EnableGfxOff,                 1),
  62         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,                  1),
  63         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,               1),
  64         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                 1),
  65         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                   1),
  66         MSG_MAP(SetHardMinVcn,                  PPSMC_MSG_SetHardMinVcn,                1),
  67         MSG_MAP(ActiveProcessNotify,            PPSMC_MSG_ActiveProcessNotify,          1),
  68         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,      1),
  69         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,        1),
  70         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,         1),
  71         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,        1),
  72         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,        1),
  73         MSG_MAP(GfxDeviceDriverReset,           PPSMC_MSG_GfxDeviceDriverReset,         1),
  74         MSG_MAP(GetEnabledSmuFeatures,          PPSMC_MSG_GetEnabledSmuFeatures,        1),
  75         MSG_MAP(SetHardMinSocclkByFreq,         PPSMC_MSG_SetHardMinSocclkByFreq,       1),
  76         MSG_MAP(SetSoftMinVcn,                  PPSMC_MSG_SetSoftMinVcn,                1),
  77         MSG_MAP(GetGfxclkFrequency,             PPSMC_MSG_GetGfxclkFrequency,           1),
  78         MSG_MAP(GetFclkFrequency,               PPSMC_MSG_GetFclkFrequency,             1),
  79         MSG_MAP(SetSoftMaxGfxClk,               PPSMC_MSG_SetSoftMaxGfxClk,             1),
  80         MSG_MAP(SetHardMinGfxClk,               PPSMC_MSG_SetHardMinGfxClk,             1),
  81         MSG_MAP(SetSoftMaxSocclkByFreq,         PPSMC_MSG_SetSoftMaxSocclkByFreq,       1),
  82         MSG_MAP(SetSoftMaxFclkByFreq,           PPSMC_MSG_SetSoftMaxFclkByFreq,         1),
  83         MSG_MAP(SetSoftMaxVcn,                  PPSMC_MSG_SetSoftMaxVcn,                1),
  84         MSG_MAP(SetPowerLimitPercentage,        PPSMC_MSG_SetPowerLimitPercentage,      1),
  85         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,                1),
  86         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                  1),
  87         MSG_MAP(SetHardMinFclkByFreq,           PPSMC_MSG_SetHardMinFclkByFreq,         1),
  88         MSG_MAP(SetSoftMinSocclkByFreq,         PPSMC_MSG_SetSoftMinSocclkByFreq,       1),
  89 };
  90
  91 static struct cmn2asic_mapping yellow_carp_feature_mask_map[SMU_FEATURE_COUNT] = {
  92         FEA_MAP(CCLK_DPM),
  93         FEA_MAP(FAN_CONTROLLER),
  94         FEA_MAP(PPT),
  95         FEA_MAP(TDC),
  96         FEA_MAP(THERMAL),
  97         FEA_MAP(ULV),
  98         FEA_MAP(VCN_DPM),
  99         FEA_MAP_REVERSE(FCLK),
 100         FEA_MAP_REVERSE(SOCCLK),
 101         FEA_MAP(LCLK_DPM),
 102         FEA_MAP(SHUBCLK_DPM),
 103         FEA_MAP(DCFCLK_DPM),
 104         FEA_MAP_HALF_REVERSE(GFX),
 105         FEA_MAP(DS_GFXCLK),
 106         FEA_MAP(DS_SOCCLK),
 107         FEA_MAP(DS_LCLK),
 108         FEA_MAP(DS_DCFCLK),
 109         FEA_MAP(DS_FCLK),
 110         FEA_MAP(DS_MP1CLK),
 111         FEA_MAP(DS_MP0CLK),
 112         FEA_MAP(GFX_DEM),
 113         FEA_MAP(PSI),
 114         FEA_MAP(PROCHOT),
 115         FEA_MAP(CPUOFF),
 116         FEA_MAP(STAPM),
 117         FEA_MAP(S0I3),
 118         FEA_MAP(PERF_LIMIT),
 119         FEA_MAP(CORE_DLDO),
 120         FEA_MAP(RSMU_LOW_POWER),
 121         FEA_MAP(SMN_LOW_POWER),
 122         FEA_MAP(THM_LOW_POWER),
 123         FEA_MAP(SMUIO_LOW_POWER),
 124         FEA_MAP(MP1_LOW_POWER),
 125         FEA_MAP(DS_VCN),
 126         FEA_MAP(CPPC),
 127         FEA_MAP(DF_CSTATES),
 128         FEA_MAP(MSMU_LOW_POWER),
 129         FEA_MAP(ATHUB_PG),
 130 };
 131
 132 static struct cmn2asic_mapping yellow_carp_table_map[SMU_TABLE_COUNT] = {
 133         TAB_MAP_VALID(WATERMARKS),
 134         TAB_MAP_VALID(SMU_METRICS),
 135         TAB_MAP_VALID(CUSTOM_DPM),
 136         TAB_MAP_VALID(DPMCLOCKS),
 137 };
 138
 139 static struct cmn2asic_mapping yellow_carp_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 140         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 141         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 142         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 143         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 144         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 145 };
 146
 147 static int yellow_carp_init_smc_tables(struct smu_context *smu)
 148 {
 149         struct smu_table_context *smu_table = &smu->smu_table;
 150         struct smu_table *tables = smu_table->tables;
 151
 152         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 153                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 154         SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
 155                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 156         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 157                 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 158
 159         smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
 160         if (!smu_table->clocks_table)
 161                 goto err0_out;
 162
 163         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 164         if (!smu_table->metrics_table)
 165                 goto err1_out;
 166         smu_table->metrics_time = 0;
 167
 168         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 169         if (!smu_table->watermarks_table)
 170                 goto err2_out;
 171
 172         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_1);
 173         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 174         if (!smu_table->gpu_metrics_table)
 175                 goto err3_out;
 176
 177         return 0;
 178
 179 err3_out:
 180         kfree(smu_table->watermarks_table);
 181 err2_out:
 182         kfree(smu_table->metrics_table);
 183 err1_out:
 184         kfree(smu_table->clocks_table);
 185 err0_out:
 186         return -ENOMEM;
 187 }
 188
 189 static int yellow_carp_system_features_control(struct smu_context *smu, bool en)
 190 {
 191         struct smu_feature *feature = &smu->smu_feature;
 192         struct amdgpu_device *adev = smu->adev;
 193         uint32_t feature_mask[2];
 194         int ret = 0;
 195
 196         if (!en && !adev->in_s0ix)
 197                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
 198
 199         bitmap_zero(feature->enabled, feature->feature_num);
 200         bitmap_zero(feature->supported, feature->feature_num);
 201
 202         if (!en)
 203                 return ret;
 204
 205         ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);
 206         if (ret)
 207                 return ret;
 208
 209         bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
 210                     feature->feature_num);
 211         bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
 212                     feature->feature_num);
 213
 214         return 0;
 215 }
 216
 217 static int yellow_carp_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 218 {
 219         int ret = 0;
 220
 221         /* vcn dpm on is a prerequisite for vcn power gate messages */
 222         if (enable)
 223                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
 224                                                       0, NULL);
 225         else
 226                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
 227                                                       0, NULL);
 228
 229         return ret;
 230 }
 231
 232 static int yellow_carp_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 233 {
 234         int ret = 0;
 235
 236         if (enable)
 237                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg,
 238                                                       0, NULL);
 239         else
 240                 ret = smu_cmn_send_smc_msg_with_param(smu,
 241                                                       SMU_MSG_PowerDownJpeg, 0,
 242                                                       NULL);
 243
 244         return ret;
 245 }
 246
 247
 248 static bool yellow_carp_is_dpm_running(struct smu_context *smu)
 249 {
 250         int ret = 0;
 251         uint32_t feature_mask[2];
 252         uint64_t feature_enabled;
 253
 254         ret = smu_cmn_get_enabled_32_bits_mask(smu, feature_mask, 2);
 255
 256         if (ret)
 257                 return false;
 258
 259         feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
 260
 261         return !!(feature_enabled & SMC_DPM_FEATURE);
 262 }
 263
 264 static int yellow_carp_post_smu_init(struct smu_context *smu)
 265 {
 266         struct amdgpu_device *adev = smu->adev;
 267         int ret = 0;
 268
 269         /* allow message will be sent after enable message on Yellow Carp*/
 270         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL);
 271         if (ret)
 272                 dev_err(adev->dev, "Failed to Enable GfxOff!\n");
 273         return ret;
 274 }
 275
 276 static int yellow_carp_mode_reset(struct smu_context *smu, int type)
 277 {
 278         int ret = 0, index = 0;
 279
 280         index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
 281                                 SMU_MSG_GfxDeviceDriverReset);
 282         if (index < 0)
 283                 return index == -EACCES ? 0 : index;
 284
 285         mutex_lock(&smu->message_lock);
 286
 287         ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type);
 288
 289         mutex_unlock(&smu->message_lock);
 290
 291         mdelay(10);
 292
 293         return ret;
 294 }
 295
 296 static int yellow_carp_mode2_reset(struct smu_context *smu)
 297 {
 298         return yellow_carp_mode_reset(smu, SMU_RESET_MODE_2);
 299 }
 300
 301 static int yellow_carp_get_smu_metrics_data(struct smu_context *smu,
 302                                                         MetricsMember_t member,
 303                                                         uint32_t *value)
 304 {
 305         struct smu_table_context *smu_table = &smu->smu_table;
 306
 307         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 308         int ret = 0;
 309
 310         mutex_lock(&smu->metrics_lock);
 311
 312         ret = smu_cmn_get_metrics_table_locked(smu, NULL, false);
 313         if (ret) {
 314                 mutex_unlock(&smu->metrics_lock);
 315                 return ret;
 316         }
 317
 318         switch (member) {
 319         case METRICS_AVERAGE_GFXCLK:
 320                 *value = metrics->GfxclkFrequency;
 321                 break;
 322         case METRICS_AVERAGE_SOCCLK:
 323                 *value = metrics->SocclkFrequency;
 324                 break;
 325         case METRICS_AVERAGE_VCLK:
 326                 *value = metrics->VclkFrequency;
 327                 break;
 328         case METRICS_AVERAGE_DCLK:
 329                 *value = metrics->DclkFrequency;
 330                 break;
 331         case METRICS_AVERAGE_UCLK:
 332                 *value = metrics->MemclkFrequency;
 333                 break;
 334         case METRICS_AVERAGE_GFXACTIVITY:
 335                 *value = metrics->GfxActivity / 100;
 336                 break;
 337         case METRICS_AVERAGE_VCNACTIVITY:
 338                 *value = metrics->UvdActivity;
 339                 break;
 340         case METRICS_AVERAGE_SOCKETPOWER:
 341                 *value = (metrics->CurrentSocketPower << 8) / 1000;
 342                 break;
 343         case METRICS_TEMPERATURE_EDGE:
 344                 *value = metrics->GfxTemperature / 100 *
 345                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 346                 break;
 347         case METRICS_TEMPERATURE_HOTSPOT:
 348                 *value = metrics->SocTemperature / 100 *
 349                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 350                 break;
 351         case METRICS_THROTTLER_STATUS:
 352                 *value = metrics->ThrottlerStatus;
 353                 break;
 354         case METRICS_VOLTAGE_VDDGFX:
 355                 *value = metrics->Voltage[0];
 356                 break;
 357         case METRICS_VOLTAGE_VDDSOC:
 358                 *value = metrics->Voltage[1];
 359                 break;
 360         case METRICS_SS_APU_SHARE:
 361                 /* return the percentage of APU power with respect to APU's power limit.
 362                  * percentage is reported, this isn't boost value. Smartshift power
 363                  * boost/shift is only when the percentage is more than 100.
 364                  */
 365                 if (metrics->StapmOpnLimit > 0)
 366                         *value =  (metrics->ApuPower * 100) / metrics->StapmOpnLimit;
 367                 else
 368                         *value = 0;
 369                 break;
 370         case METRICS_SS_DGPU_SHARE:
 371                 /* return the percentage of dGPU power with respect to dGPU's power limit.
 372                  * percentage is reported, this isn't boost value. Smartshift power
 373                  * boost/shift is only when the percentage is more than 100.
 374                  */
 375                 if ((metrics->dGpuPower > 0) &&
 376                     (metrics->StapmCurrentLimit > metrics->StapmOpnLimit))
 377                         *value = (metrics->dGpuPower * 100) /
 378                                   (metrics->StapmCurrentLimit - metrics->StapmOpnLimit);
 379                 else
 380                         *value = 0;
 381                 break;
 382         default:
 383                 *value = UINT_MAX;
 384                 break;
 385         }
 386
 387         mutex_unlock(&smu->metrics_lock);
 388
 389         return ret;
 390 }
 391
 392 static int yellow_carp_read_sensor(struct smu_context *smu,
 393                                         enum amd_pp_sensors sensor,
 394                                         void *data, uint32_t *size)
 395 {
 396         int ret = 0;
 397
 398         if (!data || !size)
 399                 return -EINVAL;
 400
 401         mutex_lock(&smu->sensor_lock);
 402         switch (sensor) {
 403         case AMDGPU_PP_SENSOR_GPU_LOAD:
 404                 ret = yellow_carp_get_smu_metrics_data(smu,
 405                                                                 METRICS_AVERAGE_GFXACTIVITY,
 406                                                                 (uint32_t *)data);
 407                 *size = 4;
 408                 break;
 409         case AMDGPU_PP_SENSOR_GPU_POWER:
 410                 ret = yellow_carp_get_smu_metrics_data(smu,
 411                                                                 METRICS_AVERAGE_SOCKETPOWER,
 412                                                                 (uint32_t *)data);
 413                 *size = 4;
 414                 break;
 415         case AMDGPU_PP_SENSOR_EDGE_TEMP:
 416                 ret = yellow_carp_get_smu_metrics_data(smu,
 417                                                                 METRICS_TEMPERATURE_EDGE,
 418                                                                 (uint32_t *)data);
 419                 *size = 4;
 420                 break;
 421         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
 422                 ret = yellow_carp_get_smu_metrics_data(smu,
 423                                                                 METRICS_TEMPERATURE_HOTSPOT,
 424                                                                 (uint32_t *)data);
 425                 *size = 4;
 426                 break;
 427         case AMDGPU_PP_SENSOR_GFX_MCLK:
 428                 ret = yellow_carp_get_smu_metrics_data(smu,
 429                                                                 METRICS_AVERAGE_UCLK,
 430                                                                 (uint32_t *)data);
 431                 *(uint32_t *)data *= 100;
 432                 *size = 4;
 433                 break;
 434         case AMDGPU_PP_SENSOR_GFX_SCLK:
 435                 ret = yellow_carp_get_smu_metrics_data(smu,
 436                                                                 METRICS_AVERAGE_GFXCLK,
 437                                                                 (uint32_t *)data);
 438                 *(uint32_t *)data *= 100;
 439                 *size = 4;
 440                 break;
 441         case AMDGPU_PP_SENSOR_VDDGFX:
 442                 ret = yellow_carp_get_smu_metrics_data(smu,
 443                                                                 METRICS_VOLTAGE_VDDGFX,
 444                                                                 (uint32_t *)data);
 445                 *size = 4;
 446                 break;
 447         case AMDGPU_PP_SENSOR_VDDNB:
 448                 ret = yellow_carp_get_smu_metrics_data(smu,
 449                                                                 METRICS_VOLTAGE_VDDSOC,
 450                                                                 (uint32_t *)data);
 451                 *size = 4;
 452                 break;
 453         case AMDGPU_PP_SENSOR_SS_APU_SHARE:
 454                 ret = yellow_carp_get_smu_metrics_data(smu,
 455                                                        METRICS_SS_APU_SHARE,
 456                                                        (uint32_t *)data);
 457                 *size = 4;
 458                 break;
 459         case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
 460                 ret = yellow_carp_get_smu_metrics_data(smu,
 461                                                        METRICS_SS_DGPU_SHARE,
 462                                                        (uint32_t *)data);
 463                 *size = 4;
 464                 break;
 465         default:
 466                 ret = -EOPNOTSUPP;
 467                 break;
 468         }
 469         mutex_unlock(&smu->sensor_lock);
 470
 471         return ret;
 472 }
 473
 474 static int yellow_carp_set_watermarks_table(struct smu_context *smu,
 475                                 struct pp_smu_wm_range_sets *clock_ranges)
 476 {
 477         int i;
 478         int ret = 0;
 479         Watermarks_t *table = smu->smu_table.watermarks_table;
 480
 481         if (!table || !clock_ranges)
 482                 return -EINVAL;
 483
 484         if (clock_ranges) {
 485                 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
 486                         clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
 487                         return -EINVAL;
 488
 489                 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
 490                         table->WatermarkRow[WM_DCFCLK][i].MinClock =
 491                                 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
 492                         table->WatermarkRow[WM_DCFCLK][i].MaxClock =
 493                                 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
 494                         table->WatermarkRow[WM_DCFCLK][i].MinMclk =
 495                                 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
 496                         table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
 497                                 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
 498
 499                         table->WatermarkRow[WM_DCFCLK][i].WmSetting =
 500                                 clock_ranges->reader_wm_sets[i].wm_inst;
 501                 }
 502
 503                 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
 504                         table->WatermarkRow[WM_SOCCLK][i].MinClock =
 505                                 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
 506                         table->WatermarkRow[WM_SOCCLK][i].MaxClock =
 507                                 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
 508                         table->WatermarkRow[WM_SOCCLK][i].MinMclk =
 509                                 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
 510                         table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
 511                                 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
 512
 513                         table->WatermarkRow[WM_SOCCLK][i].WmSetting =
 514                                 clock_ranges->writer_wm_sets[i].wm_inst;
 515                 }
 516
 517                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
 518         }
 519
 520         /* pass data to smu controller */
 521         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
 522              !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
 523                 ret = smu_cmn_write_watermarks_table(smu);
 524                 if (ret) {
 525                         dev_err(smu->adev->dev, "Failed to update WMTABLE!");
 526                         return ret;
 527                 }
 528                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
 529         }
 530
 531         return 0;
 532 }
 533
 534 static int yellow_carp_get_power_profile_mode(struct smu_context *smu,
 535                                                 char *buf)
 536 {
 537         static const char *profile_name[] = {
 538                                         "BOOTUP_DEFAULT",
 539                                         "3D_FULL_SCREEN",
 540                                         "POWER_SAVING",
 541                                         "VIDEO",
 542                                         "VR",
 543                                         "COMPUTE",
 544                                         "CUSTOM"};
 545         uint32_t i, size = 0;
 546         int16_t workload_type = 0;
 547
 548         if (!buf)
 549                 return -EINVAL;
 550
 551         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
 552                 /*
 553                  * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT.
 554                  * Not all profile modes are supported on yellow carp.
 555                  */
 556                 workload_type = smu_cmn_to_asic_specific_index(smu,
 557                                                                CMN2ASIC_MAPPING_WORKLOAD,
 558                                                                i);
 559
 560                 if (workload_type < 0)
 561                         continue;
 562
 563                 size += sprintf(buf + size, "%2d %14s%s\n",
 564                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
 565         }
 566
 567         return size;
 568 }
 569
 570 static int yellow_carp_set_power_profile_mode(struct smu_context *smu,
 571                                                 long *input, uint32_t size)
 572 {
 573         int workload_type, ret;
 574         uint32_t profile_mode = input[size];
 575
 576         if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
 577                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
 578                 return -EINVAL;
 579         }
 580
 581         if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT ||
 582                         profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING)
 583                 return 0;
 584
 585         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
 586         workload_type = smu_cmn_to_asic_specific_index(smu,
 587                                                        CMN2ASIC_MAPPING_WORKLOAD,
 588                                                        profile_mode);
 589         if (workload_type < 0) {
 590                 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on YELLOWCARP\n",
 591                                         profile_mode);
 592                 return -EINVAL;
 593         }
 594
 595         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
 596                                     1 << workload_type,
 597                                     NULL);
 598         if (ret) {
 599                 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n",
 600                                         workload_type);
 601                 return ret;
 602         }
 603
 604         smu->power_profile_mode = profile_mode;
 605
 606         return 0;
 607 }
 608
 609 static ssize_t yellow_carp_get_gpu_metrics(struct smu_context *smu,
 610                                                 void **table)
 611 {
 612         struct smu_table_context *smu_table = &smu->smu_table;
 613         struct gpu_metrics_v2_1 *gpu_metrics =
 614                 (struct gpu_metrics_v2_1 *)smu_table->gpu_metrics_table;
 615         SmuMetrics_t metrics;
 616         int ret = 0;
 617
 618         ret = smu_cmn_get_metrics_table(smu, &metrics, true);
 619         if (ret)
 620                 return ret;
 621
 622         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 1);
 623
 624         gpu_metrics->temperature_gfx = metrics.GfxTemperature;
 625         gpu_metrics->temperature_soc = metrics.SocTemperature;
 626         memcpy(&gpu_metrics->temperature_core[0],
 627                 &metrics.CoreTemperature[0],
 628                 sizeof(uint16_t) * 8);
 629         gpu_metrics->temperature_l3[0] = metrics.L3Temperature;
 630
 631         gpu_metrics->average_gfx_activity = metrics.GfxActivity;
 632         gpu_metrics->average_mm_activity = metrics.UvdActivity;
 633
 634         gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
 635         gpu_metrics->average_gfx_power = metrics.Power[0];
 636         gpu_metrics->average_soc_power = metrics.Power[1];
 637         memcpy(&gpu_metrics->average_core_power[0],
 638                 &metrics.CorePower[0],
 639                 sizeof(uint16_t) * 8);
 640
 641         gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
 642         gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
 643         gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
 644         gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
 645         gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
 646         gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
 647
 648         memcpy(&gpu_metrics->current_coreclk[0],
 649                 &metrics.CoreFrequency[0],
 650                 sizeof(uint16_t) * 8);
 651         gpu_metrics->current_l3clk[0] = metrics.L3Frequency;
 652
 653         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
 654
 655         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
 656
 657         *table = (void *)gpu_metrics;
 658
 659         return sizeof(struct gpu_metrics_v2_1);
 660 }
 661
 662 static int yellow_carp_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
 663                                         long input[], uint32_t size)
 664 {
 665         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
 666         int ret = 0;
 667
 668         /* Only allowed in manual mode */
 669         if (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
 670                 return -EINVAL;
 671
 672         switch (type) {
 673         case PP_OD_EDIT_SCLK_VDDC_TABLE:
 674                 if (size != 2) {
 675                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
 676                         return -EINVAL;
 677                 }
 678
 679                 if (input[0] == 0) {
 680                         if (input[1] < smu->gfx_default_hard_min_freq) {
 681                                 dev_warn(smu->adev->dev,
 682                                         "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
 683                                         input[1], smu->gfx_default_hard_min_freq);
 684                                 return -EINVAL;
 685                         }
 686                         smu->gfx_actual_hard_min_freq = input[1];
 687                 } else if (input[0] == 1) {
 688                         if (input[1] > smu->gfx_default_soft_max_freq) {
 689                                 dev_warn(smu->adev->dev,
 690                                         "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
 691                                         input[1], smu->gfx_default_soft_max_freq);
 692                                 return -EINVAL;
 693                         }
 694                         smu->gfx_actual_soft_max_freq = input[1];
 695                 } else {
 696                         return -EINVAL;
 697                 }
 698                 break;
 699         case PP_OD_RESTORE_DEFAULT_TABLE:
 700                 if (size != 0) {
 701                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
 702                         return -EINVAL;
 703                 } else {
 704                         smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
 705                         smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
 706                 }
 707                 break;
 708         case PP_OD_COMMIT_DPM_TABLE:
 709                 if (size != 0) {
 710                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
 711                         return -EINVAL;
 712                 } else {
 713                         if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
 714                                 dev_err(smu->adev->dev,
 715                                         "The setting minimun sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
 716                                         smu->gfx_actual_hard_min_freq,
 717                                         smu->gfx_actual_soft_max_freq);
 718                                 return -EINVAL;
 719                         }
 720
 721                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
 722                                                                         smu->gfx_actual_hard_min_freq, NULL);
 723                         if (ret) {
 724                                 dev_err(smu->adev->dev, "Set hard min sclk failed!");
 725                                 return ret;
 726                         }
 727
 728                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
 729                                                                         smu->gfx_actual_soft_max_freq, NULL);
 730                         if (ret) {
 731                                 dev_err(smu->adev->dev, "Set soft max sclk failed!");
 732                                 return ret;
 733                         }
 734                 }
 735                 break;
 736         default:
 737                 return -ENOSYS;
 738         }
 739
 740         return ret;
 741 }
 742
 743 static int yellow_carp_get_current_clk_freq(struct smu_context *smu,
 744                                                 enum smu_clk_type clk_type,
 745                                                 uint32_t *value)
 746 {
 747         MetricsMember_t member_type;
 748
 749         switch (clk_type) {
 750         case SMU_SOCCLK:
 751                 member_type = METRICS_AVERAGE_SOCCLK;
 752                 break;
 753         case SMU_VCLK:
 754             member_type = METRICS_AVERAGE_VCLK;
 755                 break;
 756         case SMU_DCLK:
 757                 member_type = METRICS_AVERAGE_DCLK;
 758                 break;
 759         case SMU_MCLK:
 760                 member_type = METRICS_AVERAGE_UCLK;
 761                 break;
 762         case SMU_FCLK:
 763                 return smu_cmn_send_smc_msg_with_param(smu,
 764                                 SMU_MSG_GetFclkFrequency, 0, value);
 765         default:
 766                 return -EINVAL;
 767         }
 768
 769         return yellow_carp_get_smu_metrics_data(smu, member_type, value);
 770 }
 771
 772 static int yellow_carp_get_dpm_level_count(struct smu_context *smu,
 773                                                 enum smu_clk_type clk_type,
 774                                                 uint32_t *count)
 775 {
 776         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
 777
 778         switch (clk_type) {
 779         case SMU_SOCCLK:
 780                 *count = clk_table->NumSocClkLevelsEnabled;
 781                 break;
 782         case SMU_VCLK:
 783                 *count = clk_table->VcnClkLevelsEnabled;
 784                 break;
 785         case SMU_DCLK:
 786                 *count = clk_table->VcnClkLevelsEnabled;
 787                 break;
 788         case SMU_MCLK:
 789                 *count = clk_table->NumDfPstatesEnabled;
 790                 break;
 791         case SMU_FCLK:
 792                 *count = clk_table->NumDfPstatesEnabled;
 793                 break;
 794         default:
 795                 break;
 796         }
 797
 798         return 0;
 799 }
 800
 801 static int yellow_carp_get_dpm_freq_by_index(struct smu_context *smu,
 802                                                 enum smu_clk_type clk_type,
 803                                                 uint32_t dpm_level,
 804                                                 uint32_t *freq)
 805 {
 806         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
 807
 808         if (!clk_table || clk_type >= SMU_CLK_COUNT)
 809                 return -EINVAL;
 810
 811         switch (clk_type) {
 812         case SMU_SOCCLK:
 813                 if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
 814                         return -EINVAL;
 815                 *freq = clk_table->SocClocks[dpm_level];
 816                 break;
 817         case SMU_VCLK:
 818                 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
 819                         return -EINVAL;
 820                 *freq = clk_table->VClocks[dpm_level];
 821                 break;
 822         case SMU_DCLK:
 823                 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
 824                         return -EINVAL;
 825                 *freq = clk_table->DClocks[dpm_level];
 826                 break;
 827         case SMU_UCLK:
 828         case SMU_MCLK:
 829                 if (dpm_level >= clk_table->NumDfPstatesEnabled)
 830                         return -EINVAL;
 831                 *freq = clk_table->DfPstateTable[dpm_level].MemClk;
 832                 break;
 833         case SMU_FCLK:
 834                 if (dpm_level >= clk_table->NumDfPstatesEnabled)
 835                         return -EINVAL;
 836                 *freq = clk_table->DfPstateTable[dpm_level].FClk;
 837                 break;
 838         default:
 839                 return -EINVAL;
 840         }
 841
 842         return 0;
 843 }
 844
 845 static bool yellow_carp_clk_dpm_is_enabled(struct smu_context *smu,
 846                                                 enum smu_clk_type clk_type)
 847 {
 848         enum smu_feature_mask feature_id = 0;
 849
 850         switch (clk_type) {
 851         case SMU_MCLK:
 852         case SMU_UCLK:
 853         case SMU_FCLK:
 854                 feature_id = SMU_FEATURE_DPM_FCLK_BIT;
 855                 break;
 856         case SMU_GFXCLK:
 857         case SMU_SCLK:
 858                 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
 859                 break;
 860         case SMU_SOCCLK:
 861                 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
 862                 break;
 863         case SMU_VCLK:
 864         case SMU_DCLK:
 865                 feature_id = SMU_FEATURE_VCN_DPM_BIT;
 866                 break;
 867         default:
 868                 return true;
 869         }
 870
 871         return smu_cmn_feature_is_enabled(smu, feature_id);
 872 }
 873
 874 static int yellow_carp_get_dpm_ultimate_freq(struct smu_context *smu,
 875                                                         enum smu_clk_type clk_type,
 876                                                         uint32_t *min,
 877                                                         uint32_t *max)
 878 {
 879         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
 880         uint32_t clock_limit;
 881         uint32_t max_dpm_level, min_dpm_level;
 882         int ret = 0;
 883
 884         if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type)) {
 885                 switch (clk_type) {
 886                 case SMU_MCLK:
 887                 case SMU_UCLK:
 888                         clock_limit = smu->smu_table.boot_values.uclk;
 889                         break;
 890                 case SMU_FCLK:
 891                         clock_limit = smu->smu_table.boot_values.fclk;
 892                         break;
 893                 case SMU_GFXCLK:
 894                 case SMU_SCLK:
 895                         clock_limit = smu->smu_table.boot_values.gfxclk;
 896                         break;
 897                 case SMU_SOCCLK:
 898                         clock_limit = smu->smu_table.boot_values.socclk;
 899                         break;
 900                 case SMU_VCLK:
 901                         clock_limit = smu->smu_table.boot_values.vclk;
 902                         break;
 903                 case SMU_DCLK:
 904                         clock_limit = smu->smu_table.boot_values.dclk;
 905                         break;
 906                 default:
 907                         clock_limit = 0;
 908                         break;
 909                 }
 910
 911                 /* clock in Mhz unit */
 912                 if (min)
 913                         *min = clock_limit / 100;
 914                 if (max)
 915                         *max = clock_limit / 100;
 916
 917                 return 0;
 918         }
 919
 920         if (max) {
 921                 switch (clk_type) {
 922                 case SMU_GFXCLK:
 923                 case SMU_SCLK:
 924                         *max = clk_table->MaxGfxClk;
 925                         break;
 926                 case SMU_MCLK:
 927                 case SMU_UCLK:
 928                 case SMU_FCLK:
 929                         max_dpm_level = 0;
 930                         break;
 931                 case SMU_SOCCLK:
 932                         max_dpm_level = clk_table->NumSocClkLevelsEnabled - 1;
 933                         break;
 934                 case SMU_VCLK:
 935                 case SMU_DCLK:
 936                         max_dpm_level = clk_table->VcnClkLevelsEnabled - 1;
 937                         break;
 938                 default:
 939                         ret = -EINVAL;
 940                         goto failed;
 941                 }
 942
 943                 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
 944                         ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, max_dpm_level, max);
 945                         if (ret)
 946                                 goto failed;
 947                 }
 948         }
 949
 950         if (min) {
 951                 switch (clk_type) {
 952                 case SMU_GFXCLK:
 953                 case SMU_SCLK:
 954                         *min = clk_table->MinGfxClk;
 955                         break;
 956                 case SMU_MCLK:
 957                 case SMU_UCLK:
 958                 case SMU_FCLK:
 959                         min_dpm_level = clk_table->NumDfPstatesEnabled - 1;
 960                         break;
 961                 case SMU_SOCCLK:
 962                         min_dpm_level = 0;
 963                         break;
 964                 case SMU_VCLK:
 965                 case SMU_DCLK:
 966                         min_dpm_level = 0;
 967                         break;
 968                 default:
 969                         ret = -EINVAL;
 970                         goto failed;
 971                 }
 972
 973                 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK) {
 974                         ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, min_dpm_level, min);
 975                         if (ret)
 976                                 goto failed;
 977                 }
 978         }
 979
 980 failed:
 981         return ret;
 982 }
 983
 984 static int yellow_carp_set_soft_freq_limited_range(struct smu_context *smu,
 985                                                         enum smu_clk_type clk_type,
 986                                                         uint32_t min,
 987                                                         uint32_t max)
 988 {
 989         enum smu_message_type msg_set_min, msg_set_max;
 990         int ret = 0;
 991
 992         if (!yellow_carp_clk_dpm_is_enabled(smu, clk_type))
 993                 return -EINVAL;
 994
 995         switch (clk_type) {
 996         case SMU_GFXCLK:
 997         case SMU_SCLK:
 998                 msg_set_min = SMU_MSG_SetHardMinGfxClk;
 999                 msg_set_max = SMU_MSG_SetSoftMaxGfxClk;
1000                 break;
1001         case SMU_FCLK:
1002                 msg_set_min = SMU_MSG_SetHardMinFclkByFreq;
1003                 msg_set_max = SMU_MSG_SetSoftMaxFclkByFreq;
1004                 break;
1005         case SMU_SOCCLK:
1006                 msg_set_min = SMU_MSG_SetHardMinSocclkByFreq;
1007                 msg_set_max = SMU_MSG_SetSoftMaxSocclkByFreq;
1008                 break;
1009         case SMU_VCLK:
1010         case SMU_DCLK:
1011                 msg_set_min = SMU_MSG_SetHardMinVcn;
1012                 msg_set_max = SMU_MSG_SetSoftMaxVcn;
1013                 break;
1014         default:
1015                 return -EINVAL;
1016         }
1017
1018         ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_min, min, NULL);
1019         if (ret)
1020                 goto out;
1021
1022         ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max, NULL);
1023         if (ret)
1024                 goto out;
1025
1026 out:
1027         return ret;
1028 }
1029
1030 static int yellow_carp_print_clk_levels(struct smu_context *smu,
1031                                 enum smu_clk_type clk_type, char *buf)
1032 {
1033         int i, size = 0, ret = 0;
1034         uint32_t cur_value = 0, value = 0, count = 0;
1035
1036         switch (clk_type) {
1037         case SMU_OD_SCLK:
1038                 size = sprintf(buf, "%s:\n", "OD_SCLK");
1039                 size += sprintf(buf + size, "0: %10uMhz\n",
1040                 (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
1041                 size += sprintf(buf + size, "1: %10uMhz\n",
1042                 (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
1043                 break;
1044         case SMU_OD_RANGE:
1045                 size = sprintf(buf, "%s:\n", "OD_RANGE");
1046                 size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
1047                                                 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
1048                 break;
1049         case SMU_SOCCLK:
1050         case SMU_VCLK:
1051         case SMU_DCLK:
1052         case SMU_MCLK:
1053         case SMU_FCLK:
1054                 ret = yellow_carp_get_current_clk_freq(smu, clk_type, &cur_value);
1055                 if (ret)
1056                         goto print_clk_out;
1057
1058                 ret = yellow_carp_get_dpm_level_count(smu, clk_type, &count);
1059                 if (ret)
1060                         goto print_clk_out;
1061
1062                 for (i = 0; i < count; i++) {
1063                         ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, i, &value);
1064                         if (ret)
1065                                 goto print_clk_out;
1066
1067                         size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
1068                                         cur_value == value ? "*" : "");
1069                 }
1070                 break;
1071         default:
1072                 break;
1073         }
1074
1075 print_clk_out:
1076         return size;
1077 }
1078
1079 static int yellow_carp_force_clk_levels(struct smu_context *smu,
1080                                 enum smu_clk_type clk_type, uint32_t mask)
1081 {
1082         uint32_t soft_min_level = 0, soft_max_level = 0;
1083         uint32_t min_freq = 0, max_freq = 0;
1084         int ret = 0;
1085
1086         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1087         soft_max_level = mask ? (fls(mask) - 1) : 0;
1088
1089         switch (clk_type) {
1090         case SMU_SOCCLK:
1091         case SMU_FCLK:
1092         case SMU_VCLK:
1093         case SMU_DCLK:
1094                 ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1095                 if (ret)
1096                         goto force_level_out;
1097
1098                 ret = yellow_carp_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1099                 if (ret)
1100                         goto force_level_out;
1101
1102                 ret = yellow_carp_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1103                 if (ret)
1104                         goto force_level_out;
1105                 break;
1106         default:
1107                 ret = -EINVAL;
1108                 break;
1109         }
1110
1111 force_level_out:
1112         return ret;
1113 }
1114
1115 static int yellow_carp_set_performance_level(struct smu_context *smu,
1116                                                 enum amd_dpm_forced_level level)
1117 {
1118         struct amdgpu_device *adev = smu->adev;
1119         uint32_t sclk_min = 0, sclk_max = 0;
1120         uint32_t fclk_min = 0, fclk_max = 0;
1121         uint32_t socclk_min = 0, socclk_max = 0;
1122         int ret = 0;
1123
1124         switch (level) {
1125         case AMD_DPM_FORCED_LEVEL_HIGH:
1126                 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_max);
1127                 yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_max);
1128                 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_max);
1129                 sclk_min = sclk_max;
1130                 fclk_min = fclk_max;
1131                 socclk_min = socclk_max;
1132                 break;
1133         case AMD_DPM_FORCED_LEVEL_LOW:
1134                 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, NULL);
1135                 yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, NULL);
1136                 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, NULL);
1137                 sclk_max = sclk_min;
1138                 fclk_max = fclk_min;
1139                 socclk_max = socclk_min;
1140                 break;
1141         case AMD_DPM_FORCED_LEVEL_AUTO:
1142                 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk_min, &sclk_max);
1143                 yellow_carp_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk_min, &fclk_max);
1144                 yellow_carp_get_dpm_ultimate_freq(smu, SMU_SOCCLK, &socclk_min, &socclk_max);
1145                 break;
1146         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1147         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1148         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1149         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1150                 /* Temporarily do nothing since the optimal clocks haven't been provided yet */
1151                 break;
1152         case AMD_DPM_FORCED_LEVEL_MANUAL:
1153         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1154                 return 0;
1155         default:
1156                 dev_err(adev->dev, "Invalid performance level %d\n", level);
1157                 return -EINVAL;
1158         }
1159
1160         if (sclk_min && sclk_max) {
1161                 ret = yellow_carp_set_soft_freq_limited_range(smu,
1162                                                             SMU_SCLK,
1163                                                             sclk_min,
1164                                                             sclk_max);
1165                 if (ret)
1166                         return ret;
1167
1168                 smu->gfx_actual_hard_min_freq = sclk_min;
1169                 smu->gfx_actual_soft_max_freq = sclk_max;
1170         }
1171
1172         if (fclk_min && fclk_max) {
1173                 ret = yellow_carp_set_soft_freq_limited_range(smu,
1174                                                             SMU_FCLK,
1175                                                             fclk_min,
1176                                                             fclk_max);
1177                 if (ret)
1178                         return ret;
1179         }
1180
1181         if (socclk_min && socclk_max) {
1182                 ret = yellow_carp_set_soft_freq_limited_range(smu,
1183                                                             SMU_SOCCLK,
1184                                                             socclk_min,
1185                                                             socclk_max);
1186                 if (ret)
1187                         return ret;
1188         }
1189
1190         return ret;
1191 }
1192
1193 static int yellow_carp_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
1194 {
1195         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
1196
1197         smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
1198         smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
1199         smu->gfx_actual_hard_min_freq = 0;
1200         smu->gfx_actual_soft_max_freq = 0;
1201
1202         return 0;
1203 }
1204
1205 static const struct pptable_funcs yellow_carp_ppt_funcs = {
1206         .check_fw_status = smu_v13_0_1_check_fw_status,
1207         .check_fw_version = smu_v13_0_1_check_fw_version,
1208         .init_smc_tables = yellow_carp_init_smc_tables,
1209         .fini_smc_tables = smu_v13_0_1_fini_smc_tables,
1210         .get_vbios_bootup_values = smu_v13_0_1_get_vbios_bootup_values,
1211         .system_features_control = yellow_carp_system_features_control,
1212         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1213         .send_smc_msg = smu_cmn_send_smc_msg,
1214         .dpm_set_vcn_enable = yellow_carp_dpm_set_vcn_enable,
1215         .dpm_set_jpeg_enable = yellow_carp_dpm_set_jpeg_enable,
1216         .set_default_dpm_table = smu_v13_0_1_set_default_dpm_tables,
1217         .read_sensor = yellow_carp_read_sensor,
1218         .is_dpm_running = yellow_carp_is_dpm_running,
1219         .set_watermarks_table = yellow_carp_set_watermarks_table,
1220         .get_power_profile_mode = yellow_carp_get_power_profile_mode,
1221         .set_power_profile_mode = yellow_carp_set_power_profile_mode,
1222         .get_gpu_metrics = yellow_carp_get_gpu_metrics,
1223         .get_enabled_mask = smu_cmn_get_enabled_32_bits_mask,
1224         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1225         .set_driver_table_location = smu_v13_0_1_set_driver_table_location,
1226         .gfx_off_control = smu_v13_0_1_gfx_off_control,
1227         .post_init = yellow_carp_post_smu_init,
1228         .mode2_reset = yellow_carp_mode2_reset,
1229         .get_dpm_ultimate_freq = yellow_carp_get_dpm_ultimate_freq,
1230         .od_edit_dpm_table = yellow_carp_od_edit_dpm_table,
1231         .print_clk_levels = yellow_carp_print_clk_levels,
1232         .force_clk_levels = yellow_carp_force_clk_levels,
1233         .set_performance_level = yellow_carp_set_performance_level,
1234         .set_fine_grain_gfx_freq_parameters = yellow_carp_set_fine_grain_gfx_freq_parameters,
1235 };
1236
1237 void yellow_carp_set_ppt_funcs(struct smu_context *smu)
1238 {
1239         smu->ppt_funcs = &yellow_carp_ppt_funcs;
1240         smu->message_map = yellow_carp_message_map;
1241         smu->feature_map = yellow_carp_feature_mask_map;
1242         smu->table_map = yellow_carp_table_map;
1243         smu->workload_map = yellow_carp_workload_map;
1244         smu->is_apu = true;
1245 }