drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_1.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 //#include <linux/reboot.h>
  24
  25 #define SWSMU_CODE_LAYER_L3
  26
  27 #include "amdgpu.h"
  28 #include "amdgpu_smu.h"
  29 #include "smu_v13_0_1.h"
  30 #include "soc15_common.h"
  31 #include "smu_cmn.h"
  32 #include "atomfirmware.h"
  33 #include "amdgpu_atomfirmware.h"
  34 #include "amdgpu_atombios.h"
  35 #include "atom.h"
  36
  37 #include "asic_reg/mp/mp_13_0_1_offset.h"
  38 #include "asic_reg/mp/mp_13_0_1_sh_mask.h"
  39
  40 /*
  41  * DO NOT use these for err/warn/info/debug messages.
  42  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  43  * They are more MGPU friendly.
  44  */
  45 #undef pr_err
  46 #undef pr_warn
  47 #undef pr_info
  48 #undef pr_debug
  49
  50 int smu_v13_0_1_check_fw_status(struct smu_context *smu)
  51 {
  52         struct amdgpu_device *adev = smu->adev;
  53         uint32_t mp1_fw_flags;
  54
  55         mp1_fw_flags = RREG32_PCIE(MP1_Public |
  56                                    (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
  57
  58         if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
  59             MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
  60                 return 0;
  61
  62         return -EIO;
  63 }
  64
  65 int smu_v13_0_1_check_fw_version(struct smu_context *smu)
  66 {
  67         uint32_t if_version = 0xff, smu_version = 0xff;
  68         uint16_t smu_major;
  69         uint8_t smu_minor, smu_debug;
  70         int ret = 0;
  71
  72         ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
  73         if (ret)
  74                 return ret;
  75
  76         smu_major = (smu_version >> 16) & 0xffff;
  77         smu_minor = (smu_version >> 8) & 0xff;
  78         smu_debug = (smu_version >> 0) & 0xff;
  79
  80         switch (smu->adev->asic_type) {
  81         case CHIP_YELLOW_CARP:
  82                 smu->smc_driver_if_version = SMU13_0_1_DRIVER_IF_VERSION_YELLOW_CARP;
  83                 break;
  84
  85         default:
  86                 dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
  87                 smu->smc_driver_if_version = SMU13_0_1_DRIVER_IF_VERSION_INV;
  88                 break;
  89         }
  90
  91         dev_info(smu->adev->dev, "smu fw reported version = 0x%08x (%d.%d.%d)\n",
  92                          smu_version, smu_major, smu_minor, smu_debug);
  93
  94         /*
  95          * 1. if_version mismatch is not critical as our fw is designed
  96          * to be backward compatible.
  97          * 2. New fw usually brings some optimizations. But that's visible
  98          * only on the paired driver.
  99          * Considering above, we just leave user a warning message instead
 100          * of halt driver loading.
 101          */
 102         if (if_version != smu->smc_driver_if_version) {
 103                 dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
 104                          "smu fw version = 0x%08x (%d.%d.%d)\n",
 105                          smu->smc_driver_if_version, if_version,
 106                          smu_version, smu_major, smu_minor, smu_debug);
 107                 dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
 108         }
 109
 110         return ret;
 111 }
 112
 113 int smu_v13_0_1_fini_smc_tables(struct smu_context *smu)
 114 {
 115         struct smu_table_context *smu_table = &smu->smu_table;
 116
 117         kfree(smu_table->clocks_table);
 118         smu_table->clocks_table = NULL;
 119
 120         kfree(smu_table->metrics_table);
 121         smu_table->metrics_table = NULL;
 122
 123         kfree(smu_table->watermarks_table);
 124         smu_table->watermarks_table = NULL;
 125
 126         return 0;
 127 }
 128
 129 static int smu_v13_0_1_atom_get_smu_clockinfo(struct amdgpu_device *adev,
 130                                                 uint8_t clk_id,
 131                                                 uint8_t syspll_id,
 132                                                 uint32_t *clk_freq)
 133 {
 134         struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
 135         struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
 136         int ret, index;
 137
 138         input.clk_id = clk_id;
 139         input.syspll_id = syspll_id;
 140         input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
 141         index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
 142                                             getsmuclockinfo);
 143
 144         ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
 145                                         (uint32_t *)&input);
 146         if (ret)
 147                 return -EINVAL;
 148
 149         output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
 150         *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
 151
 152         return 0;
 153 }
 154
 155 int smu_v13_0_1_get_vbios_bootup_values(struct smu_context *smu)
 156 {
 157         int ret, index;
 158         uint16_t size;
 159         uint8_t frev, crev;
 160         struct atom_common_table_header *header;
 161         struct atom_firmware_info_v3_4 *v_3_4;
 162         struct atom_firmware_info_v3_3 *v_3_3;
 163         struct atom_firmware_info_v3_1 *v_3_1;
 164
 165         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 166                                             firmwareinfo);
 167
 168         ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
 169                                              (uint8_t **)&header);
 170         if (ret)
 171                 return ret;
 172
 173         if (header->format_revision != 3) {
 174                 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu13\n");
 175                 return -EINVAL;
 176         }
 177
 178         switch (header->content_revision) {
 179         case 0:
 180         case 1:
 181         case 2:
 182                 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
 183                 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
 184                 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
 185                 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
 186                 smu->smu_table.boot_values.socclk = 0;
 187                 smu->smu_table.boot_values.dcefclk = 0;
 188                 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
 189                 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
 190                 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
 191                 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
 192                 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
 193                 break;
 194         case 3:
 195                 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
 196                 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
 197                 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
 198                 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
 199                 smu->smu_table.boot_values.socclk = 0;
 200                 smu->smu_table.boot_values.dcefclk = 0;
 201                 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
 202                 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
 203                 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
 204                 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
 205                 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
 206                 break;
 207         case 4:
 208         default:
 209                 v_3_4 = (struct atom_firmware_info_v3_4 *)header;
 210                 smu->smu_table.boot_values.revision = v_3_4->firmware_revision;
 211                 smu->smu_table.boot_values.gfxclk = v_3_4->bootup_sclk_in10khz;
 212                 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
 213                 smu->smu_table.boot_values.socclk = 0;
 214                 smu->smu_table.boot_values.dcefclk = 0;
 215                 smu->smu_table.boot_values.vddc = v_3_4->bootup_vddc_mv;
 216                 smu->smu_table.boot_values.vddci = v_3_4->bootup_vddci_mv;
 217                 smu->smu_table.boot_values.mvddc = v_3_4->bootup_mvddc_mv;
 218                 smu->smu_table.boot_values.vdd_gfx = v_3_4->bootup_vddgfx_mv;
 219                 smu->smu_table.boot_values.cooling_id = v_3_4->coolingsolution_id;
 220                 break;
 221         }
 222
 223         smu->smu_table.boot_values.format_revision = header->format_revision;
 224         smu->smu_table.boot_values.content_revision = header->content_revision;
 225
 226         smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,
 227                                         (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
 228                                         (uint8_t)0,
 229                                         &smu->smu_table.boot_values.socclk);
 230
 231         smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,
 232                                         (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
 233                                         (uint8_t)0,
 234                                         &smu->smu_table.boot_values.dcefclk);
 235
 236         smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,
 237                                         (uint8_t)SMU11_SYSPLL0_ECLK_ID,
 238                                         (uint8_t)0,
 239                                         &smu->smu_table.boot_values.eclk);
 240
 241         smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,
 242                                         (uint8_t)SMU11_SYSPLL0_VCLK_ID,
 243                                         (uint8_t)0,
 244                                         &smu->smu_table.boot_values.vclk);
 245
 246         smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,
 247                                         (uint8_t)SMU11_SYSPLL0_DCLK_ID,
 248                                         (uint8_t)0,
 249                                         &smu->smu_table.boot_values.dclk);
 250
 251         if ((smu->smu_table.boot_values.format_revision == 3) &&
 252             (smu->smu_table.boot_values.content_revision >= 2))
 253                 smu_v13_0_1_atom_get_smu_clockinfo(smu->adev,
 254                                                 (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
 255                                                 (uint8_t)SMU11_SYSPLL1_2_ID,
 256                                                 &smu->smu_table.boot_values.fclk);
 257
 258         return 0;
 259 }
 260
 261 int smu_v13_0_1_set_default_dpm_tables(struct smu_context *smu)
 262 {
 263         struct smu_table_context *smu_table = &smu->smu_table;
 264
 265         return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
 266 }
 267
 268 int smu_v13_0_1_set_driver_table_location(struct smu_context *smu)
 269 {
 270         struct smu_table *driver_table = &smu->smu_table.driver_table;
 271         int ret = 0;
 272
 273         if (!driver_table->mc_address)
 274                 return 0;
 275
 276         ret = smu_cmn_send_smc_msg_with_param(smu,
 277                         SMU_MSG_SetDriverDramAddrHigh,
 278                         upper_32_bits(driver_table->mc_address),
 279                         NULL);
 280
 281         if (ret)
 282                 return ret;
 283
 284         ret = smu_cmn_send_smc_msg_with_param(smu,
 285                         SMU_MSG_SetDriverDramAddrLow,
 286                         lower_32_bits(driver_table->mc_address),
 287                         NULL);
 288
 289         return ret;
 290 }
 291
 292 int smu_v13_0_1_gfx_off_control(struct smu_context *smu, bool enable)
 293 {
 294         int ret = 0;
 295         struct amdgpu_device *adev = smu->adev;
 296
 297         switch (adev->asic_type) {
 298         case CHIP_YELLOW_CARP:
 299                 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
 300                         return 0;
 301                 if (enable)
 302                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
 303                 else
 304                         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
 305                 break;
 306         default:
 307                 break;
 308         }
 309
 310         return ret;
 311 }