drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_smu.h"
  29 #include "atomfirmware.h"
  30 #include "amdgpu_atomfirmware.h"
  31 #include "amdgpu_atombios.h"
  32 #include "smu_v13_0.h"
  33 #include "smu13_driver_if_aldebaran.h"
  34 #include "soc15_common.h"
  35 #include "atom.h"
  36 #include "power_state.h"
  37 #include "aldebaran_ppt.h"
  38 #include "smu_v13_0_pptable.h"
  39 #include "aldebaran_ppsmc.h"
  40 #include "nbio/nbio_7_4_offset.h"
  41 #include "nbio/nbio_7_4_sh_mask.h"
  42 #include "thm/thm_11_0_2_offset.h"
  43 #include "thm/thm_11_0_2_sh_mask.h"
  44 #include "amdgpu_xgmi.h"
  45 #include <linux/pci.h>
  46 #include "amdgpu_ras.h"
  47 #include "smu_cmn.h"
  48 #include "mp/mp_13_0_2_offset.h"
  49
  50 /*
  51  * DO NOT use these for err/warn/info/debug messages.
  52  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  53  * They are more MGPU friendly.
  54  */
  55 #undef pr_err
  56 #undef pr_warn
  57 #undef pr_info
  58 #undef pr_debug
  59
  60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  61
  62 #define ALDEBARAN_FEA_MAP(smu_feature, aldebaran_feature) \
  63         [smu_feature] = {1, (aldebaran_feature)}
  64
  65 #define FEATURE_MASK(feature) (1ULL << feature)
  66 #define SMC_DPM_FEATURE ( \
  67                           FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \
  68                           FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)  | \
  69                           FEATURE_MASK(FEATURE_DPM_UCLK_BIT)    | \
  70                           FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)  | \
  71                           FEATURE_MASK(FEATURE_DPM_FCLK_BIT)    | \
  72                           FEATURE_MASK(FEATURE_DPM_LCLK_BIT)    | \
  73                           FEATURE_MASK(FEATURE_DPM_XGMI_BIT)    | \
  74                           FEATURE_MASK(FEATURE_DPM_VCN_BIT))
  75
  76 /* possible frequency drift (1Mhz) */
  77 #define EPSILON                         1
  78
  79 #define smnPCIE_ESM_CTRL                        0x111003D0
  80
  81 static const struct smu_temperature_range smu13_thermal_policy[] =
  82 {
  83         {-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
  84         { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
  85 };
  86
  87 static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = {
  88         MSG_MAP(TestMessage,                         PPSMC_MSG_TestMessage,                     0),
  89         MSG_MAP(GetSmuVersion,                       PPSMC_MSG_GetSmuVersion,                   1),
  90         MSG_MAP(GetDriverIfVersion,                  PPSMC_MSG_GetDriverIfVersion,              1),
  91         MSG_MAP(EnableAllSmuFeatures,                PPSMC_MSG_EnableAllSmuFeatures,            0),
  92         MSG_MAP(DisableAllSmuFeatures,               PPSMC_MSG_DisableAllSmuFeatures,           0),
  93         MSG_MAP(GetEnabledSmuFeaturesLow,            PPSMC_MSG_GetEnabledSmuFeaturesLow,        1),
  94         MSG_MAP(GetEnabledSmuFeaturesHigh,           PPSMC_MSG_GetEnabledSmuFeaturesHigh,       1),
  95         MSG_MAP(SetDriverDramAddrHigh,               PPSMC_MSG_SetDriverDramAddrHigh,           1),
  96         MSG_MAP(SetDriverDramAddrLow,                PPSMC_MSG_SetDriverDramAddrLow,            1),
  97         MSG_MAP(SetToolsDramAddrHigh,                PPSMC_MSG_SetToolsDramAddrHigh,            0),
  98         MSG_MAP(SetToolsDramAddrLow,                 PPSMC_MSG_SetToolsDramAddrLow,             0),
  99         MSG_MAP(TransferTableSmu2Dram,               PPSMC_MSG_TransferTableSmu2Dram,           1),
 100         MSG_MAP(TransferTableDram2Smu,               PPSMC_MSG_TransferTableDram2Smu,           0),
 101         MSG_MAP(UseDefaultPPTable,                   PPSMC_MSG_UseDefaultPPTable,               0),
 102         MSG_MAP(SetSystemVirtualDramAddrHigh,        PPSMC_MSG_SetSystemVirtualDramAddrHigh,    0),
 103         MSG_MAP(SetSystemVirtualDramAddrLow,         PPSMC_MSG_SetSystemVirtualDramAddrLow,     0),
 104         MSG_MAP(SetSoftMinByFreq,                    PPSMC_MSG_SetSoftMinByFreq,                0),
 105         MSG_MAP(SetSoftMaxByFreq,                    PPSMC_MSG_SetSoftMaxByFreq,                0),
 106         MSG_MAP(SetHardMinByFreq,                    PPSMC_MSG_SetHardMinByFreq,                0),
 107         MSG_MAP(SetHardMaxByFreq,                    PPSMC_MSG_SetHardMaxByFreq,                0),
 108         MSG_MAP(GetMinDpmFreq,                       PPSMC_MSG_GetMinDpmFreq,                   0),
 109         MSG_MAP(GetMaxDpmFreq,                       PPSMC_MSG_GetMaxDpmFreq,                   0),
 110         MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex,               1),
 111         MSG_MAP(SetWorkloadMask,                     PPSMC_MSG_SetWorkloadMask,                 1),
 112         MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm,                 0),
 113         MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive,        0),
 114         MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit,                     0),
 115         MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit,                     1),
 116         MSG_MAP(PrepareMp1ForUnload,                 PPSMC_MSG_PrepareMp1ForUnload,             0),
 117         MSG_MAP(GfxDeviceDriverReset,                PPSMC_MSG_GfxDriverReset,                  0),
 118         MSG_MAP(RunDcBtc,                            PPSMC_MSG_RunDcBtc,                        0),
 119         MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh,          0),
 120         MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow,           0),
 121         MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize,              0),
 122         MSG_MAP(GetDebugData,                        PPSMC_MSG_GetDebugData,                    0),
 123         MSG_MAP(WaflTest,                            PPSMC_MSG_WaflTest,                        0),
 124         MSG_MAP(SetMemoryChannelEnable,              PPSMC_MSG_SetMemoryChannelEnable,          0),
 125         MSG_MAP(SetNumBadHbmPagesRetired,            PPSMC_MSG_SetNumBadHbmPagesRetired,        0),
 126         MSG_MAP(DFCstateControl,                     PPSMC_MSG_DFCstateControl,                 0),
 127         MSG_MAP(GetGmiPwrDnHyst,                     PPSMC_MSG_GetGmiPwrDnHyst,                 0),
 128         MSG_MAP(SetGmiPwrDnHyst,                     PPSMC_MSG_SetGmiPwrDnHyst,                 0),
 129         MSG_MAP(GmiPwrDnControl,                     PPSMC_MSG_GmiPwrDnControl,                 0),
 130         MSG_MAP(EnterGfxoff,                         PPSMC_MSG_EnterGfxoff,                     0),
 131         MSG_MAP(ExitGfxoff,                          PPSMC_MSG_ExitGfxoff,                      0),
 132         MSG_MAP(SetExecuteDMATest,                   PPSMC_MSG_SetExecuteDMATest,               0),
 133         MSG_MAP(EnableDeterminism,                   PPSMC_MSG_EnableDeterminism,               0),
 134         MSG_MAP(DisableDeterminism,                  PPSMC_MSG_DisableDeterminism,              0),
 135         MSG_MAP(SetUclkDpmMode,                      PPSMC_MSG_SetUclkDpmMode,                  0),
 136         MSG_MAP(GfxDriverResetRecovery,              PPSMC_MSG_GfxDriverResetRecovery,          0),
 137         MSG_MAP(BoardPowerCalibration,               PPSMC_MSG_BoardPowerCalibration,           0),
 138 };
 139
 140 static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = {
 141         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 142         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 143         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 144         CLK_MAP(FCLK, PPCLK_FCLK),
 145         CLK_MAP(UCLK, PPCLK_UCLK),
 146         CLK_MAP(MCLK, PPCLK_UCLK),
 147         CLK_MAP(DCLK, PPCLK_DCLK),
 148         CLK_MAP(VCLK, PPCLK_VCLK),
 149         CLK_MAP(LCLK,   PPCLK_LCLK),
 150 };
 151
 152 static const struct cmn2asic_mapping aldebaran_feature_mask_map[SMU_FEATURE_COUNT] = {
 153         ALDEBARAN_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT,            FEATURE_DATA_CALCULATIONS),
 154         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT,                   FEATURE_DPM_GFXCLK_BIT),
 155         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT,                     FEATURE_DPM_UCLK_BIT),
 156         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT,                   FEATURE_DPM_SOCCLK_BIT),
 157         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT,                     FEATURE_DPM_FCLK_BIT),
 158         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT,                     FEATURE_DPM_LCLK_BIT),
 159         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT,                             FEATURE_DPM_XGMI_BIT),
 160         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT,                    FEATURE_DS_GFXCLK_BIT),
 161         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT,                    FEATURE_DS_SOCCLK_BIT),
 162         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT,                              FEATURE_DS_LCLK_BIT),
 163         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT,                              FEATURE_DS_FCLK_BIT),
 164         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_UCLK_BIT,                              FEATURE_DS_UCLK_BIT),
 165         ALDEBARAN_FEA_MAP(SMU_FEATURE_GFX_SS_BIT,                               FEATURE_GFX_SS_BIT),
 166         ALDEBARAN_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT,                              FEATURE_DPM_VCN_BIT),
 167         ALDEBARAN_FEA_MAP(SMU_FEATURE_RSMU_SMN_CG_BIT,                  FEATURE_RSMU_SMN_CG_BIT),
 168         ALDEBARAN_FEA_MAP(SMU_FEATURE_WAFL_CG_BIT,                              FEATURE_WAFL_CG_BIT),
 169         ALDEBARAN_FEA_MAP(SMU_FEATURE_PPT_BIT,                                  FEATURE_PPT_BIT),
 170         ALDEBARAN_FEA_MAP(SMU_FEATURE_TDC_BIT,                                  FEATURE_TDC_BIT),
 171         ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_PLUS_BIT,                    FEATURE_APCC_PLUS_BIT),
 172         ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT,                    FEATURE_APCC_DFLL_BIT),
 173         ALDEBARAN_FEA_MAP(SMU_FEATURE_FUSE_CG_BIT,                              FEATURE_FUSE_CG_BIT),
 174         ALDEBARAN_FEA_MAP(SMU_FEATURE_MP1_CG_BIT,                               FEATURE_MP1_CG_BIT),
 175         ALDEBARAN_FEA_MAP(SMU_FEATURE_SMUIO_CG_BIT,                     FEATURE_SMUIO_CG_BIT),
 176         ALDEBARAN_FEA_MAP(SMU_FEATURE_THM_CG_BIT,                               FEATURE_THM_CG_BIT),
 177         ALDEBARAN_FEA_MAP(SMU_FEATURE_CLK_CG_BIT,                               FEATURE_CLK_CG_BIT),
 178         ALDEBARAN_FEA_MAP(SMU_FEATURE_FW_CTF_BIT,                               FEATURE_FW_CTF_BIT),
 179         ALDEBARAN_FEA_MAP(SMU_FEATURE_THERMAL_BIT,                              FEATURE_THERMAL_BIT),
 180         ALDEBARAN_FEA_MAP(SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT,  FEATURE_OUT_OF_BAND_MONITOR_BIT),
 181         ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT,FEATURE_XGMI_PER_LINK_PWR_DWN),
 182         ALDEBARAN_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT,                    FEATURE_DF_CSTATE),
 183 };
 184
 185 static const struct cmn2asic_mapping aldebaran_table_map[SMU_TABLE_COUNT] = {
 186         TAB_MAP(PPTABLE),
 187         TAB_MAP(AVFS_PSM_DEBUG),
 188         TAB_MAP(AVFS_FUSE_OVERRIDE),
 189         TAB_MAP(PMSTATUSLOG),
 190         TAB_MAP(SMU_METRICS),
 191         TAB_MAP(DRIVER_SMU_CONFIG),
 192         TAB_MAP(I2C_COMMANDS),
 193 };
 194
 195 static const uint8_t aldebaran_throttler_map[] = {
 196         [THROTTLER_PPT0_BIT]            = (SMU_THROTTLER_PPT0_BIT),
 197         [THROTTLER_PPT1_BIT]            = (SMU_THROTTLER_PPT1_BIT),
 198         [THROTTLER_TDC_GFX_BIT]         = (SMU_THROTTLER_TDC_GFX_BIT),
 199         [THROTTLER_TDC_SOC_BIT]         = (SMU_THROTTLER_TDC_SOC_BIT),
 200         [THROTTLER_TDC_HBM_BIT]         = (SMU_THROTTLER_TDC_MEM_BIT),
 201         [THROTTLER_TEMP_GPU_BIT]        = (SMU_THROTTLER_TEMP_GPU_BIT),
 202         [THROTTLER_TEMP_MEM_BIT]        = (SMU_THROTTLER_TEMP_MEM_BIT),
 203         [THROTTLER_TEMP_VR_GFX_BIT]     = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
 204         [THROTTLER_TEMP_VR_SOC_BIT]     = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
 205         [THROTTLER_TEMP_VR_MEM_BIT]     = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
 206         [THROTTLER_APCC_BIT]            = (SMU_THROTTLER_APCC_BIT),
 207 };
 208
 209 static int aldebaran_tables_init(struct smu_context *smu)
 210 {
 211         struct smu_table_context *smu_table = &smu->smu_table;
 212         struct smu_table *tables = smu_table->tables;
 213
 214         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 215                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 216
 217         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
 218                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 219
 220         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 221                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 222
 223         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 224                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 225
 226         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 227         if (!smu_table->metrics_table)
 228                 return -ENOMEM;
 229         smu_table->metrics_time = 0;
 230
 231         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 232         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 233         if (!smu_table->gpu_metrics_table) {
 234                 kfree(smu_table->metrics_table);
 235                 return -ENOMEM;
 236         }
 237
 238         return 0;
 239 }
 240
 241 static int aldebaran_allocate_dpm_context(struct smu_context *smu)
 242 {
 243         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 244
 245         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
 246                                        GFP_KERNEL);
 247         if (!smu_dpm->dpm_context)
 248                 return -ENOMEM;
 249         smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
 250
 251         smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 252                                                    GFP_KERNEL);
 253         if (!smu_dpm->dpm_current_power_state)
 254                 return -ENOMEM;
 255
 256         smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 257                                                    GFP_KERNEL);
 258         if (!smu_dpm->dpm_request_power_state)
 259                 return -ENOMEM;
 260
 261         return 0;
 262 }
 263
 264 static int aldebaran_init_smc_tables(struct smu_context *smu)
 265 {
 266         int ret = 0;
 267
 268         ret = aldebaran_tables_init(smu);
 269         if (ret)
 270                 return ret;
 271
 272         ret = aldebaran_allocate_dpm_context(smu);
 273         if (ret)
 274                 return ret;
 275
 276         return smu_v13_0_init_smc_tables(smu);
 277 }
 278
 279 static int aldebaran_get_allowed_feature_mask(struct smu_context *smu,
 280                                               uint32_t *feature_mask, uint32_t num)
 281 {
 282         if (num > 2)
 283                 return -EINVAL;
 284
 285         /* pptable will handle the features to enable */
 286         memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
 287
 288         return 0;
 289 }
 290
 291 static int aldebaran_set_default_dpm_table(struct smu_context *smu)
 292 {
 293         struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 294         struct smu_13_0_dpm_table *dpm_table = NULL;
 295         PPTable_t *pptable = smu->smu_table.driver_pptable;
 296         int ret = 0;
 297
 298         /* socclk dpm table setup */
 299         dpm_table = &dpm_context->dpm_tables.soc_table;
 300         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 301                 ret = smu_v13_0_set_single_dpm_table(smu,
 302                                                      SMU_SOCCLK,
 303                                                      dpm_table);
 304                 if (ret)
 305                         return ret;
 306         } else {
 307                 dpm_table->count = 1;
 308                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 309                 dpm_table->dpm_levels[0].enabled = true;
 310                 dpm_table->min = dpm_table->dpm_levels[0].value;
 311                 dpm_table->max = dpm_table->dpm_levels[0].value;
 312         }
 313
 314         /* gfxclk dpm table setup */
 315         dpm_table = &dpm_context->dpm_tables.gfx_table;
 316         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 317                 /* in the case of gfxclk, only fine-grained dpm is honored */
 318                 dpm_table->count = 2;
 319                 dpm_table->dpm_levels[0].value = pptable->GfxclkFmin;
 320                 dpm_table->dpm_levels[0].enabled = true;
 321                 dpm_table->dpm_levels[1].value = pptable->GfxclkFmax;
 322                 dpm_table->dpm_levels[1].enabled = true;
 323                 dpm_table->min = dpm_table->dpm_levels[0].value;
 324                 dpm_table->max = dpm_table->dpm_levels[1].value;
 325         } else {
 326                 dpm_table->count = 1;
 327                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 328                 dpm_table->dpm_levels[0].enabled = true;
 329                 dpm_table->min = dpm_table->dpm_levels[0].value;
 330                 dpm_table->max = dpm_table->dpm_levels[0].value;
 331         }
 332
 333         /* memclk dpm table setup */
 334         dpm_table = &dpm_context->dpm_tables.uclk_table;
 335         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 336                 ret = smu_v13_0_set_single_dpm_table(smu,
 337                                                      SMU_UCLK,
 338                                                      dpm_table);
 339                 if (ret)
 340                         return ret;
 341         } else {
 342                 dpm_table->count = 1;
 343                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 344                 dpm_table->dpm_levels[0].enabled = true;
 345                 dpm_table->min = dpm_table->dpm_levels[0].value;
 346                 dpm_table->max = dpm_table->dpm_levels[0].value;
 347         }
 348
 349         /* fclk dpm table setup */
 350         dpm_table = &dpm_context->dpm_tables.fclk_table;
 351         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 352                 ret = smu_v13_0_set_single_dpm_table(smu,
 353                                                      SMU_FCLK,
 354                                                      dpm_table);
 355                 if (ret)
 356                         return ret;
 357         } else {
 358                 dpm_table->count = 1;
 359                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 360                 dpm_table->dpm_levels[0].enabled = true;
 361                 dpm_table->min = dpm_table->dpm_levels[0].value;
 362                 dpm_table->max = dpm_table->dpm_levels[0].value;
 363         }
 364
 365         return 0;
 366 }
 367
 368 static int aldebaran_check_powerplay_table(struct smu_context *smu)
 369 {
 370         struct smu_table_context *table_context = &smu->smu_table;
 371         struct smu_13_0_powerplay_table *powerplay_table =
 372                 table_context->power_play_table;
 373
 374         table_context->thermal_controller_type =
 375                 powerplay_table->thermal_controller_type;
 376
 377         return 0;
 378 }
 379
 380 static int aldebaran_store_powerplay_table(struct smu_context *smu)
 381 {
 382         struct smu_table_context *table_context = &smu->smu_table;
 383         struct smu_13_0_powerplay_table *powerplay_table =
 384                 table_context->power_play_table;
 385         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 386                sizeof(PPTable_t));
 387
 388         return 0;
 389 }
 390
 391 static int aldebaran_append_powerplay_table(struct smu_context *smu)
 392 {
 393         struct smu_table_context *table_context = &smu->smu_table;
 394         PPTable_t *smc_pptable = table_context->driver_pptable;
 395         struct atom_smc_dpm_info_v4_10 *smc_dpm_table;
 396         int index, ret;
 397
 398         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 399                                            smc_dpm_info);
 400
 401         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 402                                       (uint8_t **)&smc_dpm_table);
 403         if (ret)
 404                 return ret;
 405
 406         dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
 407                         smc_dpm_table->table_header.format_revision,
 408                         smc_dpm_table->table_header.content_revision);
 409
 410         if ((smc_dpm_table->table_header.format_revision == 4) &&
 411             (smc_dpm_table->table_header.content_revision == 10))
 412                 memcpy(&smc_pptable->GfxMaxCurrent,
 413                        &smc_dpm_table->GfxMaxCurrent,
 414                        sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_10, GfxMaxCurrent));
 415         return 0;
 416 }
 417
 418 static int aldebaran_setup_pptable(struct smu_context *smu)
 419 {
 420         int ret = 0;
 421
 422         /* VBIOS pptable is the first choice */
 423         smu->smu_table.boot_values.pp_table_id = 0;
 424
 425         ret = smu_v13_0_setup_pptable(smu);
 426         if (ret)
 427                 return ret;
 428
 429         ret = aldebaran_store_powerplay_table(smu);
 430         if (ret)
 431                 return ret;
 432
 433         ret = aldebaran_append_powerplay_table(smu);
 434         if (ret)
 435                 return ret;
 436
 437         ret = aldebaran_check_powerplay_table(smu);
 438         if (ret)
 439                 return ret;
 440
 441         return ret;
 442 }
 443
 444 static bool aldebaran_is_primary(struct smu_context *smu)
 445 {
 446         struct amdgpu_device *adev = smu->adev;
 447
 448         if (adev->smuio.funcs && adev->smuio.funcs->get_die_id)
 449                 return adev->smuio.funcs->get_die_id(adev) == 0;
 450
 451         return true;
 452 }
 453
 454 static int aldebaran_run_board_btc(struct smu_context *smu)
 455 {
 456         u32 smu_version;
 457         int ret;
 458
 459         if (!aldebaran_is_primary(smu))
 460                 return 0;
 461
 462         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
 463         if (ret) {
 464                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
 465                 return ret;
 466         }
 467         if (smu_version <= 0x00441d00)
 468                 return 0;
 469
 470         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BoardPowerCalibration, NULL);
 471         if (ret)
 472                 dev_err(smu->adev->dev, "Board power calibration failed!\n");
 473
 474         return ret;
 475 }
 476
 477 static int aldebaran_run_btc(struct smu_context *smu)
 478 {
 479         int ret;
 480
 481         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
 482         if (ret)
 483                 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
 484         else
 485                 ret = aldebaran_run_board_btc(smu);
 486
 487         return ret;
 488 }
 489
 490 static int aldebaran_populate_umd_state_clk(struct smu_context *smu)
 491 {
 492         struct smu_13_0_dpm_context *dpm_context =
 493                 smu->smu_dpm.dpm_context;
 494         struct smu_13_0_dpm_table *gfx_table =
 495                 &dpm_context->dpm_tables.gfx_table;
 496         struct smu_13_0_dpm_table *mem_table =
 497                 &dpm_context->dpm_tables.uclk_table;
 498         struct smu_13_0_dpm_table *soc_table =
 499                 &dpm_context->dpm_tables.soc_table;
 500         struct smu_umd_pstate_table *pstate_table =
 501                 &smu->pstate_table;
 502
 503         pstate_table->gfxclk_pstate.min = gfx_table->min;
 504         pstate_table->gfxclk_pstate.peak = gfx_table->max;
 505         pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
 506         pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
 507
 508         pstate_table->uclk_pstate.min = mem_table->min;
 509         pstate_table->uclk_pstate.peak = mem_table->max;
 510         pstate_table->uclk_pstate.curr.min = mem_table->min;
 511         pstate_table->uclk_pstate.curr.max = mem_table->max;
 512
 513         pstate_table->socclk_pstate.min = soc_table->min;
 514         pstate_table->socclk_pstate.peak = soc_table->max;
 515         pstate_table->socclk_pstate.curr.min = soc_table->min;
 516         pstate_table->socclk_pstate.curr.max = soc_table->max;
 517
 518         if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL &&
 519             mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL &&
 520             soc_table->count > ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL) {
 521                 pstate_table->gfxclk_pstate.standard =
 522                         gfx_table->dpm_levels[ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL].value;
 523                 pstate_table->uclk_pstate.standard =
 524                         mem_table->dpm_levels[ALDEBARAN_UMD_PSTATE_MCLK_LEVEL].value;
 525                 pstate_table->socclk_pstate.standard =
 526                         soc_table->dpm_levels[ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL].value;
 527         } else {
 528                 pstate_table->gfxclk_pstate.standard =
 529                         pstate_table->gfxclk_pstate.min;
 530                 pstate_table->uclk_pstate.standard =
 531                         pstate_table->uclk_pstate.min;
 532                 pstate_table->socclk_pstate.standard =
 533                         pstate_table->socclk_pstate.min;
 534         }
 535
 536         return 0;
 537 }
 538
 539 static int aldebaran_get_clk_table(struct smu_context *smu,
 540                                    struct pp_clock_levels_with_latency *clocks,
 541                                    struct smu_13_0_dpm_table *dpm_table)
 542 {
 543         int i, count;
 544
 545         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 546         clocks->num_levels = count;
 547
 548         for (i = 0; i < count; i++) {
 549                 clocks->data[i].clocks_in_khz =
 550                         dpm_table->dpm_levels[i].value * 1000;
 551                 clocks->data[i].latency_in_us = 0;
 552         }
 553
 554         return 0;
 555 }
 556
 557 static int aldebaran_freqs_in_same_level(int32_t frequency1,
 558                                          int32_t frequency2)
 559 {
 560         return (abs(frequency1 - frequency2) <= EPSILON);
 561 }
 562
 563 static int aldebaran_get_smu_metrics_data(struct smu_context *smu,
 564                                           MetricsMember_t member,
 565                                           uint32_t *value)
 566 {
 567         struct smu_table_context *smu_table= &smu->smu_table;
 568         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 569         int ret = 0;
 570
 571         mutex_lock(&smu->metrics_lock);
 572
 573         ret = smu_cmn_get_metrics_table_locked(smu,
 574                                                NULL,
 575                                                false);
 576         if (ret) {
 577                 mutex_unlock(&smu->metrics_lock);
 578                 return ret;
 579         }
 580
 581         switch (member) {
 582         case METRICS_CURR_GFXCLK:
 583                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 584                 break;
 585         case METRICS_CURR_SOCCLK:
 586                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 587                 break;
 588         case METRICS_CURR_UCLK:
 589                 *value = metrics->CurrClock[PPCLK_UCLK];
 590                 break;
 591         case METRICS_CURR_VCLK:
 592                 *value = metrics->CurrClock[PPCLK_VCLK];
 593                 break;
 594         case METRICS_CURR_DCLK:
 595                 *value = metrics->CurrClock[PPCLK_DCLK];
 596                 break;
 597         case METRICS_CURR_FCLK:
 598                 *value = metrics->CurrClock[PPCLK_FCLK];
 599                 break;
 600         case METRICS_AVERAGE_GFXCLK:
 601                 *value = metrics->AverageGfxclkFrequency;
 602                 break;
 603         case METRICS_AVERAGE_SOCCLK:
 604                 *value = metrics->AverageSocclkFrequency;
 605                 break;
 606         case METRICS_AVERAGE_UCLK:
 607                 *value = metrics->AverageUclkFrequency;
 608                 break;
 609         case METRICS_AVERAGE_GFXACTIVITY:
 610                 *value = metrics->AverageGfxActivity;
 611                 break;
 612         case METRICS_AVERAGE_MEMACTIVITY:
 613                 *value = metrics->AverageUclkActivity;
 614                 break;
 615         case METRICS_AVERAGE_SOCKETPOWER:
 616                 /* Valid power data is available only from primary die */
 617                 *value = aldebaran_is_primary(smu) ?
 618                                  metrics->AverageSocketPower << 8 :
 619                                  0;
 620                 break;
 621         case METRICS_TEMPERATURE_EDGE:
 622                 *value = metrics->TemperatureEdge *
 623                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 624                 break;
 625         case METRICS_TEMPERATURE_HOTSPOT:
 626                 *value = metrics->TemperatureHotspot *
 627                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 628                 break;
 629         case METRICS_TEMPERATURE_MEM:
 630                 *value = metrics->TemperatureHBM *
 631                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 632                 break;
 633         case METRICS_TEMPERATURE_VRGFX:
 634                 *value = metrics->TemperatureVrGfx *
 635                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 636                 break;
 637         case METRICS_TEMPERATURE_VRSOC:
 638                 *value = metrics->TemperatureVrSoc *
 639                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 640                 break;
 641         case METRICS_TEMPERATURE_VRMEM:
 642                 *value = metrics->TemperatureVrMem *
 643                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 644                 break;
 645         case METRICS_THROTTLER_STATUS:
 646                 *value = metrics->ThrottlerStatus;
 647                 break;
 648         default:
 649                 *value = UINT_MAX;
 650                 break;
 651         }
 652
 653         mutex_unlock(&smu->metrics_lock);
 654
 655         return ret;
 656 }
 657
 658 static int aldebaran_get_current_clk_freq_by_table(struct smu_context *smu,
 659                                                    enum smu_clk_type clk_type,
 660                                                    uint32_t *value)
 661 {
 662         MetricsMember_t member_type;
 663         int clk_id = 0;
 664
 665         if (!value)
 666                 return -EINVAL;
 667
 668         clk_id = smu_cmn_to_asic_specific_index(smu,
 669                                                 CMN2ASIC_MAPPING_CLK,
 670                                                 clk_type);
 671         if (clk_id < 0)
 672                 return -EINVAL;
 673
 674         switch (clk_id) {
 675         case PPCLK_GFXCLK:
 676                 /*
 677                  * CurrClock[clk_id] can provide accurate
 678                  *   output only when the dpm feature is enabled.
 679                  * We can use Average_* for dpm disabled case.
 680                  *   But this is available for gfxclk/uclk/socclk/vclk/dclk.
 681                  */
 682                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
 683                         member_type = METRICS_CURR_GFXCLK;
 684                 else
 685                         member_type = METRICS_AVERAGE_GFXCLK;
 686                 break;
 687         case PPCLK_UCLK:
 688                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
 689                         member_type = METRICS_CURR_UCLK;
 690                 else
 691                         member_type = METRICS_AVERAGE_UCLK;
 692                 break;
 693         case PPCLK_SOCCLK:
 694                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
 695                         member_type = METRICS_CURR_SOCCLK;
 696                 else
 697                         member_type = METRICS_AVERAGE_SOCCLK;
 698                 break;
 699         case PPCLK_VCLK:
 700                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
 701                         member_type = METRICS_CURR_VCLK;
 702                 else
 703                         member_type = METRICS_AVERAGE_VCLK;
 704                 break;
 705         case PPCLK_DCLK:
 706                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
 707                         member_type = METRICS_CURR_DCLK;
 708                 else
 709                         member_type = METRICS_AVERAGE_DCLK;
 710                 break;
 711         case PPCLK_FCLK:
 712                 member_type = METRICS_CURR_FCLK;
 713                 break;
 714         default:
 715                 return -EINVAL;
 716         }
 717
 718         return aldebaran_get_smu_metrics_data(smu,
 719                                               member_type,
 720                                               value);
 721 }
 722
 723 static int aldebaran_print_clk_levels(struct smu_context *smu,
 724                                       enum smu_clk_type type, char *buf)
 725 {
 726         int i, now, size = 0;
 727         int ret = 0;
 728         struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
 729         struct pp_clock_levels_with_latency clocks;
 730         struct smu_13_0_dpm_table *single_dpm_table;
 731         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 732         struct smu_13_0_dpm_context *dpm_context = NULL;
 733         uint32_t display_levels;
 734         uint32_t freq_values[3] = {0};
 735         uint32_t min_clk, max_clk;
 736
 737         if (amdgpu_ras_intr_triggered())
 738                 return sysfs_emit(buf, "unavailable\n");
 739
 740         dpm_context = smu_dpm->dpm_context;
 741
 742         switch (type) {
 743
 744         case SMU_OD_SCLK:
 745                 size = sysfs_emit(buf, "%s:\n", "GFXCLK");
 746                 fallthrough;
 747         case SMU_SCLK:
 748                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now);
 749                 if (ret) {
 750                         dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!");
 751                         return ret;
 752                 }
 753
 754                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 755                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 756                 if (ret) {
 757                         dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
 758                         return ret;
 759                 }
 760
 761                 display_levels = clocks.num_levels;
 762
 763                 min_clk = pstate_table->gfxclk_pstate.curr.min;
 764                 max_clk = pstate_table->gfxclk_pstate.curr.max;
 765
 766                 freq_values[0] = min_clk;
 767                 freq_values[1] = max_clk;
 768
 769                 /* fine-grained dpm has only 2 levels */
 770                 if (now > min_clk && now < max_clk) {
 771                         display_levels = clocks.num_levels + 1;
 772                         freq_values[2] = max_clk;
 773                         freq_values[1] = now;
 774                 }
 775
 776                 /*
 777                  * For DPM disabled case, there will be only one clock level.
 778                  * And it's safe to assume that is always the current clock.
 779                  */
 780                 if (display_levels == clocks.num_levels) {
 781                         for (i = 0; i < clocks.num_levels; i++)
 782                                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
 783                                         freq_values[i],
 784                                         (clocks.num_levels == 1) ?
 785                                                 "*" :
 786                                                 (aldebaran_freqs_in_same_level(
 787                                                          freq_values[i], now) ?
 788                                                          "*" :
 789                                                          ""));
 790                 } else {
 791                         for (i = 0; i < display_levels; i++)
 792                                 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
 793                                                 freq_values[i], i == 1 ? "*" : "");
 794                 }
 795
 796                 break;
 797
 798         case SMU_OD_MCLK:
 799                 size = sysfs_emit(buf, "%s:\n", "MCLK");
 800                 fallthrough;
 801         case SMU_MCLK:
 802                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, &now);
 803                 if (ret) {
 804                         dev_err(smu->adev->dev, "Attempt to get current mclk Failed!");
 805                         return ret;
 806                 }
 807
 808                 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
 809                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 810                 if (ret) {
 811                         dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
 812                         return ret;
 813                 }
 814
 815                 for (i = 0; i < clocks.num_levels; i++)
 816                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 817                                         i, clocks.data[i].clocks_in_khz / 1000,
 818                                         (clocks.num_levels == 1) ? "*" :
 819                                         (aldebaran_freqs_in_same_level(
 820                                                                        clocks.data[i].clocks_in_khz / 1000,
 821                                                                        now) ? "*" : ""));
 822                 break;
 823
 824         case SMU_SOCCLK:
 825                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now);
 826                 if (ret) {
 827                         dev_err(smu->adev->dev, "Attempt to get current socclk Failed!");
 828                         return ret;
 829                 }
 830
 831                 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
 832                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 833                 if (ret) {
 834                         dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
 835                         return ret;
 836                 }
 837
 838                 for (i = 0; i < clocks.num_levels; i++)
 839                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 840                                         i, clocks.data[i].clocks_in_khz / 1000,
 841                                         (clocks.num_levels == 1) ? "*" :
 842                                         (aldebaran_freqs_in_same_level(
 843                                                                        clocks.data[i].clocks_in_khz / 1000,
 844                                                                        now) ? "*" : ""));
 845                 break;
 846
 847         case SMU_FCLK:
 848                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_FCLK, &now);
 849                 if (ret) {
 850                         dev_err(smu->adev->dev, "Attempt to get current fclk Failed!");
 851                         return ret;
 852                 }
 853
 854                 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
 855                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 856                 if (ret) {
 857                         dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
 858                         return ret;
 859                 }
 860
 861                 for (i = 0; i < single_dpm_table->count; i++)
 862                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 863                                         i, single_dpm_table->dpm_levels[i].value,
 864                                         (clocks.num_levels == 1) ? "*" :
 865                                         (aldebaran_freqs_in_same_level(
 866                                                                        clocks.data[i].clocks_in_khz / 1000,
 867                                                                        now) ? "*" : ""));
 868                 break;
 869
 870         case SMU_VCLK:
 871                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_VCLK, &now);
 872                 if (ret) {
 873                         dev_err(smu->adev->dev, "Attempt to get current vclk Failed!");
 874                         return ret;
 875                 }
 876
 877                 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
 878                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 879                 if (ret) {
 880                         dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!");
 881                         return ret;
 882                 }
 883
 884                 for (i = 0; i < single_dpm_table->count; i++)
 885                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 886                                         i, single_dpm_table->dpm_levels[i].value,
 887                                         (clocks.num_levels == 1) ? "*" :
 888                                         (aldebaran_freqs_in_same_level(
 889                                                                        clocks.data[i].clocks_in_khz / 1000,
 890                                                                        now) ? "*" : ""));
 891                 break;
 892
 893         case SMU_DCLK:
 894                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_DCLK, &now);
 895                 if (ret) {
 896                         dev_err(smu->adev->dev, "Attempt to get current dclk Failed!");
 897                         return ret;
 898                 }
 899
 900                 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
 901                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 902                 if (ret) {
 903                         dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!");
 904                         return ret;
 905                 }
 906
 907                 for (i = 0; i < single_dpm_table->count; i++)
 908                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 909                                         i, single_dpm_table->dpm_levels[i].value,
 910                                         (clocks.num_levels == 1) ? "*" :
 911                                         (aldebaran_freqs_in_same_level(
 912                                                                        clocks.data[i].clocks_in_khz / 1000,
 913                                                                        now) ? "*" : ""));
 914                 break;
 915
 916         default:
 917                 break;
 918         }
 919
 920         return size;
 921 }
 922
 923 static int aldebaran_upload_dpm_level(struct smu_context *smu,
 924                                       bool max,
 925                                       uint32_t feature_mask,
 926                                       uint32_t level)
 927 {
 928         struct smu_13_0_dpm_context *dpm_context =
 929                 smu->smu_dpm.dpm_context;
 930         uint32_t freq;
 931         int ret = 0;
 932
 933         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
 934             (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) {
 935                 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
 936                 ret = smu_cmn_send_smc_msg_with_param(smu,
 937                                                       (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 938                                                       (PPCLK_GFXCLK << 16) | (freq & 0xffff),
 939                                                       NULL);
 940                 if (ret) {
 941                         dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
 942                                 max ? "max" : "min");
 943                         return ret;
 944                 }
 945         }
 946
 947         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 948             (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) {
 949                 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
 950                 ret = smu_cmn_send_smc_msg_with_param(smu,
 951                                                       (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 952                                                       (PPCLK_UCLK << 16) | (freq & 0xffff),
 953                                                       NULL);
 954                 if (ret) {
 955                         dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
 956                                 max ? "max" : "min");
 957                         return ret;
 958                 }
 959         }
 960
 961         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
 962             (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) {
 963                 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
 964                 ret = smu_cmn_send_smc_msg_with_param(smu,
 965                                                       (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 966                                                       (PPCLK_SOCCLK << 16) | (freq & 0xffff),
 967                                                       NULL);
 968                 if (ret) {
 969                         dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
 970                                 max ? "max" : "min");
 971                         return ret;
 972                 }
 973         }
 974
 975         return ret;
 976 }
 977
 978 static int aldebaran_force_clk_levels(struct smu_context *smu,
 979                                       enum smu_clk_type type, uint32_t mask)
 980 {
 981         struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 982         struct smu_13_0_dpm_table *single_dpm_table = NULL;
 983         uint32_t soft_min_level, soft_max_level;
 984         int ret = 0;
 985
 986         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 987         soft_max_level = mask ? (fls(mask) - 1) : 0;
 988
 989         switch (type) {
 990         case SMU_SCLK:
 991                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 992                 if (soft_max_level >= single_dpm_table->count) {
 993                         dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
 994                                 soft_max_level, single_dpm_table->count - 1);
 995                         ret = -EINVAL;
 996                         break;
 997                 }
 998
 999                 ret = aldebaran_upload_dpm_level(smu,
1000                                                  false,
1001                                                  FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT),
1002                                                  soft_min_level);
1003                 if (ret) {
1004                         dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
1005                         break;
1006                 }
1007
1008                 ret = aldebaran_upload_dpm_level(smu,
1009                                                  true,
1010                                                  FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT),
1011                                                  soft_max_level);
1012                 if (ret)
1013                         dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
1014
1015                 break;
1016
1017         case SMU_MCLK:
1018         case SMU_SOCCLK:
1019         case SMU_FCLK:
1020                 /*
1021                  * Should not arrive here since aldebaran does not
1022                  * support mclk/socclk/fclk softmin/softmax settings
1023                  */
1024                 ret = -EINVAL;
1025                 break;
1026
1027         default:
1028                 break;
1029         }
1030
1031         return ret;
1032 }
1033
1034 static int aldebaran_get_thermal_temperature_range(struct smu_context *smu,
1035                                                    struct smu_temperature_range *range)
1036 {
1037         struct smu_table_context *table_context = &smu->smu_table;
1038         struct smu_13_0_powerplay_table *powerplay_table =
1039                 table_context->power_play_table;
1040         PPTable_t *pptable = smu->smu_table.driver_pptable;
1041
1042         if (!range)
1043                 return -EINVAL;
1044
1045         memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
1046
1047         range->hotspot_crit_max = pptable->ThotspotLimit *
1048                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1049         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1050                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1051         range->mem_crit_max = pptable->TmemLimit *
1052                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1053         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
1054                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1055         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1056
1057         return 0;
1058 }
1059
1060 static int aldebaran_get_current_activity_percent(struct smu_context *smu,
1061                                                   enum amd_pp_sensors sensor,
1062                                                   uint32_t *value)
1063 {
1064         int ret = 0;
1065
1066         if (!value)
1067                 return -EINVAL;
1068
1069         switch (sensor) {
1070         case AMDGPU_PP_SENSOR_GPU_LOAD:
1071                 ret = aldebaran_get_smu_metrics_data(smu,
1072                                                      METRICS_AVERAGE_GFXACTIVITY,
1073                                                      value);
1074                 break;
1075         case AMDGPU_PP_SENSOR_MEM_LOAD:
1076                 ret = aldebaran_get_smu_metrics_data(smu,
1077                                                      METRICS_AVERAGE_MEMACTIVITY,
1078                                                      value);
1079                 break;
1080         default:
1081                 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
1082                 return -EINVAL;
1083         }
1084
1085         return ret;
1086 }
1087
1088 static int aldebaran_get_gpu_power(struct smu_context *smu, uint32_t *value)
1089 {
1090         if (!value)
1091                 return -EINVAL;
1092
1093         return aldebaran_get_smu_metrics_data(smu,
1094                                               METRICS_AVERAGE_SOCKETPOWER,
1095                                               value);
1096 }
1097
1098 static int aldebaran_thermal_get_temperature(struct smu_context *smu,
1099                                              enum amd_pp_sensors sensor,
1100                                              uint32_t *value)
1101 {
1102         int ret = 0;
1103
1104         if (!value)
1105                 return -EINVAL;
1106
1107         switch (sensor) {
1108         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1109                 ret = aldebaran_get_smu_metrics_data(smu,
1110                                                      METRICS_TEMPERATURE_HOTSPOT,
1111                                                      value);
1112                 break;
1113         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1114                 ret = aldebaran_get_smu_metrics_data(smu,
1115                                                      METRICS_TEMPERATURE_EDGE,
1116                                                      value);
1117                 break;
1118         case AMDGPU_PP_SENSOR_MEM_TEMP:
1119                 ret = aldebaran_get_smu_metrics_data(smu,
1120                                                      METRICS_TEMPERATURE_MEM,
1121                                                      value);
1122                 break;
1123         default:
1124                 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1125                 return -EINVAL;
1126         }
1127
1128         return ret;
1129 }
1130
1131 static int aldebaran_read_sensor(struct smu_context *smu,
1132                                  enum amd_pp_sensors sensor,
1133                                  void *data, uint32_t *size)
1134 {
1135         int ret = 0;
1136
1137         if (amdgpu_ras_intr_triggered())
1138                 return 0;
1139
1140         if (!data || !size)
1141                 return -EINVAL;
1142
1143         mutex_lock(&smu->sensor_lock);
1144         switch (sensor) {
1145         case AMDGPU_PP_SENSOR_MEM_LOAD:
1146         case AMDGPU_PP_SENSOR_GPU_LOAD:
1147                 ret = aldebaran_get_current_activity_percent(smu,
1148                                                              sensor,
1149                                                              (uint32_t *)data);
1150                 *size = 4;
1151                 break;
1152         case AMDGPU_PP_SENSOR_GPU_POWER:
1153                 ret = aldebaran_get_gpu_power(smu, (uint32_t *)data);
1154                 *size = 4;
1155                 break;
1156         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1157         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1158         case AMDGPU_PP_SENSOR_MEM_TEMP:
1159                 ret = aldebaran_thermal_get_temperature(smu, sensor,
1160                                                         (uint32_t *)data);
1161                 *size = 4;
1162                 break;
1163         case AMDGPU_PP_SENSOR_GFX_MCLK:
1164                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1165                 /* the output clock frequency in 10K unit */
1166                 *(uint32_t *)data *= 100;
1167                 *size = 4;
1168                 break;
1169         case AMDGPU_PP_SENSOR_GFX_SCLK:
1170                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1171                 *(uint32_t *)data *= 100;
1172                 *size = 4;
1173                 break;
1174         case AMDGPU_PP_SENSOR_VDDGFX:
1175                 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data);
1176                 *size = 4;
1177                 break;
1178         default:
1179                 ret = -EOPNOTSUPP;
1180                 break;
1181         }
1182         mutex_unlock(&smu->sensor_lock);
1183
1184         return ret;
1185 }
1186
1187 static int aldebaran_get_power_limit(struct smu_context *smu,
1188                                      uint32_t *current_power_limit,
1189                                      uint32_t *default_power_limit,
1190                                      uint32_t *max_power_limit)
1191 {
1192         PPTable_t *pptable = smu->smu_table.driver_pptable;
1193         uint32_t power_limit = 0;
1194         int ret;
1195
1196         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
1197                 if (current_power_limit)
1198                         *current_power_limit = 0;
1199                 if (default_power_limit)
1200                         *default_power_limit = 0;
1201                 if (max_power_limit)
1202                         *max_power_limit = 0;
1203
1204                 dev_warn(smu->adev->dev,
1205                         "PPT feature is not enabled, power values can't be fetched.");
1206
1207                 return 0;
1208         }
1209
1210         /* Valid power data is available only from primary die.
1211          * For secondary die show the value as 0.
1212          */
1213         if (aldebaran_is_primary(smu)) {
1214                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit,
1215                                            &power_limit);
1216
1217                 if (ret) {
1218                         /* the last hope to figure out the ppt limit */
1219                         if (!pptable) {
1220                                 dev_err(smu->adev->dev,
1221                                         "Cannot get PPT limit due to pptable missing!");
1222                                 return -EINVAL;
1223                         }
1224                         power_limit = pptable->PptLimit;
1225                 }
1226         }
1227
1228         if (current_power_limit)
1229                 *current_power_limit = power_limit;
1230         if (default_power_limit)
1231                 *default_power_limit = power_limit;
1232
1233         if (max_power_limit) {
1234                 if (pptable)
1235                         *max_power_limit = pptable->PptLimit;
1236         }
1237
1238         return 0;
1239 }
1240
1241 static int aldebaran_set_power_limit(struct smu_context *smu, uint32_t n)
1242 {
1243         /* Power limit can be set only through primary die */
1244         if (aldebaran_is_primary(smu))
1245                 return smu_v13_0_set_power_limit(smu, n);
1246
1247         return -EINVAL;
1248 }
1249
1250 static int aldebaran_system_features_control(struct  smu_context *smu, bool enable)
1251 {
1252         int ret;
1253
1254         ret = smu_v13_0_system_features_control(smu, enable);
1255         if (!ret && enable)
1256                 ret = aldebaran_run_btc(smu);
1257
1258         return ret;
1259 }
1260
1261 static int aldebaran_set_performance_level(struct smu_context *smu,
1262                                            enum amd_dpm_forced_level level)
1263 {
1264         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1265         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1266         struct smu_13_0_dpm_table *gfx_table =
1267                 &dpm_context->dpm_tables.gfx_table;
1268         struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1269
1270         /* Disable determinism if switching to another mode */
1271         if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) &&
1272             (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) {
1273                 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL);
1274                 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1275         }
1276
1277         switch (level) {
1278
1279         case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM:
1280                 return 0;
1281
1282         case AMD_DPM_FORCED_LEVEL_HIGH:
1283         case AMD_DPM_FORCED_LEVEL_LOW:
1284         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1285         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1286         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1287         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1288         default:
1289                 break;
1290         }
1291
1292         return smu_v13_0_set_performance_level(smu, level);
1293 }
1294
1295 static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu,
1296                                           enum smu_clk_type clk_type,
1297                                           uint32_t min,
1298                                           uint32_t max)
1299 {
1300         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1301         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1302         struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1303         struct amdgpu_device *adev = smu->adev;
1304         uint32_t min_clk;
1305         uint32_t max_clk;
1306         int ret = 0;
1307
1308         if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK)
1309                 return -EINVAL;
1310
1311         if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1312                         && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1313                 return -EINVAL;
1314
1315         if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
1316                 if (min >= max) {
1317                         dev_err(smu->adev->dev,
1318                                 "Minimum GFX clk should be less than the maximum allowed clock\n");
1319                         return -EINVAL;
1320                 }
1321
1322                 if ((min == pstate_table->gfxclk_pstate.curr.min) &&
1323                     (max == pstate_table->gfxclk_pstate.curr.max))
1324                         return 0;
1325
1326                 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK,
1327                                                             min, max);
1328                 if (!ret) {
1329                         pstate_table->gfxclk_pstate.curr.min = min;
1330                         pstate_table->gfxclk_pstate.curr.max = max;
1331                 }
1332
1333                 return ret;
1334         }
1335
1336         if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1337                 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) ||
1338                         (max > dpm_context->dpm_tables.gfx_table.max)) {
1339                         dev_warn(adev->dev,
1340                                         "Invalid max frequency %d MHz specified for determinism\n", max);
1341                         return -EINVAL;
1342                 }
1343
1344                 /* Restore default min/max clocks and enable determinism */
1345                 min_clk = dpm_context->dpm_tables.gfx_table.min;
1346                 max_clk = dpm_context->dpm_tables.gfx_table.max;
1347                 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1348                 if (!ret) {
1349                         usleep_range(500, 1000);
1350                         ret = smu_cmn_send_smc_msg_with_param(smu,
1351                                         SMU_MSG_EnableDeterminism,
1352                                         max, NULL);
1353                         if (ret) {
1354                                 dev_err(adev->dev,
1355                                                 "Failed to enable determinism at GFX clock %d MHz\n", max);
1356                         } else {
1357                                 pstate_table->gfxclk_pstate.curr.min = min_clk;
1358                                 pstate_table->gfxclk_pstate.curr.max = max;
1359                         }
1360                 }
1361         }
1362
1363         return ret;
1364 }
1365
1366 static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
1367                                                         long input[], uint32_t size)
1368 {
1369         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1370         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1371         struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1372         uint32_t min_clk;
1373         uint32_t max_clk;
1374         int ret = 0;
1375
1376         /* Only allowed in manual or determinism mode */
1377         if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1378                         && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1379                 return -EINVAL;
1380
1381         switch (type) {
1382         case PP_OD_EDIT_SCLK_VDDC_TABLE:
1383                 if (size != 2) {
1384                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1385                         return -EINVAL;
1386                 }
1387
1388                 if (input[0] == 0) {
1389                         if (input[1] < dpm_context->dpm_tables.gfx_table.min) {
1390                                 dev_warn(smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n",
1391                                         input[1], dpm_context->dpm_tables.gfx_table.min);
1392                                 pstate_table->gfxclk_pstate.custom.min =
1393                                         pstate_table->gfxclk_pstate.curr.min;
1394                                 return -EINVAL;
1395                         }
1396
1397                         pstate_table->gfxclk_pstate.custom.min = input[1];
1398                 } else if (input[0] == 1) {
1399                         if (input[1] > dpm_context->dpm_tables.gfx_table.max) {
1400                                 dev_warn(smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
1401                                         input[1], dpm_context->dpm_tables.gfx_table.max);
1402                                 pstate_table->gfxclk_pstate.custom.max =
1403                                         pstate_table->gfxclk_pstate.curr.max;
1404                                 return -EINVAL;
1405                         }
1406
1407                         pstate_table->gfxclk_pstate.custom.max = input[1];
1408                 } else {
1409                         return -EINVAL;
1410                 }
1411                 break;
1412         case PP_OD_RESTORE_DEFAULT_TABLE:
1413                 if (size != 0) {
1414                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1415                         return -EINVAL;
1416                 } else {
1417                         /* Use the default frequencies for manual and determinism mode */
1418                         min_clk = dpm_context->dpm_tables.gfx_table.min;
1419                         max_clk = dpm_context->dpm_tables.gfx_table.max;
1420
1421                         return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1422                 }
1423                 break;
1424         case PP_OD_COMMIT_DPM_TABLE:
1425                 if (size != 0) {
1426                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1427                         return -EINVAL;
1428                 } else {
1429                         if (!pstate_table->gfxclk_pstate.custom.min)
1430                                 pstate_table->gfxclk_pstate.custom.min =
1431                                         pstate_table->gfxclk_pstate.curr.min;
1432
1433                         if (!pstate_table->gfxclk_pstate.custom.max)
1434                                 pstate_table->gfxclk_pstate.custom.max =
1435                                         pstate_table->gfxclk_pstate.curr.max;
1436
1437                         min_clk = pstate_table->gfxclk_pstate.custom.min;
1438                         max_clk = pstate_table->gfxclk_pstate.custom.max;
1439
1440                         return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1441                 }
1442                 break;
1443         default:
1444                 return -ENOSYS;
1445         }
1446
1447         return ret;
1448 }
1449
1450 static bool aldebaran_is_dpm_running(struct smu_context *smu)
1451 {
1452         int ret;
1453         uint32_t feature_mask[2];
1454         unsigned long feature_enabled;
1455
1456         ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1457         if (ret)
1458                 return false;
1459         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1460                                           ((uint64_t)feature_mask[1] << 32));
1461         return !!(feature_enabled & SMC_DPM_FEATURE);
1462 }
1463
1464 static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap,
1465                               struct i2c_msg *msg, int num_msgs)
1466 {
1467         struct amdgpu_device *adev = to_amdgpu_device(i2c_adap);
1468         struct smu_table_context *smu_table = &adev->smu.smu_table;
1469         struct smu_table *table = &smu_table->driver_table;
1470         SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
1471         int i, j, r, c;
1472         u16 dir;
1473
1474         req = kzalloc(sizeof(*req), GFP_KERNEL);
1475         if (!req)
1476                 return -ENOMEM;
1477
1478         req->I2CcontrollerPort = 0;
1479         req->I2CSpeed = I2C_SPEED_FAST_400K;
1480         req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
1481         dir = msg[0].flags & I2C_M_RD;
1482
1483         for (c = i = 0; i < num_msgs; i++) {
1484                 for (j = 0; j < msg[i].len; j++, c++) {
1485                         SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
1486
1487                         if (!(msg[i].flags & I2C_M_RD)) {
1488                                 /* write */
1489                                 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
1490                                 cmd->ReadWriteData = msg[i].buf[j];
1491                         }
1492
1493                         if ((dir ^ msg[i].flags) & I2C_M_RD) {
1494                                 /* The direction changes.
1495                                  */
1496                                 dir = msg[i].flags & I2C_M_RD;
1497                                 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
1498                         }
1499
1500                         req->NumCmds++;
1501
1502                         /*
1503                          * Insert STOP if we are at the last byte of either last
1504                          * message for the transaction or the client explicitly
1505                          * requires a STOP at this particular message.
1506                          */
1507                         if ((j == msg[i].len - 1) &&
1508                             ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
1509                                 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
1510                                 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
1511                         }
1512                 }
1513         }
1514         mutex_lock(&adev->smu.mutex);
1515         r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
1516         mutex_unlock(&adev->smu.mutex);
1517         if (r)
1518                 goto fail;
1519
1520         for (c = i = 0; i < num_msgs; i++) {
1521                 if (!(msg[i].flags & I2C_M_RD)) {
1522                         c += msg[i].len;
1523                         continue;
1524                 }
1525                 for (j = 0; j < msg[i].len; j++, c++) {
1526                         SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
1527
1528                         msg[i].buf[j] = cmd->ReadWriteData;
1529                 }
1530         }
1531         r = num_msgs;
1532 fail:
1533         kfree(req);
1534         return r;
1535 }
1536
1537 static u32 aldebaran_i2c_func(struct i2c_adapter *adap)
1538 {
1539         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1540 }
1541
1542
1543 static const struct i2c_algorithm aldebaran_i2c_algo = {
1544         .master_xfer = aldebaran_i2c_xfer,
1545         .functionality = aldebaran_i2c_func,
1546 };
1547
1548 static const struct i2c_adapter_quirks aldebaran_i2c_control_quirks = {
1549         .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
1550         .max_read_len  = MAX_SW_I2C_COMMANDS,
1551         .max_write_len = MAX_SW_I2C_COMMANDS,
1552         .max_comb_1st_msg_len = 2,
1553         .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
1554 };
1555
1556 static int aldebaran_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
1557 {
1558         struct amdgpu_device *adev = to_amdgpu_device(control);
1559         int res;
1560
1561         control->owner = THIS_MODULE;
1562         control->class = I2C_CLASS_SPD;
1563         control->dev.parent = &adev->pdev->dev;
1564         control->algo = &aldebaran_i2c_algo;
1565         snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
1566         control->quirks = &aldebaran_i2c_control_quirks;
1567
1568         res = i2c_add_adapter(control);
1569         if (res)
1570                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
1571
1572         return res;
1573 }
1574
1575 static void aldebaran_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
1576 {
1577         i2c_del_adapter(control);
1578 }
1579
1580 static void aldebaran_get_unique_id(struct smu_context *smu)
1581 {
1582         struct amdgpu_device *adev = smu->adev;
1583         SmuMetrics_t *metrics = smu->smu_table.metrics_table;
1584         uint32_t upper32 = 0, lower32 = 0;
1585         int ret;
1586
1587         mutex_lock(&smu->metrics_lock);
1588         ret = smu_cmn_get_metrics_table_locked(smu, NULL, false);
1589         if (ret)
1590                 goto out_unlock;
1591
1592         upper32 = metrics->PublicSerialNumUpper32;
1593         lower32 = metrics->PublicSerialNumLower32;
1594
1595 out_unlock:
1596         mutex_unlock(&smu->metrics_lock);
1597
1598         adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1599         sprintf(adev->serial, "%016llx", adev->unique_id);
1600 }
1601
1602 static bool aldebaran_is_baco_supported(struct smu_context *smu)
1603 {
1604         /* aldebaran is not support baco */
1605
1606         return false;
1607 }
1608
1609 static int aldebaran_set_df_cstate(struct smu_context *smu,
1610                                    enum pp_df_cstate state)
1611 {
1612         return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
1613 }
1614
1615 static int aldebaran_allow_xgmi_power_down(struct smu_context *smu, bool en)
1616 {
1617         return smu_cmn_send_smc_msg_with_param(smu,
1618                                                SMU_MSG_GmiPwrDnControl,
1619                                                en ? 1 : 0,
1620                                                NULL);
1621 }
1622
1623 static const struct throttling_logging_label {
1624         uint32_t feature_mask;
1625         const char *label;
1626 } logging_label[] = {
1627         {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
1628         {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
1629         {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
1630         {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
1631 };
1632 static void aldebaran_log_thermal_throttling_event(struct smu_context *smu)
1633 {
1634         int ret;
1635         int throttler_idx, throtting_events = 0, buf_idx = 0;
1636         struct amdgpu_device *adev = smu->adev;
1637         uint32_t throttler_status;
1638         char log_buf[256];
1639
1640         ret = aldebaran_get_smu_metrics_data(smu,
1641                                              METRICS_THROTTLER_STATUS,
1642                                              &throttler_status);
1643         if (ret)
1644                 return;
1645
1646         memset(log_buf, 0, sizeof(log_buf));
1647         for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
1648              throttler_idx++) {
1649                 if (throttler_status & logging_label[throttler_idx].feature_mask) {
1650                         throtting_events++;
1651                         buf_idx += snprintf(log_buf + buf_idx,
1652                                             sizeof(log_buf) - buf_idx,
1653                                             "%s%s",
1654                                             throtting_events > 1 ? " and " : "",
1655                                             logging_label[throttler_idx].label);
1656                         if (buf_idx >= sizeof(log_buf)) {
1657                                 dev_err(adev->dev, "buffer overflow!\n");
1658                                 log_buf[sizeof(log_buf) - 1] = '\0';
1659                                 break;
1660                         }
1661                 }
1662         }
1663
1664         dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
1665                  log_buf);
1666         kgd2kfd_smi_event_throttle(smu->adev->kfd.dev,
1667                 smu_cmn_get_indep_throttler_status(throttler_status,
1668                                                    aldebaran_throttler_map));
1669 }
1670
1671 static int aldebaran_get_current_pcie_link_speed(struct smu_context *smu)
1672 {
1673         struct amdgpu_device *adev = smu->adev;
1674         uint32_t esm_ctrl;
1675
1676         /* TODO: confirm this on real target */
1677         esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
1678         if ((esm_ctrl >> 15) & 0x1FFFF)
1679                 return (((esm_ctrl >> 8) & 0x3F) + 128);
1680
1681         return smu_v13_0_get_current_pcie_link_speed(smu);
1682 }
1683
1684 static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu,
1685                                          void **table)
1686 {
1687         struct smu_table_context *smu_table = &smu->smu_table;
1688         struct gpu_metrics_v1_3 *gpu_metrics =
1689                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
1690         SmuMetrics_t metrics;
1691         int i, ret = 0;
1692
1693         ret = smu_cmn_get_metrics_table(smu,
1694                                         &metrics,
1695                                         true);
1696         if (ret)
1697                 return ret;
1698
1699         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
1700
1701         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
1702         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
1703         gpu_metrics->temperature_mem = metrics.TemperatureHBM;
1704         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
1705         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
1706         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
1707
1708         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
1709         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
1710         gpu_metrics->average_mm_activity = 0;
1711
1712         /* Valid power data is available only from primary die */
1713         if (aldebaran_is_primary(smu)) {
1714                 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
1715                 gpu_metrics->energy_accumulator =
1716                         (uint64_t)metrics.EnergyAcc64bitHigh << 32 |
1717                         metrics.EnergyAcc64bitLow;
1718         } else {
1719                 gpu_metrics->average_socket_power = 0;
1720                 gpu_metrics->energy_accumulator = 0;
1721         }
1722
1723         gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
1724         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
1725         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
1726         gpu_metrics->average_vclk0_frequency = 0;
1727         gpu_metrics->average_dclk0_frequency = 0;
1728
1729         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
1730         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
1731         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
1732         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
1733         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
1734
1735         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1736         gpu_metrics->indep_throttle_status =
1737                         smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1738                                                            aldebaran_throttler_map);
1739
1740         gpu_metrics->current_fan_speed = 0;
1741
1742         gpu_metrics->pcie_link_width =
1743                 smu_v13_0_get_current_pcie_link_width(smu);
1744         gpu_metrics->pcie_link_speed =
1745                 aldebaran_get_current_pcie_link_speed(smu);
1746
1747         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1748
1749         gpu_metrics->gfx_activity_acc = metrics.GfxBusyAcc;
1750         gpu_metrics->mem_activity_acc = metrics.DramBusyAcc;
1751
1752         for (i = 0; i < NUM_HBM_INSTANCES; i++)
1753                 gpu_metrics->temperature_hbm[i] = metrics.TemperatureAllHBM[i];
1754
1755         gpu_metrics->firmware_timestamp = ((uint64_t)metrics.TimeStampHigh << 32) |
1756                                         metrics.TimeStampLow;
1757
1758         *table = (void *)gpu_metrics;
1759
1760         return sizeof(struct gpu_metrics_v1_3);
1761 }
1762
1763 static int aldebaran_mode2_reset(struct smu_context *smu)
1764 {
1765         u32 smu_version;
1766         int ret = 0, index;
1767         struct amdgpu_device *adev = smu->adev;
1768         int timeout = 10;
1769
1770         smu_cmn_get_smc_version(smu, NULL, &smu_version);
1771
1772         index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
1773                                                 SMU_MSG_GfxDeviceDriverReset);
1774
1775         mutex_lock(&smu->message_lock);
1776         if (smu_version >= 0x00441400) {
1777                 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2);
1778                 /* This is similar to FLR, wait till max FLR timeout */
1779                 msleep(100);
1780                 dev_dbg(smu->adev->dev, "restore config space...\n");
1781                 /* Restore the config space saved during init */
1782                 amdgpu_device_load_pci_state(adev->pdev);
1783
1784                 dev_dbg(smu->adev->dev, "wait for reset ack\n");
1785                 while (ret == -ETIME && timeout)  {
1786                         ret = smu_cmn_wait_for_response(smu);
1787                         /* Wait a bit more time for getting ACK */
1788                         if (ret == -ETIME) {
1789                                 --timeout;
1790                                 usleep_range(500, 1000);
1791                                 continue;
1792                         }
1793
1794                         if (ret != 1) {
1795                                 dev_err(adev->dev, "failed to send mode2 message \tparam: 0x%08x response %#x\n",
1796                                                 SMU_RESET_MODE_2, ret);
1797                                 goto out;
1798                         }
1799                 }
1800
1801         } else {
1802                 dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n",
1803                                 smu_version);
1804         }
1805
1806         if (ret == 1)
1807                 ret = 0;
1808 out:
1809         mutex_unlock(&smu->message_lock);
1810
1811         return ret;
1812 }
1813
1814 static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu)
1815 {
1816 #if 0
1817         struct amdgpu_device *adev = smu->adev;
1818         u32 smu_version;
1819         uint32_t val;
1820         /**
1821          * PM FW version support mode1 reset from 68.07
1822          */
1823         smu_cmn_get_smc_version(smu, NULL, &smu_version);
1824         if ((smu_version < 0x00440700))
1825                 return false;
1826         /**
1827          * mode1 reset relies on PSP, so we should check if
1828          * PSP is alive.
1829          */
1830         val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
1831
1832         return val != 0x0;
1833 #endif
1834         return true;
1835 }
1836
1837 static bool aldebaran_is_mode2_reset_supported(struct smu_context *smu)
1838 {
1839         return true;
1840 }
1841
1842 static int aldebaran_set_mp1_state(struct smu_context *smu,
1843                                    enum pp_mp1_state mp1_state)
1844 {
1845         switch (mp1_state) {
1846         case PP_MP1_STATE_UNLOAD:
1847                 return smu_cmn_set_mp1_state(smu, mp1_state);
1848         default:
1849                 return 0;
1850         }
1851 }
1852
1853 static int aldebaran_smu_send_hbm_bad_page_num(struct smu_context *smu,
1854                 uint32_t size)
1855 {
1856         int ret = 0;
1857
1858         /* message SMU to update the bad page number on SMUBUS */
1859         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL);
1860         if (ret)
1861                 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad pages number\n",
1862                                 __func__);
1863
1864         return ret;
1865 }
1866
1867 static const struct pptable_funcs aldebaran_ppt_funcs = {
1868         /* init dpm */
1869         .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask,
1870         /* dpm/clk tables */
1871         .set_default_dpm_table = aldebaran_set_default_dpm_table,
1872         .populate_umd_state_clk = aldebaran_populate_umd_state_clk,
1873         .get_thermal_temperature_range = aldebaran_get_thermal_temperature_range,
1874         .print_clk_levels = aldebaran_print_clk_levels,
1875         .force_clk_levels = aldebaran_force_clk_levels,
1876         .read_sensor = aldebaran_read_sensor,
1877         .set_performance_level = aldebaran_set_performance_level,
1878         .get_power_limit = aldebaran_get_power_limit,
1879         .is_dpm_running = aldebaran_is_dpm_running,
1880         .get_unique_id = aldebaran_get_unique_id,
1881         .init_microcode = smu_v13_0_init_microcode,
1882         .load_microcode = smu_v13_0_load_microcode,
1883         .fini_microcode = smu_v13_0_fini_microcode,
1884         .init_smc_tables = aldebaran_init_smc_tables,
1885         .fini_smc_tables = smu_v13_0_fini_smc_tables,
1886         .init_power = smu_v13_0_init_power,
1887         .fini_power = smu_v13_0_fini_power,
1888         .check_fw_status = smu_v13_0_check_fw_status,
1889         /* pptable related */
1890         .setup_pptable = aldebaran_setup_pptable,
1891         .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
1892         .check_fw_version = smu_v13_0_check_fw_version,
1893         .write_pptable = smu_cmn_write_pptable,
1894         .set_driver_table_location = smu_v13_0_set_driver_table_location,
1895         .set_tool_table_location = smu_v13_0_set_tool_table_location,
1896         .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
1897         .system_features_control = aldebaran_system_features_control,
1898         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1899         .send_smc_msg = smu_cmn_send_smc_msg,
1900         .get_enabled_mask = smu_cmn_get_enabled_mask,
1901         .feature_is_enabled = smu_cmn_feature_is_enabled,
1902         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
1903         .set_power_limit = aldebaran_set_power_limit,
1904         .init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks,
1905         .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
1906         .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
1907         .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate,
1908         .register_irq_handler = smu_v13_0_register_irq_handler,
1909         .set_azalia_d3_pme = smu_v13_0_set_azalia_d3_pme,
1910         .get_max_sustainable_clocks_by_dc = smu_v13_0_get_max_sustainable_clocks_by_dc,
1911         .baco_is_support= aldebaran_is_baco_supported,
1912         .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq,
1913         .set_soft_freq_limited_range = aldebaran_set_soft_freq_limited_range,
1914         .od_edit_dpm_table = aldebaran_usr_edit_dpm_table,
1915         .set_df_cstate = aldebaran_set_df_cstate,
1916         .allow_xgmi_power_down = aldebaran_allow_xgmi_power_down,
1917         .log_thermal_throttling_event = aldebaran_log_thermal_throttling_event,
1918         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1919         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
1920         .get_gpu_metrics = aldebaran_get_gpu_metrics,
1921         .mode1_reset_is_support = aldebaran_is_mode1_reset_supported,
1922         .mode2_reset_is_support = aldebaran_is_mode2_reset_supported,
1923         .mode1_reset = smu_v13_0_mode1_reset,
1924         .set_mp1_state = aldebaran_set_mp1_state,
1925         .mode2_reset = aldebaran_mode2_reset,
1926         .wait_for_event = smu_v13_0_wait_for_event,
1927         .i2c_init = aldebaran_i2c_control_init,
1928         .i2c_fini = aldebaran_i2c_control_fini,
1929         .send_hbm_bad_pages_num = aldebaran_smu_send_hbm_bad_page_num,
1930 };
1931
1932 void aldebaran_set_ppt_funcs(struct smu_context *smu)
1933 {
1934         smu->ppt_funcs = &aldebaran_ppt_funcs;
1935         smu->message_map = aldebaran_message_map;
1936         smu->clock_map = aldebaran_clk_map;
1937         smu->feature_map = aldebaran_feature_mask_map;
1938         smu->table_map = aldebaran_table_map;
1939 }