drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_smu.h"
  29 #include "atomfirmware.h"
  30 #include "amdgpu_atomfirmware.h"
  31 #include "amdgpu_atombios.h"
  32 #include "smu_v13_0.h"
  33 #include "smu13_driver_if_aldebaran.h"
  34 #include "soc15_common.h"
  35 #include "atom.h"
  36 #include "power_state.h"
  37 #include "aldebaran_ppt.h"
  38 #include "smu_v13_0_pptable.h"
  39 #include "aldebaran_ppsmc.h"
  40 #include "nbio/nbio_7_4_offset.h"
  41 #include "nbio/nbio_7_4_sh_mask.h"
  42 #include "thm/thm_11_0_2_offset.h"
  43 #include "thm/thm_11_0_2_sh_mask.h"
  44 #include "amdgpu_xgmi.h"
  45 #include <linux/pci.h>
  46 #include "amdgpu_ras.h"
  47 #include "smu_cmn.h"
  48 #include "mp/mp_13_0_2_offset.h"
  49
  50 /*
  51  * DO NOT use these for err/warn/info/debug messages.
  52  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  53  * They are more MGPU friendly.
  54  */
  55 #undef pr_err
  56 #undef pr_warn
  57 #undef pr_info
  58 #undef pr_debug
  59
  60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  61
  62 #define ALDEBARAN_FEA_MAP(smu_feature, aldebaran_feature) \
  63         [smu_feature] = {1, (aldebaran_feature)}
  64
  65 #define FEATURE_MASK(feature) (1ULL << feature)
  66 #define SMC_DPM_FEATURE ( \
  67                           FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \
  68                           FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)  | \
  69                           FEATURE_MASK(FEATURE_DPM_UCLK_BIT)    | \
  70                           FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)  | \
  71                           FEATURE_MASK(FEATURE_DPM_FCLK_BIT)    | \
  72                           FEATURE_MASK(FEATURE_DPM_LCLK_BIT)    | \
  73                           FEATURE_MASK(FEATURE_DPM_XGMI_BIT)    | \
  74                           FEATURE_MASK(FEATURE_DPM_VCN_BIT))
  75
  76 /* possible frequency drift (1Mhz) */
  77 #define EPSILON                         1
  78
  79 #define smnPCIE_ESM_CTRL                        0x111003D0
  80
  81 static const struct smu_temperature_range smu13_thermal_policy[] =
  82 {
  83         {-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
  84         { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
  85 };
  86
  87 static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = {
  88         MSG_MAP(TestMessage,                         PPSMC_MSG_TestMessage,                     0),
  89         MSG_MAP(GetSmuVersion,                       PPSMC_MSG_GetSmuVersion,                   1),
  90         MSG_MAP(GetDriverIfVersion,                  PPSMC_MSG_GetDriverIfVersion,              1),
  91         MSG_MAP(EnableAllSmuFeatures,                PPSMC_MSG_EnableAllSmuFeatures,            0),
  92         MSG_MAP(DisableAllSmuFeatures,               PPSMC_MSG_DisableAllSmuFeatures,           0),
  93         MSG_MAP(GetEnabledSmuFeaturesLow,            PPSMC_MSG_GetEnabledSmuFeaturesLow,        0),
  94         MSG_MAP(GetEnabledSmuFeaturesHigh,           PPSMC_MSG_GetEnabledSmuFeaturesHigh,       0),
  95         MSG_MAP(SetDriverDramAddrHigh,               PPSMC_MSG_SetDriverDramAddrHigh,           1),
  96         MSG_MAP(SetDriverDramAddrLow,                PPSMC_MSG_SetDriverDramAddrLow,            1),
  97         MSG_MAP(SetToolsDramAddrHigh,                PPSMC_MSG_SetToolsDramAddrHigh,            0),
  98         MSG_MAP(SetToolsDramAddrLow,                 PPSMC_MSG_SetToolsDramAddrLow,             0),
  99         MSG_MAP(TransferTableSmu2Dram,               PPSMC_MSG_TransferTableSmu2Dram,           1),
 100         MSG_MAP(TransferTableDram2Smu,               PPSMC_MSG_TransferTableDram2Smu,           0),
 101         MSG_MAP(UseDefaultPPTable,                   PPSMC_MSG_UseDefaultPPTable,               0),
 102         MSG_MAP(SetSystemVirtualDramAddrHigh,        PPSMC_MSG_SetSystemVirtualDramAddrHigh,    0),
 103         MSG_MAP(SetSystemVirtualDramAddrLow,         PPSMC_MSG_SetSystemVirtualDramAddrLow,     0),
 104         MSG_MAP(SetSoftMinByFreq,                    PPSMC_MSG_SetSoftMinByFreq,                0),
 105         MSG_MAP(SetSoftMaxByFreq,                    PPSMC_MSG_SetSoftMaxByFreq,                0),
 106         MSG_MAP(SetHardMinByFreq,                    PPSMC_MSG_SetHardMinByFreq,                0),
 107         MSG_MAP(SetHardMaxByFreq,                    PPSMC_MSG_SetHardMaxByFreq,                0),
 108         MSG_MAP(GetMinDpmFreq,                       PPSMC_MSG_GetMinDpmFreq,                   0),
 109         MSG_MAP(GetMaxDpmFreq,                       PPSMC_MSG_GetMaxDpmFreq,                   0),
 110         MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex,               1),
 111         MSG_MAP(SetWorkloadMask,                     PPSMC_MSG_SetWorkloadMask,                 1),
 112         MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm,                 0),
 113         MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive,        0),
 114         MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit,                     0),
 115         MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit,                     1),
 116         MSG_MAP(PrepareMp1ForUnload,                 PPSMC_MSG_PrepareMp1ForUnload,             0),
 117         MSG_MAP(GfxDeviceDriverReset,                PPSMC_MSG_GfxDriverReset,                  0),
 118         MSG_MAP(RunDcBtc,                            PPSMC_MSG_RunDcBtc,                        0),
 119         MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh,          0),
 120         MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow,           0),
 121         MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize,              0),
 122         MSG_MAP(GetDebugData,                        PPSMC_MSG_GetDebugData,                    0),
 123         MSG_MAP(WaflTest,                            PPSMC_MSG_WaflTest,                        0),
 124         MSG_MAP(SetMemoryChannelEnable,              PPSMC_MSG_SetMemoryChannelEnable,          0),
 125         MSG_MAP(SetNumBadHbmPagesRetired,            PPSMC_MSG_SetNumBadHbmPagesRetired,        0),
 126         MSG_MAP(DFCstateControl,                     PPSMC_MSG_DFCstateControl,                 0),
 127         MSG_MAP(GetGmiPwrDnHyst,                     PPSMC_MSG_GetGmiPwrDnHyst,                 0),
 128         MSG_MAP(SetGmiPwrDnHyst,                     PPSMC_MSG_SetGmiPwrDnHyst,                 0),
 129         MSG_MAP(GmiPwrDnControl,                     PPSMC_MSG_GmiPwrDnControl,                 0),
 130         MSG_MAP(EnterGfxoff,                         PPSMC_MSG_EnterGfxoff,                     0),
 131         MSG_MAP(ExitGfxoff,                          PPSMC_MSG_ExitGfxoff,                      0),
 132         MSG_MAP(SetExecuteDMATest,                   PPSMC_MSG_SetExecuteDMATest,               0),
 133         MSG_MAP(EnableDeterminism,                   PPSMC_MSG_EnableDeterminism,               0),
 134         MSG_MAP(DisableDeterminism,                  PPSMC_MSG_DisableDeterminism,              0),
 135         MSG_MAP(SetUclkDpmMode,                      PPSMC_MSG_SetUclkDpmMode,                  0),
 136         MSG_MAP(GfxDriverResetRecovery,              PPSMC_MSG_GfxDriverResetRecovery,          0),
 137         MSG_MAP(BoardPowerCalibration,               PPSMC_MSG_BoardPowerCalibration,           0),
 138 };
 139
 140 static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = {
 141         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 142         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 143         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 144         CLK_MAP(FCLK, PPCLK_FCLK),
 145         CLK_MAP(UCLK, PPCLK_UCLK),
 146         CLK_MAP(MCLK, PPCLK_UCLK),
 147         CLK_MAP(DCLK, PPCLK_DCLK),
 148         CLK_MAP(VCLK, PPCLK_VCLK),
 149         CLK_MAP(LCLK,   PPCLK_LCLK),
 150 };
 151
 152 static const struct cmn2asic_mapping aldebaran_feature_mask_map[SMU_FEATURE_COUNT] = {
 153         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_PREFETCHER_BIT,               FEATURE_DATA_CALCULATIONS),
 154         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT,                   FEATURE_DPM_GFXCLK_BIT),
 155         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT,                     FEATURE_DPM_UCLK_BIT),
 156         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT,                   FEATURE_DPM_SOCCLK_BIT),
 157         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT,                     FEATURE_DPM_FCLK_BIT),
 158         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT,                     FEATURE_DPM_LCLK_BIT),
 159         ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_BIT,                                 FEATURE_DPM_XGMI_BIT),
 160         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT,                    FEATURE_DS_GFXCLK_BIT),
 161         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT,                    FEATURE_DS_SOCCLK_BIT),
 162         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT,                              FEATURE_DS_LCLK_BIT),
 163         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT,                              FEATURE_DS_FCLK_BIT),
 164         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_UCLK_BIT,                              FEATURE_DS_UCLK_BIT),
 165         ALDEBARAN_FEA_MAP(SMU_FEATURE_GFX_SS_BIT,                               FEATURE_GFX_SS_BIT),
 166         ALDEBARAN_FEA_MAP(SMU_FEATURE_VCN_PG_BIT,                               FEATURE_DPM_VCN_BIT),
 167         ALDEBARAN_FEA_MAP(SMU_FEATURE_RSMU_SMN_CG_BIT,                  FEATURE_RSMU_SMN_CG_BIT),
 168         ALDEBARAN_FEA_MAP(SMU_FEATURE_WAFL_CG_BIT,                              FEATURE_WAFL_CG_BIT),
 169         ALDEBARAN_FEA_MAP(SMU_FEATURE_PPT_BIT,                                  FEATURE_PPT_BIT),
 170         ALDEBARAN_FEA_MAP(SMU_FEATURE_TDC_BIT,                                  FEATURE_TDC_BIT),
 171         ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_PLUS_BIT,                    FEATURE_APCC_PLUS_BIT),
 172         ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT,                    FEATURE_APCC_DFLL_BIT),
 173         ALDEBARAN_FEA_MAP(SMU_FEATURE_FUSE_CG_BIT,                              FEATURE_FUSE_CG_BIT),
 174         ALDEBARAN_FEA_MAP(SMU_FEATURE_MP1_CG_BIT,                               FEATURE_MP1_CG_BIT),
 175         ALDEBARAN_FEA_MAP(SMU_FEATURE_SMUIO_CG_BIT,                     FEATURE_SMUIO_CG_BIT),
 176         ALDEBARAN_FEA_MAP(SMU_FEATURE_THM_CG_BIT,                               FEATURE_THM_CG_BIT),
 177         ALDEBARAN_FEA_MAP(SMU_FEATURE_CLK_CG_BIT,                               FEATURE_CLK_CG_BIT),
 178         ALDEBARAN_FEA_MAP(SMU_FEATURE_FW_CTF_BIT,                               FEATURE_FW_CTF_BIT),
 179         ALDEBARAN_FEA_MAP(SMU_FEATURE_THERMAL_BIT,                              FEATURE_THERMAL_BIT),
 180         ALDEBARAN_FEA_MAP(SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT,  FEATURE_OUT_OF_BAND_MONITOR_BIT),
 181         ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT,FEATURE_XGMI_PER_LINK_PWR_DWN),
 182         ALDEBARAN_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT,                    FEATURE_DF_CSTATE),
 183 };
 184
 185 static const struct cmn2asic_mapping aldebaran_table_map[SMU_TABLE_COUNT] = {
 186         TAB_MAP(PPTABLE),
 187         TAB_MAP(AVFS_PSM_DEBUG),
 188         TAB_MAP(AVFS_FUSE_OVERRIDE),
 189         TAB_MAP(PMSTATUSLOG),
 190         TAB_MAP(SMU_METRICS),
 191         TAB_MAP(DRIVER_SMU_CONFIG),
 192         TAB_MAP(I2C_COMMANDS),
 193 };
 194
 195 static const uint8_t aldebaran_throttler_map[] = {
 196         [THROTTLER_PPT0_BIT]            = (SMU_THROTTLER_PPT0_BIT),
 197         [THROTTLER_PPT1_BIT]            = (SMU_THROTTLER_PPT1_BIT),
 198         [THROTTLER_TDC_GFX_BIT]         = (SMU_THROTTLER_TDC_GFX_BIT),
 199         [THROTTLER_TDC_SOC_BIT]         = (SMU_THROTTLER_TDC_SOC_BIT),
 200         [THROTTLER_TDC_HBM_BIT]         = (SMU_THROTTLER_TDC_MEM_BIT),
 201         [THROTTLER_TEMP_GPU_BIT]        = (SMU_THROTTLER_TEMP_GPU_BIT),
 202         [THROTTLER_TEMP_MEM_BIT]        = (SMU_THROTTLER_TEMP_MEM_BIT),
 203         [THROTTLER_TEMP_VR_GFX_BIT]     = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
 204         [THROTTLER_TEMP_VR_SOC_BIT]     = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
 205         [THROTTLER_TEMP_VR_MEM_BIT]     = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
 206         [THROTTLER_APCC_BIT]            = (SMU_THROTTLER_APCC_BIT),
 207 };
 208
 209 static int aldebaran_tables_init(struct smu_context *smu)
 210 {
 211         struct smu_table_context *smu_table = &smu->smu_table;
 212         struct smu_table *tables = smu_table->tables;
 213
 214         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 215                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 216
 217         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
 218                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 219
 220         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 221                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 222
 223         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 224                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 225
 226         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 227         if (!smu_table->metrics_table)
 228                 return -ENOMEM;
 229         smu_table->metrics_time = 0;
 230
 231         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 232         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 233         if (!smu_table->gpu_metrics_table) {
 234                 kfree(smu_table->metrics_table);
 235                 return -ENOMEM;
 236         }
 237
 238         return 0;
 239 }
 240
 241 static int aldebaran_allocate_dpm_context(struct smu_context *smu)
 242 {
 243         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 244
 245         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
 246                                        GFP_KERNEL);
 247         if (!smu_dpm->dpm_context)
 248                 return -ENOMEM;
 249         smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
 250
 251         smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 252                                                    GFP_KERNEL);
 253         if (!smu_dpm->dpm_current_power_state)
 254                 return -ENOMEM;
 255
 256         smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 257                                                    GFP_KERNEL);
 258         if (!smu_dpm->dpm_request_power_state)
 259                 return -ENOMEM;
 260
 261         return 0;
 262 }
 263
 264 static int aldebaran_init_smc_tables(struct smu_context *smu)
 265 {
 266         int ret = 0;
 267
 268         ret = aldebaran_tables_init(smu);
 269         if (ret)
 270                 return ret;
 271
 272         ret = aldebaran_allocate_dpm_context(smu);
 273         if (ret)
 274                 return ret;
 275
 276         return smu_v13_0_init_smc_tables(smu);
 277 }
 278
 279 static int aldebaran_get_allowed_feature_mask(struct smu_context *smu,
 280                                               uint32_t *feature_mask, uint32_t num)
 281 {
 282         if (num > 2)
 283                 return -EINVAL;
 284
 285         /* pptable will handle the features to enable */
 286         memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
 287
 288         return 0;
 289 }
 290
 291 static int aldebaran_set_default_dpm_table(struct smu_context *smu)
 292 {
 293         struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 294         struct smu_13_0_dpm_table *dpm_table = NULL;
 295         PPTable_t *pptable = smu->smu_table.driver_pptable;
 296         int ret = 0;
 297
 298         /* socclk dpm table setup */
 299         dpm_table = &dpm_context->dpm_tables.soc_table;
 300         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 301                 ret = smu_v13_0_set_single_dpm_table(smu,
 302                                                      SMU_SOCCLK,
 303                                                      dpm_table);
 304                 if (ret)
 305                         return ret;
 306         } else {
 307                 dpm_table->count = 1;
 308                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 309                 dpm_table->dpm_levels[0].enabled = true;
 310                 dpm_table->min = dpm_table->dpm_levels[0].value;
 311                 dpm_table->max = dpm_table->dpm_levels[0].value;
 312         }
 313
 314         /* gfxclk dpm table setup */
 315         dpm_table = &dpm_context->dpm_tables.gfx_table;
 316         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 317                 /* in the case of gfxclk, only fine-grained dpm is honored */
 318                 dpm_table->count = 2;
 319                 dpm_table->dpm_levels[0].value = pptable->GfxclkFmin;
 320                 dpm_table->dpm_levels[0].enabled = true;
 321                 dpm_table->dpm_levels[1].value = pptable->GfxclkFmax;
 322                 dpm_table->dpm_levels[1].enabled = true;
 323                 dpm_table->min = dpm_table->dpm_levels[0].value;
 324                 dpm_table->max = dpm_table->dpm_levels[1].value;
 325         } else {
 326                 dpm_table->count = 1;
 327                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 328                 dpm_table->dpm_levels[0].enabled = true;
 329                 dpm_table->min = dpm_table->dpm_levels[0].value;
 330                 dpm_table->max = dpm_table->dpm_levels[0].value;
 331         }
 332
 333         /* memclk dpm table setup */
 334         dpm_table = &dpm_context->dpm_tables.uclk_table;
 335         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 336                 ret = smu_v13_0_set_single_dpm_table(smu,
 337                                                      SMU_UCLK,
 338                                                      dpm_table);
 339                 if (ret)
 340                         return ret;
 341         } else {
 342                 dpm_table->count = 1;
 343                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 344                 dpm_table->dpm_levels[0].enabled = true;
 345                 dpm_table->min = dpm_table->dpm_levels[0].value;
 346                 dpm_table->max = dpm_table->dpm_levels[0].value;
 347         }
 348
 349         /* fclk dpm table setup */
 350         dpm_table = &dpm_context->dpm_tables.fclk_table;
 351         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 352                 ret = smu_v13_0_set_single_dpm_table(smu,
 353                                                      SMU_FCLK,
 354                                                      dpm_table);
 355                 if (ret)
 356                         return ret;
 357         } else {
 358                 dpm_table->count = 1;
 359                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 360                 dpm_table->dpm_levels[0].enabled = true;
 361                 dpm_table->min = dpm_table->dpm_levels[0].value;
 362                 dpm_table->max = dpm_table->dpm_levels[0].value;
 363         }
 364
 365         return 0;
 366 }
 367
 368 static int aldebaran_check_powerplay_table(struct smu_context *smu)
 369 {
 370         struct smu_table_context *table_context = &smu->smu_table;
 371         struct smu_13_0_powerplay_table *powerplay_table =
 372                 table_context->power_play_table;
 373
 374         table_context->thermal_controller_type =
 375                 powerplay_table->thermal_controller_type;
 376
 377         return 0;
 378 }
 379
 380 static int aldebaran_store_powerplay_table(struct smu_context *smu)
 381 {
 382         struct smu_table_context *table_context = &smu->smu_table;
 383         struct smu_13_0_powerplay_table *powerplay_table =
 384                 table_context->power_play_table;
 385         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 386                sizeof(PPTable_t));
 387
 388         return 0;
 389 }
 390
 391 static int aldebaran_append_powerplay_table(struct smu_context *smu)
 392 {
 393         struct smu_table_context *table_context = &smu->smu_table;
 394         PPTable_t *smc_pptable = table_context->driver_pptable;
 395         struct atom_smc_dpm_info_v4_10 *smc_dpm_table;
 396         int index, ret;
 397
 398         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 399                                            smc_dpm_info);
 400
 401         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 402                                       (uint8_t **)&smc_dpm_table);
 403         if (ret)
 404                 return ret;
 405
 406         dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
 407                         smc_dpm_table->table_header.format_revision,
 408                         smc_dpm_table->table_header.content_revision);
 409
 410         if ((smc_dpm_table->table_header.format_revision == 4) &&
 411             (smc_dpm_table->table_header.content_revision == 10))
 412                 memcpy(&smc_pptable->GfxMaxCurrent,
 413                        &smc_dpm_table->GfxMaxCurrent,
 414                        sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_10, GfxMaxCurrent));
 415         return 0;
 416 }
 417
 418 static int aldebaran_setup_pptable(struct smu_context *smu)
 419 {
 420         int ret = 0;
 421
 422         /* VBIOS pptable is the first choice */
 423         smu->smu_table.boot_values.pp_table_id = 0;
 424
 425         ret = smu_v13_0_setup_pptable(smu);
 426         if (ret)
 427                 return ret;
 428
 429         ret = aldebaran_store_powerplay_table(smu);
 430         if (ret)
 431                 return ret;
 432
 433         ret = aldebaran_append_powerplay_table(smu);
 434         if (ret)
 435                 return ret;
 436
 437         ret = aldebaran_check_powerplay_table(smu);
 438         if (ret)
 439                 return ret;
 440
 441         return ret;
 442 }
 443
 444 static bool aldebaran_is_primary(struct smu_context *smu)
 445 {
 446         struct amdgpu_device *adev = smu->adev;
 447
 448         if (adev->smuio.funcs && adev->smuio.funcs->get_die_id)
 449                 return adev->smuio.funcs->get_die_id(adev) == 0;
 450
 451         return true;
 452 }
 453
 454 static int aldebaran_run_board_btc(struct smu_context *smu)
 455 {
 456         u32 smu_version;
 457         int ret;
 458
 459         if (!aldebaran_is_primary(smu))
 460                 return 0;
 461
 462         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
 463         if (ret) {
 464                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
 465                 return ret;
 466         }
 467         if (smu_version <= 0x00441d00)
 468                 return 0;
 469
 470         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_BoardPowerCalibration, NULL);
 471         if (ret)
 472                 dev_err(smu->adev->dev, "Board power calibration failed!\n");
 473
 474         return ret;
 475 }
 476
 477 static int aldebaran_run_btc(struct smu_context *smu)
 478 {
 479         int ret;
 480
 481         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
 482         if (ret)
 483                 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
 484         else
 485                 ret = aldebaran_run_board_btc(smu);
 486
 487         return ret;
 488 }
 489
 490 static int aldebaran_populate_umd_state_clk(struct smu_context *smu)
 491 {
 492         struct smu_13_0_dpm_context *dpm_context =
 493                 smu->smu_dpm.dpm_context;
 494         struct smu_13_0_dpm_table *gfx_table =
 495                 &dpm_context->dpm_tables.gfx_table;
 496         struct smu_13_0_dpm_table *mem_table =
 497                 &dpm_context->dpm_tables.uclk_table;
 498         struct smu_13_0_dpm_table *soc_table =
 499                 &dpm_context->dpm_tables.soc_table;
 500         struct smu_umd_pstate_table *pstate_table =
 501                 &smu->pstate_table;
 502
 503         pstate_table->gfxclk_pstate.min = gfx_table->min;
 504         pstate_table->gfxclk_pstate.peak = gfx_table->max;
 505         pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
 506         pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
 507
 508         pstate_table->uclk_pstate.min = mem_table->min;
 509         pstate_table->uclk_pstate.peak = mem_table->max;
 510         pstate_table->uclk_pstate.curr.min = mem_table->min;
 511         pstate_table->uclk_pstate.curr.max = mem_table->max;
 512
 513         pstate_table->socclk_pstate.min = soc_table->min;
 514         pstate_table->socclk_pstate.peak = soc_table->max;
 515         pstate_table->socclk_pstate.curr.min = soc_table->min;
 516         pstate_table->socclk_pstate.curr.max = soc_table->max;
 517
 518         if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL &&
 519             mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL &&
 520             soc_table->count > ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL) {
 521                 pstate_table->gfxclk_pstate.standard =
 522                         gfx_table->dpm_levels[ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL].value;
 523                 pstate_table->uclk_pstate.standard =
 524                         mem_table->dpm_levels[ALDEBARAN_UMD_PSTATE_MCLK_LEVEL].value;
 525                 pstate_table->socclk_pstate.standard =
 526                         soc_table->dpm_levels[ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL].value;
 527         } else {
 528                 pstate_table->gfxclk_pstate.standard =
 529                         pstate_table->gfxclk_pstate.min;
 530                 pstate_table->uclk_pstate.standard =
 531                         pstate_table->uclk_pstate.min;
 532                 pstate_table->socclk_pstate.standard =
 533                         pstate_table->socclk_pstate.min;
 534         }
 535
 536         return 0;
 537 }
 538
 539 static int aldebaran_get_clk_table(struct smu_context *smu,
 540                                    struct pp_clock_levels_with_latency *clocks,
 541                                    struct smu_13_0_dpm_table *dpm_table)
 542 {
 543         int i, count;
 544
 545         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 546         clocks->num_levels = count;
 547
 548         for (i = 0; i < count; i++) {
 549                 clocks->data[i].clocks_in_khz =
 550                         dpm_table->dpm_levels[i].value * 1000;
 551                 clocks->data[i].latency_in_us = 0;
 552         }
 553
 554         return 0;
 555 }
 556
 557 static int aldebaran_freqs_in_same_level(int32_t frequency1,
 558                                          int32_t frequency2)
 559 {
 560         return (abs(frequency1 - frequency2) <= EPSILON);
 561 }
 562
 563 static int aldebaran_get_smu_metrics_data(struct smu_context *smu,
 564                                           MetricsMember_t member,
 565                                           uint32_t *value)
 566 {
 567         struct smu_table_context *smu_table= &smu->smu_table;
 568         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 569         int ret = 0;
 570
 571         mutex_lock(&smu->metrics_lock);
 572
 573         ret = smu_cmn_get_metrics_table_locked(smu,
 574                                                NULL,
 575                                                false);
 576         if (ret) {
 577                 mutex_unlock(&smu->metrics_lock);
 578                 return ret;
 579         }
 580
 581         switch (member) {
 582         case METRICS_CURR_GFXCLK:
 583                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 584                 break;
 585         case METRICS_CURR_SOCCLK:
 586                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 587                 break;
 588         case METRICS_CURR_UCLK:
 589                 *value = metrics->CurrClock[PPCLK_UCLK];
 590                 break;
 591         case METRICS_CURR_VCLK:
 592                 *value = metrics->CurrClock[PPCLK_VCLK];
 593                 break;
 594         case METRICS_CURR_DCLK:
 595                 *value = metrics->CurrClock[PPCLK_DCLK];
 596                 break;
 597         case METRICS_CURR_FCLK:
 598                 *value = metrics->CurrClock[PPCLK_FCLK];
 599                 break;
 600         case METRICS_AVERAGE_GFXCLK:
 601                 *value = metrics->AverageGfxclkFrequency;
 602                 break;
 603         case METRICS_AVERAGE_SOCCLK:
 604                 *value = metrics->AverageSocclkFrequency;
 605                 break;
 606         case METRICS_AVERAGE_UCLK:
 607                 *value = metrics->AverageUclkFrequency;
 608                 break;
 609         case METRICS_AVERAGE_GFXACTIVITY:
 610                 *value = metrics->AverageGfxActivity;
 611                 break;
 612         case METRICS_AVERAGE_MEMACTIVITY:
 613                 *value = metrics->AverageUclkActivity;
 614                 break;
 615         case METRICS_AVERAGE_SOCKETPOWER:
 616                 /* Valid power data is available only from primary die */
 617                 *value = aldebaran_is_primary(smu) ?
 618                                  metrics->AverageSocketPower << 8 :
 619                                  0;
 620                 break;
 621         case METRICS_TEMPERATURE_EDGE:
 622                 *value = metrics->TemperatureEdge *
 623                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 624                 break;
 625         case METRICS_TEMPERATURE_HOTSPOT:
 626                 *value = metrics->TemperatureHotspot *
 627                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 628                 break;
 629         case METRICS_TEMPERATURE_MEM:
 630                 *value = metrics->TemperatureHBM *
 631                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 632                 break;
 633         case METRICS_TEMPERATURE_VRGFX:
 634                 *value = metrics->TemperatureVrGfx *
 635                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 636                 break;
 637         case METRICS_TEMPERATURE_VRSOC:
 638                 *value = metrics->TemperatureVrSoc *
 639                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 640                 break;
 641         case METRICS_TEMPERATURE_VRMEM:
 642                 *value = metrics->TemperatureVrMem *
 643                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 644                 break;
 645         case METRICS_THROTTLER_STATUS:
 646                 *value = metrics->ThrottlerStatus;
 647                 break;
 648         default:
 649                 *value = UINT_MAX;
 650                 break;
 651         }
 652
 653         mutex_unlock(&smu->metrics_lock);
 654
 655         return ret;
 656 }
 657
 658 static int aldebaran_get_current_clk_freq_by_table(struct smu_context *smu,
 659                                                    enum smu_clk_type clk_type,
 660                                                    uint32_t *value)
 661 {
 662         MetricsMember_t member_type;
 663         int clk_id = 0;
 664
 665         if (!value)
 666                 return -EINVAL;
 667
 668         clk_id = smu_cmn_to_asic_specific_index(smu,
 669                                                 CMN2ASIC_MAPPING_CLK,
 670                                                 clk_type);
 671         if (clk_id < 0)
 672                 return -EINVAL;
 673
 674         switch (clk_id) {
 675         case PPCLK_GFXCLK:
 676                 /*
 677                  * CurrClock[clk_id] can provide accurate
 678                  *   output only when the dpm feature is enabled.
 679                  * We can use Average_* for dpm disabled case.
 680                  *   But this is available for gfxclk/uclk/socclk/vclk/dclk.
 681                  */
 682                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
 683                         member_type = METRICS_CURR_GFXCLK;
 684                 else
 685                         member_type = METRICS_AVERAGE_GFXCLK;
 686                 break;
 687         case PPCLK_UCLK:
 688                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
 689                         member_type = METRICS_CURR_UCLK;
 690                 else
 691                         member_type = METRICS_AVERAGE_UCLK;
 692                 break;
 693         case PPCLK_SOCCLK:
 694                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
 695                         member_type = METRICS_CURR_SOCCLK;
 696                 else
 697                         member_type = METRICS_AVERAGE_SOCCLK;
 698                 break;
 699         case PPCLK_VCLK:
 700                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
 701                         member_type = METRICS_CURR_VCLK;
 702                 else
 703                         member_type = METRICS_AVERAGE_VCLK;
 704                 break;
 705         case PPCLK_DCLK:
 706                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
 707                         member_type = METRICS_CURR_DCLK;
 708                 else
 709                         member_type = METRICS_AVERAGE_DCLK;
 710                 break;
 711         case PPCLK_FCLK:
 712                 member_type = METRICS_CURR_FCLK;
 713                 break;
 714         default:
 715                 return -EINVAL;
 716         }
 717
 718         return aldebaran_get_smu_metrics_data(smu,
 719                                               member_type,
 720                                               value);
 721 }
 722
 723 static int aldebaran_print_clk_levels(struct smu_context *smu,
 724                                       enum smu_clk_type type, char *buf)
 725 {
 726         int i, now, size = 0;
 727         int ret = 0;
 728         struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
 729         struct pp_clock_levels_with_latency clocks;
 730         struct smu_13_0_dpm_table *single_dpm_table;
 731         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 732         struct smu_13_0_dpm_context *dpm_context = NULL;
 733         uint32_t display_levels;
 734         uint32_t freq_values[3] = {0};
 735         uint32_t min_clk, max_clk;
 736
 737         if (amdgpu_ras_intr_triggered())
 738                 return snprintf(buf, PAGE_SIZE, "unavailable\n");
 739
 740         dpm_context = smu_dpm->dpm_context;
 741
 742         switch (type) {
 743
 744         case SMU_OD_SCLK:
 745                 size = sprintf(buf, "%s:\n", "GFXCLK");
 746                 fallthrough;
 747         case SMU_SCLK:
 748                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now);
 749                 if (ret) {
 750                         dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!");
 751                         return ret;
 752                 }
 753
 754                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 755                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 756                 if (ret) {
 757                         dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
 758                         return ret;
 759                 }
 760
 761                 display_levels = clocks.num_levels;
 762
 763                 min_clk = pstate_table->gfxclk_pstate.curr.min;
 764                 max_clk = pstate_table->gfxclk_pstate.curr.max;
 765
 766                 freq_values[0] = min_clk;
 767                 freq_values[1] = max_clk;
 768
 769                 /* fine-grained dpm has only 2 levels */
 770                 if (now > min_clk && now < max_clk) {
 771                         display_levels = clocks.num_levels + 1;
 772                         freq_values[2] = max_clk;
 773                         freq_values[1] = now;
 774                 }
 775
 776                 /*
 777                  * For DPM disabled case, there will be only one clock level.
 778                  * And it's safe to assume that is always the current clock.
 779                  */
 780                 if (display_levels == clocks.num_levels) {
 781                         for (i = 0; i < clocks.num_levels; i++)
 782                                 size += sprintf(
 783                                         buf + size, "%d: %uMhz %s\n", i,
 784                                         freq_values[i],
 785                                         (clocks.num_levels == 1) ?
 786                                                 "*" :
 787                                                 (aldebaran_freqs_in_same_level(
 788                                                          freq_values[i], now) ?
 789                                                          "*" :
 790                                                          ""));
 791                 } else {
 792                         for (i = 0; i < display_levels; i++)
 793                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i,
 794                                                 freq_values[i], i == 1 ? "*" : "");
 795                 }
 796
 797                 break;
 798
 799         case SMU_OD_MCLK:
 800                 size = sprintf(buf, "%s:\n", "MCLK");
 801                 fallthrough;
 802         case SMU_MCLK:
 803                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, &now);
 804                 if (ret) {
 805                         dev_err(smu->adev->dev, "Attempt to get current mclk Failed!");
 806                         return ret;
 807                 }
 808
 809                 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
 810                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 811                 if (ret) {
 812                         dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
 813                         return ret;
 814                 }
 815
 816                 for (i = 0; i < clocks.num_levels; i++)
 817                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 818                                         i, clocks.data[i].clocks_in_khz / 1000,
 819                                         (clocks.num_levels == 1) ? "*" :
 820                                         (aldebaran_freqs_in_same_level(
 821                                                                        clocks.data[i].clocks_in_khz / 1000,
 822                                                                        now) ? "*" : ""));
 823                 break;
 824
 825         case SMU_SOCCLK:
 826                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now);
 827                 if (ret) {
 828                         dev_err(smu->adev->dev, "Attempt to get current socclk Failed!");
 829                         return ret;
 830                 }
 831
 832                 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
 833                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 834                 if (ret) {
 835                         dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
 836                         return ret;
 837                 }
 838
 839                 for (i = 0; i < clocks.num_levels; i++)
 840                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 841                                         i, clocks.data[i].clocks_in_khz / 1000,
 842                                         (clocks.num_levels == 1) ? "*" :
 843                                         (aldebaran_freqs_in_same_level(
 844                                                                        clocks.data[i].clocks_in_khz / 1000,
 845                                                                        now) ? "*" : ""));
 846                 break;
 847
 848         case SMU_FCLK:
 849                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_FCLK, &now);
 850                 if (ret) {
 851                         dev_err(smu->adev->dev, "Attempt to get current fclk Failed!");
 852                         return ret;
 853                 }
 854
 855                 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
 856                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 857                 if (ret) {
 858                         dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
 859                         return ret;
 860                 }
 861
 862                 for (i = 0; i < single_dpm_table->count; i++)
 863                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 864                                         i, single_dpm_table->dpm_levels[i].value,
 865                                         (clocks.num_levels == 1) ? "*" :
 866                                         (aldebaran_freqs_in_same_level(
 867                                                                        clocks.data[i].clocks_in_khz / 1000,
 868                                                                        now) ? "*" : ""));
 869                 break;
 870
 871         case SMU_VCLK:
 872                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_VCLK, &now);
 873                 if (ret) {
 874                         dev_err(smu->adev->dev, "Attempt to get current vclk Failed!");
 875                         return ret;
 876                 }
 877
 878                 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
 879                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 880                 if (ret) {
 881                         dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!");
 882                         return ret;
 883                 }
 884
 885                 for (i = 0; i < single_dpm_table->count; i++)
 886                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 887                                         i, single_dpm_table->dpm_levels[i].value,
 888                                         (clocks.num_levels == 1) ? "*" :
 889                                         (aldebaran_freqs_in_same_level(
 890                                                                        clocks.data[i].clocks_in_khz / 1000,
 891                                                                        now) ? "*" : ""));
 892                 break;
 893
 894         case SMU_DCLK:
 895                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_DCLK, &now);
 896                 if (ret) {
 897                         dev_err(smu->adev->dev, "Attempt to get current dclk Failed!");
 898                         return ret;
 899                 }
 900
 901                 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
 902                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 903                 if (ret) {
 904                         dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!");
 905                         return ret;
 906                 }
 907
 908                 for (i = 0; i < single_dpm_table->count; i++)
 909                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 910                                         i, single_dpm_table->dpm_levels[i].value,
 911                                         (clocks.num_levels == 1) ? "*" :
 912                                         (aldebaran_freqs_in_same_level(
 913                                                                        clocks.data[i].clocks_in_khz / 1000,
 914                                                                        now) ? "*" : ""));
 915                 break;
 916
 917         default:
 918                 break;
 919         }
 920
 921         return size;
 922 }
 923
 924 static int aldebaran_upload_dpm_level(struct smu_context *smu,
 925                                       bool max,
 926                                       uint32_t feature_mask,
 927                                       uint32_t level)
 928 {
 929         struct smu_13_0_dpm_context *dpm_context =
 930                 smu->smu_dpm.dpm_context;
 931         uint32_t freq;
 932         int ret = 0;
 933
 934         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
 935             (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) {
 936                 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
 937                 ret = smu_cmn_send_smc_msg_with_param(smu,
 938                                                       (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 939                                                       (PPCLK_GFXCLK << 16) | (freq & 0xffff),
 940                                                       NULL);
 941                 if (ret) {
 942                         dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
 943                                 max ? "max" : "min");
 944                         return ret;
 945                 }
 946         }
 947
 948         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 949             (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) {
 950                 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
 951                 ret = smu_cmn_send_smc_msg_with_param(smu,
 952                                                       (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 953                                                       (PPCLK_UCLK << 16) | (freq & 0xffff),
 954                                                       NULL);
 955                 if (ret) {
 956                         dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
 957                                 max ? "max" : "min");
 958                         return ret;
 959                 }
 960         }
 961
 962         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
 963             (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) {
 964                 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
 965                 ret = smu_cmn_send_smc_msg_with_param(smu,
 966                                                       (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 967                                                       (PPCLK_SOCCLK << 16) | (freq & 0xffff),
 968                                                       NULL);
 969                 if (ret) {
 970                         dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
 971                                 max ? "max" : "min");
 972                         return ret;
 973                 }
 974         }
 975
 976         return ret;
 977 }
 978
 979 static int aldebaran_force_clk_levels(struct smu_context *smu,
 980                                       enum smu_clk_type type, uint32_t mask)
 981 {
 982         struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 983         struct smu_13_0_dpm_table *single_dpm_table = NULL;
 984         uint32_t soft_min_level, soft_max_level;
 985         int ret = 0;
 986
 987         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 988         soft_max_level = mask ? (fls(mask) - 1) : 0;
 989
 990         switch (type) {
 991         case SMU_SCLK:
 992                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 993                 if (soft_max_level >= single_dpm_table->count) {
 994                         dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
 995                                 soft_max_level, single_dpm_table->count - 1);
 996                         ret = -EINVAL;
 997                         break;
 998                 }
 999
1000                 ret = aldebaran_upload_dpm_level(smu,
1001                                                  false,
1002                                                  FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT),
1003                                                  soft_min_level);
1004                 if (ret) {
1005                         dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
1006                         break;
1007                 }
1008
1009                 ret = aldebaran_upload_dpm_level(smu,
1010                                                  true,
1011                                                  FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT),
1012                                                  soft_max_level);
1013                 if (ret)
1014                         dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
1015
1016                 break;
1017
1018         case SMU_MCLK:
1019         case SMU_SOCCLK:
1020         case SMU_FCLK:
1021                 /*
1022                  * Should not arrive here since aldebaran does not
1023                  * support mclk/socclk/fclk softmin/softmax settings
1024                  */
1025                 ret = -EINVAL;
1026                 break;
1027
1028         default:
1029                 break;
1030         }
1031
1032         return ret;
1033 }
1034
1035 static int aldebaran_get_thermal_temperature_range(struct smu_context *smu,
1036                                                    struct smu_temperature_range *range)
1037 {
1038         struct smu_table_context *table_context = &smu->smu_table;
1039         struct smu_13_0_powerplay_table *powerplay_table =
1040                 table_context->power_play_table;
1041         PPTable_t *pptable = smu->smu_table.driver_pptable;
1042
1043         if (!range)
1044                 return -EINVAL;
1045
1046         memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
1047
1048         range->hotspot_crit_max = pptable->ThotspotLimit *
1049                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1050         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1051                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1052         range->mem_crit_max = pptable->TmemLimit *
1053                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1054         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
1055                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1056         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1057
1058         return 0;
1059 }
1060
1061 static int aldebaran_get_current_activity_percent(struct smu_context *smu,
1062                                                   enum amd_pp_sensors sensor,
1063                                                   uint32_t *value)
1064 {
1065         int ret = 0;
1066
1067         if (!value)
1068                 return -EINVAL;
1069
1070         switch (sensor) {
1071         case AMDGPU_PP_SENSOR_GPU_LOAD:
1072                 ret = aldebaran_get_smu_metrics_data(smu,
1073                                                      METRICS_AVERAGE_GFXACTIVITY,
1074                                                      value);
1075                 break;
1076         case AMDGPU_PP_SENSOR_MEM_LOAD:
1077                 ret = aldebaran_get_smu_metrics_data(smu,
1078                                                      METRICS_AVERAGE_MEMACTIVITY,
1079                                                      value);
1080                 break;
1081         default:
1082                 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
1083                 return -EINVAL;
1084         }
1085
1086         return ret;
1087 }
1088
1089 static int aldebaran_get_gpu_power(struct smu_context *smu, uint32_t *value)
1090 {
1091         if (!value)
1092                 return -EINVAL;
1093
1094         return aldebaran_get_smu_metrics_data(smu,
1095                                               METRICS_AVERAGE_SOCKETPOWER,
1096                                               value);
1097 }
1098
1099 static int aldebaran_thermal_get_temperature(struct smu_context *smu,
1100                                              enum amd_pp_sensors sensor,
1101                                              uint32_t *value)
1102 {
1103         int ret = 0;
1104
1105         if (!value)
1106                 return -EINVAL;
1107
1108         switch (sensor) {
1109         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1110                 ret = aldebaran_get_smu_metrics_data(smu,
1111                                                      METRICS_TEMPERATURE_HOTSPOT,
1112                                                      value);
1113                 break;
1114         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1115                 ret = aldebaran_get_smu_metrics_data(smu,
1116                                                      METRICS_TEMPERATURE_EDGE,
1117                                                      value);
1118                 break;
1119         case AMDGPU_PP_SENSOR_MEM_TEMP:
1120                 ret = aldebaran_get_smu_metrics_data(smu,
1121                                                      METRICS_TEMPERATURE_MEM,
1122                                                      value);
1123                 break;
1124         default:
1125                 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1126                 return -EINVAL;
1127         }
1128
1129         return ret;
1130 }
1131
1132 static int aldebaran_read_sensor(struct smu_context *smu,
1133                                  enum amd_pp_sensors sensor,
1134                                  void *data, uint32_t *size)
1135 {
1136         int ret = 0;
1137
1138         if (amdgpu_ras_intr_triggered())
1139                 return 0;
1140
1141         if (!data || !size)
1142                 return -EINVAL;
1143
1144         mutex_lock(&smu->sensor_lock);
1145         switch (sensor) {
1146         case AMDGPU_PP_SENSOR_MEM_LOAD:
1147         case AMDGPU_PP_SENSOR_GPU_LOAD:
1148                 ret = aldebaran_get_current_activity_percent(smu,
1149                                                              sensor,
1150                                                              (uint32_t *)data);
1151                 *size = 4;
1152                 break;
1153         case AMDGPU_PP_SENSOR_GPU_POWER:
1154                 ret = aldebaran_get_gpu_power(smu, (uint32_t *)data);
1155                 *size = 4;
1156                 break;
1157         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1158         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1159         case AMDGPU_PP_SENSOR_MEM_TEMP:
1160                 ret = aldebaran_thermal_get_temperature(smu, sensor,
1161                                                         (uint32_t *)data);
1162                 *size = 4;
1163                 break;
1164         case AMDGPU_PP_SENSOR_GFX_MCLK:
1165                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1166                 /* the output clock frequency in 10K unit */
1167                 *(uint32_t *)data *= 100;
1168                 *size = 4;
1169                 break;
1170         case AMDGPU_PP_SENSOR_GFX_SCLK:
1171                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1172                 *(uint32_t *)data *= 100;
1173                 *size = 4;
1174                 break;
1175         case AMDGPU_PP_SENSOR_VDDGFX:
1176                 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data);
1177                 *size = 4;
1178                 break;
1179         default:
1180                 ret = -EOPNOTSUPP;
1181                 break;
1182         }
1183         mutex_unlock(&smu->sensor_lock);
1184
1185         return ret;
1186 }
1187
1188 static int aldebaran_get_power_limit(struct smu_context *smu,
1189                                      uint32_t *current_power_limit,
1190                                      uint32_t *default_power_limit,
1191                                      uint32_t *max_power_limit)
1192 {
1193         PPTable_t *pptable = smu->smu_table.driver_pptable;
1194         uint32_t power_limit = 0;
1195         int ret;
1196
1197         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
1198                 return -EINVAL;
1199
1200         /* Valid power data is available only from primary die.
1201          * For secondary die show the value as 0.
1202          */
1203         if (aldebaran_is_primary(smu)) {
1204                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit,
1205                                            &power_limit);
1206
1207                 if (ret) {
1208                         /* the last hope to figure out the ppt limit */
1209                         if (!pptable) {
1210                                 dev_err(smu->adev->dev,
1211                                         "Cannot get PPT limit due to pptable missing!");
1212                                 return -EINVAL;
1213                         }
1214                         power_limit = pptable->PptLimit;
1215                 }
1216         }
1217
1218         if (current_power_limit)
1219                 *current_power_limit = power_limit;
1220         if (default_power_limit)
1221                 *default_power_limit = power_limit;
1222
1223         if (max_power_limit) {
1224                 if (pptable)
1225                         *max_power_limit = pptable->PptLimit;
1226         }
1227
1228         return 0;
1229 }
1230
1231 static int aldebaran_set_power_limit(struct smu_context *smu, uint32_t n)
1232 {
1233         /* Power limit can be set only through primary die */
1234         if (aldebaran_is_primary(smu))
1235                 return smu_v13_0_set_power_limit(smu, n);
1236
1237         return -EINVAL;
1238 }
1239
1240 static int aldebaran_system_features_control(struct  smu_context *smu, bool enable)
1241 {
1242         int ret;
1243
1244         ret = smu_v13_0_system_features_control(smu, enable);
1245         if (!ret && enable)
1246                 ret = aldebaran_run_btc(smu);
1247
1248         return ret;
1249 }
1250
1251 static int aldebaran_set_performance_level(struct smu_context *smu,
1252                                            enum amd_dpm_forced_level level)
1253 {
1254         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1255         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1256         struct smu_13_0_dpm_table *gfx_table =
1257                 &dpm_context->dpm_tables.gfx_table;
1258         struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1259
1260         /* Disable determinism if switching to another mode */
1261         if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) &&
1262             (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) {
1263                 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL);
1264                 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1265         }
1266
1267         switch (level) {
1268
1269         case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM:
1270                 return 0;
1271
1272         case AMD_DPM_FORCED_LEVEL_HIGH:
1273         case AMD_DPM_FORCED_LEVEL_LOW:
1274         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1275         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1276         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1277         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1278         default:
1279                 break;
1280         }
1281
1282         return smu_v13_0_set_performance_level(smu, level);
1283 }
1284
1285 static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu,
1286                                           enum smu_clk_type clk_type,
1287                                           uint32_t min,
1288                                           uint32_t max)
1289 {
1290         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1291         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1292         struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1293         struct amdgpu_device *adev = smu->adev;
1294         uint32_t min_clk;
1295         uint32_t max_clk;
1296         int ret = 0;
1297
1298         if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK)
1299                 return -EINVAL;
1300
1301         if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1302                         && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1303                 return -EINVAL;
1304
1305         if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
1306                 if (min >= max) {
1307                         dev_err(smu->adev->dev,
1308                                 "Minimum GFX clk should be less than the maximum allowed clock\n");
1309                         return -EINVAL;
1310                 }
1311
1312                 if ((min == pstate_table->gfxclk_pstate.curr.min) &&
1313                     (max == pstate_table->gfxclk_pstate.curr.max))
1314                         return 0;
1315
1316                 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK,
1317                                                             min, max);
1318                 if (!ret) {
1319                         pstate_table->gfxclk_pstate.curr.min = min;
1320                         pstate_table->gfxclk_pstate.curr.max = max;
1321                 }
1322
1323                 return ret;
1324         }
1325
1326         if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1327                 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) ||
1328                         (max > dpm_context->dpm_tables.gfx_table.max)) {
1329                         dev_warn(adev->dev,
1330                                         "Invalid max frequency %d MHz specified for determinism\n", max);
1331                         return -EINVAL;
1332                 }
1333
1334                 /* Restore default min/max clocks and enable determinism */
1335                 min_clk = dpm_context->dpm_tables.gfx_table.min;
1336                 max_clk = dpm_context->dpm_tables.gfx_table.max;
1337                 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1338                 if (!ret) {
1339                         usleep_range(500, 1000);
1340                         ret = smu_cmn_send_smc_msg_with_param(smu,
1341                                         SMU_MSG_EnableDeterminism,
1342                                         max, NULL);
1343                         if (ret) {
1344                                 dev_err(adev->dev,
1345                                                 "Failed to enable determinism at GFX clock %d MHz\n", max);
1346                         } else {
1347                                 pstate_table->gfxclk_pstate.curr.min = min_clk;
1348                                 pstate_table->gfxclk_pstate.curr.max = max;
1349                         }
1350                 }
1351         }
1352
1353         return ret;
1354 }
1355
1356 static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
1357                                                         long input[], uint32_t size)
1358 {
1359         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1360         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1361         struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1362         uint32_t min_clk;
1363         uint32_t max_clk;
1364         int ret = 0;
1365
1366         /* Only allowed in manual or determinism mode */
1367         if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1368                         && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1369                 return -EINVAL;
1370
1371         switch (type) {
1372         case PP_OD_EDIT_SCLK_VDDC_TABLE:
1373                 if (size != 2) {
1374                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1375                         return -EINVAL;
1376                 }
1377
1378                 if (input[0] == 0) {
1379                         if (input[1] < dpm_context->dpm_tables.gfx_table.min) {
1380                                 dev_warn(smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n",
1381                                         input[1], dpm_context->dpm_tables.gfx_table.min);
1382                                 pstate_table->gfxclk_pstate.custom.min =
1383                                         pstate_table->gfxclk_pstate.curr.min;
1384                                 return -EINVAL;
1385                         }
1386
1387                         pstate_table->gfxclk_pstate.custom.min = input[1];
1388                 } else if (input[0] == 1) {
1389                         if (input[1] > dpm_context->dpm_tables.gfx_table.max) {
1390                                 dev_warn(smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
1391                                         input[1], dpm_context->dpm_tables.gfx_table.max);
1392                                 pstate_table->gfxclk_pstate.custom.max =
1393                                         pstate_table->gfxclk_pstate.curr.max;
1394                                 return -EINVAL;
1395                         }
1396
1397                         pstate_table->gfxclk_pstate.custom.max = input[1];
1398                 } else {
1399                         return -EINVAL;
1400                 }
1401                 break;
1402         case PP_OD_RESTORE_DEFAULT_TABLE:
1403                 if (size != 0) {
1404                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1405                         return -EINVAL;
1406                 } else {
1407                         /* Use the default frequencies for manual and determinism mode */
1408                         min_clk = dpm_context->dpm_tables.gfx_table.min;
1409                         max_clk = dpm_context->dpm_tables.gfx_table.max;
1410
1411                         return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1412                 }
1413                 break;
1414         case PP_OD_COMMIT_DPM_TABLE:
1415                 if (size != 0) {
1416                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1417                         return -EINVAL;
1418                 } else {
1419                         if (!pstate_table->gfxclk_pstate.custom.min)
1420                                 pstate_table->gfxclk_pstate.custom.min =
1421                                         pstate_table->gfxclk_pstate.curr.min;
1422
1423                         if (!pstate_table->gfxclk_pstate.custom.max)
1424                                 pstate_table->gfxclk_pstate.custom.max =
1425                                         pstate_table->gfxclk_pstate.curr.max;
1426
1427                         min_clk = pstate_table->gfxclk_pstate.custom.min;
1428                         max_clk = pstate_table->gfxclk_pstate.custom.max;
1429
1430                         return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1431                 }
1432                 break;
1433         default:
1434                 return -ENOSYS;
1435         }
1436
1437         return ret;
1438 }
1439
1440 static bool aldebaran_is_dpm_running(struct smu_context *smu)
1441 {
1442         int ret;
1443         uint32_t feature_mask[2];
1444         unsigned long feature_enabled;
1445
1446         ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1447         if (ret)
1448                 return false;
1449         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1450                                           ((uint64_t)feature_mask[1] << 32));
1451         return !!(feature_enabled & SMC_DPM_FEATURE);
1452 }
1453
1454 static void aldebaran_fill_i2c_req(SwI2cRequest_t  *req, bool write,
1455                                   uint8_t address, uint32_t numbytes,
1456                                   uint8_t *data)
1457 {
1458         int i;
1459
1460         req->I2CcontrollerPort = 0;
1461         req->I2CSpeed = 2;
1462         req->SlaveAddress = address;
1463         req->NumCmds = numbytes;
1464
1465         for (i = 0; i < numbytes; i++) {
1466                 SwI2cCmd_t *cmd =  &req->SwI2cCmds[i];
1467
1468                 /* First 2 bytes are always write for lower 2b EEPROM address */
1469                 if (i < 2)
1470                         cmd->CmdConfig = CMDCONFIG_READWRITE_MASK;
1471                 else
1472                         cmd->CmdConfig = write ? CMDCONFIG_READWRITE_MASK : 0;
1473
1474
1475                 /* Add RESTART for read  after address filled */
1476                 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
1477
1478                 /* Add STOP in the end */
1479                 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
1480
1481                 /* Fill with data regardless if read or write to simplify code */
1482                 cmd->ReadWriteData = data[i];
1483         }
1484 }
1485
1486 static int aldebaran_i2c_read_data(struct i2c_adapter *control,
1487                                                uint8_t address,
1488                                                uint8_t *data,
1489                                                uint32_t numbytes)
1490 {
1491         uint32_t  i, ret = 0;
1492         SwI2cRequest_t req;
1493         struct amdgpu_device *adev = to_amdgpu_device(control);
1494         struct smu_table_context *smu_table = &adev->smu.smu_table;
1495         struct smu_table *table = &smu_table->driver_table;
1496
1497         if (numbytes > MAX_SW_I2C_COMMANDS) {
1498                 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
1499                         numbytes, MAX_SW_I2C_COMMANDS);
1500                 return -EINVAL;
1501         }
1502
1503         memset(&req, 0, sizeof(req));
1504         aldebaran_fill_i2c_req(&req, false, address, numbytes, data);
1505
1506         mutex_lock(&adev->smu.mutex);
1507         /* Now read data starting with that address */
1508         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
1509                                         true);
1510         mutex_unlock(&adev->smu.mutex);
1511
1512         if (!ret) {
1513                 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
1514
1515                 /* Assume SMU  fills res.SwI2cCmds[i].Data with read bytes */
1516                 for (i = 0; i < numbytes; i++)
1517                         data[i] = res->SwI2cCmds[i].ReadWriteData;
1518
1519                 dev_dbg(adev->dev, "aldebaran_i2c_read_data, address = %x, bytes = %d, data :",
1520                                   (uint16_t)address, numbytes);
1521
1522                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
1523                                8, 1, data, numbytes, false);
1524         } else
1525                 dev_err(adev->dev, "aldebaran_i2c_read_data - error occurred :%x", ret);
1526
1527         return ret;
1528 }
1529
1530 static int aldebaran_i2c_write_data(struct i2c_adapter *control,
1531                                                 uint8_t address,
1532                                                 uint8_t *data,
1533                                                 uint32_t numbytes)
1534 {
1535         uint32_t ret;
1536         SwI2cRequest_t req;
1537         struct amdgpu_device *adev = to_amdgpu_device(control);
1538
1539         if (numbytes > MAX_SW_I2C_COMMANDS) {
1540                 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
1541                         numbytes, MAX_SW_I2C_COMMANDS);
1542                 return -EINVAL;
1543         }
1544
1545         memset(&req, 0, sizeof(req));
1546         aldebaran_fill_i2c_req(&req, true, address, numbytes, data);
1547
1548         mutex_lock(&adev->smu.mutex);
1549         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
1550         mutex_unlock(&adev->smu.mutex);
1551
1552         if (!ret) {
1553                 dev_dbg(adev->dev, "aldebaran_i2c_write(), address = %x, bytes = %d , data: ",
1554                                          (uint16_t)address, numbytes);
1555
1556                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
1557                                8, 1, data, numbytes, false);
1558                 /*
1559                  * According to EEPROM spec there is a MAX of 10 ms required for
1560                  * EEPROM to flush internal RX buffer after STOP was issued at the
1561                  * end of write transaction. During this time the EEPROM will not be
1562                  * responsive to any more commands - so wait a bit more.
1563                  */
1564                 msleep(10);
1565
1566         } else
1567                 dev_err(adev->dev, "aldebaran_i2c_write- error occurred :%x", ret);
1568
1569         return ret;
1570 }
1571
1572 static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap,
1573                               struct i2c_msg *msgs, int num)
1574 {
1575         uint32_t  i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
1576         uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
1577
1578         for (i = 0; i < num; i++) {
1579                 /*
1580                  * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
1581                  * once and hence the data needs to be spliced into chunks and sent each
1582                  * chunk separately
1583                  */
1584                 data_size = msgs[i].len - 2;
1585                 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
1586                 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
1587                 data_ptr = msgs[i].buf + 2;
1588
1589                 for (j = 0; j < data_size / data_chunk_size; j++) {
1590                         /* Insert the EEPROM dest addess, bits 0-15 */
1591                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
1592                         data_chunk[1] = (next_eeprom_addr & 0xff);
1593
1594                         if (msgs[i].flags & I2C_M_RD) {
1595                                 ret = aldebaran_i2c_read_data(i2c_adap,
1596                                                              (uint8_t)msgs[i].addr,
1597                                                              data_chunk, MAX_SW_I2C_COMMANDS);
1598
1599                                 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
1600                         } else {
1601
1602                                 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
1603
1604                                 ret = aldebaran_i2c_write_data(i2c_adap,
1605                                                               (uint8_t)msgs[i].addr,
1606                                                               data_chunk, MAX_SW_I2C_COMMANDS);
1607                         }
1608
1609                         if (ret) {
1610                                 num = -EIO;
1611                                 goto fail;
1612                         }
1613
1614                         next_eeprom_addr += data_chunk_size;
1615                         data_ptr += data_chunk_size;
1616                 }
1617
1618                 if (data_size % data_chunk_size) {
1619                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
1620                         data_chunk[1] = (next_eeprom_addr & 0xff);
1621
1622                         if (msgs[i].flags & I2C_M_RD) {
1623                                 ret = aldebaran_i2c_read_data(i2c_adap,
1624                                                              (uint8_t)msgs[i].addr,
1625                                                              data_chunk, (data_size % data_chunk_size) + 2);
1626
1627                                 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
1628                         } else {
1629                                 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
1630
1631                                 ret = aldebaran_i2c_write_data(i2c_adap,
1632                                                               (uint8_t)msgs[i].addr,
1633                                                               data_chunk, (data_size % data_chunk_size) + 2);
1634                         }
1635
1636                         if (ret) {
1637                                 num = -EIO;
1638                                 goto fail;
1639                         }
1640                 }
1641         }
1642
1643 fail:
1644         return num;
1645 }
1646
1647 static u32 aldebaran_i2c_func(struct i2c_adapter *adap)
1648 {
1649         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1650 }
1651
1652
1653 static const struct i2c_algorithm aldebaran_i2c_algo = {
1654         .master_xfer = aldebaran_i2c_xfer,
1655         .functionality = aldebaran_i2c_func,
1656 };
1657
1658 static int aldebaran_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
1659 {
1660         struct amdgpu_device *adev = to_amdgpu_device(control);
1661         int res;
1662
1663         control->owner = THIS_MODULE;
1664         control->class = I2C_CLASS_SPD;
1665         control->dev.parent = &adev->pdev->dev;
1666         control->algo = &aldebaran_i2c_algo;
1667         snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
1668
1669         res = i2c_add_adapter(control);
1670         if (res)
1671                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
1672
1673         return res;
1674 }
1675
1676 static void aldebaran_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
1677 {
1678         i2c_del_adapter(control);
1679 }
1680
1681 static void aldebaran_get_unique_id(struct smu_context *smu)
1682 {
1683         struct amdgpu_device *adev = smu->adev;
1684         SmuMetrics_t *metrics = smu->smu_table.metrics_table;
1685         uint32_t upper32 = 0, lower32 = 0;
1686         int ret;
1687
1688         mutex_lock(&smu->metrics_lock);
1689         ret = smu_cmn_get_metrics_table_locked(smu, NULL, false);
1690         if (ret)
1691                 goto out_unlock;
1692
1693         upper32 = metrics->PublicSerialNumUpper32;
1694         lower32 = metrics->PublicSerialNumLower32;
1695
1696 out_unlock:
1697         mutex_unlock(&smu->metrics_lock);
1698
1699         adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1700         sprintf(adev->serial, "%016llx", adev->unique_id);
1701 }
1702
1703 static bool aldebaran_is_baco_supported(struct smu_context *smu)
1704 {
1705         /* aldebaran is not support baco */
1706
1707         return false;
1708 }
1709
1710 static int aldebaran_set_df_cstate(struct smu_context *smu,
1711                                    enum pp_df_cstate state)
1712 {
1713         return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
1714 }
1715
1716 static int aldebaran_allow_xgmi_power_down(struct smu_context *smu, bool en)
1717 {
1718         return smu_cmn_send_smc_msg_with_param(smu,
1719                                                SMU_MSG_GmiPwrDnControl,
1720                                                en ? 1 : 0,
1721                                                NULL);
1722 }
1723
1724 static const struct throttling_logging_label {
1725         uint32_t feature_mask;
1726         const char *label;
1727 } logging_label[] = {
1728         {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
1729         {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
1730         {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
1731         {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
1732 };
1733 static void aldebaran_log_thermal_throttling_event(struct smu_context *smu)
1734 {
1735         int ret;
1736         int throttler_idx, throtting_events = 0, buf_idx = 0;
1737         struct amdgpu_device *adev = smu->adev;
1738         uint32_t throttler_status;
1739         char log_buf[256];
1740
1741         ret = aldebaran_get_smu_metrics_data(smu,
1742                                              METRICS_THROTTLER_STATUS,
1743                                              &throttler_status);
1744         if (ret)
1745                 return;
1746
1747         memset(log_buf, 0, sizeof(log_buf));
1748         for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
1749              throttler_idx++) {
1750                 if (throttler_status & logging_label[throttler_idx].feature_mask) {
1751                         throtting_events++;
1752                         buf_idx += snprintf(log_buf + buf_idx,
1753                                             sizeof(log_buf) - buf_idx,
1754                                             "%s%s",
1755                                             throtting_events > 1 ? " and " : "",
1756                                             logging_label[throttler_idx].label);
1757                         if (buf_idx >= sizeof(log_buf)) {
1758                                 dev_err(adev->dev, "buffer overflow!\n");
1759                                 log_buf[sizeof(log_buf) - 1] = '\0';
1760                                 break;
1761                         }
1762                 }
1763         }
1764
1765         dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
1766                  log_buf);
1767         kgd2kfd_smi_event_throttle(smu->adev->kfd.dev, throttler_status);
1768 }
1769
1770 static int aldebaran_get_current_pcie_link_speed(struct smu_context *smu)
1771 {
1772         struct amdgpu_device *adev = smu->adev;
1773         uint32_t esm_ctrl;
1774
1775         /* TODO: confirm this on real target */
1776         esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
1777         if ((esm_ctrl >> 15) & 0x1FFFF)
1778                 return (((esm_ctrl >> 8) & 0x3F) + 128);
1779
1780         return smu_v13_0_get_current_pcie_link_speed(smu);
1781 }
1782
1783 static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu,
1784                                          void **table)
1785 {
1786         struct smu_table_context *smu_table = &smu->smu_table;
1787         struct gpu_metrics_v1_3 *gpu_metrics =
1788                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
1789         SmuMetrics_t metrics;
1790         int i, ret = 0;
1791
1792         ret = smu_cmn_get_metrics_table(smu,
1793                                         &metrics,
1794                                         true);
1795         if (ret)
1796                 return ret;
1797
1798         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
1799
1800         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
1801         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
1802         gpu_metrics->temperature_mem = metrics.TemperatureHBM;
1803         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
1804         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
1805         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
1806
1807         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
1808         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
1809         gpu_metrics->average_mm_activity = 0;
1810
1811         /* Valid power data is available only from primary die */
1812         if (aldebaran_is_primary(smu)) {
1813                 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
1814                 gpu_metrics->energy_accumulator =
1815                         (uint64_t)metrics.EnergyAcc64bitHigh << 32 |
1816                         metrics.EnergyAcc64bitLow;
1817         } else {
1818                 gpu_metrics->average_socket_power = 0;
1819                 gpu_metrics->energy_accumulator = 0;
1820         }
1821
1822         gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
1823         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
1824         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
1825         gpu_metrics->average_vclk0_frequency = 0;
1826         gpu_metrics->average_dclk0_frequency = 0;
1827
1828         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
1829         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
1830         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
1831         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
1832         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
1833
1834         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1835         gpu_metrics->indep_throttle_status =
1836                         smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1837                                                            aldebaran_throttler_map);
1838
1839         gpu_metrics->current_fan_speed = 0;
1840
1841         gpu_metrics->pcie_link_width =
1842                 smu_v13_0_get_current_pcie_link_width(smu);
1843         gpu_metrics->pcie_link_speed =
1844                 aldebaran_get_current_pcie_link_speed(smu);
1845
1846         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1847
1848         gpu_metrics->gfx_activity_acc = metrics.GfxBusyAcc;
1849         gpu_metrics->mem_activity_acc = metrics.DramBusyAcc;
1850
1851         for (i = 0; i < NUM_HBM_INSTANCES; i++)
1852                 gpu_metrics->temperature_hbm[i] = metrics.TemperatureAllHBM[i];
1853
1854         gpu_metrics->firmware_timestamp = ((uint64_t)metrics.TimeStampHigh << 32) |
1855                                         metrics.TimeStampLow;
1856
1857         *table = (void *)gpu_metrics;
1858
1859         return sizeof(struct gpu_metrics_v1_3);
1860 }
1861
1862 static int aldebaran_mode2_reset(struct smu_context *smu)
1863 {
1864         u32 smu_version;
1865         int ret = 0, index;
1866         struct amdgpu_device *adev = smu->adev;
1867         int timeout = 10;
1868
1869         smu_cmn_get_smc_version(smu, NULL, &smu_version);
1870
1871         index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
1872                                                 SMU_MSG_GfxDeviceDriverReset);
1873
1874         mutex_lock(&smu->message_lock);
1875         if (smu_version >= 0x00441400) {
1876                 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2);
1877                 /* This is similar to FLR, wait till max FLR timeout */
1878                 msleep(100);
1879                 dev_dbg(smu->adev->dev, "restore config space...\n");
1880                 /* Restore the config space saved during init */
1881                 amdgpu_device_load_pci_state(adev->pdev);
1882
1883                 dev_dbg(smu->adev->dev, "wait for reset ack\n");
1884                 while (ret == -ETIME && timeout)  {
1885                         ret = smu_cmn_wait_for_response(smu);
1886                         /* Wait a bit more time for getting ACK */
1887                         if (ret == -ETIME) {
1888                                 --timeout;
1889                                 usleep_range(500, 1000);
1890                                 continue;
1891                         }
1892
1893                         if (ret != 1) {
1894                                 dev_err(adev->dev, "failed to send mode2 message \tparam: 0x%08x response %#x\n",
1895                                                 SMU_RESET_MODE_2, ret);
1896                                 goto out;
1897                         }
1898                 }
1899
1900         } else {
1901                 dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n",
1902                                 smu_version);
1903         }
1904
1905         if (ret == 1)
1906                 ret = 0;
1907 out:
1908         mutex_unlock(&smu->message_lock);
1909
1910         return ret;
1911 }
1912
1913 static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu)
1914 {
1915 #if 0
1916         struct amdgpu_device *adev = smu->adev;
1917         u32 smu_version;
1918         uint32_t val;
1919         /**
1920          * PM FW version support mode1 reset from 68.07
1921          */
1922         smu_cmn_get_smc_version(smu, NULL, &smu_version);
1923         if ((smu_version < 0x00440700))
1924                 return false;
1925         /**
1926          * mode1 reset relies on PSP, so we should check if
1927          * PSP is alive.
1928          */
1929         val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
1930
1931         return val != 0x0;
1932 #endif
1933         return true;
1934 }
1935
1936 static bool aldebaran_is_mode2_reset_supported(struct smu_context *smu)
1937 {
1938         return true;
1939 }
1940
1941 static int aldebaran_set_mp1_state(struct smu_context *smu,
1942                                    enum pp_mp1_state mp1_state)
1943 {
1944         switch (mp1_state) {
1945         case PP_MP1_STATE_UNLOAD:
1946                 return smu_cmn_set_mp1_state(smu, mp1_state);
1947         default:
1948                 return 0;
1949         }
1950 }
1951
1952 static int aldebaran_smu_send_hbm_bad_page_num(struct smu_context *smu,
1953                 uint32_t size)
1954 {
1955         int ret = 0;
1956
1957         /* message SMU to update the bad page number on SMUBUS */
1958         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL);
1959         if (ret)
1960                 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad pages number\n",
1961                                 __func__);
1962
1963         return ret;
1964 }
1965
1966 static const struct pptable_funcs aldebaran_ppt_funcs = {
1967         /* init dpm */
1968         .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask,
1969         /* dpm/clk tables */
1970         .set_default_dpm_table = aldebaran_set_default_dpm_table,
1971         .populate_umd_state_clk = aldebaran_populate_umd_state_clk,
1972         .get_thermal_temperature_range = aldebaran_get_thermal_temperature_range,
1973         .print_clk_levels = aldebaran_print_clk_levels,
1974         .force_clk_levels = aldebaran_force_clk_levels,
1975         .read_sensor = aldebaran_read_sensor,
1976         .set_performance_level = aldebaran_set_performance_level,
1977         .get_power_limit = aldebaran_get_power_limit,
1978         .is_dpm_running = aldebaran_is_dpm_running,
1979         .get_unique_id = aldebaran_get_unique_id,
1980         .init_microcode = smu_v13_0_init_microcode,
1981         .load_microcode = smu_v13_0_load_microcode,
1982         .fini_microcode = smu_v13_0_fini_microcode,
1983         .init_smc_tables = aldebaran_init_smc_tables,
1984         .fini_smc_tables = smu_v13_0_fini_smc_tables,
1985         .init_power = smu_v13_0_init_power,
1986         .fini_power = smu_v13_0_fini_power,
1987         .check_fw_status = smu_v13_0_check_fw_status,
1988         /* pptable related */
1989         .setup_pptable = aldebaran_setup_pptable,
1990         .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
1991         .check_fw_version = smu_v13_0_check_fw_version,
1992         .write_pptable = smu_cmn_write_pptable,
1993         .set_driver_table_location = smu_v13_0_set_driver_table_location,
1994         .set_tool_table_location = smu_v13_0_set_tool_table_location,
1995         .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
1996         .system_features_control = aldebaran_system_features_control,
1997         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1998         .send_smc_msg = smu_cmn_send_smc_msg,
1999         .get_enabled_mask = smu_cmn_get_enabled_mask,
2000         .feature_is_enabled = smu_cmn_feature_is_enabled,
2001         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2002         .set_power_limit = aldebaran_set_power_limit,
2003         .init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks,
2004         .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
2005         .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
2006         .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate,
2007         .register_irq_handler = smu_v13_0_register_irq_handler,
2008         .set_azalia_d3_pme = smu_v13_0_set_azalia_d3_pme,
2009         .get_max_sustainable_clocks_by_dc = smu_v13_0_get_max_sustainable_clocks_by_dc,
2010         .baco_is_support= aldebaran_is_baco_supported,
2011         .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq,
2012         .set_soft_freq_limited_range = aldebaran_set_soft_freq_limited_range,
2013         .od_edit_dpm_table = aldebaran_usr_edit_dpm_table,
2014         .set_df_cstate = aldebaran_set_df_cstate,
2015         .allow_xgmi_power_down = aldebaran_allow_xgmi_power_down,
2016         .log_thermal_throttling_event = aldebaran_log_thermal_throttling_event,
2017         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2018         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2019         .get_gpu_metrics = aldebaran_get_gpu_metrics,
2020         .mode1_reset_is_support = aldebaran_is_mode1_reset_supported,
2021         .mode2_reset_is_support = aldebaran_is_mode2_reset_supported,
2022         .mode1_reset = smu_v13_0_mode1_reset,
2023         .set_mp1_state = aldebaran_set_mp1_state,
2024         .mode2_reset = aldebaran_mode2_reset,
2025         .wait_for_event = smu_v13_0_wait_for_event,
2026         .i2c_init = aldebaran_i2c_control_init,
2027         .i2c_fini = aldebaran_i2c_control_fini,
2028         .send_hbm_bad_pages_num = aldebaran_smu_send_hbm_bad_page_num,
2029 };
2030
2031 void aldebaran_set_ppt_funcs(struct smu_context *smu)
2032 {
2033         smu->ppt_funcs = &aldebaran_ppt_funcs;
2034         smu->message_map = aldebaran_message_map;
2035         smu->clock_map = aldebaran_clk_map;
2036         smu->feature_map = aldebaran_feature_mask_map;
2037         smu->table_map = aldebaran_table_map;
2038 }