drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_smu.h"
  29 #include "atomfirmware.h"
  30 #include "amdgpu_atomfirmware.h"
  31 #include "amdgpu_atombios.h"
  32 #include "smu_v13_0.h"
  33 #include "smu13_driver_if_aldebaran.h"
  34 #include "soc15_common.h"
  35 #include "atom.h"
  36 #include "power_state.h"
  37 #include "aldebaran_ppt.h"
  38 #include "smu_v13_0_pptable.h"
  39 #include "aldebaran_ppsmc.h"
  40 #include "nbio/nbio_7_4_offset.h"
  41 #include "nbio/nbio_7_4_sh_mask.h"
  42 #include "thm/thm_11_0_2_offset.h"
  43 #include "thm/thm_11_0_2_sh_mask.h"
  44 #include "amdgpu_xgmi.h"
  45 #include <linux/pci.h>
  46 #include "amdgpu_ras.h"
  47 #include "smu_cmn.h"
  48 #include "mp/mp_13_0_2_offset.h"
  49
  50 /*
  51  * DO NOT use these for err/warn/info/debug messages.
  52  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  53  * They are more MGPU friendly.
  54  */
  55 #undef pr_err
  56 #undef pr_warn
  57 #undef pr_info
  58 #undef pr_debug
  59
  60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  61
  62 #define ALDEBARAN_FEA_MAP(smu_feature, aldebaran_feature) \
  63         [smu_feature] = {1, (aldebaran_feature)}
  64
  65 #define FEATURE_MASK(feature) (1ULL << feature)
  66 #define SMC_DPM_FEATURE ( \
  67                           FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \
  68                           FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)  | \
  69                           FEATURE_MASK(FEATURE_DPM_UCLK_BIT)    | \
  70                           FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)  | \
  71                           FEATURE_MASK(FEATURE_DPM_FCLK_BIT)    | \
  72                           FEATURE_MASK(FEATURE_DPM_LCLK_BIT)    | \
  73                           FEATURE_MASK(FEATURE_DPM_XGMI_BIT)    | \
  74                           FEATURE_MASK(FEATURE_DPM_VCN_BIT))
  75
  76 /* possible frequency drift (1Mhz) */
  77 #define EPSILON                         1
  78
  79 #define smnPCIE_ESM_CTRL                        0x111003D0
  80
  81 static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = {
  82         MSG_MAP(TestMessage,                         PPSMC_MSG_TestMessage,                     0),
  83         MSG_MAP(GetSmuVersion,                       PPSMC_MSG_GetSmuVersion,                   1),
  84         MSG_MAP(GetDriverIfVersion,                  PPSMC_MSG_GetDriverIfVersion,              1),
  85         MSG_MAP(EnableAllSmuFeatures,                PPSMC_MSG_EnableAllSmuFeatures,            0),
  86         MSG_MAP(DisableAllSmuFeatures,               PPSMC_MSG_DisableAllSmuFeatures,           0),
  87         MSG_MAP(GetEnabledSmuFeaturesLow,            PPSMC_MSG_GetEnabledSmuFeaturesLow,        0),
  88         MSG_MAP(GetEnabledSmuFeaturesHigh,           PPSMC_MSG_GetEnabledSmuFeaturesHigh,       0),
  89         MSG_MAP(SetDriverDramAddrHigh,               PPSMC_MSG_SetDriverDramAddrHigh,           1),
  90         MSG_MAP(SetDriverDramAddrLow,                PPSMC_MSG_SetDriverDramAddrLow,            1),
  91         MSG_MAP(SetToolsDramAddrHigh,                PPSMC_MSG_SetToolsDramAddrHigh,            0),
  92         MSG_MAP(SetToolsDramAddrLow,                 PPSMC_MSG_SetToolsDramAddrLow,             0),
  93         MSG_MAP(TransferTableSmu2Dram,               PPSMC_MSG_TransferTableSmu2Dram,           1),
  94         MSG_MAP(TransferTableDram2Smu,               PPSMC_MSG_TransferTableDram2Smu,           0),
  95         MSG_MAP(UseDefaultPPTable,                   PPSMC_MSG_UseDefaultPPTable,               0),
  96         MSG_MAP(SetSystemVirtualDramAddrHigh,        PPSMC_MSG_SetSystemVirtualDramAddrHigh,    0),
  97         MSG_MAP(SetSystemVirtualDramAddrLow,         PPSMC_MSG_SetSystemVirtualDramAddrLow,     0),
  98         MSG_MAP(SetSoftMinByFreq,                    PPSMC_MSG_SetSoftMinByFreq,                0),
  99         MSG_MAP(SetSoftMaxByFreq,                    PPSMC_MSG_SetSoftMaxByFreq,                0),
 100         MSG_MAP(SetHardMinByFreq,                    PPSMC_MSG_SetHardMinByFreq,                0),
 101         MSG_MAP(SetHardMaxByFreq,                    PPSMC_MSG_SetHardMaxByFreq,                0),
 102         MSG_MAP(GetMinDpmFreq,                       PPSMC_MSG_GetMinDpmFreq,                   0),
 103         MSG_MAP(GetMaxDpmFreq,                       PPSMC_MSG_GetMaxDpmFreq,                   0),
 104         MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex,               1),
 105         MSG_MAP(SetWorkloadMask,                     PPSMC_MSG_SetWorkloadMask,                 1),
 106         MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm,                 0),
 107         MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive,        0),
 108         MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit,                     0),
 109         MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit,                     1),
 110         MSG_MAP(PrepareMp1ForUnload,                 PPSMC_MSG_PrepareMp1ForUnload,             0),
 111         MSG_MAP(GfxDeviceDriverReset,                PPSMC_MSG_GfxDriverReset,                  0),
 112         MSG_MAP(RunDcBtc,                            PPSMC_MSG_RunDcBtc,                        0),
 113         MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh,          0),
 114         MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow,           0),
 115         MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize,              0),
 116         MSG_MAP(GetDebugData,                        PPSMC_MSG_GetDebugData,                    0),
 117         MSG_MAP(WaflTest,                            PPSMC_MSG_WaflTest,                        0),
 118         MSG_MAP(SetMemoryChannelEnable,              PPSMC_MSG_SetMemoryChannelEnable,          0),
 119         MSG_MAP(SetNumBadHbmPagesRetired,            PPSMC_MSG_SetNumBadHbmPagesRetired,        0),
 120         MSG_MAP(DFCstateControl,                     PPSMC_MSG_DFCstateControl,                 0),
 121         MSG_MAP(GetGmiPwrDnHyst,                     PPSMC_MSG_GetGmiPwrDnHyst,                 0),
 122         MSG_MAP(SetGmiPwrDnHyst,                     PPSMC_MSG_SetGmiPwrDnHyst,                 0),
 123         MSG_MAP(GmiPwrDnControl,                     PPSMC_MSG_GmiPwrDnControl,                 0),
 124         MSG_MAP(EnterGfxoff,                         PPSMC_MSG_EnterGfxoff,                     0),
 125         MSG_MAP(ExitGfxoff,                          PPSMC_MSG_ExitGfxoff,                      0),
 126         MSG_MAP(SetExecuteDMATest,                   PPSMC_MSG_SetExecuteDMATest,               0),
 127         MSG_MAP(EnableDeterminism,                   PPSMC_MSG_EnableDeterminism,               0),
 128         MSG_MAP(DisableDeterminism,                  PPSMC_MSG_DisableDeterminism,              0),
 129         MSG_MAP(SetUclkDpmMode,                      PPSMC_MSG_SetUclkDpmMode,                  0),
 130         MSG_MAP(GfxDriverResetRecovery,              PPSMC_MSG_GfxDriverResetRecovery,          0),
 131 };
 132
 133 static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = {
 134         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 135         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 136         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 137         CLK_MAP(FCLK, PPCLK_FCLK),
 138         CLK_MAP(UCLK, PPCLK_UCLK),
 139         CLK_MAP(MCLK, PPCLK_UCLK),
 140         CLK_MAP(DCLK, PPCLK_DCLK),
 141         CLK_MAP(VCLK, PPCLK_VCLK),
 142         CLK_MAP(LCLK,   PPCLK_LCLK),
 143 };
 144
 145 static const struct cmn2asic_mapping aldebaran_feature_mask_map[SMU_FEATURE_COUNT] = {
 146         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_PREFETCHER_BIT,               FEATURE_DATA_CALCULATIONS),
 147         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT,                   FEATURE_DPM_GFXCLK_BIT),
 148         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT,                     FEATURE_DPM_UCLK_BIT),
 149         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT,                   FEATURE_DPM_SOCCLK_BIT),
 150         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT,                     FEATURE_DPM_FCLK_BIT),
 151         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT,                     FEATURE_DPM_LCLK_BIT),
 152         ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_BIT,                                 FEATURE_DPM_XGMI_BIT),
 153         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT,                    FEATURE_DS_GFXCLK_BIT),
 154         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT,                    FEATURE_DS_SOCCLK_BIT),
 155         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT,                              FEATURE_DS_LCLK_BIT),
 156         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT,                              FEATURE_DS_FCLK_BIT),
 157         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_UCLK_BIT,                              FEATURE_DS_UCLK_BIT),
 158         ALDEBARAN_FEA_MAP(SMU_FEATURE_GFX_SS_BIT,                               FEATURE_GFX_SS_BIT),
 159         ALDEBARAN_FEA_MAP(SMU_FEATURE_VCN_PG_BIT,                               FEATURE_DPM_VCN_BIT),
 160         ALDEBARAN_FEA_MAP(SMU_FEATURE_RSMU_SMN_CG_BIT,                  FEATURE_RSMU_SMN_CG_BIT),
 161         ALDEBARAN_FEA_MAP(SMU_FEATURE_WAFL_CG_BIT,                              FEATURE_WAFL_CG_BIT),
 162         ALDEBARAN_FEA_MAP(SMU_FEATURE_PPT_BIT,                                  FEATURE_PPT_BIT),
 163         ALDEBARAN_FEA_MAP(SMU_FEATURE_TDC_BIT,                                  FEATURE_TDC_BIT),
 164         ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_PLUS_BIT,                    FEATURE_APCC_PLUS_BIT),
 165         ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT,                    FEATURE_APCC_DFLL_BIT),
 166         ALDEBARAN_FEA_MAP(SMU_FEATURE_FUSE_CG_BIT,                              FEATURE_FUSE_CG_BIT),
 167         ALDEBARAN_FEA_MAP(SMU_FEATURE_MP1_CG_BIT,                               FEATURE_MP1_CG_BIT),
 168         ALDEBARAN_FEA_MAP(SMU_FEATURE_SMUIO_CG_BIT,                     FEATURE_SMUIO_CG_BIT),
 169         ALDEBARAN_FEA_MAP(SMU_FEATURE_THM_CG_BIT,                               FEATURE_THM_CG_BIT),
 170         ALDEBARAN_FEA_MAP(SMU_FEATURE_CLK_CG_BIT,                               FEATURE_CLK_CG_BIT),
 171         ALDEBARAN_FEA_MAP(SMU_FEATURE_FW_CTF_BIT,                               FEATURE_FW_CTF_BIT),
 172         ALDEBARAN_FEA_MAP(SMU_FEATURE_THERMAL_BIT,                              FEATURE_THERMAL_BIT),
 173         ALDEBARAN_FEA_MAP(SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT,  FEATURE_OUT_OF_BAND_MONITOR_BIT),
 174         ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT,FEATURE_XGMI_PER_LINK_PWR_DWN),
 175         ALDEBARAN_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT,                    FEATURE_DF_CSTATE),
 176 };
 177
 178 static const struct cmn2asic_mapping aldebaran_table_map[SMU_TABLE_COUNT] = {
 179         TAB_MAP(PPTABLE),
 180         TAB_MAP(AVFS_PSM_DEBUG),
 181         TAB_MAP(AVFS_FUSE_OVERRIDE),
 182         TAB_MAP(PMSTATUSLOG),
 183         TAB_MAP(SMU_METRICS),
 184         TAB_MAP(DRIVER_SMU_CONFIG),
 185         TAB_MAP(I2C_COMMANDS),
 186 };
 187
 188 static int aldebaran_tables_init(struct smu_context *smu)
 189 {
 190         struct smu_table_context *smu_table = &smu->smu_table;
 191         struct smu_table *tables = smu_table->tables;
 192
 193         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 194                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 195
 196         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
 197                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 198
 199         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 200                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 201
 202         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 203                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 204
 205         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 206         if (!smu_table->metrics_table)
 207                 return -ENOMEM;
 208         smu_table->metrics_time = 0;
 209
 210         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_1);
 211         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 212         if (!smu_table->gpu_metrics_table) {
 213                 kfree(smu_table->metrics_table);
 214                 return -ENOMEM;
 215         }
 216
 217         return 0;
 218 }
 219
 220 static int aldebaran_allocate_dpm_context(struct smu_context *smu)
 221 {
 222         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 223
 224         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
 225                                        GFP_KERNEL);
 226         if (!smu_dpm->dpm_context)
 227                 return -ENOMEM;
 228         smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
 229
 230         smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 231                                                    GFP_KERNEL);
 232         if (!smu_dpm->dpm_current_power_state)
 233                 return -ENOMEM;
 234
 235         smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 236                                                    GFP_KERNEL);
 237         if (!smu_dpm->dpm_request_power_state)
 238                 return -ENOMEM;
 239
 240         return 0;
 241 }
 242
 243 static int aldebaran_init_smc_tables(struct smu_context *smu)
 244 {
 245         int ret = 0;
 246
 247         ret = aldebaran_tables_init(smu);
 248         if (ret)
 249                 return ret;
 250
 251         ret = aldebaran_allocate_dpm_context(smu);
 252         if (ret)
 253                 return ret;
 254
 255         return smu_v13_0_init_smc_tables(smu);
 256 }
 257
 258 static int aldebaran_get_allowed_feature_mask(struct smu_context *smu,
 259                                               uint32_t *feature_mask, uint32_t num)
 260 {
 261         if (num > 2)
 262                 return -EINVAL;
 263
 264         /* pptable will handle the features to enable */
 265         memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
 266
 267         return 0;
 268 }
 269
 270 static int aldebaran_set_default_dpm_table(struct smu_context *smu)
 271 {
 272         struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 273         struct smu_13_0_dpm_table *dpm_table = NULL;
 274         PPTable_t *pptable = smu->smu_table.driver_pptable;
 275         int ret = 0;
 276
 277         /* socclk dpm table setup */
 278         dpm_table = &dpm_context->dpm_tables.soc_table;
 279         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 280                 ret = smu_v13_0_set_single_dpm_table(smu,
 281                                                      SMU_SOCCLK,
 282                                                      dpm_table);
 283                 if (ret)
 284                         return ret;
 285         } else {
 286                 dpm_table->count = 1;
 287                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 288                 dpm_table->dpm_levels[0].enabled = true;
 289                 dpm_table->min = dpm_table->dpm_levels[0].value;
 290                 dpm_table->max = dpm_table->dpm_levels[0].value;
 291         }
 292
 293         /* gfxclk dpm table setup */
 294         dpm_table = &dpm_context->dpm_tables.gfx_table;
 295         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 296                 /* in the case of gfxclk, only fine-grained dpm is honored */
 297                 dpm_table->count = 2;
 298                 dpm_table->dpm_levels[0].value = pptable->GfxclkFmin;
 299                 dpm_table->dpm_levels[0].enabled = true;
 300                 dpm_table->dpm_levels[1].value = pptable->GfxclkFmax;
 301                 dpm_table->dpm_levels[1].enabled = true;
 302                 dpm_table->min = dpm_table->dpm_levels[0].value;
 303                 dpm_table->max = dpm_table->dpm_levels[1].value;
 304         } else {
 305                 dpm_table->count = 1;
 306                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 307                 dpm_table->dpm_levels[0].enabled = true;
 308                 dpm_table->min = dpm_table->dpm_levels[0].value;
 309                 dpm_table->max = dpm_table->dpm_levels[0].value;
 310         }
 311
 312         /* memclk dpm table setup */
 313         dpm_table = &dpm_context->dpm_tables.uclk_table;
 314         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 315                 ret = smu_v13_0_set_single_dpm_table(smu,
 316                                                      SMU_UCLK,
 317                                                      dpm_table);
 318                 if (ret)
 319                         return ret;
 320         } else {
 321                 dpm_table->count = 1;
 322                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 323                 dpm_table->dpm_levels[0].enabled = true;
 324                 dpm_table->min = dpm_table->dpm_levels[0].value;
 325                 dpm_table->max = dpm_table->dpm_levels[0].value;
 326         }
 327
 328         /* fclk dpm table setup */
 329         dpm_table = &dpm_context->dpm_tables.fclk_table;
 330         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 331                 ret = smu_v13_0_set_single_dpm_table(smu,
 332                                                      SMU_FCLK,
 333                                                      dpm_table);
 334                 if (ret)
 335                         return ret;
 336         } else {
 337                 dpm_table->count = 1;
 338                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 339                 dpm_table->dpm_levels[0].enabled = true;
 340                 dpm_table->min = dpm_table->dpm_levels[0].value;
 341                 dpm_table->max = dpm_table->dpm_levels[0].value;
 342         }
 343
 344         return 0;
 345 }
 346
 347 static int aldebaran_check_powerplay_table(struct smu_context *smu)
 348 {
 349         struct smu_table_context *table_context = &smu->smu_table;
 350         struct smu_13_0_powerplay_table *powerplay_table =
 351                 table_context->power_play_table;
 352         struct smu_baco_context *smu_baco = &smu->smu_baco;
 353
 354         mutex_lock(&smu_baco->mutex);
 355         if (powerplay_table->platform_caps & SMU_13_0_PP_PLATFORM_CAP_BACO ||
 356             powerplay_table->platform_caps & SMU_13_0_PP_PLATFORM_CAP_MACO)
 357                 smu_baco->platform_support = true;
 358         mutex_unlock(&smu_baco->mutex);
 359
 360         table_context->thermal_controller_type =
 361                 powerplay_table->thermal_controller_type;
 362
 363         return 0;
 364 }
 365
 366 static int aldebaran_store_powerplay_table(struct smu_context *smu)
 367 {
 368         struct smu_table_context *table_context = &smu->smu_table;
 369         struct smu_13_0_powerplay_table *powerplay_table =
 370                 table_context->power_play_table;
 371         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 372                sizeof(PPTable_t));
 373
 374         return 0;
 375 }
 376
 377 static int aldebaran_append_powerplay_table(struct smu_context *smu)
 378 {
 379         struct smu_table_context *table_context = &smu->smu_table;
 380         PPTable_t *smc_pptable = table_context->driver_pptable;
 381         struct atom_smc_dpm_info_v4_10 *smc_dpm_table;
 382         int index, ret;
 383
 384         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 385                                            smc_dpm_info);
 386
 387         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 388                                       (uint8_t **)&smc_dpm_table);
 389         if (ret)
 390                 return ret;
 391
 392         dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
 393                         smc_dpm_table->table_header.format_revision,
 394                         smc_dpm_table->table_header.content_revision);
 395
 396         if ((smc_dpm_table->table_header.format_revision == 4) &&
 397             (smc_dpm_table->table_header.content_revision == 10))
 398                 memcpy(&smc_pptable->GfxMaxCurrent,
 399                        &smc_dpm_table->GfxMaxCurrent,
 400                        sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_10, GfxMaxCurrent));
 401         return 0;
 402 }
 403
 404 static int aldebaran_setup_pptable(struct smu_context *smu)
 405 {
 406         int ret = 0;
 407
 408         ret = smu_v13_0_setup_pptable(smu);
 409         if (ret)
 410                 return ret;
 411
 412         ret = aldebaran_store_powerplay_table(smu);
 413         if (ret)
 414                 return ret;
 415
 416         ret = aldebaran_append_powerplay_table(smu);
 417         if (ret)
 418                 return ret;
 419
 420         ret = aldebaran_check_powerplay_table(smu);
 421         if (ret)
 422                 return ret;
 423
 424         return ret;
 425 }
 426
 427 static int aldebaran_run_btc(struct smu_context *smu)
 428 {
 429         int ret;
 430
 431         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
 432         if (ret)
 433                 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
 434
 435         return ret;
 436 }
 437
 438 static int aldebaran_populate_umd_state_clk(struct smu_context *smu)
 439 {
 440         struct smu_13_0_dpm_context *dpm_context =
 441                 smu->smu_dpm.dpm_context;
 442         struct smu_13_0_dpm_table *gfx_table =
 443                 &dpm_context->dpm_tables.gfx_table;
 444         struct smu_13_0_dpm_table *mem_table =
 445                 &dpm_context->dpm_tables.uclk_table;
 446         struct smu_13_0_dpm_table *soc_table =
 447                 &dpm_context->dpm_tables.soc_table;
 448         struct smu_umd_pstate_table *pstate_table =
 449                 &smu->pstate_table;
 450
 451         pstate_table->gfxclk_pstate.min = gfx_table->min;
 452         pstate_table->gfxclk_pstate.peak = gfx_table->max;
 453
 454         pstate_table->uclk_pstate.min = mem_table->min;
 455         pstate_table->uclk_pstate.peak = mem_table->max;
 456
 457         pstate_table->socclk_pstate.min = soc_table->min;
 458         pstate_table->socclk_pstate.peak = soc_table->max;
 459
 460         if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL &&
 461             mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL &&
 462             soc_table->count > ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL) {
 463                 pstate_table->gfxclk_pstate.standard =
 464                         gfx_table->dpm_levels[ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL].value;
 465                 pstate_table->uclk_pstate.standard =
 466                         mem_table->dpm_levels[ALDEBARAN_UMD_PSTATE_MCLK_LEVEL].value;
 467                 pstate_table->socclk_pstate.standard =
 468                         soc_table->dpm_levels[ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL].value;
 469         } else {
 470                 pstate_table->gfxclk_pstate.standard =
 471                         pstate_table->gfxclk_pstate.min;
 472                 pstate_table->uclk_pstate.standard =
 473                         pstate_table->uclk_pstate.min;
 474                 pstate_table->socclk_pstate.standard =
 475                         pstate_table->socclk_pstate.min;
 476         }
 477
 478         return 0;
 479 }
 480
 481 static int aldebaran_get_clk_table(struct smu_context *smu,
 482                                    struct pp_clock_levels_with_latency *clocks,
 483                                    struct smu_13_0_dpm_table *dpm_table)
 484 {
 485         int i, count;
 486
 487         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 488         clocks->num_levels = count;
 489
 490         for (i = 0; i < count; i++) {
 491                 clocks->data[i].clocks_in_khz =
 492                         dpm_table->dpm_levels[i].value * 1000;
 493                 clocks->data[i].latency_in_us = 0;
 494         }
 495
 496         return 0;
 497 }
 498
 499 static int aldebaran_freqs_in_same_level(int32_t frequency1,
 500                                          int32_t frequency2)
 501 {
 502         return (abs(frequency1 - frequency2) <= EPSILON);
 503 }
 504
 505 static int aldebaran_get_smu_metrics_data(struct smu_context *smu,
 506                                           MetricsMember_t member,
 507                                           uint32_t *value)
 508 {
 509         struct smu_table_context *smu_table= &smu->smu_table;
 510         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 511         int ret = 0;
 512
 513         mutex_lock(&smu->metrics_lock);
 514
 515         ret = smu_cmn_get_metrics_table_locked(smu,
 516                                                NULL,
 517                                                false);
 518         if (ret) {
 519                 mutex_unlock(&smu->metrics_lock);
 520                 return ret;
 521         }
 522
 523         switch (member) {
 524         case METRICS_CURR_GFXCLK:
 525                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 526                 break;
 527         case METRICS_CURR_SOCCLK:
 528                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 529                 break;
 530         case METRICS_CURR_UCLK:
 531                 *value = metrics->CurrClock[PPCLK_UCLK];
 532                 break;
 533         case METRICS_CURR_VCLK:
 534                 *value = metrics->CurrClock[PPCLK_VCLK];
 535                 break;
 536         case METRICS_CURR_DCLK:
 537                 *value = metrics->CurrClock[PPCLK_DCLK];
 538                 break;
 539         case METRICS_CURR_FCLK:
 540                 *value = metrics->CurrClock[PPCLK_FCLK];
 541                 break;
 542         case METRICS_AVERAGE_GFXCLK:
 543                 *value = metrics->AverageGfxclkFrequency;
 544                 break;
 545         case METRICS_AVERAGE_SOCCLK:
 546                 *value = metrics->AverageSocclkFrequency;
 547                 break;
 548         case METRICS_AVERAGE_UCLK:
 549                 *value = metrics->AverageUclkFrequency;
 550                 break;
 551         case METRICS_AVERAGE_GFXACTIVITY:
 552                 *value = metrics->AverageGfxActivity;
 553                 break;
 554         case METRICS_AVERAGE_MEMACTIVITY:
 555                 *value = metrics->AverageUclkActivity;
 556                 break;
 557         case METRICS_AVERAGE_SOCKETPOWER:
 558                 *value = metrics->AverageSocketPower << 8;
 559                 break;
 560         case METRICS_TEMPERATURE_EDGE:
 561                 *value = metrics->TemperatureEdge *
 562                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 563                 break;
 564         case METRICS_TEMPERATURE_HOTSPOT:
 565                 *value = metrics->TemperatureHotspot *
 566                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 567                 break;
 568         case METRICS_TEMPERATURE_MEM:
 569                 *value = metrics->TemperatureHBM *
 570                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 571                 break;
 572         case METRICS_TEMPERATURE_VRGFX:
 573                 *value = metrics->TemperatureVrGfx *
 574                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 575                 break;
 576         case METRICS_TEMPERATURE_VRSOC:
 577                 *value = metrics->TemperatureVrSoc *
 578                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 579                 break;
 580         case METRICS_TEMPERATURE_VRMEM:
 581                 *value = metrics->TemperatureVrMem *
 582                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 583                 break;
 584         case METRICS_THROTTLER_STATUS:
 585                 *value = metrics->ThrottlerStatus;
 586                 break;
 587         default:
 588                 *value = UINT_MAX;
 589                 break;
 590         }
 591
 592         mutex_unlock(&smu->metrics_lock);
 593
 594         return ret;
 595 }
 596
 597 static int aldebaran_get_current_clk_freq_by_table(struct smu_context *smu,
 598                                                    enum smu_clk_type clk_type,
 599                                                    uint32_t *value)
 600 {
 601         MetricsMember_t member_type;
 602         int clk_id = 0;
 603
 604         if (!value)
 605                 return -EINVAL;
 606
 607         clk_id = smu_cmn_to_asic_specific_index(smu,
 608                                                 CMN2ASIC_MAPPING_CLK,
 609                                                 clk_type);
 610         if (clk_id < 0)
 611                 return -EINVAL;
 612
 613         switch (clk_id) {
 614         case PPCLK_GFXCLK:
 615                 /*
 616                  * CurrClock[clk_id] can provide accurate
 617                  *   output only when the dpm feature is enabled.
 618                  * We can use Average_* for dpm disabled case.
 619                  *   But this is available for gfxclk/uclk/socclk/vclk/dclk.
 620                  */
 621                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
 622                         member_type = METRICS_CURR_GFXCLK;
 623                 else
 624                         member_type = METRICS_AVERAGE_GFXCLK;
 625                 break;
 626         case PPCLK_UCLK:
 627                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
 628                         member_type = METRICS_CURR_UCLK;
 629                 else
 630                         member_type = METRICS_AVERAGE_UCLK;
 631                 break;
 632         case PPCLK_SOCCLK:
 633                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
 634                         member_type = METRICS_CURR_SOCCLK;
 635                 else
 636                         member_type = METRICS_AVERAGE_SOCCLK;
 637                 break;
 638         case PPCLK_VCLK:
 639                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
 640                         member_type = METRICS_CURR_VCLK;
 641                 else
 642                         member_type = METRICS_AVERAGE_VCLK;
 643                 break;
 644         case PPCLK_DCLK:
 645                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
 646                         member_type = METRICS_CURR_DCLK;
 647                 else
 648                         member_type = METRICS_AVERAGE_DCLK;
 649                 break;
 650         case PPCLK_FCLK:
 651                 member_type = METRICS_CURR_FCLK;
 652                 break;
 653         default:
 654                 return -EINVAL;
 655         }
 656
 657         return aldebaran_get_smu_metrics_data(smu,
 658                                               member_type,
 659                                               value);
 660 }
 661
 662 static int aldebaran_print_clk_levels(struct smu_context *smu,
 663                                       enum smu_clk_type type, char *buf)
 664 {
 665         int i, now, size = 0;
 666         int ret = 0;
 667         struct pp_clock_levels_with_latency clocks;
 668         struct smu_13_0_dpm_table *single_dpm_table;
 669         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 670         struct smu_13_0_dpm_context *dpm_context = NULL;
 671         uint32_t display_levels;
 672         uint32_t freq_values[3] = {0};
 673
 674         if (amdgpu_ras_intr_triggered())
 675                 return snprintf(buf, PAGE_SIZE, "unavailable\n");
 676
 677         dpm_context = smu_dpm->dpm_context;
 678
 679         switch (type) {
 680
 681         case SMU_OD_SCLK:
 682                 size = sprintf(buf, "%s:\n", "GFXCLK");
 683                 fallthrough;
 684         case SMU_SCLK:
 685                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now);
 686                 if (ret) {
 687                         dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!");
 688                         return ret;
 689                 }
 690
 691                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 692                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 693                 if (ret) {
 694                         dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
 695                         return ret;
 696                 }
 697
 698                 display_levels = clocks.num_levels;
 699
 700                 /* fine-grained dpm has only 2 levels */
 701                 if (now > single_dpm_table->dpm_levels[0].value &&
 702                                 now < single_dpm_table->dpm_levels[1].value) {
 703                         display_levels = clocks.num_levels + 1;
 704                         freq_values[0] = single_dpm_table->dpm_levels[0].value;
 705                         freq_values[2] = single_dpm_table->dpm_levels[1].value;
 706                         freq_values[1] = now;
 707                 }
 708
 709                 /*
 710                  * For DPM disabled case, there will be only one clock level.
 711                  * And it's safe to assume that is always the current clock.
 712                  */
 713                 if (display_levels == clocks.num_levels) {
 714                         for (i = 0; i < clocks.num_levels; i++)
 715                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i,
 716                                                 clocks.data[i].clocks_in_khz / 1000,
 717                                                 (clocks.num_levels == 1) ? "*" :
 718                                                 (aldebaran_freqs_in_same_level(
 719                                                                        clocks.data[i].clocks_in_khz / 1000,
 720                                                                        now) ? "*" : ""));
 721                 } else {
 722                         for (i = 0; i < display_levels; i++)
 723                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i,
 724                                                 freq_values[i], i == 1 ? "*" : "");
 725                 }
 726
 727                 break;
 728
 729         case SMU_OD_MCLK:
 730                 size = sprintf(buf, "%s:\n", "MCLK");
 731                 fallthrough;
 732         case SMU_MCLK:
 733                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, &now);
 734                 if (ret) {
 735                         dev_err(smu->adev->dev, "Attempt to get current mclk Failed!");
 736                         return ret;
 737                 }
 738
 739                 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
 740                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 741                 if (ret) {
 742                         dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
 743                         return ret;
 744                 }
 745
 746                 for (i = 0; i < clocks.num_levels; i++)
 747                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 748                                         i, clocks.data[i].clocks_in_khz / 1000,
 749                                         (clocks.num_levels == 1) ? "*" :
 750                                         (aldebaran_freqs_in_same_level(
 751                                                                        clocks.data[i].clocks_in_khz / 1000,
 752                                                                        now) ? "*" : ""));
 753                 break;
 754
 755         case SMU_SOCCLK:
 756                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now);
 757                 if (ret) {
 758                         dev_err(smu->adev->dev, "Attempt to get current socclk Failed!");
 759                         return ret;
 760                 }
 761
 762                 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
 763                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 764                 if (ret) {
 765                         dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
 766                         return ret;
 767                 }
 768
 769                 for (i = 0; i < clocks.num_levels; i++)
 770                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 771                                         i, clocks.data[i].clocks_in_khz / 1000,
 772                                         (clocks.num_levels == 1) ? "*" :
 773                                         (aldebaran_freqs_in_same_level(
 774                                                                        clocks.data[i].clocks_in_khz / 1000,
 775                                                                        now) ? "*" : ""));
 776                 break;
 777
 778         case SMU_FCLK:
 779                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_FCLK, &now);
 780                 if (ret) {
 781                         dev_err(smu->adev->dev, "Attempt to get current fclk Failed!");
 782                         return ret;
 783                 }
 784
 785                 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
 786                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 787                 if (ret) {
 788                         dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
 789                         return ret;
 790                 }
 791
 792                 for (i = 0; i < single_dpm_table->count; i++)
 793                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 794                                         i, single_dpm_table->dpm_levels[i].value,
 795                                         (clocks.num_levels == 1) ? "*" :
 796                                         (aldebaran_freqs_in_same_level(
 797                                                                        clocks.data[i].clocks_in_khz / 1000,
 798                                                                        now) ? "*" : ""));
 799                 break;
 800
 801         default:
 802                 break;
 803         }
 804
 805         return size;
 806 }
 807
 808 static int aldebaran_upload_dpm_level(struct smu_context *smu,
 809                                       bool max,
 810                                       uint32_t feature_mask,
 811                                       uint32_t level)
 812 {
 813         struct smu_13_0_dpm_context *dpm_context =
 814                 smu->smu_dpm.dpm_context;
 815         uint32_t freq;
 816         int ret = 0;
 817
 818         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
 819             (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) {
 820                 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
 821                 ret = smu_cmn_send_smc_msg_with_param(smu,
 822                                                       (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 823                                                       (PPCLK_GFXCLK << 16) | (freq & 0xffff),
 824                                                       NULL);
 825                 if (ret) {
 826                         dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
 827                                 max ? "max" : "min");
 828                         return ret;
 829                 }
 830         }
 831
 832         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 833             (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) {
 834                 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
 835                 ret = smu_cmn_send_smc_msg_with_param(smu,
 836                                                       (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 837                                                       (PPCLK_UCLK << 16) | (freq & 0xffff),
 838                                                       NULL);
 839                 if (ret) {
 840                         dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
 841                                 max ? "max" : "min");
 842                         return ret;
 843                 }
 844         }
 845
 846         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
 847             (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) {
 848                 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
 849                 ret = smu_cmn_send_smc_msg_with_param(smu,
 850                                                       (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 851                                                       (PPCLK_SOCCLK << 16) | (freq & 0xffff),
 852                                                       NULL);
 853                 if (ret) {
 854                         dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
 855                                 max ? "max" : "min");
 856                         return ret;
 857                 }
 858         }
 859
 860         return ret;
 861 }
 862
 863 static int aldebaran_force_clk_levels(struct smu_context *smu,
 864                                       enum smu_clk_type type, uint32_t mask)
 865 {
 866         struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 867         struct smu_13_0_dpm_table *single_dpm_table = NULL;
 868         uint32_t soft_min_level, soft_max_level;
 869         int ret = 0;
 870
 871         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 872         soft_max_level = mask ? (fls(mask) - 1) : 0;
 873
 874         switch (type) {
 875         case SMU_SCLK:
 876                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 877                 if (soft_max_level >= single_dpm_table->count) {
 878                         dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
 879                                 soft_max_level, single_dpm_table->count - 1);
 880                         ret = -EINVAL;
 881                         break;
 882                 }
 883
 884                 ret = aldebaran_upload_dpm_level(smu,
 885                                                  false,
 886                                                  FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT),
 887                                                  soft_min_level);
 888                 if (ret) {
 889                         dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
 890                         break;
 891                 }
 892
 893                 ret = aldebaran_upload_dpm_level(smu,
 894                                                  true,
 895                                                  FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT),
 896                                                  soft_max_level);
 897                 if (ret)
 898                         dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
 899
 900                 break;
 901
 902         case SMU_MCLK:
 903         case SMU_SOCCLK:
 904         case SMU_FCLK:
 905                 /*
 906                  * Should not arrive here since aldebaran does not
 907                  * support mclk/socclk/fclk softmin/softmax settings
 908                  */
 909                 ret = -EINVAL;
 910                 break;
 911
 912         default:
 913                 break;
 914         }
 915
 916         return ret;
 917 }
 918
 919 static int aldebaran_get_thermal_temperature_range(struct smu_context *smu,
 920                                                    struct smu_temperature_range *range)
 921 {
 922         struct smu_table_context *table_context = &smu->smu_table;
 923         struct smu_13_0_powerplay_table *powerplay_table =
 924                 table_context->power_play_table;
 925         PPTable_t *pptable = smu->smu_table.driver_pptable;
 926
 927         if (!range)
 928                 return -EINVAL;
 929
 930         memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
 931
 932         range->hotspot_crit_max = pptable->ThotspotLimit *
 933                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 934         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
 935                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 936         range->mem_crit_max = pptable->TmemLimit *
 937                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 938         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
 939                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 940         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
 941
 942         return 0;
 943 }
 944
 945 static int aldebaran_get_current_activity_percent(struct smu_context *smu,
 946                                                   enum amd_pp_sensors sensor,
 947                                                   uint32_t *value)
 948 {
 949         int ret = 0;
 950
 951         if (!value)
 952                 return -EINVAL;
 953
 954         switch (sensor) {
 955         case AMDGPU_PP_SENSOR_GPU_LOAD:
 956                 ret = aldebaran_get_smu_metrics_data(smu,
 957                                                      METRICS_AVERAGE_GFXACTIVITY,
 958                                                      value);
 959                 break;
 960         case AMDGPU_PP_SENSOR_MEM_LOAD:
 961                 ret = aldebaran_get_smu_metrics_data(smu,
 962                                                      METRICS_AVERAGE_MEMACTIVITY,
 963                                                      value);
 964                 break;
 965         default:
 966                 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
 967                 return -EINVAL;
 968         }
 969
 970         return ret;
 971 }
 972
 973 static int aldebaran_get_gpu_power(struct smu_context *smu, uint32_t *value)
 974 {
 975         if (!value)
 976                 return -EINVAL;
 977
 978         return aldebaran_get_smu_metrics_data(smu,
 979                                               METRICS_AVERAGE_SOCKETPOWER,
 980                                               value);
 981 }
 982
 983 static int aldebaran_thermal_get_temperature(struct smu_context *smu,
 984                                              enum amd_pp_sensors sensor,
 985                                              uint32_t *value)
 986 {
 987         int ret = 0;
 988
 989         if (!value)
 990                 return -EINVAL;
 991
 992         switch (sensor) {
 993         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
 994                 ret = aldebaran_get_smu_metrics_data(smu,
 995                                                      METRICS_TEMPERATURE_HOTSPOT,
 996                                                      value);
 997                 break;
 998         case AMDGPU_PP_SENSOR_EDGE_TEMP:
 999                 ret = aldebaran_get_smu_metrics_data(smu,
1000                                                      METRICS_TEMPERATURE_EDGE,
1001                                                      value);
1002                 break;
1003         case AMDGPU_PP_SENSOR_MEM_TEMP:
1004                 ret = aldebaran_get_smu_metrics_data(smu,
1005                                                      METRICS_TEMPERATURE_MEM,
1006                                                      value);
1007                 break;
1008         default:
1009                 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1010                 return -EINVAL;
1011         }
1012
1013         return ret;
1014 }
1015
1016 static int aldebaran_read_sensor(struct smu_context *smu,
1017                                  enum amd_pp_sensors sensor,
1018                                  void *data, uint32_t *size)
1019 {
1020         int ret = 0;
1021
1022         if (amdgpu_ras_intr_triggered())
1023                 return 0;
1024
1025         if (!data || !size)
1026                 return -EINVAL;
1027
1028         mutex_lock(&smu->sensor_lock);
1029         switch (sensor) {
1030         case AMDGPU_PP_SENSOR_MEM_LOAD:
1031         case AMDGPU_PP_SENSOR_GPU_LOAD:
1032                 ret = aldebaran_get_current_activity_percent(smu,
1033                                                              sensor,
1034                                                              (uint32_t *)data);
1035                 *size = 4;
1036                 break;
1037         case AMDGPU_PP_SENSOR_GPU_POWER:
1038                 ret = aldebaran_get_gpu_power(smu, (uint32_t *)data);
1039                 *size = 4;
1040                 break;
1041         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1042         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1043         case AMDGPU_PP_SENSOR_MEM_TEMP:
1044                 ret = aldebaran_thermal_get_temperature(smu, sensor,
1045                                                         (uint32_t *)data);
1046                 *size = 4;
1047                 break;
1048         case AMDGPU_PP_SENSOR_GFX_MCLK:
1049                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1050                 /* the output clock frequency in 10K unit */
1051                 *(uint32_t *)data *= 100;
1052                 *size = 4;
1053                 break;
1054         case AMDGPU_PP_SENSOR_GFX_SCLK:
1055                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1056                 *(uint32_t *)data *= 100;
1057                 *size = 4;
1058                 break;
1059         case AMDGPU_PP_SENSOR_VDDGFX:
1060                 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data);
1061                 *size = 4;
1062                 break;
1063         default:
1064                 ret = -EOPNOTSUPP;
1065                 break;
1066         }
1067         mutex_unlock(&smu->sensor_lock);
1068
1069         return ret;
1070 }
1071
1072 static int aldebaran_get_power_limit(struct smu_context *smu)
1073 {
1074         PPTable_t *pptable = smu->smu_table.driver_pptable;
1075         uint32_t power_limit = 0;
1076         int ret;
1077
1078         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
1079                 return -EINVAL;
1080
1081         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit, &power_limit);
1082
1083         if (ret) {
1084                 /* the last hope to figure out the ppt limit */
1085                 if (!pptable) {
1086                         dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1087                         return -EINVAL;
1088                 }
1089                 power_limit = pptable->PptLimit;
1090         }
1091
1092         smu->current_power_limit = smu->default_power_limit = power_limit;
1093         if (pptable)
1094                 smu->max_power_limit = pptable->PptLimit;
1095
1096         return 0;
1097 }
1098
1099 static int aldebaran_system_features_control(struct  smu_context *smu, bool enable)
1100 {
1101         int ret;
1102
1103         ret = smu_v13_0_system_features_control(smu, enable);
1104         if (!ret && enable)
1105                 ret = aldebaran_run_btc(smu);
1106
1107         return ret;
1108 }
1109
1110 static int aldebaran_set_performance_level(struct smu_context *smu,
1111                                            enum amd_dpm_forced_level level)
1112 {
1113         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1114
1115         /* Disable determinism if switching to another mode */
1116         if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
1117                         && (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1118                 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL);
1119
1120
1121         switch (level) {
1122
1123         case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM:
1124                 return 0;
1125
1126         case AMD_DPM_FORCED_LEVEL_HIGH:
1127         case AMD_DPM_FORCED_LEVEL_LOW:
1128         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1129         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1130         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1131         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1132         default:
1133                 break;
1134         }
1135
1136         return smu_v13_0_set_performance_level(smu, level);
1137 }
1138
1139 static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu,
1140                                           enum smu_clk_type clk_type,
1141                                           uint32_t min,
1142                                           uint32_t max)
1143 {
1144         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1145         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1146         struct amdgpu_device *adev = smu->adev;
1147         uint32_t min_clk;
1148         uint32_t max_clk;
1149         int ret = 0;
1150
1151         if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK)
1152                 return -EINVAL;
1153
1154         if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1155                         && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1156                 return -EINVAL;
1157
1158         if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
1159                 min_clk = max(min, dpm_context->dpm_tables.gfx_table.min);
1160                 max_clk = min(max, dpm_context->dpm_tables.gfx_table.max);
1161                 return smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1162         }
1163
1164         if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1165                 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) ||
1166                         (max > dpm_context->dpm_tables.gfx_table.max)) {
1167                         dev_warn(adev->dev,
1168                                         "Invalid max frequency %d MHz specified for determinism\n", max);
1169                         return -EINVAL;
1170                 }
1171
1172                 /* Restore default min/max clocks and enable determinism */
1173                 min_clk = dpm_context->dpm_tables.gfx_table.min;
1174                 max_clk = dpm_context->dpm_tables.gfx_table.max;
1175                 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1176                 if (!ret) {
1177                         usleep_range(500, 1000);
1178                         ret = smu_cmn_send_smc_msg_with_param(smu,
1179                                         SMU_MSG_EnableDeterminism,
1180                                         max, NULL);
1181                         if (ret)
1182                                 dev_err(adev->dev,
1183                                                 "Failed to enable determinism at GFX clock %d MHz\n", max);
1184                 }
1185         }
1186
1187         return ret;
1188 }
1189
1190 static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
1191                                                         long input[], uint32_t size)
1192 {
1193         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1194         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1195         uint32_t min_clk;
1196         uint32_t max_clk;
1197         int ret = 0;
1198
1199         /* Only allowed in manual or determinism mode */
1200         if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1201                         && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1202                 return -EINVAL;
1203
1204         switch (type) {
1205         case PP_OD_EDIT_SCLK_VDDC_TABLE:
1206                 if (size != 2) {
1207                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1208                         return -EINVAL;
1209                 }
1210
1211                 if (input[0] == 0) {
1212                         if (input[1] < dpm_context->dpm_tables.gfx_table.min) {
1213                                 dev_warn(smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n",
1214                                         input[1], dpm_context->dpm_tables.gfx_table.min);
1215                                 return -EINVAL;
1216                         }
1217                         smu->gfx_actual_hard_min_freq = input[1];
1218                 } else if (input[0] == 1) {
1219                         if (input[1] > dpm_context->dpm_tables.gfx_table.max) {
1220                                 dev_warn(smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
1221                                         input[1], dpm_context->dpm_tables.gfx_table.max);
1222                                 return -EINVAL;
1223                         }
1224                         smu->gfx_actual_soft_max_freq = input[1];
1225                 } else {
1226                         return -EINVAL;
1227                 }
1228                 break;
1229         case PP_OD_RESTORE_DEFAULT_TABLE:
1230                 if (size != 0) {
1231                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1232                         return -EINVAL;
1233                 } else {
1234                         /* Use the default frequencies for manual and determinism mode */
1235                         min_clk = dpm_context->dpm_tables.gfx_table.min;
1236                         max_clk = dpm_context->dpm_tables.gfx_table.max;
1237
1238                         return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1239                 }
1240                 break;
1241         case PP_OD_COMMIT_DPM_TABLE:
1242                 if (size != 0) {
1243                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1244                         return -EINVAL;
1245                 } else {
1246                         min_clk = smu->gfx_actual_hard_min_freq;
1247                         max_clk = smu->gfx_actual_soft_max_freq;
1248                         return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1249                 }
1250                 break;
1251         default:
1252                 return -ENOSYS;
1253         }
1254
1255         return ret;
1256 }
1257
1258 static bool aldebaran_is_dpm_running(struct smu_context *smu)
1259 {
1260         int ret = 0;
1261         uint32_t feature_mask[2];
1262         unsigned long feature_enabled;
1263         ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1264         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1265                                           ((uint64_t)feature_mask[1] << 32));
1266         return !!(feature_enabled & SMC_DPM_FEATURE);
1267 }
1268
1269 static void aldebaran_fill_i2c_req(SwI2cRequest_t  *req, bool write,
1270                                   uint8_t address, uint32_t numbytes,
1271                                   uint8_t *data)
1272 {
1273         int i;
1274
1275         req->I2CcontrollerPort = 0;
1276         req->I2CSpeed = 2;
1277         req->SlaveAddress = address;
1278         req->NumCmds = numbytes;
1279
1280         for (i = 0; i < numbytes; i++) {
1281                 SwI2cCmd_t *cmd =  &req->SwI2cCmds[i];
1282
1283                 /* First 2 bytes are always write for lower 2b EEPROM address */
1284                 if (i < 2)
1285                         cmd->CmdConfig = CMDCONFIG_READWRITE_MASK;
1286                 else
1287                         cmd->CmdConfig = write ? CMDCONFIG_READWRITE_MASK : 0;
1288
1289
1290                 /* Add RESTART for read  after address filled */
1291                 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
1292
1293                 /* Add STOP in the end */
1294                 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
1295
1296                 /* Fill with data regardless if read or write to simplify code */
1297                 cmd->ReadWriteData = data[i];
1298         }
1299 }
1300
1301 static int aldebaran_i2c_read_data(struct i2c_adapter *control,
1302                                                uint8_t address,
1303                                                uint8_t *data,
1304                                                uint32_t numbytes)
1305 {
1306         uint32_t  i, ret = 0;
1307         SwI2cRequest_t req;
1308         struct amdgpu_device *adev = to_amdgpu_device(control);
1309         struct smu_table_context *smu_table = &adev->smu.smu_table;
1310         struct smu_table *table = &smu_table->driver_table;
1311
1312         if (numbytes > MAX_SW_I2C_COMMANDS) {
1313                 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
1314                         numbytes, MAX_SW_I2C_COMMANDS);
1315                 return -EINVAL;
1316         }
1317
1318         memset(&req, 0, sizeof(req));
1319         aldebaran_fill_i2c_req(&req, false, address, numbytes, data);
1320
1321         mutex_lock(&adev->smu.mutex);
1322         /* Now read data starting with that address */
1323         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
1324                                         true);
1325         mutex_unlock(&adev->smu.mutex);
1326
1327         if (!ret) {
1328                 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
1329
1330                 /* Assume SMU  fills res.SwI2cCmds[i].Data with read bytes */
1331                 for (i = 0; i < numbytes; i++)
1332                         data[i] = res->SwI2cCmds[i].ReadWriteData;
1333
1334                 dev_dbg(adev->dev, "aldebaran_i2c_read_data, address = %x, bytes = %d, data :",
1335                                   (uint16_t)address, numbytes);
1336
1337                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
1338                                8, 1, data, numbytes, false);
1339         } else
1340                 dev_err(adev->dev, "aldebaran_i2c_read_data - error occurred :%x", ret);
1341
1342         return ret;
1343 }
1344
1345 static int aldebaran_i2c_write_data(struct i2c_adapter *control,
1346                                                 uint8_t address,
1347                                                 uint8_t *data,
1348                                                 uint32_t numbytes)
1349 {
1350         uint32_t ret;
1351         SwI2cRequest_t req;
1352         struct amdgpu_device *adev = to_amdgpu_device(control);
1353
1354         if (numbytes > MAX_SW_I2C_COMMANDS) {
1355                 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
1356                         numbytes, MAX_SW_I2C_COMMANDS);
1357                 return -EINVAL;
1358         }
1359
1360         memset(&req, 0, sizeof(req));
1361         aldebaran_fill_i2c_req(&req, true, address, numbytes, data);
1362
1363         mutex_lock(&adev->smu.mutex);
1364         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
1365         mutex_unlock(&adev->smu.mutex);
1366
1367         if (!ret) {
1368                 dev_dbg(adev->dev, "aldebaran_i2c_write(), address = %x, bytes = %d , data: ",
1369                                          (uint16_t)address, numbytes);
1370
1371                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
1372                                8, 1, data, numbytes, false);
1373                 /*
1374                  * According to EEPROM spec there is a MAX of 10 ms required for
1375                  * EEPROM to flush internal RX buffer after STOP was issued at the
1376                  * end of write transaction. During this time the EEPROM will not be
1377                  * responsive to any more commands - so wait a bit more.
1378                  */
1379                 msleep(10);
1380
1381         } else
1382                 dev_err(adev->dev, "aldebaran_i2c_write- error occurred :%x", ret);
1383
1384         return ret;
1385 }
1386
1387 static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap,
1388                               struct i2c_msg *msgs, int num)
1389 {
1390         uint32_t  i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
1391         uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
1392
1393         for (i = 0; i < num; i++) {
1394                 /*
1395                  * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
1396                  * once and hence the data needs to be spliced into chunks and sent each
1397                  * chunk separately
1398                  */
1399                 data_size = msgs[i].len - 2;
1400                 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
1401                 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
1402                 data_ptr = msgs[i].buf + 2;
1403
1404                 for (j = 0; j < data_size / data_chunk_size; j++) {
1405                         /* Insert the EEPROM dest addess, bits 0-15 */
1406                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
1407                         data_chunk[1] = (next_eeprom_addr & 0xff);
1408
1409                         if (msgs[i].flags & I2C_M_RD) {
1410                                 ret = aldebaran_i2c_read_data(i2c_adap,
1411                                                              (uint8_t)msgs[i].addr,
1412                                                              data_chunk, MAX_SW_I2C_COMMANDS);
1413
1414                                 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
1415                         } else {
1416
1417                                 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
1418
1419                                 ret = aldebaran_i2c_write_data(i2c_adap,
1420                                                               (uint8_t)msgs[i].addr,
1421                                                               data_chunk, MAX_SW_I2C_COMMANDS);
1422                         }
1423
1424                         if (ret) {
1425                                 num = -EIO;
1426                                 goto fail;
1427                         }
1428
1429                         next_eeprom_addr += data_chunk_size;
1430                         data_ptr += data_chunk_size;
1431                 }
1432
1433                 if (data_size % data_chunk_size) {
1434                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
1435                         data_chunk[1] = (next_eeprom_addr & 0xff);
1436
1437                         if (msgs[i].flags & I2C_M_RD) {
1438                                 ret = aldebaran_i2c_read_data(i2c_adap,
1439                                                              (uint8_t)msgs[i].addr,
1440                                                              data_chunk, (data_size % data_chunk_size) + 2);
1441
1442                                 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
1443                         } else {
1444                                 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
1445
1446                                 ret = aldebaran_i2c_write_data(i2c_adap,
1447                                                               (uint8_t)msgs[i].addr,
1448                                                               data_chunk, (data_size % data_chunk_size) + 2);
1449                         }
1450
1451                         if (ret) {
1452                                 num = -EIO;
1453                                 goto fail;
1454                         }
1455                 }
1456         }
1457
1458 fail:
1459         return num;
1460 }
1461
1462 static u32 aldebaran_i2c_func(struct i2c_adapter *adap)
1463 {
1464         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1465 }
1466
1467
1468 static const struct i2c_algorithm aldebaran_i2c_algo = {
1469         .master_xfer = aldebaran_i2c_xfer,
1470         .functionality = aldebaran_i2c_func,
1471 };
1472
1473 static int aldebaran_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
1474 {
1475         struct amdgpu_device *adev = to_amdgpu_device(control);
1476         int res;
1477
1478         control->owner = THIS_MODULE;
1479         control->class = I2C_CLASS_SPD;
1480         control->dev.parent = &adev->pdev->dev;
1481         control->algo = &aldebaran_i2c_algo;
1482         snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
1483
1484         res = i2c_add_adapter(control);
1485         if (res)
1486                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
1487
1488         return res;
1489 }
1490
1491 static void aldebaran_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
1492 {
1493         i2c_del_adapter(control);
1494 }
1495
1496 static void aldebaran_get_unique_id(struct smu_context *smu)
1497 {
1498         struct amdgpu_device *adev = smu->adev;
1499         SmuMetrics_t *metrics = smu->smu_table.metrics_table;
1500         uint32_t upper32 = 0, lower32 = 0;
1501         int ret;
1502
1503         mutex_lock(&smu->metrics_lock);
1504         ret = smu_cmn_get_metrics_table_locked(smu, NULL, false);
1505         if (ret)
1506                 goto out_unlock;
1507
1508         upper32 = metrics->PublicSerialNumUpper32;
1509         lower32 = metrics->PublicSerialNumLower32;
1510
1511 out_unlock:
1512         mutex_unlock(&smu->metrics_lock);
1513
1514         adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1515         sprintf(adev->serial, "%016llx", adev->unique_id);
1516 }
1517
1518 static bool aldebaran_is_baco_supported(struct smu_context *smu)
1519 {
1520         /* aldebaran is not support baco */
1521
1522         return false;
1523 }
1524
1525 static int aldebaran_set_df_cstate(struct smu_context *smu,
1526                                    enum pp_df_cstate state)
1527 {
1528         return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
1529 }
1530
1531 static int aldebaran_allow_xgmi_power_down(struct smu_context *smu, bool en)
1532 {
1533         return smu_cmn_send_smc_msg_with_param(smu,
1534                                                SMU_MSG_GmiPwrDnControl,
1535                                                en ? 1 : 0,
1536                                                NULL);
1537 }
1538
1539 static const struct throttling_logging_label {
1540         uint32_t feature_mask;
1541         const char *label;
1542 } logging_label[] = {
1543         {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
1544         {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
1545         {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
1546         {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
1547 };
1548 static void aldebaran_log_thermal_throttling_event(struct smu_context *smu)
1549 {
1550         int ret;
1551         int throttler_idx, throtting_events = 0, buf_idx = 0;
1552         struct amdgpu_device *adev = smu->adev;
1553         uint32_t throttler_status;
1554         char log_buf[256];
1555
1556         ret = aldebaran_get_smu_metrics_data(smu,
1557                                              METRICS_THROTTLER_STATUS,
1558                                              &throttler_status);
1559         if (ret)
1560                 return;
1561
1562         memset(log_buf, 0, sizeof(log_buf));
1563         for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
1564              throttler_idx++) {
1565                 if (throttler_status & logging_label[throttler_idx].feature_mask) {
1566                         throtting_events++;
1567                         buf_idx += snprintf(log_buf + buf_idx,
1568                                             sizeof(log_buf) - buf_idx,
1569                                             "%s%s",
1570                                             throtting_events > 1 ? " and " : "",
1571                                             logging_label[throttler_idx].label);
1572                         if (buf_idx >= sizeof(log_buf)) {
1573                                 dev_err(adev->dev, "buffer overflow!\n");
1574                                 log_buf[sizeof(log_buf) - 1] = '\0';
1575                                 break;
1576                         }
1577                 }
1578         }
1579
1580         dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
1581                  log_buf);
1582         kgd2kfd_smi_event_throttle(smu->adev->kfd.dev, throttler_status);
1583 }
1584
1585 static int aldebaran_get_current_pcie_link_speed(struct smu_context *smu)
1586 {
1587         struct amdgpu_device *adev = smu->adev;
1588         uint32_t esm_ctrl;
1589
1590         /* TODO: confirm this on real target */
1591         esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
1592         if ((esm_ctrl >> 15) & 0x1FFFF)
1593                 return (((esm_ctrl >> 8) & 0x3F) + 128);
1594
1595         return smu_v13_0_get_current_pcie_link_speed(smu);
1596 }
1597
1598 static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu,
1599                                          void **table)
1600 {
1601         struct smu_table_context *smu_table = &smu->smu_table;
1602         struct gpu_metrics_v1_1 *gpu_metrics =
1603                 (struct gpu_metrics_v1_1 *)smu_table->gpu_metrics_table;
1604         SmuMetrics_t metrics;
1605         int i, ret = 0;
1606
1607         ret = smu_cmn_get_metrics_table(smu,
1608                                         &metrics,
1609                                         true);
1610         if (ret)
1611                 return ret;
1612
1613         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 1);
1614
1615         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
1616         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
1617         gpu_metrics->temperature_mem = metrics.TemperatureHBM;
1618         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
1619         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
1620         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
1621
1622         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
1623         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
1624         gpu_metrics->average_mm_activity = 0;
1625
1626         gpu_metrics->average_socket_power = metrics.AverageSocketPower;
1627         gpu_metrics->energy_accumulator = 0;
1628
1629         gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
1630         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
1631         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
1632         gpu_metrics->average_vclk0_frequency = 0;
1633         gpu_metrics->average_dclk0_frequency = 0;
1634
1635         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
1636         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
1637         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
1638         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
1639         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
1640
1641         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1642
1643         gpu_metrics->current_fan_speed = 0;
1644
1645         gpu_metrics->pcie_link_width =
1646                 smu_v13_0_get_current_pcie_link_width(smu);
1647         gpu_metrics->pcie_link_speed =
1648                 aldebaran_get_current_pcie_link_speed(smu);
1649
1650         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1651
1652         gpu_metrics->gfx_activity_acc = metrics.GfxBusyAcc;
1653         gpu_metrics->mem_activity_acc = metrics.DramBusyAcc;
1654
1655         for (i = 0; i < NUM_HBM_INSTANCES; i++)
1656                 gpu_metrics->temperature_hbm[i] = metrics.TemperatureAllHBM[i];
1657
1658         *table = (void *)gpu_metrics;
1659
1660         return sizeof(struct gpu_metrics_v1_1);
1661 }
1662
1663 static int aldebaran_mode2_reset(struct smu_context *smu)
1664 {
1665         u32 smu_version;
1666         int ret = 0, index;
1667         struct amdgpu_device *adev = smu->adev;
1668         int timeout = 10;
1669
1670         smu_cmn_get_smc_version(smu, NULL, &smu_version);
1671
1672         index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
1673                                                 SMU_MSG_GfxDeviceDriverReset);
1674
1675         mutex_lock(&smu->message_lock);
1676         if (smu_version >= 0x00441400) {
1677                 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2);
1678                 /* This is similar to FLR, wait till max FLR timeout */
1679                 msleep(100);
1680                 dev_dbg(smu->adev->dev, "restore config space...\n");
1681                 /* Restore the config space saved during init */
1682                 amdgpu_device_load_pci_state(adev->pdev);
1683
1684                 dev_dbg(smu->adev->dev, "wait for reset ack\n");
1685                 while (ret == -ETIME && timeout)  {
1686                         ret = smu_cmn_wait_for_response(smu);
1687                         /* Wait a bit more time for getting ACK */
1688                         if (ret == -ETIME) {
1689                                 --timeout;
1690                                 usleep_range(500, 1000);
1691                                 continue;
1692                         }
1693
1694                         if (ret != 1) {
1695                                 dev_err(adev->dev, "failed to send mode2 message \tparam: 0x%08x response %#x\n",
1696                                                 SMU_RESET_MODE_2, ret);
1697                                 goto out;
1698                         }
1699                 }
1700
1701         } else {
1702                 dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n",
1703                                 smu_version);
1704         }
1705
1706         if (ret == 1)
1707                 ret = 0;
1708 out:
1709         mutex_unlock(&smu->message_lock);
1710
1711         return ret;
1712 }
1713
1714 static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu)
1715 {
1716 #if 0
1717         struct amdgpu_device *adev = smu->adev;
1718         u32 smu_version;
1719         uint32_t val;
1720         /**
1721          * PM FW version support mode1 reset from 68.07
1722          */
1723         smu_cmn_get_smc_version(smu, NULL, &smu_version);
1724         if ((smu_version < 0x00440700))
1725                 return false;
1726         /**
1727          * mode1 reset relies on PSP, so we should check if
1728          * PSP is alive.
1729          */
1730         val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
1731
1732         return val != 0x0;
1733 #endif
1734         return true;
1735 }
1736
1737 static bool aldebaran_is_mode2_reset_supported(struct smu_context *smu)
1738 {
1739         return true;
1740 }
1741
1742 static int aldebaran_set_mp1_state(struct smu_context *smu,
1743                                    enum pp_mp1_state mp1_state)
1744 {
1745         switch (mp1_state) {
1746         case PP_MP1_STATE_UNLOAD:
1747                 return smu_cmn_set_mp1_state(smu, mp1_state);
1748         default:
1749                 return -EINVAL;
1750         }
1751
1752         return 0;
1753 }
1754
1755 static const struct pptable_funcs aldebaran_ppt_funcs = {
1756         /* init dpm */
1757         .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask,
1758         /* dpm/clk tables */
1759         .set_default_dpm_table = aldebaran_set_default_dpm_table,
1760         .populate_umd_state_clk = aldebaran_populate_umd_state_clk,
1761         .get_thermal_temperature_range = aldebaran_get_thermal_temperature_range,
1762         .print_clk_levels = aldebaran_print_clk_levels,
1763         .force_clk_levels = aldebaran_force_clk_levels,
1764         .read_sensor = aldebaran_read_sensor,
1765         .set_performance_level = aldebaran_set_performance_level,
1766         .get_power_limit = aldebaran_get_power_limit,
1767         .is_dpm_running = aldebaran_is_dpm_running,
1768         .get_unique_id = aldebaran_get_unique_id,
1769         .init_microcode = smu_v13_0_init_microcode,
1770         .load_microcode = smu_v13_0_load_microcode,
1771         .fini_microcode = smu_v13_0_fini_microcode,
1772         .init_smc_tables = aldebaran_init_smc_tables,
1773         .fini_smc_tables = smu_v13_0_fini_smc_tables,
1774         .init_power = smu_v13_0_init_power,
1775         .fini_power = smu_v13_0_fini_power,
1776         .check_fw_status = smu_v13_0_check_fw_status,
1777         /* pptable related */
1778         .setup_pptable = aldebaran_setup_pptable,
1779         .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
1780         .check_fw_version = smu_v13_0_check_fw_version,
1781         .write_pptable = smu_cmn_write_pptable,
1782         .set_driver_table_location = smu_v13_0_set_driver_table_location,
1783         .set_tool_table_location = smu_v13_0_set_tool_table_location,
1784         .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
1785         .system_features_control = aldebaran_system_features_control,
1786         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1787         .send_smc_msg = smu_cmn_send_smc_msg,
1788         .get_enabled_mask = smu_cmn_get_enabled_mask,
1789         .feature_is_enabled = smu_cmn_feature_is_enabled,
1790         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
1791         .set_power_limit = smu_v13_0_set_power_limit,
1792         .init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks,
1793         .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
1794         .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
1795         .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate,
1796         .register_irq_handler = smu_v13_0_register_irq_handler,
1797         .set_azalia_d3_pme = smu_v13_0_set_azalia_d3_pme,
1798         .get_max_sustainable_clocks_by_dc = smu_v13_0_get_max_sustainable_clocks_by_dc,
1799         .baco_is_support= aldebaran_is_baco_supported,
1800         .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq,
1801         .set_soft_freq_limited_range = aldebaran_set_soft_freq_limited_range,
1802         .od_edit_dpm_table = aldebaran_usr_edit_dpm_table,
1803         .set_df_cstate = aldebaran_set_df_cstate,
1804         .allow_xgmi_power_down = aldebaran_allow_xgmi_power_down,
1805         .log_thermal_throttling_event = aldebaran_log_thermal_throttling_event,
1806         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1807         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
1808         .get_gpu_metrics = aldebaran_get_gpu_metrics,
1809         .mode1_reset_is_support = aldebaran_is_mode1_reset_supported,
1810         .mode2_reset_is_support = aldebaran_is_mode2_reset_supported,
1811         .mode1_reset = smu_v13_0_mode1_reset,
1812         .set_mp1_state = aldebaran_set_mp1_state,
1813         .mode2_reset = aldebaran_mode2_reset,
1814         .wait_for_event = smu_v13_0_wait_for_event,
1815         .i2c_init = aldebaran_i2c_control_init,
1816         .i2c_fini = aldebaran_i2c_control_fini,
1817 };
1818
1819 void aldebaran_set_ppt_funcs(struct smu_context *smu)
1820 {
1821         smu->ppt_funcs = &aldebaran_ppt_funcs;
1822         smu->message_map = aldebaran_message_map;
1823         smu->clock_map = aldebaran_clk_map;
1824         smu->feature_map = aldebaran_feature_mask_map;
1825         smu->table_map = aldebaran_table_map;
1826 }