drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_smu.h"
  29 #include "atomfirmware.h"
  30 #include "amdgpu_atomfirmware.h"
  31 #include "amdgpu_atombios.h"
  32 #include "smu_v13_0.h"
  33 #include "smu13_driver_if_aldebaran.h"
  34 #include "soc15_common.h"
  35 #include "atom.h"
  36 #include "power_state.h"
  37 #include "aldebaran_ppt.h"
  38 #include "smu_v13_0_pptable.h"
  39 #include "aldebaran_ppsmc.h"
  40 #include "nbio/nbio_7_4_offset.h"
  41 #include "nbio/nbio_7_4_sh_mask.h"
  42 #include "thm/thm_11_0_2_offset.h"
  43 #include "thm/thm_11_0_2_sh_mask.h"
  44 #include "amdgpu_xgmi.h"
  45 #include <linux/pci.h>
  46 #include "amdgpu_ras.h"
  47 #include "smu_cmn.h"
  48 #include "mp/mp_13_0_2_offset.h"
  49
  50 /*
  51  * DO NOT use these for err/warn/info/debug messages.
  52  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  53  * They are more MGPU friendly.
  54  */
  55 #undef pr_err
  56 #undef pr_warn
  57 #undef pr_info
  58 #undef pr_debug
  59
  60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  61
  62 #define ALDEBARAN_FEA_MAP(smu_feature, aldebaran_feature) \
  63         [smu_feature] = {1, (aldebaran_feature)}
  64
  65 #define FEATURE_MASK(feature) (1ULL << feature)
  66 #define SMC_DPM_FEATURE ( \
  67                           FEATURE_MASK(FEATURE_DATA_CALCULATIONS) | \
  68                           FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)  | \
  69                           FEATURE_MASK(FEATURE_DPM_UCLK_BIT)    | \
  70                           FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)  | \
  71                           FEATURE_MASK(FEATURE_DPM_FCLK_BIT)    | \
  72                           FEATURE_MASK(FEATURE_DPM_LCLK_BIT)    | \
  73                           FEATURE_MASK(FEATURE_DPM_XGMI_BIT)    | \
  74                           FEATURE_MASK(FEATURE_DPM_VCN_BIT))
  75
  76 /* possible frequency drift (1Mhz) */
  77 #define EPSILON                         1
  78
  79 #define smnPCIE_ESM_CTRL                        0x111003D0
  80
  81 static const struct smu_temperature_range smu13_thermal_policy[] =
  82 {
  83         {-273150,  99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
  84         { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
  85 };
  86
  87 static const struct cmn2asic_msg_mapping aldebaran_message_map[SMU_MSG_MAX_COUNT] = {
  88         MSG_MAP(TestMessage,                         PPSMC_MSG_TestMessage,                     0),
  89         MSG_MAP(GetSmuVersion,                       PPSMC_MSG_GetSmuVersion,                   1),
  90         MSG_MAP(GetDriverIfVersion,                  PPSMC_MSG_GetDriverIfVersion,              1),
  91         MSG_MAP(EnableAllSmuFeatures,                PPSMC_MSG_EnableAllSmuFeatures,            0),
  92         MSG_MAP(DisableAllSmuFeatures,               PPSMC_MSG_DisableAllSmuFeatures,           0),
  93         MSG_MAP(GetEnabledSmuFeaturesLow,            PPSMC_MSG_GetEnabledSmuFeaturesLow,        0),
  94         MSG_MAP(GetEnabledSmuFeaturesHigh,           PPSMC_MSG_GetEnabledSmuFeaturesHigh,       0),
  95         MSG_MAP(SetDriverDramAddrHigh,               PPSMC_MSG_SetDriverDramAddrHigh,           1),
  96         MSG_MAP(SetDriverDramAddrLow,                PPSMC_MSG_SetDriverDramAddrLow,            1),
  97         MSG_MAP(SetToolsDramAddrHigh,                PPSMC_MSG_SetToolsDramAddrHigh,            0),
  98         MSG_MAP(SetToolsDramAddrLow,                 PPSMC_MSG_SetToolsDramAddrLow,             0),
  99         MSG_MAP(TransferTableSmu2Dram,               PPSMC_MSG_TransferTableSmu2Dram,           1),
 100         MSG_MAP(TransferTableDram2Smu,               PPSMC_MSG_TransferTableDram2Smu,           0),
 101         MSG_MAP(UseDefaultPPTable,                   PPSMC_MSG_UseDefaultPPTable,               0),
 102         MSG_MAP(SetSystemVirtualDramAddrHigh,        PPSMC_MSG_SetSystemVirtualDramAddrHigh,    0),
 103         MSG_MAP(SetSystemVirtualDramAddrLow,         PPSMC_MSG_SetSystemVirtualDramAddrLow,     0),
 104         MSG_MAP(SetSoftMinByFreq,                    PPSMC_MSG_SetSoftMinByFreq,                0),
 105         MSG_MAP(SetSoftMaxByFreq,                    PPSMC_MSG_SetSoftMaxByFreq,                0),
 106         MSG_MAP(SetHardMinByFreq,                    PPSMC_MSG_SetHardMinByFreq,                0),
 107         MSG_MAP(SetHardMaxByFreq,                    PPSMC_MSG_SetHardMaxByFreq,                0),
 108         MSG_MAP(GetMinDpmFreq,                       PPSMC_MSG_GetMinDpmFreq,                   0),
 109         MSG_MAP(GetMaxDpmFreq,                       PPSMC_MSG_GetMaxDpmFreq,                   0),
 110         MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex,               1),
 111         MSG_MAP(SetWorkloadMask,                     PPSMC_MSG_SetWorkloadMask,                 1),
 112         MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm,                 0),
 113         MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive,        0),
 114         MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit,                     0),
 115         MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit,                     1),
 116         MSG_MAP(PrepareMp1ForUnload,                 PPSMC_MSG_PrepareMp1ForUnload,             0),
 117         MSG_MAP(GfxDeviceDriverReset,                PPSMC_MSG_GfxDriverReset,                  0),
 118         MSG_MAP(RunDcBtc,                            PPSMC_MSG_RunDcBtc,                        0),
 119         MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh,          0),
 120         MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow,           0),
 121         MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize,              0),
 122         MSG_MAP(GetDebugData,                        PPSMC_MSG_GetDebugData,                    0),
 123         MSG_MAP(WaflTest,                            PPSMC_MSG_WaflTest,                        0),
 124         MSG_MAP(SetMemoryChannelEnable,              PPSMC_MSG_SetMemoryChannelEnable,          0),
 125         MSG_MAP(SetNumBadHbmPagesRetired,            PPSMC_MSG_SetNumBadHbmPagesRetired,        0),
 126         MSG_MAP(DFCstateControl,                     PPSMC_MSG_DFCstateControl,                 0),
 127         MSG_MAP(GetGmiPwrDnHyst,                     PPSMC_MSG_GetGmiPwrDnHyst,                 0),
 128         MSG_MAP(SetGmiPwrDnHyst,                     PPSMC_MSG_SetGmiPwrDnHyst,                 0),
 129         MSG_MAP(GmiPwrDnControl,                     PPSMC_MSG_GmiPwrDnControl,                 0),
 130         MSG_MAP(EnterGfxoff,                         PPSMC_MSG_EnterGfxoff,                     0),
 131         MSG_MAP(ExitGfxoff,                          PPSMC_MSG_ExitGfxoff,                      0),
 132         MSG_MAP(SetExecuteDMATest,                   PPSMC_MSG_SetExecuteDMATest,               0),
 133         MSG_MAP(EnableDeterminism,                   PPSMC_MSG_EnableDeterminism,               0),
 134         MSG_MAP(DisableDeterminism,                  PPSMC_MSG_DisableDeterminism,              0),
 135         MSG_MAP(SetUclkDpmMode,                      PPSMC_MSG_SetUclkDpmMode,                  0),
 136         MSG_MAP(GfxDriverResetRecovery,              PPSMC_MSG_GfxDriverResetRecovery,          0),
 137 };
 138
 139 static const struct cmn2asic_mapping aldebaran_clk_map[SMU_CLK_COUNT] = {
 140         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 141         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 142         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 143         CLK_MAP(FCLK, PPCLK_FCLK),
 144         CLK_MAP(UCLK, PPCLK_UCLK),
 145         CLK_MAP(MCLK, PPCLK_UCLK),
 146         CLK_MAP(DCLK, PPCLK_DCLK),
 147         CLK_MAP(VCLK, PPCLK_VCLK),
 148         CLK_MAP(LCLK,   PPCLK_LCLK),
 149 };
 150
 151 static const struct cmn2asic_mapping aldebaran_feature_mask_map[SMU_FEATURE_COUNT] = {
 152         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_PREFETCHER_BIT,               FEATURE_DATA_CALCULATIONS),
 153         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT,                   FEATURE_DPM_GFXCLK_BIT),
 154         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT,                     FEATURE_DPM_UCLK_BIT),
 155         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT,                   FEATURE_DPM_SOCCLK_BIT),
 156         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT,                     FEATURE_DPM_FCLK_BIT),
 157         ALDEBARAN_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT,                     FEATURE_DPM_LCLK_BIT),
 158         ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_BIT,                                 FEATURE_DPM_XGMI_BIT),
 159         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT,                    FEATURE_DS_GFXCLK_BIT),
 160         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT,                    FEATURE_DS_SOCCLK_BIT),
 161         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT,                              FEATURE_DS_LCLK_BIT),
 162         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT,                              FEATURE_DS_FCLK_BIT),
 163         ALDEBARAN_FEA_MAP(SMU_FEATURE_DS_UCLK_BIT,                              FEATURE_DS_UCLK_BIT),
 164         ALDEBARAN_FEA_MAP(SMU_FEATURE_GFX_SS_BIT,                               FEATURE_GFX_SS_BIT),
 165         ALDEBARAN_FEA_MAP(SMU_FEATURE_VCN_PG_BIT,                               FEATURE_DPM_VCN_BIT),
 166         ALDEBARAN_FEA_MAP(SMU_FEATURE_RSMU_SMN_CG_BIT,                  FEATURE_RSMU_SMN_CG_BIT),
 167         ALDEBARAN_FEA_MAP(SMU_FEATURE_WAFL_CG_BIT,                              FEATURE_WAFL_CG_BIT),
 168         ALDEBARAN_FEA_MAP(SMU_FEATURE_PPT_BIT,                                  FEATURE_PPT_BIT),
 169         ALDEBARAN_FEA_MAP(SMU_FEATURE_TDC_BIT,                                  FEATURE_TDC_BIT),
 170         ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_PLUS_BIT,                    FEATURE_APCC_PLUS_BIT),
 171         ALDEBARAN_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT,                    FEATURE_APCC_DFLL_BIT),
 172         ALDEBARAN_FEA_MAP(SMU_FEATURE_FUSE_CG_BIT,                              FEATURE_FUSE_CG_BIT),
 173         ALDEBARAN_FEA_MAP(SMU_FEATURE_MP1_CG_BIT,                               FEATURE_MP1_CG_BIT),
 174         ALDEBARAN_FEA_MAP(SMU_FEATURE_SMUIO_CG_BIT,                     FEATURE_SMUIO_CG_BIT),
 175         ALDEBARAN_FEA_MAP(SMU_FEATURE_THM_CG_BIT,                               FEATURE_THM_CG_BIT),
 176         ALDEBARAN_FEA_MAP(SMU_FEATURE_CLK_CG_BIT,                               FEATURE_CLK_CG_BIT),
 177         ALDEBARAN_FEA_MAP(SMU_FEATURE_FW_CTF_BIT,                               FEATURE_FW_CTF_BIT),
 178         ALDEBARAN_FEA_MAP(SMU_FEATURE_THERMAL_BIT,                              FEATURE_THERMAL_BIT),
 179         ALDEBARAN_FEA_MAP(SMU_FEATURE_OUT_OF_BAND_MONITOR_BIT,  FEATURE_OUT_OF_BAND_MONITOR_BIT),
 180         ALDEBARAN_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT,FEATURE_XGMI_PER_LINK_PWR_DWN),
 181         ALDEBARAN_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT,                    FEATURE_DF_CSTATE),
 182 };
 183
 184 static const struct cmn2asic_mapping aldebaran_table_map[SMU_TABLE_COUNT] = {
 185         TAB_MAP(PPTABLE),
 186         TAB_MAP(AVFS_PSM_DEBUG),
 187         TAB_MAP(AVFS_FUSE_OVERRIDE),
 188         TAB_MAP(PMSTATUSLOG),
 189         TAB_MAP(SMU_METRICS),
 190         TAB_MAP(DRIVER_SMU_CONFIG),
 191         TAB_MAP(I2C_COMMANDS),
 192 };
 193
 194 static const uint8_t aldebaran_throttler_map[] = {
 195         [THROTTLER_PPT0_BIT]            = (SMU_THROTTLER_PPT0_BIT),
 196         [THROTTLER_PPT1_BIT]            = (SMU_THROTTLER_PPT1_BIT),
 197         [THROTTLER_TDC_GFX_BIT]         = (SMU_THROTTLER_TDC_GFX_BIT),
 198         [THROTTLER_TDC_SOC_BIT]         = (SMU_THROTTLER_TDC_SOC_BIT),
 199         [THROTTLER_TDC_HBM_BIT]         = (SMU_THROTTLER_TDC_MEM_BIT),
 200         [THROTTLER_TEMP_GPU_BIT]        = (SMU_THROTTLER_TEMP_GPU_BIT),
 201         [THROTTLER_TEMP_MEM_BIT]        = (SMU_THROTTLER_TEMP_MEM_BIT),
 202         [THROTTLER_TEMP_VR_GFX_BIT]     = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
 203         [THROTTLER_TEMP_VR_SOC_BIT]     = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
 204         [THROTTLER_TEMP_VR_MEM_BIT]     = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
 205         [THROTTLER_APCC_BIT]            = (SMU_THROTTLER_APCC_BIT),
 206 };
 207
 208 static int aldebaran_tables_init(struct smu_context *smu)
 209 {
 210         struct smu_table_context *smu_table = &smu->smu_table;
 211         struct smu_table *tables = smu_table->tables;
 212
 213         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 214                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 215
 216         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
 217                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 218
 219         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 220                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 221
 222         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 223                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 224
 225         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 226         if (!smu_table->metrics_table)
 227                 return -ENOMEM;
 228         smu_table->metrics_time = 0;
 229
 230         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 231         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 232         if (!smu_table->gpu_metrics_table) {
 233                 kfree(smu_table->metrics_table);
 234                 return -ENOMEM;
 235         }
 236
 237         return 0;
 238 }
 239
 240 static int aldebaran_allocate_dpm_context(struct smu_context *smu)
 241 {
 242         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 243
 244         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_13_0_dpm_context),
 245                                        GFP_KERNEL);
 246         if (!smu_dpm->dpm_context)
 247                 return -ENOMEM;
 248         smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
 249
 250         smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 251                                                    GFP_KERNEL);
 252         if (!smu_dpm->dpm_current_power_state)
 253                 return -ENOMEM;
 254
 255         smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 256                                                    GFP_KERNEL);
 257         if (!smu_dpm->dpm_request_power_state)
 258                 return -ENOMEM;
 259
 260         return 0;
 261 }
 262
 263 static int aldebaran_init_smc_tables(struct smu_context *smu)
 264 {
 265         int ret = 0;
 266
 267         ret = aldebaran_tables_init(smu);
 268         if (ret)
 269                 return ret;
 270
 271         ret = aldebaran_allocate_dpm_context(smu);
 272         if (ret)
 273                 return ret;
 274
 275         return smu_v13_0_init_smc_tables(smu);
 276 }
 277
 278 static int aldebaran_get_allowed_feature_mask(struct smu_context *smu,
 279                                               uint32_t *feature_mask, uint32_t num)
 280 {
 281         if (num > 2)
 282                 return -EINVAL;
 283
 284         /* pptable will handle the features to enable */
 285         memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
 286
 287         return 0;
 288 }
 289
 290 static int aldebaran_set_default_dpm_table(struct smu_context *smu)
 291 {
 292         struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 293         struct smu_13_0_dpm_table *dpm_table = NULL;
 294         PPTable_t *pptable = smu->smu_table.driver_pptable;
 295         int ret = 0;
 296
 297         /* socclk dpm table setup */
 298         dpm_table = &dpm_context->dpm_tables.soc_table;
 299         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 300                 ret = smu_v13_0_set_single_dpm_table(smu,
 301                                                      SMU_SOCCLK,
 302                                                      dpm_table);
 303                 if (ret)
 304                         return ret;
 305         } else {
 306                 dpm_table->count = 1;
 307                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 308                 dpm_table->dpm_levels[0].enabled = true;
 309                 dpm_table->min = dpm_table->dpm_levels[0].value;
 310                 dpm_table->max = dpm_table->dpm_levels[0].value;
 311         }
 312
 313         /* gfxclk dpm table setup */
 314         dpm_table = &dpm_context->dpm_tables.gfx_table;
 315         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 316                 /* in the case of gfxclk, only fine-grained dpm is honored */
 317                 dpm_table->count = 2;
 318                 dpm_table->dpm_levels[0].value = pptable->GfxclkFmin;
 319                 dpm_table->dpm_levels[0].enabled = true;
 320                 dpm_table->dpm_levels[1].value = pptable->GfxclkFmax;
 321                 dpm_table->dpm_levels[1].enabled = true;
 322                 dpm_table->min = dpm_table->dpm_levels[0].value;
 323                 dpm_table->max = dpm_table->dpm_levels[1].value;
 324         } else {
 325                 dpm_table->count = 1;
 326                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 327                 dpm_table->dpm_levels[0].enabled = true;
 328                 dpm_table->min = dpm_table->dpm_levels[0].value;
 329                 dpm_table->max = dpm_table->dpm_levels[0].value;
 330         }
 331
 332         /* memclk dpm table setup */
 333         dpm_table = &dpm_context->dpm_tables.uclk_table;
 334         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 335                 ret = smu_v13_0_set_single_dpm_table(smu,
 336                                                      SMU_UCLK,
 337                                                      dpm_table);
 338                 if (ret)
 339                         return ret;
 340         } else {
 341                 dpm_table->count = 1;
 342                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 343                 dpm_table->dpm_levels[0].enabled = true;
 344                 dpm_table->min = dpm_table->dpm_levels[0].value;
 345                 dpm_table->max = dpm_table->dpm_levels[0].value;
 346         }
 347
 348         /* fclk dpm table setup */
 349         dpm_table = &dpm_context->dpm_tables.fclk_table;
 350         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 351                 ret = smu_v13_0_set_single_dpm_table(smu,
 352                                                      SMU_FCLK,
 353                                                      dpm_table);
 354                 if (ret)
 355                         return ret;
 356         } else {
 357                 dpm_table->count = 1;
 358                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 359                 dpm_table->dpm_levels[0].enabled = true;
 360                 dpm_table->min = dpm_table->dpm_levels[0].value;
 361                 dpm_table->max = dpm_table->dpm_levels[0].value;
 362         }
 363
 364         return 0;
 365 }
 366
 367 static int aldebaran_check_powerplay_table(struct smu_context *smu)
 368 {
 369         struct smu_table_context *table_context = &smu->smu_table;
 370         struct smu_13_0_powerplay_table *powerplay_table =
 371                 table_context->power_play_table;
 372
 373         table_context->thermal_controller_type =
 374                 powerplay_table->thermal_controller_type;
 375
 376         return 0;
 377 }
 378
 379 static int aldebaran_store_powerplay_table(struct smu_context *smu)
 380 {
 381         struct smu_table_context *table_context = &smu->smu_table;
 382         struct smu_13_0_powerplay_table *powerplay_table =
 383                 table_context->power_play_table;
 384         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 385                sizeof(PPTable_t));
 386
 387         return 0;
 388 }
 389
 390 static int aldebaran_append_powerplay_table(struct smu_context *smu)
 391 {
 392         struct smu_table_context *table_context = &smu->smu_table;
 393         PPTable_t *smc_pptable = table_context->driver_pptable;
 394         struct atom_smc_dpm_info_v4_10 *smc_dpm_table;
 395         int index, ret;
 396
 397         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 398                                            smc_dpm_info);
 399
 400         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 401                                       (uint8_t **)&smc_dpm_table);
 402         if (ret)
 403                 return ret;
 404
 405         dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
 406                         smc_dpm_table->table_header.format_revision,
 407                         smc_dpm_table->table_header.content_revision);
 408
 409         if ((smc_dpm_table->table_header.format_revision == 4) &&
 410             (smc_dpm_table->table_header.content_revision == 10))
 411                 memcpy(&smc_pptable->GfxMaxCurrent,
 412                        &smc_dpm_table->GfxMaxCurrent,
 413                        sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_10, GfxMaxCurrent));
 414         return 0;
 415 }
 416
 417 static int aldebaran_setup_pptable(struct smu_context *smu)
 418 {
 419         int ret = 0;
 420
 421         /* VBIOS pptable is the first choice */
 422         smu->smu_table.boot_values.pp_table_id = 0;
 423
 424         ret = smu_v13_0_setup_pptable(smu);
 425         if (ret)
 426                 return ret;
 427
 428         ret = aldebaran_store_powerplay_table(smu);
 429         if (ret)
 430                 return ret;
 431
 432         ret = aldebaran_append_powerplay_table(smu);
 433         if (ret)
 434                 return ret;
 435
 436         ret = aldebaran_check_powerplay_table(smu);
 437         if (ret)
 438                 return ret;
 439
 440         return ret;
 441 }
 442
 443 static int aldebaran_run_btc(struct smu_context *smu)
 444 {
 445         int ret;
 446
 447         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
 448         if (ret)
 449                 dev_err(smu->adev->dev, "RunDcBtc failed!\n");
 450
 451         return ret;
 452 }
 453
 454 static int aldebaran_populate_umd_state_clk(struct smu_context *smu)
 455 {
 456         struct smu_13_0_dpm_context *dpm_context =
 457                 smu->smu_dpm.dpm_context;
 458         struct smu_13_0_dpm_table *gfx_table =
 459                 &dpm_context->dpm_tables.gfx_table;
 460         struct smu_13_0_dpm_table *mem_table =
 461                 &dpm_context->dpm_tables.uclk_table;
 462         struct smu_13_0_dpm_table *soc_table =
 463                 &dpm_context->dpm_tables.soc_table;
 464         struct smu_umd_pstate_table *pstate_table =
 465                 &smu->pstate_table;
 466
 467         pstate_table->gfxclk_pstate.min = gfx_table->min;
 468         pstate_table->gfxclk_pstate.peak = gfx_table->max;
 469         pstate_table->gfxclk_pstate.curr.min = gfx_table->min;
 470         pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
 471
 472         pstate_table->uclk_pstate.min = mem_table->min;
 473         pstate_table->uclk_pstate.peak = mem_table->max;
 474         pstate_table->uclk_pstate.curr.min = mem_table->min;
 475         pstate_table->uclk_pstate.curr.max = mem_table->max;
 476
 477         pstate_table->socclk_pstate.min = soc_table->min;
 478         pstate_table->socclk_pstate.peak = soc_table->max;
 479         pstate_table->socclk_pstate.curr.min = soc_table->min;
 480         pstate_table->socclk_pstate.curr.max = soc_table->max;
 481
 482         if (gfx_table->count > ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL &&
 483             mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL &&
 484             soc_table->count > ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL) {
 485                 pstate_table->gfxclk_pstate.standard =
 486                         gfx_table->dpm_levels[ALDEBARAN_UMD_PSTATE_GFXCLK_LEVEL].value;
 487                 pstate_table->uclk_pstate.standard =
 488                         mem_table->dpm_levels[ALDEBARAN_UMD_PSTATE_MCLK_LEVEL].value;
 489                 pstate_table->socclk_pstate.standard =
 490                         soc_table->dpm_levels[ALDEBARAN_UMD_PSTATE_SOCCLK_LEVEL].value;
 491         } else {
 492                 pstate_table->gfxclk_pstate.standard =
 493                         pstate_table->gfxclk_pstate.min;
 494                 pstate_table->uclk_pstate.standard =
 495                         pstate_table->uclk_pstate.min;
 496                 pstate_table->socclk_pstate.standard =
 497                         pstate_table->socclk_pstate.min;
 498         }
 499
 500         return 0;
 501 }
 502
 503 static int aldebaran_get_clk_table(struct smu_context *smu,
 504                                    struct pp_clock_levels_with_latency *clocks,
 505                                    struct smu_13_0_dpm_table *dpm_table)
 506 {
 507         int i, count;
 508
 509         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 510         clocks->num_levels = count;
 511
 512         for (i = 0; i < count; i++) {
 513                 clocks->data[i].clocks_in_khz =
 514                         dpm_table->dpm_levels[i].value * 1000;
 515                 clocks->data[i].latency_in_us = 0;
 516         }
 517
 518         return 0;
 519 }
 520
 521 static int aldebaran_freqs_in_same_level(int32_t frequency1,
 522                                          int32_t frequency2)
 523 {
 524         return (abs(frequency1 - frequency2) <= EPSILON);
 525 }
 526
 527 static bool aldebaran_is_primary(struct smu_context *smu)
 528 {
 529         struct amdgpu_device *adev = smu->adev;
 530
 531         if (adev->smuio.funcs && adev->smuio.funcs->get_die_id)
 532                 return adev->smuio.funcs->get_die_id(adev) == 0;
 533
 534         return true;
 535 }
 536
 537 static int aldebaran_get_smu_metrics_data(struct smu_context *smu,
 538                                           MetricsMember_t member,
 539                                           uint32_t *value)
 540 {
 541         struct smu_table_context *smu_table= &smu->smu_table;
 542         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 543         int ret = 0;
 544
 545         mutex_lock(&smu->metrics_lock);
 546
 547         ret = smu_cmn_get_metrics_table_locked(smu,
 548                                                NULL,
 549                                                false);
 550         if (ret) {
 551                 mutex_unlock(&smu->metrics_lock);
 552                 return ret;
 553         }
 554
 555         switch (member) {
 556         case METRICS_CURR_GFXCLK:
 557                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 558                 break;
 559         case METRICS_CURR_SOCCLK:
 560                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 561                 break;
 562         case METRICS_CURR_UCLK:
 563                 *value = metrics->CurrClock[PPCLK_UCLK];
 564                 break;
 565         case METRICS_CURR_VCLK:
 566                 *value = metrics->CurrClock[PPCLK_VCLK];
 567                 break;
 568         case METRICS_CURR_DCLK:
 569                 *value = metrics->CurrClock[PPCLK_DCLK];
 570                 break;
 571         case METRICS_CURR_FCLK:
 572                 *value = metrics->CurrClock[PPCLK_FCLK];
 573                 break;
 574         case METRICS_AVERAGE_GFXCLK:
 575                 *value = metrics->AverageGfxclkFrequency;
 576                 break;
 577         case METRICS_AVERAGE_SOCCLK:
 578                 *value = metrics->AverageSocclkFrequency;
 579                 break;
 580         case METRICS_AVERAGE_UCLK:
 581                 *value = metrics->AverageUclkFrequency;
 582                 break;
 583         case METRICS_AVERAGE_GFXACTIVITY:
 584                 *value = metrics->AverageGfxActivity;
 585                 break;
 586         case METRICS_AVERAGE_MEMACTIVITY:
 587                 *value = metrics->AverageUclkActivity;
 588                 break;
 589         case METRICS_AVERAGE_SOCKETPOWER:
 590                 /* Valid power data is available only from primary die */
 591                 *value = aldebaran_is_primary(smu) ?
 592                                  metrics->AverageSocketPower << 8 :
 593                                  0;
 594                 break;
 595         case METRICS_TEMPERATURE_EDGE:
 596                 *value = metrics->TemperatureEdge *
 597                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 598                 break;
 599         case METRICS_TEMPERATURE_HOTSPOT:
 600                 *value = metrics->TemperatureHotspot *
 601                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 602                 break;
 603         case METRICS_TEMPERATURE_MEM:
 604                 *value = metrics->TemperatureHBM *
 605                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 606                 break;
 607         case METRICS_TEMPERATURE_VRGFX:
 608                 *value = metrics->TemperatureVrGfx *
 609                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 610                 break;
 611         case METRICS_TEMPERATURE_VRSOC:
 612                 *value = metrics->TemperatureVrSoc *
 613                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 614                 break;
 615         case METRICS_TEMPERATURE_VRMEM:
 616                 *value = metrics->TemperatureVrMem *
 617                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 618                 break;
 619         case METRICS_THROTTLER_STATUS:
 620                 *value = metrics->ThrottlerStatus;
 621                 break;
 622         default:
 623                 *value = UINT_MAX;
 624                 break;
 625         }
 626
 627         mutex_unlock(&smu->metrics_lock);
 628
 629         return ret;
 630 }
 631
 632 static int aldebaran_get_current_clk_freq_by_table(struct smu_context *smu,
 633                                                    enum smu_clk_type clk_type,
 634                                                    uint32_t *value)
 635 {
 636         MetricsMember_t member_type;
 637         int clk_id = 0;
 638
 639         if (!value)
 640                 return -EINVAL;
 641
 642         clk_id = smu_cmn_to_asic_specific_index(smu,
 643                                                 CMN2ASIC_MAPPING_CLK,
 644                                                 clk_type);
 645         if (clk_id < 0)
 646                 return -EINVAL;
 647
 648         switch (clk_id) {
 649         case PPCLK_GFXCLK:
 650                 /*
 651                  * CurrClock[clk_id] can provide accurate
 652                  *   output only when the dpm feature is enabled.
 653                  * We can use Average_* for dpm disabled case.
 654                  *   But this is available for gfxclk/uclk/socclk/vclk/dclk.
 655                  */
 656                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
 657                         member_type = METRICS_CURR_GFXCLK;
 658                 else
 659                         member_type = METRICS_AVERAGE_GFXCLK;
 660                 break;
 661         case PPCLK_UCLK:
 662                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
 663                         member_type = METRICS_CURR_UCLK;
 664                 else
 665                         member_type = METRICS_AVERAGE_UCLK;
 666                 break;
 667         case PPCLK_SOCCLK:
 668                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
 669                         member_type = METRICS_CURR_SOCCLK;
 670                 else
 671                         member_type = METRICS_AVERAGE_SOCCLK;
 672                 break;
 673         case PPCLK_VCLK:
 674                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
 675                         member_type = METRICS_CURR_VCLK;
 676                 else
 677                         member_type = METRICS_AVERAGE_VCLK;
 678                 break;
 679         case PPCLK_DCLK:
 680                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
 681                         member_type = METRICS_CURR_DCLK;
 682                 else
 683                         member_type = METRICS_AVERAGE_DCLK;
 684                 break;
 685         case PPCLK_FCLK:
 686                 member_type = METRICS_CURR_FCLK;
 687                 break;
 688         default:
 689                 return -EINVAL;
 690         }
 691
 692         return aldebaran_get_smu_metrics_data(smu,
 693                                               member_type,
 694                                               value);
 695 }
 696
 697 static int aldebaran_print_clk_levels(struct smu_context *smu,
 698                                       enum smu_clk_type type, char *buf)
 699 {
 700         int i, now, size = 0;
 701         int ret = 0;
 702         struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
 703         struct pp_clock_levels_with_latency clocks;
 704         struct smu_13_0_dpm_table *single_dpm_table;
 705         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 706         struct smu_13_0_dpm_context *dpm_context = NULL;
 707         uint32_t display_levels;
 708         uint32_t freq_values[3] = {0};
 709         uint32_t min_clk, max_clk;
 710
 711         if (amdgpu_ras_intr_triggered())
 712                 return snprintf(buf, PAGE_SIZE, "unavailable\n");
 713
 714         dpm_context = smu_dpm->dpm_context;
 715
 716         switch (type) {
 717
 718         case SMU_OD_SCLK:
 719                 size = sprintf(buf, "%s:\n", "GFXCLK");
 720                 fallthrough;
 721         case SMU_SCLK:
 722                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now);
 723                 if (ret) {
 724                         dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!");
 725                         return ret;
 726                 }
 727
 728                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 729                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 730                 if (ret) {
 731                         dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
 732                         return ret;
 733                 }
 734
 735                 display_levels = clocks.num_levels;
 736
 737                 min_clk = pstate_table->gfxclk_pstate.curr.min;
 738                 max_clk = pstate_table->gfxclk_pstate.curr.max;
 739
 740                 freq_values[0] = min_clk;
 741                 freq_values[1] = max_clk;
 742
 743                 /* fine-grained dpm has only 2 levels */
 744                 if (now > min_clk && now < max_clk) {
 745                         display_levels = clocks.num_levels + 1;
 746                         freq_values[2] = max_clk;
 747                         freq_values[1] = now;
 748                 }
 749
 750                 /*
 751                  * For DPM disabled case, there will be only one clock level.
 752                  * And it's safe to assume that is always the current clock.
 753                  */
 754                 if (display_levels == clocks.num_levels) {
 755                         for (i = 0; i < clocks.num_levels; i++)
 756                                 size += sprintf(
 757                                         buf + size, "%d: %uMhz %s\n", i,
 758                                         freq_values[i],
 759                                         (clocks.num_levels == 1) ?
 760                                                 "*" :
 761                                                 (aldebaran_freqs_in_same_level(
 762                                                          freq_values[i], now) ?
 763                                                          "*" :
 764                                                          ""));
 765                 } else {
 766                         for (i = 0; i < display_levels; i++)
 767                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i,
 768                                                 freq_values[i], i == 1 ? "*" : "");
 769                 }
 770
 771                 break;
 772
 773         case SMU_OD_MCLK:
 774                 size = sprintf(buf, "%s:\n", "MCLK");
 775                 fallthrough;
 776         case SMU_MCLK:
 777                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, &now);
 778                 if (ret) {
 779                         dev_err(smu->adev->dev, "Attempt to get current mclk Failed!");
 780                         return ret;
 781                 }
 782
 783                 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
 784                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 785                 if (ret) {
 786                         dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
 787                         return ret;
 788                 }
 789
 790                 for (i = 0; i < clocks.num_levels; i++)
 791                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 792                                         i, clocks.data[i].clocks_in_khz / 1000,
 793                                         (clocks.num_levels == 1) ? "*" :
 794                                         (aldebaran_freqs_in_same_level(
 795                                                                        clocks.data[i].clocks_in_khz / 1000,
 796                                                                        now) ? "*" : ""));
 797                 break;
 798
 799         case SMU_SOCCLK:
 800                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now);
 801                 if (ret) {
 802                         dev_err(smu->adev->dev, "Attempt to get current socclk Failed!");
 803                         return ret;
 804                 }
 805
 806                 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
 807                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 808                 if (ret) {
 809                         dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
 810                         return ret;
 811                 }
 812
 813                 for (i = 0; i < clocks.num_levels; i++)
 814                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 815                                         i, clocks.data[i].clocks_in_khz / 1000,
 816                                         (clocks.num_levels == 1) ? "*" :
 817                                         (aldebaran_freqs_in_same_level(
 818                                                                        clocks.data[i].clocks_in_khz / 1000,
 819                                                                        now) ? "*" : ""));
 820                 break;
 821
 822         case SMU_FCLK:
 823                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_FCLK, &now);
 824                 if (ret) {
 825                         dev_err(smu->adev->dev, "Attempt to get current fclk Failed!");
 826                         return ret;
 827                 }
 828
 829                 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
 830                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 831                 if (ret) {
 832                         dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
 833                         return ret;
 834                 }
 835
 836                 for (i = 0; i < single_dpm_table->count; i++)
 837                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 838                                         i, single_dpm_table->dpm_levels[i].value,
 839                                         (clocks.num_levels == 1) ? "*" :
 840                                         (aldebaran_freqs_in_same_level(
 841                                                                        clocks.data[i].clocks_in_khz / 1000,
 842                                                                        now) ? "*" : ""));
 843                 break;
 844
 845         case SMU_VCLK:
 846                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_VCLK, &now);
 847                 if (ret) {
 848                         dev_err(smu->adev->dev, "Attempt to get current vclk Failed!");
 849                         return ret;
 850                 }
 851
 852                 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
 853                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 854                 if (ret) {
 855                         dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!");
 856                         return ret;
 857                 }
 858
 859                 for (i = 0; i < single_dpm_table->count; i++)
 860                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 861                                         i, single_dpm_table->dpm_levels[i].value,
 862                                         (clocks.num_levels == 1) ? "*" :
 863                                         (aldebaran_freqs_in_same_level(
 864                                                                        clocks.data[i].clocks_in_khz / 1000,
 865                                                                        now) ? "*" : ""));
 866                 break;
 867
 868         case SMU_DCLK:
 869                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_DCLK, &now);
 870                 if (ret) {
 871                         dev_err(smu->adev->dev, "Attempt to get current dclk Failed!");
 872                         return ret;
 873                 }
 874
 875                 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
 876                 ret = aldebaran_get_clk_table(smu, &clocks, single_dpm_table);
 877                 if (ret) {
 878                         dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!");
 879                         return ret;
 880                 }
 881
 882                 for (i = 0; i < single_dpm_table->count; i++)
 883                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 884                                         i, single_dpm_table->dpm_levels[i].value,
 885                                         (clocks.num_levels == 1) ? "*" :
 886                                         (aldebaran_freqs_in_same_level(
 887                                                                        clocks.data[i].clocks_in_khz / 1000,
 888                                                                        now) ? "*" : ""));
 889                 break;
 890
 891         default:
 892                 break;
 893         }
 894
 895         return size;
 896 }
 897
 898 static int aldebaran_upload_dpm_level(struct smu_context *smu,
 899                                       bool max,
 900                                       uint32_t feature_mask,
 901                                       uint32_t level)
 902 {
 903         struct smu_13_0_dpm_context *dpm_context =
 904                 smu->smu_dpm.dpm_context;
 905         uint32_t freq;
 906         int ret = 0;
 907
 908         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
 909             (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT))) {
 910                 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
 911                 ret = smu_cmn_send_smc_msg_with_param(smu,
 912                                                       (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 913                                                       (PPCLK_GFXCLK << 16) | (freq & 0xffff),
 914                                                       NULL);
 915                 if (ret) {
 916                         dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
 917                                 max ? "max" : "min");
 918                         return ret;
 919                 }
 920         }
 921
 922         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 923             (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK_BIT))) {
 924                 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
 925                 ret = smu_cmn_send_smc_msg_with_param(smu,
 926                                                       (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 927                                                       (PPCLK_UCLK << 16) | (freq & 0xffff),
 928                                                       NULL);
 929                 if (ret) {
 930                         dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
 931                                 max ? "max" : "min");
 932                         return ret;
 933                 }
 934         }
 935
 936         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
 937             (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT))) {
 938                 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
 939                 ret = smu_cmn_send_smc_msg_with_param(smu,
 940                                                       (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 941                                                       (PPCLK_SOCCLK << 16) | (freq & 0xffff),
 942                                                       NULL);
 943                 if (ret) {
 944                         dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
 945                                 max ? "max" : "min");
 946                         return ret;
 947                 }
 948         }
 949
 950         return ret;
 951 }
 952
 953 static int aldebaran_force_clk_levels(struct smu_context *smu,
 954                                       enum smu_clk_type type, uint32_t mask)
 955 {
 956         struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 957         struct smu_13_0_dpm_table *single_dpm_table = NULL;
 958         uint32_t soft_min_level, soft_max_level;
 959         int ret = 0;
 960
 961         soft_min_level = mask ? (ffs(mask) - 1) : 0;
 962         soft_max_level = mask ? (fls(mask) - 1) : 0;
 963
 964         switch (type) {
 965         case SMU_SCLK:
 966                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 967                 if (soft_max_level >= single_dpm_table->count) {
 968                         dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
 969                                 soft_max_level, single_dpm_table->count - 1);
 970                         ret = -EINVAL;
 971                         break;
 972                 }
 973
 974                 ret = aldebaran_upload_dpm_level(smu,
 975                                                  false,
 976                                                  FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT),
 977                                                  soft_min_level);
 978                 if (ret) {
 979                         dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
 980                         break;
 981                 }
 982
 983                 ret = aldebaran_upload_dpm_level(smu,
 984                                                  true,
 985                                                  FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT),
 986                                                  soft_max_level);
 987                 if (ret)
 988                         dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
 989
 990                 break;
 991
 992         case SMU_MCLK:
 993         case SMU_SOCCLK:
 994         case SMU_FCLK:
 995                 /*
 996                  * Should not arrive here since aldebaran does not
 997                  * support mclk/socclk/fclk softmin/softmax settings
 998                  */
 999                 ret = -EINVAL;
1000                 break;
1001
1002         default:
1003                 break;
1004         }
1005
1006         return ret;
1007 }
1008
1009 static int aldebaran_get_thermal_temperature_range(struct smu_context *smu,
1010                                                    struct smu_temperature_range *range)
1011 {
1012         struct smu_table_context *table_context = &smu->smu_table;
1013         struct smu_13_0_powerplay_table *powerplay_table =
1014                 table_context->power_play_table;
1015         PPTable_t *pptable = smu->smu_table.driver_pptable;
1016
1017         if (!range)
1018                 return -EINVAL;
1019
1020         memcpy(range, &smu13_thermal_policy[0], sizeof(struct smu_temperature_range));
1021
1022         range->hotspot_crit_max = pptable->ThotspotLimit *
1023                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1024         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1025                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1026         range->mem_crit_max = pptable->TmemLimit *
1027                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1028         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
1029                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1030         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1031
1032         return 0;
1033 }
1034
1035 static int aldebaran_get_current_activity_percent(struct smu_context *smu,
1036                                                   enum amd_pp_sensors sensor,
1037                                                   uint32_t *value)
1038 {
1039         int ret = 0;
1040
1041         if (!value)
1042                 return -EINVAL;
1043
1044         switch (sensor) {
1045         case AMDGPU_PP_SENSOR_GPU_LOAD:
1046                 ret = aldebaran_get_smu_metrics_data(smu,
1047                                                      METRICS_AVERAGE_GFXACTIVITY,
1048                                                      value);
1049                 break;
1050         case AMDGPU_PP_SENSOR_MEM_LOAD:
1051                 ret = aldebaran_get_smu_metrics_data(smu,
1052                                                      METRICS_AVERAGE_MEMACTIVITY,
1053                                                      value);
1054                 break;
1055         default:
1056                 dev_err(smu->adev->dev, "Invalid sensor for retrieving clock activity\n");
1057                 return -EINVAL;
1058         }
1059
1060         return ret;
1061 }
1062
1063 static int aldebaran_get_gpu_power(struct smu_context *smu, uint32_t *value)
1064 {
1065         if (!value)
1066                 return -EINVAL;
1067
1068         return aldebaran_get_smu_metrics_data(smu,
1069                                               METRICS_AVERAGE_SOCKETPOWER,
1070                                               value);
1071 }
1072
1073 static int aldebaran_thermal_get_temperature(struct smu_context *smu,
1074                                              enum amd_pp_sensors sensor,
1075                                              uint32_t *value)
1076 {
1077         int ret = 0;
1078
1079         if (!value)
1080                 return -EINVAL;
1081
1082         switch (sensor) {
1083         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1084                 ret = aldebaran_get_smu_metrics_data(smu,
1085                                                      METRICS_TEMPERATURE_HOTSPOT,
1086                                                      value);
1087                 break;
1088         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1089                 ret = aldebaran_get_smu_metrics_data(smu,
1090                                                      METRICS_TEMPERATURE_EDGE,
1091                                                      value);
1092                 break;
1093         case AMDGPU_PP_SENSOR_MEM_TEMP:
1094                 ret = aldebaran_get_smu_metrics_data(smu,
1095                                                      METRICS_TEMPERATURE_MEM,
1096                                                      value);
1097                 break;
1098         default:
1099                 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1100                 return -EINVAL;
1101         }
1102
1103         return ret;
1104 }
1105
1106 static int aldebaran_read_sensor(struct smu_context *smu,
1107                                  enum amd_pp_sensors sensor,
1108                                  void *data, uint32_t *size)
1109 {
1110         int ret = 0;
1111
1112         if (amdgpu_ras_intr_triggered())
1113                 return 0;
1114
1115         if (!data || !size)
1116                 return -EINVAL;
1117
1118         mutex_lock(&smu->sensor_lock);
1119         switch (sensor) {
1120         case AMDGPU_PP_SENSOR_MEM_LOAD:
1121         case AMDGPU_PP_SENSOR_GPU_LOAD:
1122                 ret = aldebaran_get_current_activity_percent(smu,
1123                                                              sensor,
1124                                                              (uint32_t *)data);
1125                 *size = 4;
1126                 break;
1127         case AMDGPU_PP_SENSOR_GPU_POWER:
1128                 ret = aldebaran_get_gpu_power(smu, (uint32_t *)data);
1129                 *size = 4;
1130                 break;
1131         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1132         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1133         case AMDGPU_PP_SENSOR_MEM_TEMP:
1134                 ret = aldebaran_thermal_get_temperature(smu, sensor,
1135                                                         (uint32_t *)data);
1136                 *size = 4;
1137                 break;
1138         case AMDGPU_PP_SENSOR_GFX_MCLK:
1139                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1140                 /* the output clock frequency in 10K unit */
1141                 *(uint32_t *)data *= 100;
1142                 *size = 4;
1143                 break;
1144         case AMDGPU_PP_SENSOR_GFX_SCLK:
1145                 ret = aldebaran_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1146                 *(uint32_t *)data *= 100;
1147                 *size = 4;
1148                 break;
1149         case AMDGPU_PP_SENSOR_VDDGFX:
1150                 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data);
1151                 *size = 4;
1152                 break;
1153         default:
1154                 ret = -EOPNOTSUPP;
1155                 break;
1156         }
1157         mutex_unlock(&smu->sensor_lock);
1158
1159         return ret;
1160 }
1161
1162 static int aldebaran_get_power_limit(struct smu_context *smu,
1163                                      uint32_t *current_power_limit,
1164                                      uint32_t *default_power_limit,
1165                                      uint32_t *max_power_limit)
1166 {
1167         PPTable_t *pptable = smu->smu_table.driver_pptable;
1168         uint32_t power_limit = 0;
1169         int ret;
1170
1171         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
1172                 return -EINVAL;
1173
1174         /* Valid power data is available only from primary die.
1175          * For secondary die show the value as 0.
1176          */
1177         if (aldebaran_is_primary(smu)) {
1178                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit,
1179                                            &power_limit);
1180
1181                 if (ret) {
1182                         /* the last hope to figure out the ppt limit */
1183                         if (!pptable) {
1184                                 dev_err(smu->adev->dev,
1185                                         "Cannot get PPT limit due to pptable missing!");
1186                                 return -EINVAL;
1187                         }
1188                         power_limit = pptable->PptLimit;
1189                 }
1190         }
1191
1192         if (current_power_limit)
1193                 *current_power_limit = power_limit;
1194         if (default_power_limit)
1195                 *default_power_limit = power_limit;
1196
1197         if (max_power_limit) {
1198                 if (pptable)
1199                         *max_power_limit = pptable->PptLimit;
1200         }
1201
1202         return 0;
1203 }
1204
1205 static int aldebaran_set_power_limit(struct smu_context *smu, uint32_t n)
1206 {
1207         /* Power limit can be set only through primary die */
1208         if (aldebaran_is_primary(smu))
1209                 return smu_v13_0_set_power_limit(smu, n);
1210
1211         return -EINVAL;
1212 }
1213
1214 static int aldebaran_system_features_control(struct  smu_context *smu, bool enable)
1215 {
1216         int ret;
1217
1218         ret = smu_v13_0_system_features_control(smu, enable);
1219         if (!ret && enable)
1220                 ret = aldebaran_run_btc(smu);
1221
1222         return ret;
1223 }
1224
1225 static int aldebaran_set_performance_level(struct smu_context *smu,
1226                                            enum amd_dpm_forced_level level)
1227 {
1228         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1229         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1230         struct smu_13_0_dpm_table *gfx_table =
1231                 &dpm_context->dpm_tables.gfx_table;
1232         struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1233
1234         /* Disable determinism if switching to another mode */
1235         if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) &&
1236             (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) {
1237                 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL);
1238                 pstate_table->gfxclk_pstate.curr.max = gfx_table->max;
1239         }
1240
1241         switch (level) {
1242
1243         case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM:
1244                 return 0;
1245
1246         case AMD_DPM_FORCED_LEVEL_HIGH:
1247         case AMD_DPM_FORCED_LEVEL_LOW:
1248         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1249         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1250         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1251         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1252         default:
1253                 break;
1254         }
1255
1256         return smu_v13_0_set_performance_level(smu, level);
1257 }
1258
1259 static int aldebaran_set_soft_freq_limited_range(struct smu_context *smu,
1260                                           enum smu_clk_type clk_type,
1261                                           uint32_t min,
1262                                           uint32_t max)
1263 {
1264         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1265         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1266         struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1267         struct amdgpu_device *adev = smu->adev;
1268         uint32_t min_clk;
1269         uint32_t max_clk;
1270         int ret = 0;
1271
1272         if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK)
1273                 return -EINVAL;
1274
1275         if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1276                         && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1277                 return -EINVAL;
1278
1279         if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
1280                 if (min >= max) {
1281                         dev_err(smu->adev->dev,
1282                                 "Minimum GFX clk should be less than the maximum allowed clock\n");
1283                         return -EINVAL;
1284                 }
1285
1286                 if ((min == pstate_table->gfxclk_pstate.curr.min) &&
1287                     (max == pstate_table->gfxclk_pstate.curr.max))
1288                         return 0;
1289
1290                 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK,
1291                                                             min, max);
1292                 if (!ret) {
1293                         pstate_table->gfxclk_pstate.curr.min = min;
1294                         pstate_table->gfxclk_pstate.curr.max = max;
1295                 }
1296
1297                 return ret;
1298         }
1299
1300         if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1301                 if (!max || (max < dpm_context->dpm_tables.gfx_table.min) ||
1302                         (max > dpm_context->dpm_tables.gfx_table.max)) {
1303                         dev_warn(adev->dev,
1304                                         "Invalid max frequency %d MHz specified for determinism\n", max);
1305                         return -EINVAL;
1306                 }
1307
1308                 /* Restore default min/max clocks and enable determinism */
1309                 min_clk = dpm_context->dpm_tables.gfx_table.min;
1310                 max_clk = dpm_context->dpm_tables.gfx_table.max;
1311                 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1312                 if (!ret) {
1313                         usleep_range(500, 1000);
1314                         ret = smu_cmn_send_smc_msg_with_param(smu,
1315                                         SMU_MSG_EnableDeterminism,
1316                                         max, NULL);
1317                         if (ret) {
1318                                 dev_err(adev->dev,
1319                                                 "Failed to enable determinism at GFX clock %d MHz\n", max);
1320                         } else {
1321                                 pstate_table->gfxclk_pstate.curr.min = min_clk;
1322                                 pstate_table->gfxclk_pstate.curr.max = max;
1323                         }
1324                 }
1325         }
1326
1327         return ret;
1328 }
1329
1330 static int aldebaran_usr_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
1331                                                         long input[], uint32_t size)
1332 {
1333         struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1334         struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1335         struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1336         uint32_t min_clk;
1337         uint32_t max_clk;
1338         int ret = 0;
1339
1340         /* Only allowed in manual or determinism mode */
1341         if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL)
1342                         && (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
1343                 return -EINVAL;
1344
1345         switch (type) {
1346         case PP_OD_EDIT_SCLK_VDDC_TABLE:
1347                 if (size != 2) {
1348                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1349                         return -EINVAL;
1350                 }
1351
1352                 if (input[0] == 0) {
1353                         if (input[1] < dpm_context->dpm_tables.gfx_table.min) {
1354                                 dev_warn(smu->adev->dev, "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n",
1355                                         input[1], dpm_context->dpm_tables.gfx_table.min);
1356                                 pstate_table->gfxclk_pstate.custom.min =
1357                                         pstate_table->gfxclk_pstate.curr.min;
1358                                 return -EINVAL;
1359                         }
1360
1361                         pstate_table->gfxclk_pstate.custom.min = input[1];
1362                 } else if (input[0] == 1) {
1363                         if (input[1] > dpm_context->dpm_tables.gfx_table.max) {
1364                                 dev_warn(smu->adev->dev, "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
1365                                         input[1], dpm_context->dpm_tables.gfx_table.max);
1366                                 pstate_table->gfxclk_pstate.custom.max =
1367                                         pstate_table->gfxclk_pstate.curr.max;
1368                                 return -EINVAL;
1369                         }
1370
1371                         pstate_table->gfxclk_pstate.custom.max = input[1];
1372                 } else {
1373                         return -EINVAL;
1374                 }
1375                 break;
1376         case PP_OD_RESTORE_DEFAULT_TABLE:
1377                 if (size != 0) {
1378                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1379                         return -EINVAL;
1380                 } else {
1381                         /* Use the default frequencies for manual and determinism mode */
1382                         min_clk = dpm_context->dpm_tables.gfx_table.min;
1383                         max_clk = dpm_context->dpm_tables.gfx_table.max;
1384
1385                         return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1386                 }
1387                 break;
1388         case PP_OD_COMMIT_DPM_TABLE:
1389                 if (size != 0) {
1390                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
1391                         return -EINVAL;
1392                 } else {
1393                         if (!pstate_table->gfxclk_pstate.custom.min)
1394                                 pstate_table->gfxclk_pstate.custom.min =
1395                                         pstate_table->gfxclk_pstate.curr.min;
1396
1397                         if (!pstate_table->gfxclk_pstate.custom.max)
1398                                 pstate_table->gfxclk_pstate.custom.max =
1399                                         pstate_table->gfxclk_pstate.curr.max;
1400
1401                         min_clk = pstate_table->gfxclk_pstate.custom.min;
1402                         max_clk = pstate_table->gfxclk_pstate.custom.max;
1403
1404                         return aldebaran_set_soft_freq_limited_range(smu, SMU_GFXCLK, min_clk, max_clk);
1405                 }
1406                 break;
1407         default:
1408                 return -ENOSYS;
1409         }
1410
1411         return ret;
1412 }
1413
1414 static bool aldebaran_is_dpm_running(struct smu_context *smu)
1415 {
1416         int ret;
1417         uint32_t feature_mask[2];
1418         unsigned long feature_enabled;
1419
1420         ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1421         if (ret)
1422                 return false;
1423         feature_enabled = (unsigned long)((uint64_t)feature_mask[0] |
1424                                           ((uint64_t)feature_mask[1] << 32));
1425         return !!(feature_enabled & SMC_DPM_FEATURE);
1426 }
1427
1428 static void aldebaran_fill_i2c_req(SwI2cRequest_t  *req, bool write,
1429                                   uint8_t address, uint32_t numbytes,
1430                                   uint8_t *data)
1431 {
1432         int i;
1433
1434         req->I2CcontrollerPort = 0;
1435         req->I2CSpeed = 2;
1436         req->SlaveAddress = address;
1437         req->NumCmds = numbytes;
1438
1439         for (i = 0; i < numbytes; i++) {
1440                 SwI2cCmd_t *cmd =  &req->SwI2cCmds[i];
1441
1442                 /* First 2 bytes are always write for lower 2b EEPROM address */
1443                 if (i < 2)
1444                         cmd->CmdConfig = CMDCONFIG_READWRITE_MASK;
1445                 else
1446                         cmd->CmdConfig = write ? CMDCONFIG_READWRITE_MASK : 0;
1447
1448
1449                 /* Add RESTART for read  after address filled */
1450                 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
1451
1452                 /* Add STOP in the end */
1453                 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
1454
1455                 /* Fill with data regardless if read or write to simplify code */
1456                 cmd->ReadWriteData = data[i];
1457         }
1458 }
1459
1460 static int aldebaran_i2c_read_data(struct i2c_adapter *control,
1461                                                uint8_t address,
1462                                                uint8_t *data,
1463                                                uint32_t numbytes)
1464 {
1465         uint32_t  i, ret = 0;
1466         SwI2cRequest_t req;
1467         struct amdgpu_device *adev = to_amdgpu_device(control);
1468         struct smu_table_context *smu_table = &adev->smu.smu_table;
1469         struct smu_table *table = &smu_table->driver_table;
1470
1471         if (numbytes > MAX_SW_I2C_COMMANDS) {
1472                 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
1473                         numbytes, MAX_SW_I2C_COMMANDS);
1474                 return -EINVAL;
1475         }
1476
1477         memset(&req, 0, sizeof(req));
1478         aldebaran_fill_i2c_req(&req, false, address, numbytes, data);
1479
1480         mutex_lock(&adev->smu.mutex);
1481         /* Now read data starting with that address */
1482         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
1483                                         true);
1484         mutex_unlock(&adev->smu.mutex);
1485
1486         if (!ret) {
1487                 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
1488
1489                 /* Assume SMU  fills res.SwI2cCmds[i].Data with read bytes */
1490                 for (i = 0; i < numbytes; i++)
1491                         data[i] = res->SwI2cCmds[i].ReadWriteData;
1492
1493                 dev_dbg(adev->dev, "aldebaran_i2c_read_data, address = %x, bytes = %d, data :",
1494                                   (uint16_t)address, numbytes);
1495
1496                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
1497                                8, 1, data, numbytes, false);
1498         } else
1499                 dev_err(adev->dev, "aldebaran_i2c_read_data - error occurred :%x", ret);
1500
1501         return ret;
1502 }
1503
1504 static int aldebaran_i2c_write_data(struct i2c_adapter *control,
1505                                                 uint8_t address,
1506                                                 uint8_t *data,
1507                                                 uint32_t numbytes)
1508 {
1509         uint32_t ret;
1510         SwI2cRequest_t req;
1511         struct amdgpu_device *adev = to_amdgpu_device(control);
1512
1513         if (numbytes > MAX_SW_I2C_COMMANDS) {
1514                 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
1515                         numbytes, MAX_SW_I2C_COMMANDS);
1516                 return -EINVAL;
1517         }
1518
1519         memset(&req, 0, sizeof(req));
1520         aldebaran_fill_i2c_req(&req, true, address, numbytes, data);
1521
1522         mutex_lock(&adev->smu.mutex);
1523         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
1524         mutex_unlock(&adev->smu.mutex);
1525
1526         if (!ret) {
1527                 dev_dbg(adev->dev, "aldebaran_i2c_write(), address = %x, bytes = %d , data: ",
1528                                          (uint16_t)address, numbytes);
1529
1530                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
1531                                8, 1, data, numbytes, false);
1532                 /*
1533                  * According to EEPROM spec there is a MAX of 10 ms required for
1534                  * EEPROM to flush internal RX buffer after STOP was issued at the
1535                  * end of write transaction. During this time the EEPROM will not be
1536                  * responsive to any more commands - so wait a bit more.
1537                  */
1538                 msleep(10);
1539
1540         } else
1541                 dev_err(adev->dev, "aldebaran_i2c_write- error occurred :%x", ret);
1542
1543         return ret;
1544 }
1545
1546 static int aldebaran_i2c_xfer(struct i2c_adapter *i2c_adap,
1547                               struct i2c_msg *msgs, int num)
1548 {
1549         uint32_t  i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
1550         uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
1551
1552         for (i = 0; i < num; i++) {
1553                 /*
1554                  * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
1555                  * once and hence the data needs to be spliced into chunks and sent each
1556                  * chunk separately
1557                  */
1558                 data_size = msgs[i].len - 2;
1559                 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
1560                 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
1561                 data_ptr = msgs[i].buf + 2;
1562
1563                 for (j = 0; j < data_size / data_chunk_size; j++) {
1564                         /* Insert the EEPROM dest addess, bits 0-15 */
1565                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
1566                         data_chunk[1] = (next_eeprom_addr & 0xff);
1567
1568                         if (msgs[i].flags & I2C_M_RD) {
1569                                 ret = aldebaran_i2c_read_data(i2c_adap,
1570                                                              (uint8_t)msgs[i].addr,
1571                                                              data_chunk, MAX_SW_I2C_COMMANDS);
1572
1573                                 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
1574                         } else {
1575
1576                                 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
1577
1578                                 ret = aldebaran_i2c_write_data(i2c_adap,
1579                                                               (uint8_t)msgs[i].addr,
1580                                                               data_chunk, MAX_SW_I2C_COMMANDS);
1581                         }
1582
1583                         if (ret) {
1584                                 num = -EIO;
1585                                 goto fail;
1586                         }
1587
1588                         next_eeprom_addr += data_chunk_size;
1589                         data_ptr += data_chunk_size;
1590                 }
1591
1592                 if (data_size % data_chunk_size) {
1593                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
1594                         data_chunk[1] = (next_eeprom_addr & 0xff);
1595
1596                         if (msgs[i].flags & I2C_M_RD) {
1597                                 ret = aldebaran_i2c_read_data(i2c_adap,
1598                                                              (uint8_t)msgs[i].addr,
1599                                                              data_chunk, (data_size % data_chunk_size) + 2);
1600
1601                                 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
1602                         } else {
1603                                 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
1604
1605                                 ret = aldebaran_i2c_write_data(i2c_adap,
1606                                                               (uint8_t)msgs[i].addr,
1607                                                               data_chunk, (data_size % data_chunk_size) + 2);
1608                         }
1609
1610                         if (ret) {
1611                                 num = -EIO;
1612                                 goto fail;
1613                         }
1614                 }
1615         }
1616
1617 fail:
1618         return num;
1619 }
1620
1621 static u32 aldebaran_i2c_func(struct i2c_adapter *adap)
1622 {
1623         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1624 }
1625
1626
1627 static const struct i2c_algorithm aldebaran_i2c_algo = {
1628         .master_xfer = aldebaran_i2c_xfer,
1629         .functionality = aldebaran_i2c_func,
1630 };
1631
1632 static int aldebaran_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
1633 {
1634         struct amdgpu_device *adev = to_amdgpu_device(control);
1635         int res;
1636
1637         control->owner = THIS_MODULE;
1638         control->class = I2C_CLASS_SPD;
1639         control->dev.parent = &adev->pdev->dev;
1640         control->algo = &aldebaran_i2c_algo;
1641         snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
1642
1643         res = i2c_add_adapter(control);
1644         if (res)
1645                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
1646
1647         return res;
1648 }
1649
1650 static void aldebaran_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
1651 {
1652         i2c_del_adapter(control);
1653 }
1654
1655 static void aldebaran_get_unique_id(struct smu_context *smu)
1656 {
1657         struct amdgpu_device *adev = smu->adev;
1658         SmuMetrics_t *metrics = smu->smu_table.metrics_table;
1659         uint32_t upper32 = 0, lower32 = 0;
1660         int ret;
1661
1662         mutex_lock(&smu->metrics_lock);
1663         ret = smu_cmn_get_metrics_table_locked(smu, NULL, false);
1664         if (ret)
1665                 goto out_unlock;
1666
1667         upper32 = metrics->PublicSerialNumUpper32;
1668         lower32 = metrics->PublicSerialNumLower32;
1669
1670 out_unlock:
1671         mutex_unlock(&smu->metrics_lock);
1672
1673         adev->unique_id = ((uint64_t)upper32 << 32) | lower32;
1674         sprintf(adev->serial, "%016llx", adev->unique_id);
1675 }
1676
1677 static bool aldebaran_is_baco_supported(struct smu_context *smu)
1678 {
1679         /* aldebaran is not support baco */
1680
1681         return false;
1682 }
1683
1684 static int aldebaran_set_df_cstate(struct smu_context *smu,
1685                                    enum pp_df_cstate state)
1686 {
1687         return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
1688 }
1689
1690 static int aldebaran_allow_xgmi_power_down(struct smu_context *smu, bool en)
1691 {
1692         return smu_cmn_send_smc_msg_with_param(smu,
1693                                                SMU_MSG_GmiPwrDnControl,
1694                                                en ? 1 : 0,
1695                                                NULL);
1696 }
1697
1698 static const struct throttling_logging_label {
1699         uint32_t feature_mask;
1700         const char *label;
1701 } logging_label[] = {
1702         {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
1703         {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
1704         {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
1705         {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
1706 };
1707 static void aldebaran_log_thermal_throttling_event(struct smu_context *smu)
1708 {
1709         int ret;
1710         int throttler_idx, throtting_events = 0, buf_idx = 0;
1711         struct amdgpu_device *adev = smu->adev;
1712         uint32_t throttler_status;
1713         char log_buf[256];
1714
1715         ret = aldebaran_get_smu_metrics_data(smu,
1716                                              METRICS_THROTTLER_STATUS,
1717                                              &throttler_status);
1718         if (ret)
1719                 return;
1720
1721         memset(log_buf, 0, sizeof(log_buf));
1722         for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
1723              throttler_idx++) {
1724                 if (throttler_status & logging_label[throttler_idx].feature_mask) {
1725                         throtting_events++;
1726                         buf_idx += snprintf(log_buf + buf_idx,
1727                                             sizeof(log_buf) - buf_idx,
1728                                             "%s%s",
1729                                             throtting_events > 1 ? " and " : "",
1730                                             logging_label[throttler_idx].label);
1731                         if (buf_idx >= sizeof(log_buf)) {
1732                                 dev_err(adev->dev, "buffer overflow!\n");
1733                                 log_buf[sizeof(log_buf) - 1] = '\0';
1734                                 break;
1735                         }
1736                 }
1737         }
1738
1739         dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
1740                  log_buf);
1741         kgd2kfd_smi_event_throttle(smu->adev->kfd.dev, throttler_status);
1742 }
1743
1744 static int aldebaran_get_current_pcie_link_speed(struct smu_context *smu)
1745 {
1746         struct amdgpu_device *adev = smu->adev;
1747         uint32_t esm_ctrl;
1748
1749         /* TODO: confirm this on real target */
1750         esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
1751         if ((esm_ctrl >> 15) & 0x1FFFF)
1752                 return (((esm_ctrl >> 8) & 0x3F) + 128);
1753
1754         return smu_v13_0_get_current_pcie_link_speed(smu);
1755 }
1756
1757 static ssize_t aldebaran_get_gpu_metrics(struct smu_context *smu,
1758                                          void **table)
1759 {
1760         struct smu_table_context *smu_table = &smu->smu_table;
1761         struct gpu_metrics_v1_3 *gpu_metrics =
1762                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
1763         SmuMetrics_t metrics;
1764         int i, ret = 0;
1765
1766         ret = smu_cmn_get_metrics_table(smu,
1767                                         &metrics,
1768                                         true);
1769         if (ret)
1770                 return ret;
1771
1772         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
1773
1774         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
1775         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
1776         gpu_metrics->temperature_mem = metrics.TemperatureHBM;
1777         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
1778         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
1779         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
1780
1781         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
1782         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
1783         gpu_metrics->average_mm_activity = 0;
1784
1785         /* Valid power data is available only from primary die */
1786         if (aldebaran_is_primary(smu)) {
1787                 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
1788                 gpu_metrics->energy_accumulator =
1789                         (uint64_t)metrics.EnergyAcc64bitHigh << 32 |
1790                         metrics.EnergyAcc64bitLow;
1791         } else {
1792                 gpu_metrics->average_socket_power = 0;
1793                 gpu_metrics->energy_accumulator = 0;
1794         }
1795
1796         gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
1797         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
1798         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
1799         gpu_metrics->average_vclk0_frequency = 0;
1800         gpu_metrics->average_dclk0_frequency = 0;
1801
1802         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
1803         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
1804         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
1805         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
1806         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
1807
1808         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1809         gpu_metrics->indep_throttle_status =
1810                         smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1811                                                            aldebaran_throttler_map);
1812
1813         gpu_metrics->current_fan_speed = 0;
1814
1815         gpu_metrics->pcie_link_width =
1816                 smu_v13_0_get_current_pcie_link_width(smu);
1817         gpu_metrics->pcie_link_speed =
1818                 aldebaran_get_current_pcie_link_speed(smu);
1819
1820         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1821
1822         gpu_metrics->gfx_activity_acc = metrics.GfxBusyAcc;
1823         gpu_metrics->mem_activity_acc = metrics.DramBusyAcc;
1824
1825         for (i = 0; i < NUM_HBM_INSTANCES; i++)
1826                 gpu_metrics->temperature_hbm[i] = metrics.TemperatureAllHBM[i];
1827
1828         gpu_metrics->firmware_timestamp = ((uint64_t)metrics.TimeStampHigh << 32) |
1829                                         metrics.TimeStampLow;
1830
1831         *table = (void *)gpu_metrics;
1832
1833         return sizeof(struct gpu_metrics_v1_3);
1834 }
1835
1836 static int aldebaran_mode2_reset(struct smu_context *smu)
1837 {
1838         u32 smu_version;
1839         int ret = 0, index;
1840         struct amdgpu_device *adev = smu->adev;
1841         int timeout = 10;
1842
1843         smu_cmn_get_smc_version(smu, NULL, &smu_version);
1844
1845         index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
1846                                                 SMU_MSG_GfxDeviceDriverReset);
1847
1848         mutex_lock(&smu->message_lock);
1849         if (smu_version >= 0x00441400) {
1850                 ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, SMU_RESET_MODE_2);
1851                 /* This is similar to FLR, wait till max FLR timeout */
1852                 msleep(100);
1853                 dev_dbg(smu->adev->dev, "restore config space...\n");
1854                 /* Restore the config space saved during init */
1855                 amdgpu_device_load_pci_state(adev->pdev);
1856
1857                 dev_dbg(smu->adev->dev, "wait for reset ack\n");
1858                 while (ret == -ETIME && timeout)  {
1859                         ret = smu_cmn_wait_for_response(smu);
1860                         /* Wait a bit more time for getting ACK */
1861                         if (ret == -ETIME) {
1862                                 --timeout;
1863                                 usleep_range(500, 1000);
1864                                 continue;
1865                         }
1866
1867                         if (ret != 1) {
1868                                 dev_err(adev->dev, "failed to send mode2 message \tparam: 0x%08x response %#x\n",
1869                                                 SMU_RESET_MODE_2, ret);
1870                                 goto out;
1871                         }
1872                 }
1873
1874         } else {
1875                 dev_err(adev->dev, "smu fw 0x%x does not support MSG_GfxDeviceDriverReset MSG\n",
1876                                 smu_version);
1877         }
1878
1879         if (ret == 1)
1880                 ret = 0;
1881 out:
1882         mutex_unlock(&smu->message_lock);
1883
1884         return ret;
1885 }
1886
1887 static bool aldebaran_is_mode1_reset_supported(struct smu_context *smu)
1888 {
1889 #if 0
1890         struct amdgpu_device *adev = smu->adev;
1891         u32 smu_version;
1892         uint32_t val;
1893         /**
1894          * PM FW version support mode1 reset from 68.07
1895          */
1896         smu_cmn_get_smc_version(smu, NULL, &smu_version);
1897         if ((smu_version < 0x00440700))
1898                 return false;
1899         /**
1900          * mode1 reset relies on PSP, so we should check if
1901          * PSP is alive.
1902          */
1903         val = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
1904
1905         return val != 0x0;
1906 #endif
1907         return true;
1908 }
1909
1910 static bool aldebaran_is_mode2_reset_supported(struct smu_context *smu)
1911 {
1912         return true;
1913 }
1914
1915 static int aldebaran_set_mp1_state(struct smu_context *smu,
1916                                    enum pp_mp1_state mp1_state)
1917 {
1918         switch (mp1_state) {
1919         case PP_MP1_STATE_UNLOAD:
1920                 return smu_cmn_set_mp1_state(smu, mp1_state);
1921         default:
1922                 return 0;
1923         }
1924 }
1925
1926 static int aldebaran_smu_send_hbm_bad_page_num(struct smu_context *smu,
1927                 uint32_t size)
1928 {
1929         int ret = 0;
1930
1931         /* message SMU to update the bad page number on SMUBUS */
1932         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL);
1933         if (ret)
1934                 dev_err(smu->adev->dev, "[%s] failed to message SMU to update HBM bad pages number\n",
1935                                 __func__);
1936
1937         return ret;
1938 }
1939
1940 static const struct pptable_funcs aldebaran_ppt_funcs = {
1941         /* init dpm */
1942         .get_allowed_feature_mask = aldebaran_get_allowed_feature_mask,
1943         /* dpm/clk tables */
1944         .set_default_dpm_table = aldebaran_set_default_dpm_table,
1945         .populate_umd_state_clk = aldebaran_populate_umd_state_clk,
1946         .get_thermal_temperature_range = aldebaran_get_thermal_temperature_range,
1947         .print_clk_levels = aldebaran_print_clk_levels,
1948         .force_clk_levels = aldebaran_force_clk_levels,
1949         .read_sensor = aldebaran_read_sensor,
1950         .set_performance_level = aldebaran_set_performance_level,
1951         .get_power_limit = aldebaran_get_power_limit,
1952         .is_dpm_running = aldebaran_is_dpm_running,
1953         .get_unique_id = aldebaran_get_unique_id,
1954         .init_microcode = smu_v13_0_init_microcode,
1955         .load_microcode = smu_v13_0_load_microcode,
1956         .fini_microcode = smu_v13_0_fini_microcode,
1957         .init_smc_tables = aldebaran_init_smc_tables,
1958         .fini_smc_tables = smu_v13_0_fini_smc_tables,
1959         .init_power = smu_v13_0_init_power,
1960         .fini_power = smu_v13_0_fini_power,
1961         .check_fw_status = smu_v13_0_check_fw_status,
1962         /* pptable related */
1963         .setup_pptable = aldebaran_setup_pptable,
1964         .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
1965         .check_fw_version = smu_v13_0_check_fw_version,
1966         .write_pptable = smu_cmn_write_pptable,
1967         .set_driver_table_location = smu_v13_0_set_driver_table_location,
1968         .set_tool_table_location = smu_v13_0_set_tool_table_location,
1969         .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
1970         .system_features_control = aldebaran_system_features_control,
1971         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1972         .send_smc_msg = smu_cmn_send_smc_msg,
1973         .get_enabled_mask = smu_cmn_get_enabled_mask,
1974         .feature_is_enabled = smu_cmn_feature_is_enabled,
1975         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
1976         .set_power_limit = aldebaran_set_power_limit,
1977         .init_max_sustainable_clocks = smu_v13_0_init_max_sustainable_clocks,
1978         .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
1979         .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
1980         .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate,
1981         .register_irq_handler = smu_v13_0_register_irq_handler,
1982         .set_azalia_d3_pme = smu_v13_0_set_azalia_d3_pme,
1983         .get_max_sustainable_clocks_by_dc = smu_v13_0_get_max_sustainable_clocks_by_dc,
1984         .baco_is_support= aldebaran_is_baco_supported,
1985         .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq,
1986         .set_soft_freq_limited_range = aldebaran_set_soft_freq_limited_range,
1987         .od_edit_dpm_table = aldebaran_usr_edit_dpm_table,
1988         .set_df_cstate = aldebaran_set_df_cstate,
1989         .allow_xgmi_power_down = aldebaran_allow_xgmi_power_down,
1990         .log_thermal_throttling_event = aldebaran_log_thermal_throttling_event,
1991         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1992         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
1993         .get_gpu_metrics = aldebaran_get_gpu_metrics,
1994         .mode1_reset_is_support = aldebaran_is_mode1_reset_supported,
1995         .mode2_reset_is_support = aldebaran_is_mode2_reset_supported,
1996         .mode1_reset = smu_v13_0_mode1_reset,
1997         .set_mp1_state = aldebaran_set_mp1_state,
1998         .mode2_reset = aldebaran_mode2_reset,
1999         .wait_for_event = smu_v13_0_wait_for_event,
2000         .i2c_init = aldebaran_i2c_control_init,
2001         .i2c_fini = aldebaran_i2c_control_fini,
2002         .send_hbm_bad_pages_num = aldebaran_smu_send_hbm_bad_page_num,
2003 };
2004
2005 void aldebaran_set_ppt_funcs(struct smu_context *smu)
2006 {
2007         smu->ppt_funcs = &aldebaran_ppt_funcs;
2008         smu->message_map = aldebaran_message_map;
2009         smu->clock_map = aldebaran_clk_map;
2010         smu->feature_map = aldebaran_feature_mask_map;
2011         smu->table_map = aldebaran_table_map;
2012 }