drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_smu.h"
  28 #include "smu_v11_0.h"
  29 #include "smu11_driver_if_vangogh.h"
  30 #include "vangogh_ppt.h"
  31 #include "smu_v11_5_ppsmc.h"
  32 #include "smu_v11_5_pmfw.h"
  33 #include "smu_cmn.h"
  34 #include "soc15_common.h"
  35 #include "asic_reg/gc/gc_10_3_0_offset.h"
  36 #include "asic_reg/gc/gc_10_3_0_sh_mask.h"
  37 #include <asm/processor.h>
  38
  39 /*
  40  * DO NOT use these for err/warn/info/debug messages.
  41  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  42  * They are more MGPU friendly.
  43  */
  44 #undef pr_err
  45 #undef pr_warn
  46 #undef pr_info
  47 #undef pr_debug
  48
  49 // Registers related to GFXOFF
  50 // addressBlock: smuio_smuio_SmuSmuioDec
  51 // base address: 0x5a000
  52 #define mmSMUIO_GFX_MISC_CNTL                   0x00c5
  53 #define mmSMUIO_GFX_MISC_CNTL_BASE_IDX          0
  54
  55 //SMUIO_GFX_MISC_CNTL
  56 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff__SHIFT      0x0
  57 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT           0x1
  58 #define SMUIO_GFX_MISC_CNTL__SMU_GFX_cold_vs_gfxoff_MASK        0x00000001L
  59 #define SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK             0x00000006L
  60
  61 #define FEATURE_MASK(feature) (1ULL << feature)
  62 #define SMC_DPM_FEATURE ( \
  63         FEATURE_MASK(FEATURE_CCLK_DPM_BIT) | \
  64         FEATURE_MASK(FEATURE_VCN_DPM_BIT)        | \
  65         FEATURE_MASK(FEATURE_FCLK_DPM_BIT)       | \
  66         FEATURE_MASK(FEATURE_SOCCLK_DPM_BIT)     | \
  67         FEATURE_MASK(FEATURE_MP0CLK_DPM_BIT)     | \
  68         FEATURE_MASK(FEATURE_LCLK_DPM_BIT)       | \
  69         FEATURE_MASK(FEATURE_SHUBCLK_DPM_BIT)    | \
  70         FEATURE_MASK(FEATURE_DCFCLK_DPM_BIT)| \
  71         FEATURE_MASK(FEATURE_GFX_DPM_BIT))
  72
  73 static struct cmn2asic_msg_mapping vangogh_message_map[SMU_MSG_MAX_COUNT] = {
  74         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                  0),
  75         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,                0),
  76         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,   0),
  77         MSG_MAP(EnableGfxOff,                   PPSMC_MSG_EnableGfxOff,                 0),
  78         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,          0),
  79         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,               0),
  80         MSG_MAP(PowerDownIspByTile,             PPSMC_MSG_PowerDownIspByTile,   0),
  81         MSG_MAP(PowerUpIspByTile,               PPSMC_MSG_PowerUpIspByTile,             0),
  82         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                 0),
  83         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                   0),
  84         MSG_MAP(RlcPowerNotify,                 PPSMC_MSG_RlcPowerNotify,               0),
  85         MSG_MAP(SetHardMinVcn,                  PPSMC_MSG_SetHardMinVcn,                0),
  86         MSG_MAP(SetSoftMinGfxclk,               PPSMC_MSG_SetSoftMinGfxclk,             0),
  87         MSG_MAP(ActiveProcessNotify,            PPSMC_MSG_ActiveProcessNotify,          0),
  88         MSG_MAP(SetHardMinIspiclkByFreq,        PPSMC_MSG_SetHardMinIspiclkByFreq,      0),
  89         MSG_MAP(SetHardMinIspxclkByFreq,        PPSMC_MSG_SetHardMinIspxclkByFreq,      0),
  90         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,        0),
  91         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,         0),
  92         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,        0),
  93         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,        0),
  94         MSG_MAP(GfxDeviceDriverReset,           PPSMC_MSG_GfxDeviceDriverReset,         0),
  95         MSG_MAP(GetEnabledSmuFeatures,          PPSMC_MSG_GetEnabledSmuFeatures,        0),
  96         MSG_MAP(SetHardMinSocclkByFreq,         PPSMC_MSG_SetHardMinSocclkByFreq,       0),
  97         MSG_MAP(SetSoftMinFclk,                 PPSMC_MSG_SetSoftMinFclk,               0),
  98         MSG_MAP(SetSoftMinVcn,                  PPSMC_MSG_SetSoftMinVcn,                0),
  99         MSG_MAP(EnablePostCode,                 PPSMC_MSG_EnablePostCode,               0),
 100         MSG_MAP(GetGfxclkFrequency,             PPSMC_MSG_GetGfxclkFrequency,   0),
 101         MSG_MAP(GetFclkFrequency,               PPSMC_MSG_GetFclkFrequency,             0),
 102         MSG_MAP(SetSoftMaxGfxClk,               PPSMC_MSG_SetSoftMaxGfxClk,             0),
 103         MSG_MAP(SetHardMinGfxClk,               PPSMC_MSG_SetHardMinGfxClk,             0),
 104         MSG_MAP(SetSoftMaxSocclkByFreq,         PPSMC_MSG_SetSoftMaxSocclkByFreq,       0),
 105         MSG_MAP(SetSoftMaxFclkByFreq,           PPSMC_MSG_SetSoftMaxFclkByFreq,         0),
 106         MSG_MAP(SetSoftMaxVcn,                  PPSMC_MSG_SetSoftMaxVcn,                        0),
 107         MSG_MAP(SetPowerLimitPercentage,        PPSMC_MSG_SetPowerLimitPercentage,      0),
 108         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,                        0),
 109         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                          0),
 110         MSG_MAP(SetHardMinFclkByFreq,           PPSMC_MSG_SetHardMinFclkByFreq,         0),
 111         MSG_MAP(SetSoftMinSocclkByFreq,         PPSMC_MSG_SetSoftMinSocclkByFreq,       0),
 112         MSG_MAP(PowerUpCvip,                    PPSMC_MSG_PowerUpCvip,                          0),
 113         MSG_MAP(PowerDownCvip,                  PPSMC_MSG_PowerDownCvip,                        0),
 114         MSG_MAP(GetPptLimit,                        PPSMC_MSG_GetPptLimit,                      0),
 115         MSG_MAP(GetThermalLimit,                    PPSMC_MSG_GetThermalLimit,          0),
 116         MSG_MAP(GetCurrentTemperature,              PPSMC_MSG_GetCurrentTemperature, 0),
 117         MSG_MAP(GetCurrentPower,                    PPSMC_MSG_GetCurrentPower,           0),
 118         MSG_MAP(GetCurrentVoltage,                  PPSMC_MSG_GetCurrentVoltage,         0),
 119         MSG_MAP(GetCurrentCurrent,                  PPSMC_MSG_GetCurrentCurrent,         0),
 120         MSG_MAP(GetAverageCpuActivity,              PPSMC_MSG_GetAverageCpuActivity, 0),
 121         MSG_MAP(GetAverageGfxActivity,              PPSMC_MSG_GetAverageGfxActivity, 0),
 122         MSG_MAP(GetAveragePower,                    PPSMC_MSG_GetAveragePower,           0),
 123         MSG_MAP(GetAverageTemperature,              PPSMC_MSG_GetAverageTemperature, 0),
 124         MSG_MAP(SetAveragePowerTimeConstant,        PPSMC_MSG_SetAveragePowerTimeConstant,                      0),
 125         MSG_MAP(SetAverageActivityTimeConstant,     PPSMC_MSG_SetAverageActivityTimeConstant,           0),
 126         MSG_MAP(SetAverageTemperatureTimeConstant,  PPSMC_MSG_SetAverageTemperatureTimeConstant,        0),
 127         MSG_MAP(SetMitigationEndHysteresis,         PPSMC_MSG_SetMitigationEndHysteresis,                       0),
 128         MSG_MAP(GetCurrentFreq,                     PPSMC_MSG_GetCurrentFreq,                                           0),
 129         MSG_MAP(SetReducedPptLimit,                 PPSMC_MSG_SetReducedPptLimit,                                       0),
 130         MSG_MAP(SetReducedThermalLimit,             PPSMC_MSG_SetReducedThermalLimit,                           0),
 131         MSG_MAP(DramLogSetDramAddr,                 PPSMC_MSG_DramLogSetDramAddr,                                       0),
 132         MSG_MAP(StartDramLogging,                   PPSMC_MSG_StartDramLogging,                                         0),
 133         MSG_MAP(StopDramLogging,                    PPSMC_MSG_StopDramLogging,                                          0),
 134         MSG_MAP(SetSoftMinCclk,                     PPSMC_MSG_SetSoftMinCclk,                                           0),
 135         MSG_MAP(SetSoftMaxCclk,                     PPSMC_MSG_SetSoftMaxCclk,                                           0),
 136         MSG_MAP(RequestActiveWgp,                   PPSMC_MSG_RequestActiveWgp,                     0),
 137         MSG_MAP(SetFastPPTLimit,                    PPSMC_MSG_SetFastPPTLimit,                                          0),
 138         MSG_MAP(SetSlowPPTLimit,                    PPSMC_MSG_SetSlowPPTLimit,                                          0),
 139         MSG_MAP(GetFastPPTLimit,                    PPSMC_MSG_GetFastPPTLimit,                                          0),
 140         MSG_MAP(GetSlowPPTLimit,                    PPSMC_MSG_GetSlowPPTLimit,                                          0),
 141         MSG_MAP(GetGfxOffStatus,                    PPSMC_MSG_GetGfxOffStatus,                                          0),
 142         MSG_MAP(GetGfxOffEntryCount,                PPSMC_MSG_GetGfxOffEntryCount,                                      0),
 143         MSG_MAP(LogGfxOffResidency,                 PPSMC_MSG_LogGfxOffResidency,                                       0),
 144 };
 145
 146 static struct cmn2asic_mapping vangogh_feature_mask_map[SMU_FEATURE_COUNT] = {
 147         FEA_MAP(PPT),
 148         FEA_MAP(TDC),
 149         FEA_MAP(THERMAL),
 150         FEA_MAP(DS_GFXCLK),
 151         FEA_MAP(DS_SOCCLK),
 152         FEA_MAP(DS_LCLK),
 153         FEA_MAP(DS_FCLK),
 154         FEA_MAP(DS_MP1CLK),
 155         FEA_MAP(DS_MP0CLK),
 156         FEA_MAP(ATHUB_PG),
 157         FEA_MAP(CCLK_DPM),
 158         FEA_MAP(FAN_CONTROLLER),
 159         FEA_MAP(ULV),
 160         FEA_MAP(VCN_DPM),
 161         FEA_MAP(LCLK_DPM),
 162         FEA_MAP(SHUBCLK_DPM),
 163         FEA_MAP(DCFCLK_DPM),
 164         FEA_MAP(DS_DCFCLK),
 165         FEA_MAP(S0I2),
 166         FEA_MAP(SMU_LOW_POWER),
 167         FEA_MAP(GFX_DEM),
 168         FEA_MAP(PSI),
 169         FEA_MAP(PROCHOT),
 170         FEA_MAP(CPUOFF),
 171         FEA_MAP(STAPM),
 172         FEA_MAP(S0I3),
 173         FEA_MAP(DF_CSTATES),
 174         FEA_MAP(PERF_LIMIT),
 175         FEA_MAP(CORE_DLDO),
 176         FEA_MAP(RSMU_LOW_POWER),
 177         FEA_MAP(SMN_LOW_POWER),
 178         FEA_MAP(THM_LOW_POWER),
 179         FEA_MAP(SMUIO_LOW_POWER),
 180         FEA_MAP(MP1_LOW_POWER),
 181         FEA_MAP(DS_VCN),
 182         FEA_MAP(CPPC),
 183         FEA_MAP(OS_CSTATES),
 184         FEA_MAP(ISP_DPM),
 185         FEA_MAP(A55_DPM),
 186         FEA_MAP(CVIP_DSP_DPM),
 187         FEA_MAP(MSMU_LOW_POWER),
 188         FEA_MAP_REVERSE(SOCCLK),
 189         FEA_MAP_REVERSE(FCLK),
 190         FEA_MAP_HALF_REVERSE(GFX),
 191 };
 192
 193 static struct cmn2asic_mapping vangogh_table_map[SMU_TABLE_COUNT] = {
 194         TAB_MAP_VALID(WATERMARKS),
 195         TAB_MAP_VALID(SMU_METRICS),
 196         TAB_MAP_VALID(CUSTOM_DPM),
 197         TAB_MAP_VALID(DPMCLOCKS),
 198 };
 199
 200 static struct cmn2asic_mapping vangogh_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 201         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 202         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 203         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 204         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 205         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 206         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CAPPED,               WORKLOAD_PPLIB_CAPPED_BIT),
 207         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_UNCAPPED,             WORKLOAD_PPLIB_UNCAPPED_BIT),
 208 };
 209
 210 static const uint8_t vangogh_throttler_map[] = {
 211         [THROTTLER_STATUS_BIT_SPL]      = (SMU_THROTTLER_SPL_BIT),
 212         [THROTTLER_STATUS_BIT_FPPT]     = (SMU_THROTTLER_FPPT_BIT),
 213         [THROTTLER_STATUS_BIT_SPPT]     = (SMU_THROTTLER_SPPT_BIT),
 214         [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT),
 215         [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT),
 216         [THROTTLER_STATUS_BIT_THM_GFX]  = (SMU_THROTTLER_TEMP_GPU_BIT),
 217         [THROTTLER_STATUS_BIT_THM_SOC]  = (SMU_THROTTLER_TEMP_SOC_BIT),
 218         [THROTTLER_STATUS_BIT_TDC_VDD]  = (SMU_THROTTLER_TDC_VDD_BIT),
 219         [THROTTLER_STATUS_BIT_TDC_SOC]  = (SMU_THROTTLER_TDC_SOC_BIT),
 220         [THROTTLER_STATUS_BIT_TDC_GFX]  = (SMU_THROTTLER_TDC_GFX_BIT),
 221         [THROTTLER_STATUS_BIT_TDC_CVIP] = (SMU_THROTTLER_TDC_CVIP_BIT),
 222 };
 223
 224 static int vangogh_tables_init(struct smu_context *smu)
 225 {
 226         struct smu_table_context *smu_table = &smu->smu_table;
 227         struct smu_table *tables = smu_table->tables;
 228
 229         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 230                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 231         SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
 232                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 233         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 234                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 235         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF, sizeof(DpmActivityMonitorCoeffExt_t),
 236                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 237         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, max(sizeof(SmuMetrics_t), sizeof(SmuMetrics_legacy_t)),
 238                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 239
 240         smu_table->metrics_table = kzalloc(max(sizeof(SmuMetrics_t), sizeof(SmuMetrics_legacy_t)), GFP_KERNEL);
 241         if (!smu_table->metrics_table)
 242                 goto err0_out;
 243         smu_table->metrics_time = 0;
 244
 245         smu_table->gpu_metrics_table_size = max(sizeof(struct gpu_metrics_v2_3), sizeof(struct gpu_metrics_v2_2));
 246         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 247         if (!smu_table->gpu_metrics_table)
 248                 goto err1_out;
 249
 250         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 251         if (!smu_table->watermarks_table)
 252                 goto err2_out;
 253
 254         smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
 255         if (!smu_table->clocks_table)
 256                 goto err3_out;
 257
 258         return 0;
 259
 260 err3_out:
 261         kfree(smu_table->watermarks_table);
 262 err2_out:
 263         kfree(smu_table->gpu_metrics_table);
 264 err1_out:
 265         kfree(smu_table->metrics_table);
 266 err0_out:
 267         return -ENOMEM;
 268 }
 269
 270 static int vangogh_get_legacy_smu_metrics_data(struct smu_context *smu,
 271                                        MetricsMember_t member,
 272                                        uint32_t *value)
 273 {
 274         struct smu_table_context *smu_table = &smu->smu_table;
 275         SmuMetrics_legacy_t *metrics = (SmuMetrics_legacy_t *)smu_table->metrics_table;
 276         int ret = 0;
 277
 278         ret = smu_cmn_get_metrics_table(smu,
 279                                         NULL,
 280                                         false);
 281         if (ret)
 282                 return ret;
 283
 284         switch (member) {
 285         case METRICS_CURR_GFXCLK:
 286                 *value = metrics->GfxclkFrequency;
 287                 break;
 288         case METRICS_AVERAGE_SOCCLK:
 289                 *value = metrics->SocclkFrequency;
 290                 break;
 291         case METRICS_AVERAGE_VCLK:
 292                 *value = metrics->VclkFrequency;
 293                 break;
 294         case METRICS_AVERAGE_DCLK:
 295                 *value = metrics->DclkFrequency;
 296                 break;
 297         case METRICS_CURR_UCLK:
 298                 *value = metrics->MemclkFrequency;
 299                 break;
 300         case METRICS_AVERAGE_GFXACTIVITY:
 301                 *value = metrics->GfxActivity / 100;
 302                 break;
 303         case METRICS_AVERAGE_VCNACTIVITY:
 304                 *value = metrics->UvdActivity;
 305                 break;
 306         case METRICS_AVERAGE_SOCKETPOWER:
 307                 *value = (metrics->CurrentSocketPower << 8) /
 308                 1000 ;
 309                 break;
 310         case METRICS_TEMPERATURE_EDGE:
 311                 *value = metrics->GfxTemperature / 100 *
 312                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 313                 break;
 314         case METRICS_TEMPERATURE_HOTSPOT:
 315                 *value = metrics->SocTemperature / 100 *
 316                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 317                 break;
 318         case METRICS_THROTTLER_STATUS:
 319                 *value = metrics->ThrottlerStatus;
 320                 break;
 321         case METRICS_VOLTAGE_VDDGFX:
 322                 *value = metrics->Voltage[2];
 323                 break;
 324         case METRICS_VOLTAGE_VDDSOC:
 325                 *value = metrics->Voltage[1];
 326                 break;
 327         case METRICS_AVERAGE_CPUCLK:
 328                 memcpy(value, &metrics->CoreFrequency[0],
 329                        smu->cpu_core_num * sizeof(uint16_t));
 330                 break;
 331         default:
 332                 *value = UINT_MAX;
 333                 break;
 334         }
 335
 336         return ret;
 337 }
 338
 339 static int vangogh_get_smu_metrics_data(struct smu_context *smu,
 340                                        MetricsMember_t member,
 341                                        uint32_t *value)
 342 {
 343         struct smu_table_context *smu_table = &smu->smu_table;
 344         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 345         int ret = 0;
 346
 347         ret = smu_cmn_get_metrics_table(smu,
 348                                         NULL,
 349                                         false);
 350         if (ret)
 351                 return ret;
 352
 353         switch (member) {
 354         case METRICS_CURR_GFXCLK:
 355                 *value = metrics->Current.GfxclkFrequency;
 356                 break;
 357         case METRICS_AVERAGE_SOCCLK:
 358                 *value = metrics->Current.SocclkFrequency;
 359                 break;
 360         case METRICS_AVERAGE_VCLK:
 361                 *value = metrics->Current.VclkFrequency;
 362                 break;
 363         case METRICS_AVERAGE_DCLK:
 364                 *value = metrics->Current.DclkFrequency;
 365                 break;
 366         case METRICS_CURR_UCLK:
 367                 *value = metrics->Current.MemclkFrequency;
 368                 break;
 369         case METRICS_AVERAGE_GFXACTIVITY:
 370                 *value = metrics->Current.GfxActivity;
 371                 break;
 372         case METRICS_AVERAGE_VCNACTIVITY:
 373                 *value = metrics->Current.UvdActivity;
 374                 break;
 375         case METRICS_AVERAGE_SOCKETPOWER:
 376                 *value = (metrics->Average.CurrentSocketPower << 8) /
 377                 1000;
 378                 break;
 379         case METRICS_CURR_SOCKETPOWER:
 380                 *value = (metrics->Current.CurrentSocketPower << 8) /
 381                 1000;
 382                 break;
 383         case METRICS_TEMPERATURE_EDGE:
 384                 *value = metrics->Current.GfxTemperature / 100 *
 385                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 386                 break;
 387         case METRICS_TEMPERATURE_HOTSPOT:
 388                 *value = metrics->Current.SocTemperature / 100 *
 389                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 390                 break;
 391         case METRICS_THROTTLER_STATUS:
 392                 *value = metrics->Current.ThrottlerStatus;
 393                 break;
 394         case METRICS_VOLTAGE_VDDGFX:
 395                 *value = metrics->Current.Voltage[2];
 396                 break;
 397         case METRICS_VOLTAGE_VDDSOC:
 398                 *value = metrics->Current.Voltage[1];
 399                 break;
 400         case METRICS_AVERAGE_CPUCLK:
 401                 memcpy(value, &metrics->Current.CoreFrequency[0],
 402                        smu->cpu_core_num * sizeof(uint16_t));
 403                 break;
 404         default:
 405                 *value = UINT_MAX;
 406                 break;
 407         }
 408
 409         return ret;
 410 }
 411
 412 static int vangogh_common_get_smu_metrics_data(struct smu_context *smu,
 413                                        MetricsMember_t member,
 414                                        uint32_t *value)
 415 {
 416         int ret = 0;
 417
 418         if (smu->smc_fw_if_version < 0x3)
 419                 ret = vangogh_get_legacy_smu_metrics_data(smu, member, value);
 420         else
 421                 ret = vangogh_get_smu_metrics_data(smu, member, value);
 422
 423         return ret;
 424 }
 425
 426 static int vangogh_allocate_dpm_context(struct smu_context *smu)
 427 {
 428         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 429
 430         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 431                                        GFP_KERNEL);
 432         if (!smu_dpm->dpm_context)
 433                 return -ENOMEM;
 434
 435         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 436
 437         return 0;
 438 }
 439
 440 static int vangogh_init_smc_tables(struct smu_context *smu)
 441 {
 442         int ret = 0;
 443
 444         ret = vangogh_tables_init(smu);
 445         if (ret)
 446                 return ret;
 447
 448         ret = vangogh_allocate_dpm_context(smu);
 449         if (ret)
 450                 return ret;
 451
 452 #ifdef CONFIG_X86
 453         /* AMD x86 APU only */
 454         smu->cpu_core_num = topology_num_cores_per_package();
 455 #else
 456         smu->cpu_core_num = 4;
 457 #endif
 458
 459         return smu_v11_0_init_smc_tables(smu);
 460 }
 461
 462 static int vangogh_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 463 {
 464         int ret = 0;
 465
 466         if (enable) {
 467                 /* vcn dpm on is a prerequisite for vcn power gate messages */
 468                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
 469                 if (ret)
 470                         return ret;
 471         } else {
 472                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
 473                 if (ret)
 474                         return ret;
 475         }
 476
 477         return ret;
 478 }
 479
 480 static int vangogh_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 481 {
 482         int ret = 0;
 483
 484         if (enable) {
 485                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
 486                 if (ret)
 487                         return ret;
 488         } else {
 489                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
 490                 if (ret)
 491                         return ret;
 492         }
 493
 494         return ret;
 495 }
 496
 497 static bool vangogh_is_dpm_running(struct smu_context *smu)
 498 {
 499         struct amdgpu_device *adev = smu->adev;
 500         int ret = 0;
 501         uint64_t feature_enabled;
 502
 503         /* we need to re-init after suspend so return false */
 504         if (adev->in_suspend)
 505                 return false;
 506
 507         ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
 508
 509         if (ret)
 510                 return false;
 511
 512         return !!(feature_enabled & SMC_DPM_FEATURE);
 513 }
 514
 515 static int vangogh_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
 516                                                 uint32_t dpm_level, uint32_t *freq)
 517 {
 518         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
 519
 520         if (!clk_table || clk_type >= SMU_CLK_COUNT)
 521                 return -EINVAL;
 522
 523         switch (clk_type) {
 524         case SMU_SOCCLK:
 525                 if (dpm_level >= clk_table->NumSocClkLevelsEnabled)
 526                         return -EINVAL;
 527                 *freq = clk_table->SocClocks[dpm_level];
 528                 break;
 529         case SMU_VCLK:
 530                 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
 531                         return -EINVAL;
 532                 *freq = clk_table->VcnClocks[dpm_level].vclk;
 533                 break;
 534         case SMU_DCLK:
 535                 if (dpm_level >= clk_table->VcnClkLevelsEnabled)
 536                         return -EINVAL;
 537                 *freq = clk_table->VcnClocks[dpm_level].dclk;
 538                 break;
 539         case SMU_UCLK:
 540         case SMU_MCLK:
 541                 if (dpm_level >= clk_table->NumDfPstatesEnabled)
 542                         return -EINVAL;
 543                 *freq = clk_table->DfPstateTable[dpm_level].memclk;
 544
 545                 break;
 546         case SMU_FCLK:
 547                 if (dpm_level >= clk_table->NumDfPstatesEnabled)
 548                         return -EINVAL;
 549                 *freq = clk_table->DfPstateTable[dpm_level].fclk;
 550                 break;
 551         default:
 552                 return -EINVAL;
 553         }
 554
 555         return 0;
 556 }
 557
 558 static int vangogh_print_legacy_clk_levels(struct smu_context *smu,
 559                         enum smu_clk_type clk_type, char *buf)
 560 {
 561         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
 562         SmuMetrics_legacy_t metrics;
 563         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
 564         int i, idx, size = 0, ret = 0;
 565         uint32_t cur_value = 0, value = 0, count = 0;
 566         bool cur_value_match_level = false;
 567
 568         memset(&metrics, 0, sizeof(metrics));
 569
 570         ret = smu_cmn_get_metrics_table(smu, &metrics, false);
 571         if (ret)
 572                 return ret;
 573
 574         smu_cmn_get_sysfs_buf(&buf, &size);
 575
 576         switch (clk_type) {
 577         case SMU_OD_SCLK:
 578                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
 579                         size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
 580                         size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
 581                         (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
 582                         size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
 583                         (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
 584                 }
 585                 break;
 586         case SMU_OD_CCLK:
 587                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
 588                         size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n",  smu->cpu_core_id_select);
 589                         size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
 590                         (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
 591                         size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
 592                         (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
 593                 }
 594                 break;
 595         case SMU_OD_RANGE:
 596                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
 597                         size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
 598                         size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
 599                                 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
 600                         size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
 601                                 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
 602                 }
 603                 break;
 604         case SMU_SOCCLK:
 605                 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */
 606                 count = clk_table->NumSocClkLevelsEnabled;
 607                 cur_value = metrics.SocclkFrequency;
 608                 break;
 609         case SMU_VCLK:
 610                 count = clk_table->VcnClkLevelsEnabled;
 611                 cur_value = metrics.VclkFrequency;
 612                 break;
 613         case SMU_DCLK:
 614                 count = clk_table->VcnClkLevelsEnabled;
 615                 cur_value = metrics.DclkFrequency;
 616                 break;
 617         case SMU_MCLK:
 618                 count = clk_table->NumDfPstatesEnabled;
 619                 cur_value = metrics.MemclkFrequency;
 620                 break;
 621         case SMU_FCLK:
 622                 count = clk_table->NumDfPstatesEnabled;
 623                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value);
 624                 if (ret)
 625                         return ret;
 626                 break;
 627         default:
 628                 break;
 629         }
 630
 631         switch (clk_type) {
 632         case SMU_SOCCLK:
 633         case SMU_VCLK:
 634         case SMU_DCLK:
 635         case SMU_MCLK:
 636         case SMU_FCLK:
 637                 for (i = 0; i < count; i++) {
 638                         idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
 639                         ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
 640                         if (ret)
 641                                 return ret;
 642                         if (!value)
 643                                 continue;
 644                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
 645                                         cur_value == value ? "*" : "");
 646                         if (cur_value == value)
 647                                 cur_value_match_level = true;
 648                 }
 649
 650                 if (!cur_value_match_level)
 651                         size += sysfs_emit_at(buf, size, "   %uMhz *\n", cur_value);
 652                 break;
 653         default:
 654                 break;
 655         }
 656
 657         return size;
 658 }
 659
 660 static int vangogh_print_clk_levels(struct smu_context *smu,
 661                         enum smu_clk_type clk_type, char *buf)
 662 {
 663         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
 664         SmuMetrics_t metrics;
 665         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
 666         int i, idx, size = 0, ret = 0;
 667         uint32_t cur_value = 0, value = 0, count = 0;
 668         bool cur_value_match_level = false;
 669         uint32_t min, max;
 670
 671         memset(&metrics, 0, sizeof(metrics));
 672
 673         ret = smu_cmn_get_metrics_table(smu, &metrics, false);
 674         if (ret)
 675                 return ret;
 676
 677         smu_cmn_get_sysfs_buf(&buf, &size);
 678
 679         switch (clk_type) {
 680         case SMU_OD_SCLK:
 681                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
 682                         size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
 683                         size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
 684                         (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq);
 685                         size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
 686                         (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq);
 687                 }
 688                 break;
 689         case SMU_OD_CCLK:
 690                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
 691                         size += sysfs_emit_at(buf, size, "CCLK_RANGE in Core%d:\n",  smu->cpu_core_id_select);
 692                         size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
 693                         (smu->cpu_actual_soft_min_freq > 0) ? smu->cpu_actual_soft_min_freq : smu->cpu_default_soft_min_freq);
 694                         size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
 695                         (smu->cpu_actual_soft_max_freq > 0) ? smu->cpu_actual_soft_max_freq : smu->cpu_default_soft_max_freq);
 696                 }
 697                 break;
 698         case SMU_OD_RANGE:
 699                 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
 700                         size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
 701                         size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
 702                                 smu->gfx_default_hard_min_freq, smu->gfx_default_soft_max_freq);
 703                         size += sysfs_emit_at(buf, size, "CCLK: %7uMhz %10uMhz\n",
 704                                 smu->cpu_default_soft_min_freq, smu->cpu_default_soft_max_freq);
 705                 }
 706                 break;
 707         case SMU_SOCCLK:
 708                 /* the level 3 ~ 6 of socclk use the same frequency for vangogh */
 709                 count = clk_table->NumSocClkLevelsEnabled;
 710                 cur_value = metrics.Current.SocclkFrequency;
 711                 break;
 712         case SMU_VCLK:
 713                 count = clk_table->VcnClkLevelsEnabled;
 714                 cur_value = metrics.Current.VclkFrequency;
 715                 break;
 716         case SMU_DCLK:
 717                 count = clk_table->VcnClkLevelsEnabled;
 718                 cur_value = metrics.Current.DclkFrequency;
 719                 break;
 720         case SMU_MCLK:
 721                 count = clk_table->NumDfPstatesEnabled;
 722                 cur_value = metrics.Current.MemclkFrequency;
 723                 break;
 724         case SMU_FCLK:
 725                 count = clk_table->NumDfPstatesEnabled;
 726                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetFclkFrequency, 0, &cur_value);
 727                 if (ret)
 728                         return ret;
 729                 break;
 730         case SMU_GFXCLK:
 731         case SMU_SCLK:
 732                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetGfxclkFrequency, 0, &cur_value);
 733                 if (ret) {
 734                         return ret;
 735                 }
 736                 break;
 737         default:
 738                 break;
 739         }
 740
 741         switch (clk_type) {
 742         case SMU_SOCCLK:
 743         case SMU_VCLK:
 744         case SMU_DCLK:
 745         case SMU_MCLK:
 746         case SMU_FCLK:
 747                 for (i = 0; i < count; i++) {
 748                         idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
 749                         ret = vangogh_get_dpm_clk_limited(smu, clk_type, idx, &value);
 750                         if (ret)
 751                                 return ret;
 752                         if (!value)
 753                                 continue;
 754                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
 755                                         cur_value == value ? "*" : "");
 756                         if (cur_value == value)
 757                                 cur_value_match_level = true;
 758                 }
 759
 760                 if (!cur_value_match_level)
 761                         size += sysfs_emit_at(buf, size, "   %uMhz *\n", cur_value);
 762                 break;
 763         case SMU_GFXCLK:
 764         case SMU_SCLK:
 765                 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
 766                 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
 767                 if (cur_value  == max)
 768                         i = 2;
 769                 else if (cur_value == min)
 770                         i = 0;
 771                 else
 772                         i = 1;
 773                 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
 774                                 i == 0 ? "*" : "");
 775                 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
 776                                 i == 1 ? cur_value : VANGOGH_UMD_PSTATE_STANDARD_GFXCLK,
 777                                 i == 1 ? "*" : "");
 778                 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
 779                                 i == 2 ? "*" : "");
 780                 break;
 781         default:
 782                 break;
 783         }
 784
 785         return size;
 786 }
 787
 788 static int vangogh_common_print_clk_levels(struct smu_context *smu,
 789                         enum smu_clk_type clk_type, char *buf)
 790 {
 791         int ret = 0;
 792
 793         if (smu->smc_fw_if_version < 0x3)
 794                 ret = vangogh_print_legacy_clk_levels(smu, clk_type, buf);
 795         else
 796                 ret = vangogh_print_clk_levels(smu, clk_type, buf);
 797
 798         return ret;
 799 }
 800
 801 static int vangogh_get_profiling_clk_mask(struct smu_context *smu,
 802                                          enum amd_dpm_forced_level level,
 803                                          uint32_t *vclk_mask,
 804                                          uint32_t *dclk_mask,
 805                                          uint32_t *mclk_mask,
 806                                          uint32_t *fclk_mask,
 807                                          uint32_t *soc_mask)
 808 {
 809         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
 810
 811         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
 812                 if (mclk_mask)
 813                         *mclk_mask = clk_table->NumDfPstatesEnabled - 1;
 814
 815                 if (fclk_mask)
 816                         *fclk_mask = clk_table->NumDfPstatesEnabled - 1;
 817
 818                 if (soc_mask)
 819                         *soc_mask = 0;
 820         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
 821                 if (mclk_mask)
 822                         *mclk_mask = 0;
 823
 824                 if (fclk_mask)
 825                         *fclk_mask = 0;
 826
 827                 if (soc_mask)
 828                         *soc_mask = 1;
 829
 830                 if (vclk_mask)
 831                         *vclk_mask = 1;
 832
 833                 if (dclk_mask)
 834                         *dclk_mask = 1;
 835         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) {
 836                 if (mclk_mask)
 837                         *mclk_mask = 0;
 838
 839                 if (fclk_mask)
 840                         *fclk_mask = 0;
 841
 842                 if (soc_mask)
 843                         *soc_mask = 1;
 844
 845                 if (vclk_mask)
 846                         *vclk_mask = 1;
 847
 848                 if (dclk_mask)
 849                         *dclk_mask = 1;
 850         }
 851
 852         return 0;
 853 }
 854
 855 static bool vangogh_clk_dpm_is_enabled(struct smu_context *smu,
 856                                 enum smu_clk_type clk_type)
 857 {
 858         enum smu_feature_mask feature_id = 0;
 859
 860         switch (clk_type) {
 861         case SMU_MCLK:
 862         case SMU_UCLK:
 863         case SMU_FCLK:
 864                 feature_id = SMU_FEATURE_DPM_FCLK_BIT;
 865                 break;
 866         case SMU_GFXCLK:
 867         case SMU_SCLK:
 868                 feature_id = SMU_FEATURE_DPM_GFXCLK_BIT;
 869                 break;
 870         case SMU_SOCCLK:
 871                 feature_id = SMU_FEATURE_DPM_SOCCLK_BIT;
 872                 break;
 873         case SMU_VCLK:
 874         case SMU_DCLK:
 875                 feature_id = SMU_FEATURE_VCN_DPM_BIT;
 876                 break;
 877         default:
 878                 return true;
 879         }
 880
 881         if (!smu_cmn_feature_is_enabled(smu, feature_id))
 882                 return false;
 883
 884         return true;
 885 }
 886
 887 static int vangogh_get_dpm_ultimate_freq(struct smu_context *smu,
 888                                         enum smu_clk_type clk_type,
 889                                         uint32_t *min,
 890                                         uint32_t *max)
 891 {
 892         int ret = 0;
 893         uint32_t soc_mask;
 894         uint32_t vclk_mask;
 895         uint32_t dclk_mask;
 896         uint32_t mclk_mask;
 897         uint32_t fclk_mask;
 898         uint32_t clock_limit;
 899
 900         if (!vangogh_clk_dpm_is_enabled(smu, clk_type)) {
 901                 switch (clk_type) {
 902                 case SMU_MCLK:
 903                 case SMU_UCLK:
 904                         clock_limit = smu->smu_table.boot_values.uclk;
 905                         break;
 906                 case SMU_FCLK:
 907                         clock_limit = smu->smu_table.boot_values.fclk;
 908                         break;
 909                 case SMU_GFXCLK:
 910                 case SMU_SCLK:
 911                         clock_limit = smu->smu_table.boot_values.gfxclk;
 912                         break;
 913                 case SMU_SOCCLK:
 914                         clock_limit = smu->smu_table.boot_values.socclk;
 915                         break;
 916                 case SMU_VCLK:
 917                         clock_limit = smu->smu_table.boot_values.vclk;
 918                         break;
 919                 case SMU_DCLK:
 920                         clock_limit = smu->smu_table.boot_values.dclk;
 921                         break;
 922                 default:
 923                         clock_limit = 0;
 924                         break;
 925                 }
 926
 927                 /* clock in Mhz unit */
 928                 if (min)
 929                         *min = clock_limit / 100;
 930                 if (max)
 931                         *max = clock_limit / 100;
 932
 933                 return 0;
 934         }
 935         if (max) {
 936                 ret = vangogh_get_profiling_clk_mask(smu,
 937                                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
 938                                                         &vclk_mask,
 939                                                         &dclk_mask,
 940                                                         &mclk_mask,
 941                                                         &fclk_mask,
 942                                                         &soc_mask);
 943                 if (ret)
 944                         goto failed;
 945
 946                 switch (clk_type) {
 947                 case SMU_UCLK:
 948                 case SMU_MCLK:
 949                         ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
 950                         if (ret)
 951                                 goto failed;
 952                         break;
 953                 case SMU_SOCCLK:
 954                         ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
 955                         if (ret)
 956                                 goto failed;
 957                         break;
 958                 case SMU_FCLK:
 959                         ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, max);
 960                         if (ret)
 961                                 goto failed;
 962                         break;
 963                 case SMU_VCLK:
 964                         ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, max);
 965                         if (ret)
 966                                 goto failed;
 967                         break;
 968                 case SMU_DCLK:
 969                         ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, max);
 970                         if (ret)
 971                                 goto failed;
 972                         break;
 973                 default:
 974                         ret = -EINVAL;
 975                         goto failed;
 976                 }
 977         }
 978         if (min) {
 979                 switch (clk_type) {
 980                 case SMU_UCLK:
 981                 case SMU_MCLK:
 982                         ret = vangogh_get_dpm_clk_limited(smu, clk_type, mclk_mask, min);
 983                         if (ret)
 984                                 goto failed;
 985                         break;
 986                 case SMU_SOCCLK:
 987                         ret = vangogh_get_dpm_clk_limited(smu, clk_type, soc_mask, min);
 988                         if (ret)
 989                                 goto failed;
 990                         break;
 991                 case SMU_FCLK:
 992                         ret = vangogh_get_dpm_clk_limited(smu, clk_type, fclk_mask, min);
 993                         if (ret)
 994                                 goto failed;
 995                         break;
 996                 case SMU_VCLK:
 997                         ret = vangogh_get_dpm_clk_limited(smu, clk_type, vclk_mask, min);
 998                         if (ret)
 999                                 goto failed;
1000                         break;
1001                 case SMU_DCLK:
1002                         ret = vangogh_get_dpm_clk_limited(smu, clk_type, dclk_mask, min);
1003                         if (ret)
1004                                 goto failed;
1005                         break;
1006                 default:
1007                         ret = -EINVAL;
1008                         goto failed;
1009                 }
1010         }
1011 failed:
1012         return ret;
1013 }
1014
1015 static int vangogh_get_power_profile_mode(struct smu_context *smu,
1016                                            char *buf)
1017 {
1018         uint32_t i, size = 0;
1019         int16_t workload_type = 0;
1020
1021         if (!buf)
1022                 return -EINVAL;
1023
1024         for (i = 0; i < PP_SMC_POWER_PROFILE_COUNT; i++) {
1025                 /*
1026                  * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1027                  * Not all profile modes are supported on vangogh.
1028                  */
1029                 workload_type = smu_cmn_to_asic_specific_index(smu,
1030                                                                CMN2ASIC_MAPPING_WORKLOAD,
1031                                                                i);
1032
1033                 if (workload_type < 0)
1034                         continue;
1035
1036                 size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
1037                         i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1038         }
1039
1040         return size;
1041 }
1042
1043 static int vangogh_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1044 {
1045         int workload_type, ret;
1046         uint32_t profile_mode = input[size];
1047
1048         if (profile_mode >= PP_SMC_POWER_PROFILE_COUNT) {
1049                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
1050                 return -EINVAL;
1051         }
1052
1053         if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT ||
1054                         profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING)
1055                 return 0;
1056
1057         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1058         workload_type = smu_cmn_to_asic_specific_index(smu,
1059                                                        CMN2ASIC_MAPPING_WORKLOAD,
1060                                                        profile_mode);
1061         if (workload_type < 0) {
1062                 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on VANGOGH\n",
1063                                         profile_mode);
1064                 return -EINVAL;
1065         }
1066
1067         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
1068                                     1 << workload_type,
1069                                     NULL);
1070         if (ret) {
1071                 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n",
1072                                         workload_type);
1073                 return ret;
1074         }
1075
1076         smu->power_profile_mode = profile_mode;
1077
1078         return 0;
1079 }
1080
1081 static int vangogh_set_soft_freq_limited_range(struct smu_context *smu,
1082                                           enum smu_clk_type clk_type,
1083                                           uint32_t min,
1084                                           uint32_t max)
1085 {
1086         int ret = 0;
1087
1088         if (!vangogh_clk_dpm_is_enabled(smu, clk_type))
1089                 return 0;
1090
1091         switch (clk_type) {
1092         case SMU_GFXCLK:
1093         case SMU_SCLK:
1094                 ret = smu_cmn_send_smc_msg_with_param(smu,
1095                                                         SMU_MSG_SetHardMinGfxClk,
1096                                                         min, NULL);
1097                 if (ret)
1098                         return ret;
1099
1100                 ret = smu_cmn_send_smc_msg_with_param(smu,
1101                                                         SMU_MSG_SetSoftMaxGfxClk,
1102                                                         max, NULL);
1103                 if (ret)
1104                         return ret;
1105                 break;
1106         case SMU_FCLK:
1107                 ret = smu_cmn_send_smc_msg_with_param(smu,
1108                                                         SMU_MSG_SetHardMinFclkByFreq,
1109                                                         min, NULL);
1110                 if (ret)
1111                         return ret;
1112
1113                 ret = smu_cmn_send_smc_msg_with_param(smu,
1114                                                         SMU_MSG_SetSoftMaxFclkByFreq,
1115                                                         max, NULL);
1116                 if (ret)
1117                         return ret;
1118                 break;
1119         case SMU_SOCCLK:
1120                 ret = smu_cmn_send_smc_msg_with_param(smu,
1121                                                         SMU_MSG_SetHardMinSocclkByFreq,
1122                                                         min, NULL);
1123                 if (ret)
1124                         return ret;
1125
1126                 ret = smu_cmn_send_smc_msg_with_param(smu,
1127                                                         SMU_MSG_SetSoftMaxSocclkByFreq,
1128                                                         max, NULL);
1129                 if (ret)
1130                         return ret;
1131                 break;
1132         case SMU_VCLK:
1133                 ret = smu_cmn_send_smc_msg_with_param(smu,
1134                                                         SMU_MSG_SetHardMinVcn,
1135                                                         min << 16, NULL);
1136                 if (ret)
1137                         return ret;
1138                 ret = smu_cmn_send_smc_msg_with_param(smu,
1139                                                         SMU_MSG_SetSoftMaxVcn,
1140                                                         max << 16, NULL);
1141                 if (ret)
1142                         return ret;
1143                 break;
1144         case SMU_DCLK:
1145                 ret = smu_cmn_send_smc_msg_with_param(smu,
1146                                                         SMU_MSG_SetHardMinVcn,
1147                                                         min, NULL);
1148                 if (ret)
1149                         return ret;
1150                 ret = smu_cmn_send_smc_msg_with_param(smu,
1151                                                         SMU_MSG_SetSoftMaxVcn,
1152                                                         max, NULL);
1153                 if (ret)
1154                         return ret;
1155                 break;
1156         default:
1157                 return -EINVAL;
1158         }
1159
1160         return ret;
1161 }
1162
1163 static int vangogh_force_clk_levels(struct smu_context *smu,
1164                                    enum smu_clk_type clk_type, uint32_t mask)
1165 {
1166         uint32_t soft_min_level = 0, soft_max_level = 0;
1167         uint32_t min_freq = 0, max_freq = 0;
1168         int ret = 0 ;
1169
1170         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1171         soft_max_level = mask ? (fls(mask) - 1) : 0;
1172
1173         switch (clk_type) {
1174         case SMU_SOCCLK:
1175                 ret = vangogh_get_dpm_clk_limited(smu, clk_type,
1176                                                 soft_min_level, &min_freq);
1177                 if (ret)
1178                         return ret;
1179                 ret = vangogh_get_dpm_clk_limited(smu, clk_type,
1180                                                 soft_max_level, &max_freq);
1181                 if (ret)
1182                         return ret;
1183                 ret = smu_cmn_send_smc_msg_with_param(smu,
1184                                                                 SMU_MSG_SetSoftMaxSocclkByFreq,
1185                                                                 max_freq, NULL);
1186                 if (ret)
1187                         return ret;
1188                 ret = smu_cmn_send_smc_msg_with_param(smu,
1189                                                                 SMU_MSG_SetHardMinSocclkByFreq,
1190                                                                 min_freq, NULL);
1191                 if (ret)
1192                         return ret;
1193                 break;
1194         case SMU_FCLK:
1195                 ret = vangogh_get_dpm_clk_limited(smu,
1196                                                         clk_type, soft_min_level, &min_freq);
1197                 if (ret)
1198                         return ret;
1199                 ret = vangogh_get_dpm_clk_limited(smu,
1200                                                         clk_type, soft_max_level, &max_freq);
1201                 if (ret)
1202                         return ret;
1203                 ret = smu_cmn_send_smc_msg_with_param(smu,
1204                                                                 SMU_MSG_SetSoftMaxFclkByFreq,
1205                                                                 max_freq, NULL);
1206                 if (ret)
1207                         return ret;
1208                 ret = smu_cmn_send_smc_msg_with_param(smu,
1209                                                                 SMU_MSG_SetHardMinFclkByFreq,
1210                                                                 min_freq, NULL);
1211                 if (ret)
1212                         return ret;
1213                 break;
1214         case SMU_VCLK:
1215                 ret = vangogh_get_dpm_clk_limited(smu,
1216                                                         clk_type, soft_min_level, &min_freq);
1217                 if (ret)
1218                         return ret;
1219
1220                 ret = vangogh_get_dpm_clk_limited(smu,
1221                                                         clk_type, soft_max_level, &max_freq);
1222                 if (ret)
1223                         return ret;
1224
1225
1226                 ret = smu_cmn_send_smc_msg_with_param(smu,
1227                                                                 SMU_MSG_SetHardMinVcn,
1228                                                                 min_freq << 16, NULL);
1229                 if (ret)
1230                         return ret;
1231
1232                 ret = smu_cmn_send_smc_msg_with_param(smu,
1233                                                                 SMU_MSG_SetSoftMaxVcn,
1234                                                                 max_freq << 16, NULL);
1235                 if (ret)
1236                         return ret;
1237
1238                 break;
1239         case SMU_DCLK:
1240                 ret = vangogh_get_dpm_clk_limited(smu,
1241                                                         clk_type, soft_min_level, &min_freq);
1242                 if (ret)
1243                         return ret;
1244
1245                 ret = vangogh_get_dpm_clk_limited(smu,
1246                                                         clk_type, soft_max_level, &max_freq);
1247                 if (ret)
1248                         return ret;
1249
1250                 ret = smu_cmn_send_smc_msg_with_param(smu,
1251                                                         SMU_MSG_SetHardMinVcn,
1252                                                         min_freq, NULL);
1253                 if (ret)
1254                         return ret;
1255
1256                 ret = smu_cmn_send_smc_msg_with_param(smu,
1257                                                         SMU_MSG_SetSoftMaxVcn,
1258                                                         max_freq, NULL);
1259                 if (ret)
1260                         return ret;
1261
1262                 break;
1263         default:
1264                 break;
1265         }
1266
1267         return ret;
1268 }
1269
1270 static int vangogh_force_dpm_limit_value(struct smu_context *smu, bool highest)
1271 {
1272         int ret = 0, i = 0;
1273         uint32_t min_freq, max_freq, force_freq;
1274         enum smu_clk_type clk_type;
1275
1276         enum smu_clk_type clks[] = {
1277                 SMU_SOCCLK,
1278                 SMU_VCLK,
1279                 SMU_DCLK,
1280                 SMU_FCLK,
1281         };
1282
1283         for (i = 0; i < ARRAY_SIZE(clks); i++) {
1284                 clk_type = clks[i];
1285                 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
1286                 if (ret)
1287                         return ret;
1288
1289                 force_freq = highest ? max_freq : min_freq;
1290                 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);
1291                 if (ret)
1292                         return ret;
1293         }
1294
1295         return ret;
1296 }
1297
1298 static int vangogh_unforce_dpm_levels(struct smu_context *smu)
1299 {
1300         int ret = 0, i = 0;
1301         uint32_t min_freq, max_freq;
1302         enum smu_clk_type clk_type;
1303
1304         struct clk_feature_map {
1305                 enum smu_clk_type clk_type;
1306                 uint32_t        feature;
1307         } clk_feature_map[] = {
1308                 {SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT},
1309                 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
1310                 {SMU_VCLK, SMU_FEATURE_VCN_DPM_BIT},
1311                 {SMU_DCLK, SMU_FEATURE_VCN_DPM_BIT},
1312         };
1313
1314         for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
1315
1316                 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature))
1317                     continue;
1318
1319                 clk_type = clk_feature_map[i].clk_type;
1320
1321                 ret = vangogh_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
1322
1323                 if (ret)
1324                         return ret;
1325
1326                 ret = vangogh_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1327
1328                 if (ret)
1329                         return ret;
1330         }
1331
1332         return ret;
1333 }
1334
1335 static int vangogh_set_peak_clock_by_device(struct smu_context *smu)
1336 {
1337         int ret = 0;
1338         uint32_t socclk_freq = 0, fclk_freq = 0;
1339         uint32_t vclk_freq = 0, dclk_freq = 0;
1340
1341         ret = vangogh_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk_freq);
1342         if (ret)
1343                 return ret;
1344
1345         ret = vangogh_set_soft_freq_limited_range(smu, SMU_FCLK, fclk_freq, fclk_freq);
1346         if (ret)
1347                 return ret;
1348
1349         ret = vangogh_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk_freq);
1350         if (ret)
1351                 return ret;
1352
1353         ret = vangogh_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk_freq, socclk_freq);
1354         if (ret)
1355                 return ret;
1356
1357         ret = vangogh_get_dpm_ultimate_freq(smu, SMU_VCLK, NULL, &vclk_freq);
1358         if (ret)
1359                 return ret;
1360
1361         ret = vangogh_set_soft_freq_limited_range(smu, SMU_VCLK, vclk_freq, vclk_freq);
1362         if (ret)
1363                 return ret;
1364
1365         ret = vangogh_get_dpm_ultimate_freq(smu, SMU_DCLK, NULL, &dclk_freq);
1366         if (ret)
1367                 return ret;
1368
1369         ret = vangogh_set_soft_freq_limited_range(smu, SMU_DCLK, dclk_freq, dclk_freq);
1370         if (ret)
1371                 return ret;
1372
1373         return ret;
1374 }
1375
1376 static int vangogh_set_performance_level(struct smu_context *smu,
1377                                         enum amd_dpm_forced_level level)
1378 {
1379         int ret = 0, i;
1380         uint32_t soc_mask, mclk_mask, fclk_mask;
1381         uint32_t vclk_mask = 0, dclk_mask = 0;
1382
1383         smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
1384         smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
1385
1386         switch (level) {
1387         case AMD_DPM_FORCED_LEVEL_HIGH:
1388                 smu->gfx_actual_hard_min_freq = smu->gfx_default_soft_max_freq;
1389                 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1390
1391
1392                 ret = vangogh_force_dpm_limit_value(smu, true);
1393                 if (ret)
1394                         return ret;
1395                 break;
1396         case AMD_DPM_FORCED_LEVEL_LOW:
1397                 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1398                 smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq;
1399
1400                 ret = vangogh_force_dpm_limit_value(smu, false);
1401                 if (ret)
1402                         return ret;
1403                 break;
1404         case AMD_DPM_FORCED_LEVEL_AUTO:
1405                 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1406                 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1407
1408                 ret = vangogh_unforce_dpm_levels(smu);
1409                 if (ret)
1410                         return ret;
1411                 break;
1412         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1413                 smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK;
1414                 smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_STANDARD_GFXCLK;
1415
1416                 ret = vangogh_get_profiling_clk_mask(smu, level,
1417                                                         &vclk_mask,
1418                                                         &dclk_mask,
1419                                                         &mclk_mask,
1420                                                         &fclk_mask,
1421                                                         &soc_mask);
1422                 if (ret)
1423                         return ret;
1424
1425                 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
1426                 vangogh_force_clk_levels(smu, SMU_SOCCLK, 1 << soc_mask);
1427                 vangogh_force_clk_levels(smu, SMU_VCLK, 1 << vclk_mask);
1428                 vangogh_force_clk_levels(smu, SMU_DCLK, 1 << dclk_mask);
1429                 break;
1430         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1431                 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1432                 smu->gfx_actual_soft_max_freq = smu->gfx_default_hard_min_freq;
1433                 break;
1434         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1435                 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1436                 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1437
1438                 ret = vangogh_get_profiling_clk_mask(smu, level,
1439                                                         NULL,
1440                                                         NULL,
1441                                                         &mclk_mask,
1442                                                         &fclk_mask,
1443                                                         NULL);
1444                 if (ret)
1445                         return ret;
1446
1447                 vangogh_force_clk_levels(smu, SMU_FCLK, 1 << fclk_mask);
1448                 break;
1449         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1450                 smu->gfx_actual_hard_min_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK;
1451                 smu->gfx_actual_soft_max_freq = VANGOGH_UMD_PSTATE_PEAK_GFXCLK;
1452
1453                 ret = vangogh_set_peak_clock_by_device(smu);
1454                 if (ret)
1455                         return ret;
1456                 break;
1457         case AMD_DPM_FORCED_LEVEL_MANUAL:
1458         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1459         default:
1460                 return 0;
1461         }
1462
1463         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
1464                                               smu->gfx_actual_hard_min_freq, NULL);
1465         if (ret)
1466                 return ret;
1467
1468         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
1469                                               smu->gfx_actual_soft_max_freq, NULL);
1470         if (ret)
1471                 return ret;
1472
1473         if (smu->adev->pm.fw_version >= 0x43f1b00) {
1474                 for (i = 0; i < smu->cpu_core_num; i++) {
1475                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
1476                                                               ((i << 20)
1477                                                                | smu->cpu_actual_soft_min_freq),
1478                                                               NULL);
1479                         if (ret)
1480                                 return ret;
1481
1482                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
1483                                                               ((i << 20)
1484                                                                | smu->cpu_actual_soft_max_freq),
1485                                                               NULL);
1486                         if (ret)
1487                                 return ret;
1488                 }
1489         }
1490
1491         return ret;
1492 }
1493
1494 static int vangogh_read_sensor(struct smu_context *smu,
1495                                  enum amd_pp_sensors sensor,
1496                                  void *data, uint32_t *size)
1497 {
1498         int ret = 0;
1499
1500         if (!data || !size)
1501                 return -EINVAL;
1502
1503         switch (sensor) {
1504         case AMDGPU_PP_SENSOR_GPU_LOAD:
1505                 ret = vangogh_common_get_smu_metrics_data(smu,
1506                                                    METRICS_AVERAGE_GFXACTIVITY,
1507                                                    (uint32_t *)data);
1508                 *size = 4;
1509                 break;
1510         case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1511                 ret = vangogh_common_get_smu_metrics_data(smu,
1512                                                    METRICS_AVERAGE_SOCKETPOWER,
1513                                                    (uint32_t *)data);
1514                 *size = 4;
1515                 break;
1516         case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1517                 ret = vangogh_common_get_smu_metrics_data(smu,
1518                                                    METRICS_CURR_SOCKETPOWER,
1519                                                    (uint32_t *)data);
1520                 *size = 4;
1521                 break;
1522         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1523                 ret = vangogh_common_get_smu_metrics_data(smu,
1524                                                    METRICS_TEMPERATURE_EDGE,
1525                                                    (uint32_t *)data);
1526                 *size = 4;
1527                 break;
1528         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1529                 ret = vangogh_common_get_smu_metrics_data(smu,
1530                                                    METRICS_TEMPERATURE_HOTSPOT,
1531                                                    (uint32_t *)data);
1532                 *size = 4;
1533                 break;
1534         case AMDGPU_PP_SENSOR_GFX_MCLK:
1535                 ret = vangogh_common_get_smu_metrics_data(smu,
1536                                                    METRICS_CURR_UCLK,
1537                                                    (uint32_t *)data);
1538                 *(uint32_t *)data *= 100;
1539                 *size = 4;
1540                 break;
1541         case AMDGPU_PP_SENSOR_GFX_SCLK:
1542                 ret = vangogh_common_get_smu_metrics_data(smu,
1543                                                    METRICS_CURR_GFXCLK,
1544                                                    (uint32_t *)data);
1545                 *(uint32_t *)data *= 100;
1546                 *size = 4;
1547                 break;
1548         case AMDGPU_PP_SENSOR_VDDGFX:
1549                 ret = vangogh_common_get_smu_metrics_data(smu,
1550                                                    METRICS_VOLTAGE_VDDGFX,
1551                                                    (uint32_t *)data);
1552                 *size = 4;
1553                 break;
1554         case AMDGPU_PP_SENSOR_VDDNB:
1555                 ret = vangogh_common_get_smu_metrics_data(smu,
1556                                                    METRICS_VOLTAGE_VDDSOC,
1557                                                    (uint32_t *)data);
1558                 *size = 4;
1559                 break;
1560         case AMDGPU_PP_SENSOR_CPU_CLK:
1561                 ret = vangogh_common_get_smu_metrics_data(smu,
1562                                                    METRICS_AVERAGE_CPUCLK,
1563                                                    (uint32_t *)data);
1564                 *size = smu->cpu_core_num * sizeof(uint16_t);
1565                 break;
1566         default:
1567                 ret = -EOPNOTSUPP;
1568                 break;
1569         }
1570
1571         return ret;
1572 }
1573
1574 static int vangogh_get_apu_thermal_limit(struct smu_context *smu, uint32_t *limit)
1575 {
1576         return smu_cmn_send_smc_msg_with_param(smu,
1577                                               SMU_MSG_GetThermalLimit,
1578                                               0, limit);
1579 }
1580
1581 static int vangogh_set_apu_thermal_limit(struct smu_context *smu, uint32_t limit)
1582 {
1583         return smu_cmn_send_smc_msg_with_param(smu,
1584                                               SMU_MSG_SetReducedThermalLimit,
1585                                               limit, NULL);
1586 }
1587
1588
1589 static int vangogh_set_watermarks_table(struct smu_context *smu,
1590                                        struct pp_smu_wm_range_sets *clock_ranges)
1591 {
1592         int i;
1593         int ret = 0;
1594         Watermarks_t *table = smu->smu_table.watermarks_table;
1595
1596         if (!table || !clock_ranges)
1597                 return -EINVAL;
1598
1599         if (clock_ranges) {
1600                 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1601                         clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1602                         return -EINVAL;
1603
1604                 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1605                         table->WatermarkRow[WM_DCFCLK][i].MinClock =
1606                                 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1607                         table->WatermarkRow[WM_DCFCLK][i].MaxClock =
1608                                 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1609                         table->WatermarkRow[WM_DCFCLK][i].MinMclk =
1610                                 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1611                         table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
1612                                 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1613
1614                         table->WatermarkRow[WM_DCFCLK][i].WmSetting =
1615                                 clock_ranges->reader_wm_sets[i].wm_inst;
1616                 }
1617
1618                 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1619                         table->WatermarkRow[WM_SOCCLK][i].MinClock =
1620                                 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1621                         table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1622                                 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1623                         table->WatermarkRow[WM_SOCCLK][i].MinMclk =
1624                                 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1625                         table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
1626                                 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1627
1628                         table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1629                                 clock_ranges->writer_wm_sets[i].wm_inst;
1630                 }
1631
1632                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1633         }
1634
1635         /* pass data to smu controller */
1636         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1637              !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1638                 ret = smu_cmn_write_watermarks_table(smu);
1639                 if (ret) {
1640                         dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1641                         return ret;
1642                 }
1643                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1644         }
1645
1646         return 0;
1647 }
1648
1649 static ssize_t vangogh_get_legacy_gpu_metrics_v2_3(struct smu_context *smu,
1650                                       void **table)
1651 {
1652         struct smu_table_context *smu_table = &smu->smu_table;
1653         struct gpu_metrics_v2_3 *gpu_metrics =
1654                 (struct gpu_metrics_v2_3 *)smu_table->gpu_metrics_table;
1655         SmuMetrics_legacy_t metrics;
1656         int ret = 0;
1657
1658         ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1659         if (ret)
1660                 return ret;
1661
1662         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 3);
1663
1664         gpu_metrics->temperature_gfx = metrics.GfxTemperature;
1665         gpu_metrics->temperature_soc = metrics.SocTemperature;
1666         memcpy(&gpu_metrics->temperature_core[0],
1667                 &metrics.CoreTemperature[0],
1668                 sizeof(uint16_t) * 4);
1669         gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
1670
1671         gpu_metrics->average_gfx_activity = metrics.GfxActivity;
1672         gpu_metrics->average_mm_activity = metrics.UvdActivity;
1673
1674         gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
1675         gpu_metrics->average_cpu_power = metrics.Power[0];
1676         gpu_metrics->average_soc_power = metrics.Power[1];
1677         gpu_metrics->average_gfx_power = metrics.Power[2];
1678         memcpy(&gpu_metrics->average_core_power[0],
1679                 &metrics.CorePower[0],
1680                 sizeof(uint16_t) * 4);
1681
1682         gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
1683         gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
1684         gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
1685         gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
1686         gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
1687         gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
1688
1689         memcpy(&gpu_metrics->current_coreclk[0],
1690                 &metrics.CoreFrequency[0],
1691                 sizeof(uint16_t) * 4);
1692         gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
1693
1694         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1695         gpu_metrics->indep_throttle_status =
1696                         smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1697                                                            vangogh_throttler_map);
1698
1699         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1700
1701         *table = (void *)gpu_metrics;
1702
1703         return sizeof(struct gpu_metrics_v2_3);
1704 }
1705
1706 static ssize_t vangogh_get_legacy_gpu_metrics(struct smu_context *smu,
1707                                       void **table)
1708 {
1709         struct smu_table_context *smu_table = &smu->smu_table;
1710         struct gpu_metrics_v2_2 *gpu_metrics =
1711                 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
1712         SmuMetrics_legacy_t metrics;
1713         int ret = 0;
1714
1715         ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1716         if (ret)
1717                 return ret;
1718
1719         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
1720
1721         gpu_metrics->temperature_gfx = metrics.GfxTemperature;
1722         gpu_metrics->temperature_soc = metrics.SocTemperature;
1723         memcpy(&gpu_metrics->temperature_core[0],
1724                 &metrics.CoreTemperature[0],
1725                 sizeof(uint16_t) * 4);
1726         gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
1727
1728         gpu_metrics->average_gfx_activity = metrics.GfxActivity;
1729         gpu_metrics->average_mm_activity = metrics.UvdActivity;
1730
1731         gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
1732         gpu_metrics->average_cpu_power = metrics.Power[0];
1733         gpu_metrics->average_soc_power = metrics.Power[1];
1734         gpu_metrics->average_gfx_power = metrics.Power[2];
1735         memcpy(&gpu_metrics->average_core_power[0],
1736                 &metrics.CorePower[0],
1737                 sizeof(uint16_t) * 4);
1738
1739         gpu_metrics->average_gfxclk_frequency = metrics.GfxclkFrequency;
1740         gpu_metrics->average_socclk_frequency = metrics.SocclkFrequency;
1741         gpu_metrics->average_uclk_frequency = metrics.MemclkFrequency;
1742         gpu_metrics->average_fclk_frequency = metrics.MemclkFrequency;
1743         gpu_metrics->average_vclk_frequency = metrics.VclkFrequency;
1744         gpu_metrics->average_dclk_frequency = metrics.DclkFrequency;
1745
1746         memcpy(&gpu_metrics->current_coreclk[0],
1747                 &metrics.CoreFrequency[0],
1748                 sizeof(uint16_t) * 4);
1749         gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
1750
1751         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1752         gpu_metrics->indep_throttle_status =
1753                         smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1754                                                            vangogh_throttler_map);
1755
1756         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1757
1758         *table = (void *)gpu_metrics;
1759
1760         return sizeof(struct gpu_metrics_v2_2);
1761 }
1762
1763 static ssize_t vangogh_get_gpu_metrics_v2_3(struct smu_context *smu,
1764                                       void **table)
1765 {
1766         struct smu_table_context *smu_table = &smu->smu_table;
1767         struct gpu_metrics_v2_3 *gpu_metrics =
1768                 (struct gpu_metrics_v2_3 *)smu_table->gpu_metrics_table;
1769         SmuMetrics_t metrics;
1770         int ret = 0;
1771
1772         ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1773         if (ret)
1774                 return ret;
1775
1776         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 3);
1777
1778         gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
1779         gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
1780         memcpy(&gpu_metrics->temperature_core[0],
1781                 &metrics.Current.CoreTemperature[0],
1782                 sizeof(uint16_t) * 4);
1783         gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
1784
1785         gpu_metrics->average_temperature_gfx = metrics.Average.GfxTemperature;
1786         gpu_metrics->average_temperature_soc = metrics.Average.SocTemperature;
1787         memcpy(&gpu_metrics->average_temperature_core[0],
1788                 &metrics.Average.CoreTemperature[0],
1789                 sizeof(uint16_t) * 4);
1790         gpu_metrics->average_temperature_l3[0] = metrics.Average.L3Temperature[0];
1791
1792         gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity;
1793         gpu_metrics->average_mm_activity = metrics.Current.UvdActivity;
1794
1795         gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower;
1796         gpu_metrics->average_cpu_power = metrics.Current.Power[0];
1797         gpu_metrics->average_soc_power = metrics.Current.Power[1];
1798         gpu_metrics->average_gfx_power = metrics.Current.Power[2];
1799         memcpy(&gpu_metrics->average_core_power[0],
1800                 &metrics.Average.CorePower[0],
1801                 sizeof(uint16_t) * 4);
1802
1803         gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
1804         gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
1805         gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
1806         gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
1807         gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
1808         gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
1809
1810         gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
1811         gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
1812         gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
1813         gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
1814         gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
1815         gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
1816
1817         memcpy(&gpu_metrics->current_coreclk[0],
1818                 &metrics.Current.CoreFrequency[0],
1819                 sizeof(uint16_t) * 4);
1820         gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
1821
1822         gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
1823         gpu_metrics->indep_throttle_status =
1824                         smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
1825                                                            vangogh_throttler_map);
1826
1827         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1828
1829         *table = (void *)gpu_metrics;
1830
1831         return sizeof(struct gpu_metrics_v2_3);
1832 }
1833
1834 static ssize_t vangogh_get_gpu_metrics_v2_4(struct smu_context *smu,
1835                                             void **table)
1836 {
1837         SmuMetrics_t metrics;
1838         struct smu_table_context *smu_table = &smu->smu_table;
1839         struct gpu_metrics_v2_4 *gpu_metrics =
1840                                 (struct gpu_metrics_v2_4 *)smu_table->gpu_metrics_table;
1841         int ret = 0;
1842
1843         ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1844         if (ret)
1845                 return ret;
1846
1847         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 4);
1848
1849         gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
1850         gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
1851         memcpy(&gpu_metrics->temperature_core[0],
1852                &metrics.Current.CoreTemperature[0],
1853                sizeof(uint16_t) * 4);
1854         gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
1855
1856         gpu_metrics->average_temperature_gfx = metrics.Average.GfxTemperature;
1857         gpu_metrics->average_temperature_soc = metrics.Average.SocTemperature;
1858         memcpy(&gpu_metrics->average_temperature_core[0],
1859                &metrics.Average.CoreTemperature[0],
1860                sizeof(uint16_t) * 4);
1861         gpu_metrics->average_temperature_l3[0] = metrics.Average.L3Temperature[0];
1862
1863         gpu_metrics->average_gfx_activity = metrics.Average.GfxActivity;
1864         gpu_metrics->average_mm_activity = metrics.Average.UvdActivity;
1865
1866         gpu_metrics->average_socket_power = metrics.Average.CurrentSocketPower;
1867         gpu_metrics->average_cpu_power = metrics.Average.Power[0];
1868         gpu_metrics->average_soc_power = metrics.Average.Power[1];
1869         gpu_metrics->average_gfx_power = metrics.Average.Power[2];
1870
1871         gpu_metrics->average_cpu_voltage = metrics.Average.Voltage[0];
1872         gpu_metrics->average_soc_voltage = metrics.Average.Voltage[1];
1873         gpu_metrics->average_gfx_voltage = metrics.Average.Voltage[2];
1874
1875         gpu_metrics->average_cpu_current = metrics.Average.Current[0];
1876         gpu_metrics->average_soc_current = metrics.Average.Current[1];
1877         gpu_metrics->average_gfx_current = metrics.Average.Current[2];
1878
1879         memcpy(&gpu_metrics->average_core_power[0],
1880                &metrics.Average.CorePower[0],
1881                sizeof(uint16_t) * 4);
1882
1883         gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
1884         gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
1885         gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
1886         gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
1887         gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
1888         gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
1889
1890         gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
1891         gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
1892         gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
1893         gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
1894         gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
1895         gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
1896
1897         memcpy(&gpu_metrics->current_coreclk[0],
1898                &metrics.Current.CoreFrequency[0],
1899                sizeof(uint16_t) * 4);
1900         gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
1901
1902         gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
1903         gpu_metrics->indep_throttle_status =
1904                         smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
1905                                                            vangogh_throttler_map);
1906
1907         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1908
1909         *table = (void *)gpu_metrics;
1910
1911         return sizeof(struct gpu_metrics_v2_4);
1912 }
1913
1914 static ssize_t vangogh_get_gpu_metrics(struct smu_context *smu,
1915                                       void **table)
1916 {
1917         struct smu_table_context *smu_table = &smu->smu_table;
1918         struct gpu_metrics_v2_2 *gpu_metrics =
1919                 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
1920         SmuMetrics_t metrics;
1921         int ret = 0;
1922
1923         ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1924         if (ret)
1925                 return ret;
1926
1927         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
1928
1929         gpu_metrics->temperature_gfx = metrics.Current.GfxTemperature;
1930         gpu_metrics->temperature_soc = metrics.Current.SocTemperature;
1931         memcpy(&gpu_metrics->temperature_core[0],
1932                 &metrics.Current.CoreTemperature[0],
1933                 sizeof(uint16_t) * 4);
1934         gpu_metrics->temperature_l3[0] = metrics.Current.L3Temperature[0];
1935
1936         gpu_metrics->average_gfx_activity = metrics.Current.GfxActivity;
1937         gpu_metrics->average_mm_activity = metrics.Current.UvdActivity;
1938
1939         gpu_metrics->average_socket_power = metrics.Current.CurrentSocketPower;
1940         gpu_metrics->average_cpu_power = metrics.Current.Power[0];
1941         gpu_metrics->average_soc_power = metrics.Current.Power[1];
1942         gpu_metrics->average_gfx_power = metrics.Current.Power[2];
1943         memcpy(&gpu_metrics->average_core_power[0],
1944                 &metrics.Average.CorePower[0],
1945                 sizeof(uint16_t) * 4);
1946
1947         gpu_metrics->average_gfxclk_frequency = metrics.Average.GfxclkFrequency;
1948         gpu_metrics->average_socclk_frequency = metrics.Average.SocclkFrequency;
1949         gpu_metrics->average_uclk_frequency = metrics.Average.MemclkFrequency;
1950         gpu_metrics->average_fclk_frequency = metrics.Average.MemclkFrequency;
1951         gpu_metrics->average_vclk_frequency = metrics.Average.VclkFrequency;
1952         gpu_metrics->average_dclk_frequency = metrics.Average.DclkFrequency;
1953
1954         gpu_metrics->current_gfxclk = metrics.Current.GfxclkFrequency;
1955         gpu_metrics->current_socclk = metrics.Current.SocclkFrequency;
1956         gpu_metrics->current_uclk = metrics.Current.MemclkFrequency;
1957         gpu_metrics->current_fclk = metrics.Current.MemclkFrequency;
1958         gpu_metrics->current_vclk = metrics.Current.VclkFrequency;
1959         gpu_metrics->current_dclk = metrics.Current.DclkFrequency;
1960
1961         memcpy(&gpu_metrics->current_coreclk[0],
1962                 &metrics.Current.CoreFrequency[0],
1963                 sizeof(uint16_t) * 4);
1964         gpu_metrics->current_l3clk[0] = metrics.Current.L3Frequency[0];
1965
1966         gpu_metrics->throttle_status = metrics.Current.ThrottlerStatus;
1967         gpu_metrics->indep_throttle_status =
1968                         smu_cmn_get_indep_throttler_status(metrics.Current.ThrottlerStatus,
1969                                                            vangogh_throttler_map);
1970
1971         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1972
1973         *table = (void *)gpu_metrics;
1974
1975         return sizeof(struct gpu_metrics_v2_2);
1976 }
1977
1978 static ssize_t vangogh_common_get_gpu_metrics(struct smu_context *smu,
1979                                       void **table)
1980 {
1981         uint32_t smu_program;
1982         uint32_t fw_version;
1983         int ret = 0;
1984
1985         smu_program = (smu->smc_fw_version >> 24) & 0xff;
1986         fw_version = smu->smc_fw_version & 0xffffff;
1987         if (smu_program == 6) {
1988                 if (fw_version >= 0x3F0800)
1989                         ret = vangogh_get_gpu_metrics_v2_4(smu, table);
1990                 else
1991                         ret = vangogh_get_gpu_metrics_v2_3(smu, table);
1992
1993         } else {
1994                 if (smu->smc_fw_version >= 0x043F3E00) {
1995                         if (smu->smc_fw_if_version < 0x3)
1996                                 ret = vangogh_get_legacy_gpu_metrics_v2_3(smu, table);
1997                         else
1998                                 ret = vangogh_get_gpu_metrics_v2_3(smu, table);
1999                 } else {
2000                         if (smu->smc_fw_if_version < 0x3)
2001                                 ret = vangogh_get_legacy_gpu_metrics(smu, table);
2002                         else
2003                                 ret = vangogh_get_gpu_metrics(smu, table);
2004                 }
2005         }
2006
2007         return ret;
2008 }
2009
2010 static int vangogh_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type,
2011                                         long input[], uint32_t size)
2012 {
2013         int ret = 0;
2014         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
2015
2016         if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
2017                 dev_warn(smu->adev->dev,
2018                         "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n");
2019                 return -EINVAL;
2020         }
2021
2022         switch (type) {
2023         case PP_OD_EDIT_CCLK_VDDC_TABLE:
2024                 if (size != 3) {
2025                         dev_err(smu->adev->dev, "Input parameter number not correct (should be 4 for processor)\n");
2026                         return -EINVAL;
2027                 }
2028                 if (input[0] >= smu->cpu_core_num) {
2029                         dev_err(smu->adev->dev, "core index is overflow, should be less than %d\n",
2030                                 smu->cpu_core_num);
2031                 }
2032                 smu->cpu_core_id_select = input[0];
2033                 if (input[1] == 0) {
2034                         if (input[2] < smu->cpu_default_soft_min_freq) {
2035                                 dev_warn(smu->adev->dev, "Fine grain setting minimum cclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2036                                         input[2], smu->cpu_default_soft_min_freq);
2037                                 return -EINVAL;
2038                         }
2039                         smu->cpu_actual_soft_min_freq = input[2];
2040                 } else if (input[1] == 1) {
2041                         if (input[2] > smu->cpu_default_soft_max_freq) {
2042                                 dev_warn(smu->adev->dev, "Fine grain setting maximum cclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2043                                         input[2], smu->cpu_default_soft_max_freq);
2044                                 return -EINVAL;
2045                         }
2046                         smu->cpu_actual_soft_max_freq = input[2];
2047                 } else {
2048                         return -EINVAL;
2049                 }
2050                 break;
2051         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2052                 if (size != 2) {
2053                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
2054                         return -EINVAL;
2055                 }
2056
2057                 if (input[0] == 0) {
2058                         if (input[1] < smu->gfx_default_hard_min_freq) {
2059                                 dev_warn(smu->adev->dev,
2060                                         "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
2061                                         input[1], smu->gfx_default_hard_min_freq);
2062                                 return -EINVAL;
2063                         }
2064                         smu->gfx_actual_hard_min_freq = input[1];
2065                 } else if (input[0] == 1) {
2066                         if (input[1] > smu->gfx_default_soft_max_freq) {
2067                                 dev_warn(smu->adev->dev,
2068                                         "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
2069                                         input[1], smu->gfx_default_soft_max_freq);
2070                                 return -EINVAL;
2071                         }
2072                         smu->gfx_actual_soft_max_freq = input[1];
2073                 } else {
2074                         return -EINVAL;
2075                 }
2076                 break;
2077         case PP_OD_RESTORE_DEFAULT_TABLE:
2078                 if (size != 0) {
2079                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
2080                         return -EINVAL;
2081                 } else {
2082                         smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
2083                         smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
2084                         smu->cpu_actual_soft_min_freq = smu->cpu_default_soft_min_freq;
2085                         smu->cpu_actual_soft_max_freq = smu->cpu_default_soft_max_freq;
2086                 }
2087                 break;
2088         case PP_OD_COMMIT_DPM_TABLE:
2089                 if (size != 0) {
2090                         dev_err(smu->adev->dev, "Input parameter number not correct\n");
2091                         return -EINVAL;
2092                 } else {
2093                         if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
2094                                 dev_err(smu->adev->dev,
2095                                         "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
2096                                         smu->gfx_actual_hard_min_freq,
2097                                         smu->gfx_actual_soft_max_freq);
2098                                 return -EINVAL;
2099                         }
2100
2101                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
2102                                                                         smu->gfx_actual_hard_min_freq, NULL);
2103                         if (ret) {
2104                                 dev_err(smu->adev->dev, "Set hard min sclk failed!");
2105                                 return ret;
2106                         }
2107
2108                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
2109                                                                         smu->gfx_actual_soft_max_freq, NULL);
2110                         if (ret) {
2111                                 dev_err(smu->adev->dev, "Set soft max sclk failed!");
2112                                 return ret;
2113                         }
2114
2115                         if (smu->adev->pm.fw_version < 0x43f1b00) {
2116                                 dev_warn(smu->adev->dev, "CPUSoftMax/CPUSoftMin are not supported, please update SBIOS!\n");
2117                                 break;
2118                         }
2119
2120                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinCclk,
2121                                                               ((smu->cpu_core_id_select << 20)
2122                                                                | smu->cpu_actual_soft_min_freq),
2123                                                               NULL);
2124                         if (ret) {
2125                                 dev_err(smu->adev->dev, "Set hard min cclk failed!");
2126                                 return ret;
2127                         }
2128
2129                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxCclk,
2130                                                               ((smu->cpu_core_id_select << 20)
2131                                                                | smu->cpu_actual_soft_max_freq),
2132                                                               NULL);
2133                         if (ret) {
2134                                 dev_err(smu->adev->dev, "Set soft max cclk failed!");
2135                                 return ret;
2136                         }
2137                 }
2138                 break;
2139         default:
2140                 return -ENOSYS;
2141         }
2142
2143         return ret;
2144 }
2145
2146 static int vangogh_set_default_dpm_tables(struct smu_context *smu)
2147 {
2148         struct smu_table_context *smu_table = &smu->smu_table;
2149
2150         return smu_cmn_update_table(smu, SMU_TABLE_DPMCLOCKS, 0, smu_table->clocks_table, false);
2151 }
2152
2153 static int vangogh_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
2154 {
2155         DpmClocks_t *clk_table = smu->smu_table.clocks_table;
2156
2157         smu->gfx_default_hard_min_freq = clk_table->MinGfxClk;
2158         smu->gfx_default_soft_max_freq = clk_table->MaxGfxClk;
2159         smu->gfx_actual_hard_min_freq = 0;
2160         smu->gfx_actual_soft_max_freq = 0;
2161
2162         smu->cpu_default_soft_min_freq = 1400;
2163         smu->cpu_default_soft_max_freq = 3500;
2164         smu->cpu_actual_soft_min_freq = 0;
2165         smu->cpu_actual_soft_max_freq = 0;
2166
2167         return 0;
2168 }
2169
2170 static int vangogh_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
2171 {
2172         DpmClocks_t *table = smu->smu_table.clocks_table;
2173         int i;
2174
2175         if (!clock_table || !table)
2176                 return -EINVAL;
2177
2178         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) {
2179                 clock_table->SocClocks[i].Freq = table->SocClocks[i];
2180                 clock_table->SocClocks[i].Vol = table->SocVoltage[i];
2181         }
2182
2183         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
2184                 clock_table->FClocks[i].Freq = table->DfPstateTable[i].fclk;
2185                 clock_table->FClocks[i].Vol = table->DfPstateTable[i].voltage;
2186         }
2187
2188         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
2189                 clock_table->MemClocks[i].Freq = table->DfPstateTable[i].memclk;
2190                 clock_table->MemClocks[i].Vol = table->DfPstateTable[i].voltage;
2191         }
2192
2193         return 0;
2194 }
2195
2196 static int vangogh_notify_rlc_state(struct smu_context *smu, bool en)
2197 {
2198         struct amdgpu_device *adev = smu->adev;
2199         int ret = 0;
2200
2201         if (adev->pm.fw_version >= 0x43f1700 && !en)
2202                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RlcPowerNotify,
2203                                                       RLC_STATUS_OFF, NULL);
2204
2205         return ret;
2206 }
2207
2208 static int vangogh_post_smu_init(struct smu_context *smu)
2209 {
2210         struct amdgpu_device *adev = smu->adev;
2211         uint32_t tmp;
2212         int ret = 0;
2213         uint8_t aon_bits = 0;
2214         /* Two CUs in one WGP */
2215         uint32_t req_active_wgps = adev->gfx.cu_info.number/2;
2216         uint32_t total_cu = adev->gfx.config.max_cu_per_sh *
2217                 adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
2218
2219         /* allow message will be sent after enable message on Vangogh*/
2220         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
2221                         (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
2222                 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL);
2223                 if (ret) {
2224                         dev_err(adev->dev, "Failed to Enable GfxOff!\n");
2225                         return ret;
2226                 }
2227         } else {
2228                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
2229                 dev_info(adev->dev, "If GFX DPM or power gate disabled, disable GFXOFF\n");
2230         }
2231
2232         /* if all CUs are active, no need to power off any WGPs */
2233         if (total_cu == adev->gfx.cu_info.number)
2234                 return 0;
2235
2236         /*
2237          * Calculate the total bits number of always on WGPs for all SA/SEs in
2238          * RLC_PG_ALWAYS_ON_WGP_MASK.
2239          */
2240         tmp = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_ALWAYS_ON_WGP_MASK));
2241         tmp &= RLC_PG_ALWAYS_ON_WGP_MASK__AON_WGP_MASK_MASK;
2242
2243         aon_bits = hweight32(tmp) * adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
2244
2245         /* Do not request any WGPs less than set in the AON_WGP_MASK */
2246         if (aon_bits > req_active_wgps) {
2247                 dev_info(adev->dev, "Number of always on WGPs greater than active WGPs: WGP power save not requested.\n");
2248                 return 0;
2249         } else {
2250                 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_RequestActiveWgp, req_active_wgps, NULL);
2251         }
2252 }
2253
2254 static int vangogh_mode_reset(struct smu_context *smu, int type)
2255 {
2256         int ret = 0, index = 0;
2257
2258         index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
2259                                                SMU_MSG_GfxDeviceDriverReset);
2260         if (index < 0)
2261                 return index == -EACCES ? 0 : index;
2262
2263         mutex_lock(&smu->message_lock);
2264
2265         ret = smu_cmn_send_msg_without_waiting(smu, (uint16_t)index, type);
2266
2267         mutex_unlock(&smu->message_lock);
2268
2269         mdelay(10);
2270
2271         return ret;
2272 }
2273
2274 static int vangogh_mode2_reset(struct smu_context *smu)
2275 {
2276         return vangogh_mode_reset(smu, SMU_RESET_MODE_2);
2277 }
2278
2279 /**
2280  * vangogh_get_gfxoff_status - Get gfxoff status
2281  *
2282  * @smu: amdgpu_device pointer
2283  *
2284  * Get current gfxoff status
2285  *
2286  * Return:
2287  * * 0  - GFXOFF (default if enabled).
2288  * * 1  - Transition out of GFX State.
2289  * * 2  - Not in GFXOFF.
2290  * * 3  - Transition into GFXOFF.
2291  */
2292 static u32 vangogh_get_gfxoff_status(struct smu_context *smu)
2293 {
2294         struct amdgpu_device *adev = smu->adev;
2295         u32 reg, gfxoff_status;
2296
2297         reg = RREG32_SOC15(SMUIO, 0, mmSMUIO_GFX_MISC_CNTL);
2298         gfxoff_status = (reg & SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS_MASK)
2299                 >> SMUIO_GFX_MISC_CNTL__PWR_GFXOFF_STATUS__SHIFT;
2300
2301         return gfxoff_status;
2302 }
2303
2304 static int vangogh_get_power_limit(struct smu_context *smu,
2305                                    uint32_t *current_power_limit,
2306                                    uint32_t *default_power_limit,
2307                                    uint32_t *max_power_limit,
2308                                    uint32_t *min_power_limit)
2309 {
2310         struct smu_11_5_power_context *power_context =
2311                                                                 smu->smu_power.power_context;
2312         uint32_t ppt_limit;
2313         int ret = 0;
2314
2315         if (smu->adev->pm.fw_version < 0x43f1e00)
2316                 return ret;
2317
2318         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetSlowPPTLimit, &ppt_limit);
2319         if (ret) {
2320                 dev_err(smu->adev->dev, "Get slow PPT limit failed!\n");
2321                 return ret;
2322         }
2323         /* convert from milliwatt to watt */
2324         if (current_power_limit)
2325                 *current_power_limit = ppt_limit / 1000;
2326         if (default_power_limit)
2327                 *default_power_limit = ppt_limit / 1000;
2328         if (max_power_limit)
2329                 *max_power_limit = 29;
2330         if (min_power_limit)
2331                 *min_power_limit = 0;
2332
2333         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPPTLimit, &ppt_limit);
2334         if (ret) {
2335                 dev_err(smu->adev->dev, "Get fast PPT limit failed!\n");
2336                 return ret;
2337         }
2338         /* convert from milliwatt to watt */
2339         power_context->current_fast_ppt_limit =
2340                         power_context->default_fast_ppt_limit = ppt_limit / 1000;
2341         power_context->max_fast_ppt_limit = 30;
2342
2343         return ret;
2344 }
2345
2346 static int vangogh_get_ppt_limit(struct smu_context *smu,
2347                                                                 uint32_t *ppt_limit,
2348                                                                 enum smu_ppt_limit_type type,
2349                                                                 enum smu_ppt_limit_level level)
2350 {
2351         struct smu_11_5_power_context *power_context =
2352                                                         smu->smu_power.power_context;
2353
2354         if (!power_context)
2355                 return -EOPNOTSUPP;
2356
2357         if (type == SMU_FAST_PPT_LIMIT) {
2358                 switch (level) {
2359                 case SMU_PPT_LIMIT_MAX:
2360                         *ppt_limit = power_context->max_fast_ppt_limit;
2361                         break;
2362                 case SMU_PPT_LIMIT_CURRENT:
2363                         *ppt_limit = power_context->current_fast_ppt_limit;
2364                         break;
2365                 case SMU_PPT_LIMIT_DEFAULT:
2366                         *ppt_limit = power_context->default_fast_ppt_limit;
2367                         break;
2368                 default:
2369                         break;
2370                 }
2371         }
2372
2373         return 0;
2374 }
2375
2376 static int vangogh_set_power_limit(struct smu_context *smu,
2377                                    enum smu_ppt_limit_type limit_type,
2378                                    uint32_t ppt_limit)
2379 {
2380         struct smu_11_5_power_context *power_context =
2381                         smu->smu_power.power_context;
2382         int ret = 0;
2383
2384         if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
2385                 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
2386                 return -EOPNOTSUPP;
2387         }
2388
2389         switch (limit_type) {
2390         case SMU_DEFAULT_PPT_LIMIT:
2391                 ret = smu_cmn_send_smc_msg_with_param(smu,
2392                                 SMU_MSG_SetSlowPPTLimit,
2393                                 ppt_limit * 1000, /* convert from watt to milliwatt */
2394                                 NULL);
2395                 if (ret)
2396                         return ret;
2397
2398                 smu->current_power_limit = ppt_limit;
2399                 break;
2400         case SMU_FAST_PPT_LIMIT:
2401                 ppt_limit &= ~(SMU_FAST_PPT_LIMIT << 24);
2402                 if (ppt_limit > power_context->max_fast_ppt_limit) {
2403                         dev_err(smu->adev->dev,
2404                                 "New power limit (%d) is over the max allowed %d\n",
2405                                 ppt_limit, power_context->max_fast_ppt_limit);
2406                         return ret;
2407                 }
2408
2409                 ret = smu_cmn_send_smc_msg_with_param(smu,
2410                                 SMU_MSG_SetFastPPTLimit,
2411                                 ppt_limit * 1000, /* convert from watt to milliwatt */
2412                                 NULL);
2413                 if (ret)
2414                         return ret;
2415
2416                 power_context->current_fast_ppt_limit = ppt_limit;
2417                 break;
2418         default:
2419                 return -EINVAL;
2420         }
2421
2422         return ret;
2423 }
2424
2425 /**
2426  * vangogh_set_gfxoff_residency
2427  *
2428  * @smu: amdgpu_device pointer
2429  * @start: start/stop residency log
2430  *
2431  * This function will be used to log gfxoff residency
2432  *
2433  *
2434  * Returns standard response codes.
2435  */
2436 static u32 vangogh_set_gfxoff_residency(struct smu_context *smu, bool start)
2437 {
2438         int ret = 0;
2439         u32 residency;
2440         struct amdgpu_device *adev = smu->adev;
2441
2442         if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
2443                 return 0;
2444
2445         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_LogGfxOffResidency,
2446                                               start, &residency);
2447
2448         if (!start)
2449                 adev->gfx.gfx_off_residency = residency;
2450
2451         return ret;
2452 }
2453
2454 /**
2455  * vangogh_get_gfxoff_residency
2456  *
2457  * @smu: amdgpu_device pointer
2458  * @residency: placeholder for return value
2459  *
2460  * This function will be used to get gfxoff residency.
2461  *
2462  * Returns standard response codes.
2463  */
2464 static u32 vangogh_get_gfxoff_residency(struct smu_context *smu, uint32_t *residency)
2465 {
2466         struct amdgpu_device *adev = smu->adev;
2467
2468         *residency = adev->gfx.gfx_off_residency;
2469
2470         return 0;
2471 }
2472
2473 /**
2474  * vangogh_get_gfxoff_entrycount - get gfxoff entry count
2475  *
2476  * @smu: amdgpu_device pointer
2477  * @entrycount: placeholder for return value
2478  *
2479  * This function will be used to get gfxoff entry count
2480  *
2481  * Returns standard response codes.
2482  */
2483 static u32 vangogh_get_gfxoff_entrycount(struct smu_context *smu, uint64_t *entrycount)
2484 {
2485         int ret = 0, value = 0;
2486         struct amdgpu_device *adev = smu->adev;
2487
2488         if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
2489                 return 0;
2490
2491         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetGfxOffEntryCount, &value);
2492         *entrycount = value + adev->gfx.gfx_off_entrycount;
2493
2494         return ret;
2495 }
2496
2497 static const struct pptable_funcs vangogh_ppt_funcs = {
2498
2499         .check_fw_status = smu_v11_0_check_fw_status,
2500         .check_fw_version = smu_v11_0_check_fw_version,
2501         .init_smc_tables = vangogh_init_smc_tables,
2502         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2503         .init_power = smu_v11_0_init_power,
2504         .fini_power = smu_v11_0_fini_power,
2505         .register_irq_handler = smu_v11_0_register_irq_handler,
2506         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2507         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2508         .send_smc_msg = smu_cmn_send_smc_msg,
2509         .dpm_set_vcn_enable = vangogh_dpm_set_vcn_enable,
2510         .dpm_set_jpeg_enable = vangogh_dpm_set_jpeg_enable,
2511         .is_dpm_running = vangogh_is_dpm_running,
2512         .read_sensor = vangogh_read_sensor,
2513         .get_apu_thermal_limit = vangogh_get_apu_thermal_limit,
2514         .set_apu_thermal_limit = vangogh_set_apu_thermal_limit,
2515         .get_enabled_mask = smu_cmn_get_enabled_mask,
2516         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2517         .set_watermarks_table = vangogh_set_watermarks_table,
2518         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2519         .interrupt_work = smu_v11_0_interrupt_work,
2520         .get_gpu_metrics = vangogh_common_get_gpu_metrics,
2521         .od_edit_dpm_table = vangogh_od_edit_dpm_table,
2522         .print_clk_levels = vangogh_common_print_clk_levels,
2523         .set_default_dpm_table = vangogh_set_default_dpm_tables,
2524         .set_fine_grain_gfx_freq_parameters = vangogh_set_fine_grain_gfx_freq_parameters,
2525         .notify_rlc_state = vangogh_notify_rlc_state,
2526         .feature_is_enabled = smu_cmn_feature_is_enabled,
2527         .set_power_profile_mode = vangogh_set_power_profile_mode,
2528         .get_power_profile_mode = vangogh_get_power_profile_mode,
2529         .get_dpm_clock_table = vangogh_get_dpm_clock_table,
2530         .force_clk_levels = vangogh_force_clk_levels,
2531         .set_performance_level = vangogh_set_performance_level,
2532         .post_init = vangogh_post_smu_init,
2533         .mode2_reset = vangogh_mode2_reset,
2534         .gfx_off_control = smu_v11_0_gfx_off_control,
2535         .get_gfx_off_status = vangogh_get_gfxoff_status,
2536         .get_gfx_off_entrycount = vangogh_get_gfxoff_entrycount,
2537         .get_gfx_off_residency = vangogh_get_gfxoff_residency,
2538         .set_gfx_off_residency = vangogh_set_gfxoff_residency,
2539         .get_ppt_limit = vangogh_get_ppt_limit,
2540         .get_power_limit = vangogh_get_power_limit,
2541         .set_power_limit = vangogh_set_power_limit,
2542         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2543 };
2544
2545 void vangogh_set_ppt_funcs(struct smu_context *smu)
2546 {
2547         smu->ppt_funcs = &vangogh_ppt_funcs;
2548         smu->message_map = vangogh_message_map;
2549         smu->feature_map = vangogh_feature_mask_map;
2550         smu->table_map = vangogh_table_map;
2551         smu->workload_map = vangogh_workload_map;
2552         smu->is_apu = true;
2553         smu_v11_0_set_smu_mailbox_registers(smu);
2554 }