2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/reboot.h>
28 #define SMU_11_0_PARTIAL_PPTABLE
29 #define SWSMU_CODE_LAYER_L3
32 #include "amdgpu_smu.h"
33 #include "atomfirmware.h"
34 #include "amdgpu_atomfirmware.h"
35 #include "amdgpu_atombios.h"
36 #include "smu_v11_0.h"
37 #include "soc15_common.h"
39 #include "amdgpu_ras.h"
42 #include "asic_reg/thm/thm_11_0_2_offset.h"
43 #include "asic_reg/thm/thm_11_0_2_sh_mask.h"
44 #include "asic_reg/mp/mp_11_0_offset.h"
45 #include "asic_reg/mp/mp_11_0_sh_mask.h"
46 #include "asic_reg/smuio/smuio_11_0_0_offset.h"
47 #include "asic_reg/smuio/smuio_11_0_0_sh_mask.h"
50 * DO NOT use these for err/warn/info/debug messages.
51 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
52 * They are more MGPU friendly.
59 MODULE_FIRMWARE("amdgpu/arcturus_smc.bin");
60 MODULE_FIRMWARE("amdgpu/navi10_smc.bin");
61 MODULE_FIRMWARE("amdgpu/navi14_smc.bin");
62 MODULE_FIRMWARE("amdgpu/navi12_smc.bin");
63 MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin");
64 MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin");
65 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_smc.bin");
67 #define SMU11_VOLTAGE_SCALE 4
69 #define SMU11_MODE1_RESET_WAIT_TIME_IN_MS 500 //500ms
71 #define LINK_WIDTH_MAX 6
72 #define LINK_SPEED_MAX 3
74 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x11140288
75 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
76 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
77 #define smnPCIE_LC_SPEED_CNTL 0x11140290
78 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xC000
79 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0xE
81 #define mmTHM_BACO_CNTL_ARCT 0xA7
82 #define mmTHM_BACO_CNTL_ARCT_BASE_IDX 0
84 static int link_width[] = {0, 1, 2, 4, 8, 12, 16};
85 static int link_speed[] = {25, 50, 80, 160};
87 int smu_v11_0_init_microcode(struct smu_context *smu)
89 struct amdgpu_device *adev = smu->adev;
90 const char *chip_name;
91 char fw_name[SMU_FW_NAME_LEN];
93 const struct smc_firmware_header_v1_0 *hdr;
94 const struct common_firmware_header *header;
95 struct amdgpu_firmware_info *ucode = NULL;
97 if (amdgpu_sriov_vf(adev) &&
98 ((adev->asic_type == CHIP_NAVI12) ||
99 (adev->asic_type == CHIP_SIENNA_CICHLID)))
102 switch (adev->asic_type) {
104 chip_name = "arcturus";
107 chip_name = "navi10";
110 chip_name = "navi14";
113 chip_name = "navi12";
115 case CHIP_SIENNA_CICHLID:
116 chip_name = "sienna_cichlid";
118 case CHIP_NAVY_FLOUNDER:
119 chip_name = "navy_flounder";
121 case CHIP_DIMGREY_CAVEFISH:
122 chip_name = "dimgrey_cavefish";
125 dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);
129 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
131 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
134 err = amdgpu_ucode_validate(adev->pm.fw);
138 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
139 amdgpu_ucode_print_smc_hdr(&hdr->header);
140 adev->pm.fw_version = le32_to_cpu(hdr->header.ucode_version);
142 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
143 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
144 ucode->ucode_id = AMDGPU_UCODE_ID_SMC;
145 ucode->fw = adev->pm.fw;
146 header = (const struct common_firmware_header *)ucode->fw->data;
147 adev->firmware.fw_size +=
148 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
153 DRM_ERROR("smu_v11_0: Failed to load firmware \"%s\"\n",
155 release_firmware(adev->pm.fw);
161 void smu_v11_0_fini_microcode(struct smu_context *smu)
163 struct amdgpu_device *adev = smu->adev;
165 release_firmware(adev->pm.fw);
167 adev->pm.fw_version = 0;
170 int smu_v11_0_load_microcode(struct smu_context *smu)
172 struct amdgpu_device *adev = smu->adev;
174 const struct smc_firmware_header_v1_0 *hdr;
175 uint32_t addr_start = MP1_SRAM;
177 uint32_t smc_fw_size;
178 uint32_t mp1_fw_flags;
180 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
181 src = (const uint32_t *)(adev->pm.fw->data +
182 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
183 smc_fw_size = hdr->header.ucode_size_bytes;
185 for (i = 1; i < smc_fw_size/4 - 1; i++) {
186 WREG32_PCIE(addr_start, src[i]);
190 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
191 1 & MP1_SMN_PUB_CTRL__RESET_MASK);
192 WREG32_PCIE(MP1_Public | (smnMP1_PUB_CTRL & 0xffffffff),
193 1 & ~MP1_SMN_PUB_CTRL__RESET_MASK);
195 for (i = 0; i < adev->usec_timeout; i++) {
196 mp1_fw_flags = RREG32_PCIE(MP1_Public |
197 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
198 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
199 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
204 if (i == adev->usec_timeout)
210 int smu_v11_0_check_fw_status(struct smu_context *smu)
212 struct amdgpu_device *adev = smu->adev;
213 uint32_t mp1_fw_flags;
215 mp1_fw_flags = RREG32_PCIE(MP1_Public |
216 (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
218 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
219 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
225 int smu_v11_0_check_fw_version(struct smu_context *smu)
227 struct amdgpu_device *adev = smu->adev;
228 uint32_t if_version = 0xff, smu_version = 0xff;
230 uint8_t smu_minor, smu_debug;
233 ret = smu_cmn_get_smc_version(smu, &if_version, &smu_version);
237 smu_major = (smu_version >> 16) & 0xffff;
238 smu_minor = (smu_version >> 8) & 0xff;
239 smu_debug = (smu_version >> 0) & 0xff;
241 adev->pm.fw_version = smu_version;
243 switch (smu->adev->asic_type) {
245 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_ARCT;
248 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV10;
251 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV12;
254 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_NV14;
256 case CHIP_SIENNA_CICHLID:
257 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;
259 case CHIP_NAVY_FLOUNDER:
260 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder;
263 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_VANGOGH;
265 case CHIP_DIMGREY_CAVEFISH:
266 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish;
269 dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);
270 smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
275 * 1. if_version mismatch is not critical as our fw is designed
276 * to be backward compatible.
277 * 2. New fw usually brings some optimizations. But that's visible
278 * only on the paired driver.
279 * Considering above, we just leave user a warning message instead
280 * of halt driver loading.
282 if (if_version != smu->smc_driver_if_version) {
283 dev_info(smu->adev->dev, "smu driver if version = 0x%08x, smu fw if version = 0x%08x, "
284 "smu fw version = 0x%08x (%d.%d.%d)\n",
285 smu->smc_driver_if_version, if_version,
286 smu_version, smu_major, smu_minor, smu_debug);
287 dev_warn(smu->adev->dev, "SMU driver if version not matched\n");
293 static int smu_v11_0_set_pptable_v2_0(struct smu_context *smu, void **table, uint32_t *size)
295 struct amdgpu_device *adev = smu->adev;
296 uint32_t ppt_offset_bytes;
297 const struct smc_firmware_header_v2_0 *v2;
299 v2 = (const struct smc_firmware_header_v2_0 *) adev->pm.fw->data;
301 ppt_offset_bytes = le32_to_cpu(v2->ppt_offset_bytes);
302 *size = le32_to_cpu(v2->ppt_size_bytes);
303 *table = (uint8_t *)v2 + ppt_offset_bytes;
308 static int smu_v11_0_set_pptable_v2_1(struct smu_context *smu, void **table,
309 uint32_t *size, uint32_t pptable_id)
311 struct amdgpu_device *adev = smu->adev;
312 const struct smc_firmware_header_v2_1 *v2_1;
313 struct smc_soft_pptable_entry *entries;
314 uint32_t pptable_count = 0;
317 v2_1 = (const struct smc_firmware_header_v2_1 *) adev->pm.fw->data;
318 entries = (struct smc_soft_pptable_entry *)
319 ((uint8_t *)v2_1 + le32_to_cpu(v2_1->pptable_entry_offset));
320 pptable_count = le32_to_cpu(v2_1->pptable_count);
321 for (i = 0; i < pptable_count; i++) {
322 if (le32_to_cpu(entries[i].id) == pptable_id) {
323 *table = ((uint8_t *)v2_1 + le32_to_cpu(entries[i].ppt_offset_bytes));
324 *size = le32_to_cpu(entries[i].ppt_size_bytes);
329 if (i == pptable_count)
335 int smu_v11_0_setup_pptable(struct smu_context *smu)
337 struct amdgpu_device *adev = smu->adev;
338 const struct smc_firmware_header_v1_0 *hdr;
341 uint16_t atom_table_size;
344 uint16_t version_major, version_minor;
346 if (!amdgpu_sriov_vf(adev)) {
347 hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;
348 version_major = le16_to_cpu(hdr->header.header_version_major);
349 version_minor = le16_to_cpu(hdr->header.header_version_minor);
350 if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {
351 dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);
352 switch (version_minor) {
354 ret = smu_v11_0_set_pptable_v2_0(smu, &table, &size);
357 ret = smu_v11_0_set_pptable_v2_1(smu, &table, &size,
358 smu->smu_table.boot_values.pp_table_id);
370 dev_info(adev->dev, "use vbios provided pptable\n");
371 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
374 ret = amdgpu_atombios_get_data_table(adev, index, &atom_table_size, &frev, &crev,
378 size = atom_table_size;
381 if (!smu->smu_table.power_play_table)
382 smu->smu_table.power_play_table = table;
383 if (!smu->smu_table.power_play_table_size)
384 smu->smu_table.power_play_table_size = size;
389 int smu_v11_0_init_smc_tables(struct smu_context *smu)
391 struct smu_table_context *smu_table = &smu->smu_table;
392 struct smu_table *tables = smu_table->tables;
395 smu_table->driver_pptable =
396 kzalloc(tables[SMU_TABLE_PPTABLE].size, GFP_KERNEL);
397 if (!smu_table->driver_pptable) {
402 smu_table->max_sustainable_clocks =
403 kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks), GFP_KERNEL);
404 if (!smu_table->max_sustainable_clocks) {
409 /* Arcturus does not support OVERDRIVE */
410 if (tables[SMU_TABLE_OVERDRIVE].size) {
411 smu_table->overdrive_table =
412 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
413 if (!smu_table->overdrive_table) {
418 smu_table->boot_overdrive_table =
419 kzalloc(tables[SMU_TABLE_OVERDRIVE].size, GFP_KERNEL);
420 if (!smu_table->boot_overdrive_table) {
429 kfree(smu_table->overdrive_table);
431 kfree(smu_table->max_sustainable_clocks);
433 kfree(smu_table->driver_pptable);
438 int smu_v11_0_fini_smc_tables(struct smu_context *smu)
440 struct smu_table_context *smu_table = &smu->smu_table;
441 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
443 kfree(smu_table->gpu_metrics_table);
444 kfree(smu_table->boot_overdrive_table);
445 kfree(smu_table->overdrive_table);
446 kfree(smu_table->max_sustainable_clocks);
447 kfree(smu_table->driver_pptable);
448 kfree(smu_table->clocks_table);
449 smu_table->gpu_metrics_table = NULL;
450 smu_table->boot_overdrive_table = NULL;
451 smu_table->overdrive_table = NULL;
452 smu_table->max_sustainable_clocks = NULL;
453 smu_table->driver_pptable = NULL;
454 smu_table->clocks_table = NULL;
455 kfree(smu_table->hardcode_pptable);
456 smu_table->hardcode_pptable = NULL;
458 kfree(smu_table->metrics_table);
459 kfree(smu_table->watermarks_table);
460 smu_table->metrics_table = NULL;
461 smu_table->watermarks_table = NULL;
462 smu_table->metrics_time = 0;
464 kfree(smu_dpm->dpm_context);
465 kfree(smu_dpm->golden_dpm_context);
466 kfree(smu_dpm->dpm_current_power_state);
467 kfree(smu_dpm->dpm_request_power_state);
468 smu_dpm->dpm_context = NULL;
469 smu_dpm->golden_dpm_context = NULL;
470 smu_dpm->dpm_context_size = 0;
471 smu_dpm->dpm_current_power_state = NULL;
472 smu_dpm->dpm_request_power_state = NULL;
477 int smu_v11_0_init_power(struct smu_context *smu)
479 struct smu_power_context *smu_power = &smu->smu_power;
480 size_t size = smu->adev->asic_type == CHIP_VANGOGH ?
481 sizeof(struct smu_11_5_power_context) :
482 sizeof(struct smu_11_0_power_context);
484 smu_power->power_context = kzalloc(size, GFP_KERNEL);
485 if (!smu_power->power_context)
487 smu_power->power_context_size = size;
492 int smu_v11_0_fini_power(struct smu_context *smu)
494 struct smu_power_context *smu_power = &smu->smu_power;
496 kfree(smu_power->power_context);
497 smu_power->power_context = NULL;
498 smu_power->power_context_size = 0;
503 static int smu_v11_0_atom_get_smu_clockinfo(struct amdgpu_device *adev,
508 struct atom_get_smu_clock_info_parameters_v3_1 input = {0};
509 struct atom_get_smu_clock_info_output_parameters_v3_1 *output;
512 input.clk_id = clk_id;
513 input.syspll_id = syspll_id;
514 input.command = GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ;
515 index = get_index_into_master_table(atom_master_list_of_command_functions_v2_1,
518 ret = amdgpu_atom_execute_table(adev->mode_info.atom_context, index,
523 output = (struct atom_get_smu_clock_info_output_parameters_v3_1 *)&input;
524 *clk_freq = le32_to_cpu(output->atom_smu_outputclkfreq.smu_clock_freq_hz) / 10000;
529 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu)
534 struct atom_common_table_header *header;
535 struct atom_firmware_info_v3_3 *v_3_3;
536 struct atom_firmware_info_v3_1 *v_3_1;
538 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
541 ret = amdgpu_atombios_get_data_table(smu->adev, index, &size, &frev, &crev,
542 (uint8_t **)&header);
546 if (header->format_revision != 3) {
547 dev_err(smu->adev->dev, "unknown atom_firmware_info version! for smu11\n");
551 switch (header->content_revision) {
555 v_3_1 = (struct atom_firmware_info_v3_1 *)header;
556 smu->smu_table.boot_values.revision = v_3_1->firmware_revision;
557 smu->smu_table.boot_values.gfxclk = v_3_1->bootup_sclk_in10khz;
558 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
559 smu->smu_table.boot_values.socclk = 0;
560 smu->smu_table.boot_values.dcefclk = 0;
561 smu->smu_table.boot_values.vddc = v_3_1->bootup_vddc_mv;
562 smu->smu_table.boot_values.vddci = v_3_1->bootup_vddci_mv;
563 smu->smu_table.boot_values.mvddc = v_3_1->bootup_mvddc_mv;
564 smu->smu_table.boot_values.vdd_gfx = v_3_1->bootup_vddgfx_mv;
565 smu->smu_table.boot_values.cooling_id = v_3_1->coolingsolution_id;
566 smu->smu_table.boot_values.pp_table_id = 0;
567 smu->smu_table.boot_values.firmware_caps = v_3_1->firmware_capability;
571 v_3_3 = (struct atom_firmware_info_v3_3 *)header;
572 smu->smu_table.boot_values.revision = v_3_3->firmware_revision;
573 smu->smu_table.boot_values.gfxclk = v_3_3->bootup_sclk_in10khz;
574 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
575 smu->smu_table.boot_values.socclk = 0;
576 smu->smu_table.boot_values.dcefclk = 0;
577 smu->smu_table.boot_values.vddc = v_3_3->bootup_vddc_mv;
578 smu->smu_table.boot_values.vddci = v_3_3->bootup_vddci_mv;
579 smu->smu_table.boot_values.mvddc = v_3_3->bootup_mvddc_mv;
580 smu->smu_table.boot_values.vdd_gfx = v_3_3->bootup_vddgfx_mv;
581 smu->smu_table.boot_values.cooling_id = v_3_3->coolingsolution_id;
582 smu->smu_table.boot_values.pp_table_id = v_3_3->pplib_pptable_id;
583 smu->smu_table.boot_values.firmware_caps = v_3_3->firmware_capability;
586 smu->smu_table.boot_values.format_revision = header->format_revision;
587 smu->smu_table.boot_values.content_revision = header->content_revision;
589 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
590 (uint8_t)SMU11_SYSPLL0_SOCCLK_ID,
592 &smu->smu_table.boot_values.socclk);
594 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
595 (uint8_t)SMU11_SYSPLL0_DCEFCLK_ID,
597 &smu->smu_table.boot_values.dcefclk);
599 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
600 (uint8_t)SMU11_SYSPLL0_ECLK_ID,
602 &smu->smu_table.boot_values.eclk);
604 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
605 (uint8_t)SMU11_SYSPLL0_VCLK_ID,
607 &smu->smu_table.boot_values.vclk);
609 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
610 (uint8_t)SMU11_SYSPLL0_DCLK_ID,
612 &smu->smu_table.boot_values.dclk);
614 if ((smu->smu_table.boot_values.format_revision == 3) &&
615 (smu->smu_table.boot_values.content_revision >= 2))
616 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
617 (uint8_t)SMU11_SYSPLL1_0_FCLK_ID,
618 (uint8_t)SMU11_SYSPLL1_2_ID,
619 &smu->smu_table.boot_values.fclk);
621 smu_v11_0_atom_get_smu_clockinfo(smu->adev,
622 (uint8_t)SMU11_SYSPLL3_1_LCLK_ID,
623 (uint8_t)SMU11_SYSPLL3_1_ID,
624 &smu->smu_table.boot_values.lclk);
629 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu)
631 struct smu_table_context *smu_table = &smu->smu_table;
632 struct smu_table *memory_pool = &smu_table->memory_pool;
635 uint32_t address_low, address_high;
637 if (memory_pool->size == 0 || memory_pool->cpu_addr == NULL)
640 address = (uintptr_t)memory_pool->cpu_addr;
641 address_high = (uint32_t)upper_32_bits(address);
642 address_low = (uint32_t)lower_32_bits(address);
644 ret = smu_cmn_send_smc_msg_with_param(smu,
645 SMU_MSG_SetSystemVirtualDramAddrHigh,
650 ret = smu_cmn_send_smc_msg_with_param(smu,
651 SMU_MSG_SetSystemVirtualDramAddrLow,
657 address = memory_pool->mc_address;
658 address_high = (uint32_t)upper_32_bits(address);
659 address_low = (uint32_t)lower_32_bits(address);
661 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrHigh,
665 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramAddrLow,
669 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DramLogSetDramSize,
670 (uint32_t)memory_pool->size, NULL);
677 int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk)
681 ret = smu_cmn_send_smc_msg_with_param(smu,
682 SMU_MSG_SetMinDeepSleepDcefclk, clk, NULL);
684 dev_err(smu->adev->dev, "SMU11 attempt to set divider for DCEFCLK Failed!");
689 int smu_v11_0_set_driver_table_location(struct smu_context *smu)
691 struct smu_table *driver_table = &smu->smu_table.driver_table;
694 if (driver_table->mc_address) {
695 ret = smu_cmn_send_smc_msg_with_param(smu,
696 SMU_MSG_SetDriverDramAddrHigh,
697 upper_32_bits(driver_table->mc_address),
700 ret = smu_cmn_send_smc_msg_with_param(smu,
701 SMU_MSG_SetDriverDramAddrLow,
702 lower_32_bits(driver_table->mc_address),
709 int smu_v11_0_set_tool_table_location(struct smu_context *smu)
712 struct smu_table *tool_table = &smu->smu_table.tables[SMU_TABLE_PMSTATUSLOG];
714 if (tool_table->mc_address) {
715 ret = smu_cmn_send_smc_msg_with_param(smu,
716 SMU_MSG_SetToolsDramAddrHigh,
717 upper_32_bits(tool_table->mc_address),
720 ret = smu_cmn_send_smc_msg_with_param(smu,
721 SMU_MSG_SetToolsDramAddrLow,
722 lower_32_bits(tool_table->mc_address),
729 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)
731 struct amdgpu_device *adev = smu->adev;
733 /* Navy_Flounder/Dimgrey_Cavefish do not support to change
734 * display num currently
736 if (adev->asic_type >= CHIP_NAVY_FLOUNDER &&
737 adev->asic_type <= CHIP_DIMGREY_CAVEFISH)
740 return smu_cmn_send_smc_msg_with_param(smu,
741 SMU_MSG_NumOfDisplays,
747 int smu_v11_0_set_allowed_mask(struct smu_context *smu)
749 struct smu_feature *feature = &smu->smu_feature;
751 uint32_t feature_mask[2];
753 if (bitmap_empty(feature->allowed, SMU_FEATURE_MAX) || feature->feature_num < 64)
756 bitmap_copy((unsigned long *)feature_mask, feature->allowed, 64);
758 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskHigh,
759 feature_mask[1], NULL);
763 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetAllowedFeaturesMaskLow,
764 feature_mask[0], NULL);
772 int smu_v11_0_system_features_control(struct smu_context *smu,
775 struct smu_feature *feature = &smu->smu_feature;
776 uint32_t feature_mask[2];
779 ret = smu_cmn_send_smc_msg(smu, (en ? SMU_MSG_EnableAllSmuFeatures :
780 SMU_MSG_DisableAllSmuFeatures), NULL);
784 bitmap_zero(feature->enabled, feature->feature_num);
785 bitmap_zero(feature->supported, feature->feature_num);
788 ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
792 bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
793 feature->feature_num);
794 bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
795 feature->feature_num);
801 int smu_v11_0_notify_display_change(struct smu_context *smu)
805 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
806 smu->adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM)
807 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetUclkFastSwitch, 1, NULL);
813 smu_v11_0_get_max_sustainable_clock(struct smu_context *smu, uint32_t *clock,
814 enum smu_clk_type clock_select)
819 if ((smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetDcModeMaxDpmFreq) < 0) ||
820 (smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG, SMU_MSG_GetMaxDpmFreq) < 0))
823 clk_id = smu_cmn_to_asic_specific_index(smu,
824 CMN2ASIC_MAPPING_CLK,
829 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetDcModeMaxDpmFreq,
830 clk_id << 16, clock);
832 dev_err(smu->adev->dev, "[GetMaxSustainableClock] Failed to get max DC clock from SMC!");
839 /* if DC limit is zero, return AC limit */
840 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq,
841 clk_id << 16, clock);
843 dev_err(smu->adev->dev, "[GetMaxSustainableClock] failed to get max AC clock from SMC!");
850 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
852 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
853 smu->smu_table.max_sustainable_clocks;
856 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
857 max_sustainable_clocks->soc_clock = smu->smu_table.boot_values.socclk / 100;
858 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100;
859 max_sustainable_clocks->display_clock = 0xFFFFFFFF;
860 max_sustainable_clocks->phy_clock = 0xFFFFFFFF;
861 max_sustainable_clocks->pixel_clock = 0xFFFFFFFF;
863 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
864 ret = smu_v11_0_get_max_sustainable_clock(smu,
865 &(max_sustainable_clocks->uclock),
868 dev_err(smu->adev->dev, "[%s] failed to get max UCLK from SMC!",
874 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
875 ret = smu_v11_0_get_max_sustainable_clock(smu,
876 &(max_sustainable_clocks->soc_clock),
879 dev_err(smu->adev->dev, "[%s] failed to get max SOCCLK from SMC!",
885 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
886 ret = smu_v11_0_get_max_sustainable_clock(smu,
887 &(max_sustainable_clocks->dcef_clock),
890 dev_err(smu->adev->dev, "[%s] failed to get max DCEFCLK from SMC!",
895 ret = smu_v11_0_get_max_sustainable_clock(smu,
896 &(max_sustainable_clocks->display_clock),
899 dev_err(smu->adev->dev, "[%s] failed to get max DISPCLK from SMC!",
903 ret = smu_v11_0_get_max_sustainable_clock(smu,
904 &(max_sustainable_clocks->phy_clock),
907 dev_err(smu->adev->dev, "[%s] failed to get max PHYCLK from SMC!",
911 ret = smu_v11_0_get_max_sustainable_clock(smu,
912 &(max_sustainable_clocks->pixel_clock),
915 dev_err(smu->adev->dev, "[%s] failed to get max PIXCLK from SMC!",
921 if (max_sustainable_clocks->soc_clock < max_sustainable_clocks->uclock)
922 max_sustainable_clocks->uclock = max_sustainable_clocks->soc_clock;
927 int smu_v11_0_get_current_power_limit(struct smu_context *smu,
928 uint32_t *power_limit)
933 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT))
936 power_src = smu_cmn_to_asic_specific_index(smu,
937 CMN2ASIC_MAPPING_PWR,
938 smu->adev->pm.ac_power ?
939 SMU_POWER_SOURCE_AC :
940 SMU_POWER_SOURCE_DC);
945 * BIT 24-31: ControllerId (only PPT0 is supported for now)
946 * BIT 16-23: PowerSource
948 ret = smu_cmn_send_smc_msg_with_param(smu,
950 (0 << 24) | (power_src << 16),
953 dev_err(smu->adev->dev, "[%s] get PPT limit failed!", __func__);
958 int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n)
963 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_PPT_BIT)) {
964 dev_err(smu->adev->dev, "Setting new power limit is not supported!\n");
968 power_src = smu_cmn_to_asic_specific_index(smu,
969 CMN2ASIC_MAPPING_PWR,
970 smu->adev->pm.ac_power ?
971 SMU_POWER_SOURCE_AC :
972 SMU_POWER_SOURCE_DC);
977 * BIT 24-31: ControllerId (only PPT0 is supported for now)
978 * BIT 16-23: PowerSource
979 * BIT 0-15: PowerLimit
983 n |= (power_src) << 16;
984 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPptLimit, n, NULL);
986 dev_err(smu->adev->dev, "[%s] Set power limit Failed!\n", __func__);
990 smu->current_power_limit = n;
995 static int smu_v11_0_ack_ac_dc_interrupt(struct smu_context *smu)
997 return smu_cmn_send_smc_msg(smu,
998 SMU_MSG_ReenableAcDcInterrupt,
1002 static int smu_v11_0_process_pending_interrupt(struct smu_context *smu)
1006 if (smu->dc_controlled_by_gpio &&
1007 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT))
1008 ret = smu_v11_0_ack_ac_dc_interrupt(smu);
1013 void smu_v11_0_interrupt_work(struct smu_context *smu)
1015 if (smu_v11_0_ack_ac_dc_interrupt(smu))
1016 dev_err(smu->adev->dev, "Ack AC/DC interrupt Failed!\n");
1019 int smu_v11_0_enable_thermal_alert(struct smu_context *smu)
1023 if (smu->smu_table.thermal_controller_type) {
1024 ret = amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
1030 * After init there might have been missed interrupts triggered
1031 * before driver registers for interrupt (Ex. AC/DC).
1033 return smu_v11_0_process_pending_interrupt(smu);
1036 int smu_v11_0_disable_thermal_alert(struct smu_context *smu)
1038 return amdgpu_irq_put(smu->adev, &smu->irq_source, 0);
1041 static uint16_t convert_to_vddc(uint8_t vid)
1043 return (uint16_t) ((6200 - (vid * 25)) / SMU11_VOLTAGE_SCALE);
1046 int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value)
1048 struct amdgpu_device *adev = smu->adev;
1049 uint32_t vdd = 0, val_vid = 0;
1053 val_vid = (RREG32_SOC15(SMUIO, 0, mmSMUSVI0_TEL_PLANE0) &
1054 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR_MASK) >>
1055 SMUSVI0_TEL_PLANE0__SVI0_PLANE0_VDDCOR__SHIFT;
1057 vdd = (uint32_t)convert_to_vddc((uint8_t)val_vid);
1066 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
1067 struct pp_display_clock_request
1070 enum amd_pp_clock_type clk_type = clock_req->clock_type;
1072 enum smu_clk_type clk_select = 0;
1073 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1075 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) ||
1076 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1078 case amd_pp_dcef_clock:
1079 clk_select = SMU_DCEFCLK;
1081 case amd_pp_disp_clock:
1082 clk_select = SMU_DISPCLK;
1084 case amd_pp_pixel_clock:
1085 clk_select = SMU_PIXCLK;
1087 case amd_pp_phy_clock:
1088 clk_select = SMU_PHYCLK;
1090 case amd_pp_mem_clock:
1091 clk_select = SMU_UCLK;
1094 dev_info(smu->adev->dev, "[%s] Invalid Clock Type!", __func__);
1102 if (clk_select == SMU_UCLK && smu->disable_uclk_switch)
1105 ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0);
1107 if(clk_select == SMU_UCLK)
1108 smu->hard_min_uclk_req_from_dal = clk_freq;
1115 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable)
1118 struct amdgpu_device *adev = smu->adev;
1120 switch (adev->asic_type) {
1124 case CHIP_SIENNA_CICHLID:
1125 case CHIP_NAVY_FLOUNDER:
1126 case CHIP_DIMGREY_CAVEFISH:
1128 if (!(adev->pm.pp_feature & PP_GFXOFF_MASK))
1131 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_AllowGfxOff, NULL);
1133 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_DisallowGfxOff, NULL);
1143 smu_v11_0_get_fan_control_mode(struct smu_context *smu)
1145 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1146 return AMD_FAN_CTRL_AUTO;
1148 return smu->user_dpm_profile.fan_mode;
1152 smu_v11_0_auto_fan_control(struct smu_context *smu, bool auto_fan_control)
1156 if (!smu_cmn_feature_is_supported(smu, SMU_FEATURE_FAN_CONTROL_BIT))
1159 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_FAN_CONTROL_BIT, auto_fan_control);
1161 dev_err(smu->adev->dev, "[%s]%s smc FAN CONTROL feature failed!",
1162 __func__, (auto_fan_control ? "Start" : "Stop"));
1168 smu_v11_0_set_fan_static_mode(struct smu_context *smu, uint32_t mode)
1170 struct amdgpu_device *adev = smu->adev;
1172 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1173 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1174 CG_FDO_CTRL2, TMIN, 0));
1175 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2,
1176 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2),
1177 CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1183 smu_v11_0_set_fan_speed_percent(struct smu_context *smu, uint32_t speed)
1185 struct amdgpu_device *adev = smu->adev;
1186 uint32_t duty100, duty;
1192 if (smu_v11_0_auto_fan_control(smu, 0))
1195 duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1),
1196 CG_FDO_CTRL1, FMAX_DUTY100);
1200 tmp64 = (uint64_t)speed * duty100;
1202 duty = (uint32_t)tmp64;
1204 WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0,
1205 REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0),
1206 CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1208 return smu_v11_0_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1212 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
1218 case AMD_FAN_CTRL_NONE:
1219 ret = smu_v11_0_set_fan_speed_percent(smu, 100);
1221 case AMD_FAN_CTRL_MANUAL:
1222 ret = smu_v11_0_auto_fan_control(smu, 0);
1224 case AMD_FAN_CTRL_AUTO:
1225 ret = smu_v11_0_auto_fan_control(smu, 1);
1232 dev_err(smu->adev->dev, "[%s]Set fan control mode failed!", __func__);
1239 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
1242 return smu_cmn_send_smc_msg_with_param(smu,
1243 SMU_MSG_SetXgmiMode,
1244 pstate ? XGMI_MODE_PSTATE_D0 : XGMI_MODE_PSTATE_D3,
1248 static int smu_v11_0_set_irq_state(struct amdgpu_device *adev,
1249 struct amdgpu_irq_src *source,
1251 enum amdgpu_interrupt_state state)
1253 struct smu_context *smu = &adev->smu;
1258 case AMDGPU_IRQ_STATE_DISABLE:
1260 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1261 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 1);
1262 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 1);
1263 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1265 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, 0);
1267 /* For MP1 SW irqs */
1268 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1269 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1270 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1273 case AMDGPU_IRQ_STATE_ENABLE:
1275 low = max(SMU_THERMAL_MINIMUM_ALERT_TEMP,
1276 smu->thermal_range.min / SMU_TEMPERATURE_UNITS_PER_CENTIGRADES);
1277 high = min(SMU_THERMAL_MAXIMUM_ALERT_TEMP,
1278 smu->thermal_range.software_shutdown_temp);
1280 val = RREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL);
1281 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, MAX_IH_CREDIT, 5);
1282 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_IH_HW_ENA, 1);
1283 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTH_MASK, 0);
1284 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, THERM_INTL_MASK, 0);
1285 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTH, (high & 0xff));
1286 val = REG_SET_FIELD(val, THM_THERMAL_INT_CTRL, DIG_THERM_INTL, (low & 0xff));
1287 val = val & (~THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK);
1288 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_CTRL, val);
1290 val = (1 << THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT);
1291 val |= (1 << THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT);
1292 val |= (1 << THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT);
1293 WREG32_SOC15(THM, 0, mmTHM_THERMAL_INT_ENA, val);
1295 /* For MP1 SW irqs */
1296 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT);
1297 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1298 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1299 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT, val);
1301 val = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1302 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1303 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, val);
1313 #define THM_11_0__SRCID__THM_DIG_THERM_L2H 0 /* ASIC_TEMP > CG_THERMAL_INT.DIG_THERM_INTH */
1314 #define THM_11_0__SRCID__THM_DIG_THERM_H2L 1 /* ASIC_TEMP < CG_THERMAL_INT.DIG_THERM_INTL */
1316 #define SMUIO_11_0__SRCID__SMUIO_GPIO19 83
1318 static int smu_v11_0_irq_process(struct amdgpu_device *adev,
1319 struct amdgpu_irq_src *source,
1320 struct amdgpu_iv_entry *entry)
1322 struct smu_context *smu = &adev->smu;
1323 uint32_t client_id = entry->client_id;
1324 uint32_t src_id = entry->src_id;
1326 * ctxid is used to distinguish different
1327 * events for SMCToHost interrupt.
1329 uint32_t ctxid = entry->src_data[0];
1332 if (client_id == SOC15_IH_CLIENTID_THM) {
1334 case THM_11_0__SRCID__THM_DIG_THERM_L2H:
1335 dev_emerg(adev->dev, "ERROR: GPU over temperature range(SW CTF) detected!\n");
1337 * SW CTF just occurred.
1338 * Try to do a graceful shutdown to prevent further damage.
1340 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU SW CTF!\n");
1341 orderly_poweroff(true);
1343 case THM_11_0__SRCID__THM_DIG_THERM_H2L:
1344 dev_emerg(adev->dev, "ERROR: GPU under temperature range detected\n");
1347 dev_emerg(adev->dev, "ERROR: GPU under temperature range unknown src id (%d)\n",
1351 } else if (client_id == SOC15_IH_CLIENTID_ROM_SMUIO) {
1352 dev_emerg(adev->dev, "ERROR: GPU HW Critical Temperature Fault(aka CTF) detected!\n");
1354 * HW CTF just occurred. Shutdown to prevent further damage.
1356 dev_emerg(adev->dev, "ERROR: System is going to shutdown due to GPU HW CTF!\n");
1357 orderly_poweroff(true);
1358 } else if (client_id == SOC15_IH_CLIENTID_MP1) {
1359 if (src_id == 0xfe) {
1360 /* ACK SMUToHost interrupt */
1361 data = RREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL);
1362 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1363 WREG32_SOC15(MP1, 0, mmMP1_SMN_IH_SW_INT_CTRL, data);
1367 dev_dbg(adev->dev, "Switched to AC mode!\n");
1368 schedule_work(&smu->interrupt_work);
1371 dev_dbg(adev->dev, "Switched to DC mode!\n");
1372 schedule_work(&smu->interrupt_work);
1376 * Increment the throttle interrupt counter
1378 atomic64_inc(&smu->throttle_int_counter);
1380 if (!atomic_read(&adev->throttling_logging_enabled))
1383 if (__ratelimit(&adev->throttling_logging_rs))
1384 schedule_work(&smu->throttling_logging_work);
1394 static const struct amdgpu_irq_src_funcs smu_v11_0_irq_funcs =
1396 .set = smu_v11_0_set_irq_state,
1397 .process = smu_v11_0_irq_process,
1400 int smu_v11_0_register_irq_handler(struct smu_context *smu)
1402 struct amdgpu_device *adev = smu->adev;
1403 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1406 irq_src->num_types = 1;
1407 irq_src->funcs = &smu_v11_0_irq_funcs;
1409 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1410 THM_11_0__SRCID__THM_DIG_THERM_L2H,
1415 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_THM,
1416 THM_11_0__SRCID__THM_DIG_THERM_H2L,
1421 /* Register CTF(GPIO_19) interrupt */
1422 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_ROM_SMUIO,
1423 SMUIO_11_0__SRCID__SMUIO_GPIO19,
1428 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1437 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
1438 struct pp_smu_nv_clock_table *max_clocks)
1440 struct smu_table_context *table_context = &smu->smu_table;
1441 struct smu_11_0_max_sustainable_clocks *sustainable_clocks = NULL;
1443 if (!max_clocks || !table_context->max_sustainable_clocks)
1446 sustainable_clocks = table_context->max_sustainable_clocks;
1448 max_clocks->dcfClockInKhz =
1449 (unsigned int) sustainable_clocks->dcef_clock * 1000;
1450 max_clocks->displayClockInKhz =
1451 (unsigned int) sustainable_clocks->display_clock * 1000;
1452 max_clocks->phyClockInKhz =
1453 (unsigned int) sustainable_clocks->phy_clock * 1000;
1454 max_clocks->pixelClockInKhz =
1455 (unsigned int) sustainable_clocks->pixel_clock * 1000;
1456 max_clocks->uClockInKhz =
1457 (unsigned int) sustainable_clocks->uclock * 1000;
1458 max_clocks->socClockInKhz =
1459 (unsigned int) sustainable_clocks->soc_clock * 1000;
1460 max_clocks->dscClockInKhz = 0;
1461 max_clocks->dppClockInKhz = 0;
1462 max_clocks->fabricClockInKhz = 0;
1467 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu)
1469 return smu_cmn_send_smc_msg(smu, SMU_MSG_BacoAudioD3PME, NULL);
1472 static int smu_v11_0_baco_set_armd3_sequence(struct smu_context *smu, enum smu_v11_0_baco_seq baco_seq)
1474 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ArmD3, baco_seq, NULL);
1477 bool smu_v11_0_baco_is_support(struct smu_context *smu)
1479 struct smu_baco_context *smu_baco = &smu->smu_baco;
1481 if (!smu_baco->platform_support)
1484 /* Arcturus does not support this bit mask */
1485 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_BACO_BIT) &&
1486 !smu_cmn_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT))
1492 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu)
1494 struct smu_baco_context *smu_baco = &smu->smu_baco;
1495 enum smu_baco_state baco_state;
1497 mutex_lock(&smu_baco->mutex);
1498 baco_state = smu_baco->state;
1499 mutex_unlock(&smu_baco->mutex);
1504 #define D3HOT_BACO_SEQUENCE 0
1505 #define D3HOT_BAMACO_SEQUENCE 2
1507 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state)
1509 struct smu_baco_context *smu_baco = &smu->smu_baco;
1510 struct amdgpu_device *adev = smu->adev;
1511 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1515 if (smu_v11_0_baco_get_state(smu) == state)
1518 mutex_lock(&smu_baco->mutex);
1520 if (state == SMU_BACO_STATE_ENTER) {
1521 switch (adev->asic_type) {
1522 case CHIP_SIENNA_CICHLID:
1523 case CHIP_NAVY_FLOUNDER:
1524 case CHIP_DIMGREY_CAVEFISH:
1525 if (amdgpu_runtime_pm == 2)
1526 ret = smu_cmn_send_smc_msg_with_param(smu,
1528 D3HOT_BAMACO_SEQUENCE,
1531 ret = smu_cmn_send_smc_msg_with_param(smu,
1533 D3HOT_BACO_SEQUENCE,
1537 if (!ras || !ras->supported) {
1538 if (adev->asic_type == CHIP_ARCTURUS) {
1539 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT);
1541 WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT, data);
1543 data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL);
1545 WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data);
1548 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 0, NULL);
1550 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_EnterBaco, 1, NULL);
1556 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_ExitBaco, NULL);
1560 /* clear vbios scratch 6 and 7 for coming asic reinit */
1561 WREG32(adev->bios_scratch_reg_offset + 6, 0);
1562 WREG32(adev->bios_scratch_reg_offset + 7, 0);
1567 smu_baco->state = state;
1569 mutex_unlock(&smu_baco->mutex);
1573 int smu_v11_0_baco_enter(struct smu_context *smu)
1575 struct amdgpu_device *adev = smu->adev;
1578 /* Arcturus does not need this audio workaround */
1579 if (adev->asic_type != CHIP_ARCTURUS) {
1580 ret = smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
1585 ret = smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_ENTER);
1594 int smu_v11_0_baco_exit(struct smu_context *smu)
1596 return smu_v11_0_baco_set_state(smu, SMU_BACO_STATE_EXIT);
1599 int smu_v11_0_mode1_reset(struct smu_context *smu)
1603 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_Mode1Reset, NULL);
1605 msleep(SMU11_MODE1_RESET_WAIT_TIME_IN_MS);
1610 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
1611 uint32_t *min, uint32_t *max)
1613 int ret = 0, clk_id = 0;
1615 uint32_t clock_limit;
1617 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
1621 clock_limit = smu->smu_table.boot_values.uclk;
1625 clock_limit = smu->smu_table.boot_values.gfxclk;
1628 clock_limit = smu->smu_table.boot_values.socclk;
1635 /* clock in Mhz unit */
1637 *min = clock_limit / 100;
1639 *max = clock_limit / 100;
1644 clk_id = smu_cmn_to_asic_specific_index(smu,
1645 CMN2ASIC_MAPPING_CLK,
1651 param = (clk_id & 0xffff) << 16;
1654 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMaxDpmFreq, param, max);
1660 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetMinDpmFreq, param, min);
1669 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu,
1670 enum smu_clk_type clk_type,
1674 struct amdgpu_device *adev = smu->adev;
1675 int ret = 0, clk_id = 0;
1678 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1681 clk_id = smu_cmn_to_asic_specific_index(smu,
1682 CMN2ASIC_MAPPING_CLK,
1687 if (clk_type == SMU_GFXCLK)
1688 amdgpu_gfx_off_ctrl(adev, false);
1691 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1692 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxByFreq,
1699 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1700 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinByFreq,
1707 if (clk_type == SMU_GFXCLK)
1708 amdgpu_gfx_off_ctrl(adev, true);
1713 int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
1714 enum smu_clk_type clk_type,
1718 int ret = 0, clk_id = 0;
1721 if (min <= 0 && max <= 0)
1724 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1727 clk_id = smu_cmn_to_asic_specific_index(smu,
1728 CMN2ASIC_MAPPING_CLK,
1734 param = (uint32_t)((clk_id << 16) | (max & 0xffff));
1735 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMaxByFreq,
1742 param = (uint32_t)((clk_id << 16) | (min & 0xffff));
1743 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinByFreq,
1752 int smu_v11_0_set_performance_level(struct smu_context *smu,
1753 enum amd_dpm_forced_level level)
1755 struct smu_11_0_dpm_context *dpm_context =
1756 smu->smu_dpm.dpm_context;
1757 struct smu_11_0_dpm_table *gfx_table =
1758 &dpm_context->dpm_tables.gfx_table;
1759 struct smu_11_0_dpm_table *mem_table =
1760 &dpm_context->dpm_tables.uclk_table;
1761 struct smu_11_0_dpm_table *soc_table =
1762 &dpm_context->dpm_tables.soc_table;
1763 struct smu_umd_pstate_table *pstate_table =
1765 struct amdgpu_device *adev = smu->adev;
1766 uint32_t sclk_min = 0, sclk_max = 0;
1767 uint32_t mclk_min = 0, mclk_max = 0;
1768 uint32_t socclk_min = 0, socclk_max = 0;
1772 case AMD_DPM_FORCED_LEVEL_HIGH:
1773 sclk_min = sclk_max = gfx_table->max;
1774 mclk_min = mclk_max = mem_table->max;
1775 socclk_min = socclk_max = soc_table->max;
1777 case AMD_DPM_FORCED_LEVEL_LOW:
1778 sclk_min = sclk_max = gfx_table->min;
1779 mclk_min = mclk_max = mem_table->min;
1780 socclk_min = socclk_max = soc_table->min;
1782 case AMD_DPM_FORCED_LEVEL_AUTO:
1783 sclk_min = gfx_table->min;
1784 sclk_max = gfx_table->max;
1785 mclk_min = mem_table->min;
1786 mclk_max = mem_table->max;
1787 socclk_min = soc_table->min;
1788 socclk_max = soc_table->max;
1790 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1791 sclk_min = sclk_max = pstate_table->gfxclk_pstate.standard;
1792 mclk_min = mclk_max = pstate_table->uclk_pstate.standard;
1793 socclk_min = socclk_max = pstate_table->socclk_pstate.standard;
1795 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1796 sclk_min = sclk_max = pstate_table->gfxclk_pstate.min;
1798 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1799 mclk_min = mclk_max = pstate_table->uclk_pstate.min;
1801 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1802 sclk_min = sclk_max = pstate_table->gfxclk_pstate.peak;
1803 mclk_min = mclk_max = pstate_table->uclk_pstate.peak;
1804 socclk_min = socclk_max = pstate_table->socclk_pstate.peak;
1806 case AMD_DPM_FORCED_LEVEL_MANUAL:
1807 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1810 dev_err(adev->dev, "Invalid performance level %d\n", level);
1815 * Separate MCLK and SOCCLK soft min/max settings are not allowed
1818 if (adev->asic_type == CHIP_ARCTURUS) {
1819 mclk_min = mclk_max = 0;
1820 socclk_min = socclk_max = 0;
1823 if (sclk_min && sclk_max) {
1824 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1832 if (mclk_min && mclk_max) {
1833 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1841 if (socclk_min && socclk_max) {
1842 ret = smu_v11_0_set_soft_freq_limited_range(smu,
1853 int smu_v11_0_set_power_source(struct smu_context *smu,
1854 enum smu_power_src_type power_src)
1858 pwr_source = smu_cmn_to_asic_specific_index(smu,
1859 CMN2ASIC_MAPPING_PWR,
1860 (uint32_t)power_src);
1864 return smu_cmn_send_smc_msg_with_param(smu,
1865 SMU_MSG_NotifyPowerSource,
1870 int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu,
1871 enum smu_clk_type clk_type,
1875 int ret = 0, clk_id = 0;
1881 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type))
1884 clk_id = smu_cmn_to_asic_specific_index(smu,
1885 CMN2ASIC_MAPPING_CLK,
1890 param = (uint32_t)(((clk_id & 0xffff) << 16) | (level & 0xffff));
1892 ret = smu_cmn_send_smc_msg_with_param(smu,
1893 SMU_MSG_GetDpmFreqByIndex,
1900 * BIT31: 0 - Fine grained DPM, 1 - Dicrete DPM
1901 * now, we un-support it
1903 *value = *value & 0x7fffffff;
1908 int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
1909 enum smu_clk_type clk_type,
1912 return smu_v11_0_get_dpm_freq_by_index(smu,
1918 int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
1919 enum smu_clk_type clk_type,
1920 struct smu_11_0_dpm_table *single_dpm_table)
1926 ret = smu_v11_0_get_dpm_level_count(smu,
1928 &single_dpm_table->count);
1930 dev_err(smu->adev->dev, "[%s] failed to get dpm levels!\n", __func__);
1934 for (i = 0; i < single_dpm_table->count; i++) {
1935 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1940 dev_err(smu->adev->dev, "[%s] failed to get dpm freq by index!\n", __func__);
1944 single_dpm_table->dpm_levels[i].value = clk;
1945 single_dpm_table->dpm_levels[i].enabled = true;
1948 single_dpm_table->min = clk;
1949 else if (i == single_dpm_table->count - 1)
1950 single_dpm_table->max = clk;
1956 int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
1957 enum smu_clk_type clk_type,
1958 uint32_t *min_value,
1959 uint32_t *max_value)
1961 uint32_t level_count = 0;
1964 if (!min_value && !max_value)
1968 /* by default, level 0 clock value as min value */
1969 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1978 ret = smu_v11_0_get_dpm_level_count(smu,
1984 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1995 int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu)
1997 struct amdgpu_device *adev = smu->adev;
1999 return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2000 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2001 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2004 int smu_v11_0_get_current_pcie_link_width(struct smu_context *smu)
2006 uint32_t width_level;
2008 width_level = smu_v11_0_get_current_pcie_link_width_level(smu);
2009 if (width_level > LINK_WIDTH_MAX)
2012 return link_width[width_level];
2015 int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu)
2017 struct amdgpu_device *adev = smu->adev;
2019 return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2020 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2021 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2024 int smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu)
2026 uint32_t speed_level;
2028 speed_level = smu_v11_0_get_current_pcie_link_speed_level(smu);
2029 if (speed_level > LINK_SPEED_MAX)
2032 return link_speed[speed_level];
2035 int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
2040 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
2041 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
2046 int smu_v11_0_deep_sleep_control(struct smu_context *smu,
2049 struct amdgpu_device *adev = smu->adev;
2052 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
2053 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
2055 dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
2060 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
2061 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
2063 dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
2068 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
2069 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
2071 dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
2076 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
2077 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
2079 dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
2084 if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
2085 ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
2087 dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");