drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include <linux/pci.h>
  28 #include <linux/i2c.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_smu.h"
  31 #include "atomfirmware.h"
  32 #include "amdgpu_atomfirmware.h"
  33 #include "amdgpu_atombios.h"
  34 #include "smu_v11_0.h"
  35 #include "smu11_driver_if_sienna_cichlid.h"
  36 #include "soc15_common.h"
  37 #include "atom.h"
  38 #include "sienna_cichlid_ppt.h"
  39 #include "smu_v11_0_7_pptable.h"
  40 #include "smu_v11_0_7_ppsmc.h"
  41 #include "nbio/nbio_2_3_offset.h"
  42 #include "nbio/nbio_2_3_sh_mask.h"
  43 #include "thm/thm_11_0_2_offset.h"
  44 #include "thm/thm_11_0_2_sh_mask.h"
  45 #include "mp/mp_11_0_offset.h"
  46 #include "mp/mp_11_0_sh_mask.h"
  47
  48 #include "asic_reg/mp/mp_11_0_sh_mask.h"
  49 #include "smu_cmn.h"
  50
  51 /*
  52  * DO NOT use these for err/warn/info/debug messages.
  53  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  54  * They are more MGPU friendly.
  55  */
  56 #undef pr_err
  57 #undef pr_warn
  58 #undef pr_info
  59 #undef pr_debug
  60
  61 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  62
  63 #define FEATURE_MASK(feature) (1ULL << feature)
  64 #define SMC_DPM_FEATURE ( \
  65         FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
  66         FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT)     | \
  67         FEATURE_MASK(FEATURE_DPM_UCLK_BIT)       | \
  68         FEATURE_MASK(FEATURE_DPM_LINK_BIT)       | \
  69         FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT)     | \
  70         FEATURE_MASK(FEATURE_DPM_FCLK_BIT)       | \
  71         FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT)    | \
  72         FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT))
  73
  74 #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
  75
  76 #define GET_PPTABLE_MEMBER(field, member) do {\
  77         if (smu->adev->asic_type == CHIP_BEIGE_GOBY)\
  78                 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_beige_goby_t, field));\
  79         else\
  80                 (*member) = (smu->smu_table.driver_pptable + offsetof(PPTable_t, field));\
  81 } while(0)
  82
  83 static int get_table_size(struct smu_context *smu)
  84 {
  85         if (smu->adev->asic_type == CHIP_BEIGE_GOBY)
  86                 return sizeof(PPTable_beige_goby_t);
  87         else
  88                 return sizeof(PPTable_t);
  89 }
  90
  91 static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
  92         MSG_MAP(TestMessage,                    PPSMC_MSG_TestMessage,                 1),
  93         MSG_MAP(GetSmuVersion,                  PPSMC_MSG_GetSmuVersion,               1),
  94         MSG_MAP(GetDriverIfVersion,             PPSMC_MSG_GetDriverIfVersion,          1),
  95         MSG_MAP(SetAllowedFeaturesMaskLow,      PPSMC_MSG_SetAllowedFeaturesMaskLow,   0),
  96         MSG_MAP(SetAllowedFeaturesMaskHigh,     PPSMC_MSG_SetAllowedFeaturesMaskHigh,  0),
  97         MSG_MAP(EnableAllSmuFeatures,           PPSMC_MSG_EnableAllSmuFeatures,        0),
  98         MSG_MAP(DisableAllSmuFeatures,          PPSMC_MSG_DisableAllSmuFeatures,       0),
  99         MSG_MAP(EnableSmuFeaturesLow,           PPSMC_MSG_EnableSmuFeaturesLow,        1),
 100         MSG_MAP(EnableSmuFeaturesHigh,          PPSMC_MSG_EnableSmuFeaturesHigh,       1),
 101         MSG_MAP(DisableSmuFeaturesLow,          PPSMC_MSG_DisableSmuFeaturesLow,       1),
 102         MSG_MAP(DisableSmuFeaturesHigh,         PPSMC_MSG_DisableSmuFeaturesHigh,      1),
 103         MSG_MAP(GetEnabledSmuFeaturesLow,       PPSMC_MSG_GetRunningSmuFeaturesLow,    1),
 104         MSG_MAP(GetEnabledSmuFeaturesHigh,      PPSMC_MSG_GetRunningSmuFeaturesHigh,   1),
 105         MSG_MAP(SetWorkloadMask,                PPSMC_MSG_SetWorkloadMask,             1),
 106         MSG_MAP(SetPptLimit,                    PPSMC_MSG_SetPptLimit,                 0),
 107         MSG_MAP(SetDriverDramAddrHigh,          PPSMC_MSG_SetDriverDramAddrHigh,       1),
 108         MSG_MAP(SetDriverDramAddrLow,           PPSMC_MSG_SetDriverDramAddrLow,        1),
 109         MSG_MAP(SetToolsDramAddrHigh,           PPSMC_MSG_SetToolsDramAddrHigh,        0),
 110         MSG_MAP(SetToolsDramAddrLow,            PPSMC_MSG_SetToolsDramAddrLow,         0),
 111         MSG_MAP(TransferTableSmu2Dram,          PPSMC_MSG_TransferTableSmu2Dram,       1),
 112         MSG_MAP(TransferTableDram2Smu,          PPSMC_MSG_TransferTableDram2Smu,       0),
 113         MSG_MAP(UseDefaultPPTable,              PPSMC_MSG_UseDefaultPPTable,           0),
 114         MSG_MAP(RunDcBtc,                       PPSMC_MSG_RunDcBtc,                    0),
 115         MSG_MAP(EnterBaco,                      PPSMC_MSG_EnterBaco,                   0),
 116         MSG_MAP(SetSoftMinByFreq,               PPSMC_MSG_SetSoftMinByFreq,            1),
 117         MSG_MAP(SetSoftMaxByFreq,               PPSMC_MSG_SetSoftMaxByFreq,            1),
 118         MSG_MAP(SetHardMinByFreq,               PPSMC_MSG_SetHardMinByFreq,            1),
 119         MSG_MAP(SetHardMaxByFreq,               PPSMC_MSG_SetHardMaxByFreq,            0),
 120         MSG_MAP(GetMinDpmFreq,                  PPSMC_MSG_GetMinDpmFreq,               1),
 121         MSG_MAP(GetMaxDpmFreq,                  PPSMC_MSG_GetMaxDpmFreq,               1),
 122         MSG_MAP(GetDpmFreqByIndex,              PPSMC_MSG_GetDpmFreqByIndex,           1),
 123         MSG_MAP(SetGeminiMode,                  PPSMC_MSG_SetGeminiMode,               0),
 124         MSG_MAP(SetGeminiApertureHigh,          PPSMC_MSG_SetGeminiApertureHigh,       0),
 125         MSG_MAP(SetGeminiApertureLow,           PPSMC_MSG_SetGeminiApertureLow,        0),
 126         MSG_MAP(OverridePcieParameters,         PPSMC_MSG_OverridePcieParameters,      0),
 127         MSG_MAP(ReenableAcDcInterrupt,          PPSMC_MSG_ReenableAcDcInterrupt,       0),
 128         MSG_MAP(NotifyPowerSource,              PPSMC_MSG_NotifyPowerSource,           0),
 129         MSG_MAP(SetUclkFastSwitch,              PPSMC_MSG_SetUclkFastSwitch,           0),
 130         MSG_MAP(SetVideoFps,                    PPSMC_MSG_SetVideoFps,                 0),
 131         MSG_MAP(PrepareMp1ForUnload,            PPSMC_MSG_PrepareMp1ForUnload,         1),
 132         MSG_MAP(AllowGfxOff,                    PPSMC_MSG_AllowGfxOff,                 0),
 133         MSG_MAP(DisallowGfxOff,                 PPSMC_MSG_DisallowGfxOff,              0),
 134         MSG_MAP(GetPptLimit,                    PPSMC_MSG_GetPptLimit,                 0),
 135         MSG_MAP(GetDcModeMaxDpmFreq,            PPSMC_MSG_GetDcModeMaxDpmFreq,         1),
 136         MSG_MAP(ExitBaco,                       PPSMC_MSG_ExitBaco,                    0),
 137         MSG_MAP(PowerUpVcn,                     PPSMC_MSG_PowerUpVcn,                  0),
 138         MSG_MAP(PowerDownVcn,                   PPSMC_MSG_PowerDownVcn,                0),
 139         MSG_MAP(PowerUpJpeg,                    PPSMC_MSG_PowerUpJpeg,                 0),
 140         MSG_MAP(PowerDownJpeg,                  PPSMC_MSG_PowerDownJpeg,               0),
 141         MSG_MAP(BacoAudioD3PME,                 PPSMC_MSG_BacoAudioD3PME,              0),
 142         MSG_MAP(ArmD3,                          PPSMC_MSG_ArmD3,                       0),
 143         MSG_MAP(Mode1Reset,                     PPSMC_MSG_Mode1Reset,                  0),
 144         MSG_MAP(SetMGpuFanBoostLimitRpm,        PPSMC_MSG_SetMGpuFanBoostLimitRpm,     0),
 145         MSG_MAP(SetGpoFeaturePMask,             PPSMC_MSG_SetGpoFeaturePMask,          0),
 146         MSG_MAP(DisallowGpo,                    PPSMC_MSG_DisallowGpo,                 0),
 147         MSG_MAP(Enable2ndUSB20Port,             PPSMC_MSG_Enable2ndUSB20Port,          0),
 148 };
 149
 150 static struct cmn2asic_mapping sienna_cichlid_clk_map[SMU_CLK_COUNT] = {
 151         CLK_MAP(GFXCLK,         PPCLK_GFXCLK),
 152         CLK_MAP(SCLK,           PPCLK_GFXCLK),
 153         CLK_MAP(SOCCLK,         PPCLK_SOCCLK),
 154         CLK_MAP(FCLK,           PPCLK_FCLK),
 155         CLK_MAP(UCLK,           PPCLK_UCLK),
 156         CLK_MAP(MCLK,           PPCLK_UCLK),
 157         CLK_MAP(DCLK,           PPCLK_DCLK_0),
 158         CLK_MAP(DCLK1,          PPCLK_DCLK_1),
 159         CLK_MAP(VCLK,           PPCLK_VCLK_0),
 160         CLK_MAP(VCLK1,          PPCLK_VCLK_1),
 161         CLK_MAP(DCEFCLK,        PPCLK_DCEFCLK),
 162         CLK_MAP(DISPCLK,        PPCLK_DISPCLK),
 163         CLK_MAP(PIXCLK,         PPCLK_PIXCLK),
 164         CLK_MAP(PHYCLK,         PPCLK_PHYCLK),
 165 };
 166
 167 static struct cmn2asic_mapping sienna_cichlid_feature_mask_map[SMU_FEATURE_COUNT] = {
 168         FEA_MAP(DPM_PREFETCHER),
 169         FEA_MAP(DPM_GFXCLK),
 170         FEA_MAP(DPM_GFX_GPO),
 171         FEA_MAP(DPM_UCLK),
 172         FEA_MAP(DPM_FCLK),
 173         FEA_MAP(DPM_SOCCLK),
 174         FEA_MAP(DPM_MP0CLK),
 175         FEA_MAP(DPM_LINK),
 176         FEA_MAP(DPM_DCEFCLK),
 177         FEA_MAP(DPM_XGMI),
 178         FEA_MAP(MEM_VDDCI_SCALING),
 179         FEA_MAP(MEM_MVDD_SCALING),
 180         FEA_MAP(DS_GFXCLK),
 181         FEA_MAP(DS_SOCCLK),
 182         FEA_MAP(DS_FCLK),
 183         FEA_MAP(DS_LCLK),
 184         FEA_MAP(DS_DCEFCLK),
 185         FEA_MAP(DS_UCLK),
 186         FEA_MAP(GFX_ULV),
 187         FEA_MAP(FW_DSTATE),
 188         FEA_MAP(GFXOFF),
 189         FEA_MAP(BACO),
 190         FEA_MAP(MM_DPM_PG),
 191         FEA_MAP(RSMU_SMN_CG),
 192         FEA_MAP(PPT),
 193         FEA_MAP(TDC),
 194         FEA_MAP(APCC_PLUS),
 195         FEA_MAP(GTHR),
 196         FEA_MAP(ACDC),
 197         FEA_MAP(VR0HOT),
 198         FEA_MAP(VR1HOT),
 199         FEA_MAP(FW_CTF),
 200         FEA_MAP(FAN_CONTROL),
 201         FEA_MAP(THERMAL),
 202         FEA_MAP(GFX_DCS),
 203         FEA_MAP(RM),
 204         FEA_MAP(LED_DISPLAY),
 205         FEA_MAP(GFX_SS),
 206         FEA_MAP(OUT_OF_BAND_MONITOR),
 207         FEA_MAP(TEMP_DEPENDENT_VMIN),
 208         FEA_MAP(MMHUB_PG),
 209         FEA_MAP(ATHUB_PG),
 210         FEA_MAP(APCC_DFLL),
 211 };
 212
 213 static struct cmn2asic_mapping sienna_cichlid_table_map[SMU_TABLE_COUNT] = {
 214         TAB_MAP(PPTABLE),
 215         TAB_MAP(WATERMARKS),
 216         TAB_MAP(AVFS_PSM_DEBUG),
 217         TAB_MAP(AVFS_FUSE_OVERRIDE),
 218         TAB_MAP(PMSTATUSLOG),
 219         TAB_MAP(SMU_METRICS),
 220         TAB_MAP(DRIVER_SMU_CONFIG),
 221         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 222         TAB_MAP(OVERDRIVE),
 223         TAB_MAP(I2C_COMMANDS),
 224         TAB_MAP(PACE),
 225 };
 226
 227 static struct cmn2asic_mapping sienna_cichlid_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 228         PWR_MAP(AC),
 229         PWR_MAP(DC),
 230 };
 231
 232 static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 233         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 234         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D,         WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
 235         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 236         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 237         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR,                   WORKLOAD_PPLIB_VR_BIT),
 238         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 239         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 240 };
 241
 242 static const uint8_t sienna_cichlid_throttler_map[] = {
 243         [THROTTLER_TEMP_EDGE_BIT]       = (SMU_THROTTLER_TEMP_EDGE_BIT),
 244         [THROTTLER_TEMP_HOTSPOT_BIT]    = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
 245         [THROTTLER_TEMP_MEM_BIT]        = (SMU_THROTTLER_TEMP_MEM_BIT),
 246         [THROTTLER_TEMP_VR_GFX_BIT]     = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
 247         [THROTTLER_TEMP_VR_MEM0_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
 248         [THROTTLER_TEMP_VR_MEM1_BIT]    = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
 249         [THROTTLER_TEMP_VR_SOC_BIT]     = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
 250         [THROTTLER_TEMP_LIQUID0_BIT]    = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
 251         [THROTTLER_TEMP_LIQUID1_BIT]    = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
 252         [THROTTLER_TDC_GFX_BIT]         = (SMU_THROTTLER_TDC_GFX_BIT),
 253         [THROTTLER_TDC_SOC_BIT]         = (SMU_THROTTLER_TDC_SOC_BIT),
 254         [THROTTLER_PPT0_BIT]            = (SMU_THROTTLER_PPT0_BIT),
 255         [THROTTLER_PPT1_BIT]            = (SMU_THROTTLER_PPT1_BIT),
 256         [THROTTLER_PPT2_BIT]            = (SMU_THROTTLER_PPT2_BIT),
 257         [THROTTLER_PPT3_BIT]            = (SMU_THROTTLER_PPT3_BIT),
 258         [THROTTLER_FIT_BIT]             = (SMU_THROTTLER_FIT_BIT),
 259         [THROTTLER_PPM_BIT]             = (SMU_THROTTLER_PPM_BIT),
 260         [THROTTLER_APCC_BIT]            = (SMU_THROTTLER_APCC_BIT),
 261 };
 262
 263 static int
 264 sienna_cichlid_get_allowed_feature_mask(struct smu_context *smu,
 265                                   uint32_t *feature_mask, uint32_t num)
 266 {
 267         struct amdgpu_device *adev = smu->adev;
 268
 269         if (num > 2)
 270                 return -EINVAL;
 271
 272         memset(feature_mask, 0, sizeof(uint32_t) * num);
 273
 274         *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
 275                                 | FEATURE_MASK(FEATURE_DPM_FCLK_BIT)
 276                                 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
 277                                 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
 278                                 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
 279                                 | FEATURE_MASK(FEATURE_DS_FCLK_BIT)
 280                                 | FEATURE_MASK(FEATURE_DS_UCLK_BIT)
 281                                 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
 282                                 | FEATURE_MASK(FEATURE_DF_CSTATE_BIT)
 283                                 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
 284                                 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
 285                                 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
 286                                 | FEATURE_MASK(FEATURE_PPT_BIT)
 287                                 | FEATURE_MASK(FEATURE_TDC_BIT)
 288                                 | FEATURE_MASK(FEATURE_BACO_BIT)
 289                                 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
 290                                 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
 291                                 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
 292                                 | FEATURE_MASK(FEATURE_THERMAL_BIT)
 293                                 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT);
 294
 295         if (adev->pm.pp_feature & PP_SCLK_DPM_MASK) {
 296                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
 297                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_GPO_BIT);
 298         }
 299
 300         if ((adev->pm.pp_feature & PP_GFX_DCS_MASK) &&
 301             (adev->asic_type > CHIP_SIENNA_CICHLID) &&
 302             !(adev->flags & AMD_IS_APU))
 303                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_DCS_BIT);
 304
 305         if (adev->pm.pp_feature & PP_MCLK_DPM_MASK)
 306                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
 307                                         | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
 308                                         | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
 309
 310         if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
 311                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
 312
 313         if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
 314                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
 315
 316         if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
 317                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
 318
 319         if (adev->pm.pp_feature & PP_ULV_MASK)
 320                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
 321
 322         if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
 323                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
 324
 325         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 326                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
 327
 328         if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
 329                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
 330
 331         if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
 332                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
 333
 334         if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN ||
 335             smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
 336                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MM_DPM_PG_BIT);
 337
 338         if (smu->dc_controlled_by_gpio)
 339        *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
 340
 341         if (amdgpu_aspm)
 342                 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_LCLK_BIT);
 343
 344         return 0;
 345 }
 346
 347 static void sienna_cichlid_check_bxco_support(struct smu_context *smu)
 348 {
 349         struct smu_table_context *table_context = &smu->smu_table;
 350         struct smu_11_0_7_powerplay_table *powerplay_table =
 351                 table_context->power_play_table;
 352         struct smu_baco_context *smu_baco = &smu->smu_baco;
 353         struct amdgpu_device *adev = smu->adev;
 354         uint32_t val;
 355
 356         if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_BACO ||
 357             powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_MACO) {
 358                 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
 359                 smu_baco->platform_support =
 360                         (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
 361                                                                         false;
 362         }
 363 }
 364
 365 static int sienna_cichlid_check_powerplay_table(struct smu_context *smu)
 366 {
 367         struct smu_table_context *table_context = &smu->smu_table;
 368         struct smu_11_0_7_powerplay_table *powerplay_table =
 369                 table_context->power_play_table;
 370
 371         if (powerplay_table->platform_caps & SMU_11_0_7_PP_PLATFORM_CAP_HARDWAREDC)
 372                 smu->dc_controlled_by_gpio = true;
 373
 374         sienna_cichlid_check_bxco_support(smu);
 375
 376         table_context->thermal_controller_type =
 377                 powerplay_table->thermal_controller_type;
 378
 379         /*
 380          * Instead of having its own buffer space and get overdrive_table copied,
 381          * smu->od_settings just points to the actual overdrive_table
 382          */
 383         smu->od_settings = &powerplay_table->overdrive_table;
 384
 385         return 0;
 386 }
 387
 388 static int sienna_cichlid_append_powerplay_table(struct smu_context *smu)
 389 {
 390         struct atom_smc_dpm_info_v4_9 *smc_dpm_table;
 391         int index, ret;
 392         I2cControllerConfig_t *table_member;
 393
 394         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 395                                             smc_dpm_info);
 396
 397         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 398                                       (uint8_t **)&smc_dpm_table);
 399         if (ret)
 400                 return ret;
 401         GET_PPTABLE_MEMBER(I2cControllers, &table_member);
 402         memcpy(table_member, smc_dpm_table->I2cControllers,
 403                         sizeof(*smc_dpm_table) - sizeof(smc_dpm_table->table_header));
 404
 405         return 0;
 406 }
 407
 408 static int sienna_cichlid_store_powerplay_table(struct smu_context *smu)
 409 {
 410         struct smu_table_context *table_context = &smu->smu_table;
 411         struct smu_11_0_7_powerplay_table *powerplay_table =
 412                 table_context->power_play_table;
 413         int table_size;
 414
 415         table_size = get_table_size(smu);
 416         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 417                table_size);
 418
 419         return 0;
 420 }
 421
 422 static int sienna_cichlid_setup_pptable(struct smu_context *smu)
 423 {
 424         int ret = 0;
 425
 426         ret = smu_v11_0_setup_pptable(smu);
 427         if (ret)
 428                 return ret;
 429
 430         ret = sienna_cichlid_store_powerplay_table(smu);
 431         if (ret)
 432                 return ret;
 433
 434         ret = sienna_cichlid_append_powerplay_table(smu);
 435         if (ret)
 436                 return ret;
 437
 438         ret = sienna_cichlid_check_powerplay_table(smu);
 439         if (ret)
 440                 return ret;
 441
 442         return ret;
 443 }
 444
 445 static int sienna_cichlid_tables_init(struct smu_context *smu)
 446 {
 447         struct smu_table_context *smu_table = &smu->smu_table;
 448         struct smu_table *tables = smu_table->tables;
 449         int table_size;
 450
 451         table_size = get_table_size(smu);
 452         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, table_size,
 453                                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 454         SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
 455                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 456         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetricsExternal_t),
 457                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 458         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 459                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 460         SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
 461                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 462         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 463                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 464         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 465                        sizeof(DpmActivityMonitorCoeffIntExternal_t), PAGE_SIZE,
 466                        AMDGPU_GEM_DOMAIN_VRAM);
 467
 468         smu_table->metrics_table = kzalloc(sizeof(SmuMetricsExternal_t), GFP_KERNEL);
 469         if (!smu_table->metrics_table)
 470                 goto err0_out;
 471         smu_table->metrics_time = 0;
 472
 473         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 474         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 475         if (!smu_table->gpu_metrics_table)
 476                 goto err1_out;
 477
 478         smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
 479         if (!smu_table->watermarks_table)
 480                 goto err2_out;
 481
 482         return 0;
 483
 484 err2_out:
 485         kfree(smu_table->gpu_metrics_table);
 486 err1_out:
 487         kfree(smu_table->metrics_table);
 488 err0_out:
 489         return -ENOMEM;
 490 }
 491
 492 static uint32_t sienna_cichlid_get_throttler_status_locked(struct smu_context *smu)
 493 {
 494         struct smu_table_context *smu_table= &smu->smu_table;
 495         SmuMetricsExternal_t *metrics_ext =
 496                 (SmuMetricsExternal_t *)(smu_table->metrics_table);
 497         uint32_t throttler_status = 0;
 498         int i;
 499
 500         if ((smu->adev->asic_type == CHIP_SIENNA_CICHLID) &&
 501              (smu->smc_fw_version >= 0x3A4300)) {
 502                 for (i = 0; i < THROTTLER_COUNT; i++)
 503                         throttler_status |=
 504                                 (metrics_ext->SmuMetrics_V2.ThrottlingPercentage[i] ? 1U << i : 0);
 505         } else {
 506                 throttler_status = metrics_ext->SmuMetrics.ThrottlerStatus;
 507         }
 508
 509         return throttler_status;
 510 }
 511
 512 static int sienna_cichlid_get_smu_metrics_data(struct smu_context *smu,
 513                                                MetricsMember_t member,
 514                                                uint32_t *value)
 515 {
 516         struct smu_table_context *smu_table= &smu->smu_table;
 517         SmuMetrics_t *metrics =
 518                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics);
 519         SmuMetrics_V2_t *metrics_v2 =
 520                 &(((SmuMetricsExternal_t *)(smu_table->metrics_table))->SmuMetrics_V2);
 521         bool use_metrics_v2 = ((smu->adev->asic_type == CHIP_SIENNA_CICHLID) &&
 522                 (smu->smc_fw_version >= 0x3A4300)) ? true : false;
 523         uint16_t average_gfx_activity;
 524         int ret = 0;
 525
 526         mutex_lock(&smu->metrics_lock);
 527
 528         ret = smu_cmn_get_metrics_table_locked(smu,
 529                                                NULL,
 530                                                false);
 531         if (ret) {
 532                 mutex_unlock(&smu->metrics_lock);
 533                 return ret;
 534         }
 535
 536         switch (member) {
 537         case METRICS_CURR_GFXCLK:
 538                 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] :
 539                         metrics->CurrClock[PPCLK_GFXCLK];
 540                 break;
 541         case METRICS_CURR_SOCCLK:
 542                 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] :
 543                         metrics->CurrClock[PPCLK_SOCCLK];
 544                 break;
 545         case METRICS_CURR_UCLK:
 546                 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] :
 547                         metrics->CurrClock[PPCLK_UCLK];
 548                 break;
 549         case METRICS_CURR_VCLK:
 550                 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] :
 551                         metrics->CurrClock[PPCLK_VCLK_0];
 552                 break;
 553         case METRICS_CURR_VCLK1:
 554                 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] :
 555                         metrics->CurrClock[PPCLK_VCLK_1];
 556                 break;
 557         case METRICS_CURR_DCLK:
 558                 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] :
 559                         metrics->CurrClock[PPCLK_DCLK_0];
 560                 break;
 561         case METRICS_CURR_DCLK1:
 562                 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] :
 563                         metrics->CurrClock[PPCLK_DCLK_1];
 564                 break;
 565         case METRICS_CURR_DCEFCLK:
 566                 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCEFCLK] :
 567                         metrics->CurrClock[PPCLK_DCEFCLK];
 568                 break;
 569         case METRICS_CURR_FCLK:
 570                 *value = use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_FCLK] :
 571                         metrics->CurrClock[PPCLK_FCLK];
 572                 break;
 573         case METRICS_AVERAGE_GFXCLK:
 574                 average_gfx_activity = use_metrics_v2 ? metrics_v2->AverageGfxActivity :
 575                         metrics->AverageGfxActivity;
 576                 if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
 577                         *value = use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs :
 578                                 metrics->AverageGfxclkFrequencyPostDs;
 579                 else
 580                         *value = use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs :
 581                                 metrics->AverageGfxclkFrequencyPreDs;
 582                 break;
 583         case METRICS_AVERAGE_FCLK:
 584                 *value = use_metrics_v2 ? metrics_v2->AverageFclkFrequencyPostDs :
 585                         metrics->AverageFclkFrequencyPostDs;
 586                 break;
 587         case METRICS_AVERAGE_UCLK:
 588                 *value = use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs :
 589                         metrics->AverageUclkFrequencyPostDs;
 590                 break;
 591         case METRICS_AVERAGE_GFXACTIVITY:
 592                 *value = use_metrics_v2 ? metrics_v2->AverageGfxActivity :
 593                         metrics->AverageGfxActivity;
 594                 break;
 595         case METRICS_AVERAGE_MEMACTIVITY:
 596                 *value = use_metrics_v2 ? metrics_v2->AverageUclkActivity :
 597                         metrics->AverageUclkActivity;
 598                 break;
 599         case METRICS_AVERAGE_SOCKETPOWER:
 600                 *value = use_metrics_v2 ? metrics_v2->AverageSocketPower << 8 :
 601                         metrics->AverageSocketPower << 8;
 602                 break;
 603         case METRICS_TEMPERATURE_EDGE:
 604                 *value = (use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge) *
 605                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 606                 break;
 607         case METRICS_TEMPERATURE_HOTSPOT:
 608                 *value = (use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot) *
 609                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 610                 break;
 611         case METRICS_TEMPERATURE_MEM:
 612                 *value = (use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem) *
 613                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 614                 break;
 615         case METRICS_TEMPERATURE_VRGFX:
 616                 *value = (use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx) *
 617                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 618                 break;
 619         case METRICS_TEMPERATURE_VRSOC:
 620                 *value = (use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc) *
 621                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 622                 break;
 623         case METRICS_THROTTLER_STATUS:
 624                 *value = sienna_cichlid_get_throttler_status_locked(smu);
 625                 break;
 626         case METRICS_CURR_FANSPEED:
 627                 *value = use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
 628                 break;
 629         default:
 630                 *value = UINT_MAX;
 631                 break;
 632         }
 633
 634         mutex_unlock(&smu->metrics_lock);
 635
 636         return ret;
 637
 638 }
 639
 640 static int sienna_cichlid_allocate_dpm_context(struct smu_context *smu)
 641 {
 642         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 643
 644         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 645                                        GFP_KERNEL);
 646         if (!smu_dpm->dpm_context)
 647                 return -ENOMEM;
 648
 649         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 650
 651         return 0;
 652 }
 653
 654 static int sienna_cichlid_init_smc_tables(struct smu_context *smu)
 655 {
 656         int ret = 0;
 657
 658         ret = sienna_cichlid_tables_init(smu);
 659         if (ret)
 660                 return ret;
 661
 662         ret = sienna_cichlid_allocate_dpm_context(smu);
 663         if (ret)
 664                 return ret;
 665
 666         return smu_v11_0_init_smc_tables(smu);
 667 }
 668
 669 static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
 670 {
 671         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 672         struct smu_11_0_dpm_table *dpm_table;
 673         struct amdgpu_device *adev = smu->adev;
 674         int ret = 0;
 675         DpmDescriptor_t *table_member;
 676
 677         /* socclk dpm table setup */
 678         dpm_table = &dpm_context->dpm_tables.soc_table;
 679         GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
 680         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 681                 ret = smu_v11_0_set_single_dpm_table(smu,
 682                                                      SMU_SOCCLK,
 683                                                      dpm_table);
 684                 if (ret)
 685                         return ret;
 686                 dpm_table->is_fine_grained =
 687                         !table_member[PPCLK_SOCCLK].SnapToDiscrete;
 688         } else {
 689                 dpm_table->count = 1;
 690                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 691                 dpm_table->dpm_levels[0].enabled = true;
 692                 dpm_table->min = dpm_table->dpm_levels[0].value;
 693                 dpm_table->max = dpm_table->dpm_levels[0].value;
 694         }
 695
 696         /* gfxclk dpm table setup */
 697         dpm_table = &dpm_context->dpm_tables.gfx_table;
 698         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 699                 ret = smu_v11_0_set_single_dpm_table(smu,
 700                                                      SMU_GFXCLK,
 701                                                      dpm_table);
 702                 if (ret)
 703                         return ret;
 704                 dpm_table->is_fine_grained =
 705                         !table_member[PPCLK_GFXCLK].SnapToDiscrete;
 706         } else {
 707                 dpm_table->count = 1;
 708                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 709                 dpm_table->dpm_levels[0].enabled = true;
 710                 dpm_table->min = dpm_table->dpm_levels[0].value;
 711                 dpm_table->max = dpm_table->dpm_levels[0].value;
 712         }
 713
 714         /* uclk dpm table setup */
 715         dpm_table = &dpm_context->dpm_tables.uclk_table;
 716         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 717                 ret = smu_v11_0_set_single_dpm_table(smu,
 718                                                      SMU_UCLK,
 719                                                      dpm_table);
 720                 if (ret)
 721                         return ret;
 722                 dpm_table->is_fine_grained =
 723                         !table_member[PPCLK_UCLK].SnapToDiscrete;
 724         } else {
 725                 dpm_table->count = 1;
 726                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 727                 dpm_table->dpm_levels[0].enabled = true;
 728                 dpm_table->min = dpm_table->dpm_levels[0].value;
 729                 dpm_table->max = dpm_table->dpm_levels[0].value;
 730         }
 731
 732         /* fclk dpm table setup */
 733         dpm_table = &dpm_context->dpm_tables.fclk_table;
 734         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 735                 ret = smu_v11_0_set_single_dpm_table(smu,
 736                                                      SMU_FCLK,
 737                                                      dpm_table);
 738                 if (ret)
 739                         return ret;
 740                 dpm_table->is_fine_grained =
 741                         !table_member[PPCLK_FCLK].SnapToDiscrete;
 742         } else {
 743                 dpm_table->count = 1;
 744                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 745                 dpm_table->dpm_levels[0].enabled = true;
 746                 dpm_table->min = dpm_table->dpm_levels[0].value;
 747                 dpm_table->max = dpm_table->dpm_levels[0].value;
 748         }
 749
 750         /* vclk0 dpm table setup */
 751         dpm_table = &dpm_context->dpm_tables.vclk_table;
 752         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 753                 ret = smu_v11_0_set_single_dpm_table(smu,
 754                                                      SMU_VCLK,
 755                                                      dpm_table);
 756                 if (ret)
 757                         return ret;
 758                 dpm_table->is_fine_grained =
 759                         !table_member[PPCLK_VCLK_0].SnapToDiscrete;
 760         } else {
 761                 dpm_table->count = 1;
 762                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
 763                 dpm_table->dpm_levels[0].enabled = true;
 764                 dpm_table->min = dpm_table->dpm_levels[0].value;
 765                 dpm_table->max = dpm_table->dpm_levels[0].value;
 766         }
 767
 768         /* vclk1 dpm table setup */
 769         if (adev->vcn.num_vcn_inst > 1) {
 770                 dpm_table = &dpm_context->dpm_tables.vclk1_table;
 771                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 772                         ret = smu_v11_0_set_single_dpm_table(smu,
 773                                                              SMU_VCLK1,
 774                                                              dpm_table);
 775                         if (ret)
 776                                 return ret;
 777                         dpm_table->is_fine_grained =
 778                                 !table_member[PPCLK_VCLK_1].SnapToDiscrete;
 779                 } else {
 780                         dpm_table->count = 1;
 781                         dpm_table->dpm_levels[0].value =
 782                                 smu->smu_table.boot_values.vclk / 100;
 783                         dpm_table->dpm_levels[0].enabled = true;
 784                         dpm_table->min = dpm_table->dpm_levels[0].value;
 785                         dpm_table->max = dpm_table->dpm_levels[0].value;
 786                 }
 787         }
 788
 789         /* dclk0 dpm table setup */
 790         dpm_table = &dpm_context->dpm_tables.dclk_table;
 791         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 792                 ret = smu_v11_0_set_single_dpm_table(smu,
 793                                                      SMU_DCLK,
 794                                                      dpm_table);
 795                 if (ret)
 796                         return ret;
 797                 dpm_table->is_fine_grained =
 798                         !table_member[PPCLK_DCLK_0].SnapToDiscrete;
 799         } else {
 800                 dpm_table->count = 1;
 801                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
 802                 dpm_table->dpm_levels[0].enabled = true;
 803                 dpm_table->min = dpm_table->dpm_levels[0].value;
 804                 dpm_table->max = dpm_table->dpm_levels[0].value;
 805         }
 806
 807         /* dclk1 dpm table setup */
 808         if (adev->vcn.num_vcn_inst > 1) {
 809                 dpm_table = &dpm_context->dpm_tables.dclk1_table;
 810                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 811                         ret = smu_v11_0_set_single_dpm_table(smu,
 812                                                              SMU_DCLK1,
 813                                                              dpm_table);
 814                         if (ret)
 815                                 return ret;
 816                         dpm_table->is_fine_grained =
 817                                 !table_member[PPCLK_DCLK_1].SnapToDiscrete;
 818                 } else {
 819                         dpm_table->count = 1;
 820                         dpm_table->dpm_levels[0].value =
 821                                 smu->smu_table.boot_values.dclk / 100;
 822                         dpm_table->dpm_levels[0].enabled = true;
 823                         dpm_table->min = dpm_table->dpm_levels[0].value;
 824                         dpm_table->max = dpm_table->dpm_levels[0].value;
 825                 }
 826         }
 827
 828         /* dcefclk dpm table setup */
 829         dpm_table = &dpm_context->dpm_tables.dcef_table;
 830         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 831                 ret = smu_v11_0_set_single_dpm_table(smu,
 832                                                      SMU_DCEFCLK,
 833                                                      dpm_table);
 834                 if (ret)
 835                         return ret;
 836                 dpm_table->is_fine_grained =
 837                         !table_member[PPCLK_DCEFCLK].SnapToDiscrete;
 838         } else {
 839                 dpm_table->count = 1;
 840                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 841                 dpm_table->dpm_levels[0].enabled = true;
 842                 dpm_table->min = dpm_table->dpm_levels[0].value;
 843                 dpm_table->max = dpm_table->dpm_levels[0].value;
 844         }
 845
 846         /* pixelclk dpm table setup */
 847         dpm_table = &dpm_context->dpm_tables.pixel_table;
 848         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 849                 ret = smu_v11_0_set_single_dpm_table(smu,
 850                                                      SMU_PIXCLK,
 851                                                      dpm_table);
 852                 if (ret)
 853                         return ret;
 854                 dpm_table->is_fine_grained =
 855                         !table_member[PPCLK_PIXCLK].SnapToDiscrete;
 856         } else {
 857                 dpm_table->count = 1;
 858                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 859                 dpm_table->dpm_levels[0].enabled = true;
 860                 dpm_table->min = dpm_table->dpm_levels[0].value;
 861                 dpm_table->max = dpm_table->dpm_levels[0].value;
 862         }
 863
 864         /* displayclk dpm table setup */
 865         dpm_table = &dpm_context->dpm_tables.display_table;
 866         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 867                 ret = smu_v11_0_set_single_dpm_table(smu,
 868                                                      SMU_DISPCLK,
 869                                                      dpm_table);
 870                 if (ret)
 871                         return ret;
 872                 dpm_table->is_fine_grained =
 873                         !table_member[PPCLK_DISPCLK].SnapToDiscrete;
 874         } else {
 875                 dpm_table->count = 1;
 876                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 877                 dpm_table->dpm_levels[0].enabled = true;
 878                 dpm_table->min = dpm_table->dpm_levels[0].value;
 879                 dpm_table->max = dpm_table->dpm_levels[0].value;
 880         }
 881
 882         /* phyclk dpm table setup */
 883         dpm_table = &dpm_context->dpm_tables.phy_table;
 884         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
 885                 ret = smu_v11_0_set_single_dpm_table(smu,
 886                                                      SMU_PHYCLK,
 887                                                      dpm_table);
 888                 if (ret)
 889                         return ret;
 890                 dpm_table->is_fine_grained =
 891                         !table_member[PPCLK_PHYCLK].SnapToDiscrete;
 892         } else {
 893                 dpm_table->count = 1;
 894                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
 895                 dpm_table->dpm_levels[0].enabled = true;
 896                 dpm_table->min = dpm_table->dpm_levels[0].value;
 897                 dpm_table->max = dpm_table->dpm_levels[0].value;
 898         }
 899
 900         return 0;
 901 }
 902
 903 static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
 904 {
 905         struct amdgpu_device *adev = smu->adev;
 906         int ret = 0;
 907
 908         if (enable) {
 909                 /* vcn dpm on is a prerequisite for vcn power gate messages */
 910                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 911                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
 912                         if (ret)
 913                                 return ret;
 914                         if (adev->vcn.num_vcn_inst > 1) {
 915                                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn,
 916                                                                   0x10000, NULL);
 917                                 if (ret)
 918                                         return ret;
 919                         }
 920                 }
 921         } else {
 922                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 923                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn, 0, NULL);
 924                         if (ret)
 925                                 return ret;
 926                         if (adev->vcn.num_vcn_inst > 1) {
 927                                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownVcn,
 928                                                                   0x10000, NULL);
 929                                 if (ret)
 930                                         return ret;
 931                         }
 932                 }
 933         }
 934
 935         return ret;
 936 }
 937
 938 static int sienna_cichlid_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
 939 {
 940         int ret = 0;
 941
 942         if (enable) {
 943                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 944                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
 945                         if (ret)
 946                                 return ret;
 947                 }
 948         } else {
 949                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_MM_DPM_PG_BIT)) {
 950                         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
 951                         if (ret)
 952                                 return ret;
 953                 }
 954         }
 955
 956         return ret;
 957 }
 958
 959 static int sienna_cichlid_get_current_clk_freq_by_table(struct smu_context *smu,
 960                                        enum smu_clk_type clk_type,
 961                                        uint32_t *value)
 962 {
 963         MetricsMember_t member_type;
 964         int clk_id = 0;
 965
 966         clk_id = smu_cmn_to_asic_specific_index(smu,
 967                                                 CMN2ASIC_MAPPING_CLK,
 968                                                 clk_type);
 969         if (clk_id < 0)
 970                 return clk_id;
 971
 972         switch (clk_id) {
 973         case PPCLK_GFXCLK:
 974                 member_type = METRICS_CURR_GFXCLK;
 975                 break;
 976         case PPCLK_UCLK:
 977                 member_type = METRICS_CURR_UCLK;
 978                 break;
 979         case PPCLK_SOCCLK:
 980                 member_type = METRICS_CURR_SOCCLK;
 981                 break;
 982         case PPCLK_FCLK:
 983                 member_type = METRICS_CURR_FCLK;
 984                 break;
 985         case PPCLK_VCLK_0:
 986                 member_type = METRICS_CURR_VCLK;
 987                 break;
 988         case PPCLK_VCLK_1:
 989                 member_type = METRICS_CURR_VCLK1;
 990                 break;
 991         case PPCLK_DCLK_0:
 992                 member_type = METRICS_CURR_DCLK;
 993                 break;
 994         case PPCLK_DCLK_1:
 995                 member_type = METRICS_CURR_DCLK1;
 996                 break;
 997         case PPCLK_DCEFCLK:
 998                 member_type = METRICS_CURR_DCEFCLK;
 999                 break;
1000         default:
1001                 return -EINVAL;
1002         }
1003
1004         return sienna_cichlid_get_smu_metrics_data(smu,
1005                                                    member_type,
1006                                                    value);
1007
1008 }
1009
1010 static bool sienna_cichlid_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1011 {
1012         DpmDescriptor_t *dpm_desc = NULL;
1013         DpmDescriptor_t *table_member;
1014         uint32_t clk_index = 0;
1015
1016         GET_PPTABLE_MEMBER(DpmDescriptor, &table_member);
1017         clk_index = smu_cmn_to_asic_specific_index(smu,
1018                                                    CMN2ASIC_MAPPING_CLK,
1019                                                    clk_type);
1020         dpm_desc = &table_member[clk_index];
1021
1022         /* 0 - Fine grained DPM, 1 - Discrete DPM */
1023         return dpm_desc->SnapToDiscrete == 0;
1024 }
1025
1026 static bool sienna_cichlid_is_od_feature_supported(struct smu_11_0_7_overdrive_table *od_table,
1027                                                    enum SMU_11_0_7_ODFEATURE_CAP cap)
1028 {
1029         return od_table->cap[cap];
1030 }
1031
1032 static void sienna_cichlid_get_od_setting_range(struct smu_11_0_7_overdrive_table *od_table,
1033                                                 enum SMU_11_0_7_ODSETTING_ID setting,
1034                                                 uint32_t *min, uint32_t *max)
1035 {
1036         if (min)
1037                 *min = od_table->min[setting];
1038         if (max)
1039                 *max = od_table->max[setting];
1040 }
1041
1042 static int sienna_cichlid_print_clk_levels(struct smu_context *smu,
1043                         enum smu_clk_type clk_type, char *buf)
1044 {
1045         struct amdgpu_device *adev = smu->adev;
1046         struct smu_table_context *table_context = &smu->smu_table;
1047         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1048         struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1049         uint16_t *table_member;
1050
1051         struct smu_11_0_7_overdrive_table *od_settings = smu->od_settings;
1052         OverDriveTable_t *od_table =
1053                 (OverDriveTable_t *)table_context->overdrive_table;
1054         int i, size = 0, ret = 0;
1055         uint32_t cur_value = 0, value = 0, count = 0;
1056         uint32_t freq_values[3] = {0};
1057         uint32_t mark_index = 0;
1058         uint32_t gen_speed, lane_width;
1059         uint32_t min_value, max_value;
1060         uint32_t smu_version;
1061
1062         switch (clk_type) {
1063         case SMU_GFXCLK:
1064         case SMU_SCLK:
1065         case SMU_SOCCLK:
1066         case SMU_MCLK:
1067         case SMU_UCLK:
1068         case SMU_FCLK:
1069         case SMU_VCLK:
1070         case SMU_VCLK1:
1071         case SMU_DCLK:
1072         case SMU_DCLK1:
1073         case SMU_DCEFCLK:
1074                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1075                 if (ret)
1076                         goto print_clk_out;
1077
1078                 /* no need to disable gfxoff when retrieving the current gfxclk */
1079                 if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1080                         amdgpu_gfx_off_ctrl(adev, false);
1081
1082                 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1083                 if (ret)
1084                         goto print_clk_out;
1085
1086                 if (!sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1087                         for (i = 0; i < count; i++) {
1088                                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
1089                                 if (ret)
1090                                         goto print_clk_out;
1091
1092                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, value,
1093                                                 cur_value == value ? "*" : "");
1094                         }
1095                 } else {
1096                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
1097                         if (ret)
1098                                 goto print_clk_out;
1099                         ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
1100                         if (ret)
1101                                 goto print_clk_out;
1102
1103                         freq_values[1] = cur_value;
1104                         mark_index = cur_value == freq_values[0] ? 0 :
1105                                      cur_value == freq_values[2] ? 2 : 1;
1106
1107                         count = 3;
1108                         if (mark_index != 1) {
1109                                 count = 2;
1110                                 freq_values[1] = freq_values[2];
1111                         }
1112
1113                         for (i = 0; i < count; i++) {
1114                                 size += sprintf(buf + size, "%d: %uMhz %s\n", i, freq_values[i],
1115                                                 cur_value  == freq_values[i] ? "*" : "");
1116                         }
1117
1118                 }
1119                 break;
1120         case SMU_PCIE:
1121                 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1122                 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1123                 GET_PPTABLE_MEMBER(LclkFreq, &table_member);
1124                 for (i = 0; i < NUM_LINK_LEVELS; i++)
1125                         size += sprintf(buf + size, "%d: %s %s %dMhz %s\n", i,
1126                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1127                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1128                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1129                                         (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1130                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1131                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1132                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1133                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1134                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1135                                         (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1136                                         table_member[i],
1137                                         (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1138                                         (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1139                                         "*" : "");
1140                 break;
1141         case SMU_OD_SCLK:
1142                 if (!smu->od_enabled || !od_table || !od_settings)
1143                         break;
1144
1145                 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS))
1146                         break;
1147
1148                 size += sprintf(buf + size, "OD_SCLK:\n");
1149                 size += sprintf(buf + size, "0: %uMhz\n1: %uMhz\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
1150                 break;
1151
1152         case SMU_OD_MCLK:
1153                 if (!smu->od_enabled || !od_table || !od_settings)
1154                         break;
1155
1156                 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS))
1157                         break;
1158
1159                 size += sprintf(buf + size, "OD_MCLK:\n");
1160                 size += sprintf(buf + size, "0: %uMhz\n1: %uMHz\n", od_table->UclkFmin, od_table->UclkFmax);
1161                 break;
1162
1163         case SMU_OD_VDDGFX_OFFSET:
1164                 if (!smu->od_enabled || !od_table || !od_settings)
1165                         break;
1166
1167                 /*
1168                  * OD GFX Voltage Offset functionality is supported only by 58.41.0
1169                  * and onwards SMU firmwares.
1170                  */
1171                 smu_cmn_get_smc_version(smu, NULL, &smu_version);
1172                 if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1173                      (smu_version < 0x003a2900))
1174                         break;
1175
1176                 size += sprintf(buf + size, "OD_VDDGFX_OFFSET:\n");
1177                 size += sprintf(buf + size, "%dmV\n", od_table->VddGfxOffset);
1178                 break;
1179
1180         case SMU_OD_RANGE:
1181                 if (!smu->od_enabled || !od_table || !od_settings)
1182                         break;
1183
1184                 size = sprintf(buf, "%s:\n", "OD_RANGE");
1185
1186                 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
1187                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMIN,
1188                                                             &min_value, NULL);
1189                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_GFXCLKFMAX,
1190                                                             NULL, &max_value);
1191                         size += sprintf(buf + size, "SCLK: %7uMhz %10uMhz\n",
1192                                         min_value, max_value);
1193                 }
1194
1195                 if (sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
1196                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMIN,
1197                                                             &min_value, NULL);
1198                         sienna_cichlid_get_od_setting_range(od_settings, SMU_11_0_7_ODSETTING_UCLKFMAX,
1199                                                             NULL, &max_value);
1200                         size += sprintf(buf + size, "MCLK: %7uMhz %10uMhz\n",
1201                                         min_value, max_value);
1202                 }
1203                 break;
1204
1205         default:
1206                 break;
1207         }
1208
1209 print_clk_out:
1210         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1211                 amdgpu_gfx_off_ctrl(adev, true);
1212
1213         return size;
1214 }
1215
1216 static int sienna_cichlid_force_clk_levels(struct smu_context *smu,
1217                                    enum smu_clk_type clk_type, uint32_t mask)
1218 {
1219         struct amdgpu_device *adev = smu->adev;
1220         int ret = 0, size = 0;
1221         uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1222
1223         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1224         soft_max_level = mask ? (fls(mask) - 1) : 0;
1225
1226         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1227                 amdgpu_gfx_off_ctrl(adev, false);
1228
1229         switch (clk_type) {
1230         case SMU_GFXCLK:
1231         case SMU_SCLK:
1232         case SMU_SOCCLK:
1233         case SMU_MCLK:
1234         case SMU_UCLK:
1235         case SMU_FCLK:
1236                 /* There is only 2 levels for fine grained DPM */
1237                 if (sienna_cichlid_is_support_fine_grained_dpm(smu, clk_type)) {
1238                         soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1239                         soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1240                 }
1241
1242                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1243                 if (ret)
1244                         goto forec_level_out;
1245
1246                 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1247                 if (ret)
1248                         goto forec_level_out;
1249
1250                 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1251                 if (ret)
1252                         goto forec_level_out;
1253                 break;
1254         case SMU_DCEFCLK:
1255                 dev_info(smu->adev->dev,"Setting DCEFCLK min/max dpm level is not supported!\n");
1256                 break;
1257         default:
1258                 break;
1259         }
1260
1261 forec_level_out:
1262         if ((clk_type == SMU_GFXCLK) || (clk_type == SMU_SCLK))
1263                 amdgpu_gfx_off_ctrl(adev, true);
1264
1265         return size;
1266 }
1267
1268 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
1269 {
1270         struct smu_11_0_dpm_context *dpm_context =
1271                                 smu->smu_dpm.dpm_context;
1272         struct smu_11_0_dpm_table *gfx_table =
1273                                 &dpm_context->dpm_tables.gfx_table;
1274         struct smu_11_0_dpm_table *mem_table =
1275                                 &dpm_context->dpm_tables.uclk_table;
1276         struct smu_11_0_dpm_table *soc_table =
1277                                 &dpm_context->dpm_tables.soc_table;
1278         struct smu_umd_pstate_table *pstate_table =
1279                                 &smu->pstate_table;
1280
1281         pstate_table->gfxclk_pstate.min = gfx_table->min;
1282         pstate_table->gfxclk_pstate.peak = gfx_table->max;
1283         if (gfx_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK)
1284                 pstate_table->gfxclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_GFXCLK;
1285
1286         pstate_table->uclk_pstate.min = mem_table->min;
1287         pstate_table->uclk_pstate.peak = mem_table->max;
1288         if (mem_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK)
1289                 pstate_table->uclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_MEMCLK;
1290
1291         pstate_table->socclk_pstate.min = soc_table->min;
1292         pstate_table->socclk_pstate.peak = soc_table->max;
1293         if (soc_table->max >= SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK)
1294                 pstate_table->socclk_pstate.standard = SIENNA_CICHLID_UMD_PSTATE_PROFILING_SOCCLK;
1295
1296         return 0;
1297 }
1298
1299 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)
1300 {
1301         int ret = 0;
1302         uint32_t max_freq = 0;
1303
1304         /* Sienna_Cichlid do not support to change display num currently */
1305         return 0;
1306 #if 0
1307         ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1308         if (ret)
1309                 return ret;
1310 #endif
1311
1312         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1313                 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1314                 if (ret)
1315                         return ret;
1316                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1317                 if (ret)
1318                         return ret;
1319         }
1320
1321         return ret;
1322 }
1323
1324 static int sienna_cichlid_display_config_changed(struct smu_context *smu)
1325 {
1326         int ret = 0;
1327
1328         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1329             smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1330             smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1331 #if 0
1332                 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1333                                                   smu->display_config->num_display,
1334                                                   NULL);
1335 #endif
1336                 if (ret)
1337                         return ret;
1338         }
1339
1340         return ret;
1341 }
1342
1343 static bool sienna_cichlid_is_dpm_running(struct smu_context *smu)
1344 {
1345         int ret = 0;
1346         uint32_t feature_mask[2];
1347         uint64_t feature_enabled;
1348
1349         ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1350         if (ret)
1351                 return false;
1352
1353         feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1354
1355         return !!(feature_enabled & SMC_DPM_FEATURE);
1356 }
1357
1358 static int sienna_cichlid_get_fan_speed_percent(struct smu_context *smu,
1359                                                 uint32_t *speed)
1360 {
1361         int ret;
1362         u32 rpm;
1363
1364         if (!speed)
1365                 return -EINVAL;
1366
1367         switch (smu_v11_0_get_fan_control_mode(smu)) {
1368         case AMD_FAN_CTRL_AUTO:
1369                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1370                                                           METRICS_CURR_FANSPEED,
1371                                                           &rpm);
1372                 if (!ret && smu->fan_max_rpm)
1373                         *speed = rpm * 100 / smu->fan_max_rpm;
1374                 return ret;
1375         default:
1376                 *speed = smu->user_dpm_profile.fan_speed_percent;
1377                 return 0;
1378         }
1379 }
1380
1381 static int sienna_cichlid_get_fan_parameters(struct smu_context *smu)
1382 {
1383         uint16_t *table_member;
1384
1385         GET_PPTABLE_MEMBER(FanMaximumRpm, &table_member);
1386         smu->fan_max_rpm = *table_member;
1387
1388         return 0;
1389 }
1390
1391 static int sienna_cichlid_get_power_profile_mode(struct smu_context *smu, char *buf)
1392 {
1393         DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1394         DpmActivityMonitorCoeffInt_t *activity_monitor =
1395                 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1396         uint32_t i, size = 0;
1397         int16_t workload_type = 0;
1398         static const char *profile_name[] = {
1399                                         "BOOTUP_DEFAULT",
1400                                         "3D_FULL_SCREEN",
1401                                         "POWER_SAVING",
1402                                         "VIDEO",
1403                                         "VR",
1404                                         "COMPUTE",
1405                                         "CUSTOM"};
1406         static const char *title[] = {
1407                         "PROFILE_INDEX(NAME)",
1408                         "CLOCK_TYPE(NAME)",
1409                         "FPS",
1410                         "MinFreqType",
1411                         "MinActiveFreqType",
1412                         "MinActiveFreq",
1413                         "BoosterFreqType",
1414                         "BoosterFreq",
1415                         "PD_Data_limit_c",
1416                         "PD_Data_error_coeff",
1417                         "PD_Data_error_rate_coeff"};
1418         int result = 0;
1419
1420         if (!buf)
1421                 return -EINVAL;
1422
1423         size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1424                         title[0], title[1], title[2], title[3], title[4], title[5],
1425                         title[6], title[7], title[8], title[9], title[10]);
1426
1427         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1428                 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1429                 workload_type = smu_cmn_to_asic_specific_index(smu,
1430                                                                CMN2ASIC_MAPPING_WORKLOAD,
1431                                                                i);
1432                 if (workload_type < 0)
1433                         return -EINVAL;
1434
1435                 result = smu_cmn_update_table(smu,
1436                                           SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1437                                           (void *)(&activity_monitor_external), false);
1438                 if (result) {
1439                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1440                         return result;
1441                 }
1442
1443                 size += sprintf(buf + size, "%2d %14s%s:\n",
1444                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1445
1446                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1447                         " ",
1448                         0,
1449                         "GFXCLK",
1450                         activity_monitor->Gfx_FPS,
1451                         activity_monitor->Gfx_MinFreqStep,
1452                         activity_monitor->Gfx_MinActiveFreqType,
1453                         activity_monitor->Gfx_MinActiveFreq,
1454                         activity_monitor->Gfx_BoosterFreqType,
1455                         activity_monitor->Gfx_BoosterFreq,
1456                         activity_monitor->Gfx_PD_Data_limit_c,
1457                         activity_monitor->Gfx_PD_Data_error_coeff,
1458                         activity_monitor->Gfx_PD_Data_error_rate_coeff);
1459
1460                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1461                         " ",
1462                         1,
1463                         "SOCCLK",
1464                         activity_monitor->Fclk_FPS,
1465                         activity_monitor->Fclk_MinFreqStep,
1466                         activity_monitor->Fclk_MinActiveFreqType,
1467                         activity_monitor->Fclk_MinActiveFreq,
1468                         activity_monitor->Fclk_BoosterFreqType,
1469                         activity_monitor->Fclk_BoosterFreq,
1470                         activity_monitor->Fclk_PD_Data_limit_c,
1471                         activity_monitor->Fclk_PD_Data_error_coeff,
1472                         activity_monitor->Fclk_PD_Data_error_rate_coeff);
1473
1474                 size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1475                         " ",
1476                         2,
1477                         "MEMLK",
1478                         activity_monitor->Mem_FPS,
1479                         activity_monitor->Mem_MinFreqStep,
1480                         activity_monitor->Mem_MinActiveFreqType,
1481                         activity_monitor->Mem_MinActiveFreq,
1482                         activity_monitor->Mem_BoosterFreqType,
1483                         activity_monitor->Mem_BoosterFreq,
1484                         activity_monitor->Mem_PD_Data_limit_c,
1485                         activity_monitor->Mem_PD_Data_error_coeff,
1486                         activity_monitor->Mem_PD_Data_error_rate_coeff);
1487         }
1488
1489         return size;
1490 }
1491
1492 static int sienna_cichlid_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
1493 {
1494
1495         DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
1496         DpmActivityMonitorCoeffInt_t *activity_monitor =
1497                 &(activity_monitor_external.DpmActivityMonitorCoeffInt);
1498         int workload_type, ret = 0;
1499
1500         smu->power_profile_mode = input[size];
1501
1502         if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1503                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
1504                 return -EINVAL;
1505         }
1506
1507         if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1508
1509                 ret = smu_cmn_update_table(smu,
1510                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1511                                        (void *)(&activity_monitor_external), false);
1512                 if (ret) {
1513                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1514                         return ret;
1515                 }
1516
1517                 switch (input[0]) {
1518                 case 0: /* Gfxclk */
1519                         activity_monitor->Gfx_FPS = input[1];
1520                         activity_monitor->Gfx_MinFreqStep = input[2];
1521                         activity_monitor->Gfx_MinActiveFreqType = input[3];
1522                         activity_monitor->Gfx_MinActiveFreq = input[4];
1523                         activity_monitor->Gfx_BoosterFreqType = input[5];
1524                         activity_monitor->Gfx_BoosterFreq = input[6];
1525                         activity_monitor->Gfx_PD_Data_limit_c = input[7];
1526                         activity_monitor->Gfx_PD_Data_error_coeff = input[8];
1527                         activity_monitor->Gfx_PD_Data_error_rate_coeff = input[9];
1528                         break;
1529                 case 1: /* Socclk */
1530                         activity_monitor->Fclk_FPS = input[1];
1531                         activity_monitor->Fclk_MinFreqStep = input[2];
1532                         activity_monitor->Fclk_MinActiveFreqType = input[3];
1533                         activity_monitor->Fclk_MinActiveFreq = input[4];
1534                         activity_monitor->Fclk_BoosterFreqType = input[5];
1535                         activity_monitor->Fclk_BoosterFreq = input[6];
1536                         activity_monitor->Fclk_PD_Data_limit_c = input[7];
1537                         activity_monitor->Fclk_PD_Data_error_coeff = input[8];
1538                         activity_monitor->Fclk_PD_Data_error_rate_coeff = input[9];
1539                         break;
1540                 case 2: /* Memlk */
1541                         activity_monitor->Mem_FPS = input[1];
1542                         activity_monitor->Mem_MinFreqStep = input[2];
1543                         activity_monitor->Mem_MinActiveFreqType = input[3];
1544                         activity_monitor->Mem_MinActiveFreq = input[4];
1545                         activity_monitor->Mem_BoosterFreqType = input[5];
1546                         activity_monitor->Mem_BoosterFreq = input[6];
1547                         activity_monitor->Mem_PD_Data_limit_c = input[7];
1548                         activity_monitor->Mem_PD_Data_error_coeff = input[8];
1549                         activity_monitor->Mem_PD_Data_error_rate_coeff = input[9];
1550                         break;
1551                 }
1552
1553                 ret = smu_cmn_update_table(smu,
1554                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
1555                                        (void *)(&activity_monitor_external), true);
1556                 if (ret) {
1557                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1558                         return ret;
1559                 }
1560         }
1561
1562         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1563         workload_type = smu_cmn_to_asic_specific_index(smu,
1564                                                        CMN2ASIC_MAPPING_WORKLOAD,
1565                                                        smu->power_profile_mode);
1566         if (workload_type < 0)
1567                 return -EINVAL;
1568         smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
1569                                     1 << workload_type, NULL);
1570
1571         return ret;
1572 }
1573
1574 static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
1575 {
1576         struct smu_clocks min_clocks = {0};
1577         struct pp_display_clock_request clock_req;
1578         int ret = 0;
1579
1580         min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
1581         min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
1582         min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
1583
1584         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1585                 clock_req.clock_type = amd_pp_dcef_clock;
1586                 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
1587
1588                 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
1589                 if (!ret) {
1590                         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
1591                                 ret = smu_cmn_send_smc_msg_with_param(smu,
1592                                                                   SMU_MSG_SetMinDeepSleepDcefclk,
1593                                                                   min_clocks.dcef_clock_in_sr/100,
1594                                                                   NULL);
1595                                 if (ret) {
1596                                         dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
1597                                         return ret;
1598                                 }
1599                         }
1600                 } else {
1601                         dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
1602                 }
1603         }
1604
1605         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1606                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
1607                 if (ret) {
1608                         dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
1609                         return ret;
1610                 }
1611         }
1612
1613         return 0;
1614 }
1615
1616 static int sienna_cichlid_set_watermarks_table(struct smu_context *smu,
1617                                                struct pp_smu_wm_range_sets *clock_ranges)
1618 {
1619         Watermarks_t *table = smu->smu_table.watermarks_table;
1620         int ret = 0;
1621         int i;
1622
1623         if (clock_ranges) {
1624                 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1625                     clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1626                         return -EINVAL;
1627
1628                 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1629                         table->WatermarkRow[WM_DCEFCLK][i].MinClock =
1630                                 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1631                         table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
1632                                 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1633                         table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
1634                                 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1635                         table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
1636                                 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1637
1638                         table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
1639                                 clock_ranges->reader_wm_sets[i].wm_inst;
1640                 }
1641
1642                 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1643                         table->WatermarkRow[WM_SOCCLK][i].MinClock =
1644                                 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1645                         table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1646                                 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1647                         table->WatermarkRow[WM_SOCCLK][i].MinUclk =
1648                                 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1649                         table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
1650                                 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1651
1652                         table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1653                                 clock_ranges->writer_wm_sets[i].wm_inst;
1654                 }
1655
1656                 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1657         }
1658
1659         if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1660              !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1661                 ret = smu_cmn_write_watermarks_table(smu);
1662                 if (ret) {
1663                         dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1664                         return ret;
1665                 }
1666                 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1667         }
1668
1669         return 0;
1670 }
1671
1672 static int sienna_cichlid_read_sensor(struct smu_context *smu,
1673                                  enum amd_pp_sensors sensor,
1674                                  void *data, uint32_t *size)
1675 {
1676         int ret = 0;
1677         uint16_t *temp;
1678
1679         if(!data || !size)
1680                 return -EINVAL;
1681
1682         mutex_lock(&smu->sensor_lock);
1683         switch (sensor) {
1684         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1685                 GET_PPTABLE_MEMBER(FanMaximumRpm, &temp);
1686                 *(uint16_t *)data = *temp;
1687                 *size = 4;
1688                 break;
1689         case AMDGPU_PP_SENSOR_MEM_LOAD:
1690                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1691                                                           METRICS_AVERAGE_MEMACTIVITY,
1692                                                           (uint32_t *)data);
1693                 *size = 4;
1694                 break;
1695         case AMDGPU_PP_SENSOR_GPU_LOAD:
1696                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1697                                                           METRICS_AVERAGE_GFXACTIVITY,
1698                                                           (uint32_t *)data);
1699                 *size = 4;
1700                 break;
1701         case AMDGPU_PP_SENSOR_GPU_POWER:
1702                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1703                                                           METRICS_AVERAGE_SOCKETPOWER,
1704                                                           (uint32_t *)data);
1705                 *size = 4;
1706                 break;
1707         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1708                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1709                                                           METRICS_TEMPERATURE_HOTSPOT,
1710                                                           (uint32_t *)data);
1711                 *size = 4;
1712                 break;
1713         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1714                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1715                                                           METRICS_TEMPERATURE_EDGE,
1716                                                           (uint32_t *)data);
1717                 *size = 4;
1718                 break;
1719         case AMDGPU_PP_SENSOR_MEM_TEMP:
1720                 ret = sienna_cichlid_get_smu_metrics_data(smu,
1721                                                           METRICS_TEMPERATURE_MEM,
1722                                                           (uint32_t *)data);
1723                 *size = 4;
1724                 break;
1725         case AMDGPU_PP_SENSOR_GFX_MCLK:
1726                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1727                 *(uint32_t *)data *= 100;
1728                 *size = 4;
1729                 break;
1730         case AMDGPU_PP_SENSOR_GFX_SCLK:
1731                 ret = sienna_cichlid_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1732                 *(uint32_t *)data *= 100;
1733                 *size = 4;
1734                 break;
1735         case AMDGPU_PP_SENSOR_VDDGFX:
1736                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1737                 *size = 4;
1738                 break;
1739         default:
1740                 ret = -EOPNOTSUPP;
1741                 break;
1742         }
1743         mutex_unlock(&smu->sensor_lock);
1744
1745         return ret;
1746 }
1747
1748 static int sienna_cichlid_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
1749 {
1750         uint32_t num_discrete_levels = 0;
1751         uint16_t *dpm_levels = NULL;
1752         uint16_t i = 0;
1753         struct smu_table_context *table_context = &smu->smu_table;
1754         DpmDescriptor_t *table_member1;
1755         uint16_t *table_member2;
1756
1757         if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
1758                 return -EINVAL;
1759
1760         GET_PPTABLE_MEMBER(DpmDescriptor, &table_member1);
1761         num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels;
1762         GET_PPTABLE_MEMBER(FreqTableUclk, &table_member2);
1763         dpm_levels = table_member2;
1764
1765         if (num_discrete_levels == 0 || dpm_levels == NULL)
1766                 return -EINVAL;
1767
1768         *num_states = num_discrete_levels;
1769         for (i = 0; i < num_discrete_levels; i++) {
1770                 /* convert to khz */
1771                 *clocks_in_khz = (*dpm_levels) * 1000;
1772                 clocks_in_khz++;
1773                 dpm_levels++;
1774         }
1775
1776         return 0;
1777 }
1778
1779 static int sienna_cichlid_get_thermal_temperature_range(struct smu_context *smu,
1780                                                 struct smu_temperature_range *range)
1781 {
1782         struct smu_table_context *table_context = &smu->smu_table;
1783         struct smu_11_0_7_powerplay_table *powerplay_table =
1784                                 table_context->power_play_table;
1785         uint16_t *table_member;
1786         uint16_t temp_edge, temp_hotspot, temp_mem;
1787
1788         if (!range)
1789                 return -EINVAL;
1790
1791         memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1792
1793         GET_PPTABLE_MEMBER(TemperatureLimit, &table_member);
1794         temp_edge = table_member[TEMP_EDGE];
1795         temp_hotspot = table_member[TEMP_HOTSPOT];
1796         temp_mem = table_member[TEMP_MEM];
1797
1798         range->max = temp_edge * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1799         range->edge_emergency_max = (temp_edge + CTF_OFFSET_EDGE) *
1800                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1801         range->hotspot_crit_max = temp_hotspot * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1802         range->hotspot_emergency_max = (temp_hotspot + CTF_OFFSET_HOTSPOT) *
1803                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1804         range->mem_crit_max = temp_mem * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1805         range->mem_emergency_max = (temp_mem + CTF_OFFSET_MEM)*
1806                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1807
1808         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1809
1810         return 0;
1811 }
1812
1813 static int sienna_cichlid_display_disable_memory_clock_switch(struct smu_context *smu,
1814                                                 bool disable_memory_clock_switch)
1815 {
1816         int ret = 0;
1817         struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
1818                 (struct smu_11_0_max_sustainable_clocks *)
1819                         smu->smu_table.max_sustainable_clocks;
1820         uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
1821         uint32_t max_memory_clock = max_sustainable_clocks->uclock;
1822
1823         if(smu->disable_uclk_switch == disable_memory_clock_switch)
1824                 return 0;
1825
1826         if(disable_memory_clock_switch)
1827                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
1828         else
1829                 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
1830
1831         if(!ret)
1832                 smu->disable_uclk_switch = disable_memory_clock_switch;
1833
1834         return ret;
1835 }
1836
1837 static int sienna_cichlid_get_power_limit(struct smu_context *smu,
1838                                           uint32_t *current_power_limit,
1839                                           uint32_t *default_power_limit,
1840                                           uint32_t *max_power_limit)
1841 {
1842         struct smu_11_0_7_powerplay_table *powerplay_table =
1843                 (struct smu_11_0_7_powerplay_table *)smu->smu_table.power_play_table;
1844         uint32_t power_limit, od_percent;
1845         uint16_t *table_member;
1846
1847         GET_PPTABLE_MEMBER(SocketPowerLimitAc, &table_member);
1848
1849         if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1850                 power_limit =
1851                         table_member[PPT_THROTTLER_PPT0];
1852         }
1853
1854         if (current_power_limit)
1855                 *current_power_limit = power_limit;
1856         if (default_power_limit)
1857                 *default_power_limit = power_limit;
1858
1859         if (max_power_limit) {
1860                 if (smu->od_enabled) {
1861                         od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_7_ODSETTING_POWERPERCENTAGE]);
1862
1863                         dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1864
1865                         power_limit *= (100 + od_percent);
1866                         power_limit /= 100;
1867                 }
1868                 *max_power_limit = power_limit;
1869         }
1870
1871         return 0;
1872 }
1873
1874 static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
1875                                          uint32_t pcie_gen_cap,
1876                                          uint32_t pcie_width_cap)
1877 {
1878         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1879
1880         uint32_t smu_pcie_arg;
1881         uint8_t *table_member1, *table_member2;
1882         int ret, i;
1883
1884         GET_PPTABLE_MEMBER(PcieGenSpeed, &table_member1);
1885         GET_PPTABLE_MEMBER(PcieLaneCount, &table_member2);
1886
1887         /* lclk dpm table setup */
1888         for (i = 0; i < MAX_PCIE_CONF; i++) {
1889                 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = table_member1[i];
1890                 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = table_member2[i];
1891         }
1892
1893         for (i = 0; i < NUM_LINK_LEVELS; i++) {
1894                 smu_pcie_arg = (i << 16) |
1895                         ((table_member1[i] <= pcie_gen_cap) ?
1896                          (table_member1[i] << 8) :
1897                          (pcie_gen_cap << 8)) |
1898                         ((table_member2[i] <= pcie_width_cap) ?
1899                          table_member2[i] :
1900                          pcie_width_cap);
1901
1902                 ret = smu_cmn_send_smc_msg_with_param(smu,
1903                                 SMU_MSG_OverridePcieParameters,
1904                                 smu_pcie_arg,
1905                                 NULL);
1906                 if (ret)
1907                         return ret;
1908
1909                 if (table_member1[i] > pcie_gen_cap)
1910                         dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
1911                 if (table_member2[i] > pcie_width_cap)
1912                         dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
1913         }
1914
1915         return 0;
1916 }
1917
1918 static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
1919                                 enum smu_clk_type clk_type,
1920                                 uint32_t *min, uint32_t *max)
1921 {
1922         struct amdgpu_device *adev = smu->adev;
1923         int ret;
1924
1925         if (clk_type == SMU_GFXCLK)
1926                 amdgpu_gfx_off_ctrl(adev, false);
1927         ret = smu_v11_0_get_dpm_ultimate_freq(smu, clk_type, min, max);
1928         if (clk_type == SMU_GFXCLK)
1929                 amdgpu_gfx_off_ctrl(adev, true);
1930
1931         return ret;
1932 }
1933
1934 static void sienna_cichlid_dump_od_table(struct smu_context *smu,
1935                                          OverDriveTable_t *od_table)
1936 {
1937         struct amdgpu_device *adev = smu->adev;
1938         uint32_t smu_version;
1939
1940         dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin,
1941                                                           od_table->GfxclkFmax);
1942         dev_dbg(smu->adev->dev, "OD: Uclk: (%d, %d)\n", od_table->UclkFmin,
1943                                                         od_table->UclkFmax);
1944
1945         smu_cmn_get_smc_version(smu, NULL, &smu_version);
1946         if (!((adev->asic_type == CHIP_SIENNA_CICHLID) &&
1947                (smu_version < 0x003a2900)))
1948                 dev_dbg(smu->adev->dev, "OD: VddGfxOffset: %d\n", od_table->VddGfxOffset);
1949 }
1950
1951 static int sienna_cichlid_set_default_od_settings(struct smu_context *smu)
1952 {
1953         OverDriveTable_t *od_table =
1954                 (OverDriveTable_t *)smu->smu_table.overdrive_table;
1955         OverDriveTable_t *boot_od_table =
1956                 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
1957         OverDriveTable_t *user_od_table =
1958                 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
1959         int ret = 0;
1960
1961         /*
1962          * For S3/S4/Runpm resume, no need to setup those overdrive tables again as
1963          *   - either they already have the default OD settings got during cold bootup
1964          *   - or they have some user customized OD settings which cannot be overwritten
1965          */
1966         if (smu->adev->in_suspend)
1967                 return 0;
1968
1969         ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE,
1970                                    0, (void *)boot_od_table, false);
1971         if (ret) {
1972                 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
1973                 return ret;
1974         }
1975
1976         sienna_cichlid_dump_od_table(smu, boot_od_table);
1977
1978         memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
1979         memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
1980
1981         return 0;
1982 }
1983
1984 static int sienna_cichlid_od_setting_check_range(struct smu_context *smu,
1985                                                  struct smu_11_0_7_overdrive_table *od_table,
1986                                                  enum SMU_11_0_7_ODSETTING_ID setting,
1987                                                  uint32_t value)
1988 {
1989         if (value < od_table->min[setting]) {
1990                 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n",
1991                                           setting, value, od_table->min[setting]);
1992                 return -EINVAL;
1993         }
1994         if (value > od_table->max[setting]) {
1995                 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n",
1996                                           setting, value, od_table->max[setting]);
1997                 return -EINVAL;
1998         }
1999
2000         return 0;
2001 }
2002
2003 static int sienna_cichlid_od_edit_dpm_table(struct smu_context *smu,
2004                                             enum PP_OD_DPM_TABLE_COMMAND type,
2005                                             long input[], uint32_t size)
2006 {
2007         struct smu_table_context *table_context = &smu->smu_table;
2008         OverDriveTable_t *od_table =
2009                 (OverDriveTable_t *)table_context->overdrive_table;
2010         struct smu_11_0_7_overdrive_table *od_settings =
2011                 (struct smu_11_0_7_overdrive_table *)smu->od_settings;
2012         struct amdgpu_device *adev = smu->adev;
2013         enum SMU_11_0_7_ODSETTING_ID freq_setting;
2014         uint16_t *freq_ptr;
2015         int i, ret = 0;
2016         uint32_t smu_version;
2017
2018         if (!smu->od_enabled) {
2019                 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2020                 return -EINVAL;
2021         }
2022
2023         if (!smu->od_settings) {
2024                 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2025                 return -ENOENT;
2026         }
2027
2028         if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2029                 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2030                 return -EINVAL;
2031         }
2032
2033         switch (type) {
2034         case PP_OD_EDIT_SCLK_VDDC_TABLE:
2035                 if (!sienna_cichlid_is_od_feature_supported(od_settings,
2036                                                             SMU_11_0_7_ODCAP_GFXCLK_LIMITS)) {
2037                         dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2038                         return -ENOTSUPP;
2039                 }
2040
2041                 for (i = 0; i < size; i += 2) {
2042                         if (i + 2 > size) {
2043                                 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2044                                 return -EINVAL;
2045                         }
2046
2047                         switch (input[i]) {
2048                         case 0:
2049                                 if (input[i + 1] > od_table->GfxclkFmax) {
2050                                         dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2051                                                 input[i + 1], od_table->GfxclkFmax);
2052                                         return -EINVAL;
2053                                 }
2054
2055                                 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMIN;
2056                                 freq_ptr = &od_table->GfxclkFmin;
2057                                 break;
2058
2059                         case 1:
2060                                 if (input[i + 1] < od_table->GfxclkFmin) {
2061                                         dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2062                                                 input[i + 1], od_table->GfxclkFmin);
2063                                         return -EINVAL;
2064                                 }
2065
2066                                 freq_setting = SMU_11_0_7_ODSETTING_GFXCLKFMAX;
2067                                 freq_ptr = &od_table->GfxclkFmax;
2068                                 break;
2069
2070                         default:
2071                                 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2072                                 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2073                                 return -EINVAL;
2074                         }
2075
2076                         ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2077                                                                     freq_setting, input[i + 1]);
2078                         if (ret)
2079                                 return ret;
2080
2081                         *freq_ptr = (uint16_t)input[i + 1];
2082                 }
2083                 break;
2084
2085         case PP_OD_EDIT_MCLK_VDDC_TABLE:
2086                 if (!sienna_cichlid_is_od_feature_supported(od_settings, SMU_11_0_7_ODCAP_UCLK_LIMITS)) {
2087                         dev_warn(smu->adev->dev, "UCLK_LIMITS not supported!\n");
2088                         return -ENOTSUPP;
2089                 }
2090
2091                 for (i = 0; i < size; i += 2) {
2092                         if (i + 2 > size) {
2093                                 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2094                                 return -EINVAL;
2095                         }
2096
2097                         switch (input[i]) {
2098                         case 0:
2099                                 if (input[i + 1] > od_table->UclkFmax) {
2100                                         dev_info(smu->adev->dev, "UclkFmin (%ld) must be <= UclkFmax (%u)!\n",
2101                                                 input[i + 1], od_table->UclkFmax);
2102                                         return -EINVAL;
2103                                 }
2104
2105                                 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMIN;
2106                                 freq_ptr = &od_table->UclkFmin;
2107                                 break;
2108
2109                         case 1:
2110                                 if (input[i + 1] < od_table->UclkFmin) {
2111                                         dev_info(smu->adev->dev, "UclkFmax (%ld) must be >= UclkFmin (%u)!\n",
2112                                                 input[i + 1], od_table->UclkFmin);
2113                                         return -EINVAL;
2114                                 }
2115
2116                                 freq_setting = SMU_11_0_7_ODSETTING_UCLKFMAX;
2117                                 freq_ptr = &od_table->UclkFmax;
2118                                 break;
2119
2120                         default:
2121                                 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[i]);
2122                                 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2123                                 return -EINVAL;
2124                         }
2125
2126                         ret = sienna_cichlid_od_setting_check_range(smu, od_settings,
2127                                                                     freq_setting, input[i + 1]);
2128                         if (ret)
2129                                 return ret;
2130
2131                         *freq_ptr = (uint16_t)input[i + 1];
2132                 }
2133                 break;
2134
2135         case PP_OD_RESTORE_DEFAULT_TABLE:
2136                 memcpy(table_context->overdrive_table,
2137                                 table_context->boot_overdrive_table,
2138                                 sizeof(OverDriveTable_t));
2139                 fallthrough;
2140
2141         case PP_OD_COMMIT_DPM_TABLE:
2142                 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2143                         sienna_cichlid_dump_od_table(smu, od_table);
2144                         ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2145                         if (ret) {
2146                                 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2147                                 return ret;
2148                         }
2149                         memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2150                         smu->user_dpm_profile.user_od = true;
2151
2152                         if (!memcmp(table_context->user_overdrive_table,
2153                                     table_context->boot_overdrive_table,
2154                                     sizeof(OverDriveTable_t)))
2155                                 smu->user_dpm_profile.user_od = false;
2156                 }
2157                 break;
2158
2159         case PP_OD_EDIT_VDDGFX_OFFSET:
2160                 if (size != 1) {
2161                         dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2162                         return -EINVAL;
2163                 }
2164
2165                 /*
2166                  * OD GFX Voltage Offset functionality is supported only by 58.41.0
2167                  * and onwards SMU firmwares.
2168                  */
2169                 smu_cmn_get_smc_version(smu, NULL, &smu_version);
2170                 if ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
2171                      (smu_version < 0x003a2900)) {
2172                         dev_err(smu->adev->dev, "OD GFX Voltage offset functionality is supported "
2173                                                 "only by 58.41.0 and onwards SMU firmwares!\n");
2174                         return -EOPNOTSUPP;
2175                 }
2176
2177                 od_table->VddGfxOffset = (int16_t)input[0];
2178
2179                 sienna_cichlid_dump_od_table(smu, od_table);
2180                 break;
2181
2182         default:
2183                 return -ENOSYS;
2184         }
2185
2186         return ret;
2187 }
2188
2189 static int sienna_cichlid_run_btc(struct smu_context *smu)
2190 {
2191         return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
2192 }
2193
2194 static int sienna_cichlid_baco_enter(struct smu_context *smu)
2195 {
2196         struct amdgpu_device *adev = smu->adev;
2197
2198         if (adev->in_runpm)
2199                 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2200         else
2201                 return smu_v11_0_baco_enter(smu);
2202 }
2203
2204 static int sienna_cichlid_baco_exit(struct smu_context *smu)
2205 {
2206         struct amdgpu_device *adev = smu->adev;
2207
2208         if (adev->in_runpm) {
2209                 /* Wait for PMFW handling for the Dstate change */
2210                 msleep(10);
2211                 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2212         } else {
2213                 return smu_v11_0_baco_exit(smu);
2214         }
2215 }
2216
2217 static bool sienna_cichlid_is_mode1_reset_supported(struct smu_context *smu)
2218 {
2219         struct amdgpu_device *adev = smu->adev;
2220         uint32_t val;
2221         u32 smu_version;
2222
2223         /**
2224          * SRIOV env will not support SMU mode1 reset
2225          * PM FW support mode1 reset from 58.26
2226          */
2227         smu_cmn_get_smc_version(smu, NULL, &smu_version);
2228         if (amdgpu_sriov_vf(adev) || (smu_version < 0x003a1a00))
2229                 return false;
2230
2231         /**
2232          * mode1 reset relies on PSP, so we should check if
2233          * PSP is alive.
2234          */
2235         val = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
2236         return val != 0x0;
2237 }
2238
2239 static void beige_goby_dump_pptable(struct smu_context *smu)
2240 {
2241         struct smu_table_context *table_context = &smu->smu_table;
2242         PPTable_beige_goby_t *pptable = table_context->driver_pptable;
2243         int i;
2244
2245         dev_info(smu->adev->dev, "Dumped PPTable:\n");
2246
2247         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2248         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2249         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2250
2251         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2252                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2253                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2254                 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2255                 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2256         }
2257
2258         for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2259                 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2260                 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2261         }
2262
2263         for (i = 0; i < TEMP_COUNT; i++) {
2264                 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2265         }
2266
2267         dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2268         dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2269         dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2270         dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2271         dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2272
2273         dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2274         for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2275                 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2276                 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2277         }
2278         dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2279
2280         dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2281
2282         dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2283         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2284         dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2285         dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2286
2287         dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2288
2289         dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2290
2291         dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2292         dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2293         dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2294         dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2295
2296         dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2297         dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2298
2299         dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2300         dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2301         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2302         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2303         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2304         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2305         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2306         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2307
2308         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2309                         "  .VoltageMode          = 0x%02x\n"
2310                         "  .SnapToDiscrete       = 0x%02x\n"
2311                         "  .NumDiscreteLevels    = 0x%02x\n"
2312                         "  .padding              = 0x%02x\n"
2313                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2314                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2315                         "  .SsFmin               = 0x%04x\n"
2316                         "  .Padding_16           = 0x%04x\n",
2317                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2318                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2319                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2320                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2321                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2322                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2323                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2324                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2325                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2326                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2327                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2328
2329         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2330                         "  .VoltageMode          = 0x%02x\n"
2331                         "  .SnapToDiscrete       = 0x%02x\n"
2332                         "  .NumDiscreteLevels    = 0x%02x\n"
2333                         "  .padding              = 0x%02x\n"
2334                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2335                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2336                         "  .SsFmin               = 0x%04x\n"
2337                         "  .Padding_16           = 0x%04x\n",
2338                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2339                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2340                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2341                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2342                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2343                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2344                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2345                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2346                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2347                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2348                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2349
2350         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2351                         "  .VoltageMode          = 0x%02x\n"
2352                         "  .SnapToDiscrete       = 0x%02x\n"
2353                         "  .NumDiscreteLevels    = 0x%02x\n"
2354                         "  .padding              = 0x%02x\n"
2355                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2356                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2357                         "  .SsFmin               = 0x%04x\n"
2358                         "  .Padding_16           = 0x%04x\n",
2359                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2360                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2361                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
2362                         pptable->DpmDescriptor[PPCLK_UCLK].Padding,
2363                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
2364                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
2365                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
2366                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
2367                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
2368                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
2369                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
2370
2371         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
2372                         "  .VoltageMode          = 0x%02x\n"
2373                         "  .SnapToDiscrete       = 0x%02x\n"
2374                         "  .NumDiscreteLevels    = 0x%02x\n"
2375                         "  .padding              = 0x%02x\n"
2376                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2377                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2378                         "  .SsFmin               = 0x%04x\n"
2379                         "  .Padding_16           = 0x%04x\n",
2380                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
2381                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
2382                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
2383                         pptable->DpmDescriptor[PPCLK_FCLK].Padding,
2384                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
2385                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
2386                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
2387                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
2388                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
2389                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
2390                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
2391
2392         dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
2393                         "  .VoltageMode          = 0x%02x\n"
2394                         "  .SnapToDiscrete       = 0x%02x\n"
2395                         "  .NumDiscreteLevels    = 0x%02x\n"
2396                         "  .padding              = 0x%02x\n"
2397                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2398                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2399                         "  .SsFmin               = 0x%04x\n"
2400                         "  .Padding_16           = 0x%04x\n",
2401                         pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
2402                         pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
2403                         pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
2404                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
2405                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
2406                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
2407                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
2408                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
2409                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
2410                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
2411                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
2412
2413         dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
2414                         "  .VoltageMode          = 0x%02x\n"
2415                         "  .SnapToDiscrete       = 0x%02x\n"
2416                         "  .NumDiscreteLevels    = 0x%02x\n"
2417                         "  .padding              = 0x%02x\n"
2418                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2419                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2420                         "  .SsFmin               = 0x%04x\n"
2421                         "  .Padding_16           = 0x%04x\n",
2422                         pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
2423                         pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
2424                         pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
2425                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
2426                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
2427                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
2428                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
2429                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
2430                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
2431                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
2432                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
2433
2434         dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
2435                         "  .VoltageMode          = 0x%02x\n"
2436                         "  .SnapToDiscrete       = 0x%02x\n"
2437                         "  .NumDiscreteLevels    = 0x%02x\n"
2438                         "  .padding              = 0x%02x\n"
2439                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2440                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2441                         "  .SsFmin               = 0x%04x\n"
2442                         "  .Padding_16           = 0x%04x\n",
2443                         pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
2444                         pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
2445                         pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
2446                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
2447                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
2448                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
2449                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
2450                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
2451                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
2452                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
2453                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
2454
2455         dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
2456                         "  .VoltageMode          = 0x%02x\n"
2457                         "  .SnapToDiscrete       = 0x%02x\n"
2458                         "  .NumDiscreteLevels    = 0x%02x\n"
2459                         "  .padding              = 0x%02x\n"
2460                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2461                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2462                         "  .SsFmin               = 0x%04x\n"
2463                         "  .Padding_16           = 0x%04x\n",
2464                         pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
2465                         pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
2466                         pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
2467                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
2468                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
2469                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
2470                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
2471                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
2472                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
2473                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
2474                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
2475
2476         dev_info(smu->adev->dev, "FreqTableGfx\n");
2477         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
2478                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
2479
2480         dev_info(smu->adev->dev, "FreqTableVclk\n");
2481         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
2482                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
2483
2484         dev_info(smu->adev->dev, "FreqTableDclk\n");
2485         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
2486                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
2487
2488         dev_info(smu->adev->dev, "FreqTableSocclk\n");
2489         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
2490                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
2491
2492         dev_info(smu->adev->dev, "FreqTableUclk\n");
2493         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2494                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
2495
2496         dev_info(smu->adev->dev, "FreqTableFclk\n");
2497         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
2498                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
2499
2500         dev_info(smu->adev->dev, "DcModeMaxFreq\n");
2501         dev_info(smu->adev->dev, "  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
2502         dev_info(smu->adev->dev, "  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
2503         dev_info(smu->adev->dev, "  .PPCLK_UCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
2504         dev_info(smu->adev->dev, "  .PPCLK_FCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
2505         dev_info(smu->adev->dev, "  .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
2506         dev_info(smu->adev->dev, "  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
2507         dev_info(smu->adev->dev, "  .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
2508         dev_info(smu->adev->dev, "  .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
2509
2510         dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
2511         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2512                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
2513
2514         dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
2515         dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
2516
2517         dev_info(smu->adev->dev, "Mp0clkFreq\n");
2518         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2519                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
2520
2521         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
2522         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
2523                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
2524
2525         dev_info(smu->adev->dev, "MemVddciVoltage\n");
2526         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2527                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
2528
2529         dev_info(smu->adev->dev, "MemMvddVoltage\n");
2530         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2531                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
2532
2533         dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
2534         dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
2535         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
2536         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
2537         dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
2538
2539         dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
2540
2541         dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
2542         dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
2543         dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
2544         dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
2545         dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
2546         dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
2547         dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
2548         dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
2549         dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
2550         dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
2551         dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
2552
2553         dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
2554         dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
2555         dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
2556         dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
2557         dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
2558         dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
2559
2560         dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
2561         dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
2562         dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
2563         dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
2564         dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
2565
2566         dev_info(smu->adev->dev, "FlopsPerByteTable\n");
2567         for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
2568                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
2569
2570         dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
2571         dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
2572         dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
2573         dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
2574
2575         dev_info(smu->adev->dev, "UclkDpmPstates\n");
2576         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
2577                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
2578
2579         dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
2580         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2581                 pptable->UclkDpmSrcFreqRange.Fmin);
2582         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2583                 pptable->UclkDpmSrcFreqRange.Fmax);
2584         dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
2585         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
2586                 pptable->UclkDpmTargFreqRange.Fmin);
2587         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
2588                 pptable->UclkDpmTargFreqRange.Fmax);
2589         dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
2590         dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
2591
2592         dev_info(smu->adev->dev, "PcieGenSpeed\n");
2593         for (i = 0; i < NUM_LINK_LEVELS; i++)
2594                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
2595
2596         dev_info(smu->adev->dev, "PcieLaneCount\n");
2597         for (i = 0; i < NUM_LINK_LEVELS; i++)
2598                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
2599
2600         dev_info(smu->adev->dev, "LclkFreq\n");
2601         for (i = 0; i < NUM_LINK_LEVELS; i++)
2602                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
2603
2604         dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
2605         dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
2606
2607         dev_info(smu->adev->dev, "FanGain\n");
2608         for (i = 0; i < TEMP_COUNT; i++)
2609                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FanGain[i]);
2610
2611         dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
2612         dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
2613         dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
2614         dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
2615         dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
2616         dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
2617         dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
2618         dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
2619         dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
2620         dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
2621         dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
2622         dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
2623
2624         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
2625         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
2626         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
2627         dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
2628
2629         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
2630         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
2631         dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
2632         dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
2633
2634         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2635                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
2636                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
2637                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
2638         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2639                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
2640                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
2641                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
2642         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
2643                         pptable->dBtcGbGfxPll.a,
2644                         pptable->dBtcGbGfxPll.b,
2645                         pptable->dBtcGbGfxPll.c);
2646         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
2647                         pptable->dBtcGbGfxDfll.a,
2648                         pptable->dBtcGbGfxDfll.b,
2649                         pptable->dBtcGbGfxDfll.c);
2650         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
2651                         pptable->dBtcGbSoc.a,
2652                         pptable->dBtcGbSoc.b,
2653                         pptable->dBtcGbSoc.c);
2654         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
2655                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
2656                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
2657         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
2658                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
2659                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
2660
2661         dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
2662         for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
2663                 dev_info(smu->adev->dev, "              Fset[%d] = 0x%x\n",
2664                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
2665                 dev_info(smu->adev->dev, "              Vdroop[%d] = 0x%x\n",
2666                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
2667         }
2668
2669         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
2670                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
2671                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
2672                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
2673         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
2674                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
2675                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
2676                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
2677
2678         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
2679         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
2680
2681         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
2682         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
2683         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
2684         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
2685
2686         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
2687         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
2688         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
2689         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
2690
2691         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
2692         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
2693
2694         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
2695         for (i = 0; i < NUM_XGMI_LEVELS; i++)
2696                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
2697         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
2698         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
2699
2700         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
2701         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
2702                         pptable->ReservedEquation0.a,
2703                         pptable->ReservedEquation0.b,
2704                         pptable->ReservedEquation0.c);
2705         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
2706                         pptable->ReservedEquation1.a,
2707                         pptable->ReservedEquation1.b,
2708                         pptable->ReservedEquation1.c);
2709         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
2710                         pptable->ReservedEquation2.a,
2711                         pptable->ReservedEquation2.b,
2712                         pptable->ReservedEquation2.c);
2713         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
2714                         pptable->ReservedEquation3.a,
2715                         pptable->ReservedEquation3.b,
2716                         pptable->ReservedEquation3.c);
2717
2718         dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
2719         dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
2720         dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
2721         dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
2722         dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
2723         dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
2724         dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
2725         dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
2726
2727         dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
2728         dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
2729         dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
2730         dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
2731         dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
2732         dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
2733
2734         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
2735                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
2736                 dev_info(smu->adev->dev, "                   .Enabled = 0x%x\n",
2737                                 pptable->I2cControllers[i].Enabled);
2738                 dev_info(smu->adev->dev, "                   .Speed = 0x%x\n",
2739                                 pptable->I2cControllers[i].Speed);
2740                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
2741                                 pptable->I2cControllers[i].SlaveAddress);
2742                 dev_info(smu->adev->dev, "                   .ControllerPort = 0x%x\n",
2743                                 pptable->I2cControllers[i].ControllerPort);
2744                 dev_info(smu->adev->dev, "                   .ControllerName = 0x%x\n",
2745                                 pptable->I2cControllers[i].ControllerName);
2746                 dev_info(smu->adev->dev, "                   .ThermalThrottler = 0x%x\n",
2747                                 pptable->I2cControllers[i].ThermalThrotter);
2748                 dev_info(smu->adev->dev, "                   .I2cProtocol = 0x%x\n",
2749                                 pptable->I2cControllers[i].I2cProtocol);
2750                 dev_info(smu->adev->dev, "                   .PaddingConfig = 0x%x\n",
2751                                 pptable->I2cControllers[i].PaddingConfig);
2752         }
2753
2754         dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
2755         dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
2756         dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
2757         dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
2758
2759         dev_info(smu->adev->dev, "Board Parameters:\n");
2760         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
2761         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
2762         dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
2763         dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
2764         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
2765         dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
2766         dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
2767         dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
2768
2769         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
2770         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
2771         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
2772
2773         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
2774         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
2775         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
2776
2777         dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
2778         dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
2779         dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
2780
2781         dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
2782         dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
2783         dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
2784
2785         dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
2786
2787         dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
2788         dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
2789         dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
2790         dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
2791         dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
2792         dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
2793         dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
2794         dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
2795         dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
2796         dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
2797         dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
2798         dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
2799         dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
2800         dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
2801         dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
2802         dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
2803
2804         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
2805         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
2806         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n",    pptable->PllGfxclkSpreadFreq);
2807
2808         dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
2809         dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
2810         dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n",    pptable->DfllGfxclkSpreadFreq);
2811
2812         dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
2813         dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
2814
2815         dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
2816         dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
2817         dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
2818
2819         dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
2820         dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
2821         dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
2822         dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
2823         dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
2824
2825         dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
2826         dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
2827
2828         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
2829         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2830                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
2831         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
2832         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2833                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
2834         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
2835         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2836                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
2837         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
2838         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2839                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
2840
2841         dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
2842         dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
2843         dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
2844         dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
2845
2846         dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
2847         dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
2848         dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
2849         dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
2850         dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
2851         dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
2852         dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
2853         dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
2854         dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
2855         dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
2856         dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
2857
2858         dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
2859         dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
2860         dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
2861         dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
2862         dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
2863         dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
2864         dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
2865         dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
2866 }
2867
2868 static void sienna_cichlid_dump_pptable(struct smu_context *smu)
2869 {
2870         struct smu_table_context *table_context = &smu->smu_table;
2871         PPTable_t *pptable = table_context->driver_pptable;
2872         int i;
2873
2874         if (smu->adev->asic_type == CHIP_BEIGE_GOBY) {
2875                 beige_goby_dump_pptable(smu);
2876                 return;
2877         }
2878
2879         dev_info(smu->adev->dev, "Dumped PPTable:\n");
2880
2881         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
2882         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
2883         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
2884
2885         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
2886                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = 0x%x\n", i, pptable->SocketPowerLimitAc[i]);
2887                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitAcTau[i]);
2888                 dev_info(smu->adev->dev, "SocketPowerLimitDc[%d] = 0x%x\n", i, pptable->SocketPowerLimitDc[i]);
2889                 dev_info(smu->adev->dev, "SocketPowerLimitDcTau[%d] = 0x%x\n", i, pptable->SocketPowerLimitDcTau[i]);
2890         }
2891
2892         for (i = 0; i < TDC_THROTTLER_COUNT; i++) {
2893                 dev_info(smu->adev->dev, "TdcLimit[%d] = 0x%x\n", i, pptable->TdcLimit[i]);
2894                 dev_info(smu->adev->dev, "TdcLimitTau[%d] = 0x%x\n", i, pptable->TdcLimitTau[i]);
2895         }
2896
2897         for (i = 0; i < TEMP_COUNT; i++) {
2898                 dev_info(smu->adev->dev, "TemperatureLimit[%d] = 0x%x\n", i, pptable->TemperatureLimit[i]);
2899         }
2900
2901         dev_info(smu->adev->dev, "FitLimit = 0x%x\n", pptable->FitLimit);
2902         dev_info(smu->adev->dev, "TotalPowerConfig = 0x%x\n", pptable->TotalPowerConfig);
2903         dev_info(smu->adev->dev, "TotalPowerPadding[0] = 0x%x\n", pptable->TotalPowerPadding[0]);
2904         dev_info(smu->adev->dev, "TotalPowerPadding[1] = 0x%x\n", pptable->TotalPowerPadding[1]);
2905         dev_info(smu->adev->dev, "TotalPowerPadding[2] = 0x%x\n", pptable->TotalPowerPadding[2]);
2906
2907         dev_info(smu->adev->dev, "ApccPlusResidencyLimit = 0x%x\n", pptable->ApccPlusResidencyLimit);
2908         for (i = 0; i < NUM_SMNCLK_DPM_LEVELS; i++) {
2909                 dev_info(smu->adev->dev, "SmnclkDpmFreq[%d] = 0x%x\n", i, pptable->SmnclkDpmFreq[i]);
2910                 dev_info(smu->adev->dev, "SmnclkDpmVoltage[%d] = 0x%x\n", i, pptable->SmnclkDpmVoltage[i]);
2911         }
2912         dev_info(smu->adev->dev, "ThrottlerControlMask = 0x%x\n", pptable->ThrottlerControlMask);
2913
2914         dev_info(smu->adev->dev, "FwDStateMask = 0x%x\n", pptable->FwDStateMask);
2915
2916         dev_info(smu->adev->dev, "UlvVoltageOffsetSoc = 0x%x\n", pptable->UlvVoltageOffsetSoc);
2917         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = 0x%x\n", pptable->UlvVoltageOffsetGfx);
2918         dev_info(smu->adev->dev, "MinVoltageUlvGfx = 0x%x\n", pptable->MinVoltageUlvGfx);
2919         dev_info(smu->adev->dev, "MinVoltageUlvSoc = 0x%x\n", pptable->MinVoltageUlvSoc);
2920
2921         dev_info(smu->adev->dev, "SocLIVmin = 0x%x\n", pptable->SocLIVmin);
2922         dev_info(smu->adev->dev, "PaddingLIVmin = 0x%x\n", pptable->PaddingLIVmin);
2923
2924         dev_info(smu->adev->dev, "GceaLinkMgrIdleThreshold = 0x%x\n", pptable->GceaLinkMgrIdleThreshold);
2925         dev_info(smu->adev->dev, "paddingRlcUlvParams[0] = 0x%x\n", pptable->paddingRlcUlvParams[0]);
2926         dev_info(smu->adev->dev, "paddingRlcUlvParams[1] = 0x%x\n", pptable->paddingRlcUlvParams[1]);
2927         dev_info(smu->adev->dev, "paddingRlcUlvParams[2] = 0x%x\n", pptable->paddingRlcUlvParams[2]);
2928
2929         dev_info(smu->adev->dev, "MinVoltageGfx = 0x%x\n", pptable->MinVoltageGfx);
2930         dev_info(smu->adev->dev, "MinVoltageSoc = 0x%x\n", pptable->MinVoltageSoc);
2931         dev_info(smu->adev->dev, "MaxVoltageGfx = 0x%x\n", pptable->MaxVoltageGfx);
2932         dev_info(smu->adev->dev, "MaxVoltageSoc = 0x%x\n", pptable->MaxVoltageSoc);
2933
2934         dev_info(smu->adev->dev, "LoadLineResistanceGfx = 0x%x\n", pptable->LoadLineResistanceGfx);
2935         dev_info(smu->adev->dev, "LoadLineResistanceSoc = 0x%x\n", pptable->LoadLineResistanceSoc);
2936
2937         dev_info(smu->adev->dev, "VDDGFX_TVmin = 0x%x\n", pptable->VDDGFX_TVmin);
2938         dev_info(smu->adev->dev, "VDDSOC_TVmin = 0x%x\n", pptable->VDDSOC_TVmin);
2939         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = 0x%x\n", pptable->VDDGFX_Vmin_HiTemp);
2940         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = 0x%x\n", pptable->VDDGFX_Vmin_LoTemp);
2941         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = 0x%x\n", pptable->VDDSOC_Vmin_HiTemp);
2942         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = 0x%x\n", pptable->VDDSOC_Vmin_LoTemp);
2943         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = 0x%x\n", pptable->VDDGFX_TVminHystersis);
2944         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = 0x%x\n", pptable->VDDSOC_TVminHystersis);
2945
2946         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
2947                         "  .VoltageMode          = 0x%02x\n"
2948                         "  .SnapToDiscrete       = 0x%02x\n"
2949                         "  .NumDiscreteLevels    = 0x%02x\n"
2950                         "  .padding              = 0x%02x\n"
2951                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2952                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2953                         "  .SsFmin               = 0x%04x\n"
2954                         "  .Padding_16           = 0x%04x\n",
2955                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
2956                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
2957                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
2958                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding,
2959                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
2960                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
2961                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
2962                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
2963                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
2964                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
2965                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
2966
2967         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
2968                         "  .VoltageMode          = 0x%02x\n"
2969                         "  .SnapToDiscrete       = 0x%02x\n"
2970                         "  .NumDiscreteLevels    = 0x%02x\n"
2971                         "  .padding              = 0x%02x\n"
2972                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2973                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2974                         "  .SsFmin               = 0x%04x\n"
2975                         "  .Padding_16           = 0x%04x\n",
2976                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
2977                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
2978                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
2979                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding,
2980                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
2981                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
2982                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
2983                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
2984                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
2985                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
2986                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
2987
2988         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
2989                         "  .VoltageMode          = 0x%02x\n"
2990                         "  .SnapToDiscrete       = 0x%02x\n"
2991                         "  .NumDiscreteLevels    = 0x%02x\n"
2992                         "  .padding              = 0x%02x\n"
2993                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
2994                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
2995                         "  .SsFmin               = 0x%04x\n"
2996                         "  .Padding_16           = 0x%04x\n",
2997                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
2998                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
2999                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
3000                         pptable->DpmDescriptor[PPCLK_UCLK].Padding,
3001                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
3002                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
3003                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
3004                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
3005                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
3006                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
3007                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
3008
3009         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
3010                         "  .VoltageMode          = 0x%02x\n"
3011                         "  .SnapToDiscrete       = 0x%02x\n"
3012                         "  .NumDiscreteLevels    = 0x%02x\n"
3013                         "  .padding              = 0x%02x\n"
3014                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3015                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3016                         "  .SsFmin               = 0x%04x\n"
3017                         "  .Padding_16           = 0x%04x\n",
3018                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
3019                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
3020                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
3021                         pptable->DpmDescriptor[PPCLK_FCLK].Padding,
3022                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
3023                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
3024                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
3025                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
3026                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
3027                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
3028                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
3029
3030         dev_info(smu->adev->dev, "[PPCLK_DCLK_0]\n"
3031                         "  .VoltageMode          = 0x%02x\n"
3032                         "  .SnapToDiscrete       = 0x%02x\n"
3033                         "  .NumDiscreteLevels    = 0x%02x\n"
3034                         "  .padding              = 0x%02x\n"
3035                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3036                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3037                         "  .SsFmin               = 0x%04x\n"
3038                         "  .Padding_16           = 0x%04x\n",
3039                         pptable->DpmDescriptor[PPCLK_DCLK_0].VoltageMode,
3040                         pptable->DpmDescriptor[PPCLK_DCLK_0].SnapToDiscrete,
3041                         pptable->DpmDescriptor[PPCLK_DCLK_0].NumDiscreteLevels,
3042                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding,
3043                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.m,
3044                         pptable->DpmDescriptor[PPCLK_DCLK_0].ConversionToAvfsClk.b,
3045                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.a,
3046                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.b,
3047                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsCurve.c,
3048                         pptable->DpmDescriptor[PPCLK_DCLK_0].SsFmin,
3049                         pptable->DpmDescriptor[PPCLK_DCLK_0].Padding16);
3050
3051         dev_info(smu->adev->dev, "[PPCLK_VCLK_0]\n"
3052                         "  .VoltageMode          = 0x%02x\n"
3053                         "  .SnapToDiscrete       = 0x%02x\n"
3054                         "  .NumDiscreteLevels    = 0x%02x\n"
3055                         "  .padding              = 0x%02x\n"
3056                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3057                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3058                         "  .SsFmin               = 0x%04x\n"
3059                         "  .Padding_16           = 0x%04x\n",
3060                         pptable->DpmDescriptor[PPCLK_VCLK_0].VoltageMode,
3061                         pptable->DpmDescriptor[PPCLK_VCLK_0].SnapToDiscrete,
3062                         pptable->DpmDescriptor[PPCLK_VCLK_0].NumDiscreteLevels,
3063                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding,
3064                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.m,
3065                         pptable->DpmDescriptor[PPCLK_VCLK_0].ConversionToAvfsClk.b,
3066                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.a,
3067                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.b,
3068                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsCurve.c,
3069                         pptable->DpmDescriptor[PPCLK_VCLK_0].SsFmin,
3070                         pptable->DpmDescriptor[PPCLK_VCLK_0].Padding16);
3071
3072         dev_info(smu->adev->dev, "[PPCLK_DCLK_1]\n"
3073                         "  .VoltageMode          = 0x%02x\n"
3074                         "  .SnapToDiscrete       = 0x%02x\n"
3075                         "  .NumDiscreteLevels    = 0x%02x\n"
3076                         "  .padding              = 0x%02x\n"
3077                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3078                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3079                         "  .SsFmin               = 0x%04x\n"
3080                         "  .Padding_16           = 0x%04x\n",
3081                         pptable->DpmDescriptor[PPCLK_DCLK_1].VoltageMode,
3082                         pptable->DpmDescriptor[PPCLK_DCLK_1].SnapToDiscrete,
3083                         pptable->DpmDescriptor[PPCLK_DCLK_1].NumDiscreteLevels,
3084                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding,
3085                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.m,
3086                         pptable->DpmDescriptor[PPCLK_DCLK_1].ConversionToAvfsClk.b,
3087                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.a,
3088                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.b,
3089                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsCurve.c,
3090                         pptable->DpmDescriptor[PPCLK_DCLK_1].SsFmin,
3091                         pptable->DpmDescriptor[PPCLK_DCLK_1].Padding16);
3092
3093         dev_info(smu->adev->dev, "[PPCLK_VCLK_1]\n"
3094                         "  .VoltageMode          = 0x%02x\n"
3095                         "  .SnapToDiscrete       = 0x%02x\n"
3096                         "  .NumDiscreteLevels    = 0x%02x\n"
3097                         "  .padding              = 0x%02x\n"
3098                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
3099                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
3100                         "  .SsFmin               = 0x%04x\n"
3101                         "  .Padding_16           = 0x%04x\n",
3102                         pptable->DpmDescriptor[PPCLK_VCLK_1].VoltageMode,
3103                         pptable->DpmDescriptor[PPCLK_VCLK_1].SnapToDiscrete,
3104                         pptable->DpmDescriptor[PPCLK_VCLK_1].NumDiscreteLevels,
3105                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding,
3106                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.m,
3107                         pptable->DpmDescriptor[PPCLK_VCLK_1].ConversionToAvfsClk.b,
3108                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.a,
3109                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.b,
3110                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsCurve.c,
3111                         pptable->DpmDescriptor[PPCLK_VCLK_1].SsFmin,
3112                         pptable->DpmDescriptor[PPCLK_VCLK_1].Padding16);
3113
3114         dev_info(smu->adev->dev, "FreqTableGfx\n");
3115         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
3116                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableGfx[i]);
3117
3118         dev_info(smu->adev->dev, "FreqTableVclk\n");
3119         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
3120                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableVclk[i]);
3121
3122         dev_info(smu->adev->dev, "FreqTableDclk\n");
3123         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
3124                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableDclk[i]);
3125
3126         dev_info(smu->adev->dev, "FreqTableSocclk\n");
3127         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
3128                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableSocclk[i]);
3129
3130         dev_info(smu->adev->dev, "FreqTableUclk\n");
3131         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3132                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableUclk[i]);
3133
3134         dev_info(smu->adev->dev, "FreqTableFclk\n");
3135         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
3136                 dev_info(smu->adev->dev, "  .[%02d] = 0x%x\n", i, pptable->FreqTableFclk[i]);
3137
3138         dev_info(smu->adev->dev, "DcModeMaxFreq\n");
3139         dev_info(smu->adev->dev, "  .PPCLK_GFXCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_GFXCLK]);
3140         dev_info(smu->adev->dev, "  .PPCLK_SOCCLK = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_SOCCLK]);
3141         dev_info(smu->adev->dev, "  .PPCLK_UCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_UCLK]);
3142         dev_info(smu->adev->dev, "  .PPCLK_FCLK   = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_FCLK]);
3143         dev_info(smu->adev->dev, "  .PPCLK_DCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_0]);
3144         dev_info(smu->adev->dev, "  .PPCLK_VCLK_0 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_0]);
3145         dev_info(smu->adev->dev, "  .PPCLK_DCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_DCLK_1]);
3146         dev_info(smu->adev->dev, "  .PPCLK_VCLK_1 = 0x%x\n", pptable->DcModeMaxFreq[PPCLK_VCLK_1]);
3147
3148         dev_info(smu->adev->dev, "FreqTableUclkDiv\n");
3149         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3150                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FreqTableUclkDiv[i]);
3151
3152         dev_info(smu->adev->dev, "FclkBoostFreq = 0x%x\n", pptable->FclkBoostFreq);
3153         dev_info(smu->adev->dev, "FclkParamPadding = 0x%x\n", pptable->FclkParamPadding);
3154
3155         dev_info(smu->adev->dev, "Mp0clkFreq\n");
3156         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3157                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0clkFreq[i]);
3158
3159         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
3160         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
3161                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->Mp0DpmVoltage[i]);
3162
3163         dev_info(smu->adev->dev, "MemVddciVoltage\n");
3164         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3165                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemVddciVoltage[i]);
3166
3167         dev_info(smu->adev->dev, "MemMvddVoltage\n");
3168         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3169                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->MemMvddVoltage[i]);
3170
3171         dev_info(smu->adev->dev, "GfxclkFgfxoffEntry = 0x%x\n", pptable->GfxclkFgfxoffEntry);
3172         dev_info(smu->adev->dev, "GfxclkFinit = 0x%x\n", pptable->GfxclkFinit);
3173         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
3174         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
3175         dev_info(smu->adev->dev, "GfxclkPadding = 0x%x\n", pptable->GfxclkPadding);
3176
3177         dev_info(smu->adev->dev, "GfxGpoSubFeatureMask = 0x%x\n", pptable->GfxGpoSubFeatureMask);
3178
3179         dev_info(smu->adev->dev, "GfxGpoEnabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoEnabledWorkPolicyMask);
3180         dev_info(smu->adev->dev, "GfxGpoDisabledWorkPolicyMask = 0x%x\n", pptable->GfxGpoDisabledWorkPolicyMask);
3181         dev_info(smu->adev->dev, "GfxGpoPadding[0] = 0x%x\n", pptable->GfxGpoPadding[0]);
3182         dev_info(smu->adev->dev, "GfxGpoVotingAllow = 0x%x\n", pptable->GfxGpoVotingAllow);
3183         dev_info(smu->adev->dev, "GfxGpoPadding32[0] = 0x%x\n", pptable->GfxGpoPadding32[0]);
3184         dev_info(smu->adev->dev, "GfxGpoPadding32[1] = 0x%x\n", pptable->GfxGpoPadding32[1]);
3185         dev_info(smu->adev->dev, "GfxGpoPadding32[2] = 0x%x\n", pptable->GfxGpoPadding32[2]);
3186         dev_info(smu->adev->dev, "GfxGpoPadding32[3] = 0x%x\n", pptable->GfxGpoPadding32[3]);
3187         dev_info(smu->adev->dev, "GfxDcsFopt = 0x%x\n", pptable->GfxDcsFopt);
3188         dev_info(smu->adev->dev, "GfxDcsFclkFopt = 0x%x\n", pptable->GfxDcsFclkFopt);
3189         dev_info(smu->adev->dev, "GfxDcsUclkFopt = 0x%x\n", pptable->GfxDcsUclkFopt);
3190
3191         dev_info(smu->adev->dev, "DcsGfxOffVoltage = 0x%x\n", pptable->DcsGfxOffVoltage);
3192         dev_info(smu->adev->dev, "DcsMinGfxOffTime = 0x%x\n", pptable->DcsMinGfxOffTime);
3193         dev_info(smu->adev->dev, "DcsMaxGfxOffTime = 0x%x\n", pptable->DcsMaxGfxOffTime);
3194         dev_info(smu->adev->dev, "DcsMinCreditAccum = 0x%x\n", pptable->DcsMinCreditAccum);
3195         dev_info(smu->adev->dev, "DcsExitHysteresis = 0x%x\n", pptable->DcsExitHysteresis);
3196         dev_info(smu->adev->dev, "DcsTimeout = 0x%x\n", pptable->DcsTimeout);
3197
3198         dev_info(smu->adev->dev, "DcsParamPadding[0] = 0x%x\n", pptable->DcsParamPadding[0]);
3199         dev_info(smu->adev->dev, "DcsParamPadding[1] = 0x%x\n", pptable->DcsParamPadding[1]);
3200         dev_info(smu->adev->dev, "DcsParamPadding[2] = 0x%x\n", pptable->DcsParamPadding[2]);
3201         dev_info(smu->adev->dev, "DcsParamPadding[3] = 0x%x\n", pptable->DcsParamPadding[3]);
3202         dev_info(smu->adev->dev, "DcsParamPadding[4] = 0x%x\n", pptable->DcsParamPadding[4]);
3203
3204         dev_info(smu->adev->dev, "FlopsPerByteTable\n");
3205         for (i = 0; i < RLC_PACE_TABLE_NUM_LEVELS; i++)
3206                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FlopsPerByteTable[i]);
3207
3208         dev_info(smu->adev->dev, "LowestUclkReservedForUlv = 0x%x\n", pptable->LowestUclkReservedForUlv);
3209         dev_info(smu->adev->dev, "vddingMem[0] = 0x%x\n", pptable->PaddingMem[0]);
3210         dev_info(smu->adev->dev, "vddingMem[1] = 0x%x\n", pptable->PaddingMem[1]);
3211         dev_info(smu->adev->dev, "vddingMem[2] = 0x%x\n", pptable->PaddingMem[2]);
3212
3213         dev_info(smu->adev->dev, "UclkDpmPstates\n");
3214         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
3215                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->UclkDpmPstates[i]);
3216
3217         dev_info(smu->adev->dev, "UclkDpmSrcFreqRange\n");
3218         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
3219                 pptable->UclkDpmSrcFreqRange.Fmin);
3220         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
3221                 pptable->UclkDpmSrcFreqRange.Fmax);
3222         dev_info(smu->adev->dev, "UclkDpmTargFreqRange\n");
3223         dev_info(smu->adev->dev, "  .Fmin = 0x%x\n",
3224                 pptable->UclkDpmTargFreqRange.Fmin);
3225         dev_info(smu->adev->dev, "  .Fmax = 0x%x\n",
3226                 pptable->UclkDpmTargFreqRange.Fmax);
3227         dev_info(smu->adev->dev, "UclkDpmMidstepFreq = 0x%x\n", pptable->UclkDpmMidstepFreq);
3228         dev_info(smu->adev->dev, "UclkMidstepPadding = 0x%x\n", pptable->UclkMidstepPadding);
3229
3230         dev_info(smu->adev->dev, "PcieGenSpeed\n");
3231         for (i = 0; i < NUM_LINK_LEVELS; i++)
3232                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieGenSpeed[i]);
3233
3234         dev_info(smu->adev->dev, "PcieLaneCount\n");
3235         for (i = 0; i < NUM_LINK_LEVELS; i++)
3236                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->PcieLaneCount[i]);
3237
3238         dev_info(smu->adev->dev, "LclkFreq\n");
3239         for (i = 0; i < NUM_LINK_LEVELS; i++)
3240                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->LclkFreq[i]);
3241
3242         dev_info(smu->adev->dev, "FanStopTemp = 0x%x\n", pptable->FanStopTemp);
3243         dev_info(smu->adev->dev, "FanStartTemp = 0x%x\n", pptable->FanStartTemp);
3244
3245         dev_info(smu->adev->dev, "FanGain\n");
3246         for (i = 0; i < TEMP_COUNT; i++)
3247                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->FanGain[i]);
3248
3249         dev_info(smu->adev->dev, "FanPwmMin = 0x%x\n", pptable->FanPwmMin);
3250         dev_info(smu->adev->dev, "FanAcousticLimitRpm = 0x%x\n", pptable->FanAcousticLimitRpm);
3251         dev_info(smu->adev->dev, "FanThrottlingRpm = 0x%x\n", pptable->FanThrottlingRpm);
3252         dev_info(smu->adev->dev, "FanMaximumRpm = 0x%x\n", pptable->FanMaximumRpm);
3253         dev_info(smu->adev->dev, "MGpuFanBoostLimitRpm = 0x%x\n", pptable->MGpuFanBoostLimitRpm);
3254         dev_info(smu->adev->dev, "FanTargetTemperature = 0x%x\n", pptable->FanTargetTemperature);
3255         dev_info(smu->adev->dev, "FanTargetGfxclk = 0x%x\n", pptable->FanTargetGfxclk);
3256         dev_info(smu->adev->dev, "FanPadding16 = 0x%x\n", pptable->FanPadding16);
3257         dev_info(smu->adev->dev, "FanTempInputSelect = 0x%x\n", pptable->FanTempInputSelect);
3258         dev_info(smu->adev->dev, "FanPadding = 0x%x\n", pptable->FanPadding);
3259         dev_info(smu->adev->dev, "FanZeroRpmEnable = 0x%x\n", pptable->FanZeroRpmEnable);
3260         dev_info(smu->adev->dev, "FanTachEdgePerRev = 0x%x\n", pptable->FanTachEdgePerRev);
3261
3262         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorSetDelta);
3263         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = 0x%x\n", pptable->FuzzyFan_ErrorRateSetDelta);
3264         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = 0x%x\n", pptable->FuzzyFan_PwmSetDelta);
3265         dev_info(smu->adev->dev, "FuzzyFan_Reserved = 0x%x\n", pptable->FuzzyFan_Reserved);
3266
3267         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
3268         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
3269         dev_info(smu->adev->dev, "dBtcGbGfxDfllModelSelect = 0x%x\n", pptable->dBtcGbGfxDfllModelSelect);
3270         dev_info(smu->adev->dev, "Padding8_Avfs = 0x%x\n", pptable->Padding8_Avfs);
3271
3272         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3273                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].a,
3274                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].b,
3275                         pptable->qAvfsGb[AVFS_VOLTAGE_GFX].c);
3276         dev_info(smu->adev->dev, "qAvfsGb[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3277                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].a,
3278                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].b,
3279                         pptable->qAvfsGb[AVFS_VOLTAGE_SOC].c);
3280         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
3281                         pptable->dBtcGbGfxPll.a,
3282                         pptable->dBtcGbGfxPll.b,
3283                         pptable->dBtcGbGfxPll.c);
3284         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
3285                         pptable->dBtcGbGfxDfll.a,
3286                         pptable->dBtcGbGfxDfll.b,
3287                         pptable->dBtcGbGfxDfll.c);
3288         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
3289                         pptable->dBtcGbSoc.a,
3290                         pptable->dBtcGbSoc.b,
3291                         pptable->dBtcGbSoc.c);
3292         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
3293                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
3294                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
3295         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
3296                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
3297                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
3298
3299         dev_info(smu->adev->dev, "PiecewiseLinearDroopIntGfxDfll\n");
3300         for (i = 0; i < NUM_PIECE_WISE_LINEAR_DROOP_MODEL_VF_POINTS; i++) {
3301                 dev_info(smu->adev->dev, "              Fset[%d] = 0x%x\n",
3302                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Fset[i]);
3303                 dev_info(smu->adev->dev, "              Vdroop[%d] = 0x%x\n",
3304                         i, pptable->PiecewiseLinearDroopIntGfxDfll.Vdroop[i]);
3305         }
3306
3307         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
3308                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
3309                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
3310                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
3311         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
3312                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
3313                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
3314                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
3315
3316         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
3317         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
3318
3319         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
3320         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
3321         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
3322         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
3323
3324         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
3325         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
3326         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
3327         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
3328
3329         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
3330         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
3331
3332         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
3333         for (i = 0; i < NUM_XGMI_LEVELS; i++)
3334                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiDpmPstates[i]);
3335         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
3336         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
3337
3338         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
3339         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
3340                         pptable->ReservedEquation0.a,
3341                         pptable->ReservedEquation0.b,
3342                         pptable->ReservedEquation0.c);
3343         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
3344                         pptable->ReservedEquation1.a,
3345                         pptable->ReservedEquation1.b,
3346                         pptable->ReservedEquation1.c);
3347         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
3348                         pptable->ReservedEquation2.a,
3349                         pptable->ReservedEquation2.b,
3350                         pptable->ReservedEquation2.c);
3351         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
3352                         pptable->ReservedEquation3.a,
3353                         pptable->ReservedEquation3.b,
3354                         pptable->ReservedEquation3.c);
3355
3356         dev_info(smu->adev->dev, "SkuReserved[0] = 0x%x\n", pptable->SkuReserved[0]);
3357         dev_info(smu->adev->dev, "SkuReserved[1] = 0x%x\n", pptable->SkuReserved[1]);
3358         dev_info(smu->adev->dev, "SkuReserved[2] = 0x%x\n", pptable->SkuReserved[2]);
3359         dev_info(smu->adev->dev, "SkuReserved[3] = 0x%x\n", pptable->SkuReserved[3]);
3360         dev_info(smu->adev->dev, "SkuReserved[4] = 0x%x\n", pptable->SkuReserved[4]);
3361         dev_info(smu->adev->dev, "SkuReserved[5] = 0x%x\n", pptable->SkuReserved[5]);
3362         dev_info(smu->adev->dev, "SkuReserved[6] = 0x%x\n", pptable->SkuReserved[6]);
3363         dev_info(smu->adev->dev, "SkuReserved[7] = 0x%x\n", pptable->SkuReserved[7]);
3364
3365         dev_info(smu->adev->dev, "GamingClk[0] = 0x%x\n", pptable->GamingClk[0]);
3366         dev_info(smu->adev->dev, "GamingClk[1] = 0x%x\n", pptable->GamingClk[1]);
3367         dev_info(smu->adev->dev, "GamingClk[2] = 0x%x\n", pptable->GamingClk[2]);
3368         dev_info(smu->adev->dev, "GamingClk[3] = 0x%x\n", pptable->GamingClk[3]);
3369         dev_info(smu->adev->dev, "GamingClk[4] = 0x%x\n", pptable->GamingClk[4]);
3370         dev_info(smu->adev->dev, "GamingClk[5] = 0x%x\n", pptable->GamingClk[5]);
3371
3372         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
3373                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
3374                 dev_info(smu->adev->dev, "                   .Enabled = 0x%x\n",
3375                                 pptable->I2cControllers[i].Enabled);
3376                 dev_info(smu->adev->dev, "                   .Speed = 0x%x\n",
3377                                 pptable->I2cControllers[i].Speed);
3378                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
3379                                 pptable->I2cControllers[i].SlaveAddress);
3380                 dev_info(smu->adev->dev, "                   .ControllerPort = 0x%x\n",
3381                                 pptable->I2cControllers[i].ControllerPort);
3382                 dev_info(smu->adev->dev, "                   .ControllerName = 0x%x\n",
3383                                 pptable->I2cControllers[i].ControllerName);
3384                 dev_info(smu->adev->dev, "                   .ThermalThrottler = 0x%x\n",
3385                                 pptable->I2cControllers[i].ThermalThrotter);
3386                 dev_info(smu->adev->dev, "                   .I2cProtocol = 0x%x\n",
3387                                 pptable->I2cControllers[i].I2cProtocol);
3388                 dev_info(smu->adev->dev, "                   .PaddingConfig = 0x%x\n",
3389                                 pptable->I2cControllers[i].PaddingConfig);
3390         }
3391
3392         dev_info(smu->adev->dev, "GpioScl = 0x%x\n", pptable->GpioScl);
3393         dev_info(smu->adev->dev, "GpioSda = 0x%x\n", pptable->GpioSda);
3394         dev_info(smu->adev->dev, "FchUsbPdSlaveAddr = 0x%x\n", pptable->FchUsbPdSlaveAddr);
3395         dev_info(smu->adev->dev, "I2cSpare[0] = 0x%x\n", pptable->I2cSpare[0]);
3396
3397         dev_info(smu->adev->dev, "Board Parameters:\n");
3398         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
3399         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
3400         dev_info(smu->adev->dev, "VddMem0VrMapping = 0x%x\n", pptable->VddMem0VrMapping);
3401         dev_info(smu->adev->dev, "VddMem1VrMapping = 0x%x\n", pptable->VddMem1VrMapping);
3402         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
3403         dev_info(smu->adev->dev, "SocUlvPhaseSheddingMask = 0x%x\n", pptable->SocUlvPhaseSheddingMask);
3404         dev_info(smu->adev->dev, "VddciUlvPhaseSheddingMask = 0x%x\n", pptable->VddciUlvPhaseSheddingMask);
3405         dev_info(smu->adev->dev, "MvddUlvPhaseSheddingMask = 0x%x\n", pptable->MvddUlvPhaseSheddingMask);
3406
3407         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
3408         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
3409         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
3410
3411         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
3412         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
3413         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
3414
3415         dev_info(smu->adev->dev, "Mem0MaxCurrent = 0x%x\n", pptable->Mem0MaxCurrent);
3416         dev_info(smu->adev->dev, "Mem0Offset = 0x%x\n", pptable->Mem0Offset);
3417         dev_info(smu->adev->dev, "Padding_TelemetryMem0 = 0x%x\n", pptable->Padding_TelemetryMem0);
3418
3419         dev_info(smu->adev->dev, "Mem1MaxCurrent = 0x%x\n", pptable->Mem1MaxCurrent);
3420         dev_info(smu->adev->dev, "Mem1Offset = 0x%x\n", pptable->Mem1Offset);
3421         dev_info(smu->adev->dev, "Padding_TelemetryMem1 = 0x%x\n", pptable->Padding_TelemetryMem1);
3422
3423         dev_info(smu->adev->dev, "MvddRatio = 0x%x\n", pptable->MvddRatio);
3424
3425         dev_info(smu->adev->dev, "AcDcGpio = 0x%x\n", pptable->AcDcGpio);
3426         dev_info(smu->adev->dev, "AcDcPolarity = 0x%x\n", pptable->AcDcPolarity);
3427         dev_info(smu->adev->dev, "VR0HotGpio = 0x%x\n", pptable->VR0HotGpio);
3428         dev_info(smu->adev->dev, "VR0HotPolarity = 0x%x\n", pptable->VR0HotPolarity);
3429         dev_info(smu->adev->dev, "VR1HotGpio = 0x%x\n", pptable->VR1HotGpio);
3430         dev_info(smu->adev->dev, "VR1HotPolarity = 0x%x\n", pptable->VR1HotPolarity);
3431         dev_info(smu->adev->dev, "GthrGpio = 0x%x\n", pptable->GthrGpio);
3432         dev_info(smu->adev->dev, "GthrPolarity = 0x%x\n", pptable->GthrPolarity);
3433         dev_info(smu->adev->dev, "LedPin0 = 0x%x\n", pptable->LedPin0);
3434         dev_info(smu->adev->dev, "LedPin1 = 0x%x\n", pptable->LedPin1);
3435         dev_info(smu->adev->dev, "LedPin2 = 0x%x\n", pptable->LedPin2);
3436         dev_info(smu->adev->dev, "LedEnableMask = 0x%x\n", pptable->LedEnableMask);
3437         dev_info(smu->adev->dev, "LedPcie = 0x%x\n", pptable->LedPcie);
3438         dev_info(smu->adev->dev, "LedError = 0x%x\n", pptable->LedError);
3439         dev_info(smu->adev->dev, "LedSpare1[0] = 0x%x\n", pptable->LedSpare1[0]);
3440         dev_info(smu->adev->dev, "LedSpare1[1] = 0x%x\n", pptable->LedSpare1[1]);
3441
3442         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = 0x%x\n", pptable->PllGfxclkSpreadEnabled);
3443         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = 0x%x\n", pptable->PllGfxclkSpreadPercent);
3444         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = 0x%x\n",    pptable->PllGfxclkSpreadFreq);
3445
3446         dev_info(smu->adev->dev, "DfllGfxclkSpreadEnabled = 0x%x\n", pptable->DfllGfxclkSpreadEnabled);
3447         dev_info(smu->adev->dev, "DfllGfxclkSpreadPercent = 0x%x\n", pptable->DfllGfxclkSpreadPercent);
3448         dev_info(smu->adev->dev, "DfllGfxclkSpreadFreq = 0x%x\n",    pptable->DfllGfxclkSpreadFreq);
3449
3450         dev_info(smu->adev->dev, "UclkSpreadPadding = 0x%x\n", pptable->UclkSpreadPadding);
3451         dev_info(smu->adev->dev, "UclkSpreadFreq = 0x%x\n", pptable->UclkSpreadFreq);
3452
3453         dev_info(smu->adev->dev, "FclkSpreadEnabled = 0x%x\n", pptable->FclkSpreadEnabled);
3454         dev_info(smu->adev->dev, "FclkSpreadPercent = 0x%x\n", pptable->FclkSpreadPercent);
3455         dev_info(smu->adev->dev, "FclkSpreadFreq = 0x%x\n", pptable->FclkSpreadFreq);
3456
3457         dev_info(smu->adev->dev, "MemoryChannelEnabled = 0x%x\n", pptable->MemoryChannelEnabled);
3458         dev_info(smu->adev->dev, "DramBitWidth = 0x%x\n", pptable->DramBitWidth);
3459         dev_info(smu->adev->dev, "PaddingMem1[0] = 0x%x\n", pptable->PaddingMem1[0]);
3460         dev_info(smu->adev->dev, "PaddingMem1[1] = 0x%x\n", pptable->PaddingMem1[1]);
3461         dev_info(smu->adev->dev, "PaddingMem1[2] = 0x%x\n", pptable->PaddingMem1[2]);
3462
3463         dev_info(smu->adev->dev, "TotalBoardPower = 0x%x\n", pptable->TotalBoardPower);
3464         dev_info(smu->adev->dev, "BoardPowerPadding = 0x%x\n", pptable->BoardPowerPadding);
3465
3466         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
3467         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3468                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkSpeed[i]);
3469         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
3470         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3471                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiLinkWidth[i]);
3472         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
3473         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3474                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiFclkFreq[i]);
3475         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
3476         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
3477                 dev_info(smu->adev->dev, "  .[%d] = 0x%x\n", i, pptable->XgmiSocVoltage[i]);
3478
3479         dev_info(smu->adev->dev, "HsrEnabled = 0x%x\n", pptable->HsrEnabled);
3480         dev_info(smu->adev->dev, "VddqOffEnabled = 0x%x\n", pptable->VddqOffEnabled);
3481         dev_info(smu->adev->dev, "PaddingUmcFlags[0] = 0x%x\n", pptable->PaddingUmcFlags[0]);
3482         dev_info(smu->adev->dev, "PaddingUmcFlags[1] = 0x%x\n", pptable->PaddingUmcFlags[1]);
3483
3484         dev_info(smu->adev->dev, "BoardReserved[0] = 0x%x\n", pptable->BoardReserved[0]);
3485         dev_info(smu->adev->dev, "BoardReserved[1] = 0x%x\n", pptable->BoardReserved[1]);
3486         dev_info(smu->adev->dev, "BoardReserved[2] = 0x%x\n", pptable->BoardReserved[2]);
3487         dev_info(smu->adev->dev, "BoardReserved[3] = 0x%x\n", pptable->BoardReserved[3]);
3488         dev_info(smu->adev->dev, "BoardReserved[4] = 0x%x\n", pptable->BoardReserved[4]);
3489         dev_info(smu->adev->dev, "BoardReserved[5] = 0x%x\n", pptable->BoardReserved[5]);
3490         dev_info(smu->adev->dev, "BoardReserved[6] = 0x%x\n", pptable->BoardReserved[6]);
3491         dev_info(smu->adev->dev, "BoardReserved[7] = 0x%x\n", pptable->BoardReserved[7]);
3492         dev_info(smu->adev->dev, "BoardReserved[8] = 0x%x\n", pptable->BoardReserved[8]);
3493         dev_info(smu->adev->dev, "BoardReserved[9] = 0x%x\n", pptable->BoardReserved[9]);
3494         dev_info(smu->adev->dev, "BoardReserved[10] = 0x%x\n", pptable->BoardReserved[10]);
3495
3496         dev_info(smu->adev->dev, "MmHubPadding[0] = 0x%x\n", pptable->MmHubPadding[0]);
3497         dev_info(smu->adev->dev, "MmHubPadding[1] = 0x%x\n", pptable->MmHubPadding[1]);
3498         dev_info(smu->adev->dev, "MmHubPadding[2] = 0x%x\n", pptable->MmHubPadding[2]);
3499         dev_info(smu->adev->dev, "MmHubPadding[3] = 0x%x\n", pptable->MmHubPadding[3]);
3500         dev_info(smu->adev->dev, "MmHubPadding[4] = 0x%x\n", pptable->MmHubPadding[4]);
3501         dev_info(smu->adev->dev, "MmHubPadding[5] = 0x%x\n", pptable->MmHubPadding[5]);
3502         dev_info(smu->adev->dev, "MmHubPadding[6] = 0x%x\n", pptable->MmHubPadding[6]);
3503         dev_info(smu->adev->dev, "MmHubPadding[7] = 0x%x\n", pptable->MmHubPadding[7]);
3504 }
3505
3506 static int sienna_cichlid_i2c_xfer(struct i2c_adapter *i2c_adap,
3507                                    struct i2c_msg *msg, int num_msgs)
3508 {
3509         struct amdgpu_device *adev = to_amdgpu_device(i2c_adap);
3510         struct smu_table_context *smu_table = &adev->smu.smu_table;
3511         struct smu_table *table = &smu_table->driver_table;
3512         SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
3513         int i, j, r, c;
3514         u16 dir;
3515
3516         req = kzalloc(sizeof(*req), GFP_KERNEL);
3517         if (!req)
3518                 return -ENOMEM;
3519
3520         req->I2CcontrollerPort = 1;
3521         req->I2CSpeed = I2C_SPEED_FAST_400K;
3522         req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
3523         dir = msg[0].flags & I2C_M_RD;
3524
3525         for (c = i = 0; i < num_msgs; i++) {
3526                 for (j = 0; j < msg[i].len; j++, c++) {
3527                         SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
3528
3529                         if (!(msg[i].flags & I2C_M_RD)) {
3530                                 /* write */
3531                                 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
3532                                 cmd->ReadWriteData = msg[i].buf[j];
3533                         }
3534
3535                         if ((dir ^ msg[i].flags) & I2C_M_RD) {
3536                                 /* The direction changes.
3537                                  */
3538                                 dir = msg[i].flags & I2C_M_RD;
3539                                 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
3540                         }
3541
3542                         req->NumCmds++;
3543
3544                         /*
3545                          * Insert STOP if we are at the last byte of either last
3546                          * message for the transaction or the client explicitly
3547                          * requires a STOP at this particular message.
3548                          */
3549                         if ((j == msg[i].len - 1) &&
3550                             ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
3551                                 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
3552                                 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
3553                         }
3554                 }
3555         }
3556         mutex_lock(&adev->smu.mutex);
3557         r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
3558         mutex_unlock(&adev->smu.mutex);
3559         if (r)
3560                 goto fail;
3561
3562         for (c = i = 0; i < num_msgs; i++) {
3563                 if (!(msg[i].flags & I2C_M_RD)) {
3564                         c += msg[i].len;
3565                         continue;
3566                 }
3567                 for (j = 0; j < msg[i].len; j++, c++) {
3568                         SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
3569
3570                         msg[i].buf[j] = cmd->ReadWriteData;
3571                 }
3572         }
3573         r = num_msgs;
3574 fail:
3575         kfree(req);
3576         return r;
3577 }
3578
3579 static u32 sienna_cichlid_i2c_func(struct i2c_adapter *adap)
3580 {
3581         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3582 }
3583
3584
3585 static const struct i2c_algorithm sienna_cichlid_i2c_algo = {
3586         .master_xfer = sienna_cichlid_i2c_xfer,
3587         .functionality = sienna_cichlid_i2c_func,
3588 };
3589
3590 static const struct i2c_adapter_quirks sienna_cichlid_i2c_control_quirks = {
3591         .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
3592         .max_read_len  = MAX_SW_I2C_COMMANDS,
3593         .max_write_len = MAX_SW_I2C_COMMANDS,
3594         .max_comb_1st_msg_len = 2,
3595         .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
3596 };
3597
3598 static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
3599 {
3600         struct amdgpu_device *adev = to_amdgpu_device(control);
3601         int res;
3602
3603         control->owner = THIS_MODULE;
3604         control->class = I2C_CLASS_HWMON;
3605         control->dev.parent = &adev->pdev->dev;
3606         control->algo = &sienna_cichlid_i2c_algo;
3607         snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
3608         control->quirks = &sienna_cichlid_i2c_control_quirks;
3609
3610         res = i2c_add_adapter(control);
3611         if (res)
3612                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3613
3614         return res;
3615 }
3616
3617 static void sienna_cichlid_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
3618 {
3619         i2c_del_adapter(control);
3620 }
3621
3622 static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
3623                                               void **table)
3624 {
3625         struct smu_table_context *smu_table = &smu->smu_table;
3626         struct gpu_metrics_v1_3 *gpu_metrics =
3627                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3628         SmuMetricsExternal_t metrics_external;
3629         SmuMetrics_t *metrics =
3630                 &(metrics_external.SmuMetrics);
3631         SmuMetrics_V2_t *metrics_v2 =
3632                 &(metrics_external.SmuMetrics_V2);
3633         struct amdgpu_device *adev = smu->adev;
3634         bool use_metrics_v2 = ((adev->asic_type == CHIP_SIENNA_CICHLID) &&
3635                 (smu->smc_fw_version >= 0x3A4300)) ? true : false;
3636         uint16_t average_gfx_activity;
3637         int ret = 0;
3638
3639         mutex_lock(&smu->metrics_lock);
3640         ret = smu_cmn_get_metrics_table_locked(smu,
3641                                                &metrics_external,
3642                                                true);
3643         if (ret) {
3644                 mutex_unlock(&smu->metrics_lock);
3645                 return ret;
3646         }
3647
3648         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3649
3650         gpu_metrics->temperature_edge =
3651                 use_metrics_v2 ? metrics_v2->TemperatureEdge : metrics->TemperatureEdge;
3652         gpu_metrics->temperature_hotspot =
3653                 use_metrics_v2 ? metrics_v2->TemperatureHotspot : metrics->TemperatureHotspot;
3654         gpu_metrics->temperature_mem =
3655                 use_metrics_v2 ? metrics_v2->TemperatureMem : metrics->TemperatureMem;
3656         gpu_metrics->temperature_vrgfx =
3657                 use_metrics_v2 ? metrics_v2->TemperatureVrGfx : metrics->TemperatureVrGfx;
3658         gpu_metrics->temperature_vrsoc =
3659                 use_metrics_v2 ? metrics_v2->TemperatureVrSoc : metrics->TemperatureVrSoc;
3660         gpu_metrics->temperature_vrmem =
3661                 use_metrics_v2 ? metrics_v2->TemperatureVrMem0 : metrics->TemperatureVrMem0;
3662
3663         gpu_metrics->average_gfx_activity =
3664                 use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3665         gpu_metrics->average_umc_activity =
3666                 use_metrics_v2 ? metrics_v2->AverageUclkActivity : metrics->AverageUclkActivity;
3667         gpu_metrics->average_mm_activity =
3668                 use_metrics_v2 ? metrics_v2->VcnActivityPercentage : metrics->VcnActivityPercentage;
3669
3670         gpu_metrics->average_socket_power =
3671                 use_metrics_v2 ? metrics_v2->AverageSocketPower : metrics->AverageSocketPower;
3672         gpu_metrics->energy_accumulator =
3673                 use_metrics_v2 ? metrics_v2->EnergyAccumulator : metrics->EnergyAccumulator;
3674
3675         average_gfx_activity = use_metrics_v2 ? metrics_v2->AverageGfxActivity : metrics->AverageGfxActivity;
3676         if (average_gfx_activity <= SMU_11_0_7_GFX_BUSY_THRESHOLD)
3677                 gpu_metrics->average_gfxclk_frequency =
3678                         use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPostDs : metrics->AverageGfxclkFrequencyPostDs;
3679         else
3680                 gpu_metrics->average_gfxclk_frequency =
3681                         use_metrics_v2 ? metrics_v2->AverageGfxclkFrequencyPreDs : metrics->AverageGfxclkFrequencyPreDs;
3682         gpu_metrics->average_uclk_frequency =
3683                 use_metrics_v2 ? metrics_v2->AverageUclkFrequencyPostDs : metrics->AverageUclkFrequencyPostDs;
3684         gpu_metrics->average_vclk0_frequency =
3685                 use_metrics_v2 ? metrics_v2->AverageVclk0Frequency : metrics->AverageVclk0Frequency;
3686         gpu_metrics->average_dclk0_frequency =
3687                 use_metrics_v2 ? metrics_v2->AverageDclk0Frequency : metrics->AverageDclk0Frequency;
3688         gpu_metrics->average_vclk1_frequency =
3689                 use_metrics_v2 ? metrics_v2->AverageVclk1Frequency : metrics->AverageVclk1Frequency;
3690         gpu_metrics->average_dclk1_frequency =
3691                 use_metrics_v2 ? metrics_v2->AverageDclk1Frequency : metrics->AverageDclk1Frequency;
3692
3693         gpu_metrics->current_gfxclk =
3694                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_GFXCLK] : metrics->CurrClock[PPCLK_GFXCLK];
3695         gpu_metrics->current_socclk =
3696                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_SOCCLK] : metrics->CurrClock[PPCLK_SOCCLK];
3697         gpu_metrics->current_uclk =
3698                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK];
3699         gpu_metrics->current_vclk0 =
3700                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_0] : metrics->CurrClock[PPCLK_VCLK_0];
3701         gpu_metrics->current_dclk0 =
3702                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_0] : metrics->CurrClock[PPCLK_DCLK_0];
3703         gpu_metrics->current_vclk1 =
3704                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_VCLK_1] : metrics->CurrClock[PPCLK_VCLK_1];
3705         gpu_metrics->current_dclk1 =
3706                 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_DCLK_1] : metrics->CurrClock[PPCLK_DCLK_1];
3707
3708         gpu_metrics->throttle_status = sienna_cichlid_get_throttler_status_locked(smu);
3709         gpu_metrics->indep_throttle_status =
3710                         smu_cmn_get_indep_throttler_status(gpu_metrics->throttle_status,
3711                                                            sienna_cichlid_throttler_map);
3712
3713         gpu_metrics->current_fan_speed = use_metrics_v2 ? metrics_v2->CurrFanSpeed : metrics->CurrFanSpeed;
3714
3715         if (((adev->asic_type == CHIP_SIENNA_CICHLID) && smu->smc_fw_version > 0x003A1E00) ||
3716               ((adev->asic_type == CHIP_NAVY_FLOUNDER) && smu->smc_fw_version > 0x00410400)) {
3717                 gpu_metrics->pcie_link_width = use_metrics_v2 ? metrics_v2->PcieWidth : metrics->PcieWidth;
3718                 gpu_metrics->pcie_link_speed = link_speed[use_metrics_v2 ? metrics_v2->PcieRate : metrics->PcieRate];
3719         } else {
3720                 gpu_metrics->pcie_link_width =
3721                                 smu_v11_0_get_current_pcie_link_width(smu);
3722                 gpu_metrics->pcie_link_speed =
3723                                 smu_v11_0_get_current_pcie_link_speed(smu);
3724         }
3725
3726         mutex_unlock(&smu->metrics_lock);
3727
3728         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3729
3730         *table = (void *)gpu_metrics;
3731
3732         return sizeof(struct gpu_metrics_v1_3);
3733 }
3734
3735 static int sienna_cichlid_enable_mgpu_fan_boost(struct smu_context *smu)
3736 {
3737         struct smu_table_context *table_context = &smu->smu_table;
3738         PPTable_t *smc_pptable = table_context->driver_pptable;
3739
3740         /*
3741          * Skip the MGpuFanBoost setting for those ASICs
3742          * which do not support it
3743          */
3744         if (!smc_pptable->MGpuFanBoostLimitRpm)
3745                 return 0;
3746
3747         return smu_cmn_send_smc_msg_with_param(smu,
3748                                                SMU_MSG_SetMGpuFanBoostLimitRpm,
3749                                                0,
3750                                                NULL);
3751 }
3752
3753 static int sienna_cichlid_gpo_control(struct smu_context *smu,
3754                                       bool enablement)
3755 {
3756         uint32_t smu_version;
3757         int ret = 0;
3758
3759
3760         if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
3761                 ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
3762                 if (ret)
3763                         return ret;
3764
3765                 if (enablement) {
3766                         if (smu_version < 0x003a2500) {
3767                                 ret = smu_cmn_send_smc_msg_with_param(smu,
3768                                                                       SMU_MSG_SetGpoFeaturePMask,
3769                                                                       GFX_GPO_PACE_MASK | GFX_GPO_DEM_MASK,
3770                                                                       NULL);
3771                         } else {
3772                                 ret = smu_cmn_send_smc_msg_with_param(smu,
3773                                                                       SMU_MSG_DisallowGpo,
3774                                                                       0,
3775                                                                       NULL);
3776                         }
3777                 } else {
3778                         if (smu_version < 0x003a2500) {
3779                                 ret = smu_cmn_send_smc_msg_with_param(smu,
3780                                                                       SMU_MSG_SetGpoFeaturePMask,
3781                                                                       0,
3782                                                                       NULL);
3783                         } else {
3784                                 ret = smu_cmn_send_smc_msg_with_param(smu,
3785                                                                       SMU_MSG_DisallowGpo,
3786                                                                       1,
3787                                                                       NULL);
3788                         }
3789                 }
3790         }
3791
3792         return ret;
3793 }
3794
3795 static int sienna_cichlid_notify_2nd_usb20_port(struct smu_context *smu)
3796 {
3797         uint32_t smu_version;
3798         int ret = 0;
3799
3800         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
3801         if (ret)
3802                 return ret;
3803
3804         /*
3805          * Message SMU_MSG_Enable2ndUSB20Port is supported by 58.45
3806          * onwards PMFWs.
3807          */
3808         if (smu_version < 0x003A2D00)
3809                 return 0;
3810
3811         return smu_cmn_send_smc_msg_with_param(smu,
3812                                                SMU_MSG_Enable2ndUSB20Port,
3813                                                smu->smu_table.boot_values.firmware_caps & ATOM_FIRMWARE_CAP_ENABLE_2ND_USB20PORT ?
3814                                                1 : 0,
3815                                                NULL);
3816 }
3817
3818 static int sienna_cichlid_system_features_control(struct smu_context *smu,
3819                                                   bool en)
3820 {
3821         int ret = 0;
3822
3823         if (en) {
3824                 ret = sienna_cichlid_notify_2nd_usb20_port(smu);
3825                 if (ret)
3826                         return ret;
3827         }
3828
3829         return smu_v11_0_system_features_control(smu, en);
3830 }
3831
3832 static int sienna_cichlid_set_mp1_state(struct smu_context *smu,
3833                                         enum pp_mp1_state mp1_state)
3834 {
3835         int ret;
3836
3837         switch (mp1_state) {
3838         case PP_MP1_STATE_UNLOAD:
3839                 ret = smu_cmn_set_mp1_state(smu, mp1_state);
3840                 break;
3841         default:
3842                 /* Ignore others */
3843                 ret = 0;
3844         }
3845
3846         return ret;
3847 }
3848
3849 static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
3850         .get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
3851         .set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
3852         .dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
3853         .dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
3854         .i2c_init = sienna_cichlid_i2c_control_init,
3855         .i2c_fini = sienna_cichlid_i2c_control_fini,
3856         .print_clk_levels = sienna_cichlid_print_clk_levels,
3857         .force_clk_levels = sienna_cichlid_force_clk_levels,
3858         .populate_umd_state_clk = sienna_cichlid_populate_umd_state_clk,
3859         .pre_display_config_changed = sienna_cichlid_pre_display_config_changed,
3860         .display_config_changed = sienna_cichlid_display_config_changed,
3861         .notify_smc_display_config = sienna_cichlid_notify_smc_display_config,
3862         .is_dpm_running = sienna_cichlid_is_dpm_running,
3863         .get_fan_speed_percent = sienna_cichlid_get_fan_speed_percent,
3864         .get_power_profile_mode = sienna_cichlid_get_power_profile_mode,
3865         .set_power_profile_mode = sienna_cichlid_set_power_profile_mode,
3866         .set_watermarks_table = sienna_cichlid_set_watermarks_table,
3867         .read_sensor = sienna_cichlid_read_sensor,
3868         .get_uclk_dpm_states = sienna_cichlid_get_uclk_dpm_states,
3869         .set_performance_level = smu_v11_0_set_performance_level,
3870         .get_thermal_temperature_range = sienna_cichlid_get_thermal_temperature_range,
3871         .display_disable_memory_clock_switch = sienna_cichlid_display_disable_memory_clock_switch,
3872         .get_power_limit = sienna_cichlid_get_power_limit,
3873         .update_pcie_parameters = sienna_cichlid_update_pcie_parameters,
3874         .dump_pptable = sienna_cichlid_dump_pptable,
3875         .init_microcode = smu_v11_0_init_microcode,
3876         .load_microcode = smu_v11_0_load_microcode,
3877         .init_smc_tables = sienna_cichlid_init_smc_tables,
3878         .fini_smc_tables = smu_v11_0_fini_smc_tables,
3879         .init_power = smu_v11_0_init_power,
3880         .fini_power = smu_v11_0_fini_power,
3881         .check_fw_status = smu_v11_0_check_fw_status,
3882         .setup_pptable = sienna_cichlid_setup_pptable,
3883         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
3884         .check_fw_version = smu_v11_0_check_fw_version,
3885         .write_pptable = smu_cmn_write_pptable,
3886         .set_driver_table_location = smu_v11_0_set_driver_table_location,
3887         .set_tool_table_location = smu_v11_0_set_tool_table_location,
3888         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
3889         .system_features_control = sienna_cichlid_system_features_control,
3890         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
3891         .send_smc_msg = smu_cmn_send_smc_msg,
3892         .init_display_count = NULL,
3893         .set_allowed_mask = smu_v11_0_set_allowed_mask,
3894         .get_enabled_mask = smu_cmn_get_enabled_mask,
3895         .feature_is_enabled = smu_cmn_feature_is_enabled,
3896         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
3897         .notify_display_change = NULL,
3898         .set_power_limit = smu_v11_0_set_power_limit,
3899         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
3900         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
3901         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
3902         .set_min_dcef_deep_sleep = NULL,
3903         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
3904         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
3905         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
3906         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
3907         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
3908         .gfx_off_control = smu_v11_0_gfx_off_control,
3909         .register_irq_handler = smu_v11_0_register_irq_handler,
3910         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
3911         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
3912         .baco_is_support = smu_v11_0_baco_is_support,
3913         .baco_get_state = smu_v11_0_baco_get_state,
3914         .baco_set_state = smu_v11_0_baco_set_state,
3915         .baco_enter = sienna_cichlid_baco_enter,
3916         .baco_exit = sienna_cichlid_baco_exit,
3917         .mode1_reset_is_support = sienna_cichlid_is_mode1_reset_supported,
3918         .mode1_reset = smu_v11_0_mode1_reset,
3919         .get_dpm_ultimate_freq = sienna_cichlid_get_dpm_ultimate_freq,
3920         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
3921         .set_default_od_settings = sienna_cichlid_set_default_od_settings,
3922         .od_edit_dpm_table = sienna_cichlid_od_edit_dpm_table,
3923         .restore_user_od_settings = smu_v11_0_restore_user_od_settings,
3924         .run_btc = sienna_cichlid_run_btc,
3925         .set_power_source = smu_v11_0_set_power_source,
3926         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3927         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
3928         .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
3929         .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
3930         .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
3931         .deep_sleep_control = smu_v11_0_deep_sleep_control,
3932         .get_fan_parameters = sienna_cichlid_get_fan_parameters,
3933         .interrupt_work = smu_v11_0_interrupt_work,
3934         .gpo_control = sienna_cichlid_gpo_control,
3935         .set_mp1_state = sienna_cichlid_set_mp1_state,
3936 };
3937
3938 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
3939 {
3940         smu->ppt_funcs = &sienna_cichlid_ppt_funcs;
3941         smu->message_map = sienna_cichlid_message_map;
3942         smu->clock_map = sienna_cichlid_clk_map;
3943         smu->feature_map = sienna_cichlid_feature_mask_map;
3944         smu->table_map = sienna_cichlid_table_map;
3945         smu->pwr_src_map = sienna_cichlid_pwr_src_map;
3946         smu->workload_map = sienna_cichlid_workload_map;
3947 }