drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_smu.h"
  29 #include "atomfirmware.h"
  30 #include "amdgpu_atomfirmware.h"
  31 #include "amdgpu_atombios.h"
  32 #include "smu_v11_0.h"
  33 #include "smu11_driver_if_arcturus.h"
  34 #include "soc15_common.h"
  35 #include "atom.h"
  36 #include "power_state.h"
  37 #include "arcturus_ppt.h"
  38 #include "smu_v11_0_pptable.h"
  39 #include "arcturus_ppsmc.h"
  40 #include "nbio/nbio_7_4_offset.h"
  41 #include "nbio/nbio_7_4_sh_mask.h"
  42 #include "thm/thm_11_0_2_offset.h"
  43 #include "thm/thm_11_0_2_sh_mask.h"
  44 #include "amdgpu_xgmi.h"
  45 #include <linux/i2c.h>
  46 #include <linux/pci.h>
  47 #include "amdgpu_ras.h"
  48 #include "smu_cmn.h"
  49
  50 /*
  51  * DO NOT use these for err/warn/info/debug messages.
  52  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  53  * They are more MGPU friendly.
  54  */
  55 #undef pr_err
  56 #undef pr_warn
  57 #undef pr_info
  58 #undef pr_debug
  59
  60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  61
  62 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
  63         [smu_feature] = {1, (arcturus_feature)}
  64
  65 #define SMU_FEATURES_LOW_MASK        0x00000000FFFFFFFF
  66 #define SMU_FEATURES_LOW_SHIFT       0
  67 #define SMU_FEATURES_HIGH_MASK       0xFFFFFFFF00000000
  68 #define SMU_FEATURES_HIGH_SHIFT      32
  69
  70 #define SMC_DPM_FEATURE ( \
  71         FEATURE_DPM_PREFETCHER_MASK | \
  72         FEATURE_DPM_GFXCLK_MASK | \
  73         FEATURE_DPM_UCLK_MASK | \
  74         FEATURE_DPM_SOCCLK_MASK | \
  75         FEATURE_DPM_MP0CLK_MASK | \
  76         FEATURE_DPM_FCLK_MASK | \
  77         FEATURE_DPM_XGMI_MASK)
  78
  79 /* possible frequency drift (1Mhz) */
  80 #define EPSILON                         1
  81
  82 #define smnPCIE_ESM_CTRL                        0x111003D0
  83
  84 #define mmCG_FDO_CTRL0_ARCT                     0x8B
  85 #define mmCG_FDO_CTRL0_ARCT_BASE_IDX            0
  86
  87 #define mmCG_FDO_CTRL1_ARCT                     0x8C
  88 #define mmCG_FDO_CTRL1_ARCT_BASE_IDX            0
  89
  90 #define mmCG_FDO_CTRL2_ARCT                     0x8D
  91 #define mmCG_FDO_CTRL2_ARCT_BASE_IDX            0
  92
  93 #define mmCG_TACH_CTRL_ARCT                     0x8E
  94 #define mmCG_TACH_CTRL_ARCT_BASE_IDX            0
  95
  96 #define mmCG_TACH_STATUS_ARCT                   0x8F
  97 #define mmCG_TACH_STATUS_ARCT_BASE_IDX          0
  98
  99 #define mmCG_THERMAL_STATUS_ARCT                0x90
 100 #define mmCG_THERMAL_STATUS_ARCT_BASE_IDX       0
 101
 102 static const struct cmn2asic_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
 103         MSG_MAP(TestMessage,                         PPSMC_MSG_TestMessage,                     0),
 104         MSG_MAP(GetSmuVersion,                       PPSMC_MSG_GetSmuVersion,                   1),
 105         MSG_MAP(GetDriverIfVersion,                  PPSMC_MSG_GetDriverIfVersion,              1),
 106         MSG_MAP(SetAllowedFeaturesMaskLow,           PPSMC_MSG_SetAllowedFeaturesMaskLow,       0),
 107         MSG_MAP(SetAllowedFeaturesMaskHigh,          PPSMC_MSG_SetAllowedFeaturesMaskHigh,      0),
 108         MSG_MAP(EnableAllSmuFeatures,                PPSMC_MSG_EnableAllSmuFeatures,            0),
 109         MSG_MAP(DisableAllSmuFeatures,               PPSMC_MSG_DisableAllSmuFeatures,           0),
 110         MSG_MAP(EnableSmuFeaturesLow,                PPSMC_MSG_EnableSmuFeaturesLow,            1),
 111         MSG_MAP(EnableSmuFeaturesHigh,               PPSMC_MSG_EnableSmuFeaturesHigh,           1),
 112         MSG_MAP(DisableSmuFeaturesLow,               PPSMC_MSG_DisableSmuFeaturesLow,           0),
 113         MSG_MAP(DisableSmuFeaturesHigh,              PPSMC_MSG_DisableSmuFeaturesHigh,          0),
 114         MSG_MAP(GetEnabledSmuFeaturesLow,            PPSMC_MSG_GetEnabledSmuFeaturesLow,        0),
 115         MSG_MAP(GetEnabledSmuFeaturesHigh,           PPSMC_MSG_GetEnabledSmuFeaturesHigh,       0),
 116         MSG_MAP(SetDriverDramAddrHigh,               PPSMC_MSG_SetDriverDramAddrHigh,           1),
 117         MSG_MAP(SetDriverDramAddrLow,                PPSMC_MSG_SetDriverDramAddrLow,            1),
 118         MSG_MAP(SetToolsDramAddrHigh,                PPSMC_MSG_SetToolsDramAddrHigh,            0),
 119         MSG_MAP(SetToolsDramAddrLow,                 PPSMC_MSG_SetToolsDramAddrLow,             0),
 120         MSG_MAP(TransferTableSmu2Dram,               PPSMC_MSG_TransferTableSmu2Dram,           1),
 121         MSG_MAP(TransferTableDram2Smu,               PPSMC_MSG_TransferTableDram2Smu,           0),
 122         MSG_MAP(UseDefaultPPTable,                   PPSMC_MSG_UseDefaultPPTable,               0),
 123         MSG_MAP(UseBackupPPTable,                    PPSMC_MSG_UseBackupPPTable,                0),
 124         MSG_MAP(SetSystemVirtualDramAddrHigh,        PPSMC_MSG_SetSystemVirtualDramAddrHigh,    0),
 125         MSG_MAP(SetSystemVirtualDramAddrLow,         PPSMC_MSG_SetSystemVirtualDramAddrLow,     0),
 126         MSG_MAP(EnterBaco,                           PPSMC_MSG_EnterBaco,                       0),
 127         MSG_MAP(ExitBaco,                            PPSMC_MSG_ExitBaco,                        0),
 128         MSG_MAP(ArmD3,                               PPSMC_MSG_ArmD3,                           0),
 129         MSG_MAP(SetSoftMinByFreq,                    PPSMC_MSG_SetSoftMinByFreq,                0),
 130         MSG_MAP(SetSoftMaxByFreq,                    PPSMC_MSG_SetSoftMaxByFreq,                0),
 131         MSG_MAP(SetHardMinByFreq,                    PPSMC_MSG_SetHardMinByFreq,                0),
 132         MSG_MAP(SetHardMaxByFreq,                    PPSMC_MSG_SetHardMaxByFreq,                0),
 133         MSG_MAP(GetMinDpmFreq,                       PPSMC_MSG_GetMinDpmFreq,                   0),
 134         MSG_MAP(GetMaxDpmFreq,                       PPSMC_MSG_GetMaxDpmFreq,                   0),
 135         MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex,               1),
 136         MSG_MAP(SetWorkloadMask,                     PPSMC_MSG_SetWorkloadMask,                 1),
 137         MSG_MAP(SetDfSwitchType,                     PPSMC_MSG_SetDfSwitchType,                 0),
 138         MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm,                 0),
 139         MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive,        0),
 140         MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit,                     0),
 141         MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit,                     1),
 142         MSG_MAP(PowerUpVcn0,                         PPSMC_MSG_PowerUpVcn0,                     0),
 143         MSG_MAP(PowerDownVcn0,                       PPSMC_MSG_PowerDownVcn0,                   0),
 144         MSG_MAP(PowerUpVcn1,                         PPSMC_MSG_PowerUpVcn1,                     0),
 145         MSG_MAP(PowerDownVcn1,                       PPSMC_MSG_PowerDownVcn1,                   0),
 146         MSG_MAP(PrepareMp1ForUnload,                 PPSMC_MSG_PrepareMp1ForUnload,             0),
 147         MSG_MAP(PrepareMp1ForReset,                  PPSMC_MSG_PrepareMp1ForReset,              0),
 148         MSG_MAP(PrepareMp1ForShutdown,               PPSMC_MSG_PrepareMp1ForShutdown,           0),
 149         MSG_MAP(SoftReset,                           PPSMC_MSG_SoftReset,                       0),
 150         MSG_MAP(RunAfllBtc,                          PPSMC_MSG_RunAfllBtc,                      0),
 151         MSG_MAP(RunDcBtc,                            PPSMC_MSG_RunDcBtc,                        0),
 152         MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh,          0),
 153         MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow,           0),
 154         MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize,              0),
 155         MSG_MAP(GetDebugData,                        PPSMC_MSG_GetDebugData,                    0),
 156         MSG_MAP(WaflTest,                            PPSMC_MSG_WaflTest,                        0),
 157         MSG_MAP(SetXgmiMode,                         PPSMC_MSG_SetXgmiMode,                     0),
 158         MSG_MAP(SetMemoryChannelEnable,              PPSMC_MSG_SetMemoryChannelEnable,          0),
 159         MSG_MAP(DFCstateControl,                     PPSMC_MSG_DFCstateControl,                 0),
 160         MSG_MAP(GmiPwrDnControl,                     PPSMC_MSG_GmiPwrDnControl,                 0),
 161         MSG_MAP(ReadSerialNumTop32,                  PPSMC_MSG_ReadSerialNumTop32,              1),
 162         MSG_MAP(ReadSerialNumBottom32,               PPSMC_MSG_ReadSerialNumBottom32,           1),
 163         MSG_MAP(LightSBR,                            PPSMC_MSG_LightSBR,                        0),
 164 };
 165
 166 static const struct cmn2asic_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
 167         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 168         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 169         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 170         CLK_MAP(FCLK, PPCLK_FCLK),
 171         CLK_MAP(UCLK, PPCLK_UCLK),
 172         CLK_MAP(MCLK, PPCLK_UCLK),
 173         CLK_MAP(DCLK, PPCLK_DCLK),
 174         CLK_MAP(VCLK, PPCLK_VCLK),
 175 };
 176
 177 static const struct cmn2asic_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
 178         FEA_MAP(DPM_PREFETCHER),
 179         FEA_MAP(DPM_GFXCLK),
 180         FEA_MAP(DPM_UCLK),
 181         FEA_MAP(DPM_SOCCLK),
 182         FEA_MAP(DPM_FCLK),
 183         FEA_MAP(DPM_MP0CLK),
 184         FEA_MAP(DPM_XGMI),
 185         FEA_MAP(DS_GFXCLK),
 186         FEA_MAP(DS_SOCCLK),
 187         FEA_MAP(DS_LCLK),
 188         FEA_MAP(DS_FCLK),
 189         FEA_MAP(DS_UCLK),
 190         FEA_MAP(GFX_ULV),
 191         ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN_BIT),
 192         FEA_MAP(RSMU_SMN_CG),
 193         FEA_MAP(WAFL_CG),
 194         FEA_MAP(PPT),
 195         FEA_MAP(TDC),
 196         FEA_MAP(APCC_PLUS),
 197         FEA_MAP(VR0HOT),
 198         FEA_MAP(VR1HOT),
 199         FEA_MAP(FW_CTF),
 200         FEA_MAP(FAN_CONTROL),
 201         FEA_MAP(THERMAL),
 202         FEA_MAP(OUT_OF_BAND_MONITOR),
 203         FEA_MAP(TEMP_DEPENDENT_VMIN),
 204 };
 205
 206 static const struct cmn2asic_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
 207         TAB_MAP(PPTABLE),
 208         TAB_MAP(AVFS),
 209         TAB_MAP(AVFS_PSM_DEBUG),
 210         TAB_MAP(AVFS_FUSE_OVERRIDE),
 211         TAB_MAP(PMSTATUSLOG),
 212         TAB_MAP(SMU_METRICS),
 213         TAB_MAP(DRIVER_SMU_CONFIG),
 214         TAB_MAP(OVERDRIVE),
 215         TAB_MAP(I2C_COMMANDS),
 216         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 217 };
 218
 219 static const struct cmn2asic_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 220         PWR_MAP(AC),
 221         PWR_MAP(DC),
 222 };
 223
 224 static const struct cmn2asic_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 225         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 226         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 227         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 228         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 229         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 230 };
 231
 232 static const uint8_t arcturus_throttler_map[] = {
 233         [THROTTLER_TEMP_EDGE_BIT]       = (SMU_THROTTLER_TEMP_EDGE_BIT),
 234         [THROTTLER_TEMP_HOTSPOT_BIT]    = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
 235         [THROTTLER_TEMP_MEM_BIT]        = (SMU_THROTTLER_TEMP_MEM_BIT),
 236         [THROTTLER_TEMP_VR_GFX_BIT]     = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
 237         [THROTTLER_TEMP_VR_MEM_BIT]     = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
 238         [THROTTLER_TEMP_VR_SOC_BIT]     = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
 239         [THROTTLER_TDC_GFX_BIT]         = (SMU_THROTTLER_TDC_GFX_BIT),
 240         [THROTTLER_TDC_SOC_BIT]         = (SMU_THROTTLER_TDC_SOC_BIT),
 241         [THROTTLER_PPT0_BIT]            = (SMU_THROTTLER_PPT0_BIT),
 242         [THROTTLER_PPT1_BIT]            = (SMU_THROTTLER_PPT1_BIT),
 243         [THROTTLER_PPT2_BIT]            = (SMU_THROTTLER_PPT2_BIT),
 244         [THROTTLER_PPT3_BIT]            = (SMU_THROTTLER_PPT3_BIT),
 245         [THROTTLER_PPM_BIT]             = (SMU_THROTTLER_PPM_BIT),
 246         [THROTTLER_FIT_BIT]             = (SMU_THROTTLER_FIT_BIT),
 247         [THROTTLER_APCC_BIT]            = (SMU_THROTTLER_APCC_BIT),
 248         [THROTTLER_VRHOT0_BIT]          = (SMU_THROTTLER_VRHOT0_BIT),
 249         [THROTTLER_VRHOT1_BIT]          = (SMU_THROTTLER_VRHOT1_BIT),
 250 };
 251
 252 static int arcturus_tables_init(struct smu_context *smu)
 253 {
 254         struct smu_table_context *smu_table = &smu->smu_table;
 255         struct smu_table *tables = smu_table->tables;
 256
 257         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 258                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 259
 260         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 261                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 262
 263         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 264                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 265
 266         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 267                                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 268
 269         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 270                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 271                        AMDGPU_GEM_DOMAIN_VRAM);
 272
 273         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 274         if (!smu_table->metrics_table)
 275                 return -ENOMEM;
 276         smu_table->metrics_time = 0;
 277
 278         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 279         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 280         if (!smu_table->gpu_metrics_table) {
 281                 kfree(smu_table->metrics_table);
 282                 return -ENOMEM;
 283         }
 284
 285         return 0;
 286 }
 287
 288 static int arcturus_allocate_dpm_context(struct smu_context *smu)
 289 {
 290         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 291
 292         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 293                                        GFP_KERNEL);
 294         if (!smu_dpm->dpm_context)
 295                 return -ENOMEM;
 296         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 297
 298         smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 299                                        GFP_KERNEL);
 300         if (!smu_dpm->dpm_current_power_state)
 301                 return -ENOMEM;
 302
 303         smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 304                                        GFP_KERNEL);
 305         if (!smu_dpm->dpm_request_power_state)
 306                 return -ENOMEM;
 307
 308         return 0;
 309 }
 310
 311 static int arcturus_init_smc_tables(struct smu_context *smu)
 312 {
 313         int ret = 0;
 314
 315         ret = arcturus_tables_init(smu);
 316         if (ret)
 317                 return ret;
 318
 319         ret = arcturus_allocate_dpm_context(smu);
 320         if (ret)
 321                 return ret;
 322
 323         return smu_v11_0_init_smc_tables(smu);
 324 }
 325
 326 static int
 327 arcturus_get_allowed_feature_mask(struct smu_context *smu,
 328                                   uint32_t *feature_mask, uint32_t num)
 329 {
 330         if (num > 2)
 331                 return -EINVAL;
 332
 333         /* pptable will handle the features to enable */
 334         memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
 335
 336         return 0;
 337 }
 338
 339 static int arcturus_set_default_dpm_table(struct smu_context *smu)
 340 {
 341         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 342         PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
 343         struct smu_11_0_dpm_table *dpm_table = NULL;
 344         int ret = 0;
 345
 346         /* socclk dpm table setup */
 347         dpm_table = &dpm_context->dpm_tables.soc_table;
 348         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 349                 ret = smu_v11_0_set_single_dpm_table(smu,
 350                                                      SMU_SOCCLK,
 351                                                      dpm_table);
 352                 if (ret)
 353                         return ret;
 354                 dpm_table->is_fine_grained =
 355                         !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
 356         } else {
 357                 dpm_table->count = 1;
 358                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 359                 dpm_table->dpm_levels[0].enabled = true;
 360                 dpm_table->min = dpm_table->dpm_levels[0].value;
 361                 dpm_table->max = dpm_table->dpm_levels[0].value;
 362         }
 363
 364         /* gfxclk dpm table setup */
 365         dpm_table = &dpm_context->dpm_tables.gfx_table;
 366         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 367                 ret = smu_v11_0_set_single_dpm_table(smu,
 368                                                      SMU_GFXCLK,
 369                                                      dpm_table);
 370                 if (ret)
 371                         return ret;
 372                 dpm_table->is_fine_grained =
 373                         !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
 374         } else {
 375                 dpm_table->count = 1;
 376                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 377                 dpm_table->dpm_levels[0].enabled = true;
 378                 dpm_table->min = dpm_table->dpm_levels[0].value;
 379                 dpm_table->max = dpm_table->dpm_levels[0].value;
 380         }
 381
 382         /* memclk dpm table setup */
 383         dpm_table = &dpm_context->dpm_tables.uclk_table;
 384         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 385                 ret = smu_v11_0_set_single_dpm_table(smu,
 386                                                      SMU_UCLK,
 387                                                      dpm_table);
 388                 if (ret)
 389                         return ret;
 390                 dpm_table->is_fine_grained =
 391                         !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
 392         } else {
 393                 dpm_table->count = 1;
 394                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 395                 dpm_table->dpm_levels[0].enabled = true;
 396                 dpm_table->min = dpm_table->dpm_levels[0].value;
 397                 dpm_table->max = dpm_table->dpm_levels[0].value;
 398         }
 399
 400         /* fclk dpm table setup */
 401         dpm_table = &dpm_context->dpm_tables.fclk_table;
 402         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 403                 ret = smu_v11_0_set_single_dpm_table(smu,
 404                                                      SMU_FCLK,
 405                                                      dpm_table);
 406                 if (ret)
 407                         return ret;
 408                 dpm_table->is_fine_grained =
 409                         !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
 410         } else {
 411                 dpm_table->count = 1;
 412                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 413                 dpm_table->dpm_levels[0].enabled = true;
 414                 dpm_table->min = dpm_table->dpm_levels[0].value;
 415                 dpm_table->max = dpm_table->dpm_levels[0].value;
 416         }
 417
 418         return 0;
 419 }
 420
 421 static void arcturus_check_bxco_support(struct smu_context *smu)
 422 {
 423         struct smu_table_context *table_context = &smu->smu_table;
 424         struct smu_11_0_powerplay_table *powerplay_table =
 425                 table_context->power_play_table;
 426         struct smu_baco_context *smu_baco = &smu->smu_baco;
 427         struct amdgpu_device *adev = smu->adev;
 428         uint32_t val;
 429
 430         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 431             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) {
 432                 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
 433                 smu_baco->platform_support =
 434                         (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
 435                                                                         false;
 436         }
 437 }
 438
 439 static int arcturus_check_powerplay_table(struct smu_context *smu)
 440 {
 441         struct smu_table_context *table_context = &smu->smu_table;
 442         struct smu_11_0_powerplay_table *powerplay_table =
 443                 table_context->power_play_table;
 444
 445         arcturus_check_bxco_support(smu);
 446
 447         table_context->thermal_controller_type =
 448                 powerplay_table->thermal_controller_type;
 449
 450         return 0;
 451 }
 452
 453 static int arcturus_store_powerplay_table(struct smu_context *smu)
 454 {
 455         struct smu_table_context *table_context = &smu->smu_table;
 456         struct smu_11_0_powerplay_table *powerplay_table =
 457                 table_context->power_play_table;
 458
 459         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 460                sizeof(PPTable_t));
 461
 462         return 0;
 463 }
 464
 465 static int arcturus_append_powerplay_table(struct smu_context *smu)
 466 {
 467         struct smu_table_context *table_context = &smu->smu_table;
 468         PPTable_t *smc_pptable = table_context->driver_pptable;
 469         struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
 470         int index, ret;
 471
 472         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 473                                            smc_dpm_info);
 474
 475         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 476                                       (uint8_t **)&smc_dpm_table);
 477         if (ret)
 478                 return ret;
 479
 480         dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
 481                         smc_dpm_table->table_header.format_revision,
 482                         smc_dpm_table->table_header.content_revision);
 483
 484         if ((smc_dpm_table->table_header.format_revision == 4) &&
 485             (smc_dpm_table->table_header.content_revision == 6))
 486                 memcpy(&smc_pptable->MaxVoltageStepGfx,
 487                        &smc_dpm_table->maxvoltagestepgfx,
 488                        sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx));
 489
 490         return 0;
 491 }
 492
 493 static int arcturus_setup_pptable(struct smu_context *smu)
 494 {
 495         int ret = 0;
 496
 497         ret = smu_v11_0_setup_pptable(smu);
 498         if (ret)
 499                 return ret;
 500
 501         ret = arcturus_store_powerplay_table(smu);
 502         if (ret)
 503                 return ret;
 504
 505         ret = arcturus_append_powerplay_table(smu);
 506         if (ret)
 507                 return ret;
 508
 509         ret = arcturus_check_powerplay_table(smu);
 510         if (ret)
 511                 return ret;
 512
 513         return ret;
 514 }
 515
 516 static int arcturus_run_btc(struct smu_context *smu)
 517 {
 518         int ret = 0;
 519
 520         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL);
 521         if (ret) {
 522                 dev_err(smu->adev->dev, "RunAfllBtc failed!\n");
 523                 return ret;
 524         }
 525
 526         return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
 527 }
 528
 529 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
 530 {
 531         struct smu_11_0_dpm_context *dpm_context =
 532                                 smu->smu_dpm.dpm_context;
 533         struct smu_11_0_dpm_table *gfx_table =
 534                                 &dpm_context->dpm_tables.gfx_table;
 535         struct smu_11_0_dpm_table *mem_table =
 536                                 &dpm_context->dpm_tables.uclk_table;
 537         struct smu_11_0_dpm_table *soc_table =
 538                                 &dpm_context->dpm_tables.soc_table;
 539         struct smu_umd_pstate_table *pstate_table =
 540                                 &smu->pstate_table;
 541
 542         pstate_table->gfxclk_pstate.min = gfx_table->min;
 543         pstate_table->gfxclk_pstate.peak = gfx_table->max;
 544
 545         pstate_table->uclk_pstate.min = mem_table->min;
 546         pstate_table->uclk_pstate.peak = mem_table->max;
 547
 548         pstate_table->socclk_pstate.min = soc_table->min;
 549         pstate_table->socclk_pstate.peak = soc_table->max;
 550
 551         if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
 552             mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
 553             soc_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
 554                 pstate_table->gfxclk_pstate.standard =
 555                         gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
 556                 pstate_table->uclk_pstate.standard =
 557                         mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
 558                 pstate_table->socclk_pstate.standard =
 559                         soc_table->dpm_levels[ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL].value;
 560         } else {
 561                 pstate_table->gfxclk_pstate.standard =
 562                         pstate_table->gfxclk_pstate.min;
 563                 pstate_table->uclk_pstate.standard =
 564                         pstate_table->uclk_pstate.min;
 565                 pstate_table->socclk_pstate.standard =
 566                         pstate_table->socclk_pstate.min;
 567         }
 568
 569         return 0;
 570 }
 571
 572 static int arcturus_get_clk_table(struct smu_context *smu,
 573                         struct pp_clock_levels_with_latency *clocks,
 574                         struct smu_11_0_dpm_table *dpm_table)
 575 {
 576         int i, count;
 577
 578         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 579         clocks->num_levels = count;
 580
 581         for (i = 0; i < count; i++) {
 582                 clocks->data[i].clocks_in_khz =
 583                         dpm_table->dpm_levels[i].value * 1000;
 584                 clocks->data[i].latency_in_us = 0;
 585         }
 586
 587         return 0;
 588 }
 589
 590 static int arcturus_freqs_in_same_level(int32_t frequency1,
 591                                         int32_t frequency2)
 592 {
 593         return (abs(frequency1 - frequency2) <= EPSILON);
 594 }
 595
 596 static int arcturus_get_smu_metrics_data(struct smu_context *smu,
 597                                          MetricsMember_t member,
 598                                          uint32_t *value)
 599 {
 600         struct smu_table_context *smu_table= &smu->smu_table;
 601         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 602         int ret = 0;
 603
 604         mutex_lock(&smu->metrics_lock);
 605
 606         ret = smu_cmn_get_metrics_table_locked(smu,
 607                                                NULL,
 608                                                false);
 609         if (ret) {
 610                 mutex_unlock(&smu->metrics_lock);
 611                 return ret;
 612         }
 613
 614         switch (member) {
 615         case METRICS_CURR_GFXCLK:
 616                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 617                 break;
 618         case METRICS_CURR_SOCCLK:
 619                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 620                 break;
 621         case METRICS_CURR_UCLK:
 622                 *value = metrics->CurrClock[PPCLK_UCLK];
 623                 break;
 624         case METRICS_CURR_VCLK:
 625                 *value = metrics->CurrClock[PPCLK_VCLK];
 626                 break;
 627         case METRICS_CURR_DCLK:
 628                 *value = metrics->CurrClock[PPCLK_DCLK];
 629                 break;
 630         case METRICS_CURR_FCLK:
 631                 *value = metrics->CurrClock[PPCLK_FCLK];
 632                 break;
 633         case METRICS_AVERAGE_GFXCLK:
 634                 *value = metrics->AverageGfxclkFrequency;
 635                 break;
 636         case METRICS_AVERAGE_SOCCLK:
 637                 *value = metrics->AverageSocclkFrequency;
 638                 break;
 639         case METRICS_AVERAGE_UCLK:
 640                 *value = metrics->AverageUclkFrequency;
 641                 break;
 642         case METRICS_AVERAGE_VCLK:
 643                 *value = metrics->AverageVclkFrequency;
 644                 break;
 645         case METRICS_AVERAGE_DCLK:
 646                 *value = metrics->AverageDclkFrequency;
 647                 break;
 648         case METRICS_AVERAGE_GFXACTIVITY:
 649                 *value = metrics->AverageGfxActivity;
 650                 break;
 651         case METRICS_AVERAGE_MEMACTIVITY:
 652                 *value = metrics->AverageUclkActivity;
 653                 break;
 654         case METRICS_AVERAGE_VCNACTIVITY:
 655                 *value = metrics->VcnActivityPercentage;
 656                 break;
 657         case METRICS_AVERAGE_SOCKETPOWER:
 658                 *value = metrics->AverageSocketPower << 8;
 659                 break;
 660         case METRICS_TEMPERATURE_EDGE:
 661                 *value = metrics->TemperatureEdge *
 662                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 663                 break;
 664         case METRICS_TEMPERATURE_HOTSPOT:
 665                 *value = metrics->TemperatureHotspot *
 666                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 667                 break;
 668         case METRICS_TEMPERATURE_MEM:
 669                 *value = metrics->TemperatureHBM *
 670                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 671                 break;
 672         case METRICS_TEMPERATURE_VRGFX:
 673                 *value = metrics->TemperatureVrGfx *
 674                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 675                 break;
 676         case METRICS_TEMPERATURE_VRSOC:
 677                 *value = metrics->TemperatureVrSoc *
 678                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 679                 break;
 680         case METRICS_TEMPERATURE_VRMEM:
 681                 *value = metrics->TemperatureVrMem *
 682                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 683                 break;
 684         case METRICS_THROTTLER_STATUS:
 685                 *value = metrics->ThrottlerStatus;
 686                 break;
 687         case METRICS_CURR_FANSPEED:
 688                 *value = metrics->CurrFanSpeed;
 689                 break;
 690         default:
 691                 *value = UINT_MAX;
 692                 break;
 693         }
 694
 695         mutex_unlock(&smu->metrics_lock);
 696
 697         return ret;
 698 }
 699
 700 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
 701                                        enum smu_clk_type clk_type,
 702                                        uint32_t *value)
 703 {
 704         MetricsMember_t member_type;
 705         int clk_id = 0;
 706
 707         if (!value)
 708                 return -EINVAL;
 709
 710         clk_id = smu_cmn_to_asic_specific_index(smu,
 711                                                 CMN2ASIC_MAPPING_CLK,
 712                                                 clk_type);
 713         if (clk_id < 0)
 714                 return -EINVAL;
 715
 716         switch (clk_id) {
 717         case PPCLK_GFXCLK:
 718                 /*
 719                  * CurrClock[clk_id] can provide accurate
 720                  *   output only when the dpm feature is enabled.
 721                  * We can use Average_* for dpm disabled case.
 722                  *   But this is available for gfxclk/uclk/socclk/vclk/dclk.
 723                  */
 724                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
 725                         member_type = METRICS_CURR_GFXCLK;
 726                 else
 727                         member_type = METRICS_AVERAGE_GFXCLK;
 728                 break;
 729         case PPCLK_UCLK:
 730                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
 731                         member_type = METRICS_CURR_UCLK;
 732                 else
 733                         member_type = METRICS_AVERAGE_UCLK;
 734                 break;
 735         case PPCLK_SOCCLK:
 736                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
 737                         member_type = METRICS_CURR_SOCCLK;
 738                 else
 739                         member_type = METRICS_AVERAGE_SOCCLK;
 740                 break;
 741         case PPCLK_VCLK:
 742                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT))
 743                         member_type = METRICS_CURR_VCLK;
 744                 else
 745                         member_type = METRICS_AVERAGE_VCLK;
 746                 break;
 747         case PPCLK_DCLK:
 748                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT))
 749                         member_type = METRICS_CURR_DCLK;
 750                 else
 751                         member_type = METRICS_AVERAGE_DCLK;
 752                 break;
 753         case PPCLK_FCLK:
 754                 member_type = METRICS_CURR_FCLK;
 755                 break;
 756         default:
 757                 return -EINVAL;
 758         }
 759
 760         return arcturus_get_smu_metrics_data(smu,
 761                                              member_type,
 762                                              value);
 763 }
 764
 765 static int arcturus_print_clk_levels(struct smu_context *smu,
 766                         enum smu_clk_type type, char *buf)
 767 {
 768         int i, now, size = 0;
 769         int ret = 0;
 770         struct pp_clock_levels_with_latency clocks;
 771         struct smu_11_0_dpm_table *single_dpm_table;
 772         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 773         struct smu_11_0_dpm_context *dpm_context = NULL;
 774         uint32_t gen_speed, lane_width;
 775
 776         if (amdgpu_ras_intr_triggered())
 777                 return sysfs_emit(buf, "unavailable\n");
 778
 779         dpm_context = smu_dpm->dpm_context;
 780
 781         switch (type) {
 782         case SMU_SCLK:
 783                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now);
 784                 if (ret) {
 785                         dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!");
 786                         return ret;
 787                 }
 788
 789                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 790                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 791                 if (ret) {
 792                         dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
 793                         return ret;
 794                 }
 795
 796                 /*
 797                  * For DPM disabled case, there will be only one clock level.
 798                  * And it's safe to assume that is always the current clock.
 799                  */
 800                 for (i = 0; i < clocks.num_levels; i++)
 801                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i,
 802                                         clocks.data[i].clocks_in_khz / 1000,
 803                                         (clocks.num_levels == 1) ? "*" :
 804                                         (arcturus_freqs_in_same_level(
 805                                         clocks.data[i].clocks_in_khz / 1000,
 806                                         now) ? "*" : ""));
 807                 break;
 808
 809         case SMU_MCLK:
 810                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, &now);
 811                 if (ret) {
 812                         dev_err(smu->adev->dev, "Attempt to get current mclk Failed!");
 813                         return ret;
 814                 }
 815
 816                 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
 817                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 818                 if (ret) {
 819                         dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
 820                         return ret;
 821                 }
 822
 823                 for (i = 0; i < clocks.num_levels; i++)
 824                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 825                                 i, clocks.data[i].clocks_in_khz / 1000,
 826                                 (clocks.num_levels == 1) ? "*" :
 827                                 (arcturus_freqs_in_same_level(
 828                                 clocks.data[i].clocks_in_khz / 1000,
 829                                 now) ? "*" : ""));
 830                 break;
 831
 832         case SMU_SOCCLK:
 833                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now);
 834                 if (ret) {
 835                         dev_err(smu->adev->dev, "Attempt to get current socclk Failed!");
 836                         return ret;
 837                 }
 838
 839                 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
 840                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 841                 if (ret) {
 842                         dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
 843                         return ret;
 844                 }
 845
 846                 for (i = 0; i < clocks.num_levels; i++)
 847                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 848                                 i, clocks.data[i].clocks_in_khz / 1000,
 849                                 (clocks.num_levels == 1) ? "*" :
 850                                 (arcturus_freqs_in_same_level(
 851                                 clocks.data[i].clocks_in_khz / 1000,
 852                                 now) ? "*" : ""));
 853                 break;
 854
 855         case SMU_FCLK:
 856                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_FCLK, &now);
 857                 if (ret) {
 858                         dev_err(smu->adev->dev, "Attempt to get current fclk Failed!");
 859                         return ret;
 860                 }
 861
 862                 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
 863                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 864                 if (ret) {
 865                         dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
 866                         return ret;
 867                 }
 868
 869                 for (i = 0; i < single_dpm_table->count; i++)
 870                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 871                                 i, single_dpm_table->dpm_levels[i].value,
 872                                 (clocks.num_levels == 1) ? "*" :
 873                                 (arcturus_freqs_in_same_level(
 874                                 clocks.data[i].clocks_in_khz / 1000,
 875                                 now) ? "*" : ""));
 876                 break;
 877
 878         case SMU_VCLK:
 879                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_VCLK, &now);
 880                 if (ret) {
 881                         dev_err(smu->adev->dev, "Attempt to get current vclk Failed!");
 882                         return ret;
 883                 }
 884
 885                 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
 886                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 887                 if (ret) {
 888                         dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!");
 889                         return ret;
 890                 }
 891
 892                 for (i = 0; i < single_dpm_table->count; i++)
 893                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 894                                 i, single_dpm_table->dpm_levels[i].value,
 895                                 (clocks.num_levels == 1) ? "*" :
 896                                 (arcturus_freqs_in_same_level(
 897                                 clocks.data[i].clocks_in_khz / 1000,
 898                                 now) ? "*" : ""));
 899                 break;
 900
 901         case SMU_DCLK:
 902                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_DCLK, &now);
 903                 if (ret) {
 904                         dev_err(smu->adev->dev, "Attempt to get current dclk Failed!");
 905                         return ret;
 906                 }
 907
 908                 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
 909                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 910                 if (ret) {
 911                         dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!");
 912                         return ret;
 913                 }
 914
 915                 for (i = 0; i < single_dpm_table->count; i++)
 916                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
 917                                 i, single_dpm_table->dpm_levels[i].value,
 918                                 (clocks.num_levels == 1) ? "*" :
 919                                 (arcturus_freqs_in_same_level(
 920                                 clocks.data[i].clocks_in_khz / 1000,
 921                                 now) ? "*" : ""));
 922                 break;
 923
 924         case SMU_PCIE:
 925                 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
 926                 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
 927                 size += sysfs_emit_at(buf, size, "0: %s %s %dMhz *\n",
 928                                 (gen_speed == 0) ? "2.5GT/s," :
 929                                 (gen_speed == 1) ? "5.0GT/s," :
 930                                 (gen_speed == 2) ? "8.0GT/s," :
 931                                 (gen_speed == 3) ? "16.0GT/s," : "",
 932                                 (lane_width == 1) ? "x1" :
 933                                 (lane_width == 2) ? "x2" :
 934                                 (lane_width == 3) ? "x4" :
 935                                 (lane_width == 4) ? "x8" :
 936                                 (lane_width == 5) ? "x12" :
 937                                 (lane_width == 6) ? "x16" : "",
 938                                 smu->smu_table.boot_values.lclk / 100);
 939                 break;
 940
 941         default:
 942                 break;
 943         }
 944
 945         return size;
 946 }
 947
 948 static int arcturus_upload_dpm_level(struct smu_context *smu,
 949                                      bool max,
 950                                      uint32_t feature_mask,
 951                                      uint32_t level)
 952 {
 953         struct smu_11_0_dpm_context *dpm_context =
 954                         smu->smu_dpm.dpm_context;
 955         uint32_t freq;
 956         int ret = 0;
 957
 958         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
 959             (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
 960                 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
 961                 ret = smu_cmn_send_smc_msg_with_param(smu,
 962                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 963                         (PPCLK_GFXCLK << 16) | (freq & 0xffff),
 964                         NULL);
 965                 if (ret) {
 966                         dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
 967                                                 max ? "max" : "min");
 968                         return ret;
 969                 }
 970         }
 971
 972         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 973             (feature_mask & FEATURE_DPM_UCLK_MASK)) {
 974                 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
 975                 ret = smu_cmn_send_smc_msg_with_param(smu,
 976                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 977                         (PPCLK_UCLK << 16) | (freq & 0xffff),
 978                         NULL);
 979                 if (ret) {
 980                         dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
 981                                                 max ? "max" : "min");
 982                         return ret;
 983                 }
 984         }
 985
 986         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
 987             (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
 988                 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
 989                 ret = smu_cmn_send_smc_msg_with_param(smu,
 990                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 991                         (PPCLK_SOCCLK << 16) | (freq & 0xffff),
 992                         NULL);
 993                 if (ret) {
 994                         dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
 995                                                 max ? "max" : "min");
 996                         return ret;
 997                 }
 998         }
 999
1000         return ret;
1001 }
1002
1003 static int arcturus_force_clk_levels(struct smu_context *smu,
1004                         enum smu_clk_type type, uint32_t mask)
1005 {
1006         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1007         struct smu_11_0_dpm_table *single_dpm_table = NULL;
1008         uint32_t soft_min_level, soft_max_level;
1009         uint32_t smu_version;
1010         int ret = 0;
1011
1012         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1013         if (ret) {
1014                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
1015                 return ret;
1016         }
1017
1018         if ((smu_version >= 0x361200) &&
1019             (smu_version <= 0x361a00)) {
1020                 dev_err(smu->adev->dev, "Forcing clock level is not supported with "
1021                        "54.18 - 54.26(included) SMU firmwares\n");
1022                 return -EOPNOTSUPP;
1023         }
1024
1025         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1026         soft_max_level = mask ? (fls(mask) - 1) : 0;
1027
1028         switch (type) {
1029         case SMU_SCLK:
1030                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1031                 if (soft_max_level >= single_dpm_table->count) {
1032                         dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
1033                                         soft_max_level, single_dpm_table->count - 1);
1034                         ret = -EINVAL;
1035                         break;
1036                 }
1037
1038                 ret = arcturus_upload_dpm_level(smu,
1039                                                 false,
1040                                                 FEATURE_DPM_GFXCLK_MASK,
1041                                                 soft_min_level);
1042                 if (ret) {
1043                         dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
1044                         break;
1045                 }
1046
1047                 ret = arcturus_upload_dpm_level(smu,
1048                                                 true,
1049                                                 FEATURE_DPM_GFXCLK_MASK,
1050                                                 soft_max_level);
1051                 if (ret)
1052                         dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
1053
1054                 break;
1055
1056         case SMU_MCLK:
1057         case SMU_SOCCLK:
1058         case SMU_FCLK:
1059                 /*
1060                  * Should not arrive here since Arcturus does not
1061                  * support mclk/socclk/fclk softmin/softmax settings
1062                  */
1063                 ret = -EINVAL;
1064                 break;
1065
1066         default:
1067                 break;
1068         }
1069
1070         return ret;
1071 }
1072
1073 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
1074                                                 struct smu_temperature_range *range)
1075 {
1076         struct smu_table_context *table_context = &smu->smu_table;
1077         struct smu_11_0_powerplay_table *powerplay_table =
1078                                 table_context->power_play_table;
1079         PPTable_t *pptable = smu->smu_table.driver_pptable;
1080
1081         if (!range)
1082                 return -EINVAL;
1083
1084         memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1085
1086         range->max = pptable->TedgeLimit *
1087                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1088         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
1089                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1090         range->hotspot_crit_max = pptable->ThotspotLimit *
1091                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1092         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1093                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1094         range->mem_crit_max = pptable->TmemLimit *
1095                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1096         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
1097                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1098         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1099
1100         return 0;
1101 }
1102
1103 static int arcturus_read_sensor(struct smu_context *smu,
1104                                 enum amd_pp_sensors sensor,
1105                                 void *data, uint32_t *size)
1106 {
1107         struct smu_table_context *table_context = &smu->smu_table;
1108         PPTable_t *pptable = table_context->driver_pptable;
1109         int ret = 0;
1110
1111         if (amdgpu_ras_intr_triggered())
1112                 return 0;
1113
1114         if (!data || !size)
1115                 return -EINVAL;
1116
1117         mutex_lock(&smu->sensor_lock);
1118         switch (sensor) {
1119         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1120                 *(uint32_t *)data = pptable->FanMaximumRpm;
1121                 *size = 4;
1122                 break;
1123         case AMDGPU_PP_SENSOR_MEM_LOAD:
1124                 ret = arcturus_get_smu_metrics_data(smu,
1125                                                     METRICS_AVERAGE_MEMACTIVITY,
1126                                                     (uint32_t *)data);
1127                 *size = 4;
1128                 break;
1129         case AMDGPU_PP_SENSOR_GPU_LOAD:
1130                 ret = arcturus_get_smu_metrics_data(smu,
1131                                                     METRICS_AVERAGE_GFXACTIVITY,
1132                                                     (uint32_t *)data);
1133                 *size = 4;
1134                 break;
1135         case AMDGPU_PP_SENSOR_GPU_POWER:
1136                 ret = arcturus_get_smu_metrics_data(smu,
1137                                                     METRICS_AVERAGE_SOCKETPOWER,
1138                                                     (uint32_t *)data);
1139                 *size = 4;
1140                 break;
1141         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1142                 ret = arcturus_get_smu_metrics_data(smu,
1143                                                     METRICS_TEMPERATURE_HOTSPOT,
1144                                                     (uint32_t *)data);
1145                 *size = 4;
1146                 break;
1147         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1148                 ret = arcturus_get_smu_metrics_data(smu,
1149                                                     METRICS_TEMPERATURE_EDGE,
1150                                                     (uint32_t *)data);
1151                 *size = 4;
1152                 break;
1153         case AMDGPU_PP_SENSOR_MEM_TEMP:
1154                 ret = arcturus_get_smu_metrics_data(smu,
1155                                                     METRICS_TEMPERATURE_MEM,
1156                                                     (uint32_t *)data);
1157                 *size = 4;
1158                 break;
1159         case AMDGPU_PP_SENSOR_GFX_MCLK:
1160                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1161                 /* the output clock frequency in 10K unit */
1162                 *(uint32_t *)data *= 100;
1163                 *size = 4;
1164                 break;
1165         case AMDGPU_PP_SENSOR_GFX_SCLK:
1166                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1167                 *(uint32_t *)data *= 100;
1168                 *size = 4;
1169                 break;
1170         case AMDGPU_PP_SENSOR_VDDGFX:
1171                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1172                 *size = 4;
1173                 break;
1174         default:
1175                 ret = -EOPNOTSUPP;
1176                 break;
1177         }
1178         mutex_unlock(&smu->sensor_lock);
1179
1180         return ret;
1181 }
1182
1183 static int arcturus_set_fan_static_mode(struct smu_context *smu,
1184                                         uint32_t mode)
1185 {
1186         struct amdgpu_device *adev = smu->adev;
1187
1188         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT,
1189                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),
1190                                    CG_FDO_CTRL2, TMIN, 0));
1191         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT,
1192                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL2_ARCT),
1193                                    CG_FDO_CTRL2, FDO_PWM_MODE, mode));
1194
1195         return 0;
1196 }
1197
1198 static int arcturus_get_fan_speed_rpm(struct smu_context *smu,
1199                                       uint32_t *speed)
1200 {
1201         struct amdgpu_device *adev = smu->adev;
1202         uint32_t crystal_clock_freq = 2500;
1203         uint32_t tach_status;
1204         uint64_t tmp64;
1205         int ret = 0;
1206
1207         if (!speed)
1208                 return -EINVAL;
1209
1210         switch (smu_v11_0_get_fan_control_mode(smu)) {
1211         case AMD_FAN_CTRL_AUTO:
1212                 ret = arcturus_get_smu_metrics_data(smu,
1213                                                     METRICS_CURR_FANSPEED,
1214                                                     speed);
1215                 break;
1216         default:
1217                 /*
1218                  * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1219                  * detected via register retrieving. To workaround this, we will
1220                  * report the fan speed as 0 RPM if user just requested such.
1221                  */
1222                 if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_RPM)
1223                      && !smu->user_dpm_profile.fan_speed_rpm) {
1224                         *speed = 0;
1225                         return 0;
1226                 }
1227
1228                 tmp64 = (uint64_t)crystal_clock_freq * 60 * 10000;
1229                 tach_status = RREG32_SOC15(THM, 0, mmCG_TACH_STATUS_ARCT);
1230                 if (tach_status) {
1231                         do_div(tmp64, tach_status);
1232                         *speed = (uint32_t)tmp64;
1233                 } else {
1234                         *speed = 0;
1235                 }
1236
1237                 break;
1238         }
1239
1240         return ret;
1241 }
1242
1243 static int arcturus_set_fan_speed_pwm(struct smu_context *smu,
1244                                       uint32_t speed)
1245 {
1246         struct amdgpu_device *adev = smu->adev;
1247         uint32_t duty100, duty;
1248         uint64_t tmp64;
1249
1250         speed = MIN(speed, 255);
1251
1252         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT),
1253                                 CG_FDO_CTRL1, FMAX_DUTY100);
1254         if (!duty100)
1255                 return -EINVAL;
1256
1257         tmp64 = (uint64_t)speed * duty100;
1258         do_div(tmp64, 255);
1259         duty = (uint32_t)tmp64;
1260
1261         WREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT,
1262                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL0_ARCT),
1263                                    CG_FDO_CTRL0, FDO_STATIC_DUTY, duty));
1264
1265         return arcturus_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC);
1266 }
1267
1268 static int arcturus_set_fan_speed_rpm(struct smu_context *smu,
1269                                       uint32_t speed)
1270 {
1271         struct amdgpu_device *adev = smu->adev;
1272         /*
1273          * crystal_clock_freq used for fan speed rpm calculation is
1274          * always 25Mhz. So, hardcode it as 2500(in 10K unit).
1275          */
1276         uint32_t crystal_clock_freq = 2500;
1277         uint32_t tach_period;
1278
1279         tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
1280         WREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT,
1281                      REG_SET_FIELD(RREG32_SOC15(THM, 0, mmCG_TACH_CTRL_ARCT),
1282                                    CG_TACH_CTRL, TARGET_PERIOD,
1283                                    tach_period));
1284
1285         return arcturus_set_fan_static_mode(smu, FDO_PWM_MODE_STATIC_RPM);
1286 }
1287
1288 static int arcturus_get_fan_speed_pwm(struct smu_context *smu,
1289                                       uint32_t *speed)
1290 {
1291         struct amdgpu_device *adev = smu->adev;
1292         uint32_t duty100, duty;
1293         uint64_t tmp64;
1294
1295         /*
1296          * For pre Sienna Cichlid ASICs, the 0 RPM may be not correctly
1297          * detected via register retrieving. To workaround this, we will
1298          * report the fan speed as 0 PWM if user just requested such.
1299          */
1300         if ((smu->user_dpm_profile.flags & SMU_CUSTOM_FAN_SPEED_PWM)
1301              && !smu->user_dpm_profile.fan_speed_pwm) {
1302                 *speed = 0;
1303                 return 0;
1304         }
1305
1306         duty100 = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_FDO_CTRL1_ARCT),
1307                                 CG_FDO_CTRL1, FMAX_DUTY100);
1308         duty = REG_GET_FIELD(RREG32_SOC15(THM, 0, mmCG_THERMAL_STATUS_ARCT),
1309                                 CG_THERMAL_STATUS, FDO_PWM_DUTY);
1310
1311         if (duty100) {
1312                 tmp64 = (uint64_t)duty * 255;
1313                 do_div(tmp64, duty100);
1314                 *speed = MIN((uint32_t)tmp64, 255);
1315         } else {
1316                 *speed = 0;
1317         }
1318
1319         return 0;
1320 }
1321
1322 static int arcturus_get_fan_parameters(struct smu_context *smu)
1323 {
1324         PPTable_t *pptable = smu->smu_table.driver_pptable;
1325
1326         smu->fan_max_rpm = pptable->FanMaximumRpm;
1327
1328         return 0;
1329 }
1330
1331 static int arcturus_get_power_limit(struct smu_context *smu,
1332                                     uint32_t *current_power_limit,
1333                                     uint32_t *default_power_limit,
1334                                     uint32_t *max_power_limit)
1335 {
1336         struct smu_11_0_powerplay_table *powerplay_table =
1337                 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
1338         PPTable_t *pptable = smu->smu_table.driver_pptable;
1339         uint32_t power_limit, od_percent;
1340
1341         if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1342                 /* the last hope to figure out the ppt limit */
1343                 if (!pptable) {
1344                         dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1345                         return -EINVAL;
1346                 }
1347                 power_limit =
1348                         pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1349         }
1350
1351         if (current_power_limit)
1352                 *current_power_limit = power_limit;
1353         if (default_power_limit)
1354                 *default_power_limit = power_limit;
1355
1356         if (max_power_limit) {
1357                 if (smu->od_enabled) {
1358                         od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1359
1360                         dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1361
1362                         power_limit *= (100 + od_percent);
1363                         power_limit /= 100;
1364                 }
1365
1366                 *max_power_limit = power_limit;
1367         }
1368
1369         return 0;
1370 }
1371
1372 static int arcturus_get_power_profile_mode(struct smu_context *smu,
1373                                            char *buf)
1374 {
1375         DpmActivityMonitorCoeffInt_t activity_monitor;
1376         static const char *profile_name[] = {
1377                                         "BOOTUP_DEFAULT",
1378                                         "3D_FULL_SCREEN",
1379                                         "POWER_SAVING",
1380                                         "VIDEO",
1381                                         "VR",
1382                                         "COMPUTE",
1383                                         "CUSTOM"};
1384         static const char *title[] = {
1385                         "PROFILE_INDEX(NAME)",
1386                         "CLOCK_TYPE(NAME)",
1387                         "FPS",
1388                         "UseRlcBusy",
1389                         "MinActiveFreqType",
1390                         "MinActiveFreq",
1391                         "BoosterFreqType",
1392                         "BoosterFreq",
1393                         "PD_Data_limit_c",
1394                         "PD_Data_error_coeff",
1395                         "PD_Data_error_rate_coeff"};
1396         uint32_t i, size = 0;
1397         int16_t workload_type = 0;
1398         int result = 0;
1399         uint32_t smu_version;
1400
1401         if (!buf)
1402                 return -EINVAL;
1403
1404         result = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1405         if (result)
1406                 return result;
1407
1408         if (smu_version >= 0x360d00)
1409                 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1410                         title[0], title[1], title[2], title[3], title[4], title[5],
1411                         title[6], title[7], title[8], title[9], title[10]);
1412         else
1413                 size += sysfs_emit_at(buf, size, "%16s\n",
1414                         title[0]);
1415
1416         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1417                 /*
1418                  * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1419                  * Not all profile modes are supported on arcturus.
1420                  */
1421                 workload_type = smu_cmn_to_asic_specific_index(smu,
1422                                                                CMN2ASIC_MAPPING_WORKLOAD,
1423                                                                i);
1424                 if (workload_type < 0)
1425                         continue;
1426
1427                 if (smu_version >= 0x360d00) {
1428                         result = smu_cmn_update_table(smu,
1429                                                   SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1430                                                   workload_type,
1431                                                   (void *)(&activity_monitor),
1432                                                   false);
1433                         if (result) {
1434                                 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1435                                 return result;
1436                         }
1437                 }
1438
1439                 size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
1440                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1441
1442                 if (smu_version >= 0x360d00) {
1443                         size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1444                                 " ",
1445                                 0,
1446                                 "GFXCLK",
1447                                 activity_monitor.Gfx_FPS,
1448                                 activity_monitor.Gfx_UseRlcBusy,
1449                                 activity_monitor.Gfx_MinActiveFreqType,
1450                                 activity_monitor.Gfx_MinActiveFreq,
1451                                 activity_monitor.Gfx_BoosterFreqType,
1452                                 activity_monitor.Gfx_BoosterFreq,
1453                                 activity_monitor.Gfx_PD_Data_limit_c,
1454                                 activity_monitor.Gfx_PD_Data_error_coeff,
1455                                 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1456
1457                         size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1458                                 " ",
1459                                 1,
1460                                 "UCLK",
1461                                 activity_monitor.Mem_FPS,
1462                                 activity_monitor.Mem_UseRlcBusy,
1463                                 activity_monitor.Mem_MinActiveFreqType,
1464                                 activity_monitor.Mem_MinActiveFreq,
1465                                 activity_monitor.Mem_BoosterFreqType,
1466                                 activity_monitor.Mem_BoosterFreq,
1467                                 activity_monitor.Mem_PD_Data_limit_c,
1468                                 activity_monitor.Mem_PD_Data_error_coeff,
1469                                 activity_monitor.Mem_PD_Data_error_rate_coeff);
1470                 }
1471         }
1472
1473         return size;
1474 }
1475
1476 static int arcturus_set_power_profile_mode(struct smu_context *smu,
1477                                            long *input,
1478                                            uint32_t size)
1479 {
1480         DpmActivityMonitorCoeffInt_t activity_monitor;
1481         int workload_type = 0;
1482         uint32_t profile_mode = input[size];
1483         int ret = 0;
1484         uint32_t smu_version;
1485
1486         if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1487                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
1488                 return -EINVAL;
1489         }
1490
1491         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1492         if (ret)
1493                 return ret;
1494
1495         if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&
1496              (smu_version >=0x360d00)) {
1497                 ret = smu_cmn_update_table(smu,
1498                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1499                                        WORKLOAD_PPLIB_CUSTOM_BIT,
1500                                        (void *)(&activity_monitor),
1501                                        false);
1502                 if (ret) {
1503                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1504                         return ret;
1505                 }
1506
1507                 switch (input[0]) {
1508                 case 0: /* Gfxclk */
1509                         activity_monitor.Gfx_FPS = input[1];
1510                         activity_monitor.Gfx_UseRlcBusy = input[2];
1511                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1512                         activity_monitor.Gfx_MinActiveFreq = input[4];
1513                         activity_monitor.Gfx_BoosterFreqType = input[5];
1514                         activity_monitor.Gfx_BoosterFreq = input[6];
1515                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1516                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1517                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1518                         break;
1519                 case 1: /* Uclk */
1520                         activity_monitor.Mem_FPS = input[1];
1521                         activity_monitor.Mem_UseRlcBusy = input[2];
1522                         activity_monitor.Mem_MinActiveFreqType = input[3];
1523                         activity_monitor.Mem_MinActiveFreq = input[4];
1524                         activity_monitor.Mem_BoosterFreqType = input[5];
1525                         activity_monitor.Mem_BoosterFreq = input[6];
1526                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1527                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1528                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1529                         break;
1530                 }
1531
1532                 ret = smu_cmn_update_table(smu,
1533                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1534                                        WORKLOAD_PPLIB_CUSTOM_BIT,
1535                                        (void *)(&activity_monitor),
1536                                        true);
1537                 if (ret) {
1538                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1539                         return ret;
1540                 }
1541         }
1542
1543         /*
1544          * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1545          * Not all profile modes are supported on arcturus.
1546          */
1547         workload_type = smu_cmn_to_asic_specific_index(smu,
1548                                                        CMN2ASIC_MAPPING_WORKLOAD,
1549                                                        profile_mode);
1550         if (workload_type < 0) {
1551                 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on arcturus\n", profile_mode);
1552                 return -EINVAL;
1553         }
1554
1555         ret = smu_cmn_send_smc_msg_with_param(smu,
1556                                           SMU_MSG_SetWorkloadMask,
1557                                           1 << workload_type,
1558                                           NULL);
1559         if (ret) {
1560                 dev_err(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
1561                 return ret;
1562         }
1563
1564         smu->power_profile_mode = profile_mode;
1565
1566         return 0;
1567 }
1568
1569 static int arcturus_set_performance_level(struct smu_context *smu,
1570                                           enum amd_dpm_forced_level level)
1571 {
1572         uint32_t smu_version;
1573         int ret;
1574
1575         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1576         if (ret) {
1577                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
1578                 return ret;
1579         }
1580
1581         switch (level) {
1582         case AMD_DPM_FORCED_LEVEL_HIGH:
1583         case AMD_DPM_FORCED_LEVEL_LOW:
1584         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1585         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1586         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1587         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1588                 if ((smu_version >= 0x361200) &&
1589                     (smu_version <= 0x361a00)) {
1590                         dev_err(smu->adev->dev, "Forcing clock level is not supported with "
1591                                "54.18 - 54.26(included) SMU firmwares\n");
1592                         return -EOPNOTSUPP;
1593                 }
1594                 break;
1595         default:
1596                 break;
1597         }
1598
1599         return smu_v11_0_set_performance_level(smu, level);
1600 }
1601
1602 static void arcturus_dump_pptable(struct smu_context *smu)
1603 {
1604         struct smu_table_context *table_context = &smu->smu_table;
1605         PPTable_t *pptable = table_context->driver_pptable;
1606         int i;
1607
1608         dev_info(smu->adev->dev, "Dumped PPTable:\n");
1609
1610         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
1611
1612         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1613         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1614
1615         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1616                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1617                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1618         }
1619
1620         dev_info(smu->adev->dev, "TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1621         dev_info(smu->adev->dev, "TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1622         dev_info(smu->adev->dev, "TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1623         dev_info(smu->adev->dev, "TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1624
1625         dev_info(smu->adev->dev, "TedgeLimit = %d\n", pptable->TedgeLimit);
1626         dev_info(smu->adev->dev, "ThotspotLimit = %d\n", pptable->ThotspotLimit);
1627         dev_info(smu->adev->dev, "TmemLimit = %d\n", pptable->TmemLimit);
1628         dev_info(smu->adev->dev, "Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1629         dev_info(smu->adev->dev, "Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1630         dev_info(smu->adev->dev, "Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1631         dev_info(smu->adev->dev, "FitLimit = %d\n", pptable->FitLimit);
1632
1633         dev_info(smu->adev->dev, "PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1634         dev_info(smu->adev->dev, "PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1635
1636         dev_info(smu->adev->dev, "ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1637
1638         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1639         dev_info(smu->adev->dev, "UlvPadding = 0x%08x\n", pptable->UlvPadding);
1640
1641         dev_info(smu->adev->dev, "UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1642         dev_info(smu->adev->dev, "Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1643         dev_info(smu->adev->dev, "Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1644         dev_info(smu->adev->dev, "Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1645
1646         dev_info(smu->adev->dev, "MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1647         dev_info(smu->adev->dev, "MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1648         dev_info(smu->adev->dev, "MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1649         dev_info(smu->adev->dev, "MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1650
1651         dev_info(smu->adev->dev, "LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1652         dev_info(smu->adev->dev, "LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1653
1654         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
1655                         "  .VoltageMode          = 0x%02x\n"
1656                         "  .SnapToDiscrete       = 0x%02x\n"
1657                         "  .NumDiscreteLevels    = 0x%02x\n"
1658                         "  .padding              = 0x%02x\n"
1659                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1660                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1661                         "  .SsFmin               = 0x%04x\n"
1662                         "  .Padding_16           = 0x%04x\n",
1663                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1664                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1665                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1666                         pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1667                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1668                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1669                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1670                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1671                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1672                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1673                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1674
1675         dev_info(smu->adev->dev, "[PPCLK_VCLK]\n"
1676                         "  .VoltageMode          = 0x%02x\n"
1677                         "  .SnapToDiscrete       = 0x%02x\n"
1678                         "  .NumDiscreteLevels    = 0x%02x\n"
1679                         "  .padding              = 0x%02x\n"
1680                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1681                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1682                         "  .SsFmin               = 0x%04x\n"
1683                         "  .Padding_16           = 0x%04x\n",
1684                         pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1685                         pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1686                         pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1687                         pptable->DpmDescriptor[PPCLK_VCLK].padding,
1688                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1689                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1690                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1691                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1692                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1693                         pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1694                         pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1695
1696         dev_info(smu->adev->dev, "[PPCLK_DCLK]\n"
1697                         "  .VoltageMode          = 0x%02x\n"
1698                         "  .SnapToDiscrete       = 0x%02x\n"
1699                         "  .NumDiscreteLevels    = 0x%02x\n"
1700                         "  .padding              = 0x%02x\n"
1701                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1702                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1703                         "  .SsFmin               = 0x%04x\n"
1704                         "  .Padding_16           = 0x%04x\n",
1705                         pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1706                         pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1707                         pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1708                         pptable->DpmDescriptor[PPCLK_DCLK].padding,
1709                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1710                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1711                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1712                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1713                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1714                         pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1715                         pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1716
1717         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
1718                         "  .VoltageMode          = 0x%02x\n"
1719                         "  .SnapToDiscrete       = 0x%02x\n"
1720                         "  .NumDiscreteLevels    = 0x%02x\n"
1721                         "  .padding              = 0x%02x\n"
1722                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1723                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1724                         "  .SsFmin               = 0x%04x\n"
1725                         "  .Padding_16           = 0x%04x\n",
1726                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1727                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1728                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1729                         pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1730                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1731                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1732                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1733                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1734                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1735                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1736                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1737
1738         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
1739                         "  .VoltageMode          = 0x%02x\n"
1740                         "  .SnapToDiscrete       = 0x%02x\n"
1741                         "  .NumDiscreteLevels    = 0x%02x\n"
1742                         "  .padding              = 0x%02x\n"
1743                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1744                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1745                         "  .SsFmin               = 0x%04x\n"
1746                         "  .Padding_16           = 0x%04x\n",
1747                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1748                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1749                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1750                         pptable->DpmDescriptor[PPCLK_UCLK].padding,
1751                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1752                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1753                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1754                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1755                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1756                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1757                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1758
1759         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
1760                         "  .VoltageMode          = 0x%02x\n"
1761                         "  .SnapToDiscrete       = 0x%02x\n"
1762                         "  .NumDiscreteLevels    = 0x%02x\n"
1763                         "  .padding              = 0x%02x\n"
1764                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1765                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1766                         "  .SsFmin               = 0x%04x\n"
1767                         "  .Padding_16           = 0x%04x\n",
1768                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1769                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1770                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1771                         pptable->DpmDescriptor[PPCLK_FCLK].padding,
1772                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1773                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1774                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1775                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1776                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1777                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1778                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1779
1780
1781         dev_info(smu->adev->dev, "FreqTableGfx\n");
1782         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1783                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1784
1785         dev_info(smu->adev->dev, "FreqTableVclk\n");
1786         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1787                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1788
1789         dev_info(smu->adev->dev, "FreqTableDclk\n");
1790         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1791                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1792
1793         dev_info(smu->adev->dev, "FreqTableSocclk\n");
1794         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1795                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1796
1797         dev_info(smu->adev->dev, "FreqTableUclk\n");
1798         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1799                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1800
1801         dev_info(smu->adev->dev, "FreqTableFclk\n");
1802         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1803                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1804
1805         dev_info(smu->adev->dev, "Mp0clkFreq\n");
1806         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1807                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1808
1809         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
1810         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1811                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1812
1813         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1814         dev_info(smu->adev->dev, "GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1815         dev_info(smu->adev->dev, "Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1816         dev_info(smu->adev->dev, "Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1817         dev_info(smu->adev->dev, "Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1818         dev_info(smu->adev->dev, "Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1819         dev_info(smu->adev->dev, "GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1820         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1821         dev_info(smu->adev->dev, "Padding456 = 0x%x\n", pptable->Padding456);
1822
1823         dev_info(smu->adev->dev, "EnableTdpm = %d\n", pptable->EnableTdpm);
1824         dev_info(smu->adev->dev, "TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1825         dev_info(smu->adev->dev, "TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1826         dev_info(smu->adev->dev, "GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1827
1828         dev_info(smu->adev->dev, "FanStopTemp = %d\n", pptable->FanStopTemp);
1829         dev_info(smu->adev->dev, "FanStartTemp = %d\n", pptable->FanStartTemp);
1830
1831         dev_info(smu->adev->dev, "FanGainEdge = %d\n", pptable->FanGainEdge);
1832         dev_info(smu->adev->dev, "FanGainHotspot = %d\n", pptable->FanGainHotspot);
1833         dev_info(smu->adev->dev, "FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1834         dev_info(smu->adev->dev, "FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1835         dev_info(smu->adev->dev, "FanGainVrMem = %d\n", pptable->FanGainVrMem);
1836         dev_info(smu->adev->dev, "FanGainHbm = %d\n", pptable->FanGainHbm);
1837
1838         dev_info(smu->adev->dev, "FanPwmMin = %d\n", pptable->FanPwmMin);
1839         dev_info(smu->adev->dev, "FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1840         dev_info(smu->adev->dev, "FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1841         dev_info(smu->adev->dev, "FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1842         dev_info(smu->adev->dev, "FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1843         dev_info(smu->adev->dev, "FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1844         dev_info(smu->adev->dev, "FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1845         dev_info(smu->adev->dev, "FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1846         dev_info(smu->adev->dev, "FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1847
1848         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1849         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1850         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1851         dev_info(smu->adev->dev, "FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1852
1853         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1854         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1855         dev_info(smu->adev->dev, "Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1856         dev_info(smu->adev->dev, "Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1857
1858         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1859                         pptable->dBtcGbGfxPll.a,
1860                         pptable->dBtcGbGfxPll.b,
1861                         pptable->dBtcGbGfxPll.c);
1862         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1863                         pptable->dBtcGbGfxAfll.a,
1864                         pptable->dBtcGbGfxAfll.b,
1865                         pptable->dBtcGbGfxAfll.c);
1866         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1867                         pptable->dBtcGbSoc.a,
1868                         pptable->dBtcGbSoc.b,
1869                         pptable->dBtcGbSoc.c);
1870
1871         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1872                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1873                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1874         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1875                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1876                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1877
1878         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1879                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1880                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1881                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1882         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1883                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1884                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1885                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1886
1887         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1888         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1889
1890         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1891         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1892         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1893         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1894
1895         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1896         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1897         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1898         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1899
1900         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1901         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1902
1903         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
1904         for (i = 0; i < NUM_XGMI_LEVELS; i++)
1905                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1906         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1907         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1908
1909         dev_info(smu->adev->dev, "VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1910         dev_info(smu->adev->dev, "VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1911         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1912         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1913         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1914         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1915         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1916         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1917
1918         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1919         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1920                         pptable->ReservedEquation0.a,
1921                         pptable->ReservedEquation0.b,
1922                         pptable->ReservedEquation0.c);
1923         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1924                         pptable->ReservedEquation1.a,
1925                         pptable->ReservedEquation1.b,
1926                         pptable->ReservedEquation1.c);
1927         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1928                         pptable->ReservedEquation2.a,
1929                         pptable->ReservedEquation2.b,
1930                         pptable->ReservedEquation2.c);
1931         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1932                         pptable->ReservedEquation3.a,
1933                         pptable->ReservedEquation3.b,
1934                         pptable->ReservedEquation3.c);
1935
1936         dev_info(smu->adev->dev, "MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1937         dev_info(smu->adev->dev, "PaddingUlv = %d\n", pptable->PaddingUlv);
1938
1939         dev_info(smu->adev->dev, "TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1940         dev_info(smu->adev->dev, "TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1941         dev_info(smu->adev->dev, "TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1942
1943         dev_info(smu->adev->dev, "PccThresholdLow = %d\n", pptable->PccThresholdLow);
1944         dev_info(smu->adev->dev, "PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1945
1946         dev_info(smu->adev->dev, "Board Parameters:\n");
1947         dev_info(smu->adev->dev, "MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1948         dev_info(smu->adev->dev, "MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1949
1950         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1951         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1952         dev_info(smu->adev->dev, "VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1953         dev_info(smu->adev->dev, "BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1954
1955         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1956         dev_info(smu->adev->dev, "ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1957
1958         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1959         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
1960         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1961
1962         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1963         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
1964         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1965
1966         dev_info(smu->adev->dev, "MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1967         dev_info(smu->adev->dev, "MemOffset = 0x%x\n", pptable->MemOffset);
1968         dev_info(smu->adev->dev, "Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1969
1970         dev_info(smu->adev->dev, "BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1971         dev_info(smu->adev->dev, "BoardOffset = 0x%x\n", pptable->BoardOffset);
1972         dev_info(smu->adev->dev, "Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1973
1974         dev_info(smu->adev->dev, "VR0HotGpio = %d\n", pptable->VR0HotGpio);
1975         dev_info(smu->adev->dev, "VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1976         dev_info(smu->adev->dev, "VR1HotGpio = %d\n", pptable->VR1HotGpio);
1977         dev_info(smu->adev->dev, "VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1978
1979         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1980         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1981         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1982
1983         dev_info(smu->adev->dev, "UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1984         dev_info(smu->adev->dev, "UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1985         dev_info(smu->adev->dev, "UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1986
1987         dev_info(smu->adev->dev, "FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1988         dev_info(smu->adev->dev, "FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1989         dev_info(smu->adev->dev, "FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1990
1991         dev_info(smu->adev->dev, "FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1992         dev_info(smu->adev->dev, "FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1993         dev_info(smu->adev->dev, "FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
1994
1995         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1996                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
1997                 dev_info(smu->adev->dev, "                   .Enabled = %d\n",
1998                                 pptable->I2cControllers[i].Enabled);
1999                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
2000                                 pptable->I2cControllers[i].SlaveAddress);
2001                 dev_info(smu->adev->dev, "                   .ControllerPort = %d\n",
2002                                 pptable->I2cControllers[i].ControllerPort);
2003                 dev_info(smu->adev->dev, "                   .ControllerName = %d\n",
2004                                 pptable->I2cControllers[i].ControllerName);
2005                 dev_info(smu->adev->dev, "                   .ThermalThrottler = %d\n",
2006                                 pptable->I2cControllers[i].ThermalThrotter);
2007                 dev_info(smu->adev->dev, "                   .I2cProtocol = %d\n",
2008                                 pptable->I2cControllers[i].I2cProtocol);
2009                 dev_info(smu->adev->dev, "                   .Speed = %d\n",
2010                                 pptable->I2cControllers[i].Speed);
2011         }
2012
2013         dev_info(smu->adev->dev, "MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
2014         dev_info(smu->adev->dev, "DramBitWidth = %d\n", pptable->DramBitWidth);
2015
2016         dev_info(smu->adev->dev, "TotalBoardPower = %d\n", pptable->TotalBoardPower);
2017
2018         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
2019         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2020                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
2021         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
2022         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2023                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
2024         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
2025         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2026                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
2027         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
2028         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
2029                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
2030
2031 }
2032
2033 static bool arcturus_is_dpm_running(struct smu_context *smu)
2034 {
2035         int ret = 0;
2036         uint32_t feature_mask[2];
2037         uint64_t feature_enabled;
2038
2039         ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
2040         if (ret)
2041                 return false;
2042
2043         feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
2044
2045         return !!(feature_enabled & SMC_DPM_FEATURE);
2046 }
2047
2048 static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
2049 {
2050         int ret = 0;
2051
2052         if (enable) {
2053                 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) {
2054                         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_DPM_BIT, 1);
2055                         if (ret) {
2056                                 dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n");
2057                                 return ret;
2058                         }
2059                 }
2060         } else {
2061                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_DPM_BIT)) {
2062                         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_DPM_BIT, 0);
2063                         if (ret) {
2064                                 dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n");
2065                                 return ret;
2066                         }
2067                 }
2068         }
2069
2070         return ret;
2071 }
2072
2073 static int arcturus_i2c_xfer(struct i2c_adapter *i2c_adap,
2074                              struct i2c_msg *msg, int num_msgs)
2075 {
2076         struct amdgpu_device *adev = to_amdgpu_device(i2c_adap);
2077         struct smu_table_context *smu_table = &adev->smu.smu_table;
2078         struct smu_table *table = &smu_table->driver_table;
2079         SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
2080         int i, j, r, c;
2081         u16 dir;
2082
2083         req = kzalloc(sizeof(*req), GFP_KERNEL);
2084         if (!req)
2085                 return -ENOMEM;
2086
2087         req->I2CcontrollerPort = 0;
2088         req->I2CSpeed = I2C_SPEED_FAST_400K;
2089         req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
2090         dir = msg[0].flags & I2C_M_RD;
2091
2092         for (c = i = 0; i < num_msgs; i++) {
2093                 for (j = 0; j < msg[i].len; j++, c++) {
2094                         SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
2095
2096                         if (!(msg[i].flags & I2C_M_RD)) {
2097                                 /* write */
2098                                 cmd->Cmd = I2C_CMD_WRITE;
2099                                 cmd->RegisterAddr = msg[i].buf[j];
2100                         }
2101
2102                         if ((dir ^ msg[i].flags) & I2C_M_RD) {
2103                                 /* The direction changes.
2104                                  */
2105                                 dir = msg[i].flags & I2C_M_RD;
2106                                 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
2107                         }
2108
2109                         req->NumCmds++;
2110
2111                         /*
2112                          * Insert STOP if we are at the last byte of either last
2113                          * message for the transaction or the client explicitly
2114                          * requires a STOP at this particular message.
2115                          */
2116                         if ((j == msg[i].len - 1) &&
2117                             ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
2118                                 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
2119                                 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
2120                         }
2121                 }
2122         }
2123         mutex_lock(&adev->smu.mutex);
2124         r = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
2125         mutex_unlock(&adev->smu.mutex);
2126         if (r)
2127                 goto fail;
2128
2129         for (c = i = 0; i < num_msgs; i++) {
2130                 if (!(msg[i].flags & I2C_M_RD)) {
2131                         c += msg[i].len;
2132                         continue;
2133                 }
2134                 for (j = 0; j < msg[i].len; j++, c++) {
2135                         SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
2136
2137                         msg[i].buf[j] = cmd->Data;
2138                 }
2139         }
2140         r = num_msgs;
2141 fail:
2142         kfree(req);
2143         return r;
2144 }
2145
2146 static u32 arcturus_i2c_func(struct i2c_adapter *adap)
2147 {
2148         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2149 }
2150
2151
2152 static const struct i2c_algorithm arcturus_i2c_algo = {
2153         .master_xfer = arcturus_i2c_xfer,
2154         .functionality = arcturus_i2c_func,
2155 };
2156
2157
2158 static const struct i2c_adapter_quirks arcturus_i2c_control_quirks = {
2159         .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
2160         .max_read_len  = MAX_SW_I2C_COMMANDS,
2161         .max_write_len = MAX_SW_I2C_COMMANDS,
2162         .max_comb_1st_msg_len = 2,
2163         .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
2164 };
2165
2166 static int arcturus_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2167 {
2168         struct amdgpu_device *adev = to_amdgpu_device(control);
2169         int res;
2170
2171         control->owner = THIS_MODULE;
2172         control->class = I2C_CLASS_HWMON;
2173         control->dev.parent = &adev->pdev->dev;
2174         control->algo = &arcturus_i2c_algo;
2175         control->quirks = &arcturus_i2c_control_quirks;
2176         snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2177
2178         res = i2c_add_adapter(control);
2179         if (res)
2180                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2181
2182         return res;
2183 }
2184
2185 static void arcturus_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2186 {
2187         i2c_del_adapter(control);
2188 }
2189
2190 static void arcturus_get_unique_id(struct smu_context *smu)
2191 {
2192         struct amdgpu_device *adev = smu->adev;
2193         uint32_t top32 = 0, bottom32 = 0, smu_version;
2194         uint64_t id;
2195
2196         if (smu_cmn_get_smc_version(smu, NULL, &smu_version)) {
2197                 dev_warn(adev->dev, "Failed to get smu version, cannot get unique_id or serial_number\n");
2198                 return;
2199         }
2200
2201         /* PPSMC_MSG_ReadSerial* is supported by 54.23.0 and onwards */
2202         if (smu_version < 0x361700) {
2203                 dev_warn(adev->dev, "ReadSerial is only supported by PMFW 54.23.0 and onwards\n");
2204                 return;
2205         }
2206
2207         /* Get the SN to turn into a Unique ID */
2208         smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32);
2209         smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32);
2210
2211         id = ((uint64_t)bottom32 << 32) | top32;
2212         adev->unique_id = id;
2213         /* For Arcturus-and-later, unique_id == serial_number, so convert it to a
2214          * 16-digit HEX string for convenience and backwards-compatibility
2215          */
2216         sprintf(adev->serial, "%llx", id);
2217 }
2218
2219 static int arcturus_set_df_cstate(struct smu_context *smu,
2220                                   enum pp_df_cstate state)
2221 {
2222         uint32_t smu_version;
2223         int ret;
2224
2225         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2226         if (ret) {
2227                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
2228                 return ret;
2229         }
2230
2231         /* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */
2232         if (smu_version < 0x360F00) {
2233                 dev_err(smu->adev->dev, "DFCstateControl is only supported by PMFW 54.15.0 and onwards\n");
2234                 return -EINVAL;
2235         }
2236
2237         return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
2238 }
2239
2240 static int arcturus_allow_xgmi_power_down(struct smu_context *smu, bool en)
2241 {
2242         uint32_t smu_version;
2243         int ret;
2244
2245         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2246         if (ret) {
2247                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
2248                 return ret;
2249         }
2250
2251         /* PPSMC_MSG_GmiPwrDnControl is supported by 54.23.0 and onwards */
2252         if (smu_version < 0x00361700) {
2253                 dev_err(smu->adev->dev, "XGMI power down control is only supported by PMFW 54.23.0 and onwards\n");
2254                 return -EINVAL;
2255         }
2256
2257         if (en)
2258                 return smu_cmn_send_smc_msg_with_param(smu,
2259                                                    SMU_MSG_GmiPwrDnControl,
2260                                                    1,
2261                                                    NULL);
2262
2263         return smu_cmn_send_smc_msg_with_param(smu,
2264                                            SMU_MSG_GmiPwrDnControl,
2265                                            0,
2266                                            NULL);
2267 }
2268
2269 static const struct throttling_logging_label {
2270         uint32_t feature_mask;
2271         const char *label;
2272 } logging_label[] = {
2273         {(1U << THROTTLER_TEMP_HOTSPOT_BIT), "GPU"},
2274         {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
2275         {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
2276         {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
2277         {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
2278         {(1U << THROTTLER_VRHOT0_BIT), "VR0 HOT"},
2279         {(1U << THROTTLER_VRHOT1_BIT), "VR1 HOT"},
2280 };
2281 static void arcturus_log_thermal_throttling_event(struct smu_context *smu)
2282 {
2283         int ret;
2284         int throttler_idx, throtting_events = 0, buf_idx = 0;
2285         struct amdgpu_device *adev = smu->adev;
2286         uint32_t throttler_status;
2287         char log_buf[256];
2288
2289         ret = arcturus_get_smu_metrics_data(smu,
2290                                             METRICS_THROTTLER_STATUS,
2291                                             &throttler_status);
2292         if (ret)
2293                 return;
2294
2295         memset(log_buf, 0, sizeof(log_buf));
2296         for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
2297              throttler_idx++) {
2298                 if (throttler_status & logging_label[throttler_idx].feature_mask) {
2299                         throtting_events++;
2300                         buf_idx += snprintf(log_buf + buf_idx,
2301                                             sizeof(log_buf) - buf_idx,
2302                                             "%s%s",
2303                                             throtting_events > 1 ? " and " : "",
2304                                             logging_label[throttler_idx].label);
2305                         if (buf_idx >= sizeof(log_buf)) {
2306                                 dev_err(adev->dev, "buffer overflow!\n");
2307                                 log_buf[sizeof(log_buf) - 1] = '\0';
2308                                 break;
2309                         }
2310                 }
2311         }
2312
2313         dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
2314                         log_buf);
2315         kgd2kfd_smi_event_throttle(smu->adev->kfd.dev,
2316                 smu_cmn_get_indep_throttler_status(throttler_status,
2317                                                    arcturus_throttler_map));
2318 }
2319
2320 static uint16_t arcturus_get_current_pcie_link_speed(struct smu_context *smu)
2321 {
2322         struct amdgpu_device *adev = smu->adev;
2323         uint32_t esm_ctrl;
2324
2325         /* TODO: confirm this on real target */
2326         esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
2327         if ((esm_ctrl >> 15) & 0x1FFFF)
2328                 return (uint16_t)(((esm_ctrl >> 8) & 0x3F) + 128);
2329
2330         return smu_v11_0_get_current_pcie_link_speed(smu);
2331 }
2332
2333 static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu,
2334                                         void **table)
2335 {
2336         struct smu_table_context *smu_table = &smu->smu_table;
2337         struct gpu_metrics_v1_3 *gpu_metrics =
2338                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2339         SmuMetrics_t metrics;
2340         int ret = 0;
2341
2342         ret = smu_cmn_get_metrics_table(smu,
2343                                         &metrics,
2344                                         true);
2345         if (ret)
2346                 return ret;
2347
2348         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2349
2350         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2351         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2352         gpu_metrics->temperature_mem = metrics.TemperatureHBM;
2353         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2354         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2355         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
2356
2357         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2358         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2359         gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
2360
2361         gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2362         gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2363
2364         gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2365         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2366         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2367         gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
2368         gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
2369
2370         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2371         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2372         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2373         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2374         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2375
2376         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2377         gpu_metrics->indep_throttle_status =
2378                         smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
2379                                                            arcturus_throttler_map);
2380
2381         gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2382
2383         gpu_metrics->pcie_link_width =
2384                         smu_v11_0_get_current_pcie_link_width(smu);
2385         gpu_metrics->pcie_link_speed =
2386                         arcturus_get_current_pcie_link_speed(smu);
2387
2388         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2389
2390         *table = (void *)gpu_metrics;
2391
2392         return sizeof(struct gpu_metrics_v1_3);
2393 }
2394
2395 static const struct pptable_funcs arcturus_ppt_funcs = {
2396         /* init dpm */
2397         .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
2398         /* btc */
2399         .run_btc = arcturus_run_btc,
2400         /* dpm/clk tables */
2401         .set_default_dpm_table = arcturus_set_default_dpm_table,
2402         .populate_umd_state_clk = arcturus_populate_umd_state_clk,
2403         .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
2404         .print_clk_levels = arcturus_print_clk_levels,
2405         .force_clk_levels = arcturus_force_clk_levels,
2406         .read_sensor = arcturus_read_sensor,
2407         .get_fan_speed_pwm = arcturus_get_fan_speed_pwm,
2408         .get_fan_speed_rpm = arcturus_get_fan_speed_rpm,
2409         .get_power_profile_mode = arcturus_get_power_profile_mode,
2410         .set_power_profile_mode = arcturus_set_power_profile_mode,
2411         .set_performance_level = arcturus_set_performance_level,
2412         /* debug (internal used) */
2413         .dump_pptable = arcturus_dump_pptable,
2414         .get_power_limit = arcturus_get_power_limit,
2415         .is_dpm_running = arcturus_is_dpm_running,
2416         .dpm_set_vcn_enable = arcturus_dpm_set_vcn_enable,
2417         .i2c_init = arcturus_i2c_control_init,
2418         .i2c_fini = arcturus_i2c_control_fini,
2419         .get_unique_id = arcturus_get_unique_id,
2420         .init_microcode = smu_v11_0_init_microcode,
2421         .load_microcode = smu_v11_0_load_microcode,
2422         .fini_microcode = smu_v11_0_fini_microcode,
2423         .init_smc_tables = arcturus_init_smc_tables,
2424         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2425         .init_power = smu_v11_0_init_power,
2426         .fini_power = smu_v11_0_fini_power,
2427         .check_fw_status = smu_v11_0_check_fw_status,
2428         /* pptable related */
2429         .setup_pptable = arcturus_setup_pptable,
2430         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2431         .check_fw_version = smu_v11_0_check_fw_version,
2432         .write_pptable = smu_cmn_write_pptable,
2433         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2434         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2435         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2436         .system_features_control = smu_v11_0_system_features_control,
2437         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2438         .send_smc_msg = smu_cmn_send_smc_msg,
2439         .init_display_count = NULL,
2440         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2441         .get_enabled_mask = smu_cmn_get_enabled_mask,
2442         .feature_is_enabled = smu_cmn_feature_is_enabled,
2443         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2444         .notify_display_change = NULL,
2445         .set_power_limit = smu_v11_0_set_power_limit,
2446         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2447         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2448         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2449         .set_min_dcef_deep_sleep = NULL,
2450         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2451         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2452         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2453         .set_fan_speed_pwm = arcturus_set_fan_speed_pwm,
2454         .set_fan_speed_rpm = arcturus_set_fan_speed_rpm,
2455         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2456         .gfx_off_control = smu_v11_0_gfx_off_control,
2457         .register_irq_handler = smu_v11_0_register_irq_handler,
2458         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2459         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2460         .baco_is_support = smu_v11_0_baco_is_support,
2461         .baco_get_state = smu_v11_0_baco_get_state,
2462         .baco_set_state = smu_v11_0_baco_set_state,
2463         .baco_enter = smu_v11_0_baco_enter,
2464         .baco_exit = smu_v11_0_baco_exit,
2465         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2466         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2467         .set_df_cstate = arcturus_set_df_cstate,
2468         .allow_xgmi_power_down = arcturus_allow_xgmi_power_down,
2469         .log_thermal_throttling_event = arcturus_log_thermal_throttling_event,
2470         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2471         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2472         .get_gpu_metrics = arcturus_get_gpu_metrics,
2473         .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
2474         .deep_sleep_control = smu_v11_0_deep_sleep_control,
2475         .get_fan_parameters = arcturus_get_fan_parameters,
2476         .interrupt_work = smu_v11_0_interrupt_work,
2477         .set_light_sbr = smu_v11_0_set_light_sbr,
2478         .set_mp1_state = smu_cmn_set_mp1_state,
2479 };
2480
2481 void arcturus_set_ppt_funcs(struct smu_context *smu)
2482 {
2483         smu->ppt_funcs = &arcturus_ppt_funcs;
2484         smu->message_map = arcturus_message_map;
2485         smu->clock_map = arcturus_clk_map;
2486         smu->feature_map = arcturus_feature_mask_map;
2487         smu->table_map = arcturus_table_map;
2488         smu->pwr_src_map = arcturus_pwr_src_map;
2489         smu->workload_map = arcturus_workload_map;
2490 }