drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #define SWSMU_CODE_LAYER_L2
  25
  26 #include <linux/firmware.h>
  27 #include "amdgpu.h"
  28 #include "amdgpu_smu.h"
  29 #include "atomfirmware.h"
  30 #include "amdgpu_atomfirmware.h"
  31 #include "amdgpu_atombios.h"
  32 #include "smu_v11_0.h"
  33 #include "smu11_driver_if_arcturus.h"
  34 #include "soc15_common.h"
  35 #include "atom.h"
  36 #include "power_state.h"
  37 #include "arcturus_ppt.h"
  38 #include "smu_v11_0_pptable.h"
  39 #include "arcturus_ppsmc.h"
  40 #include "nbio/nbio_7_4_offset.h"
  41 #include "nbio/nbio_7_4_sh_mask.h"
  42 #include "thm/thm_11_0_2_offset.h"
  43 #include "thm/thm_11_0_2_sh_mask.h"
  44 #include "amdgpu_xgmi.h"
  45 #include <linux/i2c.h>
  46 #include <linux/pci.h>
  47 #include "amdgpu_ras.h"
  48 #include "smu_cmn.h"
  49
  50 /*
  51  * DO NOT use these for err/warn/info/debug messages.
  52  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  53  * They are more MGPU friendly.
  54  */
  55 #undef pr_err
  56 #undef pr_warn
  57 #undef pr_info
  58 #undef pr_debug
  59
  60 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
  61
  62 #define ARCTURUS_FEA_MAP(smu_feature, arcturus_feature) \
  63         [smu_feature] = {1, (arcturus_feature)}
  64
  65 #define SMU_FEATURES_LOW_MASK        0x00000000FFFFFFFF
  66 #define SMU_FEATURES_LOW_SHIFT       0
  67 #define SMU_FEATURES_HIGH_MASK       0xFFFFFFFF00000000
  68 #define SMU_FEATURES_HIGH_SHIFT      32
  69
  70 #define SMC_DPM_FEATURE ( \
  71         FEATURE_DPM_PREFETCHER_MASK | \
  72         FEATURE_DPM_GFXCLK_MASK | \
  73         FEATURE_DPM_UCLK_MASK | \
  74         FEATURE_DPM_SOCCLK_MASK | \
  75         FEATURE_DPM_MP0CLK_MASK | \
  76         FEATURE_DPM_FCLK_MASK | \
  77         FEATURE_DPM_XGMI_MASK)
  78
  79 /* possible frequency drift (1Mhz) */
  80 #define EPSILON                         1
  81
  82 #define smnPCIE_ESM_CTRL                        0x111003D0
  83
  84 static const struct cmn2asic_msg_mapping arcturus_message_map[SMU_MSG_MAX_COUNT] = {
  85         MSG_MAP(TestMessage,                         PPSMC_MSG_TestMessage,                     0),
  86         MSG_MAP(GetSmuVersion,                       PPSMC_MSG_GetSmuVersion,                   1),
  87         MSG_MAP(GetDriverIfVersion,                  PPSMC_MSG_GetDriverIfVersion,              1),
  88         MSG_MAP(SetAllowedFeaturesMaskLow,           PPSMC_MSG_SetAllowedFeaturesMaskLow,       0),
  89         MSG_MAP(SetAllowedFeaturesMaskHigh,          PPSMC_MSG_SetAllowedFeaturesMaskHigh,      0),
  90         MSG_MAP(EnableAllSmuFeatures,                PPSMC_MSG_EnableAllSmuFeatures,            0),
  91         MSG_MAP(DisableAllSmuFeatures,               PPSMC_MSG_DisableAllSmuFeatures,           0),
  92         MSG_MAP(EnableSmuFeaturesLow,                PPSMC_MSG_EnableSmuFeaturesLow,            1),
  93         MSG_MAP(EnableSmuFeaturesHigh,               PPSMC_MSG_EnableSmuFeaturesHigh,           1),
  94         MSG_MAP(DisableSmuFeaturesLow,               PPSMC_MSG_DisableSmuFeaturesLow,           0),
  95         MSG_MAP(DisableSmuFeaturesHigh,              PPSMC_MSG_DisableSmuFeaturesHigh,          0),
  96         MSG_MAP(GetEnabledSmuFeaturesLow,            PPSMC_MSG_GetEnabledSmuFeaturesLow,        0),
  97         MSG_MAP(GetEnabledSmuFeaturesHigh,           PPSMC_MSG_GetEnabledSmuFeaturesHigh,       0),
  98         MSG_MAP(SetDriverDramAddrHigh,               PPSMC_MSG_SetDriverDramAddrHigh,           1),
  99         MSG_MAP(SetDriverDramAddrLow,                PPSMC_MSG_SetDriverDramAddrLow,            1),
 100         MSG_MAP(SetToolsDramAddrHigh,                PPSMC_MSG_SetToolsDramAddrHigh,            0),
 101         MSG_MAP(SetToolsDramAddrLow,                 PPSMC_MSG_SetToolsDramAddrLow,             0),
 102         MSG_MAP(TransferTableSmu2Dram,               PPSMC_MSG_TransferTableSmu2Dram,           1),
 103         MSG_MAP(TransferTableDram2Smu,               PPSMC_MSG_TransferTableDram2Smu,           0),
 104         MSG_MAP(UseDefaultPPTable,                   PPSMC_MSG_UseDefaultPPTable,               0),
 105         MSG_MAP(UseBackupPPTable,                    PPSMC_MSG_UseBackupPPTable,                0),
 106         MSG_MAP(SetSystemVirtualDramAddrHigh,        PPSMC_MSG_SetSystemVirtualDramAddrHigh,    0),
 107         MSG_MAP(SetSystemVirtualDramAddrLow,         PPSMC_MSG_SetSystemVirtualDramAddrLow,     0),
 108         MSG_MAP(EnterBaco,                           PPSMC_MSG_EnterBaco,                       0),
 109         MSG_MAP(ExitBaco,                            PPSMC_MSG_ExitBaco,                        0),
 110         MSG_MAP(ArmD3,                               PPSMC_MSG_ArmD3,                           0),
 111         MSG_MAP(SetSoftMinByFreq,                    PPSMC_MSG_SetSoftMinByFreq,                0),
 112         MSG_MAP(SetSoftMaxByFreq,                    PPSMC_MSG_SetSoftMaxByFreq,                0),
 113         MSG_MAP(SetHardMinByFreq,                    PPSMC_MSG_SetHardMinByFreq,                0),
 114         MSG_MAP(SetHardMaxByFreq,                    PPSMC_MSG_SetHardMaxByFreq,                0),
 115         MSG_MAP(GetMinDpmFreq,                       PPSMC_MSG_GetMinDpmFreq,                   0),
 116         MSG_MAP(GetMaxDpmFreq,                       PPSMC_MSG_GetMaxDpmFreq,                   0),
 117         MSG_MAP(GetDpmFreqByIndex,                   PPSMC_MSG_GetDpmFreqByIndex,               1),
 118         MSG_MAP(SetWorkloadMask,                     PPSMC_MSG_SetWorkloadMask,                 1),
 119         MSG_MAP(SetDfSwitchType,                     PPSMC_MSG_SetDfSwitchType,                 0),
 120         MSG_MAP(GetVoltageByDpm,                     PPSMC_MSG_GetVoltageByDpm,                 0),
 121         MSG_MAP(GetVoltageByDpmOverdrive,            PPSMC_MSG_GetVoltageByDpmOverdrive,        0),
 122         MSG_MAP(SetPptLimit,                         PPSMC_MSG_SetPptLimit,                     0),
 123         MSG_MAP(GetPptLimit,                         PPSMC_MSG_GetPptLimit,                     1),
 124         MSG_MAP(PowerUpVcn0,                         PPSMC_MSG_PowerUpVcn0,                     0),
 125         MSG_MAP(PowerDownVcn0,                       PPSMC_MSG_PowerDownVcn0,                   0),
 126         MSG_MAP(PowerUpVcn1,                         PPSMC_MSG_PowerUpVcn1,                     0),
 127         MSG_MAP(PowerDownVcn1,                       PPSMC_MSG_PowerDownVcn1,                   0),
 128         MSG_MAP(PrepareMp1ForUnload,                 PPSMC_MSG_PrepareMp1ForUnload,             0),
 129         MSG_MAP(PrepareMp1ForReset,                  PPSMC_MSG_PrepareMp1ForReset,              0),
 130         MSG_MAP(PrepareMp1ForShutdown,               PPSMC_MSG_PrepareMp1ForShutdown,           0),
 131         MSG_MAP(SoftReset,                           PPSMC_MSG_SoftReset,                       0),
 132         MSG_MAP(RunAfllBtc,                          PPSMC_MSG_RunAfllBtc,                      0),
 133         MSG_MAP(RunDcBtc,                            PPSMC_MSG_RunDcBtc,                        0),
 134         MSG_MAP(DramLogSetDramAddrHigh,              PPSMC_MSG_DramLogSetDramAddrHigh,          0),
 135         MSG_MAP(DramLogSetDramAddrLow,               PPSMC_MSG_DramLogSetDramAddrLow,           0),
 136         MSG_MAP(DramLogSetDramSize,                  PPSMC_MSG_DramLogSetDramSize,              0),
 137         MSG_MAP(GetDebugData,                        PPSMC_MSG_GetDebugData,                    0),
 138         MSG_MAP(WaflTest,                            PPSMC_MSG_WaflTest,                        0),
 139         MSG_MAP(SetXgmiMode,                         PPSMC_MSG_SetXgmiMode,                     0),
 140         MSG_MAP(SetMemoryChannelEnable,              PPSMC_MSG_SetMemoryChannelEnable,          0),
 141         MSG_MAP(DFCstateControl,                     PPSMC_MSG_DFCstateControl,                 0),
 142         MSG_MAP(GmiPwrDnControl,                     PPSMC_MSG_GmiPwrDnControl,                 0),
 143         MSG_MAP(ReadSerialNumTop32,                  PPSMC_MSG_ReadSerialNumTop32,              1),
 144         MSG_MAP(ReadSerialNumBottom32,               PPSMC_MSG_ReadSerialNumBottom32,           1),
 145         MSG_MAP(LightSBR,                            PPSMC_MSG_LightSBR,                        0),
 146 };
 147
 148 static const struct cmn2asic_mapping arcturus_clk_map[SMU_CLK_COUNT] = {
 149         CLK_MAP(GFXCLK, PPCLK_GFXCLK),
 150         CLK_MAP(SCLK,   PPCLK_GFXCLK),
 151         CLK_MAP(SOCCLK, PPCLK_SOCCLK),
 152         CLK_MAP(FCLK, PPCLK_FCLK),
 153         CLK_MAP(UCLK, PPCLK_UCLK),
 154         CLK_MAP(MCLK, PPCLK_UCLK),
 155         CLK_MAP(DCLK, PPCLK_DCLK),
 156         CLK_MAP(VCLK, PPCLK_VCLK),
 157 };
 158
 159 static const struct cmn2asic_mapping arcturus_feature_mask_map[SMU_FEATURE_COUNT] = {
 160         FEA_MAP(DPM_PREFETCHER),
 161         FEA_MAP(DPM_GFXCLK),
 162         FEA_MAP(DPM_UCLK),
 163         FEA_MAP(DPM_SOCCLK),
 164         FEA_MAP(DPM_FCLK),
 165         FEA_MAP(DPM_MP0CLK),
 166         ARCTURUS_FEA_MAP(SMU_FEATURE_XGMI_BIT, FEATURE_DPM_XGMI_BIT),
 167         FEA_MAP(DS_GFXCLK),
 168         FEA_MAP(DS_SOCCLK),
 169         FEA_MAP(DS_LCLK),
 170         FEA_MAP(DS_FCLK),
 171         FEA_MAP(DS_UCLK),
 172         FEA_MAP(GFX_ULV),
 173         ARCTURUS_FEA_MAP(SMU_FEATURE_VCN_PG_BIT, FEATURE_DPM_VCN_BIT),
 174         FEA_MAP(RSMU_SMN_CG),
 175         FEA_MAP(WAFL_CG),
 176         FEA_MAP(PPT),
 177         FEA_MAP(TDC),
 178         FEA_MAP(APCC_PLUS),
 179         FEA_MAP(VR0HOT),
 180         FEA_MAP(VR1HOT),
 181         FEA_MAP(FW_CTF),
 182         FEA_MAP(FAN_CONTROL),
 183         FEA_MAP(THERMAL),
 184         FEA_MAP(OUT_OF_BAND_MONITOR),
 185         FEA_MAP(TEMP_DEPENDENT_VMIN),
 186 };
 187
 188 static const struct cmn2asic_mapping arcturus_table_map[SMU_TABLE_COUNT] = {
 189         TAB_MAP(PPTABLE),
 190         TAB_MAP(AVFS),
 191         TAB_MAP(AVFS_PSM_DEBUG),
 192         TAB_MAP(AVFS_FUSE_OVERRIDE),
 193         TAB_MAP(PMSTATUSLOG),
 194         TAB_MAP(SMU_METRICS),
 195         TAB_MAP(DRIVER_SMU_CONFIG),
 196         TAB_MAP(OVERDRIVE),
 197         TAB_MAP(I2C_COMMANDS),
 198         TAB_MAP(ACTIVITY_MONITOR_COEFF),
 199 };
 200
 201 static const struct cmn2asic_mapping arcturus_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
 202         PWR_MAP(AC),
 203         PWR_MAP(DC),
 204 };
 205
 206 static const struct cmn2asic_mapping arcturus_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
 207         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT,       WORKLOAD_PPLIB_DEFAULT_BIT),
 208         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING,          WORKLOAD_PPLIB_POWER_SAVING_BIT),
 209         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO,                WORKLOAD_PPLIB_VIDEO_BIT),
 210         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE,              WORKLOAD_PPLIB_COMPUTE_BIT),
 211         WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM,               WORKLOAD_PPLIB_CUSTOM_BIT),
 212 };
 213
 214 static const uint8_t arcturus_throttler_map[] = {
 215         [THROTTLER_TEMP_EDGE_BIT]       = (SMU_THROTTLER_TEMP_EDGE_BIT),
 216         [THROTTLER_TEMP_HOTSPOT_BIT]    = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
 217         [THROTTLER_TEMP_MEM_BIT]        = (SMU_THROTTLER_TEMP_MEM_BIT),
 218         [THROTTLER_TEMP_VR_GFX_BIT]     = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
 219         [THROTTLER_TEMP_VR_MEM_BIT]     = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
 220         [THROTTLER_TEMP_VR_SOC_BIT]     = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
 221         [THROTTLER_TDC_GFX_BIT]         = (SMU_THROTTLER_TDC_GFX_BIT),
 222         [THROTTLER_TDC_SOC_BIT]         = (SMU_THROTTLER_TDC_SOC_BIT),
 223         [THROTTLER_PPT0_BIT]            = (SMU_THROTTLER_PPT0_BIT),
 224         [THROTTLER_PPT1_BIT]            = (SMU_THROTTLER_PPT1_BIT),
 225         [THROTTLER_PPT2_BIT]            = (SMU_THROTTLER_PPT2_BIT),
 226         [THROTTLER_PPT3_BIT]            = (SMU_THROTTLER_PPT3_BIT),
 227         [THROTTLER_PPM_BIT]             = (SMU_THROTTLER_PPM_BIT),
 228         [THROTTLER_FIT_BIT]             = (SMU_THROTTLER_FIT_BIT),
 229         [THROTTLER_APCC_BIT]            = (SMU_THROTTLER_APCC_BIT),
 230         [THROTTLER_VRHOT0_BIT]          = (SMU_THROTTLER_VRHOT0_BIT),
 231         [THROTTLER_VRHOT1_BIT]          = (SMU_THROTTLER_VRHOT1_BIT),
 232 };
 233
 234 static int arcturus_tables_init(struct smu_context *smu)
 235 {
 236         struct smu_table_context *smu_table = &smu->smu_table;
 237         struct smu_table *tables = smu_table->tables;
 238
 239         SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
 240                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 241
 242         SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
 243                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 244
 245         SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
 246                        PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 247
 248         SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
 249                                PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
 250
 251         SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
 252                        sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
 253                        AMDGPU_GEM_DOMAIN_VRAM);
 254
 255         smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
 256         if (!smu_table->metrics_table)
 257                 return -ENOMEM;
 258         smu_table->metrics_time = 0;
 259
 260         smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
 261         smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
 262         if (!smu_table->gpu_metrics_table) {
 263                 kfree(smu_table->metrics_table);
 264                 return -ENOMEM;
 265         }
 266
 267         return 0;
 268 }
 269
 270 static int arcturus_allocate_dpm_context(struct smu_context *smu)
 271 {
 272         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 273
 274         smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
 275                                        GFP_KERNEL);
 276         if (!smu_dpm->dpm_context)
 277                 return -ENOMEM;
 278         smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
 279
 280         smu_dpm->dpm_current_power_state = kzalloc(sizeof(struct smu_power_state),
 281                                        GFP_KERNEL);
 282         if (!smu_dpm->dpm_current_power_state)
 283                 return -ENOMEM;
 284
 285         smu_dpm->dpm_request_power_state = kzalloc(sizeof(struct smu_power_state),
 286                                        GFP_KERNEL);
 287         if (!smu_dpm->dpm_request_power_state)
 288                 return -ENOMEM;
 289
 290         return 0;
 291 }
 292
 293 static int arcturus_init_smc_tables(struct smu_context *smu)
 294 {
 295         int ret = 0;
 296
 297         ret = arcturus_tables_init(smu);
 298         if (ret)
 299                 return ret;
 300
 301         ret = arcturus_allocate_dpm_context(smu);
 302         if (ret)
 303                 return ret;
 304
 305         return smu_v11_0_init_smc_tables(smu);
 306 }
 307
 308 static int
 309 arcturus_get_allowed_feature_mask(struct smu_context *smu,
 310                                   uint32_t *feature_mask, uint32_t num)
 311 {
 312         if (num > 2)
 313                 return -EINVAL;
 314
 315         /* pptable will handle the features to enable */
 316         memset(feature_mask, 0xFF, sizeof(uint32_t) * num);
 317
 318         return 0;
 319 }
 320
 321 static int arcturus_set_default_dpm_table(struct smu_context *smu)
 322 {
 323         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 324         PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
 325         struct smu_11_0_dpm_table *dpm_table = NULL;
 326         int ret = 0;
 327
 328         /* socclk dpm table setup */
 329         dpm_table = &dpm_context->dpm_tables.soc_table;
 330         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 331                 ret = smu_v11_0_set_single_dpm_table(smu,
 332                                                      SMU_SOCCLK,
 333                                                      dpm_table);
 334                 if (ret)
 335                         return ret;
 336                 dpm_table->is_fine_grained =
 337                         !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
 338         } else {
 339                 dpm_table->count = 1;
 340                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
 341                 dpm_table->dpm_levels[0].enabled = true;
 342                 dpm_table->min = dpm_table->dpm_levels[0].value;
 343                 dpm_table->max = dpm_table->dpm_levels[0].value;
 344         }
 345
 346         /* gfxclk dpm table setup */
 347         dpm_table = &dpm_context->dpm_tables.gfx_table;
 348         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
 349                 ret = smu_v11_0_set_single_dpm_table(smu,
 350                                                      SMU_GFXCLK,
 351                                                      dpm_table);
 352                 if (ret)
 353                         return ret;
 354                 dpm_table->is_fine_grained =
 355                         !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
 356         } else {
 357                 dpm_table->count = 1;
 358                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
 359                 dpm_table->dpm_levels[0].enabled = true;
 360                 dpm_table->min = dpm_table->dpm_levels[0].value;
 361                 dpm_table->max = dpm_table->dpm_levels[0].value;
 362         }
 363
 364         /* memclk dpm table setup */
 365         dpm_table = &dpm_context->dpm_tables.uclk_table;
 366         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
 367                 ret = smu_v11_0_set_single_dpm_table(smu,
 368                                                      SMU_UCLK,
 369                                                      dpm_table);
 370                 if (ret)
 371                         return ret;
 372                 dpm_table->is_fine_grained =
 373                         !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
 374         } else {
 375                 dpm_table->count = 1;
 376                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
 377                 dpm_table->dpm_levels[0].enabled = true;
 378                 dpm_table->min = dpm_table->dpm_levels[0].value;
 379                 dpm_table->max = dpm_table->dpm_levels[0].value;
 380         }
 381
 382         /* fclk dpm table setup */
 383         dpm_table = &dpm_context->dpm_tables.fclk_table;
 384         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT)) {
 385                 ret = smu_v11_0_set_single_dpm_table(smu,
 386                                                      SMU_FCLK,
 387                                                      dpm_table);
 388                 if (ret)
 389                         return ret;
 390                 dpm_table->is_fine_grained =
 391                         !driver_ppt->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete;
 392         } else {
 393                 dpm_table->count = 1;
 394                 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.fclk / 100;
 395                 dpm_table->dpm_levels[0].enabled = true;
 396                 dpm_table->min = dpm_table->dpm_levels[0].value;
 397                 dpm_table->max = dpm_table->dpm_levels[0].value;
 398         }
 399
 400         return 0;
 401 }
 402
 403 static void arcturus_check_bxco_support(struct smu_context *smu)
 404 {
 405         struct smu_table_context *table_context = &smu->smu_table;
 406         struct smu_11_0_powerplay_table *powerplay_table =
 407                 table_context->power_play_table;
 408         struct smu_baco_context *smu_baco = &smu->smu_baco;
 409         struct amdgpu_device *adev = smu->adev;
 410         uint32_t val;
 411
 412         if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
 413             powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) {
 414                 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
 415                 smu_baco->platform_support =
 416                         (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
 417                                                                         false;
 418         }
 419 }
 420
 421 static int arcturus_check_powerplay_table(struct smu_context *smu)
 422 {
 423         struct smu_table_context *table_context = &smu->smu_table;
 424         struct smu_11_0_powerplay_table *powerplay_table =
 425                 table_context->power_play_table;
 426
 427         arcturus_check_bxco_support(smu);
 428
 429         table_context->thermal_controller_type =
 430                 powerplay_table->thermal_controller_type;
 431
 432         return 0;
 433 }
 434
 435 static int arcturus_store_powerplay_table(struct smu_context *smu)
 436 {
 437         struct smu_table_context *table_context = &smu->smu_table;
 438         struct smu_11_0_powerplay_table *powerplay_table =
 439                 table_context->power_play_table;
 440
 441         memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
 442                sizeof(PPTable_t));
 443
 444         return 0;
 445 }
 446
 447 static int arcturus_append_powerplay_table(struct smu_context *smu)
 448 {
 449         struct smu_table_context *table_context = &smu->smu_table;
 450         PPTable_t *smc_pptable = table_context->driver_pptable;
 451         struct atom_smc_dpm_info_v4_6 *smc_dpm_table;
 452         int index, ret;
 453
 454         index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
 455                                            smc_dpm_info);
 456
 457         ret = amdgpu_atombios_get_data_table(smu->adev, index, NULL, NULL, NULL,
 458                                       (uint8_t **)&smc_dpm_table);
 459         if (ret)
 460                 return ret;
 461
 462         dev_info(smu->adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
 463                         smc_dpm_table->table_header.format_revision,
 464                         smc_dpm_table->table_header.content_revision);
 465
 466         if ((smc_dpm_table->table_header.format_revision == 4) &&
 467             (smc_dpm_table->table_header.content_revision == 6))
 468                 memcpy(&smc_pptable->MaxVoltageStepGfx,
 469                        &smc_dpm_table->maxvoltagestepgfx,
 470                        sizeof(*smc_dpm_table) - offsetof(struct atom_smc_dpm_info_v4_6, maxvoltagestepgfx));
 471
 472         return 0;
 473 }
 474
 475 static int arcturus_setup_pptable(struct smu_context *smu)
 476 {
 477         int ret = 0;
 478
 479         ret = smu_v11_0_setup_pptable(smu);
 480         if (ret)
 481                 return ret;
 482
 483         ret = arcturus_store_powerplay_table(smu);
 484         if (ret)
 485                 return ret;
 486
 487         ret = arcturus_append_powerplay_table(smu);
 488         if (ret)
 489                 return ret;
 490
 491         ret = arcturus_check_powerplay_table(smu);
 492         if (ret)
 493                 return ret;
 494
 495         return ret;
 496 }
 497
 498 static int arcturus_run_btc(struct smu_context *smu)
 499 {
 500         int ret = 0;
 501
 502         ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunAfllBtc, NULL);
 503         if (ret) {
 504                 dev_err(smu->adev->dev, "RunAfllBtc failed!\n");
 505                 return ret;
 506         }
 507
 508         return smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
 509 }
 510
 511 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
 512 {
 513         struct smu_11_0_dpm_context *dpm_context =
 514                                 smu->smu_dpm.dpm_context;
 515         struct smu_11_0_dpm_table *gfx_table =
 516                                 &dpm_context->dpm_tables.gfx_table;
 517         struct smu_11_0_dpm_table *mem_table =
 518                                 &dpm_context->dpm_tables.uclk_table;
 519         struct smu_11_0_dpm_table *soc_table =
 520                                 &dpm_context->dpm_tables.soc_table;
 521         struct smu_umd_pstate_table *pstate_table =
 522                                 &smu->pstate_table;
 523
 524         pstate_table->gfxclk_pstate.min = gfx_table->min;
 525         pstate_table->gfxclk_pstate.peak = gfx_table->max;
 526
 527         pstate_table->uclk_pstate.min = mem_table->min;
 528         pstate_table->uclk_pstate.peak = mem_table->max;
 529
 530         pstate_table->socclk_pstate.min = soc_table->min;
 531         pstate_table->socclk_pstate.peak = soc_table->max;
 532
 533         if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
 534             mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
 535             soc_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
 536                 pstate_table->gfxclk_pstate.standard =
 537                         gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
 538                 pstate_table->uclk_pstate.standard =
 539                         mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
 540                 pstate_table->socclk_pstate.standard =
 541                         soc_table->dpm_levels[ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL].value;
 542         } else {
 543                 pstate_table->gfxclk_pstate.standard =
 544                         pstate_table->gfxclk_pstate.min;
 545                 pstate_table->uclk_pstate.standard =
 546                         pstate_table->uclk_pstate.min;
 547                 pstate_table->socclk_pstate.standard =
 548                         pstate_table->socclk_pstate.min;
 549         }
 550
 551         return 0;
 552 }
 553
 554 static int arcturus_get_clk_table(struct smu_context *smu,
 555                         struct pp_clock_levels_with_latency *clocks,
 556                         struct smu_11_0_dpm_table *dpm_table)
 557 {
 558         int i, count;
 559
 560         count = (dpm_table->count > MAX_NUM_CLOCKS) ? MAX_NUM_CLOCKS : dpm_table->count;
 561         clocks->num_levels = count;
 562
 563         for (i = 0; i < count; i++) {
 564                 clocks->data[i].clocks_in_khz =
 565                         dpm_table->dpm_levels[i].value * 1000;
 566                 clocks->data[i].latency_in_us = 0;
 567         }
 568
 569         return 0;
 570 }
 571
 572 static int arcturus_freqs_in_same_level(int32_t frequency1,
 573                                         int32_t frequency2)
 574 {
 575         return (abs(frequency1 - frequency2) <= EPSILON);
 576 }
 577
 578 static int arcturus_get_smu_metrics_data(struct smu_context *smu,
 579                                          MetricsMember_t member,
 580                                          uint32_t *value)
 581 {
 582         struct smu_table_context *smu_table= &smu->smu_table;
 583         SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
 584         int ret = 0;
 585
 586         mutex_lock(&smu->metrics_lock);
 587
 588         ret = smu_cmn_get_metrics_table_locked(smu,
 589                                                NULL,
 590                                                false);
 591         if (ret) {
 592                 mutex_unlock(&smu->metrics_lock);
 593                 return ret;
 594         }
 595
 596         switch (member) {
 597         case METRICS_CURR_GFXCLK:
 598                 *value = metrics->CurrClock[PPCLK_GFXCLK];
 599                 break;
 600         case METRICS_CURR_SOCCLK:
 601                 *value = metrics->CurrClock[PPCLK_SOCCLK];
 602                 break;
 603         case METRICS_CURR_UCLK:
 604                 *value = metrics->CurrClock[PPCLK_UCLK];
 605                 break;
 606         case METRICS_CURR_VCLK:
 607                 *value = metrics->CurrClock[PPCLK_VCLK];
 608                 break;
 609         case METRICS_CURR_DCLK:
 610                 *value = metrics->CurrClock[PPCLK_DCLK];
 611                 break;
 612         case METRICS_CURR_FCLK:
 613                 *value = metrics->CurrClock[PPCLK_FCLK];
 614                 break;
 615         case METRICS_AVERAGE_GFXCLK:
 616                 *value = metrics->AverageGfxclkFrequency;
 617                 break;
 618         case METRICS_AVERAGE_SOCCLK:
 619                 *value = metrics->AverageSocclkFrequency;
 620                 break;
 621         case METRICS_AVERAGE_UCLK:
 622                 *value = metrics->AverageUclkFrequency;
 623                 break;
 624         case METRICS_AVERAGE_VCLK:
 625                 *value = metrics->AverageVclkFrequency;
 626                 break;
 627         case METRICS_AVERAGE_DCLK:
 628                 *value = metrics->AverageDclkFrequency;
 629                 break;
 630         case METRICS_AVERAGE_GFXACTIVITY:
 631                 *value = metrics->AverageGfxActivity;
 632                 break;
 633         case METRICS_AVERAGE_MEMACTIVITY:
 634                 *value = metrics->AverageUclkActivity;
 635                 break;
 636         case METRICS_AVERAGE_VCNACTIVITY:
 637                 *value = metrics->VcnActivityPercentage;
 638                 break;
 639         case METRICS_AVERAGE_SOCKETPOWER:
 640                 *value = metrics->AverageSocketPower << 8;
 641                 break;
 642         case METRICS_TEMPERATURE_EDGE:
 643                 *value = metrics->TemperatureEdge *
 644                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 645                 break;
 646         case METRICS_TEMPERATURE_HOTSPOT:
 647                 *value = metrics->TemperatureHotspot *
 648                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 649                 break;
 650         case METRICS_TEMPERATURE_MEM:
 651                 *value = metrics->TemperatureHBM *
 652                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 653                 break;
 654         case METRICS_TEMPERATURE_VRGFX:
 655                 *value = metrics->TemperatureVrGfx *
 656                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 657                 break;
 658         case METRICS_TEMPERATURE_VRSOC:
 659                 *value = metrics->TemperatureVrSoc *
 660                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 661                 break;
 662         case METRICS_TEMPERATURE_VRMEM:
 663                 *value = metrics->TemperatureVrMem *
 664                         SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
 665                 break;
 666         case METRICS_THROTTLER_STATUS:
 667                 *value = metrics->ThrottlerStatus;
 668                 break;
 669         case METRICS_CURR_FANSPEED:
 670                 *value = metrics->CurrFanSpeed;
 671                 break;
 672         default:
 673                 *value = UINT_MAX;
 674                 break;
 675         }
 676
 677         mutex_unlock(&smu->metrics_lock);
 678
 679         return ret;
 680 }
 681
 682 static int arcturus_get_current_clk_freq_by_table(struct smu_context *smu,
 683                                        enum smu_clk_type clk_type,
 684                                        uint32_t *value)
 685 {
 686         MetricsMember_t member_type;
 687         int clk_id = 0;
 688
 689         if (!value)
 690                 return -EINVAL;
 691
 692         clk_id = smu_cmn_to_asic_specific_index(smu,
 693                                                 CMN2ASIC_MAPPING_CLK,
 694                                                 clk_type);
 695         if (clk_id < 0)
 696                 return -EINVAL;
 697
 698         switch (clk_id) {
 699         case PPCLK_GFXCLK:
 700                 /*
 701                  * CurrClock[clk_id] can provide accurate
 702                  *   output only when the dpm feature is enabled.
 703                  * We can use Average_* for dpm disabled case.
 704                  *   But this is available for gfxclk/uclk/socclk/vclk/dclk.
 705                  */
 706                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT))
 707                         member_type = METRICS_CURR_GFXCLK;
 708                 else
 709                         member_type = METRICS_AVERAGE_GFXCLK;
 710                 break;
 711         case PPCLK_UCLK:
 712                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
 713                         member_type = METRICS_CURR_UCLK;
 714                 else
 715                         member_type = METRICS_AVERAGE_UCLK;
 716                 break;
 717         case PPCLK_SOCCLK:
 718                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT))
 719                         member_type = METRICS_CURR_SOCCLK;
 720                 else
 721                         member_type = METRICS_AVERAGE_SOCCLK;
 722                 break;
 723         case PPCLK_VCLK:
 724                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
 725                         member_type = METRICS_CURR_VCLK;
 726                 else
 727                         member_type = METRICS_AVERAGE_VCLK;
 728                 break;
 729         case PPCLK_DCLK:
 730                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT))
 731                         member_type = METRICS_CURR_DCLK;
 732                 else
 733                         member_type = METRICS_AVERAGE_DCLK;
 734                 break;
 735         case PPCLK_FCLK:
 736                 member_type = METRICS_CURR_FCLK;
 737                 break;
 738         default:
 739                 return -EINVAL;
 740         }
 741
 742         return arcturus_get_smu_metrics_data(smu,
 743                                              member_type,
 744                                              value);
 745 }
 746
 747 static int arcturus_print_clk_levels(struct smu_context *smu,
 748                         enum smu_clk_type type, char *buf)
 749 {
 750         int i, now, size = 0;
 751         int ret = 0;
 752         struct pp_clock_levels_with_latency clocks;
 753         struct smu_11_0_dpm_table *single_dpm_table;
 754         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
 755         struct smu_11_0_dpm_context *dpm_context = NULL;
 756         uint32_t gen_speed, lane_width;
 757
 758         if (amdgpu_ras_intr_triggered())
 759                 return snprintf(buf, PAGE_SIZE, "unavailable\n");
 760
 761         dpm_context = smu_dpm->dpm_context;
 762
 763         switch (type) {
 764         case SMU_SCLK:
 765                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, &now);
 766                 if (ret) {
 767                         dev_err(smu->adev->dev, "Attempt to get current gfx clk Failed!");
 768                         return ret;
 769                 }
 770
 771                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
 772                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 773                 if (ret) {
 774                         dev_err(smu->adev->dev, "Attempt to get gfx clk levels Failed!");
 775                         return ret;
 776                 }
 777
 778                 /*
 779                  * For DPM disabled case, there will be only one clock level.
 780                  * And it's safe to assume that is always the current clock.
 781                  */
 782                 for (i = 0; i < clocks.num_levels; i++)
 783                         size += sprintf(buf + size, "%d: %uMhz %s\n", i,
 784                                         clocks.data[i].clocks_in_khz / 1000,
 785                                         (clocks.num_levels == 1) ? "*" :
 786                                         (arcturus_freqs_in_same_level(
 787                                         clocks.data[i].clocks_in_khz / 1000,
 788                                         now) ? "*" : ""));
 789                 break;
 790
 791         case SMU_MCLK:
 792                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, &now);
 793                 if (ret) {
 794                         dev_err(smu->adev->dev, "Attempt to get current mclk Failed!");
 795                         return ret;
 796                 }
 797
 798                 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
 799                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 800                 if (ret) {
 801                         dev_err(smu->adev->dev, "Attempt to get memory clk levels Failed!");
 802                         return ret;
 803                 }
 804
 805                 for (i = 0; i < clocks.num_levels; i++)
 806                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 807                                 i, clocks.data[i].clocks_in_khz / 1000,
 808                                 (clocks.num_levels == 1) ? "*" :
 809                                 (arcturus_freqs_in_same_level(
 810                                 clocks.data[i].clocks_in_khz / 1000,
 811                                 now) ? "*" : ""));
 812                 break;
 813
 814         case SMU_SOCCLK:
 815                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_SOCCLK, &now);
 816                 if (ret) {
 817                         dev_err(smu->adev->dev, "Attempt to get current socclk Failed!");
 818                         return ret;
 819                 }
 820
 821                 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
 822                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 823                 if (ret) {
 824                         dev_err(smu->adev->dev, "Attempt to get socclk levels Failed!");
 825                         return ret;
 826                 }
 827
 828                 for (i = 0; i < clocks.num_levels; i++)
 829                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 830                                 i, clocks.data[i].clocks_in_khz / 1000,
 831                                 (clocks.num_levels == 1) ? "*" :
 832                                 (arcturus_freqs_in_same_level(
 833                                 clocks.data[i].clocks_in_khz / 1000,
 834                                 now) ? "*" : ""));
 835                 break;
 836
 837         case SMU_FCLK:
 838                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_FCLK, &now);
 839                 if (ret) {
 840                         dev_err(smu->adev->dev, "Attempt to get current fclk Failed!");
 841                         return ret;
 842                 }
 843
 844                 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
 845                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 846                 if (ret) {
 847                         dev_err(smu->adev->dev, "Attempt to get fclk levels Failed!");
 848                         return ret;
 849                 }
 850
 851                 for (i = 0; i < single_dpm_table->count; i++)
 852                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 853                                 i, single_dpm_table->dpm_levels[i].value,
 854                                 (clocks.num_levels == 1) ? "*" :
 855                                 (arcturus_freqs_in_same_level(
 856                                 clocks.data[i].clocks_in_khz / 1000,
 857                                 now) ? "*" : ""));
 858                 break;
 859
 860         case SMU_VCLK:
 861                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_VCLK, &now);
 862                 if (ret) {
 863                         dev_err(smu->adev->dev, "Attempt to get current vclk Failed!");
 864                         return ret;
 865                 }
 866
 867                 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
 868                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 869                 if (ret) {
 870                         dev_err(smu->adev->dev, "Attempt to get vclk levels Failed!");
 871                         return ret;
 872                 }
 873
 874                 for (i = 0; i < single_dpm_table->count; i++)
 875                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 876                                 i, single_dpm_table->dpm_levels[i].value,
 877                                 (clocks.num_levels == 1) ? "*" :
 878                                 (arcturus_freqs_in_same_level(
 879                                 clocks.data[i].clocks_in_khz / 1000,
 880                                 now) ? "*" : ""));
 881                 break;
 882
 883         case SMU_DCLK:
 884                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_DCLK, &now);
 885                 if (ret) {
 886                         dev_err(smu->adev->dev, "Attempt to get current dclk Failed!");
 887                         return ret;
 888                 }
 889
 890                 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
 891                 ret = arcturus_get_clk_table(smu, &clocks, single_dpm_table);
 892                 if (ret) {
 893                         dev_err(smu->adev->dev, "Attempt to get dclk levels Failed!");
 894                         return ret;
 895                 }
 896
 897                 for (i = 0; i < single_dpm_table->count; i++)
 898                         size += sprintf(buf + size, "%d: %uMhz %s\n",
 899                                 i, single_dpm_table->dpm_levels[i].value,
 900                                 (clocks.num_levels == 1) ? "*" :
 901                                 (arcturus_freqs_in_same_level(
 902                                 clocks.data[i].clocks_in_khz / 1000,
 903                                 now) ? "*" : ""));
 904                 break;
 905
 906         case SMU_PCIE:
 907                 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
 908                 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
 909                 size += sprintf(buf + size, "0: %s %s %dMhz *\n",
 910                                 (gen_speed == 0) ? "2.5GT/s," :
 911                                 (gen_speed == 1) ? "5.0GT/s," :
 912                                 (gen_speed == 2) ? "8.0GT/s," :
 913                                 (gen_speed == 3) ? "16.0GT/s," : "",
 914                                 (lane_width == 1) ? "x1" :
 915                                 (lane_width == 2) ? "x2" :
 916                                 (lane_width == 3) ? "x4" :
 917                                 (lane_width == 4) ? "x8" :
 918                                 (lane_width == 5) ? "x12" :
 919                                 (lane_width == 6) ? "x16" : "",
 920                                 smu->smu_table.boot_values.lclk / 100);
 921                 break;
 922
 923         default:
 924                 break;
 925         }
 926
 927         return size;
 928 }
 929
 930 static int arcturus_upload_dpm_level(struct smu_context *smu,
 931                                      bool max,
 932                                      uint32_t feature_mask,
 933                                      uint32_t level)
 934 {
 935         struct smu_11_0_dpm_context *dpm_context =
 936                         smu->smu_dpm.dpm_context;
 937         uint32_t freq;
 938         int ret = 0;
 939
 940         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
 941             (feature_mask & FEATURE_DPM_GFXCLK_MASK)) {
 942                 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
 943                 ret = smu_cmn_send_smc_msg_with_param(smu,
 944                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 945                         (PPCLK_GFXCLK << 16) | (freq & 0xffff),
 946                         NULL);
 947                 if (ret) {
 948                         dev_err(smu->adev->dev, "Failed to set soft %s gfxclk !\n",
 949                                                 max ? "max" : "min");
 950                         return ret;
 951                 }
 952         }
 953
 954         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
 955             (feature_mask & FEATURE_DPM_UCLK_MASK)) {
 956                 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level].value;
 957                 ret = smu_cmn_send_smc_msg_with_param(smu,
 958                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 959                         (PPCLK_UCLK << 16) | (freq & 0xffff),
 960                         NULL);
 961                 if (ret) {
 962                         dev_err(smu->adev->dev, "Failed to set soft %s memclk !\n",
 963                                                 max ? "max" : "min");
 964                         return ret;
 965                 }
 966         }
 967
 968         if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
 969             (feature_mask & FEATURE_DPM_SOCCLK_MASK)) {
 970                 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
 971                 ret = smu_cmn_send_smc_msg_with_param(smu,
 972                         (max ? SMU_MSG_SetSoftMaxByFreq : SMU_MSG_SetSoftMinByFreq),
 973                         (PPCLK_SOCCLK << 16) | (freq & 0xffff),
 974                         NULL);
 975                 if (ret) {
 976                         dev_err(smu->adev->dev, "Failed to set soft %s socclk !\n",
 977                                                 max ? "max" : "min");
 978                         return ret;
 979                 }
 980         }
 981
 982         return ret;
 983 }
 984
 985 static int arcturus_force_clk_levels(struct smu_context *smu,
 986                         enum smu_clk_type type, uint32_t mask)
 987 {
 988         struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
 989         struct smu_11_0_dpm_table *single_dpm_table = NULL;
 990         uint32_t soft_min_level, soft_max_level;
 991         uint32_t smu_version;
 992         int ret = 0;
 993
 994         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
 995         if (ret) {
 996                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
 997                 return ret;
 998         }
 999
1000         if ((smu_version >= 0x361200) &&
1001             (smu_version <= 0x361a00)) {
1002                 dev_err(smu->adev->dev, "Forcing clock level is not supported with "
1003                        "54.18 - 54.26(included) SMU firmwares\n");
1004                 return -EOPNOTSUPP;
1005         }
1006
1007         soft_min_level = mask ? (ffs(mask) - 1) : 0;
1008         soft_max_level = mask ? (fls(mask) - 1) : 0;
1009
1010         switch (type) {
1011         case SMU_SCLK:
1012                 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1013                 if (soft_max_level >= single_dpm_table->count) {
1014                         dev_err(smu->adev->dev, "Clock level specified %d is over max allowed %d\n",
1015                                         soft_max_level, single_dpm_table->count - 1);
1016                         ret = -EINVAL;
1017                         break;
1018                 }
1019
1020                 ret = arcturus_upload_dpm_level(smu,
1021                                                 false,
1022                                                 FEATURE_DPM_GFXCLK_MASK,
1023                                                 soft_min_level);
1024                 if (ret) {
1025                         dev_err(smu->adev->dev, "Failed to upload boot level to lowest!\n");
1026                         break;
1027                 }
1028
1029                 ret = arcturus_upload_dpm_level(smu,
1030                                                 true,
1031                                                 FEATURE_DPM_GFXCLK_MASK,
1032                                                 soft_max_level);
1033                 if (ret)
1034                         dev_err(smu->adev->dev, "Failed to upload dpm max level to highest!\n");
1035
1036                 break;
1037
1038         case SMU_MCLK:
1039         case SMU_SOCCLK:
1040         case SMU_FCLK:
1041                 /*
1042                  * Should not arrive here since Arcturus does not
1043                  * support mclk/socclk/fclk softmin/softmax settings
1044                  */
1045                 ret = -EINVAL;
1046                 break;
1047
1048         default:
1049                 break;
1050         }
1051
1052         return ret;
1053 }
1054
1055 static int arcturus_get_thermal_temperature_range(struct smu_context *smu,
1056                                                 struct smu_temperature_range *range)
1057 {
1058         struct smu_table_context *table_context = &smu->smu_table;
1059         struct smu_11_0_powerplay_table *powerplay_table =
1060                                 table_context->power_play_table;
1061         PPTable_t *pptable = smu->smu_table.driver_pptable;
1062
1063         if (!range)
1064                 return -EINVAL;
1065
1066         memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
1067
1068         range->max = pptable->TedgeLimit *
1069                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1070         range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
1071                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1072         range->hotspot_crit_max = pptable->ThotspotLimit *
1073                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1074         range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
1075                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1076         range->mem_crit_max = pptable->TmemLimit *
1077                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1078         range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
1079                 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1080         range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
1081
1082         return 0;
1083 }
1084
1085 static int arcturus_read_sensor(struct smu_context *smu,
1086                                 enum amd_pp_sensors sensor,
1087                                 void *data, uint32_t *size)
1088 {
1089         struct smu_table_context *table_context = &smu->smu_table;
1090         PPTable_t *pptable = table_context->driver_pptable;
1091         int ret = 0;
1092
1093         if (amdgpu_ras_intr_triggered())
1094                 return 0;
1095
1096         if (!data || !size)
1097                 return -EINVAL;
1098
1099         mutex_lock(&smu->sensor_lock);
1100         switch (sensor) {
1101         case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
1102                 *(uint32_t *)data = pptable->FanMaximumRpm;
1103                 *size = 4;
1104                 break;
1105         case AMDGPU_PP_SENSOR_MEM_LOAD:
1106                 ret = arcturus_get_smu_metrics_data(smu,
1107                                                     METRICS_AVERAGE_MEMACTIVITY,
1108                                                     (uint32_t *)data);
1109                 *size = 4;
1110                 break;
1111         case AMDGPU_PP_SENSOR_GPU_LOAD:
1112                 ret = arcturus_get_smu_metrics_data(smu,
1113                                                     METRICS_AVERAGE_GFXACTIVITY,
1114                                                     (uint32_t *)data);
1115                 *size = 4;
1116                 break;
1117         case AMDGPU_PP_SENSOR_GPU_POWER:
1118                 ret = arcturus_get_smu_metrics_data(smu,
1119                                                     METRICS_AVERAGE_SOCKETPOWER,
1120                                                     (uint32_t *)data);
1121                 *size = 4;
1122                 break;
1123         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1124                 ret = arcturus_get_smu_metrics_data(smu,
1125                                                     METRICS_TEMPERATURE_HOTSPOT,
1126                                                     (uint32_t *)data);
1127                 *size = 4;
1128                 break;
1129         case AMDGPU_PP_SENSOR_EDGE_TEMP:
1130                 ret = arcturus_get_smu_metrics_data(smu,
1131                                                     METRICS_TEMPERATURE_EDGE,
1132                                                     (uint32_t *)data);
1133                 *size = 4;
1134                 break;
1135         case AMDGPU_PP_SENSOR_MEM_TEMP:
1136                 ret = arcturus_get_smu_metrics_data(smu,
1137                                                     METRICS_TEMPERATURE_MEM,
1138                                                     (uint32_t *)data);
1139                 *size = 4;
1140                 break;
1141         case AMDGPU_PP_SENSOR_GFX_MCLK:
1142                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
1143                 /* the output clock frequency in 10K unit */
1144                 *(uint32_t *)data *= 100;
1145                 *size = 4;
1146                 break;
1147         case AMDGPU_PP_SENSOR_GFX_SCLK:
1148                 ret = arcturus_get_current_clk_freq_by_table(smu, SMU_GFXCLK, (uint32_t *)data);
1149                 *(uint32_t *)data *= 100;
1150                 *size = 4;
1151                 break;
1152         case AMDGPU_PP_SENSOR_VDDGFX:
1153                 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
1154                 *size = 4;
1155                 break;
1156         default:
1157                 ret = -EOPNOTSUPP;
1158                 break;
1159         }
1160         mutex_unlock(&smu->sensor_lock);
1161
1162         return ret;
1163 }
1164
1165 static int arcturus_get_fan_speed_percent(struct smu_context *smu,
1166                                           uint32_t *speed)
1167 {
1168         int ret;
1169         u32 rpm;
1170
1171         if (!speed)
1172                 return -EINVAL;
1173
1174         switch (smu_v11_0_get_fan_control_mode(smu)) {
1175         case AMD_FAN_CTRL_AUTO:
1176                 ret = arcturus_get_smu_metrics_data(smu,
1177                                                     METRICS_CURR_FANSPEED,
1178                                                     &rpm);
1179                 if (!ret && smu->fan_max_rpm)
1180                         *speed = rpm * 100 / smu->fan_max_rpm;
1181                 return ret;
1182         default:
1183                 *speed = smu->user_dpm_profile.fan_speed_percent;
1184                 return 0;
1185         }
1186 }
1187
1188 static int arcturus_get_fan_parameters(struct smu_context *smu)
1189 {
1190         PPTable_t *pptable = smu->smu_table.driver_pptable;
1191
1192         smu->fan_max_rpm = pptable->FanMaximumRpm;
1193
1194         return 0;
1195 }
1196
1197 static int arcturus_get_power_limit(struct smu_context *smu,
1198                                     uint32_t *current_power_limit,
1199                                     uint32_t *default_power_limit,
1200                                     uint32_t *max_power_limit)
1201 {
1202         struct smu_11_0_powerplay_table *powerplay_table =
1203                 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
1204         PPTable_t *pptable = smu->smu_table.driver_pptable;
1205         uint32_t power_limit, od_percent;
1206
1207         if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
1208                 /* the last hope to figure out the ppt limit */
1209                 if (!pptable) {
1210                         dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
1211                         return -EINVAL;
1212                 }
1213                 power_limit =
1214                         pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
1215         }
1216
1217         if (current_power_limit)
1218                 *current_power_limit = power_limit;
1219         if (default_power_limit)
1220                 *default_power_limit = power_limit;
1221
1222         if (max_power_limit) {
1223                 if (smu->od_enabled) {
1224                         od_percent = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
1225
1226                         dev_dbg(smu->adev->dev, "ODSETTING_POWERPERCENTAGE: %d (default: %d)\n", od_percent, power_limit);
1227
1228                         power_limit *= (100 + od_percent);
1229                         power_limit /= 100;
1230                 }
1231
1232                 *max_power_limit = power_limit;
1233         }
1234
1235         return 0;
1236 }
1237
1238 static int arcturus_get_power_profile_mode(struct smu_context *smu,
1239                                            char *buf)
1240 {
1241         DpmActivityMonitorCoeffInt_t activity_monitor;
1242         static const char *profile_name[] = {
1243                                         "BOOTUP_DEFAULT",
1244                                         "3D_FULL_SCREEN",
1245                                         "POWER_SAVING",
1246                                         "VIDEO",
1247                                         "VR",
1248                                         "COMPUTE",
1249                                         "CUSTOM"};
1250         static const char *title[] = {
1251                         "PROFILE_INDEX(NAME)",
1252                         "CLOCK_TYPE(NAME)",
1253                         "FPS",
1254                         "UseRlcBusy",
1255                         "MinActiveFreqType",
1256                         "MinActiveFreq",
1257                         "BoosterFreqType",
1258                         "BoosterFreq",
1259                         "PD_Data_limit_c",
1260                         "PD_Data_error_coeff",
1261                         "PD_Data_error_rate_coeff"};
1262         uint32_t i, size = 0;
1263         int16_t workload_type = 0;
1264         int result = 0;
1265         uint32_t smu_version;
1266
1267         if (!buf)
1268                 return -EINVAL;
1269
1270         result = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1271         if (result)
1272                 return result;
1273
1274         if (smu_version >= 0x360d00)
1275                 size += sprintf(buf + size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1276                         title[0], title[1], title[2], title[3], title[4], title[5],
1277                         title[6], title[7], title[8], title[9], title[10]);
1278         else
1279                 size += sprintf(buf + size, "%16s\n",
1280                         title[0]);
1281
1282         for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1283                 /*
1284                  * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1285                  * Not all profile modes are supported on arcturus.
1286                  */
1287                 workload_type = smu_cmn_to_asic_specific_index(smu,
1288                                                                CMN2ASIC_MAPPING_WORKLOAD,
1289                                                                i);
1290                 if (workload_type < 0)
1291                         continue;
1292
1293                 if (smu_version >= 0x360d00) {
1294                         result = smu_cmn_update_table(smu,
1295                                                   SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1296                                                   workload_type,
1297                                                   (void *)(&activity_monitor),
1298                                                   false);
1299                         if (result) {
1300                                 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1301                                 return result;
1302                         }
1303                 }
1304
1305                 size += sprintf(buf + size, "%2d %14s%s\n",
1306                         i, profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1307
1308                 if (smu_version >= 0x360d00) {
1309                         size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1310                                 " ",
1311                                 0,
1312                                 "GFXCLK",
1313                                 activity_monitor.Gfx_FPS,
1314                                 activity_monitor.Gfx_UseRlcBusy,
1315                                 activity_monitor.Gfx_MinActiveFreqType,
1316                                 activity_monitor.Gfx_MinActiveFreq,
1317                                 activity_monitor.Gfx_BoosterFreqType,
1318                                 activity_monitor.Gfx_BoosterFreq,
1319                                 activity_monitor.Gfx_PD_Data_limit_c,
1320                                 activity_monitor.Gfx_PD_Data_error_coeff,
1321                                 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1322
1323                         size += sprintf(buf + size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1324                                 " ",
1325                                 1,
1326                                 "UCLK",
1327                                 activity_monitor.Mem_FPS,
1328                                 activity_monitor.Mem_UseRlcBusy,
1329                                 activity_monitor.Mem_MinActiveFreqType,
1330                                 activity_monitor.Mem_MinActiveFreq,
1331                                 activity_monitor.Mem_BoosterFreqType,
1332                                 activity_monitor.Mem_BoosterFreq,
1333                                 activity_monitor.Mem_PD_Data_limit_c,
1334                                 activity_monitor.Mem_PD_Data_error_coeff,
1335                                 activity_monitor.Mem_PD_Data_error_rate_coeff);
1336                 }
1337         }
1338
1339         return size;
1340 }
1341
1342 static int arcturus_set_power_profile_mode(struct smu_context *smu,
1343                                            long *input,
1344                                            uint32_t size)
1345 {
1346         DpmActivityMonitorCoeffInt_t activity_monitor;
1347         int workload_type = 0;
1348         uint32_t profile_mode = input[size];
1349         int ret = 0;
1350         uint32_t smu_version;
1351
1352         if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
1353                 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
1354                 return -EINVAL;
1355         }
1356
1357         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1358         if (ret)
1359                 return ret;
1360
1361         if ((profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) &&
1362              (smu_version >=0x360d00)) {
1363                 ret = smu_cmn_update_table(smu,
1364                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1365                                        WORKLOAD_PPLIB_CUSTOM_BIT,
1366                                        (void *)(&activity_monitor),
1367                                        false);
1368                 if (ret) {
1369                         dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1370                         return ret;
1371                 }
1372
1373                 switch (input[0]) {
1374                 case 0: /* Gfxclk */
1375                         activity_monitor.Gfx_FPS = input[1];
1376                         activity_monitor.Gfx_UseRlcBusy = input[2];
1377                         activity_monitor.Gfx_MinActiveFreqType = input[3];
1378                         activity_monitor.Gfx_MinActiveFreq = input[4];
1379                         activity_monitor.Gfx_BoosterFreqType = input[5];
1380                         activity_monitor.Gfx_BoosterFreq = input[6];
1381                         activity_monitor.Gfx_PD_Data_limit_c = input[7];
1382                         activity_monitor.Gfx_PD_Data_error_coeff = input[8];
1383                         activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
1384                         break;
1385                 case 1: /* Uclk */
1386                         activity_monitor.Mem_FPS = input[1];
1387                         activity_monitor.Mem_UseRlcBusy = input[2];
1388                         activity_monitor.Mem_MinActiveFreqType = input[3];
1389                         activity_monitor.Mem_MinActiveFreq = input[4];
1390                         activity_monitor.Mem_BoosterFreqType = input[5];
1391                         activity_monitor.Mem_BoosterFreq = input[6];
1392                         activity_monitor.Mem_PD_Data_limit_c = input[7];
1393                         activity_monitor.Mem_PD_Data_error_coeff = input[8];
1394                         activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
1395                         break;
1396                 }
1397
1398                 ret = smu_cmn_update_table(smu,
1399                                        SMU_TABLE_ACTIVITY_MONITOR_COEFF,
1400                                        WORKLOAD_PPLIB_CUSTOM_BIT,
1401                                        (void *)(&activity_monitor),
1402                                        true);
1403                 if (ret) {
1404                         dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
1405                         return ret;
1406                 }
1407         }
1408
1409         /*
1410          * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1411          * Not all profile modes are supported on arcturus.
1412          */
1413         workload_type = smu_cmn_to_asic_specific_index(smu,
1414                                                        CMN2ASIC_MAPPING_WORKLOAD,
1415                                                        profile_mode);
1416         if (workload_type < 0) {
1417                 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on arcturus\n", profile_mode);
1418                 return -EINVAL;
1419         }
1420
1421         ret = smu_cmn_send_smc_msg_with_param(smu,
1422                                           SMU_MSG_SetWorkloadMask,
1423                                           1 << workload_type,
1424                                           NULL);
1425         if (ret) {
1426                 dev_err(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
1427                 return ret;
1428         }
1429
1430         smu->power_profile_mode = profile_mode;
1431
1432         return 0;
1433 }
1434
1435 static int arcturus_set_performance_level(struct smu_context *smu,
1436                                           enum amd_dpm_forced_level level)
1437 {
1438         uint32_t smu_version;
1439         int ret;
1440
1441         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
1442         if (ret) {
1443                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
1444                 return ret;
1445         }
1446
1447         switch (level) {
1448         case AMD_DPM_FORCED_LEVEL_HIGH:
1449         case AMD_DPM_FORCED_LEVEL_LOW:
1450         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1451         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1452         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1453         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1454                 if ((smu_version >= 0x361200) &&
1455                     (smu_version <= 0x361a00)) {
1456                         dev_err(smu->adev->dev, "Forcing clock level is not supported with "
1457                                "54.18 - 54.26(included) SMU firmwares\n");
1458                         return -EOPNOTSUPP;
1459                 }
1460                 break;
1461         default:
1462                 break;
1463         }
1464
1465         return smu_v11_0_set_performance_level(smu, level);
1466 }
1467
1468 static void arcturus_dump_pptable(struct smu_context *smu)
1469 {
1470         struct smu_table_context *table_context = &smu->smu_table;
1471         PPTable_t *pptable = table_context->driver_pptable;
1472         int i;
1473
1474         dev_info(smu->adev->dev, "Dumped PPTable:\n");
1475
1476         dev_info(smu->adev->dev, "Version = 0x%08x\n", pptable->Version);
1477
1478         dev_info(smu->adev->dev, "FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
1479         dev_info(smu->adev->dev, "FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
1480
1481         for (i = 0; i < PPT_THROTTLER_COUNT; i++) {
1482                 dev_info(smu->adev->dev, "SocketPowerLimitAc[%d] = %d\n", i, pptable->SocketPowerLimitAc[i]);
1483                 dev_info(smu->adev->dev, "SocketPowerLimitAcTau[%d] = %d\n", i, pptable->SocketPowerLimitAcTau[i]);
1484         }
1485
1486         dev_info(smu->adev->dev, "TdcLimitSoc = %d\n", pptable->TdcLimitSoc);
1487         dev_info(smu->adev->dev, "TdcLimitSocTau = %d\n", pptable->TdcLimitSocTau);
1488         dev_info(smu->adev->dev, "TdcLimitGfx = %d\n", pptable->TdcLimitGfx);
1489         dev_info(smu->adev->dev, "TdcLimitGfxTau = %d\n", pptable->TdcLimitGfxTau);
1490
1491         dev_info(smu->adev->dev, "TedgeLimit = %d\n", pptable->TedgeLimit);
1492         dev_info(smu->adev->dev, "ThotspotLimit = %d\n", pptable->ThotspotLimit);
1493         dev_info(smu->adev->dev, "TmemLimit = %d\n", pptable->TmemLimit);
1494         dev_info(smu->adev->dev, "Tvr_gfxLimit = %d\n", pptable->Tvr_gfxLimit);
1495         dev_info(smu->adev->dev, "Tvr_memLimit = %d\n", pptable->Tvr_memLimit);
1496         dev_info(smu->adev->dev, "Tvr_socLimit = %d\n", pptable->Tvr_socLimit);
1497         dev_info(smu->adev->dev, "FitLimit = %d\n", pptable->FitLimit);
1498
1499         dev_info(smu->adev->dev, "PpmPowerLimit = %d\n", pptable->PpmPowerLimit);
1500         dev_info(smu->adev->dev, "PpmTemperatureThreshold = %d\n", pptable->PpmTemperatureThreshold);
1501
1502         dev_info(smu->adev->dev, "ThrottlerControlMask = %d\n", pptable->ThrottlerControlMask);
1503
1504         dev_info(smu->adev->dev, "UlvVoltageOffsetGfx = %d\n", pptable->UlvVoltageOffsetGfx);
1505         dev_info(smu->adev->dev, "UlvPadding = 0x%08x\n", pptable->UlvPadding);
1506
1507         dev_info(smu->adev->dev, "UlvGfxclkBypass = %d\n", pptable->UlvGfxclkBypass);
1508         dev_info(smu->adev->dev, "Padding234[0] = 0x%02x\n", pptable->Padding234[0]);
1509         dev_info(smu->adev->dev, "Padding234[1] = 0x%02x\n", pptable->Padding234[1]);
1510         dev_info(smu->adev->dev, "Padding234[2] = 0x%02x\n", pptable->Padding234[2]);
1511
1512         dev_info(smu->adev->dev, "MinVoltageGfx = %d\n", pptable->MinVoltageGfx);
1513         dev_info(smu->adev->dev, "MinVoltageSoc = %d\n", pptable->MinVoltageSoc);
1514         dev_info(smu->adev->dev, "MaxVoltageGfx = %d\n", pptable->MaxVoltageGfx);
1515         dev_info(smu->adev->dev, "MaxVoltageSoc = %d\n", pptable->MaxVoltageSoc);
1516
1517         dev_info(smu->adev->dev, "LoadLineResistanceGfx = %d\n", pptable->LoadLineResistanceGfx);
1518         dev_info(smu->adev->dev, "LoadLineResistanceSoc = %d\n", pptable->LoadLineResistanceSoc);
1519
1520         dev_info(smu->adev->dev, "[PPCLK_GFXCLK]\n"
1521                         "  .VoltageMode          = 0x%02x\n"
1522                         "  .SnapToDiscrete       = 0x%02x\n"
1523                         "  .NumDiscreteLevels    = 0x%02x\n"
1524                         "  .padding              = 0x%02x\n"
1525                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1526                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1527                         "  .SsFmin               = 0x%04x\n"
1528                         "  .Padding_16           = 0x%04x\n",
1529                         pptable->DpmDescriptor[PPCLK_GFXCLK].VoltageMode,
1530                         pptable->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete,
1531                         pptable->DpmDescriptor[PPCLK_GFXCLK].NumDiscreteLevels,
1532                         pptable->DpmDescriptor[PPCLK_GFXCLK].padding,
1533                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.m,
1534                         pptable->DpmDescriptor[PPCLK_GFXCLK].ConversionToAvfsClk.b,
1535                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.a,
1536                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.b,
1537                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsCurve.c,
1538                         pptable->DpmDescriptor[PPCLK_GFXCLK].SsFmin,
1539                         pptable->DpmDescriptor[PPCLK_GFXCLK].Padding16);
1540
1541         dev_info(smu->adev->dev, "[PPCLK_VCLK]\n"
1542                         "  .VoltageMode          = 0x%02x\n"
1543                         "  .SnapToDiscrete       = 0x%02x\n"
1544                         "  .NumDiscreteLevels    = 0x%02x\n"
1545                         "  .padding              = 0x%02x\n"
1546                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1547                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1548                         "  .SsFmin               = 0x%04x\n"
1549                         "  .Padding_16           = 0x%04x\n",
1550                         pptable->DpmDescriptor[PPCLK_VCLK].VoltageMode,
1551                         pptable->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete,
1552                         pptable->DpmDescriptor[PPCLK_VCLK].NumDiscreteLevels,
1553                         pptable->DpmDescriptor[PPCLK_VCLK].padding,
1554                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.m,
1555                         pptable->DpmDescriptor[PPCLK_VCLK].ConversionToAvfsClk.b,
1556                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.a,
1557                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.b,
1558                         pptable->DpmDescriptor[PPCLK_VCLK].SsCurve.c,
1559                         pptable->DpmDescriptor[PPCLK_VCLK].SsFmin,
1560                         pptable->DpmDescriptor[PPCLK_VCLK].Padding16);
1561
1562         dev_info(smu->adev->dev, "[PPCLK_DCLK]\n"
1563                         "  .VoltageMode          = 0x%02x\n"
1564                         "  .SnapToDiscrete       = 0x%02x\n"
1565                         "  .NumDiscreteLevels    = 0x%02x\n"
1566                         "  .padding              = 0x%02x\n"
1567                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1568                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1569                         "  .SsFmin               = 0x%04x\n"
1570                         "  .Padding_16           = 0x%04x\n",
1571                         pptable->DpmDescriptor[PPCLK_DCLK].VoltageMode,
1572                         pptable->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete,
1573                         pptable->DpmDescriptor[PPCLK_DCLK].NumDiscreteLevels,
1574                         pptable->DpmDescriptor[PPCLK_DCLK].padding,
1575                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.m,
1576                         pptable->DpmDescriptor[PPCLK_DCLK].ConversionToAvfsClk.b,
1577                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.a,
1578                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.b,
1579                         pptable->DpmDescriptor[PPCLK_DCLK].SsCurve.c,
1580                         pptable->DpmDescriptor[PPCLK_DCLK].SsFmin,
1581                         pptable->DpmDescriptor[PPCLK_DCLK].Padding16);
1582
1583         dev_info(smu->adev->dev, "[PPCLK_SOCCLK]\n"
1584                         "  .VoltageMode          = 0x%02x\n"
1585                         "  .SnapToDiscrete       = 0x%02x\n"
1586                         "  .NumDiscreteLevels    = 0x%02x\n"
1587                         "  .padding              = 0x%02x\n"
1588                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1589                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1590                         "  .SsFmin               = 0x%04x\n"
1591                         "  .Padding_16           = 0x%04x\n",
1592                         pptable->DpmDescriptor[PPCLK_SOCCLK].VoltageMode,
1593                         pptable->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete,
1594                         pptable->DpmDescriptor[PPCLK_SOCCLK].NumDiscreteLevels,
1595                         pptable->DpmDescriptor[PPCLK_SOCCLK].padding,
1596                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.m,
1597                         pptable->DpmDescriptor[PPCLK_SOCCLK].ConversionToAvfsClk.b,
1598                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.a,
1599                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.b,
1600                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsCurve.c,
1601                         pptable->DpmDescriptor[PPCLK_SOCCLK].SsFmin,
1602                         pptable->DpmDescriptor[PPCLK_SOCCLK].Padding16);
1603
1604         dev_info(smu->adev->dev, "[PPCLK_UCLK]\n"
1605                         "  .VoltageMode          = 0x%02x\n"
1606                         "  .SnapToDiscrete       = 0x%02x\n"
1607                         "  .NumDiscreteLevels    = 0x%02x\n"
1608                         "  .padding              = 0x%02x\n"
1609                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1610                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1611                         "  .SsFmin               = 0x%04x\n"
1612                         "  .Padding_16           = 0x%04x\n",
1613                         pptable->DpmDescriptor[PPCLK_UCLK].VoltageMode,
1614                         pptable->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete,
1615                         pptable->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels,
1616                         pptable->DpmDescriptor[PPCLK_UCLK].padding,
1617                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.m,
1618                         pptable->DpmDescriptor[PPCLK_UCLK].ConversionToAvfsClk.b,
1619                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.a,
1620                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.b,
1621                         pptable->DpmDescriptor[PPCLK_UCLK].SsCurve.c,
1622                         pptable->DpmDescriptor[PPCLK_UCLK].SsFmin,
1623                         pptable->DpmDescriptor[PPCLK_UCLK].Padding16);
1624
1625         dev_info(smu->adev->dev, "[PPCLK_FCLK]\n"
1626                         "  .VoltageMode          = 0x%02x\n"
1627                         "  .SnapToDiscrete       = 0x%02x\n"
1628                         "  .NumDiscreteLevels    = 0x%02x\n"
1629                         "  .padding              = 0x%02x\n"
1630                         "  .ConversionToAvfsClk{m = 0x%08x b = 0x%08x}\n"
1631                         "  .SsCurve            {a = 0x%08x b = 0x%08x c = 0x%08x}\n"
1632                         "  .SsFmin               = 0x%04x\n"
1633                         "  .Padding_16           = 0x%04x\n",
1634                         pptable->DpmDescriptor[PPCLK_FCLK].VoltageMode,
1635                         pptable->DpmDescriptor[PPCLK_FCLK].SnapToDiscrete,
1636                         pptable->DpmDescriptor[PPCLK_FCLK].NumDiscreteLevels,
1637                         pptable->DpmDescriptor[PPCLK_FCLK].padding,
1638                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.m,
1639                         pptable->DpmDescriptor[PPCLK_FCLK].ConversionToAvfsClk.b,
1640                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.a,
1641                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.b,
1642                         pptable->DpmDescriptor[PPCLK_FCLK].SsCurve.c,
1643                         pptable->DpmDescriptor[PPCLK_FCLK].SsFmin,
1644                         pptable->DpmDescriptor[PPCLK_FCLK].Padding16);
1645
1646
1647         dev_info(smu->adev->dev, "FreqTableGfx\n");
1648         for (i = 0; i < NUM_GFXCLK_DPM_LEVELS; i++)
1649                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableGfx[i]);
1650
1651         dev_info(smu->adev->dev, "FreqTableVclk\n");
1652         for (i = 0; i < NUM_VCLK_DPM_LEVELS; i++)
1653                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableVclk[i]);
1654
1655         dev_info(smu->adev->dev, "FreqTableDclk\n");
1656         for (i = 0; i < NUM_DCLK_DPM_LEVELS; i++)
1657                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableDclk[i]);
1658
1659         dev_info(smu->adev->dev, "FreqTableSocclk\n");
1660         for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++)
1661                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableSocclk[i]);
1662
1663         dev_info(smu->adev->dev, "FreqTableUclk\n");
1664         for (i = 0; i < NUM_UCLK_DPM_LEVELS; i++)
1665                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableUclk[i]);
1666
1667         dev_info(smu->adev->dev, "FreqTableFclk\n");
1668         for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++)
1669                 dev_info(smu->adev->dev, "  .[%02d] = %d\n", i, pptable->FreqTableFclk[i]);
1670
1671         dev_info(smu->adev->dev, "Mp0clkFreq\n");
1672         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1673                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->Mp0clkFreq[i]);
1674
1675         dev_info(smu->adev->dev, "Mp0DpmVoltage\n");
1676         for (i = 0; i < NUM_MP0CLK_DPM_LEVELS; i++)
1677                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->Mp0DpmVoltage[i]);
1678
1679         dev_info(smu->adev->dev, "GfxclkFidle = 0x%x\n", pptable->GfxclkFidle);
1680         dev_info(smu->adev->dev, "GfxclkSlewRate = 0x%x\n", pptable->GfxclkSlewRate);
1681         dev_info(smu->adev->dev, "Padding567[0] = 0x%x\n", pptable->Padding567[0]);
1682         dev_info(smu->adev->dev, "Padding567[1] = 0x%x\n", pptable->Padding567[1]);
1683         dev_info(smu->adev->dev, "Padding567[2] = 0x%x\n", pptable->Padding567[2]);
1684         dev_info(smu->adev->dev, "Padding567[3] = 0x%x\n", pptable->Padding567[3]);
1685         dev_info(smu->adev->dev, "GfxclkDsMaxFreq = %d\n", pptable->GfxclkDsMaxFreq);
1686         dev_info(smu->adev->dev, "GfxclkSource = 0x%x\n", pptable->GfxclkSource);
1687         dev_info(smu->adev->dev, "Padding456 = 0x%x\n", pptable->Padding456);
1688
1689         dev_info(smu->adev->dev, "EnableTdpm = %d\n", pptable->EnableTdpm);
1690         dev_info(smu->adev->dev, "TdpmHighHystTemperature = %d\n", pptable->TdpmHighHystTemperature);
1691         dev_info(smu->adev->dev, "TdpmLowHystTemperature = %d\n", pptable->TdpmLowHystTemperature);
1692         dev_info(smu->adev->dev, "GfxclkFreqHighTempLimit = %d\n", pptable->GfxclkFreqHighTempLimit);
1693
1694         dev_info(smu->adev->dev, "FanStopTemp = %d\n", pptable->FanStopTemp);
1695         dev_info(smu->adev->dev, "FanStartTemp = %d\n", pptable->FanStartTemp);
1696
1697         dev_info(smu->adev->dev, "FanGainEdge = %d\n", pptable->FanGainEdge);
1698         dev_info(smu->adev->dev, "FanGainHotspot = %d\n", pptable->FanGainHotspot);
1699         dev_info(smu->adev->dev, "FanGainVrGfx = %d\n", pptable->FanGainVrGfx);
1700         dev_info(smu->adev->dev, "FanGainVrSoc = %d\n", pptable->FanGainVrSoc);
1701         dev_info(smu->adev->dev, "FanGainVrMem = %d\n", pptable->FanGainVrMem);
1702         dev_info(smu->adev->dev, "FanGainHbm = %d\n", pptable->FanGainHbm);
1703
1704         dev_info(smu->adev->dev, "FanPwmMin = %d\n", pptable->FanPwmMin);
1705         dev_info(smu->adev->dev, "FanAcousticLimitRpm = %d\n", pptable->FanAcousticLimitRpm);
1706         dev_info(smu->adev->dev, "FanThrottlingRpm = %d\n", pptable->FanThrottlingRpm);
1707         dev_info(smu->adev->dev, "FanMaximumRpm = %d\n", pptable->FanMaximumRpm);
1708         dev_info(smu->adev->dev, "FanTargetTemperature = %d\n", pptable->FanTargetTemperature);
1709         dev_info(smu->adev->dev, "FanTargetGfxclk = %d\n", pptable->FanTargetGfxclk);
1710         dev_info(smu->adev->dev, "FanZeroRpmEnable = %d\n", pptable->FanZeroRpmEnable);
1711         dev_info(smu->adev->dev, "FanTachEdgePerRev = %d\n", pptable->FanTachEdgePerRev);
1712         dev_info(smu->adev->dev, "FanTempInputSelect = %d\n", pptable->FanTempInputSelect);
1713
1714         dev_info(smu->adev->dev, "FuzzyFan_ErrorSetDelta = %d\n", pptable->FuzzyFan_ErrorSetDelta);
1715         dev_info(smu->adev->dev, "FuzzyFan_ErrorRateSetDelta = %d\n", pptable->FuzzyFan_ErrorRateSetDelta);
1716         dev_info(smu->adev->dev, "FuzzyFan_PwmSetDelta = %d\n", pptable->FuzzyFan_PwmSetDelta);
1717         dev_info(smu->adev->dev, "FuzzyFan_Reserved = %d\n", pptable->FuzzyFan_Reserved);
1718
1719         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_GFX]);
1720         dev_info(smu->adev->dev, "OverrideAvfsGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->OverrideAvfsGb[AVFS_VOLTAGE_SOC]);
1721         dev_info(smu->adev->dev, "Padding8_Avfs[0] = %d\n", pptable->Padding8_Avfs[0]);
1722         dev_info(smu->adev->dev, "Padding8_Avfs[1] = %d\n", pptable->Padding8_Avfs[1]);
1723
1724         dev_info(smu->adev->dev, "dBtcGbGfxPll{a = 0x%x b = 0x%x c = 0x%x}\n",
1725                         pptable->dBtcGbGfxPll.a,
1726                         pptable->dBtcGbGfxPll.b,
1727                         pptable->dBtcGbGfxPll.c);
1728         dev_info(smu->adev->dev, "dBtcGbGfxAfll{a = 0x%x b = 0x%x c = 0x%x}\n",
1729                         pptable->dBtcGbGfxAfll.a,
1730                         pptable->dBtcGbGfxAfll.b,
1731                         pptable->dBtcGbGfxAfll.c);
1732         dev_info(smu->adev->dev, "dBtcGbSoc{a = 0x%x b = 0x%x c = 0x%x}\n",
1733                         pptable->dBtcGbSoc.a,
1734                         pptable->dBtcGbSoc.b,
1735                         pptable->dBtcGbSoc.c);
1736
1737         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_GFX]{m = 0x%x b = 0x%x}\n",
1738                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].m,
1739                         pptable->qAgingGb[AVFS_VOLTAGE_GFX].b);
1740         dev_info(smu->adev->dev, "qAgingGb[AVFS_VOLTAGE_SOC]{m = 0x%x b = 0x%x}\n",
1741                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].m,
1742                         pptable->qAgingGb[AVFS_VOLTAGE_SOC].b);
1743
1744         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_GFX]{a = 0x%x b = 0x%x c = 0x%x}\n",
1745                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].a,
1746                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].b,
1747                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_GFX].c);
1748         dev_info(smu->adev->dev, "qStaticVoltageOffset[AVFS_VOLTAGE_SOC]{a = 0x%x b = 0x%x c = 0x%x}\n",
1749                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].a,
1750                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].b,
1751                         pptable->qStaticVoltageOffset[AVFS_VOLTAGE_SOC].c);
1752
1753         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_GFX]);
1754         dev_info(smu->adev->dev, "DcTol[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcTol[AVFS_VOLTAGE_SOC]);
1755
1756         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_GFX]);
1757         dev_info(smu->adev->dev, "DcBtcEnabled[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcEnabled[AVFS_VOLTAGE_SOC]);
1758         dev_info(smu->adev->dev, "Padding8_GfxBtc[0] = 0x%x\n", pptable->Padding8_GfxBtc[0]);
1759         dev_info(smu->adev->dev, "Padding8_GfxBtc[1] = 0x%x\n", pptable->Padding8_GfxBtc[1]);
1760
1761         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_GFX]);
1762         dev_info(smu->adev->dev, "DcBtcMin[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMin[AVFS_VOLTAGE_SOC]);
1763         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_GFX]);
1764         dev_info(smu->adev->dev, "DcBtcMax[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcMax[AVFS_VOLTAGE_SOC]);
1765
1766         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_GFX] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_GFX]);
1767         dev_info(smu->adev->dev, "DcBtcGb[AVFS_VOLTAGE_SOC] = 0x%x\n", pptable->DcBtcGb[AVFS_VOLTAGE_SOC]);
1768
1769         dev_info(smu->adev->dev, "XgmiDpmPstates\n");
1770         for (i = 0; i < NUM_XGMI_LEVELS; i++)
1771                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiDpmPstates[i]);
1772         dev_info(smu->adev->dev, "XgmiDpmSpare[0] = 0x%02x\n", pptable->XgmiDpmSpare[0]);
1773         dev_info(smu->adev->dev, "XgmiDpmSpare[1] = 0x%02x\n", pptable->XgmiDpmSpare[1]);
1774
1775         dev_info(smu->adev->dev, "VDDGFX_TVmin = %d\n", pptable->VDDGFX_TVmin);
1776         dev_info(smu->adev->dev, "VDDSOC_TVmin = %d\n", pptable->VDDSOC_TVmin);
1777         dev_info(smu->adev->dev, "VDDGFX_Vmin_HiTemp = %d\n", pptable->VDDGFX_Vmin_HiTemp);
1778         dev_info(smu->adev->dev, "VDDGFX_Vmin_LoTemp = %d\n", pptable->VDDGFX_Vmin_LoTemp);
1779         dev_info(smu->adev->dev, "VDDSOC_Vmin_HiTemp = %d\n", pptable->VDDSOC_Vmin_HiTemp);
1780         dev_info(smu->adev->dev, "VDDSOC_Vmin_LoTemp = %d\n", pptable->VDDSOC_Vmin_LoTemp);
1781         dev_info(smu->adev->dev, "VDDGFX_TVminHystersis = %d\n", pptable->VDDGFX_TVminHystersis);
1782         dev_info(smu->adev->dev, "VDDSOC_TVminHystersis = %d\n", pptable->VDDSOC_TVminHystersis);
1783
1784         dev_info(smu->adev->dev, "DebugOverrides = 0x%x\n", pptable->DebugOverrides);
1785         dev_info(smu->adev->dev, "ReservedEquation0{a = 0x%x b = 0x%x c = 0x%x}\n",
1786                         pptable->ReservedEquation0.a,
1787                         pptable->ReservedEquation0.b,
1788                         pptable->ReservedEquation0.c);
1789         dev_info(smu->adev->dev, "ReservedEquation1{a = 0x%x b = 0x%x c = 0x%x}\n",
1790                         pptable->ReservedEquation1.a,
1791                         pptable->ReservedEquation1.b,
1792                         pptable->ReservedEquation1.c);
1793         dev_info(smu->adev->dev, "ReservedEquation2{a = 0x%x b = 0x%x c = 0x%x}\n",
1794                         pptable->ReservedEquation2.a,
1795                         pptable->ReservedEquation2.b,
1796                         pptable->ReservedEquation2.c);
1797         dev_info(smu->adev->dev, "ReservedEquation3{a = 0x%x b = 0x%x c = 0x%x}\n",
1798                         pptable->ReservedEquation3.a,
1799                         pptable->ReservedEquation3.b,
1800                         pptable->ReservedEquation3.c);
1801
1802         dev_info(smu->adev->dev, "MinVoltageUlvGfx = %d\n", pptable->MinVoltageUlvGfx);
1803         dev_info(smu->adev->dev, "PaddingUlv = %d\n", pptable->PaddingUlv);
1804
1805         dev_info(smu->adev->dev, "TotalPowerConfig = %d\n", pptable->TotalPowerConfig);
1806         dev_info(smu->adev->dev, "TotalPowerSpare1 = %d\n", pptable->TotalPowerSpare1);
1807         dev_info(smu->adev->dev, "TotalPowerSpare2 = %d\n", pptable->TotalPowerSpare2);
1808
1809         dev_info(smu->adev->dev, "PccThresholdLow = %d\n", pptable->PccThresholdLow);
1810         dev_info(smu->adev->dev, "PccThresholdHigh = %d\n", pptable->PccThresholdHigh);
1811
1812         dev_info(smu->adev->dev, "Board Parameters:\n");
1813         dev_info(smu->adev->dev, "MaxVoltageStepGfx = 0x%x\n", pptable->MaxVoltageStepGfx);
1814         dev_info(smu->adev->dev, "MaxVoltageStepSoc = 0x%x\n", pptable->MaxVoltageStepSoc);
1815
1816         dev_info(smu->adev->dev, "VddGfxVrMapping = 0x%x\n", pptable->VddGfxVrMapping);
1817         dev_info(smu->adev->dev, "VddSocVrMapping = 0x%x\n", pptable->VddSocVrMapping);
1818         dev_info(smu->adev->dev, "VddMemVrMapping = 0x%x\n", pptable->VddMemVrMapping);
1819         dev_info(smu->adev->dev, "BoardVrMapping = 0x%x\n", pptable->BoardVrMapping);
1820
1821         dev_info(smu->adev->dev, "GfxUlvPhaseSheddingMask = 0x%x\n", pptable->GfxUlvPhaseSheddingMask);
1822         dev_info(smu->adev->dev, "ExternalSensorPresent = 0x%x\n", pptable->ExternalSensorPresent);
1823
1824         dev_info(smu->adev->dev, "GfxMaxCurrent = 0x%x\n", pptable->GfxMaxCurrent);
1825         dev_info(smu->adev->dev, "GfxOffset = 0x%x\n", pptable->GfxOffset);
1826         dev_info(smu->adev->dev, "Padding_TelemetryGfx = 0x%x\n", pptable->Padding_TelemetryGfx);
1827
1828         dev_info(smu->adev->dev, "SocMaxCurrent = 0x%x\n", pptable->SocMaxCurrent);
1829         dev_info(smu->adev->dev, "SocOffset = 0x%x\n", pptable->SocOffset);
1830         dev_info(smu->adev->dev, "Padding_TelemetrySoc = 0x%x\n", pptable->Padding_TelemetrySoc);
1831
1832         dev_info(smu->adev->dev, "MemMaxCurrent = 0x%x\n", pptable->MemMaxCurrent);
1833         dev_info(smu->adev->dev, "MemOffset = 0x%x\n", pptable->MemOffset);
1834         dev_info(smu->adev->dev, "Padding_TelemetryMem = 0x%x\n", pptable->Padding_TelemetryMem);
1835
1836         dev_info(smu->adev->dev, "BoardMaxCurrent = 0x%x\n", pptable->BoardMaxCurrent);
1837         dev_info(smu->adev->dev, "BoardOffset = 0x%x\n", pptable->BoardOffset);
1838         dev_info(smu->adev->dev, "Padding_TelemetryBoardInput = 0x%x\n", pptable->Padding_TelemetryBoardInput);
1839
1840         dev_info(smu->adev->dev, "VR0HotGpio = %d\n", pptable->VR0HotGpio);
1841         dev_info(smu->adev->dev, "VR0HotPolarity = %d\n", pptable->VR0HotPolarity);
1842         dev_info(smu->adev->dev, "VR1HotGpio = %d\n", pptable->VR1HotGpio);
1843         dev_info(smu->adev->dev, "VR1HotPolarity = %d\n", pptable->VR1HotPolarity);
1844
1845         dev_info(smu->adev->dev, "PllGfxclkSpreadEnabled = %d\n", pptable->PllGfxclkSpreadEnabled);
1846         dev_info(smu->adev->dev, "PllGfxclkSpreadPercent = %d\n", pptable->PllGfxclkSpreadPercent);
1847         dev_info(smu->adev->dev, "PllGfxclkSpreadFreq = %d\n", pptable->PllGfxclkSpreadFreq);
1848
1849         dev_info(smu->adev->dev, "UclkSpreadEnabled = %d\n", pptable->UclkSpreadEnabled);
1850         dev_info(smu->adev->dev, "UclkSpreadPercent = %d\n", pptable->UclkSpreadPercent);
1851         dev_info(smu->adev->dev, "UclkSpreadFreq = %d\n", pptable->UclkSpreadFreq);
1852
1853         dev_info(smu->adev->dev, "FclkSpreadEnabled = %d\n", pptable->FclkSpreadEnabled);
1854         dev_info(smu->adev->dev, "FclkSpreadPercent = %d\n", pptable->FclkSpreadPercent);
1855         dev_info(smu->adev->dev, "FclkSpreadFreq = %d\n", pptable->FclkSpreadFreq);
1856
1857         dev_info(smu->adev->dev, "FllGfxclkSpreadEnabled = %d\n", pptable->FllGfxclkSpreadEnabled);
1858         dev_info(smu->adev->dev, "FllGfxclkSpreadPercent = %d\n", pptable->FllGfxclkSpreadPercent);
1859         dev_info(smu->adev->dev, "FllGfxclkSpreadFreq = %d\n", pptable->FllGfxclkSpreadFreq);
1860
1861         for (i = 0; i < NUM_I2C_CONTROLLERS; i++) {
1862                 dev_info(smu->adev->dev, "I2cControllers[%d]:\n", i);
1863                 dev_info(smu->adev->dev, "                   .Enabled = %d\n",
1864                                 pptable->I2cControllers[i].Enabled);
1865                 dev_info(smu->adev->dev, "                   .SlaveAddress = 0x%x\n",
1866                                 pptable->I2cControllers[i].SlaveAddress);
1867                 dev_info(smu->adev->dev, "                   .ControllerPort = %d\n",
1868                                 pptable->I2cControllers[i].ControllerPort);
1869                 dev_info(smu->adev->dev, "                   .ControllerName = %d\n",
1870                                 pptable->I2cControllers[i].ControllerName);
1871                 dev_info(smu->adev->dev, "                   .ThermalThrottler = %d\n",
1872                                 pptable->I2cControllers[i].ThermalThrotter);
1873                 dev_info(smu->adev->dev, "                   .I2cProtocol = %d\n",
1874                                 pptable->I2cControllers[i].I2cProtocol);
1875                 dev_info(smu->adev->dev, "                   .Speed = %d\n",
1876                                 pptable->I2cControllers[i].Speed);
1877         }
1878
1879         dev_info(smu->adev->dev, "MemoryChannelEnabled = %d\n", pptable->MemoryChannelEnabled);
1880         dev_info(smu->adev->dev, "DramBitWidth = %d\n", pptable->DramBitWidth);
1881
1882         dev_info(smu->adev->dev, "TotalBoardPower = %d\n", pptable->TotalBoardPower);
1883
1884         dev_info(smu->adev->dev, "XgmiLinkSpeed\n");
1885         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1886                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiLinkSpeed[i]);
1887         dev_info(smu->adev->dev, "XgmiLinkWidth\n");
1888         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1889                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiLinkWidth[i]);
1890         dev_info(smu->adev->dev, "XgmiFclkFreq\n");
1891         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1892                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiFclkFreq[i]);
1893         dev_info(smu->adev->dev, "XgmiSocVoltage\n");
1894         for (i = 0; i < NUM_XGMI_PSTATE_LEVELS; i++)
1895                 dev_info(smu->adev->dev, "  .[%d] = %d\n", i, pptable->XgmiSocVoltage[i]);
1896
1897 }
1898
1899 static bool arcturus_is_dpm_running(struct smu_context *smu)
1900 {
1901         int ret = 0;
1902         uint32_t feature_mask[2];
1903         uint64_t feature_enabled;
1904
1905         ret = smu_cmn_get_enabled_mask(smu, feature_mask, 2);
1906         if (ret)
1907                 return false;
1908
1909         feature_enabled = (uint64_t)feature_mask[1] << 32 | feature_mask[0];
1910
1911         return !!(feature_enabled & SMC_DPM_FEATURE);
1912 }
1913
1914 static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1915 {
1916         int ret = 0;
1917
1918         if (enable) {
1919                 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1920                         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 1);
1921                         if (ret) {
1922                                 dev_err(smu->adev->dev, "[EnableVCNDPM] failed!\n");
1923                                 return ret;
1924                         }
1925                 }
1926         } else {
1927                 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1928                         ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_VCN_PG_BIT, 0);
1929                         if (ret) {
1930                                 dev_err(smu->adev->dev, "[DisableVCNDPM] failed!\n");
1931                                 return ret;
1932                         }
1933                 }
1934         }
1935
1936         return ret;
1937 }
1938
1939 static void arcturus_fill_i2c_req(SwI2cRequest_t  *req, bool write,
1940                                   uint8_t address, uint32_t numbytes,
1941                                   uint8_t *data)
1942 {
1943         int i;
1944
1945         req->I2CcontrollerPort = 0;
1946         req->I2CSpeed = 2;
1947         req->SlaveAddress = address;
1948         req->NumCmds = numbytes;
1949
1950         for (i = 0; i < numbytes; i++) {
1951                 SwI2cCmd_t *cmd =  &req->SwI2cCmds[i];
1952
1953                 /* First 2 bytes are always write for lower 2b EEPROM address */
1954                 if (i < 2)
1955                         cmd->Cmd = 1;
1956                 else
1957                         cmd->Cmd = write;
1958
1959
1960                 /* Add RESTART for read  after address filled */
1961                 cmd->CmdConfig |= (i == 2 && !write) ? CMDCONFIG_RESTART_MASK : 0;
1962
1963                 /* Add STOP in the end */
1964                 cmd->CmdConfig |= (i == (numbytes - 1)) ? CMDCONFIG_STOP_MASK : 0;
1965
1966                 /* Fill with data regardless if read or write to simplify code */
1967                 cmd->RegisterAddr = data[i];
1968         }
1969 }
1970
1971 static int arcturus_i2c_read_data(struct i2c_adapter *control,
1972                                                uint8_t address,
1973                                                uint8_t *data,
1974                                                uint32_t numbytes)
1975 {
1976         uint32_t  i, ret = 0;
1977         SwI2cRequest_t req;
1978         struct amdgpu_device *adev = to_amdgpu_device(control);
1979         struct smu_table_context *smu_table = &adev->smu.smu_table;
1980         struct smu_table *table = &smu_table->driver_table;
1981
1982         if (numbytes > MAX_SW_I2C_COMMANDS) {
1983                 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
1984                         numbytes, MAX_SW_I2C_COMMANDS);
1985                 return -EINVAL;
1986         }
1987
1988         memset(&req, 0, sizeof(req));
1989         arcturus_fill_i2c_req(&req, false, address, numbytes, data);
1990
1991         mutex_lock(&adev->smu.mutex);
1992         /* Now read data starting with that address */
1993         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req,
1994                                         true);
1995         mutex_unlock(&adev->smu.mutex);
1996
1997         if (!ret) {
1998                 SwI2cRequest_t *res = (SwI2cRequest_t *)table->cpu_addr;
1999
2000                 /* Assume SMU  fills res.SwI2cCmds[i].Data with read bytes */
2001                 for (i = 0; i < numbytes; i++)
2002                         data[i] = res->SwI2cCmds[i].Data;
2003
2004                 dev_dbg(adev->dev, "arcturus_i2c_read_data, address = %x, bytes = %d, data :",
2005                                   (uint16_t)address, numbytes);
2006
2007                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2008                                8, 1, data, numbytes, false);
2009         } else
2010                 dev_err(adev->dev, "arcturus_i2c_read_data - error occurred :%x", ret);
2011
2012         return ret;
2013 }
2014
2015 static int arcturus_i2c_write_data(struct i2c_adapter *control,
2016                                                 uint8_t address,
2017                                                 uint8_t *data,
2018                                                 uint32_t numbytes)
2019 {
2020         uint32_t ret;
2021         SwI2cRequest_t req;
2022         struct amdgpu_device *adev = to_amdgpu_device(control);
2023
2024         if (numbytes > MAX_SW_I2C_COMMANDS) {
2025                 dev_err(adev->dev, "numbytes requested %d is over max allowed %d\n",
2026                         numbytes, MAX_SW_I2C_COMMANDS);
2027                 return -EINVAL;
2028         }
2029
2030         memset(&req, 0, sizeof(req));
2031         arcturus_fill_i2c_req(&req, true, address, numbytes, data);
2032
2033         mutex_lock(&adev->smu.mutex);
2034         ret = smu_cmn_update_table(&adev->smu, SMU_TABLE_I2C_COMMANDS, 0, &req, true);
2035         mutex_unlock(&adev->smu.mutex);
2036
2037         if (!ret) {
2038                 dev_dbg(adev->dev, "arcturus_i2c_write(), address = %x, bytes = %d , data: ",
2039                                          (uint16_t)address, numbytes);
2040
2041                 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_NONE,
2042                                8, 1, data, numbytes, false);
2043                 /*
2044                  * According to EEPROM spec there is a MAX of 10 ms required for
2045                  * EEPROM to flush internal RX buffer after STOP was issued at the
2046                  * end of write transaction. During this time the EEPROM will not be
2047                  * responsive to any more commands - so wait a bit more.
2048                  */
2049                 msleep(10);
2050
2051         } else
2052                 dev_err(adev->dev, "arcturus_i2c_write- error occurred :%x", ret);
2053
2054         return ret;
2055 }
2056
2057 static int arcturus_i2c_xfer(struct i2c_adapter *i2c_adap,
2058                               struct i2c_msg *msgs, int num)
2059 {
2060         uint32_t  i, j, ret, data_size, data_chunk_size, next_eeprom_addr = 0;
2061         uint8_t *data_ptr, data_chunk[MAX_SW_I2C_COMMANDS] = { 0 };
2062
2063         for (i = 0; i < num; i++) {
2064                 /*
2065                  * SMU interface allows at most MAX_SW_I2C_COMMANDS bytes of data at
2066                  * once and hence the data needs to be spliced into chunks and sent each
2067                  * chunk separately
2068                  */
2069                 data_size = msgs[i].len - 2;
2070                 data_chunk_size = MAX_SW_I2C_COMMANDS - 2;
2071                 next_eeprom_addr = (msgs[i].buf[0] << 8 & 0xff00) | (msgs[i].buf[1] & 0xff);
2072                 data_ptr = msgs[i].buf + 2;
2073
2074                 for (j = 0; j < data_size / data_chunk_size; j++) {
2075                         /* Insert the EEPROM dest addess, bits 0-15 */
2076                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2077                         data_chunk[1] = (next_eeprom_addr & 0xff);
2078
2079                         if (msgs[i].flags & I2C_M_RD) {
2080                                 ret = arcturus_i2c_read_data(i2c_adap,
2081                                                              (uint8_t)msgs[i].addr,
2082                                                              data_chunk, MAX_SW_I2C_COMMANDS);
2083
2084                                 memcpy(data_ptr, data_chunk + 2, data_chunk_size);
2085                         } else {
2086
2087                                 memcpy(data_chunk + 2, data_ptr, data_chunk_size);
2088
2089                                 ret = arcturus_i2c_write_data(i2c_adap,
2090                                                               (uint8_t)msgs[i].addr,
2091                                                               data_chunk, MAX_SW_I2C_COMMANDS);
2092                         }
2093
2094                         if (ret) {
2095                                 num = -EIO;
2096                                 goto fail;
2097                         }
2098
2099                         next_eeprom_addr += data_chunk_size;
2100                         data_ptr += data_chunk_size;
2101                 }
2102
2103                 if (data_size % data_chunk_size) {
2104                         data_chunk[0] = ((next_eeprom_addr >> 8) & 0xff);
2105                         data_chunk[1] = (next_eeprom_addr & 0xff);
2106
2107                         if (msgs[i].flags & I2C_M_RD) {
2108                                 ret = arcturus_i2c_read_data(i2c_adap,
2109                                                              (uint8_t)msgs[i].addr,
2110                                                              data_chunk, (data_size % data_chunk_size) + 2);
2111
2112                                 memcpy(data_ptr, data_chunk + 2, data_size % data_chunk_size);
2113                         } else {
2114                                 memcpy(data_chunk + 2, data_ptr, data_size % data_chunk_size);
2115
2116                                 ret = arcturus_i2c_write_data(i2c_adap,
2117                                                               (uint8_t)msgs[i].addr,
2118                                                               data_chunk, (data_size % data_chunk_size) + 2);
2119                         }
2120
2121                         if (ret) {
2122                                 num = -EIO;
2123                                 goto fail;
2124                         }
2125                 }
2126         }
2127
2128 fail:
2129         return num;
2130 }
2131
2132 static u32 arcturus_i2c_func(struct i2c_adapter *adap)
2133 {
2134         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2135 }
2136
2137
2138 static const struct i2c_algorithm arcturus_i2c_algo = {
2139         .master_xfer = arcturus_i2c_xfer,
2140         .functionality = arcturus_i2c_func,
2141 };
2142
2143 static int arcturus_i2c_control_init(struct smu_context *smu, struct i2c_adapter *control)
2144 {
2145         struct amdgpu_device *adev = to_amdgpu_device(control);
2146         int res;
2147
2148         control->owner = THIS_MODULE;
2149         control->class = I2C_CLASS_SPD;
2150         control->dev.parent = &adev->pdev->dev;
2151         control->algo = &arcturus_i2c_algo;
2152         snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
2153
2154         res = i2c_add_adapter(control);
2155         if (res)
2156                 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2157
2158         return res;
2159 }
2160
2161 static void arcturus_i2c_control_fini(struct smu_context *smu, struct i2c_adapter *control)
2162 {
2163         i2c_del_adapter(control);
2164 }
2165
2166 static void arcturus_get_unique_id(struct smu_context *smu)
2167 {
2168         struct amdgpu_device *adev = smu->adev;
2169         uint32_t top32 = 0, bottom32 = 0, smu_version;
2170         uint64_t id;
2171
2172         if (smu_cmn_get_smc_version(smu, NULL, &smu_version)) {
2173                 dev_warn(adev->dev, "Failed to get smu version, cannot get unique_id or serial_number\n");
2174                 return;
2175         }
2176
2177         /* PPSMC_MSG_ReadSerial* is supported by 54.23.0 and onwards */
2178         if (smu_version < 0x361700) {
2179                 dev_warn(adev->dev, "ReadSerial is only supported by PMFW 54.23.0 and onwards\n");
2180                 return;
2181         }
2182
2183         /* Get the SN to turn into a Unique ID */
2184         smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumTop32, &top32);
2185         smu_cmn_send_smc_msg(smu, SMU_MSG_ReadSerialNumBottom32, &bottom32);
2186
2187         id = ((uint64_t)bottom32 << 32) | top32;
2188         adev->unique_id = id;
2189         /* For Arcturus-and-later, unique_id == serial_number, so convert it to a
2190          * 16-digit HEX string for convenience and backwards-compatibility
2191          */
2192         sprintf(adev->serial, "%llx", id);
2193 }
2194
2195 static int arcturus_set_df_cstate(struct smu_context *smu,
2196                                   enum pp_df_cstate state)
2197 {
2198         uint32_t smu_version;
2199         int ret;
2200
2201         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2202         if (ret) {
2203                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
2204                 return ret;
2205         }
2206
2207         /* PPSMC_MSG_DFCstateControl is supported by 54.15.0 and onwards */
2208         if (smu_version < 0x360F00) {
2209                 dev_err(smu->adev->dev, "DFCstateControl is only supported by PMFW 54.15.0 and onwards\n");
2210                 return -EINVAL;
2211         }
2212
2213         return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_DFCstateControl, state, NULL);
2214 }
2215
2216 static int arcturus_allow_xgmi_power_down(struct smu_context *smu, bool en)
2217 {
2218         uint32_t smu_version;
2219         int ret;
2220
2221         ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
2222         if (ret) {
2223                 dev_err(smu->adev->dev, "Failed to get smu version!\n");
2224                 return ret;
2225         }
2226
2227         /* PPSMC_MSG_GmiPwrDnControl is supported by 54.23.0 and onwards */
2228         if (smu_version < 0x00361700) {
2229                 dev_err(smu->adev->dev, "XGMI power down control is only supported by PMFW 54.23.0 and onwards\n");
2230                 return -EINVAL;
2231         }
2232
2233         if (en)
2234                 return smu_cmn_send_smc_msg_with_param(smu,
2235                                                    SMU_MSG_GmiPwrDnControl,
2236                                                    1,
2237                                                    NULL);
2238
2239         return smu_cmn_send_smc_msg_with_param(smu,
2240                                            SMU_MSG_GmiPwrDnControl,
2241                                            0,
2242                                            NULL);
2243 }
2244
2245 static const struct throttling_logging_label {
2246         uint32_t feature_mask;
2247         const char *label;
2248 } logging_label[] = {
2249         {(1U << THROTTLER_TEMP_HOTSPOT_BIT), "GPU"},
2250         {(1U << THROTTLER_TEMP_MEM_BIT), "HBM"},
2251         {(1U << THROTTLER_TEMP_VR_GFX_BIT), "VR of GFX rail"},
2252         {(1U << THROTTLER_TEMP_VR_MEM_BIT), "VR of HBM rail"},
2253         {(1U << THROTTLER_TEMP_VR_SOC_BIT), "VR of SOC rail"},
2254         {(1U << THROTTLER_VRHOT0_BIT), "VR0 HOT"},
2255         {(1U << THROTTLER_VRHOT1_BIT), "VR1 HOT"},
2256 };
2257 static void arcturus_log_thermal_throttling_event(struct smu_context *smu)
2258 {
2259         int ret;
2260         int throttler_idx, throtting_events = 0, buf_idx = 0;
2261         struct amdgpu_device *adev = smu->adev;
2262         uint32_t throttler_status;
2263         char log_buf[256];
2264
2265         ret = arcturus_get_smu_metrics_data(smu,
2266                                             METRICS_THROTTLER_STATUS,
2267                                             &throttler_status);
2268         if (ret)
2269                 return;
2270
2271         memset(log_buf, 0, sizeof(log_buf));
2272         for (throttler_idx = 0; throttler_idx < ARRAY_SIZE(logging_label);
2273              throttler_idx++) {
2274                 if (throttler_status & logging_label[throttler_idx].feature_mask) {
2275                         throtting_events++;
2276                         buf_idx += snprintf(log_buf + buf_idx,
2277                                             sizeof(log_buf) - buf_idx,
2278                                             "%s%s",
2279                                             throtting_events > 1 ? " and " : "",
2280                                             logging_label[throttler_idx].label);
2281                         if (buf_idx >= sizeof(log_buf)) {
2282                                 dev_err(adev->dev, "buffer overflow!\n");
2283                                 log_buf[sizeof(log_buf) - 1] = '\0';
2284                                 break;
2285                         }
2286                 }
2287         }
2288
2289         dev_warn(adev->dev, "WARN: GPU thermal throttling temperature reached, expect performance decrease. %s.\n",
2290                         log_buf);
2291         kgd2kfd_smi_event_throttle(smu->adev->kfd.dev, throttler_status);
2292 }
2293
2294 static uint16_t arcturus_get_current_pcie_link_speed(struct smu_context *smu)
2295 {
2296         struct amdgpu_device *adev = smu->adev;
2297         uint32_t esm_ctrl;
2298
2299         /* TODO: confirm this on real target */
2300         esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
2301         if ((esm_ctrl >> 15) & 0x1FFFF)
2302                 return (uint16_t)(((esm_ctrl >> 8) & 0x3F) + 128);
2303
2304         return smu_v11_0_get_current_pcie_link_speed(smu);
2305 }
2306
2307 static ssize_t arcturus_get_gpu_metrics(struct smu_context *smu,
2308                                         void **table)
2309 {
2310         struct smu_table_context *smu_table = &smu->smu_table;
2311         struct gpu_metrics_v1_3 *gpu_metrics =
2312                 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2313         SmuMetrics_t metrics;
2314         int ret = 0;
2315
2316         ret = smu_cmn_get_metrics_table(smu,
2317                                         &metrics,
2318                                         true);
2319         if (ret)
2320                 return ret;
2321
2322         smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2323
2324         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2325         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2326         gpu_metrics->temperature_mem = metrics.TemperatureHBM;
2327         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2328         gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2329         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
2330
2331         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2332         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2333         gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
2334
2335         gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2336         gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
2337
2338         gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2339         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2340         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2341         gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
2342         gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
2343
2344         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2345         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2346         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2347         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2348         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2349
2350         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2351         gpu_metrics->indep_throttle_status =
2352                         smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
2353                                                            arcturus_throttler_map);
2354
2355         gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2356
2357         gpu_metrics->pcie_link_width =
2358                         smu_v11_0_get_current_pcie_link_width(smu);
2359         gpu_metrics->pcie_link_speed =
2360                         arcturus_get_current_pcie_link_speed(smu);
2361
2362         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2363
2364         *table = (void *)gpu_metrics;
2365
2366         return sizeof(struct gpu_metrics_v1_3);
2367 }
2368
2369 static const struct pptable_funcs arcturus_ppt_funcs = {
2370         /* init dpm */
2371         .get_allowed_feature_mask = arcturus_get_allowed_feature_mask,
2372         /* btc */
2373         .run_btc = arcturus_run_btc,
2374         /* dpm/clk tables */
2375         .set_default_dpm_table = arcturus_set_default_dpm_table,
2376         .populate_umd_state_clk = arcturus_populate_umd_state_clk,
2377         .get_thermal_temperature_range = arcturus_get_thermal_temperature_range,
2378         .print_clk_levels = arcturus_print_clk_levels,
2379         .force_clk_levels = arcturus_force_clk_levels,
2380         .read_sensor = arcturus_read_sensor,
2381         .get_fan_speed_percent = arcturus_get_fan_speed_percent,
2382         .get_power_profile_mode = arcturus_get_power_profile_mode,
2383         .set_power_profile_mode = arcturus_set_power_profile_mode,
2384         .set_performance_level = arcturus_set_performance_level,
2385         /* debug (internal used) */
2386         .dump_pptable = arcturus_dump_pptable,
2387         .get_power_limit = arcturus_get_power_limit,
2388         .is_dpm_running = arcturus_is_dpm_running,
2389         .dpm_set_vcn_enable = arcturus_dpm_set_vcn_enable,
2390         .i2c_init = arcturus_i2c_control_init,
2391         .i2c_fini = arcturus_i2c_control_fini,
2392         .get_unique_id = arcturus_get_unique_id,
2393         .init_microcode = smu_v11_0_init_microcode,
2394         .load_microcode = smu_v11_0_load_microcode,
2395         .fini_microcode = smu_v11_0_fini_microcode,
2396         .init_smc_tables = arcturus_init_smc_tables,
2397         .fini_smc_tables = smu_v11_0_fini_smc_tables,
2398         .init_power = smu_v11_0_init_power,
2399         .fini_power = smu_v11_0_fini_power,
2400         .check_fw_status = smu_v11_0_check_fw_status,
2401         /* pptable related */
2402         .setup_pptable = arcturus_setup_pptable,
2403         .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
2404         .check_fw_version = smu_v11_0_check_fw_version,
2405         .write_pptable = smu_cmn_write_pptable,
2406         .set_driver_table_location = smu_v11_0_set_driver_table_location,
2407         .set_tool_table_location = smu_v11_0_set_tool_table_location,
2408         .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
2409         .system_features_control = smu_v11_0_system_features_control,
2410         .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
2411         .send_smc_msg = smu_cmn_send_smc_msg,
2412         .init_display_count = NULL,
2413         .set_allowed_mask = smu_v11_0_set_allowed_mask,
2414         .get_enabled_mask = smu_cmn_get_enabled_mask,
2415         .feature_is_enabled = smu_cmn_feature_is_enabled,
2416         .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
2417         .notify_display_change = NULL,
2418         .set_power_limit = smu_v11_0_set_power_limit,
2419         .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
2420         .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
2421         .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
2422         .set_min_dcef_deep_sleep = NULL,
2423         .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
2424         .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
2425         .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
2426         .set_fan_speed_percent = smu_v11_0_set_fan_speed_percent,
2427         .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
2428         .gfx_off_control = smu_v11_0_gfx_off_control,
2429         .register_irq_handler = smu_v11_0_register_irq_handler,
2430         .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
2431         .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
2432         .baco_is_support = smu_v11_0_baco_is_support,
2433         .baco_get_state = smu_v11_0_baco_get_state,
2434         .baco_set_state = smu_v11_0_baco_set_state,
2435         .baco_enter = smu_v11_0_baco_enter,
2436         .baco_exit = smu_v11_0_baco_exit,
2437         .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
2438         .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
2439         .set_df_cstate = arcturus_set_df_cstate,
2440         .allow_xgmi_power_down = arcturus_allow_xgmi_power_down,
2441         .log_thermal_throttling_event = arcturus_log_thermal_throttling_event,
2442         .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
2443         .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
2444         .get_gpu_metrics = arcturus_get_gpu_metrics,
2445         .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
2446         .deep_sleep_control = smu_v11_0_deep_sleep_control,
2447         .get_fan_parameters = arcturus_get_fan_parameters,
2448         .interrupt_work = smu_v11_0_interrupt_work,
2449         .set_light_sbr = smu_v11_0_set_light_sbr,
2450         .set_mp1_state = smu_cmn_set_mp1_state,
2451 };
2452
2453 void arcturus_set_ppt_funcs(struct smu_context *smu)
2454 {
2455         smu->ppt_funcs = &arcturus_ppt_funcs;
2456         smu->message_map = arcturus_message_map;
2457         smu->clock_map = arcturus_clk_map;
2458         smu->feature_map = arcturus_feature_mask_map;
2459         smu->table_map = arcturus_table_map;
2460         smu->pwr_src_map = arcturus_pwr_src_map;
2461         smu->workload_map = arcturus_workload_map;
2462 }