drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #define SWSMU_CODE_LAYER_L1
  24
  25 #include <linux/firmware.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_smu.h"
  30 #include "smu_internal.h"
  31 #include "atom.h"
  32 #include "arcturus_ppt.h"
  33 #include "navi10_ppt.h"
  34 #include "sienna_cichlid_ppt.h"
  35 #include "renoir_ppt.h"
  36 #include "vangogh_ppt.h"
  37 #include "aldebaran_ppt.h"
  38 #include "yellow_carp_ppt.h"
  39 #include "cyan_skillfish_ppt.h"
  40 #include "amd_pcie.h"
  41
  42 /*
  43  * DO NOT use these for err/warn/info/debug messages.
  44  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  45  * They are more MGPU friendly.
  46  */
  47 #undef pr_err
  48 #undef pr_warn
  49 #undef pr_info
  50 #undef pr_debug
  51
  52 static const struct amd_pm_funcs swsmu_pm_funcs;
  53 static int smu_force_smuclk_levels(struct smu_context *smu,
  54                                    enum smu_clk_type clk_type,
  55                                    uint32_t mask);
  56 static int smu_handle_task(struct smu_context *smu,
  57                            enum amd_dpm_forced_level level,
  58                            enum amd_pp_task task_id,
  59                            bool lock_needed);
  60 static int smu_reset(struct smu_context *smu);
  61 static int smu_set_fan_speed_percent(void *handle, u32 speed);
  62 static int smu_set_fan_control_mode(struct smu_context *smu, int value);
  63 static int smu_set_power_limit(void *handle, uint32_t limit);
  64 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed);
  65 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
  66
  67 static int smu_sys_get_pp_feature_mask(void *handle,
  68                                        char *buf)
  69 {
  70         struct smu_context *smu = handle;
  71         int size = 0;
  72
  73         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
  74                 return -EOPNOTSUPP;
  75
  76         mutex_lock(&smu->mutex);
  77
  78         size = smu_get_pp_feature_mask(smu, buf);
  79
  80         mutex_unlock(&smu->mutex);
  81
  82         return size;
  83 }
  84
  85 static int smu_sys_set_pp_feature_mask(void *handle,
  86                                        uint64_t new_mask)
  87 {
  88         struct smu_context *smu = handle;
  89         int ret = 0;
  90
  91         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
  92                 return -EOPNOTSUPP;
  93
  94         mutex_lock(&smu->mutex);
  95
  96         ret = smu_set_pp_feature_mask(smu, new_mask);
  97
  98         mutex_unlock(&smu->mutex);
  99
 100         return ret;
 101 }
 102
 103 int smu_get_status_gfxoff(struct amdgpu_device *adev, uint32_t *value)
 104 {
 105         int ret = 0;
 106         struct smu_context *smu = &adev->smu;
 107
 108         if (is_support_sw_smu(adev) && smu->ppt_funcs->get_gfx_off_status)
 109                 *value = smu_get_gfx_off_status(smu);
 110         else
 111                 ret = -EINVAL;
 112
 113         return ret;
 114 }
 115
 116 int smu_set_soft_freq_range(struct smu_context *smu,
 117                             enum smu_clk_type clk_type,
 118                             uint32_t min,
 119                             uint32_t max)
 120 {
 121         int ret = 0;
 122
 123         mutex_lock(&smu->mutex);
 124
 125         if (smu->ppt_funcs->set_soft_freq_limited_range)
 126                 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
 127                                                                   clk_type,
 128                                                                   min,
 129                                                                   max);
 130
 131         mutex_unlock(&smu->mutex);
 132
 133         return ret;
 134 }
 135
 136 int smu_get_dpm_freq_range(struct smu_context *smu,
 137                            enum smu_clk_type clk_type,
 138                            uint32_t *min,
 139                            uint32_t *max)
 140 {
 141         int ret = 0;
 142
 143         if (!min && !max)
 144                 return -EINVAL;
 145
 146         mutex_lock(&smu->mutex);
 147
 148         if (smu->ppt_funcs->get_dpm_ultimate_freq)
 149                 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
 150                                                             clk_type,
 151                                                             min,
 152                                                             max);
 153
 154         mutex_unlock(&smu->mutex);
 155
 156         return ret;
 157 }
 158
 159 static u32 smu_get_mclk(void *handle, bool low)
 160 {
 161         struct smu_context *smu = handle;
 162         uint32_t clk_freq;
 163         int ret = 0;
 164
 165         ret = smu_get_dpm_freq_range(smu, SMU_UCLK,
 166                                      low ? &clk_freq : NULL,
 167                                      !low ? &clk_freq : NULL);
 168         if (ret)
 169                 return 0;
 170         return clk_freq * 100;
 171 }
 172
 173 static u32 smu_get_sclk(void *handle, bool low)
 174 {
 175         struct smu_context *smu = handle;
 176         uint32_t clk_freq;
 177         int ret = 0;
 178
 179         ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK,
 180                                      low ? &clk_freq : NULL,
 181                                      !low ? &clk_freq : NULL);
 182         if (ret)
 183                 return 0;
 184         return clk_freq * 100;
 185 }
 186
 187 static int smu_dpm_set_vcn_enable_locked(struct smu_context *smu,
 188                                          bool enable)
 189 {
 190         struct smu_power_context *smu_power = &smu->smu_power;
 191         struct smu_power_gate *power_gate = &smu_power->power_gate;
 192         int ret = 0;
 193
 194         if (!smu->ppt_funcs->dpm_set_vcn_enable)
 195                 return 0;
 196
 197         if (atomic_read(&power_gate->vcn_gated) ^ enable)
 198                 return 0;
 199
 200         ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
 201         if (!ret)
 202                 atomic_set(&power_gate->vcn_gated, !enable);
 203
 204         return ret;
 205 }
 206
 207 static int smu_dpm_set_vcn_enable(struct smu_context *smu,
 208                                   bool enable)
 209 {
 210         struct smu_power_context *smu_power = &smu->smu_power;
 211         struct smu_power_gate *power_gate = &smu_power->power_gate;
 212         int ret = 0;
 213
 214         mutex_lock(&power_gate->vcn_gate_lock);
 215
 216         ret = smu_dpm_set_vcn_enable_locked(smu, enable);
 217
 218         mutex_unlock(&power_gate->vcn_gate_lock);
 219
 220         return ret;
 221 }
 222
 223 static int smu_dpm_set_jpeg_enable_locked(struct smu_context *smu,
 224                                           bool enable)
 225 {
 226         struct smu_power_context *smu_power = &smu->smu_power;
 227         struct smu_power_gate *power_gate = &smu_power->power_gate;
 228         int ret = 0;
 229
 230         if (!smu->ppt_funcs->dpm_set_jpeg_enable)
 231                 return 0;
 232
 233         if (atomic_read(&power_gate->jpeg_gated) ^ enable)
 234                 return 0;
 235
 236         ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
 237         if (!ret)
 238                 atomic_set(&power_gate->jpeg_gated, !enable);
 239
 240         return ret;
 241 }
 242
 243 static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
 244                                    bool enable)
 245 {
 246         struct smu_power_context *smu_power = &smu->smu_power;
 247         struct smu_power_gate *power_gate = &smu_power->power_gate;
 248         int ret = 0;
 249
 250         mutex_lock(&power_gate->jpeg_gate_lock);
 251
 252         ret = smu_dpm_set_jpeg_enable_locked(smu, enable);
 253
 254         mutex_unlock(&power_gate->jpeg_gate_lock);
 255
 256         return ret;
 257 }
 258
 259 /**
 260  * smu_dpm_set_power_gate - power gate/ungate the specific IP block
 261  *
 262  * @handle:        smu_context pointer
 263  * @block_type: the IP block to power gate/ungate
 264  * @gate:       to power gate if true, ungate otherwise
 265  *
 266  * This API uses no smu->mutex lock protection due to:
 267  * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
 268  *    This is guarded to be race condition free by the caller.
 269  * 2. Or get called on user setting request of power_dpm_force_performance_level.
 270  *    Under this case, the smu->mutex lock protection is already enforced on
 271  *    the parent API smu_force_performance_level of the call path.
 272  */
 273 static int smu_dpm_set_power_gate(void *handle,
 274                                   uint32_t block_type,
 275                                   bool gate)
 276 {
 277         struct smu_context *smu = handle;
 278         int ret = 0;
 279
 280         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 281                 return -EOPNOTSUPP;
 282
 283         switch (block_type) {
 284         /*
 285          * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
 286          * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
 287          */
 288         case AMD_IP_BLOCK_TYPE_UVD:
 289         case AMD_IP_BLOCK_TYPE_VCN:
 290                 ret = smu_dpm_set_vcn_enable(smu, !gate);
 291                 if (ret)
 292                         dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
 293                                 gate ? "gate" : "ungate");
 294                 break;
 295         case AMD_IP_BLOCK_TYPE_GFX:
 296                 ret = smu_gfx_off_control(smu, gate);
 297                 if (ret)
 298                         dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
 299                                 gate ? "enable" : "disable");
 300                 break;
 301         case AMD_IP_BLOCK_TYPE_SDMA:
 302                 ret = smu_powergate_sdma(smu, gate);
 303                 if (ret)
 304                         dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
 305                                 gate ? "gate" : "ungate");
 306                 break;
 307         case AMD_IP_BLOCK_TYPE_JPEG:
 308                 ret = smu_dpm_set_jpeg_enable(smu, !gate);
 309                 if (ret)
 310                         dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
 311                                 gate ? "gate" : "ungate");
 312                 break;
 313         default:
 314                 dev_err(smu->adev->dev, "Unsupported block type!\n");
 315                 return -EINVAL;
 316         }
 317
 318         return ret;
 319 }
 320
 321 /**
 322  * smu_set_user_clk_dependencies - set user profile clock dependencies
 323  *
 324  * @smu:        smu_context pointer
 325  * @clk:        enum smu_clk_type type
 326  *
 327  * Enable/Disable the clock dependency for the @clk type.
 328  */
 329 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk)
 330 {
 331         if (smu->adev->in_suspend)
 332                 return;
 333
 334         if (clk == SMU_MCLK) {
 335                 smu->user_dpm_profile.clk_dependency = 0;
 336                 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK);
 337         } else if (clk == SMU_FCLK) {
 338                 /* MCLK takes precedence over FCLK */
 339                 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
 340                         return;
 341
 342                 smu->user_dpm_profile.clk_dependency = 0;
 343                 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK);
 344         } else if (clk == SMU_SOCCLK) {
 345                 /* MCLK takes precedence over SOCCLK */
 346                 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
 347                         return;
 348
 349                 smu->user_dpm_profile.clk_dependency = 0;
 350                 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK);
 351         } else
 352                 /* Add clk dependencies here, if any */
 353                 return;
 354 }
 355
 356 /**
 357  * smu_restore_dpm_user_profile - reinstate user dpm profile
 358  *
 359  * @smu:        smu_context pointer
 360  *
 361  * Restore the saved user power configurations include power limit,
 362  * clock frequencies, fan control mode and fan speed.
 363  */
 364 static void smu_restore_dpm_user_profile(struct smu_context *smu)
 365 {
 366         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
 367         int ret = 0;
 368
 369         if (!smu->adev->in_suspend)
 370                 return;
 371
 372         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 373                 return;
 374
 375         /* Enable restore flag */
 376         smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE;
 377
 378         /* set the user dpm power limit */
 379         if (smu->user_dpm_profile.power_limit) {
 380                 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit);
 381                 if (ret)
 382                         dev_err(smu->adev->dev, "Failed to set power limit value\n");
 383         }
 384
 385         /* set the user dpm clock configurations */
 386         if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
 387                 enum smu_clk_type clk_type;
 388
 389                 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) {
 390                         /*
 391                          * Iterate over smu clk type and force the saved user clk
 392                          * configs, skip if clock dependency is enabled
 393                          */
 394                         if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) &&
 395                                         smu->user_dpm_profile.clk_mask[clk_type]) {
 396                                 ret = smu_force_smuclk_levels(smu, clk_type,
 397                                                 smu->user_dpm_profile.clk_mask[clk_type]);
 398                                 if (ret)
 399                                         dev_err(smu->adev->dev,
 400                                                 "Failed to set clock type = %d\n", clk_type);
 401                         }
 402                 }
 403         }
 404
 405         /* set the user dpm fan configurations */
 406         if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL ||
 407             smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) {
 408                 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode);
 409                 if (ret) {
 410                         smu->user_dpm_profile.fan_speed_percent = 0;
 411                         smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO;
 412                         dev_err(smu->adev->dev, "Failed to set manual fan control mode\n");
 413                 }
 414
 415                 if (smu->user_dpm_profile.fan_speed_percent) {
 416                         ret = smu_set_fan_speed_percent(smu, smu->user_dpm_profile.fan_speed_percent);
 417                         if (ret)
 418                                 dev_err(smu->adev->dev, "Failed to set manual fan speed\n");
 419                 }
 420         }
 421
 422         /* Restore user customized OD settings */
 423         if (smu->user_dpm_profile.user_od) {
 424                 if (smu->ppt_funcs->restore_user_od_settings) {
 425                         ret = smu->ppt_funcs->restore_user_od_settings(smu);
 426                         if (ret)
 427                                 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n");
 428                 }
 429         }
 430
 431         /* Disable restore flag */
 432         smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE;
 433 }
 434
 435 static int smu_get_power_num_states(void *handle,
 436                                     struct pp_states_info *state_info)
 437 {
 438         if (!state_info)
 439                 return -EINVAL;
 440
 441         /* not support power state */
 442         memset(state_info, 0, sizeof(struct pp_states_info));
 443         state_info->nums = 1;
 444         state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
 445
 446         return 0;
 447 }
 448
 449 bool is_support_sw_smu(struct amdgpu_device *adev)
 450 {
 451         if (adev->asic_type >= CHIP_ARCTURUS)
 452                 return true;
 453
 454         return false;
 455 }
 456
 457 bool is_support_cclk_dpm(struct amdgpu_device *adev)
 458 {
 459         struct smu_context *smu = &adev->smu;
 460
 461         if (!is_support_sw_smu(adev))
 462                 return false;
 463
 464         if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT))
 465                 return false;
 466
 467         return true;
 468 }
 469
 470
 471 static int smu_sys_get_pp_table(void *handle,
 472                                 char **table)
 473 {
 474         struct smu_context *smu = handle;
 475         struct smu_table_context *smu_table = &smu->smu_table;
 476         uint32_t powerplay_table_size;
 477
 478         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 479                 return -EOPNOTSUPP;
 480
 481         if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
 482                 return -EINVAL;
 483
 484         mutex_lock(&smu->mutex);
 485
 486         if (smu_table->hardcode_pptable)
 487                 *table = smu_table->hardcode_pptable;
 488         else
 489                 *table = smu_table->power_play_table;
 490
 491         powerplay_table_size = smu_table->power_play_table_size;
 492
 493         mutex_unlock(&smu->mutex);
 494
 495         return powerplay_table_size;
 496 }
 497
 498 static int smu_sys_set_pp_table(void *handle,
 499                                 const char *buf,
 500                                 size_t size)
 501 {
 502         struct smu_context *smu = handle;
 503         struct smu_table_context *smu_table = &smu->smu_table;
 504         ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
 505         int ret = 0;
 506
 507         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 508                 return -EOPNOTSUPP;
 509
 510         if (header->usStructureSize != size) {
 511                 dev_err(smu->adev->dev, "pp table size not matched !\n");
 512                 return -EIO;
 513         }
 514
 515         mutex_lock(&smu->mutex);
 516         if (!smu_table->hardcode_pptable)
 517                 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
 518         if (!smu_table->hardcode_pptable) {
 519                 ret = -ENOMEM;
 520                 goto failed;
 521         }
 522
 523         memcpy(smu_table->hardcode_pptable, buf, size);
 524         smu_table->power_play_table = smu_table->hardcode_pptable;
 525         smu_table->power_play_table_size = size;
 526
 527         /*
 528          * Special hw_fini action(for Navi1x, the DPMs disablement will be
 529          * skipped) may be needed for custom pptable uploading.
 530          */
 531         smu->uploading_custom_pp_table = true;
 532
 533         ret = smu_reset(smu);
 534         if (ret)
 535                 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
 536
 537         smu->uploading_custom_pp_table = false;
 538
 539 failed:
 540         mutex_unlock(&smu->mutex);
 541         return ret;
 542 }
 543
 544 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
 545 {
 546         struct smu_feature *feature = &smu->smu_feature;
 547         int ret = 0;
 548         uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
 549
 550         bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
 551
 552         ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
 553                                              SMU_FEATURE_MAX/32);
 554         if (ret)
 555                 return ret;
 556
 557         bitmap_or(feature->allowed, feature->allowed,
 558                       (unsigned long *)allowed_feature_mask,
 559                       feature->feature_num);
 560
 561         return ret;
 562 }
 563
 564 static int smu_set_funcs(struct amdgpu_device *adev)
 565 {
 566         struct smu_context *smu = &adev->smu;
 567
 568         if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
 569                 smu->od_enabled = true;
 570
 571         switch (adev->asic_type) {
 572         case CHIP_NAVI10:
 573         case CHIP_NAVI14:
 574         case CHIP_NAVI12:
 575                 navi10_set_ppt_funcs(smu);
 576                 break;
 577         case CHIP_ARCTURUS:
 578                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 579                 arcturus_set_ppt_funcs(smu);
 580                 /* OD is not supported on Arcturus */
 581                 smu->od_enabled =false;
 582                 break;
 583         case CHIP_SIENNA_CICHLID:
 584         case CHIP_NAVY_FLOUNDER:
 585         case CHIP_DIMGREY_CAVEFISH:
 586         case CHIP_BEIGE_GOBY:
 587                 sienna_cichlid_set_ppt_funcs(smu);
 588                 break;
 589         case CHIP_ALDEBARAN:
 590                 aldebaran_set_ppt_funcs(smu);
 591                 /* Enable pp_od_clk_voltage node */
 592                 smu->od_enabled = true;
 593                 break;
 594         case CHIP_RENOIR:
 595                 renoir_set_ppt_funcs(smu);
 596                 break;
 597         case CHIP_VANGOGH:
 598                 vangogh_set_ppt_funcs(smu);
 599                 break;
 600         case CHIP_YELLOW_CARP:
 601                 yellow_carp_set_ppt_funcs(smu);
 602                 break;
 603         case CHIP_CYAN_SKILLFISH:
 604                 cyan_skillfish_set_ppt_funcs(smu);
 605                 break;
 606         default:
 607                 return -EINVAL;
 608         }
 609
 610         return 0;
 611 }
 612
 613 static int smu_early_init(void *handle)
 614 {
 615         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 616         struct smu_context *smu = &adev->smu;
 617
 618         smu->adev = adev;
 619         smu->pm_enabled = !!amdgpu_dpm;
 620         smu->is_apu = false;
 621         mutex_init(&smu->mutex);
 622         mutex_init(&smu->smu_baco.mutex);
 623         smu->smu_baco.state = SMU_BACO_STATE_EXIT;
 624         smu->smu_baco.platform_support = false;
 625         smu->user_dpm_profile.fan_mode = -1;
 626
 627         adev->powerplay.pp_handle = smu;
 628         adev->powerplay.pp_funcs = &swsmu_pm_funcs;
 629
 630         return smu_set_funcs(adev);
 631 }
 632
 633 static int smu_set_default_dpm_table(struct smu_context *smu)
 634 {
 635         struct smu_power_context *smu_power = &smu->smu_power;
 636         struct smu_power_gate *power_gate = &smu_power->power_gate;
 637         int vcn_gate, jpeg_gate;
 638         int ret = 0;
 639
 640         if (!smu->ppt_funcs->set_default_dpm_table)
 641                 return 0;
 642
 643         mutex_lock(&power_gate->vcn_gate_lock);
 644         mutex_lock(&power_gate->jpeg_gate_lock);
 645
 646         vcn_gate = atomic_read(&power_gate->vcn_gated);
 647         jpeg_gate = atomic_read(&power_gate->jpeg_gated);
 648
 649         ret = smu_dpm_set_vcn_enable_locked(smu, true);
 650         if (ret)
 651                 goto err0_out;
 652
 653         ret = smu_dpm_set_jpeg_enable_locked(smu, true);
 654         if (ret)
 655                 goto err1_out;
 656
 657         ret = smu->ppt_funcs->set_default_dpm_table(smu);
 658         if (ret)
 659                 dev_err(smu->adev->dev,
 660                         "Failed to setup default dpm clock tables!\n");
 661
 662         smu_dpm_set_jpeg_enable_locked(smu, !jpeg_gate);
 663 err1_out:
 664         smu_dpm_set_vcn_enable_locked(smu, !vcn_gate);
 665 err0_out:
 666         mutex_unlock(&power_gate->jpeg_gate_lock);
 667         mutex_unlock(&power_gate->vcn_gate_lock);
 668
 669         return ret;
 670 }
 671
 672
 673 static int smu_late_init(void *handle)
 674 {
 675         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 676         struct smu_context *smu = &adev->smu;
 677         int ret = 0;
 678
 679         smu_set_fine_grain_gfx_freq_parameters(smu);
 680
 681         if (!smu->pm_enabled)
 682                 return 0;
 683
 684         ret = smu_post_init(smu);
 685         if (ret) {
 686                 dev_err(adev->dev, "Failed to post smu init!\n");
 687                 return ret;
 688         }
 689
 690         if (adev->asic_type == CHIP_YELLOW_CARP)
 691                 return 0;
 692
 693         if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
 694                 ret = smu_set_default_od_settings(smu);
 695                 if (ret) {
 696                         dev_err(adev->dev, "Failed to setup default OD settings!\n");
 697                         return ret;
 698                 }
 699         }
 700
 701         ret = smu_populate_umd_state_clk(smu);
 702         if (ret) {
 703                 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
 704                 return ret;
 705         }
 706
 707         ret = smu_get_asic_power_limits(smu,
 708                                         &smu->current_power_limit,
 709                                         &smu->default_power_limit,
 710                                         &smu->max_power_limit);
 711         if (ret) {
 712                 dev_err(adev->dev, "Failed to get asic power limits!\n");
 713                 return ret;
 714         }
 715
 716         if (!amdgpu_sriov_vf(adev))
 717                 smu_get_unique_id(smu);
 718
 719         smu_get_fan_parameters(smu);
 720
 721         smu_handle_task(&adev->smu,
 722                         smu->smu_dpm.dpm_level,
 723                         AMD_PP_TASK_COMPLETE_INIT,
 724                         false);
 725
 726         smu_restore_dpm_user_profile(smu);
 727
 728         return 0;
 729 }
 730
 731 static int smu_init_fb_allocations(struct smu_context *smu)
 732 {
 733         struct amdgpu_device *adev = smu->adev;
 734         struct smu_table_context *smu_table = &smu->smu_table;
 735         struct smu_table *tables = smu_table->tables;
 736         struct smu_table *driver_table = &(smu_table->driver_table);
 737         uint32_t max_table_size = 0;
 738         int ret, i;
 739
 740         /* VRAM allocation for tool table */
 741         if (tables[SMU_TABLE_PMSTATUSLOG].size) {
 742                 ret = amdgpu_bo_create_kernel(adev,
 743                                               tables[SMU_TABLE_PMSTATUSLOG].size,
 744                                               tables[SMU_TABLE_PMSTATUSLOG].align,
 745                                               tables[SMU_TABLE_PMSTATUSLOG].domain,
 746                                               &tables[SMU_TABLE_PMSTATUSLOG].bo,
 747                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 748                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 749                 if (ret) {
 750                         dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
 751                         return ret;
 752                 }
 753         }
 754
 755         /* VRAM allocation for driver table */
 756         for (i = 0; i < SMU_TABLE_COUNT; i++) {
 757                 if (tables[i].size == 0)
 758                         continue;
 759
 760                 if (i == SMU_TABLE_PMSTATUSLOG)
 761                         continue;
 762
 763                 if (max_table_size < tables[i].size)
 764                         max_table_size = tables[i].size;
 765         }
 766
 767         driver_table->size = max_table_size;
 768         driver_table->align = PAGE_SIZE;
 769         driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
 770
 771         ret = amdgpu_bo_create_kernel(adev,
 772                                       driver_table->size,
 773                                       driver_table->align,
 774                                       driver_table->domain,
 775                                       &driver_table->bo,
 776                                       &driver_table->mc_address,
 777                                       &driver_table->cpu_addr);
 778         if (ret) {
 779                 dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
 780                 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 781                         amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 782                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 783                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 784         }
 785
 786         return ret;
 787 }
 788
 789 static int smu_fini_fb_allocations(struct smu_context *smu)
 790 {
 791         struct smu_table_context *smu_table = &smu->smu_table;
 792         struct smu_table *tables = smu_table->tables;
 793         struct smu_table *driver_table = &(smu_table->driver_table);
 794
 795         if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 796                 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 797                                       &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 798                                       &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 799
 800         amdgpu_bo_free_kernel(&driver_table->bo,
 801                               &driver_table->mc_address,
 802                               &driver_table->cpu_addr);
 803
 804         return 0;
 805 }
 806
 807 /**
 808  * smu_alloc_memory_pool - allocate memory pool in the system memory
 809  *
 810  * @smu: amdgpu_device pointer
 811  *
 812  * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
 813  * and DramLogSetDramAddr can notify it changed.
 814  *
 815  * Returns 0 on success, error on failure.
 816  */
 817 static int smu_alloc_memory_pool(struct smu_context *smu)
 818 {
 819         struct amdgpu_device *adev = smu->adev;
 820         struct smu_table_context *smu_table = &smu->smu_table;
 821         struct smu_table *memory_pool = &smu_table->memory_pool;
 822         uint64_t pool_size = smu->pool_size;
 823         int ret = 0;
 824
 825         if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
 826                 return ret;
 827
 828         memory_pool->size = pool_size;
 829         memory_pool->align = PAGE_SIZE;
 830         memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
 831
 832         switch (pool_size) {
 833         case SMU_MEMORY_POOL_SIZE_256_MB:
 834         case SMU_MEMORY_POOL_SIZE_512_MB:
 835         case SMU_MEMORY_POOL_SIZE_1_GB:
 836         case SMU_MEMORY_POOL_SIZE_2_GB:
 837                 ret = amdgpu_bo_create_kernel(adev,
 838                                               memory_pool->size,
 839                                               memory_pool->align,
 840                                               memory_pool->domain,
 841                                               &memory_pool->bo,
 842                                               &memory_pool->mc_address,
 843                                               &memory_pool->cpu_addr);
 844                 if (ret)
 845                         dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
 846                 break;
 847         default:
 848                 break;
 849         }
 850
 851         return ret;
 852 }
 853
 854 static int smu_free_memory_pool(struct smu_context *smu)
 855 {
 856         struct smu_table_context *smu_table = &smu->smu_table;
 857         struct smu_table *memory_pool = &smu_table->memory_pool;
 858
 859         if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
 860                 return 0;
 861
 862         amdgpu_bo_free_kernel(&memory_pool->bo,
 863                               &memory_pool->mc_address,
 864                               &memory_pool->cpu_addr);
 865
 866         memset(memory_pool, 0, sizeof(struct smu_table));
 867
 868         return 0;
 869 }
 870
 871 static int smu_alloc_dummy_read_table(struct smu_context *smu)
 872 {
 873         struct smu_table_context *smu_table = &smu->smu_table;
 874         struct smu_table *dummy_read_1_table =
 875                         &smu_table->dummy_read_1_table;
 876         struct amdgpu_device *adev = smu->adev;
 877         int ret = 0;
 878
 879         dummy_read_1_table->size = 0x40000;
 880         dummy_read_1_table->align = PAGE_SIZE;
 881         dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
 882
 883         ret = amdgpu_bo_create_kernel(adev,
 884                                       dummy_read_1_table->size,
 885                                       dummy_read_1_table->align,
 886                                       dummy_read_1_table->domain,
 887                                       &dummy_read_1_table->bo,
 888                                       &dummy_read_1_table->mc_address,
 889                                       &dummy_read_1_table->cpu_addr);
 890         if (ret)
 891                 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n");
 892
 893         return ret;
 894 }
 895
 896 static void smu_free_dummy_read_table(struct smu_context *smu)
 897 {
 898         struct smu_table_context *smu_table = &smu->smu_table;
 899         struct smu_table *dummy_read_1_table =
 900                         &smu_table->dummy_read_1_table;
 901
 902
 903         amdgpu_bo_free_kernel(&dummy_read_1_table->bo,
 904                               &dummy_read_1_table->mc_address,
 905                               &dummy_read_1_table->cpu_addr);
 906
 907         memset(dummy_read_1_table, 0, sizeof(struct smu_table));
 908 }
 909
 910 static int smu_smc_table_sw_init(struct smu_context *smu)
 911 {
 912         int ret;
 913
 914         /**
 915          * Create smu_table structure, and init smc tables such as
 916          * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
 917          */
 918         ret = smu_init_smc_tables(smu);
 919         if (ret) {
 920                 dev_err(smu->adev->dev, "Failed to init smc tables!\n");
 921                 return ret;
 922         }
 923
 924         /**
 925          * Create smu_power_context structure, and allocate smu_dpm_context and
 926          * context size to fill the smu_power_context data.
 927          */
 928         ret = smu_init_power(smu);
 929         if (ret) {
 930                 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
 931                 return ret;
 932         }
 933
 934         /*
 935          * allocate vram bos to store smc table contents.
 936          */
 937         ret = smu_init_fb_allocations(smu);
 938         if (ret)
 939                 return ret;
 940
 941         ret = smu_alloc_memory_pool(smu);
 942         if (ret)
 943                 return ret;
 944
 945         ret = smu_alloc_dummy_read_table(smu);
 946         if (ret)
 947                 return ret;
 948
 949         ret = smu_i2c_init(smu, &smu->adev->pm.smu_i2c);
 950         if (ret)
 951                 return ret;
 952
 953         return 0;
 954 }
 955
 956 static int smu_smc_table_sw_fini(struct smu_context *smu)
 957 {
 958         int ret;
 959
 960         smu_i2c_fini(smu, &smu->adev->pm.smu_i2c);
 961
 962         smu_free_dummy_read_table(smu);
 963
 964         ret = smu_free_memory_pool(smu);
 965         if (ret)
 966                 return ret;
 967
 968         ret = smu_fini_fb_allocations(smu);
 969         if (ret)
 970                 return ret;
 971
 972         ret = smu_fini_power(smu);
 973         if (ret) {
 974                 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
 975                 return ret;
 976         }
 977
 978         ret = smu_fini_smc_tables(smu);
 979         if (ret) {
 980                 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
 981                 return ret;
 982         }
 983
 984         return 0;
 985 }
 986
 987 static void smu_throttling_logging_work_fn(struct work_struct *work)
 988 {
 989         struct smu_context *smu = container_of(work, struct smu_context,
 990                                                throttling_logging_work);
 991
 992         smu_log_thermal_throttling(smu);
 993 }
 994
 995 static void smu_interrupt_work_fn(struct work_struct *work)
 996 {
 997         struct smu_context *smu = container_of(work, struct smu_context,
 998                                                interrupt_work);
 999
1000         mutex_lock(&smu->mutex);
1001
1002         if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work)
1003                 smu->ppt_funcs->interrupt_work(smu);
1004
1005         mutex_unlock(&smu->mutex);
1006 }
1007
1008 static int smu_sw_init(void *handle)
1009 {
1010         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1011         struct smu_context *smu = &adev->smu;
1012         int ret;
1013
1014         smu->pool_size = adev->pm.smu_prv_buffer_size;
1015         smu->smu_feature.feature_num = SMU_FEATURE_MAX;
1016         mutex_init(&smu->smu_feature.mutex);
1017         bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
1018         bitmap_zero(smu->smu_feature.enabled, SMU_FEATURE_MAX);
1019         bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
1020
1021         mutex_init(&smu->sensor_lock);
1022         mutex_init(&smu->metrics_lock);
1023         mutex_init(&smu->message_lock);
1024
1025         INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
1026         INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn);
1027         atomic64_set(&smu->throttle_int_counter, 0);
1028         smu->watermarks_bitmap = 0;
1029         smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1030         smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1031
1032         atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
1033         atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
1034         mutex_init(&smu->smu_power.power_gate.vcn_gate_lock);
1035         mutex_init(&smu->smu_power.power_gate.jpeg_gate_lock);
1036
1037         smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
1038         smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
1039         smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
1040         smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
1041         smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
1042         smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
1043         smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
1044         smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
1045
1046         smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1047         smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1048         smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
1049         smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
1050         smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
1051         smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
1052         smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
1053         smu->display_config = &adev->pm.pm_display_cfg;
1054
1055         smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1056         smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1057
1058         ret = smu_init_microcode(smu);
1059         if (ret) {
1060                 dev_err(adev->dev, "Failed to load smu firmware!\n");
1061                 return ret;
1062         }
1063
1064         ret = smu_smc_table_sw_init(smu);
1065         if (ret) {
1066                 dev_err(adev->dev, "Failed to sw init smc table!\n");
1067                 return ret;
1068         }
1069
1070         ret = smu_register_irq_handler(smu);
1071         if (ret) {
1072                 dev_err(adev->dev, "Failed to register smc irq handler!\n");
1073                 return ret;
1074         }
1075
1076         /* If there is no way to query fan control mode, fan control is not supported */
1077         if (!smu->ppt_funcs->get_fan_control_mode)
1078                 smu->adev->pm.no_fan = true;
1079
1080         return 0;
1081 }
1082
1083 static int smu_sw_fini(void *handle)
1084 {
1085         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1086         struct smu_context *smu = &adev->smu;
1087         int ret;
1088
1089         ret = smu_smc_table_sw_fini(smu);
1090         if (ret) {
1091                 dev_err(adev->dev, "Failed to sw fini smc table!\n");
1092                 return ret;
1093         }
1094
1095         smu_fini_microcode(smu);
1096
1097         return 0;
1098 }
1099
1100 static int smu_get_thermal_temperature_range(struct smu_context *smu)
1101 {
1102         struct amdgpu_device *adev = smu->adev;
1103         struct smu_temperature_range *range =
1104                                 &smu->thermal_range;
1105         int ret = 0;
1106
1107         if (!smu->ppt_funcs->get_thermal_temperature_range)
1108                 return 0;
1109
1110         ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range);
1111         if (ret)
1112                 return ret;
1113
1114         adev->pm.dpm.thermal.min_temp = range->min;
1115         adev->pm.dpm.thermal.max_temp = range->max;
1116         adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max;
1117         adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min;
1118         adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max;
1119         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max;
1120         adev->pm.dpm.thermal.min_mem_temp = range->mem_min;
1121         adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max;
1122         adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max;
1123
1124         return ret;
1125 }
1126
1127 static int smu_smc_hw_setup(struct smu_context *smu)
1128 {
1129         struct amdgpu_device *adev = smu->adev;
1130         uint32_t pcie_gen = 0, pcie_width = 0;
1131         int ret = 0;
1132
1133         if (adev->in_suspend && smu_is_dpm_running(smu)) {
1134                 dev_info(adev->dev, "dpm has been enabled\n");
1135                 /* this is needed specifically */
1136                 if ((adev->asic_type >= CHIP_SIENNA_CICHLID) &&
1137                     (adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
1138                         ret = smu_system_features_control(smu, true);
1139                 return ret;
1140         }
1141
1142         ret = smu_init_display_count(smu, 0);
1143         if (ret) {
1144                 dev_info(adev->dev, "Failed to pre-set display count as 0!\n");
1145                 return ret;
1146         }
1147
1148         ret = smu_set_driver_table_location(smu);
1149         if (ret) {
1150                 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
1151                 return ret;
1152         }
1153
1154         /*
1155          * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1156          */
1157         ret = smu_set_tool_table_location(smu);
1158         if (ret) {
1159                 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
1160                 return ret;
1161         }
1162
1163         /*
1164          * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1165          * pool location.
1166          */
1167         ret = smu_notify_memory_pool_location(smu);
1168         if (ret) {
1169                 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n");
1170                 return ret;
1171         }
1172
1173         /* smu_dump_pptable(smu); */
1174         /*
1175          * Copy pptable bo in the vram to smc with SMU MSGs such as
1176          * SetDriverDramAddr and TransferTableDram2Smu.
1177          */
1178         ret = smu_write_pptable(smu);
1179         if (ret) {
1180                 dev_err(adev->dev, "Failed to transfer pptable to SMC!\n");
1181                 return ret;
1182         }
1183
1184         /* issue Run*Btc msg */
1185         ret = smu_run_btc(smu);
1186         if (ret)
1187                 return ret;
1188
1189         ret = smu_feature_set_allowed_mask(smu);
1190         if (ret) {
1191                 dev_err(adev->dev, "Failed to set driver allowed features mask!\n");
1192                 return ret;
1193         }
1194
1195         ret = smu_system_features_control(smu, true);
1196         if (ret) {
1197                 dev_err(adev->dev, "Failed to enable requested dpm features!\n");
1198                 return ret;
1199         }
1200
1201         if (!smu_is_dpm_running(smu))
1202                 dev_info(adev->dev, "dpm has been disabled\n");
1203
1204         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1205                 pcie_gen = 3;
1206         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1207                 pcie_gen = 2;
1208         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1209                 pcie_gen = 1;
1210         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1211                 pcie_gen = 0;
1212
1213         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1214          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1215          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
1216          */
1217         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1218                 pcie_width = 6;
1219         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1220                 pcie_width = 5;
1221         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1222                 pcie_width = 4;
1223         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1224                 pcie_width = 3;
1225         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1226                 pcie_width = 2;
1227         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1228                 pcie_width = 1;
1229         ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1230         if (ret) {
1231                 dev_err(adev->dev, "Attempt to override pcie params failed!\n");
1232                 return ret;
1233         }
1234
1235         ret = smu_get_thermal_temperature_range(smu);
1236         if (ret) {
1237                 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n");
1238                 return ret;
1239         }
1240
1241         ret = smu_enable_thermal_alert(smu);
1242         if (ret) {
1243                 dev_err(adev->dev, "Failed to enable thermal alert!\n");
1244                 return ret;
1245         }
1246
1247         /*
1248          * Set initialized values (get from vbios) to dpm tables context such as
1249          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1250          * type of clks.
1251          */
1252         ret = smu_set_default_dpm_table(smu);
1253         if (ret) {
1254                 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
1255                 return ret;
1256         }
1257
1258         ret = smu_notify_display_change(smu);
1259         if (ret)
1260                 return ret;
1261
1262         /*
1263          * Set min deep sleep dce fclk with bootup value from vbios via
1264          * SetMinDeepSleepDcefclk MSG.
1265          */
1266         ret = smu_set_min_dcef_deep_sleep(smu,
1267                                           smu->smu_table.boot_values.dcefclk / 100);
1268         if (ret)
1269                 return ret;
1270
1271         return ret;
1272 }
1273
1274 static int smu_start_smc_engine(struct smu_context *smu)
1275 {
1276         struct amdgpu_device *adev = smu->adev;
1277         int ret = 0;
1278
1279         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1280                 if (adev->asic_type < CHIP_NAVI10) {
1281                         if (smu->ppt_funcs->load_microcode) {
1282                                 ret = smu->ppt_funcs->load_microcode(smu);
1283                                 if (ret)
1284                                         return ret;
1285                         }
1286                 }
1287         }
1288
1289         if (smu->ppt_funcs->check_fw_status) {
1290                 ret = smu->ppt_funcs->check_fw_status(smu);
1291                 if (ret) {
1292                         dev_err(adev->dev, "SMC is not ready\n");
1293                         return ret;
1294                 }
1295         }
1296
1297         /*
1298          * Send msg GetDriverIfVersion to check if the return value is equal
1299          * with DRIVER_IF_VERSION of smc header.
1300          */
1301         ret = smu_check_fw_version(smu);
1302         if (ret)
1303                 return ret;
1304
1305         return ret;
1306 }
1307
1308 static int smu_hw_init(void *handle)
1309 {
1310         int ret;
1311         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1312         struct smu_context *smu = &adev->smu;
1313
1314         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
1315                 smu->pm_enabled = false;
1316                 return 0;
1317         }
1318
1319         ret = smu_start_smc_engine(smu);
1320         if (ret) {
1321                 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1322                 return ret;
1323         }
1324
1325         if (smu->is_apu) {
1326                 smu_powergate_sdma(&adev->smu, false);
1327                 smu_dpm_set_vcn_enable(smu, true);
1328                 smu_dpm_set_jpeg_enable(smu, true);
1329                 smu_set_gfx_cgpg(&adev->smu, true);
1330         }
1331
1332         if (!smu->pm_enabled)
1333                 return 0;
1334
1335         /* get boot_values from vbios to set revision, gfxclk, and etc. */
1336         ret = smu_get_vbios_bootup_values(smu);
1337         if (ret) {
1338                 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n");
1339                 return ret;
1340         }
1341
1342         ret = smu_setup_pptable(smu);
1343         if (ret) {
1344                 dev_err(adev->dev, "Failed to setup pptable!\n");
1345                 return ret;
1346         }
1347
1348         ret = smu_get_driver_allowed_feature_mask(smu);
1349         if (ret)
1350                 return ret;
1351
1352         ret = smu_smc_hw_setup(smu);
1353         if (ret) {
1354                 dev_err(adev->dev, "Failed to setup smc hw!\n");
1355                 return ret;
1356         }
1357
1358         /*
1359          * Move maximum sustainable clock retrieving here considering
1360          * 1. It is not needed on resume(from S3).
1361          * 2. DAL settings come between .hw_init and .late_init of SMU.
1362          *    And DAL needs to know the maximum sustainable clocks. Thus
1363          *    it cannot be put in .late_init().
1364          */
1365         ret = smu_init_max_sustainable_clocks(smu);
1366         if (ret) {
1367                 dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
1368                 return ret;
1369         }
1370
1371         adev->pm.dpm_enabled = true;
1372
1373         dev_info(adev->dev, "SMU is initialized successfully!\n");
1374
1375         return 0;
1376 }
1377
1378 static int smu_disable_dpms(struct smu_context *smu)
1379 {
1380         struct amdgpu_device *adev = smu->adev;
1381         int ret = 0;
1382         bool use_baco = !smu->is_apu &&
1383                 ((amdgpu_in_reset(adev) &&
1384                   (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1385                  ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev)));
1386
1387         /*
1388          * For custom pptable uploading, skip the DPM features
1389          * disable process on Navi1x ASICs.
1390          *   - As the gfx related features are under control of
1391          *     RLC on those ASICs. RLC reinitialization will be
1392          *     needed to reenable them. That will cost much more
1393          *     efforts.
1394          *
1395          *   - SMU firmware can handle the DPM reenablement
1396          *     properly.
1397          */
1398         if (smu->uploading_custom_pp_table &&
1399             (adev->asic_type >= CHIP_NAVI10) &&
1400             (adev->asic_type <= CHIP_DIMGREY_CAVEFISH))
1401                 return smu_disable_all_features_with_exception(smu,
1402                                                                true,
1403                                                                SMU_FEATURE_COUNT);
1404
1405         /*
1406          * For Sienna_Cichlid, PMFW will handle the features disablement properly
1407          * on BACO in. Driver involvement is unnecessary.
1408          */
1409         if (((adev->asic_type == CHIP_SIENNA_CICHLID) ||
1410              ((adev->asic_type >= CHIP_NAVI10) && (adev->asic_type <= CHIP_NAVI12))) &&
1411              use_baco)
1412                 return smu_disable_all_features_with_exception(smu,
1413                                                                true,
1414                                                                SMU_FEATURE_BACO_BIT);
1415
1416         /*
1417          * For gpu reset, runpm and hibernation through BACO,
1418          * BACO feature has to be kept enabled.
1419          */
1420         if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
1421                 ret = smu_disable_all_features_with_exception(smu,
1422                                                               false,
1423                                                               SMU_FEATURE_BACO_BIT);
1424                 if (ret)
1425                         dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
1426         } else {
1427                 ret = smu_system_features_control(smu, false);
1428                 if (ret)
1429                         dev_err(adev->dev, "Failed to disable smu features.\n");
1430         }
1431
1432         if (adev->asic_type >= CHIP_NAVI10 &&
1433             adev->gfx.rlc.funcs->stop)
1434                 adev->gfx.rlc.funcs->stop(adev);
1435
1436         return ret;
1437 }
1438
1439 static int smu_smc_hw_cleanup(struct smu_context *smu)
1440 {
1441         struct amdgpu_device *adev = smu->adev;
1442         int ret = 0;
1443
1444         cancel_work_sync(&smu->throttling_logging_work);
1445         cancel_work_sync(&smu->interrupt_work);
1446
1447         ret = smu_disable_thermal_alert(smu);
1448         if (ret) {
1449                 dev_err(adev->dev, "Fail to disable thermal alert!\n");
1450                 return ret;
1451         }
1452
1453         ret = smu_disable_dpms(smu);
1454         if (ret) {
1455                 dev_err(adev->dev, "Fail to disable dpm features!\n");
1456                 return ret;
1457         }
1458
1459         return 0;
1460 }
1461
1462 static int smu_hw_fini(void *handle)
1463 {
1464         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1465         struct smu_context *smu = &adev->smu;
1466
1467         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1468                 return 0;
1469
1470         if (smu->is_apu) {
1471                 smu_powergate_sdma(&adev->smu, true);
1472         }
1473
1474         smu_dpm_set_vcn_enable(smu, false);
1475         smu_dpm_set_jpeg_enable(smu, false);
1476
1477         adev->vcn.cur_state = AMD_PG_STATE_GATE;
1478         adev->jpeg.cur_state = AMD_PG_STATE_GATE;
1479
1480         if (!smu->pm_enabled)
1481                 return 0;
1482
1483         adev->pm.dpm_enabled = false;
1484
1485         return smu_smc_hw_cleanup(smu);
1486 }
1487
1488 static int smu_reset(struct smu_context *smu)
1489 {
1490         struct amdgpu_device *adev = smu->adev;
1491         int ret;
1492
1493         amdgpu_gfx_off_ctrl(smu->adev, false);
1494
1495         ret = smu_hw_fini(adev);
1496         if (ret)
1497                 return ret;
1498
1499         ret = smu_hw_init(adev);
1500         if (ret)
1501                 return ret;
1502
1503         ret = smu_late_init(adev);
1504         if (ret)
1505                 return ret;
1506
1507         amdgpu_gfx_off_ctrl(smu->adev, true);
1508
1509         return 0;
1510 }
1511
1512 static int smu_suspend(void *handle)
1513 {
1514         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1515         struct smu_context *smu = &adev->smu;
1516         int ret;
1517
1518         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1519                 return 0;
1520
1521         if (!smu->pm_enabled)
1522                 return 0;
1523
1524         adev->pm.dpm_enabled = false;
1525
1526         ret = smu_smc_hw_cleanup(smu);
1527         if (ret)
1528                 return ret;
1529
1530         smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1531
1532         /* skip CGPG when in S0ix */
1533         if (smu->is_apu && !adev->in_s0ix)
1534                 smu_set_gfx_cgpg(&adev->smu, false);
1535
1536         return 0;
1537 }
1538
1539 static int smu_resume(void *handle)
1540 {
1541         int ret;
1542         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1543         struct smu_context *smu = &adev->smu;
1544
1545         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1546                 return 0;
1547
1548         if (!smu->pm_enabled)
1549                 return 0;
1550
1551         dev_info(adev->dev, "SMU is resuming...\n");
1552
1553         ret = smu_start_smc_engine(smu);
1554         if (ret) {
1555                 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1556                 return ret;
1557         }
1558
1559         ret = smu_smc_hw_setup(smu);
1560         if (ret) {
1561                 dev_err(adev->dev, "Failed to setup smc hw!\n");
1562                 return ret;
1563         }
1564
1565         if (smu->is_apu)
1566                 smu_set_gfx_cgpg(&adev->smu, true);
1567
1568         smu->disable_uclk_switch = 0;
1569
1570         adev->pm.dpm_enabled = true;
1571
1572         dev_info(adev->dev, "SMU is resumed successfully!\n");
1573
1574         return 0;
1575 }
1576
1577 static int smu_display_configuration_change(void *handle,
1578                                             const struct amd_pp_display_configuration *display_config)
1579 {
1580         struct smu_context *smu = handle;
1581         int index = 0;
1582         int num_of_active_display = 0;
1583
1584         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1585                 return -EOPNOTSUPP;
1586
1587         if (!display_config)
1588                 return -EINVAL;
1589
1590         mutex_lock(&smu->mutex);
1591
1592         smu_set_min_dcef_deep_sleep(smu,
1593                                     display_config->min_dcef_deep_sleep_set_clk / 100);
1594
1595         for (index = 0; index < display_config->num_path_including_non_display; index++) {
1596                 if (display_config->displays[index].controller_id != 0)
1597                         num_of_active_display++;
1598         }
1599
1600         mutex_unlock(&smu->mutex);
1601
1602         return 0;
1603 }
1604
1605 static int smu_set_clockgating_state(void *handle,
1606                                      enum amd_clockgating_state state)
1607 {
1608         return 0;
1609 }
1610
1611 static int smu_set_powergating_state(void *handle,
1612                                      enum amd_powergating_state state)
1613 {
1614         return 0;
1615 }
1616
1617 static int smu_enable_umd_pstate(void *handle,
1618                       enum amd_dpm_forced_level *level)
1619 {
1620         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1621                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1622                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1623                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1624
1625         struct smu_context *smu = (struct smu_context*)(handle);
1626         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1627
1628         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1629                 return -EINVAL;
1630
1631         if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1632                 /* enter umd pstate, save current level, disable gfx cg*/
1633                 if (*level & profile_mode_mask) {
1634                         smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1635                         smu_dpm_ctx->enable_umd_pstate = true;
1636                         smu_gpo_control(smu, false);
1637                         amdgpu_device_ip_set_powergating_state(smu->adev,
1638                                                                AMD_IP_BLOCK_TYPE_GFX,
1639                                                                AMD_PG_STATE_UNGATE);
1640                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1641                                                                AMD_IP_BLOCK_TYPE_GFX,
1642                                                                AMD_CG_STATE_UNGATE);
1643                         smu_gfx_ulv_control(smu, false);
1644                         smu_deep_sleep_control(smu, false);
1645                         amdgpu_asic_update_umd_stable_pstate(smu->adev, true);
1646                 }
1647         } else {
1648                 /* exit umd pstate, restore level, enable gfx cg*/
1649                 if (!(*level & profile_mode_mask)) {
1650                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1651                                 *level = smu_dpm_ctx->saved_dpm_level;
1652                         smu_dpm_ctx->enable_umd_pstate = false;
1653                         amdgpu_asic_update_umd_stable_pstate(smu->adev, false);
1654                         smu_deep_sleep_control(smu, true);
1655                         smu_gfx_ulv_control(smu, true);
1656                         amdgpu_device_ip_set_clockgating_state(smu->adev,
1657                                                                AMD_IP_BLOCK_TYPE_GFX,
1658                                                                AMD_CG_STATE_GATE);
1659                         amdgpu_device_ip_set_powergating_state(smu->adev,
1660                                                                AMD_IP_BLOCK_TYPE_GFX,
1661                                                                AMD_PG_STATE_GATE);
1662                         smu_gpo_control(smu, true);
1663                 }
1664         }
1665
1666         return 0;
1667 }
1668
1669 static int smu_bump_power_profile_mode(struct smu_context *smu,
1670                                            long *param,
1671                                            uint32_t param_size)
1672 {
1673         int ret = 0;
1674
1675         if (smu->ppt_funcs->set_power_profile_mode)
1676                 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
1677
1678         return ret;
1679 }
1680
1681 static int smu_adjust_power_state_dynamic(struct smu_context *smu,
1682                                    enum amd_dpm_forced_level level,
1683                                    bool skip_display_settings)
1684 {
1685         int ret = 0;
1686         int index = 0;
1687         long workload;
1688         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1689
1690         if (!skip_display_settings) {
1691                 ret = smu_display_config_changed(smu);
1692                 if (ret) {
1693                         dev_err(smu->adev->dev, "Failed to change display config!");
1694                         return ret;
1695                 }
1696         }
1697
1698         ret = smu_apply_clocks_adjust_rules(smu);
1699         if (ret) {
1700                 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
1701                 return ret;
1702         }
1703
1704         if (!skip_display_settings) {
1705                 ret = smu_notify_smc_display_config(smu);
1706                 if (ret) {
1707                         dev_err(smu->adev->dev, "Failed to notify smc display config!");
1708                         return ret;
1709                 }
1710         }
1711
1712         if (smu_dpm_ctx->dpm_level != level) {
1713                 ret = smu_asic_set_performance_level(smu, level);
1714                 if (ret) {
1715                         dev_err(smu->adev->dev, "Failed to set performance level!");
1716                         return ret;
1717                 }
1718
1719                 /* update the saved copy */
1720                 smu_dpm_ctx->dpm_level = level;
1721         }
1722
1723         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
1724                 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1725                 index = fls(smu->workload_mask);
1726                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1727                 workload = smu->workload_setting[index];
1728
1729                 if (smu->power_profile_mode != workload)
1730                         smu_bump_power_profile_mode(smu, &workload, 0);
1731         }
1732
1733         return ret;
1734 }
1735
1736 static int smu_handle_task(struct smu_context *smu,
1737                            enum amd_dpm_forced_level level,
1738                            enum amd_pp_task task_id,
1739                            bool lock_needed)
1740 {
1741         int ret = 0;
1742
1743         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1744                 return -EOPNOTSUPP;
1745
1746         if (lock_needed)
1747                 mutex_lock(&smu->mutex);
1748
1749         switch (task_id) {
1750         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1751                 ret = smu_pre_display_config_changed(smu);
1752                 if (ret)
1753                         goto out;
1754                 ret = smu_adjust_power_state_dynamic(smu, level, false);
1755                 break;
1756         case AMD_PP_TASK_COMPLETE_INIT:
1757         case AMD_PP_TASK_READJUST_POWER_STATE:
1758                 ret = smu_adjust_power_state_dynamic(smu, level, true);
1759                 break;
1760         default:
1761                 break;
1762         }
1763
1764 out:
1765         if (lock_needed)
1766                 mutex_unlock(&smu->mutex);
1767
1768         return ret;
1769 }
1770
1771 static int smu_handle_dpm_task(void *handle,
1772                                enum amd_pp_task task_id,
1773                                enum amd_pm_state_type *user_state)
1774 {
1775         struct smu_context *smu = handle;
1776         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1777
1778         return smu_handle_task(smu, smu_dpm->dpm_level, task_id, true);
1779
1780 }
1781
1782 static int smu_switch_power_profile(void *handle,
1783                                     enum PP_SMC_POWER_PROFILE type,
1784                                     bool en)
1785 {
1786         struct smu_context *smu = handle;
1787         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1788         long workload;
1789         uint32_t index;
1790
1791         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1792                 return -EOPNOTSUPP;
1793
1794         if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1795                 return -EINVAL;
1796
1797         mutex_lock(&smu->mutex);
1798
1799         if (!en) {
1800                 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1801                 index = fls(smu->workload_mask);
1802                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1803                 workload = smu->workload_setting[index];
1804         } else {
1805                 smu->workload_mask |= (1 << smu->workload_prority[type]);
1806                 index = fls(smu->workload_mask);
1807                 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1808                 workload = smu->workload_setting[index];
1809         }
1810
1811         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
1812                 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
1813                 smu_bump_power_profile_mode(smu, &workload, 0);
1814
1815         mutex_unlock(&smu->mutex);
1816
1817         return 0;
1818 }
1819
1820 static enum amd_dpm_forced_level smu_get_performance_level(void *handle)
1821 {
1822         struct smu_context *smu = handle;
1823         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1824         enum amd_dpm_forced_level level;
1825
1826         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1827                 return -EOPNOTSUPP;
1828
1829         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1830                 return -EINVAL;
1831
1832         mutex_lock(&(smu->mutex));
1833         level = smu_dpm_ctx->dpm_level;
1834         mutex_unlock(&(smu->mutex));
1835
1836         return level;
1837 }
1838
1839 static int smu_force_performance_level(void *handle,
1840                                        enum amd_dpm_forced_level level)
1841 {
1842         struct smu_context *smu = handle;
1843         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1844         int ret = 0;
1845
1846         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1847                 return -EOPNOTSUPP;
1848
1849         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1850                 return -EINVAL;
1851
1852         mutex_lock(&smu->mutex);
1853
1854         ret = smu_enable_umd_pstate(smu, &level);
1855         if (ret) {
1856                 mutex_unlock(&smu->mutex);
1857                 return ret;
1858         }
1859
1860         ret = smu_handle_task(smu, level,
1861                               AMD_PP_TASK_READJUST_POWER_STATE,
1862                               false);
1863
1864         mutex_unlock(&smu->mutex);
1865
1866         /* reset user dpm clock state */
1867         if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1868                 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask));
1869                 smu->user_dpm_profile.clk_dependency = 0;
1870         }
1871
1872         return ret;
1873 }
1874
1875 static int smu_set_display_count(void *handle, uint32_t count)
1876 {
1877         struct smu_context *smu = handle;
1878         int ret = 0;
1879
1880         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1881                 return -EOPNOTSUPP;
1882
1883         mutex_lock(&smu->mutex);
1884         ret = smu_init_display_count(smu, count);
1885         mutex_unlock(&smu->mutex);
1886
1887         return ret;
1888 }
1889
1890 static int smu_force_smuclk_levels(struct smu_context *smu,
1891                          enum smu_clk_type clk_type,
1892                          uint32_t mask)
1893 {
1894         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1895         int ret = 0;
1896
1897         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1898                 return -EOPNOTSUPP;
1899
1900         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1901                 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
1902                 return -EINVAL;
1903         }
1904
1905         mutex_lock(&smu->mutex);
1906
1907         if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) {
1908                 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1909                 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
1910                         smu->user_dpm_profile.clk_mask[clk_type] = mask;
1911                         smu_set_user_clk_dependencies(smu, clk_type);
1912                 }
1913         }
1914
1915         mutex_unlock(&smu->mutex);
1916
1917         return ret;
1918 }
1919
1920 static int smu_force_ppclk_levels(void *handle,
1921                                   enum pp_clock_type type,
1922                                   uint32_t mask)
1923 {
1924         struct smu_context *smu = handle;
1925         enum smu_clk_type clk_type;
1926
1927         switch (type) {
1928         case PP_SCLK:
1929                 clk_type = SMU_SCLK; break;
1930         case PP_MCLK:
1931                 clk_type = SMU_MCLK; break;
1932         case PP_PCIE:
1933                 clk_type = SMU_PCIE; break;
1934         case PP_SOCCLK:
1935                 clk_type = SMU_SOCCLK; break;
1936         case PP_FCLK:
1937                 clk_type = SMU_FCLK; break;
1938         case PP_DCEFCLK:
1939                 clk_type = SMU_DCEFCLK; break;
1940         case PP_VCLK:
1941                 clk_type = SMU_VCLK; break;
1942         case PP_DCLK:
1943                 clk_type = SMU_DCLK; break;
1944         case OD_SCLK:
1945                 clk_type = SMU_OD_SCLK; break;
1946         case OD_MCLK:
1947                 clk_type = SMU_OD_MCLK; break;
1948         case OD_VDDC_CURVE:
1949                 clk_type = SMU_OD_VDDC_CURVE; break;
1950         case OD_RANGE:
1951                 clk_type = SMU_OD_RANGE; break;
1952         default:
1953                 return -EINVAL;
1954         }
1955
1956         return smu_force_smuclk_levels(smu, clk_type, mask);
1957 }
1958
1959 /*
1960  * On system suspending or resetting, the dpm_enabled
1961  * flag will be cleared. So that those SMU services which
1962  * are not supported will be gated.
1963  * However, the mp1 state setting should still be granted
1964  * even if the dpm_enabled cleared.
1965  */
1966 static int smu_set_mp1_state(void *handle,
1967                              enum pp_mp1_state mp1_state)
1968 {
1969         struct smu_context *smu = handle;
1970         int ret = 0;
1971
1972         if (!smu->pm_enabled)
1973                 return -EOPNOTSUPP;
1974
1975         mutex_lock(&smu->mutex);
1976
1977         if (smu->ppt_funcs &&
1978             smu->ppt_funcs->set_mp1_state)
1979                 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state);
1980
1981         mutex_unlock(&smu->mutex);
1982
1983         return ret;
1984 }
1985
1986 static int smu_set_df_cstate(void *handle,
1987                              enum pp_df_cstate state)
1988 {
1989         struct smu_context *smu = handle;
1990         int ret = 0;
1991
1992         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1993                 return -EOPNOTSUPP;
1994
1995         if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
1996                 return 0;
1997
1998         mutex_lock(&smu->mutex);
1999
2000         ret = smu->ppt_funcs->set_df_cstate(smu, state);
2001         if (ret)
2002                 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
2003
2004         mutex_unlock(&smu->mutex);
2005
2006         return ret;
2007 }
2008
2009 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
2010 {
2011         int ret = 0;
2012
2013         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2014                 return -EOPNOTSUPP;
2015
2016         if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down)
2017                 return 0;
2018
2019         mutex_lock(&smu->mutex);
2020
2021         ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en);
2022         if (ret)
2023                 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n");
2024
2025         mutex_unlock(&smu->mutex);
2026
2027         return ret;
2028 }
2029
2030 int smu_write_watermarks_table(struct smu_context *smu)
2031 {
2032         int ret = 0;
2033
2034         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2035                 return -EOPNOTSUPP;
2036
2037         mutex_lock(&smu->mutex);
2038
2039         ret = smu_set_watermarks_table(smu, NULL);
2040
2041         mutex_unlock(&smu->mutex);
2042
2043         return ret;
2044 }
2045
2046 static int smu_set_watermarks_for_clock_ranges(void *handle,
2047                                                struct pp_smu_wm_range_sets *clock_ranges)
2048 {
2049         struct smu_context *smu = handle;
2050         int ret = 0;
2051
2052         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2053                 return -EOPNOTSUPP;
2054
2055         if (smu->disable_watermark)
2056                 return 0;
2057
2058         mutex_lock(&smu->mutex);
2059
2060         ret = smu_set_watermarks_table(smu, clock_ranges);
2061
2062         mutex_unlock(&smu->mutex);
2063
2064         return ret;
2065 }
2066
2067 int smu_set_ac_dc(struct smu_context *smu)
2068 {
2069         int ret = 0;
2070
2071         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2072                 return -EOPNOTSUPP;
2073
2074         /* controlled by firmware */
2075         if (smu->dc_controlled_by_gpio)
2076                 return 0;
2077
2078         mutex_lock(&smu->mutex);
2079         ret = smu_set_power_source(smu,
2080                                    smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
2081                                    SMU_POWER_SOURCE_DC);
2082         if (ret)
2083                 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
2084                        smu->adev->pm.ac_power ? "AC" : "DC");
2085         mutex_unlock(&smu->mutex);
2086
2087         return ret;
2088 }
2089
2090 const struct amd_ip_funcs smu_ip_funcs = {
2091         .name = "smu",
2092         .early_init = smu_early_init,
2093         .late_init = smu_late_init,
2094         .sw_init = smu_sw_init,
2095         .sw_fini = smu_sw_fini,
2096         .hw_init = smu_hw_init,
2097         .hw_fini = smu_hw_fini,
2098         .suspend = smu_suspend,
2099         .resume = smu_resume,
2100         .is_idle = NULL,
2101         .check_soft_reset = NULL,
2102         .wait_for_idle = NULL,
2103         .soft_reset = NULL,
2104         .set_clockgating_state = smu_set_clockgating_state,
2105         .set_powergating_state = smu_set_powergating_state,
2106         .enable_umd_pstate = smu_enable_umd_pstate,
2107 };
2108
2109 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
2110 {
2111         .type = AMD_IP_BLOCK_TYPE_SMC,
2112         .major = 11,
2113         .minor = 0,
2114         .rev = 0,
2115         .funcs = &smu_ip_funcs,
2116 };
2117
2118 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
2119 {
2120         .type = AMD_IP_BLOCK_TYPE_SMC,
2121         .major = 12,
2122         .minor = 0,
2123         .rev = 0,
2124         .funcs = &smu_ip_funcs,
2125 };
2126
2127 const struct amdgpu_ip_block_version smu_v13_0_ip_block =
2128 {
2129         .type = AMD_IP_BLOCK_TYPE_SMC,
2130         .major = 13,
2131         .minor = 0,
2132         .rev = 0,
2133         .funcs = &smu_ip_funcs,
2134 };
2135
2136 static int smu_load_microcode(void *handle)
2137 {
2138         struct smu_context *smu = handle;
2139         struct amdgpu_device *adev = smu->adev;
2140         int ret = 0;
2141
2142         if (!smu->pm_enabled)
2143                 return -EOPNOTSUPP;
2144
2145         /* This should be used for non PSP loading */
2146         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
2147                 return 0;
2148
2149         if (smu->ppt_funcs->load_microcode) {
2150                 ret = smu->ppt_funcs->load_microcode(smu);
2151                 if (ret) {
2152                         dev_err(adev->dev, "Load microcode failed\n");
2153                         return ret;
2154                 }
2155         }
2156
2157         if (smu->ppt_funcs->check_fw_status) {
2158                 ret = smu->ppt_funcs->check_fw_status(smu);
2159                 if (ret) {
2160                         dev_err(adev->dev, "SMC is not ready\n");
2161                         return ret;
2162                 }
2163         }
2164
2165         return ret;
2166 }
2167
2168 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
2169 {
2170         int ret = 0;
2171
2172         mutex_lock(&smu->mutex);
2173
2174         if (smu->ppt_funcs->set_gfx_cgpg)
2175                 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2176
2177         mutex_unlock(&smu->mutex);
2178
2179         return ret;
2180 }
2181
2182 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
2183 {
2184         struct smu_context *smu = handle;
2185         u32 percent;
2186         int ret = 0;
2187
2188         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2189                 return -EOPNOTSUPP;
2190
2191         mutex_lock(&smu->mutex);
2192
2193         if (smu->ppt_funcs->set_fan_speed_percent) {
2194                 percent = speed * 100 / smu->fan_max_rpm;
2195                 ret = smu->ppt_funcs->set_fan_speed_percent(smu, percent);
2196                 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
2197                         smu->user_dpm_profile.fan_speed_percent = percent;
2198         }
2199
2200         mutex_unlock(&smu->mutex);
2201
2202         return ret;
2203 }
2204
2205 /**
2206  * smu_get_power_limit - Request one of the SMU Power Limits
2207  *
2208  * @handle: pointer to smu context
2209  * @limit: requested limit is written back to this variable
2210  * @pp_limit_level: &pp_power_limit_level which limit of the power to return
2211  * @pp_power_type: &pp_power_type type of power
2212  * Return:  0 on success, <0 on error
2213  *
2214  */
2215 int smu_get_power_limit(void *handle,
2216                         uint32_t *limit,
2217                         enum pp_power_limit_level pp_limit_level,
2218                         enum pp_power_type pp_power_type)
2219 {
2220         struct smu_context *smu = handle;
2221         enum smu_ppt_limit_level limit_level;
2222         uint32_t limit_type;
2223         int ret = 0;
2224
2225         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2226                 return -EOPNOTSUPP;
2227
2228         switch(pp_power_type) {
2229         case PP_PWR_TYPE_SUSTAINED:
2230                 limit_type = SMU_DEFAULT_PPT_LIMIT;
2231                 break;
2232         case PP_PWR_TYPE_FAST:
2233                 limit_type = SMU_FAST_PPT_LIMIT;
2234                 break;
2235         default:
2236                 return -EOPNOTSUPP;
2237                 break;
2238         }
2239
2240         switch(pp_limit_level){
2241         case PP_PWR_LIMIT_CURRENT:
2242                 limit_level = SMU_PPT_LIMIT_CURRENT;
2243                 break;
2244         case PP_PWR_LIMIT_DEFAULT:
2245                 limit_level = SMU_PPT_LIMIT_DEFAULT;
2246                 break;
2247         case PP_PWR_LIMIT_MAX:
2248                 limit_level = SMU_PPT_LIMIT_MAX;
2249                 break;
2250         case PP_PWR_LIMIT_MIN:
2251         default:
2252                 return -EOPNOTSUPP;
2253                 break;
2254         }
2255
2256         mutex_lock(&smu->mutex);
2257
2258         if (limit_type != SMU_DEFAULT_PPT_LIMIT) {
2259                 if (smu->ppt_funcs->get_ppt_limit)
2260                         ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level);
2261         } else {
2262                 switch (limit_level) {
2263                 case SMU_PPT_LIMIT_CURRENT:
2264                         if ((smu->adev->asic_type == CHIP_ALDEBARAN) ||
2265                              (smu->adev->asic_type == CHIP_SIENNA_CICHLID) ||
2266                              (smu->adev->asic_type == CHIP_NAVY_FLOUNDER) ||
2267                              (smu->adev->asic_type == CHIP_DIMGREY_CAVEFISH) ||
2268                              (smu->adev->asic_type == CHIP_BEIGE_GOBY))
2269                                 ret = smu_get_asic_power_limits(smu,
2270                                                                 &smu->current_power_limit,
2271                                                                 NULL,
2272                                                                 NULL);
2273                         *limit = smu->current_power_limit;
2274                         break;
2275                 case SMU_PPT_LIMIT_DEFAULT:
2276                         *limit = smu->default_power_limit;
2277                         break;
2278                 case SMU_PPT_LIMIT_MAX:
2279                         *limit = smu->max_power_limit;
2280                         break;
2281                 default:
2282                         break;
2283                 }
2284         }
2285
2286         mutex_unlock(&smu->mutex);
2287
2288         return ret;
2289 }
2290
2291 static int smu_set_power_limit(void *handle, uint32_t limit)
2292 {
2293         struct smu_context *smu = handle;
2294         uint32_t limit_type = limit >> 24;
2295         int ret = 0;
2296
2297         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2298                 return -EOPNOTSUPP;
2299
2300         mutex_lock(&smu->mutex);
2301
2302         if (limit_type != SMU_DEFAULT_PPT_LIMIT)
2303                 if (smu->ppt_funcs->set_power_limit) {
2304                         ret = smu->ppt_funcs->set_power_limit(smu, limit);
2305                         goto out;
2306                 }
2307
2308         if (limit > smu->max_power_limit) {
2309                 dev_err(smu->adev->dev,
2310                         "New power limit (%d) is over the max allowed %d\n",
2311                         limit, smu->max_power_limit);
2312                 ret = -EINVAL;
2313                 goto out;
2314         }
2315
2316         if (!limit)
2317                 limit = smu->current_power_limit;
2318
2319         if (smu->ppt_funcs->set_power_limit) {
2320                 ret = smu->ppt_funcs->set_power_limit(smu, limit);
2321                 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
2322                         smu->user_dpm_profile.power_limit = limit;
2323         }
2324
2325 out:
2326         mutex_unlock(&smu->mutex);
2327
2328         return ret;
2329 }
2330
2331 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2332 {
2333         int ret = 0;
2334
2335         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2336                 return -EOPNOTSUPP;
2337
2338         mutex_lock(&smu->mutex);
2339
2340         if (smu->ppt_funcs->print_clk_levels)
2341                 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2342
2343         mutex_unlock(&smu->mutex);
2344
2345         return ret;
2346 }
2347
2348 static int smu_print_ppclk_levels(void *handle,
2349                                   enum pp_clock_type type,
2350                                   char *buf)
2351 {
2352         struct smu_context *smu = handle;
2353         enum smu_clk_type clk_type;
2354
2355         switch (type) {
2356         case PP_SCLK:
2357                 clk_type = SMU_SCLK; break;
2358         case PP_MCLK:
2359                 clk_type = SMU_MCLK; break;
2360         case PP_PCIE:
2361                 clk_type = SMU_PCIE; break;
2362         case PP_SOCCLK:
2363                 clk_type = SMU_SOCCLK; break;
2364         case PP_FCLK:
2365                 clk_type = SMU_FCLK; break;
2366         case PP_DCEFCLK:
2367                 clk_type = SMU_DCEFCLK; break;
2368         case PP_VCLK:
2369                 clk_type = SMU_VCLK; break;
2370         case PP_DCLK:
2371                 clk_type = SMU_DCLK; break;
2372         case OD_SCLK:
2373                 clk_type = SMU_OD_SCLK; break;
2374         case OD_MCLK:
2375                 clk_type = SMU_OD_MCLK; break;
2376         case OD_VDDC_CURVE:
2377                 clk_type = SMU_OD_VDDC_CURVE; break;
2378         case OD_RANGE:
2379                 clk_type = SMU_OD_RANGE; break;
2380         case OD_VDDGFX_OFFSET:
2381                 clk_type = SMU_OD_VDDGFX_OFFSET; break;
2382         case OD_CCLK:
2383                 clk_type = SMU_OD_CCLK; break;
2384         default:
2385                 return -EINVAL;
2386         }
2387
2388         return smu_print_smuclk_levels(smu, clk_type, buf);
2389 }
2390
2391 static int smu_od_edit_dpm_table(void *handle,
2392                                  enum PP_OD_DPM_TABLE_COMMAND type,
2393                                  long *input, uint32_t size)
2394 {
2395         struct smu_context *smu = handle;
2396         int ret = 0;
2397
2398         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2399                 return -EOPNOTSUPP;
2400
2401         mutex_lock(&smu->mutex);
2402
2403         if (smu->ppt_funcs->od_edit_dpm_table) {
2404                 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2405         }
2406
2407         mutex_unlock(&smu->mutex);
2408
2409         return ret;
2410 }
2411
2412 static int smu_read_sensor(void *handle,
2413                            int sensor,
2414                            void *data,
2415                            int *size_arg)
2416 {
2417         struct smu_context *smu = handle;
2418         struct smu_umd_pstate_table *pstate_table =
2419                                 &smu->pstate_table;
2420         int ret = 0;
2421         uint32_t *size, size_val;
2422
2423         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2424                 return -EOPNOTSUPP;
2425
2426         if (!data || !size_arg)
2427                 return -EINVAL;
2428
2429         size_val = *size_arg;
2430         size = &size_val;
2431
2432         mutex_lock(&smu->mutex);
2433
2434         if (smu->ppt_funcs->read_sensor)
2435                 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
2436                         goto unlock;
2437
2438         switch (sensor) {
2439         case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
2440                 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
2441                 *size = 4;
2442                 break;
2443         case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
2444                 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
2445                 *size = 4;
2446                 break;
2447         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2448                 ret = smu_feature_get_enabled_mask(smu, (uint32_t *)data, 2);
2449                 *size = 8;
2450                 break;
2451         case AMDGPU_PP_SENSOR_UVD_POWER:
2452                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
2453                 *size = 4;
2454                 break;
2455         case AMDGPU_PP_SENSOR_VCE_POWER:
2456                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
2457                 *size = 4;
2458                 break;
2459         case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
2460                 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1;
2461                 *size = 4;
2462                 break;
2463         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
2464                 *(uint32_t *)data = 0;
2465                 *size = 4;
2466                 break;
2467         default:
2468                 *size = 0;
2469                 ret = -EOPNOTSUPP;
2470                 break;
2471         }
2472
2473 unlock:
2474         mutex_unlock(&smu->mutex);
2475
2476         // assign uint32_t to int
2477         *size_arg = size_val;
2478
2479         return ret;
2480 }
2481
2482 static int smu_get_power_profile_mode(void *handle, char *buf)
2483 {
2484         struct smu_context *smu = handle;
2485         int ret = 0;
2486
2487         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2488                 return -EOPNOTSUPP;
2489
2490         mutex_lock(&smu->mutex);
2491
2492         if (smu->ppt_funcs->get_power_profile_mode)
2493                 ret = smu->ppt_funcs->get_power_profile_mode(smu, buf);
2494
2495         mutex_unlock(&smu->mutex);
2496
2497         return ret;
2498 }
2499
2500 static int smu_set_power_profile_mode(void *handle,
2501                                       long *param,
2502                                       uint32_t param_size)
2503 {
2504         struct smu_context *smu = handle;
2505         int ret = 0;
2506
2507         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2508                 return -EOPNOTSUPP;
2509
2510         mutex_lock(&smu->mutex);
2511
2512         smu_bump_power_profile_mode(smu, param, param_size);
2513
2514         mutex_unlock(&smu->mutex);
2515
2516         return ret;
2517 }
2518
2519
2520 static u32 smu_get_fan_control_mode(void *handle)
2521 {
2522         struct smu_context *smu = handle;
2523         u32 ret = 0;
2524
2525         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2526                 return AMD_FAN_CTRL_NONE;
2527
2528         mutex_lock(&smu->mutex);
2529
2530         if (smu->ppt_funcs->get_fan_control_mode)
2531                 ret = smu->ppt_funcs->get_fan_control_mode(smu);
2532
2533         mutex_unlock(&smu->mutex);
2534
2535         return ret;
2536 }
2537
2538 static int smu_set_fan_control_mode(struct smu_context *smu, int value)
2539 {
2540         int ret = 0;
2541
2542         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2543                 return  -EOPNOTSUPP;
2544
2545         mutex_lock(&smu->mutex);
2546
2547         if (smu->ppt_funcs->set_fan_control_mode) {
2548                 ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2549                 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
2550                         smu->user_dpm_profile.fan_mode = value;
2551         }
2552
2553         mutex_unlock(&smu->mutex);
2554
2555         /* reset user dpm fan speed */
2556         if (!ret && value != AMD_FAN_CTRL_MANUAL &&
2557                         !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
2558                 smu->user_dpm_profile.fan_speed_percent = 0;
2559
2560         return ret;
2561 }
2562
2563 static void smu_pp_set_fan_control_mode(void *handle, u32 value)
2564 {
2565         struct smu_context *smu = handle;
2566
2567         smu_set_fan_control_mode(smu, value);
2568 }
2569
2570
2571 static int smu_get_fan_speed_percent(void *handle, u32 *speed)
2572 {
2573         struct smu_context *smu = handle;
2574         int ret = 0;
2575         uint32_t percent;
2576
2577         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2578                 return -EOPNOTSUPP;
2579
2580         mutex_lock(&smu->mutex);
2581
2582         if (smu->ppt_funcs->get_fan_speed_percent) {
2583                 ret = smu->ppt_funcs->get_fan_speed_percent(smu, &percent);
2584                 if (!ret) {
2585                         *speed = percent > 100 ? 100 : percent;
2586                 }
2587         }
2588
2589         mutex_unlock(&smu->mutex);
2590
2591
2592         return ret;
2593 }
2594
2595 static int smu_set_fan_speed_percent(void *handle, u32 speed)
2596 {
2597         struct smu_context *smu = handle;
2598         int ret = 0;
2599
2600         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2601                 return -EOPNOTSUPP;
2602
2603         mutex_lock(&smu->mutex);
2604
2605         if (smu->ppt_funcs->set_fan_speed_percent) {
2606                 if (speed > 100)
2607                         speed = 100;
2608                 ret = smu->ppt_funcs->set_fan_speed_percent(smu, speed);
2609                 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
2610                         smu->user_dpm_profile.fan_speed_percent = speed;
2611         }
2612
2613         mutex_unlock(&smu->mutex);
2614
2615         return ret;
2616 }
2617
2618 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed)
2619 {
2620         struct smu_context *smu = handle;
2621         int ret = 0;
2622         u32 percent;
2623
2624         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2625                 return -EOPNOTSUPP;
2626
2627         mutex_lock(&smu->mutex);
2628
2629         if (smu->ppt_funcs->get_fan_speed_percent) {
2630                 ret = smu->ppt_funcs->get_fan_speed_percent(smu, &percent);
2631                 *speed = percent * smu->fan_max_rpm / 100;
2632         }
2633
2634         mutex_unlock(&smu->mutex);
2635
2636         return ret;
2637 }
2638
2639 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk)
2640 {
2641         struct smu_context *smu = handle;
2642         int ret = 0;
2643
2644         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2645                 return -EOPNOTSUPP;
2646
2647         mutex_lock(&smu->mutex);
2648
2649         ret = smu_set_min_dcef_deep_sleep(smu, clk);
2650
2651         mutex_unlock(&smu->mutex);
2652
2653         return ret;
2654 }
2655
2656 static int smu_get_clock_by_type_with_latency(void *handle,
2657                                               enum amd_pp_clock_type type,
2658                                               struct pp_clock_levels_with_latency *clocks)
2659 {
2660         struct smu_context *smu = handle;
2661         enum smu_clk_type clk_type;
2662         int ret = 0;
2663
2664         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2665                 return -EOPNOTSUPP;
2666
2667         mutex_lock(&smu->mutex);
2668
2669         if (smu->ppt_funcs->get_clock_by_type_with_latency) {
2670                 switch (type) {
2671                 case amd_pp_sys_clock:
2672                         clk_type = SMU_GFXCLK;
2673                         break;
2674                 case amd_pp_mem_clock:
2675                         clk_type = SMU_MCLK;
2676                         break;
2677                 case amd_pp_dcef_clock:
2678                         clk_type = SMU_DCEFCLK;
2679                         break;
2680                 case amd_pp_disp_clock:
2681                         clk_type = SMU_DISPCLK;
2682                         break;
2683                 default:
2684                         dev_err(smu->adev->dev, "Invalid clock type!\n");
2685                         mutex_unlock(&smu->mutex);
2686                         return -EINVAL;
2687                 }
2688
2689                 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2690         }
2691
2692         mutex_unlock(&smu->mutex);
2693
2694         return ret;
2695 }
2696
2697 static int smu_display_clock_voltage_request(void *handle,
2698                                              struct pp_display_clock_request *clock_req)
2699 {
2700         struct smu_context *smu = handle;
2701         int ret = 0;
2702
2703         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2704                 return -EOPNOTSUPP;
2705
2706         mutex_lock(&smu->mutex);
2707
2708         if (smu->ppt_funcs->display_clock_voltage_request)
2709                 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2710
2711         mutex_unlock(&smu->mutex);
2712
2713         return ret;
2714 }
2715
2716
2717 static int smu_display_disable_memory_clock_switch(void *handle,
2718                                                    bool disable_memory_clock_switch)
2719 {
2720         struct smu_context *smu = handle;
2721         int ret = -EINVAL;
2722
2723         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2724                 return -EOPNOTSUPP;
2725
2726         mutex_lock(&smu->mutex);
2727
2728         if (smu->ppt_funcs->display_disable_memory_clock_switch)
2729                 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2730
2731         mutex_unlock(&smu->mutex);
2732
2733         return ret;
2734 }
2735
2736 static int smu_set_xgmi_pstate(void *handle,
2737                                uint32_t pstate)
2738 {
2739         struct smu_context *smu = handle;
2740         int ret = 0;
2741
2742         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2743                 return -EOPNOTSUPP;
2744
2745         mutex_lock(&smu->mutex);
2746
2747         if (smu->ppt_funcs->set_xgmi_pstate)
2748                 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2749
2750         mutex_unlock(&smu->mutex);
2751
2752         if(ret)
2753                 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n");
2754
2755         return ret;
2756 }
2757
2758 static int smu_get_baco_capability(void *handle, bool *cap)
2759 {
2760         struct smu_context *smu = handle;
2761         int ret = 0;
2762
2763         *cap = false;
2764
2765         if (!smu->pm_enabled)
2766                 return 0;
2767
2768         mutex_lock(&smu->mutex);
2769
2770         if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2771                 *cap = smu->ppt_funcs->baco_is_support(smu);
2772
2773         mutex_unlock(&smu->mutex);
2774
2775         return ret;
2776 }
2777
2778 static int smu_baco_set_state(void *handle, int state)
2779 {
2780         struct smu_context *smu = handle;
2781         int ret = 0;
2782
2783         if (!smu->pm_enabled)
2784                 return -EOPNOTSUPP;
2785
2786         if (state == 0) {
2787                 mutex_lock(&smu->mutex);
2788
2789                 if (smu->ppt_funcs->baco_exit)
2790                         ret = smu->ppt_funcs->baco_exit(smu);
2791
2792                 mutex_unlock(&smu->mutex);
2793         } else if (state == 1) {
2794                 mutex_lock(&smu->mutex);
2795
2796                 if (smu->ppt_funcs->baco_enter)
2797                         ret = smu->ppt_funcs->baco_enter(smu);
2798
2799                 mutex_unlock(&smu->mutex);
2800
2801         } else {
2802                 return -EINVAL;
2803         }
2804
2805         if (ret)
2806                 dev_err(smu->adev->dev, "Failed to %s BACO state!\n",
2807                                 (state)?"enter":"exit");
2808
2809         return ret;
2810 }
2811
2812 bool smu_mode1_reset_is_support(struct smu_context *smu)
2813 {
2814         bool ret = false;
2815
2816         if (!smu->pm_enabled)
2817                 return false;
2818
2819         mutex_lock(&smu->mutex);
2820
2821         if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support)
2822                 ret = smu->ppt_funcs->mode1_reset_is_support(smu);
2823
2824         mutex_unlock(&smu->mutex);
2825
2826         return ret;
2827 }
2828
2829 bool smu_mode2_reset_is_support(struct smu_context *smu)
2830 {
2831         bool ret = false;
2832
2833         if (!smu->pm_enabled)
2834                 return false;
2835
2836         mutex_lock(&smu->mutex);
2837
2838         if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support)
2839                 ret = smu->ppt_funcs->mode2_reset_is_support(smu);
2840
2841         mutex_unlock(&smu->mutex);
2842
2843         return ret;
2844 }
2845
2846 int smu_mode1_reset(struct smu_context *smu)
2847 {
2848         int ret = 0;
2849
2850         if (!smu->pm_enabled)
2851                 return -EOPNOTSUPP;
2852
2853         mutex_lock(&smu->mutex);
2854
2855         if (smu->ppt_funcs->mode1_reset)
2856                 ret = smu->ppt_funcs->mode1_reset(smu);
2857
2858         mutex_unlock(&smu->mutex);
2859
2860         return ret;
2861 }
2862
2863 static int smu_mode2_reset(void *handle)
2864 {
2865         struct smu_context *smu = handle;
2866         int ret = 0;
2867
2868         if (!smu->pm_enabled)
2869                 return -EOPNOTSUPP;
2870
2871         mutex_lock(&smu->mutex);
2872
2873         if (smu->ppt_funcs->mode2_reset)
2874                 ret = smu->ppt_funcs->mode2_reset(smu);
2875
2876         mutex_unlock(&smu->mutex);
2877
2878         if (ret)
2879                 dev_err(smu->adev->dev, "Mode2 reset failed!\n");
2880
2881         return ret;
2882 }
2883
2884 static int smu_get_max_sustainable_clocks_by_dc(void *handle,
2885                                                 struct pp_smu_nv_clock_table *max_clocks)
2886 {
2887         struct smu_context *smu = handle;
2888         int ret = 0;
2889
2890         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2891                 return -EOPNOTSUPP;
2892
2893         mutex_lock(&smu->mutex);
2894
2895         if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2896                 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2897
2898         mutex_unlock(&smu->mutex);
2899
2900         return ret;
2901 }
2902
2903 static int smu_get_uclk_dpm_states(void *handle,
2904                                    unsigned int *clock_values_in_khz,
2905                                    unsigned int *num_states)
2906 {
2907         struct smu_context *smu = handle;
2908         int ret = 0;
2909
2910         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2911                 return -EOPNOTSUPP;
2912
2913         mutex_lock(&smu->mutex);
2914
2915         if (smu->ppt_funcs->get_uclk_dpm_states)
2916                 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2917
2918         mutex_unlock(&smu->mutex);
2919
2920         return ret;
2921 }
2922
2923 static enum amd_pm_state_type smu_get_current_power_state(void *handle)
2924 {
2925         struct smu_context *smu = handle;
2926         enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2927
2928         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2929                 return -EOPNOTSUPP;
2930
2931         mutex_lock(&smu->mutex);
2932
2933         if (smu->ppt_funcs->get_current_power_state)
2934                 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2935
2936         mutex_unlock(&smu->mutex);
2937
2938         return pm_state;
2939 }
2940
2941 static int smu_get_dpm_clock_table(void *handle,
2942                                    struct dpm_clocks *clock_table)
2943 {
2944         struct smu_context *smu = handle;
2945         int ret = 0;
2946
2947         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2948                 return -EOPNOTSUPP;
2949
2950         mutex_lock(&smu->mutex);
2951
2952         if (smu->ppt_funcs->get_dpm_clock_table)
2953                 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2954
2955         mutex_unlock(&smu->mutex);
2956
2957         return ret;
2958 }
2959
2960 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table)
2961 {
2962         struct smu_context *smu = handle;
2963         ssize_t size;
2964
2965         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2966                 return -EOPNOTSUPP;
2967
2968         if (!smu->ppt_funcs->get_gpu_metrics)
2969                 return -EOPNOTSUPP;
2970
2971         mutex_lock(&smu->mutex);
2972
2973         size = smu->ppt_funcs->get_gpu_metrics(smu, table);
2974
2975         mutex_unlock(&smu->mutex);
2976
2977         return size;
2978 }
2979
2980 static int smu_enable_mgpu_fan_boost(void *handle)
2981 {
2982         struct smu_context *smu = handle;
2983         int ret = 0;
2984
2985         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2986                 return -EOPNOTSUPP;
2987
2988         mutex_lock(&smu->mutex);
2989
2990         if (smu->ppt_funcs->enable_mgpu_fan_boost)
2991                 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu);
2992
2993         mutex_unlock(&smu->mutex);
2994
2995         return ret;
2996 }
2997
2998 static int smu_gfx_state_change_set(void *handle,
2999                                     uint32_t state)
3000 {
3001         struct smu_context *smu = handle;
3002         int ret = 0;
3003
3004         mutex_lock(&smu->mutex);
3005         if (smu->ppt_funcs->gfx_state_change_set)
3006                 ret = smu->ppt_funcs->gfx_state_change_set(smu, state);
3007         mutex_unlock(&smu->mutex);
3008
3009         return ret;
3010 }
3011
3012 int smu_set_light_sbr(struct smu_context *smu, bool enable)
3013 {
3014         int ret = 0;
3015
3016         mutex_lock(&smu->mutex);
3017         if (smu->ppt_funcs->set_light_sbr)
3018                 ret = smu->ppt_funcs->set_light_sbr(smu, enable);
3019         mutex_unlock(&smu->mutex);
3020
3021         return ret;
3022 }
3023
3024 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size)
3025 {
3026         struct smu_context *smu = handle;
3027         struct smu_table_context *smu_table = &smu->smu_table;
3028         struct smu_table *memory_pool = &smu_table->memory_pool;
3029
3030         if (!addr || !size)
3031                 return -EINVAL;
3032
3033         *addr = NULL;
3034         *size = 0;
3035         mutex_lock(&smu->mutex);
3036         if (memory_pool->bo) {
3037                 *addr = memory_pool->cpu_addr;
3038                 *size = memory_pool->size;
3039         }
3040         mutex_unlock(&smu->mutex);
3041
3042         return 0;
3043 }
3044
3045 static const struct amd_pm_funcs swsmu_pm_funcs = {
3046         /* export for sysfs */
3047         .set_fan_control_mode    = smu_pp_set_fan_control_mode,
3048         .get_fan_control_mode    = smu_get_fan_control_mode,
3049         .set_fan_speed_percent   = smu_set_fan_speed_percent,
3050         .get_fan_speed_percent   = smu_get_fan_speed_percent,
3051         .force_clock_level       = smu_force_ppclk_levels,
3052         .print_clock_levels      = smu_print_ppclk_levels,
3053         .force_performance_level = smu_force_performance_level,
3054         .read_sensor             = smu_read_sensor,
3055         .get_performance_level   = smu_get_performance_level,
3056         .get_current_power_state = smu_get_current_power_state,
3057         .get_fan_speed_rpm       = smu_get_fan_speed_rpm,
3058         .set_fan_speed_rpm       = smu_set_fan_speed_rpm,
3059         .get_pp_num_states       = smu_get_power_num_states,
3060         .get_pp_table            = smu_sys_get_pp_table,
3061         .set_pp_table            = smu_sys_set_pp_table,
3062         .switch_power_profile    = smu_switch_power_profile,
3063         /* export to amdgpu */
3064         .dispatch_tasks          = smu_handle_dpm_task,
3065         .load_firmware           = smu_load_microcode,
3066         .set_powergating_by_smu  = smu_dpm_set_power_gate,
3067         .set_power_limit         = smu_set_power_limit,
3068         .get_power_limit         = smu_get_power_limit,
3069         .get_power_profile_mode  = smu_get_power_profile_mode,
3070         .set_power_profile_mode  = smu_set_power_profile_mode,
3071         .odn_edit_dpm_table      = smu_od_edit_dpm_table,
3072         .set_mp1_state           = smu_set_mp1_state,
3073         .gfx_state_change_set    = smu_gfx_state_change_set,
3074         /* export to DC */
3075         .get_sclk                         = smu_get_sclk,
3076         .get_mclk                         = smu_get_mclk,
3077         .display_configuration_change     = smu_display_configuration_change,
3078         .get_clock_by_type_with_latency   = smu_get_clock_by_type_with_latency,
3079         .display_clock_voltage_request    = smu_display_clock_voltage_request,
3080         .enable_mgpu_fan_boost            = smu_enable_mgpu_fan_boost,
3081         .set_active_display_count         = smu_set_display_count,
3082         .set_min_deep_sleep_dcefclk       = smu_set_deep_sleep_dcefclk,
3083         .get_asic_baco_capability         = smu_get_baco_capability,
3084         .set_asic_baco_state              = smu_baco_set_state,
3085         .get_ppfeature_status             = smu_sys_get_pp_feature_mask,
3086         .set_ppfeature_status             = smu_sys_set_pp_feature_mask,
3087         .asic_reset_mode_2                = smu_mode2_reset,
3088         .set_df_cstate                    = smu_set_df_cstate,
3089         .set_xgmi_pstate                  = smu_set_xgmi_pstate,
3090         .get_gpu_metrics                  = smu_sys_get_gpu_metrics,
3091         .set_watermarks_for_clock_ranges     = smu_set_watermarks_for_clock_ranges,
3092         .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch,
3093         .get_max_sustainable_clocks_by_dc    = smu_get_max_sustainable_clocks_by_dc,
3094         .get_uclk_dpm_states              = smu_get_uclk_dpm_states,
3095         .get_dpm_clock_table              = smu_get_dpm_clock_table,
3096         .get_smu_prv_buf_details = smu_get_prv_buffer_details,
3097 };
3098
3099 int smu_wait_for_event(struct amdgpu_device *adev, enum smu_event_type event,
3100                        uint64_t event_arg)
3101 {
3102         int ret = -EINVAL;
3103         struct smu_context *smu = &adev->smu;
3104
3105         if (smu->ppt_funcs->wait_for_event) {
3106                 mutex_lock(&smu->mutex);
3107                 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg);
3108                 mutex_unlock(&smu->mutex);
3109         }
3110
3111         return ret;
3112 }