drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/pci.h>
  25
  26 #include "pp_debug.h"
  27 #include "smumgr.h"
  28 #include "smu74.h"
  29 #include "smu_ucode_xfer_vi.h"
  30 #include "polaris10_smumgr.h"
  31 #include "smu74_discrete.h"
  32 #include "smu/smu_7_1_3_d.h"
  33 #include "smu/smu_7_1_3_sh_mask.h"
  34 #include "gmc/gmc_8_1_d.h"
  35 #include "gmc/gmc_8_1_sh_mask.h"
  36 #include "oss/oss_3_0_d.h"
  37 #include "gca/gfx_8_0_d.h"
  38 #include "bif/bif_5_0_d.h"
  39 #include "bif/bif_5_0_sh_mask.h"
  40 #include "ppatomctrl.h"
  41 #include "cgs_common.h"
  42 #include "smu7_ppsmc.h"
  43 #include "smu7_smumgr.h"
  44
  45 #include "smu7_dyn_defaults.h"
  46
  47 #include "smu7_hwmgr.h"
  48 #include "hardwaremanager.h"
  49 #include "atombios.h"
  50 #include "pppcielanes.h"
  51
  52 #include "dce/dce_10_0_d.h"
  53 #include "dce/dce_10_0_sh_mask.h"
  54
  55 #define POLARIS10_SMC_SIZE 0x20000
  56 #define POWERTUNE_DEFAULT_SET_MAX    1
  57 #define VDDC_VDDCI_DELTA            200
  58 #define MC_CG_ARB_FREQ_F1           0x0b
  59
  60 static const struct polaris10_pt_defaults polaris10_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
  61         /* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt,
  62          * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */
  63         { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
  64         { 0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
  65         { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } },
  66 };
  67
  68 static const sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = {
  69                         {VCO_2_4, POSTDIV_DIV_BY_16,  75, 160, 112},
  70                         {VCO_3_6, POSTDIV_DIV_BY_16, 112, 224, 160},
  71                         {VCO_2_4, POSTDIV_DIV_BY_8,   75, 160, 112},
  72                         {VCO_3_6, POSTDIV_DIV_BY_8,  112, 224, 160},
  73                         {VCO_2_4, POSTDIV_DIV_BY_4,   75, 160, 112},
  74                         {VCO_3_6, POSTDIV_DIV_BY_4,  112, 216, 160},
  75                         {VCO_2_4, POSTDIV_DIV_BY_2,   75, 160, 108},
  76                         {VCO_3_6, POSTDIV_DIV_BY_2,  112, 216, 160} };
  77
  78 #define PPPOLARIS10_TARGETACTIVITY_DFLT                     50
  79
  80 static const SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = {
  81         /*  Min      pcie   DeepSleep Activity  CgSpll      CgSpll    CcPwr  CcPwr  Sclk         Enabled      Enabled                       Voltage    Power */
  82         /* Voltage, DpmLevel, DivId,  Level,  FuncCntl3,  FuncCntl4,  DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */
  83         { 0x100ea446, 0x00, 0x03, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x30750000, 0x3000, 0, 0x2600, 0, 0, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
  84         { 0x400ea446, 0x01, 0x04, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x409c0000, 0x2000, 0, 0x1e00, 1, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
  85         { 0x740ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x50c30000, 0x2800, 0, 0x2000, 1, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } },
  86         { 0xa40ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x60ea0000, 0x3000, 0, 0x2600, 1, 1, 0x0004, 0x8f02, 0xffff, 0x2f00, 0x300e, 0x2700 } },
  87         { 0xd80ea446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x70110100, 0x3800, 0, 0x2c00, 1, 1, 0x0004, 0x1203, 0xffff, 0x3600, 0xc9e2, 0x2e00 } },
  88         { 0x3c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x80380100, 0x2000, 0, 0x1e00, 2, 1, 0x0004, 0x8300, 0xffff, 0x1f00, 0xcb5e, 0x1a00 } },
  89         { 0x6c0fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0x905f0100, 0x2400, 0, 0x1e00, 2, 1, 0x0004, 0x8901, 0xffff, 0x2300, 0x314c, 0x1d00 } },
  90         { 0xa00fa446, 0x01, 0x00, 0x3200, 0, 0, 0, 0, 0, 0, 0x01, 0x01, 0x0a, 0x00, 0x00, 0x00, { 0xa0860100, 0x2800, 0, 0x2000, 2, 1, 0x0004, 0x0c02, 0xffff, 0x2700, 0x6433, 0x2100 } }
  91 };
  92
  93 static const SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {
  94         0x100ea446, 0, 0x30750000, 0x01, 0x01, 0x01, 0x00, 0x00, 0x64, 0x00, 0x00, 0x1f00, 0x00, 0x00};
  95
  96 static int polaris10_perform_btc(struct pp_hwmgr *hwmgr)
  97 {
  98         int result = 0;
  99         struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
 100
 101         if (0 != smu_data->avfs_btc_param) {
 102                 if (0 != smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_PerformBtc, smu_data->avfs_btc_param,
 103                                         NULL)) {
 104                         pr_info("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed");
 105                         result = -1;
 106                 }
 107         }
 108         if (smu_data->avfs_btc_param > 1) {
 109                 /* Soft-Reset to reset the engine before loading uCode */
 110                 /* halt */
 111                 cgs_write_register(hwmgr->device, mmCP_MEC_CNTL, 0x50000000);
 112                 /* reset everything */
 113                 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0xffffffff);
 114                 cgs_write_register(hwmgr->device, mmGRBM_SOFT_RESET, 0);
 115         }
 116         return result;
 117 }
 118
 119
 120 static int polaris10_setup_graphics_level_structure(struct pp_hwmgr *hwmgr)
 121 {
 122         uint32_t vr_config;
 123         uint32_t dpm_table_start;
 124
 125         uint16_t u16_boot_mvdd;
 126         uint32_t graphics_level_address, vr_config_address, graphics_level_size;
 127
 128         graphics_level_size = sizeof(avfs_graphics_level_polaris10);
 129         u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE);
 130
 131         PP_ASSERT_WITH_CODE(0 == smu7_read_smc_sram_dword(hwmgr,
 132                                 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable),
 133                                 &dpm_table_start, 0x40000),
 134                         "[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table",
 135                         return -1);
 136
 137         /*  Default value for VRConfig = VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */
 138         vr_config = 0x01000500; /* Real value:0x50001 */
 139
 140         vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig);
 141
 142         PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, vr_config_address,
 143                                 (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000),
 144                         "[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC",
 145                         return -1);
 146
 147         graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
 148
 149         PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
 150                                 (uint8_t *)(&avfs_graphics_level_polaris10),
 151                                 graphics_level_size, 0x40000),
 152                         "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!",
 153                         return -1);
 154
 155         graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
 156
 157         PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
 158                                 (uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000),
 159                                 "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!",
 160                         return -1);
 161
 162         /* MVDD Boot value - neccessary for getting rid of the hang that occurs during Mclk DPM enablement */
 163
 164         graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd);
 165
 166         PP_ASSERT_WITH_CODE(0 == smu7_copy_bytes_to_smc(hwmgr, graphics_level_address,
 167                         (uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000),
 168                         "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!",
 169                         return -1);
 170
 171         return 0;
 172 }
 173
 174
 175 static int polaris10_avfs_event_mgr(struct pp_hwmgr *hwmgr)
 176 {
 177         struct smu7_smumgr *smu_data = (struct smu7_smumgr *)(hwmgr->smu_backend);
 178
 179         if (!hwmgr->avfs_supported)
 180                 return 0;
 181
 182         PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(hwmgr),
 183                 "[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU",
 184                 return -EINVAL);
 185
 186         if (smu_data->avfs_btc_param > 1) {
 187                 pr_info("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting.");
 188                 PP_ASSERT_WITH_CODE(0 == smu7_setup_pwr_virus(hwmgr),
 189                 "[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ",
 190                 return -EINVAL);
 191         }
 192
 193         PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(hwmgr),
 194                                 "[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled",
 195                          return -EINVAL);
 196
 197         return 0;
 198 }
 199
 200 static int polaris10_start_smu_in_protection_mode(struct pp_hwmgr *hwmgr)
 201 {
 202         int result = 0;
 203
 204         /* Wait for smc boot up */
 205         /* PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(smumgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0) */
 206
 207         /* Assert reset */
 208         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 209                                         SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 210
 211         result = smu7_upload_smu_firmware_image(hwmgr);
 212         if (result != 0)
 213                 return result;
 214
 215         /* Clear status */
 216         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_STATUS, 0);
 217
 218         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 219                                         SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 220
 221         /* De-assert reset */
 222         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 223                                         SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 224
 225
 226         PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, RCU_UC_EVENTS, INTERRUPTS_ENABLED, 1);
 227
 228
 229         /* Call Test SMU message with 0x20000 offset to trigger SMU start */
 230         smu7_send_msg_to_smc_offset(hwmgr);
 231
 232         /* Wait done bit to be set */
 233         /* Check pass/failed indicator */
 234
 235         PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, SMU_STATUS, SMU_DONE, 0);
 236
 237         if (1 != PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 238                                                 SMU_STATUS, SMU_PASS))
 239                 PP_ASSERT_WITH_CODE(false, "SMU Firmware start failed!", return -1);
 240
 241         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixFIRMWARE_FLAGS, 0);
 242
 243         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 244                                         SMC_SYSCON_RESET_CNTL, rst_reg, 1);
 245
 246         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 247                                         SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 248
 249         /* Wait for firmware to initialize */
 250         PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND, FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
 251
 252         return result;
 253 }
 254
 255 static int polaris10_start_smu_in_non_protection_mode(struct pp_hwmgr *hwmgr)
 256 {
 257         int result = 0;
 258
 259         /* wait for smc boot up */
 260         PHM_WAIT_VFPF_INDIRECT_FIELD_UNEQUAL(hwmgr, SMC_IND, RCU_UC_EVENTS, boot_seq_done, 0);
 261
 262         /* Clear firmware interrupt enable flag */
 263         /* PHM_WRITE_VFPF_INDIRECT_FIELD(pSmuMgr, SMC_IND, SMC_SYSCON_MISC_CNTL, pre_fetcher_en, 1); */
 264         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
 265                                 ixFIRMWARE_FLAGS, 0);
 266
 267         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 268                                         SMC_SYSCON_RESET_CNTL,
 269                                         rst_reg, 1);
 270
 271         result = smu7_upload_smu_firmware_image(hwmgr);
 272         if (result != 0)
 273                 return result;
 274
 275         /* Set smc instruct start point at 0x0 */
 276         smu7_program_jump_on_start(hwmgr);
 277
 278         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 279                                         SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0);
 280
 281         PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
 282                                         SMC_SYSCON_RESET_CNTL, rst_reg, 0);
 283
 284         /* Wait for firmware to initialize */
 285
 286         PHM_WAIT_VFPF_INDIRECT_FIELD(hwmgr, SMC_IND,
 287                                         FIRMWARE_FLAGS, INTERRUPTS_ENABLED, 1);
 288
 289         return result;
 290 }
 291
 292 static int polaris10_start_smu(struct pp_hwmgr *hwmgr)
 293 {
 294         int result = 0;
 295         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 296
 297         /* Only start SMC if SMC RAM is not running */
 298         if (!smu7_is_smc_ram_running(hwmgr) && hwmgr->not_vf) {
 299                 smu_data->protected_mode = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE));
 300                 smu_data->smu7_data.security_hard_key = (uint8_t) (PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL));
 301
 302                 /* Check if SMU is running in protected mode */
 303                 if (smu_data->protected_mode == 0)
 304                         result = polaris10_start_smu_in_non_protection_mode(hwmgr);
 305                 else
 306                         result = polaris10_start_smu_in_protection_mode(hwmgr);
 307
 308                 if (result != 0)
 309                         PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result);
 310
 311                 polaris10_avfs_event_mgr(hwmgr);
 312         }
 313
 314         /* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */
 315         smu7_read_smc_sram_dword(hwmgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters),
 316                                         &(smu_data->smu7_data.soft_regs_start), 0x40000);
 317
 318         result = smu7_request_smu_load_fw(hwmgr);
 319
 320         return result;
 321 }
 322
 323 static bool polaris10_is_hw_avfs_present(struct pp_hwmgr *hwmgr)
 324 {
 325         uint32_t efuse;
 326
 327         efuse = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixSMU_EFUSE_0 + (49*4));
 328         efuse &= 0x00000001;
 329         if (efuse)
 330                 return true;
 331
 332         return false;
 333 }
 334
 335 static int polaris10_smu_init(struct pp_hwmgr *hwmgr)
 336 {
 337         struct polaris10_smumgr *smu_data;
 338
 339         smu_data = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL);
 340         if (smu_data == NULL)
 341                 return -ENOMEM;
 342
 343         hwmgr->smu_backend = smu_data;
 344
 345         if (smu7_init(hwmgr)) {
 346                 kfree(smu_data);
 347                 return -EINVAL;
 348         }
 349
 350         return 0;
 351 }
 352
 353 static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr,
 354                 struct phm_ppt_v1_clock_voltage_dependency_table *dep_table,
 355                 uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
 356 {
 357         uint32_t i;
 358         uint16_t vddci;
 359         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 360
 361         *voltage = *mvdd = 0;
 362
 363         /* clock - voltage dependency table is empty table */
 364         if (dep_table->count == 0)
 365                 return -EINVAL;
 366
 367         for (i = 0; i < dep_table->count; i++) {
 368                 /* find first sclk bigger than request */
 369                 if (dep_table->entries[i].clk >= clock) {
 370                         *voltage |= (dep_table->entries[i].vddc *
 371                                         VOLTAGE_SCALE) << VDDC_SHIFT;
 372                         if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
 373                                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
 374                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
 375                         else if (dep_table->entries[i].vddci)
 376                                 *voltage |= (dep_table->entries[i].vddci *
 377                                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
 378                         else {
 379                                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
 380                                                 (dep_table->entries[i].vddc -
 381                                                                 (uint16_t)VDDC_VDDCI_DELTA));
 382                                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
 383                         }
 384
 385                         if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
 386                                 *mvdd = data->vbios_boot_state.mvdd_bootup_value *
 387                                         VOLTAGE_SCALE;
 388                         else if (dep_table->entries[i].mvdd)
 389                                 *mvdd = (uint32_t) dep_table->entries[i].mvdd *
 390                                         VOLTAGE_SCALE;
 391
 392                         *voltage |= 1 << PHASES_SHIFT;
 393                         return 0;
 394                 }
 395         }
 396
 397         /* sclk is bigger than max sclk in the dependence table */
 398         *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
 399
 400         if (SMU7_VOLTAGE_CONTROL_NONE == data->vddci_control)
 401                 *voltage |= (data->vbios_boot_state.vddci_bootup_value *
 402                                 VOLTAGE_SCALE) << VDDCI_SHIFT;
 403         else if (dep_table->entries[i-1].vddci) {
 404                 vddci = phm_find_closest_vddci(&(data->vddci_voltage_table),
 405                                 (dep_table->entries[i].vddc -
 406                                                 (uint16_t)VDDC_VDDCI_DELTA));
 407                 *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
 408         }
 409
 410         if (SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control)
 411                 *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE;
 412         else if (dep_table->entries[i].mvdd)
 413                 *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE;
 414
 415         return 0;
 416 }
 417
 418 static uint16_t scale_fan_gain_settings(uint16_t raw_setting)
 419 {
 420         uint32_t tmp;
 421         tmp = raw_setting * 4096 / 100;
 422         return (uint16_t)tmp;
 423 }
 424
 425 static int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
 426 {
 427         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 428
 429         const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
 430         SMU74_Discrete_DpmTable  *table = &(smu_data->smc_state_table);
 431         struct phm_ppt_v1_information *table_info =
 432                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 433         struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
 434         struct pp_advance_fan_control_parameters *fan_table =
 435                         &hwmgr->thermal_controller.advanceFanControlParameters;
 436         int i, j, k;
 437         const uint16_t *pdef1;
 438         const uint16_t *pdef2;
 439
 440         table->DefaultTdp = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
 441         table->TargetTdp  = PP_HOST_TO_SMC_US((uint16_t)(cac_dtp_table->usTDP * 128));
 442
 443         PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
 444                                 "Target Operating Temp is out of Range!",
 445                                 );
 446
 447         table->TemperatureLimitEdge = PP_HOST_TO_SMC_US(
 448                         cac_dtp_table->usTargetOperatingTemp * 256);
 449         table->TemperatureLimitHotspot = PP_HOST_TO_SMC_US(
 450                         cac_dtp_table->usTemperatureLimitHotspot * 256);
 451         table->FanGainEdge = PP_HOST_TO_SMC_US(
 452                         scale_fan_gain_settings(fan_table->usFanGainEdge));
 453         table->FanGainHotspot = PP_HOST_TO_SMC_US(
 454                         scale_fan_gain_settings(fan_table->usFanGainHotspot));
 455
 456         pdef1 = defaults->BAPMTI_R;
 457         pdef2 = defaults->BAPMTI_RC;
 458
 459         for (i = 0; i < SMU74_DTE_ITERATIONS; i++) {
 460                 for (j = 0; j < SMU74_DTE_SOURCES; j++) {
 461                         for (k = 0; k < SMU74_DTE_SINKS; k++) {
 462                                 table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);
 463                                 table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);
 464                                 pdef1++;
 465                                 pdef2++;
 466                         }
 467                 }
 468         }
 469
 470         return 0;
 471 }
 472
 473 static void polaris10_populate_zero_rpm_parameters(struct pp_hwmgr *hwmgr)
 474 {
 475         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 476         SMU74_Discrete_DpmTable  *table = &(smu_data->smc_state_table);
 477         uint16_t fan_stop_temp =
 478                 ((uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucFanStopTemperature) << 8;
 479         uint16_t fan_start_temp =
 480                 ((uint16_t)hwmgr->thermal_controller.advanceFanControlParameters.ucFanStartTemperature) << 8;
 481
 482         if (hwmgr->thermal_controller.advanceFanControlParameters.ucEnableZeroRPM) {
 483                 table->FanStartTemperature = PP_HOST_TO_SMC_US(fan_start_temp);
 484                 table->FanStopTemperature = PP_HOST_TO_SMC_US(fan_stop_temp);
 485         }
 486 }
 487
 488 static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr)
 489 {
 490         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 491         const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
 492
 493         smu_data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn;
 494         smu_data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC;
 495         smu_data->power_tune_table.SviLoadLineTrimVddC = 3;
 496         smu_data->power_tune_table.SviLoadLineOffsetVddC = 0;
 497
 498         return 0;
 499 }
 500
 501 static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr)
 502 {
 503         uint16_t tdc_limit;
 504         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 505         struct phm_ppt_v1_information *table_info =
 506                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 507         const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
 508
 509         tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128);
 510         smu_data->power_tune_table.TDC_VDDC_PkgLimit =
 511                         CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
 512         smu_data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
 513                         defaults->TDC_VDDC_ThrottleReleaseLimitPerc;
 514         smu_data->power_tune_table.TDC_MAWt = defaults->TDC_MAWt;
 515
 516         return 0;
 517 }
 518
 519 static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
 520 {
 521         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 522         const struct polaris10_pt_defaults *defaults = smu_data->power_tune_defaults;
 523         uint32_t temp;
 524
 525         if (smu7_read_smc_sram_dword(hwmgr,
 526                         fuse_table_offset +
 527                         offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl),
 528                         (uint32_t *)&temp, SMC_RAM_END))
 529                 PP_ASSERT_WITH_CODE(false,
 530                                 "Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
 531                                 return -EINVAL);
 532         else {
 533                 smu_data->power_tune_table.TdcWaterfallCtl = defaults->TdcWaterfallCtl;
 534                 smu_data->power_tune_table.LPMLTemperatureMin =
 535                                 (uint8_t)((temp >> 16) & 0xff);
 536                 smu_data->power_tune_table.LPMLTemperatureMax =
 537                                 (uint8_t)((temp >> 8) & 0xff);
 538                 smu_data->power_tune_table.Reserved = (uint8_t)(temp & 0xff);
 539         }
 540         return 0;
 541 }
 542
 543 static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
 544 {
 545         int i;
 546         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 547
 548         /* Currently not used. Set all to zero. */
 549         for (i = 0; i < 16; i++)
 550                 smu_data->power_tune_table.LPMLTemperatureScaler[i] = 0;
 551
 552         return 0;
 553 }
 554
 555 static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
 556 {
 557         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 558
 559 /* TO DO move to hwmgr */
 560         if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15))
 561                 || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity)
 562                 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity =
 563                         hwmgr->thermal_controller.advanceFanControlParameters.usDefaultFanOutputSensitivity;
 564
 565         smu_data->power_tune_table.FuzzyFan_PwmSetDelta = PP_HOST_TO_SMC_US(
 566                                 hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity);
 567         return 0;
 568 }
 569
 570 static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
 571 {
 572         int i;
 573         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 574
 575         /* Currently not used. Set all to zero. */
 576         for (i = 0; i < 16; i++)
 577                 smu_data->power_tune_table.GnbLPML[i] = 0;
 578
 579         return 0;
 580 }
 581
 582 static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
 583 {
 584         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 585         struct phm_ppt_v1_information *table_info =
 586                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 587         uint16_t hi_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd;
 588         uint16_t lo_sidd = smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd;
 589         struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
 590
 591         hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
 592         lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
 593
 594         smu_data->power_tune_table.BapmVddCBaseLeakageHiSidd =
 595                         CONVERT_FROM_HOST_TO_SMC_US(hi_sidd);
 596         smu_data->power_tune_table.BapmVddCBaseLeakageLoSidd =
 597                         CONVERT_FROM_HOST_TO_SMC_US(lo_sidd);
 598
 599         return 0;
 600 }
 601
 602 static int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr)
 603 {
 604         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 605         uint32_t pm_fuse_table_offset;
 606
 607         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
 608                         PHM_PlatformCaps_PowerContainment)) {
 609                 if (smu7_read_smc_sram_dword(hwmgr,
 610                                 SMU7_FIRMWARE_HEADER_LOCATION +
 611                                 offsetof(SMU74_Firmware_Header, PmFuseTable),
 612                                 &pm_fuse_table_offset, SMC_RAM_END))
 613                         PP_ASSERT_WITH_CODE(false,
 614                                         "Attempt to get pm_fuse_table_offset Failed!",
 615                                         return -EINVAL);
 616
 617                 if (polaris10_populate_svi_load_line(hwmgr))
 618                         PP_ASSERT_WITH_CODE(false,
 619                                         "Attempt to populate SviLoadLine Failed!",
 620                                         return -EINVAL);
 621
 622                 if (polaris10_populate_tdc_limit(hwmgr))
 623                         PP_ASSERT_WITH_CODE(false,
 624                                         "Attempt to populate TDCLimit Failed!", return -EINVAL);
 625
 626                 if (polaris10_populate_dw8(hwmgr, pm_fuse_table_offset))
 627                         PP_ASSERT_WITH_CODE(false,
 628                                         "Attempt to populate TdcWaterfallCtl, "
 629                                         "LPMLTemperature Min and Max Failed!",
 630                                         return -EINVAL);
 631
 632                 if (0 != polaris10_populate_temperature_scaler(hwmgr))
 633                         PP_ASSERT_WITH_CODE(false,
 634                                         "Attempt to populate LPMLTemperatureScaler Failed!",
 635                                         return -EINVAL);
 636
 637                 if (polaris10_populate_fuzzy_fan(hwmgr))
 638                         PP_ASSERT_WITH_CODE(false,
 639                                         "Attempt to populate Fuzzy Fan Control parameters Failed!",
 640                                         return -EINVAL);
 641
 642                 if (polaris10_populate_gnb_lpml(hwmgr))
 643                         PP_ASSERT_WITH_CODE(false,
 644                                         "Attempt to populate GnbLPML Failed!",
 645                                         return -EINVAL);
 646
 647                 if (polaris10_populate_bapm_vddc_base_leakage_sidd(hwmgr))
 648                         PP_ASSERT_WITH_CODE(false,
 649                                         "Attempt to populate BapmVddCBaseLeakage Hi and Lo "
 650                                         "Sidd Failed!", return -EINVAL);
 651
 652                 if (smu7_copy_bytes_to_smc(hwmgr, pm_fuse_table_offset,
 653                                 (uint8_t *)&smu_data->power_tune_table,
 654                                 (sizeof(struct SMU74_Discrete_PmFuses) - 92), SMC_RAM_END))
 655                         PP_ASSERT_WITH_CODE(false,
 656                                         "Attempt to download PmFuseTable Failed!",
 657                                         return -EINVAL);
 658         }
 659         return 0;
 660 }
 661
 662 static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
 663                         SMU74_Discrete_DpmTable *table)
 664 {
 665         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 666         uint32_t count, level;
 667
 668         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
 669                 count = data->mvdd_voltage_table.count;
 670                 if (count > SMU_MAX_SMIO_LEVELS)
 671                         count = SMU_MAX_SMIO_LEVELS;
 672                 for (level = 0; level < count; level++) {
 673                         table->SmioTable2.Pattern[level].Voltage =
 674                                 PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[level].value * VOLTAGE_SCALE);
 675                         /* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
 676                         table->SmioTable2.Pattern[level].Smio =
 677                                 (uint8_t) level;
 678                         table->Smio[level] |=
 679                                 data->mvdd_voltage_table.entries[level].smio_low;
 680                 }
 681                 table->SmioMask2 = data->mvdd_voltage_table.mask_low;
 682
 683                 table->MvddLevelCount = (uint32_t) PP_HOST_TO_SMC_UL(count);
 684         }
 685
 686         return 0;
 687 }
 688
 689 static int polaris10_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
 690                                         struct SMU74_Discrete_DpmTable *table)
 691 {
 692         uint32_t count, level;
 693         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 694
 695         count = data->vddc_voltage_table.count;
 696
 697         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->voltage_control) {
 698                 if (count > SMU_MAX_SMIO_LEVELS)
 699                         count = SMU_MAX_SMIO_LEVELS;
 700                 for (level = 0; level < count; ++level) {
 701                         table->SmioTable1.Pattern[level].Voltage =
 702                                 PP_HOST_TO_SMC_US(data->vddc_voltage_table.entries[level].value * VOLTAGE_SCALE);
 703                         table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
 704
 705                         table->Smio[level] |= data->vddc_voltage_table.entries[level].smio_low;
 706                 }
 707
 708                 table->SmioMask1 = data->vddc_voltage_table.mask_low;
 709         }
 710
 711         return 0;
 712 }
 713
 714 static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr,
 715                                         struct SMU74_Discrete_DpmTable *table)
 716 {
 717         uint32_t count, level;
 718         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 719
 720         count = data->vddci_voltage_table.count;
 721
 722         if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
 723                 if (count > SMU_MAX_SMIO_LEVELS)
 724                         count = SMU_MAX_SMIO_LEVELS;
 725                 for (level = 0; level < count; ++level) {
 726                         table->SmioTable1.Pattern[level].Voltage =
 727                                 PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[level].value * VOLTAGE_SCALE);
 728                         table->SmioTable1.Pattern[level].Smio = (uint8_t) level;
 729
 730                         table->Smio[level] |= data->vddci_voltage_table.entries[level].smio_low;
 731                 }
 732
 733                 table->SmioMask1 = data->vddci_voltage_table.mask_low;
 734         }
 735
 736         return 0;
 737 }
 738
 739 static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr,
 740                 struct SMU74_Discrete_DpmTable *table)
 741 {
 742         uint32_t count;
 743         uint8_t index;
 744         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 745         struct phm_ppt_v1_information *table_info =
 746                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 747         struct phm_ppt_v1_voltage_lookup_table *lookup_table =
 748                         table_info->vddc_lookup_table;
 749         /* tables is already swapped, so in order to use the value from it,
 750          * we need to swap it back.
 751          * We are populating vddc CAC data to BapmVddc table
 752          * in split and merged mode
 753          */
 754         for (count = 0; count < lookup_table->count; count++) {
 755                 index = phm_get_voltage_index(lookup_table,
 756                                 data->vddc_voltage_table.entries[count].value);
 757                 table->BapmVddcVidLoSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_low);
 758                 table->BapmVddcVidHiSidd[count] = convert_to_vid(lookup_table->entries[index].us_cac_mid);
 759                 table->BapmVddcVidHiSidd2[count] = convert_to_vid(lookup_table->entries[index].us_cac_high);
 760         }
 761
 762         return 0;
 763 }
 764
 765 static int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
 766                 struct SMU74_Discrete_DpmTable *table)
 767 {
 768         polaris10_populate_smc_vddc_table(hwmgr, table);
 769         polaris10_populate_smc_vddci_table(hwmgr, table);
 770         polaris10_populate_smc_mvdd_table(hwmgr, table);
 771         polaris10_populate_cac_table(hwmgr, table);
 772
 773         return 0;
 774 }
 775
 776 static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr,
 777                 struct SMU74_Discrete_Ulv *state)
 778 {
 779         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 780         struct phm_ppt_v1_information *table_info =
 781                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 782
 783         state->CcPwrDynRm = 0;
 784         state->CcPwrDynRm1 = 0;
 785
 786         state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
 787         state->VddcOffsetVid = (uint8_t)(table_info->us_ulv_voltage_offset *
 788                         VOLTAGE_VID_OFFSET_SCALE2 / VOLTAGE_VID_OFFSET_SCALE1);
 789
 790         if (hwmgr->chip_id == CHIP_POLARIS12 || hwmgr->is_kicker)
 791                 state->VddcPhase = data->vddc_phase_shed_control ^ 0x3;
 792         else
 793                 state->VddcPhase = (data->vddc_phase_shed_control) ? 0 : 1;
 794
 795         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm);
 796         CONVERT_FROM_HOST_TO_SMC_UL(state->CcPwrDynRm1);
 797         CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
 798
 799         return 0;
 800 }
 801
 802 static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr,
 803                 struct SMU74_Discrete_DpmTable *table)
 804 {
 805         return polaris10_populate_ulv_level(hwmgr, &table->Ulv);
 806 }
 807
 808 static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr,
 809                 struct SMU74_Discrete_DpmTable *table)
 810 {
 811         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 812         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 813         struct smu7_dpm_table *dpm_table = &data->dpm_table;
 814         int i;
 815
 816         /* Index (dpm_table->pcie_speed_table.count)
 817          * is reserved for PCIE boot level. */
 818         for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
 819                 table->LinkLevel[i].PcieGenSpeed  =
 820                                 (uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
 821                 table->LinkLevel[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
 822                                 dpm_table->pcie_speed_table.dpm_levels[i].param1);
 823                 table->LinkLevel[i].EnabledForActivity = 1;
 824                 table->LinkLevel[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
 825                 table->LinkLevel[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
 826                 table->LinkLevel[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
 827         }
 828
 829         smu_data->smc_state_table.LinkLevelCount =
 830                         (uint8_t)dpm_table->pcie_speed_table.count;
 831
 832 /* To Do move to hwmgr */
 833         data->dpm_level_enable_mask.pcie_dpm_enable_mask =
 834                         phm_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
 835
 836         return 0;
 837 }
 838
 839
 840 static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr,
 841                                    SMU74_Discrete_DpmTable  *table)
 842 {
 843         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 844         uint32_t i, ref_clk;
 845
 846         struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } };
 847
 848         ref_clk = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
 849
 850         if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) {
 851                 for (i = 0; i < NUM_SCLK_RANGE; i++) {
 852                         table->SclkFcwRangeTable[i].vco_setting = range_table_from_vbios.entry[i].ucVco_setting;
 853                         table->SclkFcwRangeTable[i].postdiv = range_table_from_vbios.entry[i].ucPostdiv;
 854                         table->SclkFcwRangeTable[i].fcw_pcc = range_table_from_vbios.entry[i].usFcw_pcc;
 855
 856                         table->SclkFcwRangeTable[i].fcw_trans_upper = range_table_from_vbios.entry[i].usFcw_trans_upper;
 857                         table->SclkFcwRangeTable[i].fcw_trans_lower = range_table_from_vbios.entry[i].usRcw_trans_lower;
 858
 859                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
 860                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
 861                         CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
 862                 }
 863                 return;
 864         }
 865
 866         for (i = 0; i < NUM_SCLK_RANGE; i++) {
 867                 smu_data->range_table[i].trans_lower_frequency = (ref_clk * Range_Table[i].fcw_trans_lower) >> Range_Table[i].postdiv;
 868                 smu_data->range_table[i].trans_upper_frequency = (ref_clk * Range_Table[i].fcw_trans_upper) >> Range_Table[i].postdiv;
 869
 870                 table->SclkFcwRangeTable[i].vco_setting = Range_Table[i].vco_setting;
 871                 table->SclkFcwRangeTable[i].postdiv = Range_Table[i].postdiv;
 872                 table->SclkFcwRangeTable[i].fcw_pcc = Range_Table[i].fcw_pcc;
 873
 874                 table->SclkFcwRangeTable[i].fcw_trans_upper = Range_Table[i].fcw_trans_upper;
 875                 table->SclkFcwRangeTable[i].fcw_trans_lower = Range_Table[i].fcw_trans_lower;
 876
 877                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_pcc);
 878                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_upper);
 879                 CONVERT_FROM_HOST_TO_SMC_US(table->SclkFcwRangeTable[i].fcw_trans_lower);
 880         }
 881 }
 882
 883 static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr,
 884                 uint32_t clock, SMU_SclkSetting *sclk_setting)
 885 {
 886         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
 887         const SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
 888         struct pp_atomctrl_clock_dividers_ai dividers;
 889         uint32_t ref_clock;
 890         uint32_t pcc_target_percent, pcc_target_freq, ss_target_percent, ss_target_freq;
 891         uint8_t i;
 892         int result;
 893         uint64_t temp;
 894
 895         sclk_setting->SclkFrequency = clock;
 896         /* get the engine clock dividers for this clock value */
 897         result = atomctrl_get_engine_pll_dividers_ai(hwmgr, clock,  &dividers);
 898         if (result == 0) {
 899                 sclk_setting->Fcw_int = dividers.usSclk_fcw_int;
 900                 sclk_setting->Fcw_frac = dividers.usSclk_fcw_frac;
 901                 sclk_setting->Pcc_fcw_int = dividers.usPcc_fcw_int;
 902                 sclk_setting->PllRange = dividers.ucSclkPllRange;
 903                 sclk_setting->Sclk_slew_rate = 0x400;
 904                 sclk_setting->Pcc_up_slew_rate = dividers.usPcc_fcw_slew_frac;
 905                 sclk_setting->Pcc_down_slew_rate = 0xffff;
 906                 sclk_setting->SSc_En = dividers.ucSscEnable;
 907                 sclk_setting->Fcw1_int = dividers.usSsc_fcw1_int;
 908                 sclk_setting->Fcw1_frac = dividers.usSsc_fcw1_frac;
 909                 sclk_setting->Sclk_ss_slew_rate = dividers.usSsc_fcw_slew_frac;
 910                 return result;
 911         }
 912
 913         ref_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
 914
 915         for (i = 0; i < NUM_SCLK_RANGE; i++) {
 916                 if (clock > smu_data->range_table[i].trans_lower_frequency
 917                 && clock <= smu_data->range_table[i].trans_upper_frequency) {
 918                         sclk_setting->PllRange = i;
 919                         break;
 920                 }
 921         }
 922
 923         sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 924         temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
 925         temp <<= 0x10;
 926         do_div(temp, ref_clock);
 927         sclk_setting->Fcw_frac = temp & 0xffff;
 928
 929         pcc_target_percent = 10; /*  Hardcode 10% for now. */
 930         pcc_target_freq = clock - (clock * pcc_target_percent / 100);
 931         sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 932
 933         ss_target_percent = 2; /*  Hardcode 2% for now. */
 934         sclk_setting->SSc_En = 0;
 935         if (ss_target_percent) {
 936                 sclk_setting->SSc_En = 1;
 937                 ss_target_freq = clock - (clock * ss_target_percent / 100);
 938                 sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock);
 939                 temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;
 940                 temp <<= 0x10;
 941                 do_div(temp, ref_clock);
 942                 sclk_setting->Fcw1_frac = temp & 0xffff;
 943         }
 944
 945         return 0;
 946 }
 947
 948 static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr,
 949                 uint32_t clock, struct SMU74_Discrete_GraphicsLevel *level)
 950 {
 951         int result;
 952         /* PP_Clocks minClocks; */
 953         uint32_t mvdd;
 954         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
 955         struct phm_ppt_v1_information *table_info =
 956                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
 957         SMU_SclkSetting curr_sclk_setting = { 0 };
 958         phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
 959
 960         result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting);
 961
 962         if (hwmgr->od_enabled)
 963                 vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_sclk;
 964         else
 965                 vdd_dep_table = table_info->vdd_dep_on_sclk;
 966
 967         /* populate graphics levels */
 968         result = polaris10_get_dependency_volt_by_clk(hwmgr,
 969                         vdd_dep_table, clock,
 970                         &level->MinVoltage, &mvdd);
 971
 972         PP_ASSERT_WITH_CODE((0 == result),
 973                         "can not find VDDC voltage value for "
 974                         "VDDC engine clock dependency table",
 975                         return result);
 976         level->ActivityLevel = data->current_profile_setting.sclk_activity;
 977
 978         level->CcPwrDynRm = 0;
 979         level->CcPwrDynRm1 = 0;
 980         level->EnabledForActivity = 0;
 981         level->EnabledForThrottle = 1;
 982         level->UpHyst = data->current_profile_setting.sclk_up_hyst;
 983         level->DownHyst = data->current_profile_setting.sclk_down_hyst;
 984         level->VoltageDownHyst = 0;
 985         level->PowerThrottle = 0;
 986         data->display_timing.min_clock_in_sr = hwmgr->display_config->min_core_set_clock_in_sr;
 987
 988         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep))
 989                 level->DeepSleepDivId = smu7_get_sleep_divider_id_from_clock(clock,
 990                                                                 hwmgr->display_config->min_core_set_clock_in_sr);
 991
 992         /* Default to slow, highest DPM level will be
 993          * set to PPSMC_DISPLAY_WATERMARK_LOW later.
 994          */
 995         if (data->update_up_hyst)
 996                 level->UpHyst = (uint8_t)data->up_hyst;
 997         if (data->update_down_hyst)
 998                 level->DownHyst = (uint8_t)data->down_hyst;
 999
1000         level->SclkSetting = curr_sclk_setting;
1001
1002         CONVERT_FROM_HOST_TO_SMC_UL(level->MinVoltage);
1003         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm);
1004         CONVERT_FROM_HOST_TO_SMC_UL(level->CcPwrDynRm1);
1005         CONVERT_FROM_HOST_TO_SMC_US(level->ActivityLevel);
1006         CONVERT_FROM_HOST_TO_SMC_UL(level->SclkSetting.SclkFrequency);
1007         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_int);
1008         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw_frac);
1009         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_fcw_int);
1010         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_slew_rate);
1011         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_up_slew_rate);
1012         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Pcc_down_slew_rate);
1013         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_int);
1014         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Fcw1_frac);
1015         CONVERT_FROM_HOST_TO_SMC_US(level->SclkSetting.Sclk_ss_slew_rate);
1016         return 0;
1017 }
1018
1019 static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
1020 {
1021         struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1022         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1023         struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
1024         struct phm_ppt_v1_information *table_info =
1025                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1026         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
1027         uint8_t pcie_entry_cnt = (uint8_t) hw_data->dpm_table.pcie_speed_table.count;
1028         int result = 0;
1029         uint32_t array = smu_data->smu7_data.dpm_table_start +
1030                         offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
1031         uint32_t array_size = sizeof(struct SMU74_Discrete_GraphicsLevel) *
1032                         SMU74_MAX_LEVELS_GRAPHICS;
1033         struct SMU74_Discrete_GraphicsLevel *levels =
1034                         smu_data->smc_state_table.GraphicsLevel;
1035         uint32_t i, max_entry;
1036         uint8_t hightest_pcie_level_enabled = 0,
1037                 lowest_pcie_level_enabled = 0,
1038                 mid_pcie_level_enabled = 0,
1039                 count = 0;
1040         struct amdgpu_device *adev = hwmgr->adev;
1041         pp_atomctrl_clock_dividers_vi dividers;
1042         uint32_t dpm0_sclkfrequency = levels[0].SclkSetting.SclkFrequency;
1043
1044         polaris10_get_sclk_range_table(hwmgr, &(smu_data->smc_state_table));
1045
1046         for (i = 0; i < dpm_table->sclk_table.count; i++) {
1047
1048                 result = polaris10_populate_single_graphic_level(hwmgr,
1049                                 dpm_table->sclk_table.dpm_levels[i].value,
1050                                 &(smu_data->smc_state_table.GraphicsLevel[i]));
1051                 if (result)
1052                         return result;
1053
1054                 /* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
1055                 if (i > 1)
1056                         levels[i].DeepSleepDivId = 0;
1057         }
1058         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1059                                         PHM_PlatformCaps_SPLLShutdownSupport)) {
1060                 smu_data->smc_state_table.GraphicsLevel[0].SclkSetting.SSc_En = 0;
1061                 if (dpm0_sclkfrequency != levels[0].SclkSetting.SclkFrequency) {
1062                         result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1063                                         dpm_table->sclk_table.dpm_levels[0].value,
1064                                         &dividers);
1065                         PP_ASSERT_WITH_CODE((0 == result),
1066                                         "can not find divide id for sclk",
1067                                         return result);
1068                         smum_send_msg_to_smc_with_parameter(hwmgr,
1069                                         PPSMC_MSG_SetGpuPllDfsForSclk,
1070                                         dividers.real_clock < dpm_table->sclk_table.dpm_levels[0].value ?
1071                                         dividers.pll_post_divider - 1 : dividers.pll_post_divider,
1072                                         NULL);
1073                 }
1074         }
1075
1076         smu_data->smc_state_table.GraphicsDpmLevelCount =
1077                         (uint8_t)dpm_table->sclk_table.count;
1078         hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask =
1079                         phm_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
1080
1081         for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++)
1082                 smu_data->smc_state_table.GraphicsLevel[i].EnabledForActivity =
1083                         (hw_data->dpm_level_enable_mask.sclk_dpm_enable_mask & (1 << i)) >> i;
1084
1085         if (pcie_table != NULL) {
1086                 PP_ASSERT_WITH_CODE((1 <= pcie_entry_cnt),
1087                                 "There must be 1 or more PCIE levels defined in PPTable.",
1088                                 return -EINVAL);
1089                 max_entry = pcie_entry_cnt - 1;
1090                 for (i = 0; i < dpm_table->sclk_table.count; i++)
1091                         levels[i].pcieDpmLevel =
1092                                         (uint8_t) ((i < max_entry) ? i : max_entry);
1093         } else {
1094                 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1095                                 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1096                                                 (1 << (hightest_pcie_level_enabled + 1))) != 0))
1097                         hightest_pcie_level_enabled++;
1098
1099                 while (hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
1100                                 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1101                                                 (1 << lowest_pcie_level_enabled)) == 0))
1102                         lowest_pcie_level_enabled++;
1103
1104                 while ((count < hightest_pcie_level_enabled) &&
1105                                 ((hw_data->dpm_level_enable_mask.pcie_dpm_enable_mask &
1106                                                 (1 << (lowest_pcie_level_enabled + 1 + count))) == 0))
1107                         count++;
1108
1109                 mid_pcie_level_enabled = (lowest_pcie_level_enabled + 1 + count) <
1110                                 hightest_pcie_level_enabled ?
1111                                                 (lowest_pcie_level_enabled + 1 + count) :
1112                                                 hightest_pcie_level_enabled;
1113
1114                 /* set pcieDpmLevel to hightest_pcie_level_enabled */
1115                 for (i = 2; i < dpm_table->sclk_table.count; i++)
1116                         levels[i].pcieDpmLevel = hightest_pcie_level_enabled;
1117
1118                 /* set pcieDpmLevel to lowest_pcie_level_enabled */
1119                 levels[0].pcieDpmLevel = lowest_pcie_level_enabled;
1120
1121                 /* set pcieDpmLevel to mid_pcie_level_enabled */
1122                 levels[1].pcieDpmLevel = mid_pcie_level_enabled;
1123         }
1124         /* level count will send to smc once at init smc table and never change */
1125         result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1126                         (uint32_t)array_size, SMC_RAM_END);
1127
1128         return result;
1129 }
1130
1131
1132 static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr,
1133                 uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level)
1134 {
1135         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1136         struct phm_ppt_v1_information *table_info =
1137                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1138         int result = 0;
1139         uint32_t mclk_stutter_mode_threshold = 40000;
1140         phm_ppt_v1_clock_voltage_dependency_table *vdd_dep_table = NULL;
1141
1142
1143         if (hwmgr->od_enabled)
1144                 vdd_dep_table = (phm_ppt_v1_clock_voltage_dependency_table *)&data->odn_dpm_table.vdd_dependency_on_mclk;
1145         else
1146                 vdd_dep_table = table_info->vdd_dep_on_mclk;
1147
1148         if (vdd_dep_table) {
1149                 result = polaris10_get_dependency_volt_by_clk(hwmgr,
1150                                 vdd_dep_table, clock,
1151                                 &mem_level->MinVoltage, &mem_level->MinMvdd);
1152                 PP_ASSERT_WITH_CODE((0 == result),
1153                                 "can not find MinVddc voltage value from memory "
1154                                 "VDDC voltage dependency table", return result);
1155         }
1156
1157         mem_level->MclkFrequency = clock;
1158         mem_level->EnabledForThrottle = 1;
1159         mem_level->EnabledForActivity = 0;
1160         mem_level->UpHyst = data->current_profile_setting.mclk_up_hyst;
1161         mem_level->DownHyst = data->current_profile_setting.mclk_down_hyst;
1162         mem_level->VoltageDownHyst = 0;
1163         mem_level->ActivityLevel = data->current_profile_setting.mclk_activity;
1164         mem_level->StutterEnable = false;
1165         mem_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
1166
1167         data->display_timing.num_existing_displays = hwmgr->display_config->num_display;
1168         data->display_timing.vrefresh = hwmgr->display_config->vrefresh;
1169
1170         if (mclk_stutter_mode_threshold &&
1171                 (clock <= mclk_stutter_mode_threshold) &&
1172                 (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL,
1173                                 STUTTER_ENABLE) & 0x1) &&
1174                 (data->display_timing.num_existing_displays <= 2) &&
1175                 data->display_timing.num_existing_displays)
1176                 mem_level->StutterEnable = true;
1177
1178         if (!result) {
1179                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinMvdd);
1180                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MclkFrequency);
1181                 CONVERT_FROM_HOST_TO_SMC_US(mem_level->ActivityLevel);
1182                 CONVERT_FROM_HOST_TO_SMC_UL(mem_level->MinVoltage);
1183         }
1184         return result;
1185 }
1186
1187 static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
1188 {
1189         struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1190         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1191         struct smu7_dpm_table *dpm_table = &hw_data->dpm_table;
1192         int result;
1193         /* populate MCLK dpm table to SMU7 */
1194         uint32_t array = smu_data->smu7_data.dpm_table_start +
1195                         offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
1196         uint32_t array_size = sizeof(SMU74_Discrete_MemoryLevel) *
1197                         SMU74_MAX_LEVELS_MEMORY;
1198         struct SMU74_Discrete_MemoryLevel *levels =
1199                         smu_data->smc_state_table.MemoryLevel;
1200         uint32_t i;
1201
1202         for (i = 0; i < dpm_table->mclk_table.count; i++) {
1203                 PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
1204                                 "can not populate memory level as memory clock is zero",
1205                                 return -EINVAL);
1206                 result = polaris10_populate_single_memory_level(hwmgr,
1207                                 dpm_table->mclk_table.dpm_levels[i].value,
1208                                 &levels[i]);
1209                 if (i == dpm_table->mclk_table.count - 1)
1210                         levels[i].DisplayWatermark = PPSMC_DISPLAY_WATERMARK_HIGH;
1211                 if (result)
1212                         return result;
1213         }
1214
1215         smu_data->smc_state_table.MemoryDpmLevelCount =
1216                         (uint8_t)dpm_table->mclk_table.count;
1217         hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask =
1218                         phm_get_dpm_level_enable_mask_value(&dpm_table->mclk_table);
1219
1220         for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++)
1221                 smu_data->smc_state_table.MemoryLevel[i].EnabledForActivity =
1222                         (hw_data->dpm_level_enable_mask.mclk_dpm_enable_mask & (1 << i)) >> i;
1223
1224         /* level count will send to smc once at init smc table and never change */
1225         result = smu7_copy_bytes_to_smc(hwmgr, array, (uint8_t *)levels,
1226                         (uint32_t)array_size, SMC_RAM_END);
1227
1228         return result;
1229 }
1230
1231 static int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr,
1232                 uint32_t mclk, SMIO_Pattern *smio_pat)
1233 {
1234         const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1235         struct phm_ppt_v1_information *table_info =
1236                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1237         uint32_t i = 0;
1238
1239         if (SMU7_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
1240                 /* find mvdd value which clock is more than request */
1241                 for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) {
1242                         if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) {
1243                                 smio_pat->Voltage = data->mvdd_voltage_table.entries[i].value;
1244                                 break;
1245                         }
1246                 }
1247                 PP_ASSERT_WITH_CODE(i < table_info->vdd_dep_on_mclk->count,
1248                                 "MVDD Voltage is outside the supported range.",
1249                                 return -EINVAL);
1250         } else
1251                 return -EINVAL;
1252
1253         return 0;
1254 }
1255
1256 static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr,
1257                 SMU74_Discrete_DpmTable *table)
1258 {
1259         int result = 0;
1260         uint32_t sclk_frequency;
1261         const struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1262         struct phm_ppt_v1_information *table_info =
1263                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1264         SMIO_Pattern vol_level;
1265         uint32_t mvdd;
1266
1267         table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
1268
1269         /* Get MinVoltage and Frequency from DPM0,
1270          * already converted to SMC_UL */
1271         sclk_frequency = data->vbios_boot_state.sclk_bootup_value;
1272         result = polaris10_get_dependency_volt_by_clk(hwmgr,
1273                         table_info->vdd_dep_on_sclk,
1274                         sclk_frequency,
1275                         &table->ACPILevel.MinVoltage, &mvdd);
1276         PP_ASSERT_WITH_CODE((0 == result),
1277                         "Cannot find ACPI VDDC voltage value "
1278                         "in Clock Dependency Table",
1279                         );
1280
1281         result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency,  &(table->ACPILevel.SclkSetting));
1282         PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result);
1283
1284         table->ACPILevel.DeepSleepDivId = 0;
1285         table->ACPILevel.CcPwrDynRm = 0;
1286         table->ACPILevel.CcPwrDynRm1 = 0;
1287
1288         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
1289         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.MinVoltage);
1290         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
1291         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
1292
1293         CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkSetting.SclkFrequency);
1294         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_int);
1295         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw_frac);
1296         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_fcw_int);
1297         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_slew_rate);
1298         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_up_slew_rate);
1299         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Pcc_down_slew_rate);
1300         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_int);
1301         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Fcw1_frac);
1302         CONVERT_FROM_HOST_TO_SMC_US(table->ACPILevel.SclkSetting.Sclk_ss_slew_rate);
1303
1304
1305         /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */
1306         table->MemoryACPILevel.MclkFrequency = data->vbios_boot_state.mclk_bootup_value;
1307         result = polaris10_get_dependency_volt_by_clk(hwmgr,
1308                         table_info->vdd_dep_on_mclk,
1309                         table->MemoryACPILevel.MclkFrequency,
1310                         &table->MemoryACPILevel.MinVoltage, &mvdd);
1311         PP_ASSERT_WITH_CODE((0 == result),
1312                         "Cannot find ACPI VDDCI voltage value "
1313                         "in Clock Dependency Table",
1314                         );
1315
1316         if (!((SMU7_VOLTAGE_CONTROL_NONE == data->mvdd_control) ||
1317                         (data->mclk_dpm_key_disabled)))
1318                 polaris10_populate_mvdd_value(hwmgr,
1319                                 data->dpm_table.mclk_table.dpm_levels[0].value,
1320                                 &vol_level);
1321
1322         if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level))
1323                 table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage);
1324         else
1325                 table->MemoryACPILevel.MinMvdd = 0;
1326
1327         table->MemoryACPILevel.StutterEnable = false;
1328
1329         table->MemoryACPILevel.EnabledForThrottle = 0;
1330         table->MemoryACPILevel.EnabledForActivity = 0;
1331         table->MemoryACPILevel.UpHyst = 0;
1332         table->MemoryACPILevel.DownHyst = 100;
1333         table->MemoryACPILevel.VoltageDownHyst = 0;
1334         /* To align with the settings from other OSes */
1335         table->MemoryACPILevel.ActivityLevel =
1336                         PP_HOST_TO_SMC_US(data->current_profile_setting.sclk_activity);
1337
1338         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MclkFrequency);
1339         CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);
1340
1341         return result;
1342 }
1343
1344 static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
1345                 SMU74_Discrete_DpmTable *table)
1346 {
1347         int result = -EINVAL;
1348         uint8_t count;
1349         struct pp_atomctrl_clock_dividers_vi dividers;
1350         struct phm_ppt_v1_information *table_info =
1351                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1352         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1353                         table_info->mm_dep_table;
1354         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1355         uint32_t vddci;
1356
1357         table->VceLevelCount = (uint8_t)(mm_table->count);
1358         table->VceBootLevel = 0;
1359
1360         for (count = 0; count < table->VceLevelCount; count++) {
1361                 table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
1362                 table->VceLevel[count].MinVoltage = 0;
1363                 table->VceLevel[count].MinVoltage |=
1364                                 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1365
1366                 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1367                         vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1368                                                 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1369                 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1370                         vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1371                 else
1372                         vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1373
1374
1375                 table->VceLevel[count].MinVoltage |=
1376                                 (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1377                 table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1378
1379                 /*retrieve divider value for VBIOS */
1380                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1381                                 table->VceLevel[count].Frequency, &dividers);
1382                 PP_ASSERT_WITH_CODE((0 == result),
1383                                 "can not find divide id for VCE engine clock",
1384                                 return result);
1385
1386                 table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1387
1388                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
1389                 CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
1390         }
1391         return result;
1392 }
1393
1394 static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
1395                 SMU74_Discrete_DpmTable *table)
1396 {
1397         int result = -EINVAL;
1398         uint8_t count;
1399         struct pp_atomctrl_clock_dividers_vi dividers;
1400         struct phm_ppt_v1_information *table_info =
1401                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1402         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1403                         table_info->mm_dep_table;
1404         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1405         uint32_t vddci;
1406
1407         table->SamuLevelCount = (uint8_t)(mm_table->count);
1408         table->SamuBootLevel = 0;
1409
1410         for (count = 0; count < table->SamuLevelCount; count++) {
1411                 table->SamuLevel[count].Frequency = mm_table->entries[count].samclock;
1412                 table->SamuLevel[count].MinVoltage |=
1413                                 (mm_table->entries[count].vddc * VOLTAGE_SCALE) << VDDC_SHIFT;
1414
1415                 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1416                         vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1417                                                 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1418                 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1419                         vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1420                 else
1421                         vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1422
1423
1424                 table->SamuLevel[count].MinVoltage |=
1425                                 (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1426                 table->SamuLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1427
1428                 /*retrieve divider value for VBIOS */
1429                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1430                                 table->SamuLevel[count].Frequency, &dividers);
1431                 PP_ASSERT_WITH_CODE((0 == result),
1432                                 "can not find divide id for VCE engine clock",
1433                                 return result);
1434
1435                 table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
1436
1437                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
1438                 CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].MinVoltage);
1439         }
1440         return result;
1441 }
1442
1443 static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr,
1444                 int32_t eng_clock, int32_t mem_clock,
1445                 SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs)
1446 {
1447         uint32_t dram_timing;
1448         uint32_t dram_timing2;
1449         uint32_t burst_time;
1450         int result;
1451
1452         result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
1453                         eng_clock, mem_clock);
1454         PP_ASSERT_WITH_CODE(result == 0,
1455                         "Error calling VBIOS to set DRAM_TIMING.", return result);
1456
1457         dram_timing = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
1458         dram_timing2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
1459         burst_time = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
1460
1461
1462         arb_regs->McArbDramTiming  = PP_HOST_TO_SMC_UL(dram_timing);
1463         arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dram_timing2);
1464         arb_regs->McArbBurstTime   = (uint8_t)burst_time;
1465
1466         return 0;
1467 }
1468
1469 static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
1470 {
1471         struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1472         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1473         struct SMU74_Discrete_MCArbDramTimingTable arb_regs;
1474         uint32_t i, j;
1475         int result = 0;
1476
1477         for (i = 0; i < hw_data->dpm_table.sclk_table.count; i++) {
1478                 for (j = 0; j < hw_data->dpm_table.mclk_table.count; j++) {
1479                         result = polaris10_populate_memory_timing_parameters(hwmgr,
1480                                         hw_data->dpm_table.sclk_table.dpm_levels[i].value,
1481                                         hw_data->dpm_table.mclk_table.dpm_levels[j].value,
1482                                         &arb_regs.entries[i][j]);
1483                         if (result == 0 && i == 0)
1484                                 result = atomctrl_set_ac_timing_ai(hwmgr, hw_data->dpm_table.mclk_table.dpm_levels[j].value, j);
1485                         if (result != 0)
1486                                 return result;
1487                 }
1488         }
1489
1490         result = smu7_copy_bytes_to_smc(
1491                         hwmgr,
1492                         smu_data->smu7_data.arb_table_start,
1493                         (uint8_t *)&arb_regs,
1494                         sizeof(SMU74_Discrete_MCArbDramTimingTable),
1495                         SMC_RAM_END);
1496         return result;
1497 }
1498
1499 static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
1500                 struct SMU74_Discrete_DpmTable *table)
1501 {
1502         int result = -EINVAL;
1503         uint8_t count;
1504         struct pp_atomctrl_clock_dividers_vi dividers;
1505         struct phm_ppt_v1_information *table_info =
1506                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1507         struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table =
1508                         table_info->mm_dep_table;
1509         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1510         uint32_t vddci;
1511
1512         table->UvdLevelCount = (uint8_t)(mm_table->count);
1513         table->UvdBootLevel = 0;
1514
1515         for (count = 0; count < table->UvdLevelCount; count++) {
1516                 table->UvdLevel[count].MinVoltage = 0;
1517                 table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
1518                 table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
1519                 table->UvdLevel[count].MinVoltage |= (mm_table->entries[count].vddc *
1520                                 VOLTAGE_SCALE) << VDDC_SHIFT;
1521
1522                 if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control)
1523                         vddci = (uint32_t)phm_find_closest_vddci(&(data->vddci_voltage_table),
1524                                                 mm_table->entries[count].vddc - VDDC_VDDCI_DELTA);
1525                 else if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control)
1526                         vddci = mm_table->entries[count].vddc - VDDC_VDDCI_DELTA;
1527                 else
1528                         vddci = (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT;
1529
1530                 table->UvdLevel[count].MinVoltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT;
1531                 table->UvdLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
1532
1533                 /* retrieve divider value for VBIOS */
1534                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1535                                 table->UvdLevel[count].VclkFrequency, &dividers);
1536                 PP_ASSERT_WITH_CODE((0 == result),
1537                                 "can not find divide id for Vclk clock", return result);
1538
1539                 table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
1540
1541                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
1542                                 table->UvdLevel[count].DclkFrequency, &dividers);
1543                 PP_ASSERT_WITH_CODE((0 == result),
1544                                 "can not find divide id for Dclk clock", return result);
1545
1546                 table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
1547
1548                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
1549                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
1550                 CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].MinVoltage);
1551         }
1552
1553         return result;
1554 }
1555
1556 static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
1557                 struct SMU74_Discrete_DpmTable *table)
1558 {
1559         int result = 0;
1560         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1561
1562         table->GraphicsBootLevel = 0;
1563         table->MemoryBootLevel = 0;
1564
1565         /* find boot level from dpm table */
1566         result = phm_find_boot_level(&(data->dpm_table.sclk_table),
1567                         data->vbios_boot_state.sclk_bootup_value,
1568                         (uint32_t *)&(table->GraphicsBootLevel));
1569
1570         result = phm_find_boot_level(&(data->dpm_table.mclk_table),
1571                         data->vbios_boot_state.mclk_bootup_value,
1572                         (uint32_t *)&(table->MemoryBootLevel));
1573
1574         table->BootVddc  = data->vbios_boot_state.vddc_bootup_value *
1575                         VOLTAGE_SCALE;
1576         table->BootVddci = data->vbios_boot_state.vddci_bootup_value *
1577                         VOLTAGE_SCALE;
1578         table->BootMVdd  = data->vbios_boot_state.mvdd_bootup_value *
1579                         VOLTAGE_SCALE;
1580
1581         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddc);
1582         CONVERT_FROM_HOST_TO_SMC_US(table->BootVddci);
1583         CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
1584
1585         return 0;
1586 }
1587
1588 static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr)
1589 {
1590         struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1591         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1592         struct phm_ppt_v1_information *table_info =
1593                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1594         uint8_t count, level;
1595
1596         count = (uint8_t)(table_info->vdd_dep_on_sclk->count);
1597
1598         for (level = 0; level < count; level++) {
1599                 if (table_info->vdd_dep_on_sclk->entries[level].clk >=
1600                                 hw_data->vbios_boot_state.sclk_bootup_value) {
1601                         smu_data->smc_state_table.GraphicsBootLevel = level;
1602                         break;
1603                 }
1604         }
1605
1606         count = (uint8_t)(table_info->vdd_dep_on_mclk->count);
1607         for (level = 0; level < count; level++) {
1608                 if (table_info->vdd_dep_on_mclk->entries[level].clk >=
1609                                 hw_data->vbios_boot_state.mclk_bootup_value) {
1610                         smu_data->smc_state_table.MemoryBootLevel = level;
1611                         break;
1612                 }
1613         }
1614
1615         return 0;
1616 }
1617
1618 #define STRAP_ASIC_RO_LSB    2168
1619 #define STRAP_ASIC_RO_MSB    2175
1620
1621 static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr)
1622 {
1623         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1624         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1625         struct phm_ppt_v1_information *table_info =
1626                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1627         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1628                         table_info->vdd_dep_on_sclk;
1629         uint32_t ro, efuse, volt_without_cks, volt_with_cks, value;
1630         uint8_t i, stretch_amount, volt_offset = 0;
1631
1632         stretch_amount = (uint8_t)table_info->cac_dtp_table->usClockStretchAmount;
1633
1634         /* Read SMU_Eefuse to read and calculate RO and determine
1635          * if the part is SS or FF. if RO >= 1660MHz, part is FF.
1636          */
1637         atomctrl_read_efuse(hwmgr, STRAP_ASIC_RO_LSB, STRAP_ASIC_RO_MSB, &efuse);
1638         ro = ((efuse * (data->ro_range_maximum - data->ro_range_minimum)) / 255) +
1639                 data->ro_range_minimum;
1640
1641         /* Populate Sclk_CKS_masterEn0_7 and Sclk_voltageOffset */
1642         for (i = 0; i < sclk_table->count; i++) {
1643                 smu_data->smc_state_table.Sclk_CKS_masterEn0_7 |=
1644                                 sclk_table->entries[i].cks_enable << i;
1645                 if (hwmgr->chip_id == CHIP_POLARIS10) {
1646                         volt_without_cks = (uint32_t)((2753594000U + (sclk_table->entries[i].clk/100) * 136418 - (ro - 70) * 1000000) / \
1647                                                 (2424180 - (sclk_table->entries[i].clk/100) * 1132925/1000));
1648                         volt_with_cks = (uint32_t)((2797202000U + sclk_table->entries[i].clk/100 * 3232 - (ro - 65) * 1000000) / \
1649                                         (2522480 - sclk_table->entries[i].clk/100 * 115764/100));
1650                 } else {
1651                         volt_without_cks = (uint32_t)((2416794800U + (sclk_table->entries[i].clk/100) * 1476925/10 - (ro - 50) * 1000000) / \
1652                                                 (2625416 - (sclk_table->entries[i].clk/100) * (12586807/10000)));
1653                         volt_with_cks = (uint32_t)((2999656000U - sclk_table->entries[i].clk/100 * 392803 - (ro - 44) * 1000000) / \
1654                                         (3422454 - sclk_table->entries[i].clk/100 * (18886376/10000)));
1655                 }
1656
1657                 if (volt_without_cks >= volt_with_cks)
1658                         volt_offset = (uint8_t)(((volt_without_cks - volt_with_cks +
1659                                         sclk_table->entries[i].cks_voffset) * 100 + 624) / 625);
1660
1661                 smu_data->smc_state_table.Sclk_voltageOffset[i] = volt_offset;
1662         }
1663
1664         smu_data->smc_state_table.LdoRefSel = (table_info->cac_dtp_table->ucCKS_LDO_REFSEL != 0) ? table_info->cac_dtp_table->ucCKS_LDO_REFSEL : 5;
1665
1666         /* Populate CKS Lookup Table */
1667         if (stretch_amount == 0 || stretch_amount > 5) {
1668                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
1669                                 PHM_PlatformCaps_ClockStretcher);
1670                 PP_ASSERT_WITH_CODE(false,
1671                                 "Stretch Amount in PPTable not supported",
1672                                 return -EINVAL);
1673         }
1674
1675         value = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL);
1676         value &= 0xFFFFFFFE;
1677         cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value);
1678
1679         return 0;
1680 }
1681
1682 static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr,
1683                 struct SMU74_Discrete_DpmTable *table)
1684 {
1685         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1686         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1687         uint16_t config;
1688
1689         config = VR_MERGED_WITH_VDDC;
1690         table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT);
1691
1692         /* Set Vddc Voltage Controller */
1693         if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
1694                 config = VR_SVI2_PLANE_1;
1695                 table->VRConfig |= config;
1696         } else {
1697                 PP_ASSERT_WITH_CODE(false,
1698                                 "VDDC should be on SVI2 control in merged mode!",
1699                                 );
1700         }
1701         /* Set Vddci Voltage Controller */
1702         if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) {
1703                 config = VR_SVI2_PLANE_2;  /* only in merged mode */
1704                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1705         } else if (SMU7_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) {
1706                 config = VR_SMIO_PATTERN_1;
1707                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1708         } else {
1709                 config = VR_STATIC_VOLTAGE;
1710                 table->VRConfig |= (config << VRCONF_VDDCI_SHIFT);
1711         }
1712         /* Set Mvdd Voltage Controller */
1713         if (SMU7_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) {
1714                 config = VR_SVI2_PLANE_2;
1715                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1716                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, smu_data->smu7_data.soft_regs_start +
1717                         offsetof(SMU74_SoftRegisters, AllowMvddSwitch), 0x1);
1718         } else {
1719                 config = VR_STATIC_VOLTAGE;
1720                 table->VRConfig |= (config << VRCONF_MVDD_SHIFT);
1721         }
1722
1723         return 0;
1724 }
1725
1726
1727 static int polaris10_populate_avfs_parameters(struct pp_hwmgr *hwmgr)
1728 {
1729         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1730         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1731         struct amdgpu_device *adev = hwmgr->adev;
1732
1733         SMU74_Discrete_DpmTable  *table = &(smu_data->smc_state_table);
1734         int result = 0;
1735         struct pp_atom_ctrl__avfs_parameters avfs_params = {0};
1736         AVFS_meanNsigma_t AVFS_meanNsigma = { {0} };
1737         AVFS_Sclk_Offset_t AVFS_SclkOffset = { {0} };
1738         uint32_t tmp, i;
1739
1740         struct phm_ppt_v1_information *table_info =
1741                         (struct phm_ppt_v1_information *)hwmgr->pptable;
1742         struct phm_ppt_v1_clock_voltage_dependency_table *sclk_table =
1743                         table_info->vdd_dep_on_sclk;
1744
1745
1746         if (!hwmgr->avfs_supported)
1747                 return 0;
1748
1749         result = atomctrl_get_avfs_information(hwmgr, &avfs_params);
1750
1751         if (0 == result) {
1752                 if (((adev->pdev->device == 0x67ef) &&
1753                      ((adev->pdev->revision == 0xe0) ||
1754                       (adev->pdev->revision == 0xe5))) ||
1755                     ((adev->pdev->device == 0x67ff) &&
1756                      ((adev->pdev->revision == 0xcf) ||
1757                       (adev->pdev->revision == 0xef) ||
1758                       (adev->pdev->revision == 0xff)))) {
1759                         avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage = 1;
1760                         if ((adev->pdev->device == 0x67ef && adev->pdev->revision == 0xe5) ||
1761                             (adev->pdev->device == 0x67ff && adev->pdev->revision == 0xef)) {
1762                                 if ((avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0 == 0xEA522DD3) &&
1763                                     (avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1 == 0x5645A) &&
1764                                     (avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2 == 0x33F9E) &&
1765                                     (avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 == 0xFFFFC5CC) &&
1766                                     (avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 == 0x1B1A) &&
1767                                     (avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b == 0xFFFFFCED)) {
1768                                         avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0   = 0xF718F1D4;
1769                                         avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1   = 0x323FD;
1770                                         avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2   = 0x1E455;
1771                                         avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0;
1772                                         avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0;
1773                                         avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b  = 0x23;
1774                                 }
1775                         }
1776                 } else if (hwmgr->chip_id == CHIP_POLARIS12 && !hwmgr->is_kicker) {
1777                         avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage = 1;
1778                         avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0   = 0xF6B024DD;
1779                         avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1   = 0x3005E;
1780                         avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2   = 0x18A5F;
1781                         avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0x315;
1782                         avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0xFED1;
1783                         avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b  = 0x3B;
1784                 } else if (((adev->pdev->device == 0x67df) &&
1785                             ((adev->pdev->revision == 0xe0) ||
1786                              (adev->pdev->revision == 0xe3) ||
1787                              (adev->pdev->revision == 0xe4) ||
1788                              (adev->pdev->revision == 0xe5) ||
1789                              (adev->pdev->revision == 0xe7) ||
1790                              (adev->pdev->revision == 0xef))) ||
1791                            ((adev->pdev->device == 0x6fdf) &&
1792                             ((adev->pdev->revision == 0xef) ||
1793                              (adev->pdev->revision == 0xff)))) {
1794                         avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage = 1;
1795                         avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0   = 0xF843B66B;
1796                         avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1   = 0x59CB5;
1797                         avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2   = 0xFFFF287F;
1798                         avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1 = 0;
1799                         avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2 = 0xFF23;
1800                         avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b  = 0x58;
1801                 }
1802         }
1803
1804         if (0 == result) {
1805                 table->BTCGB_VDROOP_TABLE[0].a0  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a0);
1806                 table->BTCGB_VDROOP_TABLE[0].a1  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a1);
1807                 table->BTCGB_VDROOP_TABLE[0].a2  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSON_a2);
1808                 table->BTCGB_VDROOP_TABLE[1].a0  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a0);
1809                 table->BTCGB_VDROOP_TABLE[1].a1  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a1);
1810                 table->BTCGB_VDROOP_TABLE[1].a2  = PP_HOST_TO_SMC_UL(avfs_params.ulGB_VDROOP_TABLE_CKSOFF_a2);
1811                 table->AVFSGB_VDROOP_TABLE[0].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_m1);
1812                 table->AVFSGB_VDROOP_TABLE[0].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSON_m2);
1813                 table->AVFSGB_VDROOP_TABLE[0].b  = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSON_b);
1814                 table->AVFSGB_VDROOP_TABLE[0].m1_shift = 24;
1815                 table->AVFSGB_VDROOP_TABLE[0].m2_shift  = 12;
1816                 table->AVFSGB_VDROOP_TABLE[1].m1 = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_m1);
1817                 table->AVFSGB_VDROOP_TABLE[1].m2 = PP_HOST_TO_SMC_US(avfs_params.usAVFSGB_FUSE_TABLE_CKSOFF_m2);
1818                 table->AVFSGB_VDROOP_TABLE[1].b  = PP_HOST_TO_SMC_UL(avfs_params.ulAVFSGB_FUSE_TABLE_CKSOFF_b);
1819                 table->AVFSGB_VDROOP_TABLE[1].m1_shift = 24;
1820                 table->AVFSGB_VDROOP_TABLE[1].m2_shift  = 12;
1821                 table->MaxVoltage                = PP_HOST_TO_SMC_US(avfs_params.usMaxVoltage_0_25mv);
1822                 AVFS_meanNsigma.Aconstant[0]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant0);
1823                 AVFS_meanNsigma.Aconstant[1]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant1);
1824                 AVFS_meanNsigma.Aconstant[2]      = PP_HOST_TO_SMC_UL(avfs_params.ulAVFS_meanNsigma_Acontant2);
1825                 AVFS_meanNsigma.DC_tol_sigma      = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_DC_tol_sigma);
1826                 AVFS_meanNsigma.Platform_mean     = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_mean);
1827                 AVFS_meanNsigma.PSM_Age_CompFactor = PP_HOST_TO_SMC_US(avfs_params.usPSM_Age_ComFactor);
1828                 AVFS_meanNsigma.Platform_sigma     = PP_HOST_TO_SMC_US(avfs_params.usAVFS_meanNsigma_Platform_sigma);
1829
1830                 for (i = 0; i < NUM_VFT_COLUMNS; i++) {
1831                         AVFS_meanNsigma.Static_Voltage_Offset[i] = (uint8_t)(sclk_table->entries[i].cks_voffset * 100 / 625);
1832                         AVFS_SclkOffset.Sclk_Offset[i] = PP_HOST_TO_SMC_US((uint16_t)(sclk_table->entries[i].sclk_offset) / 100);
1833                 }
1834
1835                 result = smu7_read_smc_sram_dword(hwmgr,
1836                                 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsMeanNSigma),
1837                                 &tmp, SMC_RAM_END);
1838
1839                 smu7_copy_bytes_to_smc(hwmgr,
1840                                         tmp,
1841                                         (uint8_t *)&AVFS_meanNsigma,
1842                                         sizeof(AVFS_meanNsigma_t),
1843                                         SMC_RAM_END);
1844
1845                 result = smu7_read_smc_sram_dword(hwmgr,
1846                                 SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, AvfsSclkOffsetTable),
1847                                 &tmp, SMC_RAM_END);
1848                 smu7_copy_bytes_to_smc(hwmgr,
1849                                         tmp,
1850                                         (uint8_t *)&AVFS_SclkOffset,
1851                                         sizeof(AVFS_Sclk_Offset_t),
1852                                         SMC_RAM_END);
1853
1854                 data->avfs_vdroop_override_setting = (avfs_params.ucEnableGB_VDROOP_TABLE_CKSON << BTCGB0_Vdroop_Enable_SHIFT) |
1855                                                 (avfs_params.ucEnableGB_VDROOP_TABLE_CKSOFF << BTCGB1_Vdroop_Enable_SHIFT) |
1856                                                 (avfs_params.ucEnableGB_FUSE_TABLE_CKSON << AVFSGB0_Vdroop_Enable_SHIFT) |
1857                                                 (avfs_params.ucEnableGB_FUSE_TABLE_CKSOFF << AVFSGB1_Vdroop_Enable_SHIFT);
1858                 data->apply_avfs_cks_off_voltage = (avfs_params.ucEnableApplyAVFS_CKS_OFF_Voltage == 1) ? true : false;
1859         }
1860         return result;
1861 }
1862
1863 static void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
1864 {
1865         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1866         struct  phm_ppt_v1_information *table_info =
1867                         (struct  phm_ppt_v1_information *)(hwmgr->pptable);
1868
1869         if (table_info &&
1870                         table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
1871                         table_info->cac_dtp_table->usPowerTuneDataSetID)
1872                 smu_data->power_tune_defaults =
1873                                 &polaris10_power_tune_data_set_array
1874                                 [table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
1875         else
1876                 smu_data->power_tune_defaults = &polaris10_power_tune_data_set_array[0];
1877
1878 }
1879
1880 static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
1881 {
1882         int result;
1883         struct smu7_hwmgr *hw_data = (struct smu7_hwmgr *)(hwmgr->backend);
1884         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
1885
1886         struct phm_ppt_v1_information *table_info =
1887                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
1888         struct SMU74_Discrete_DpmTable *table = &(smu_data->smc_state_table);
1889         uint8_t i;
1890         struct pp_atomctrl_gpio_pin_assignment gpio_pin;
1891         pp_atomctrl_clock_dividers_vi dividers;
1892         struct phm_ppt_v1_gpio_table *gpio_table = table_info->gpio_table;
1893
1894         polaris10_initialize_power_tune_defaults(hwmgr);
1895
1896         if (SMU7_VOLTAGE_CONTROL_NONE != hw_data->voltage_control)
1897                 polaris10_populate_smc_voltage_tables(hwmgr, table);
1898
1899         table->SystemFlags = 0;
1900         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1901                         PHM_PlatformCaps_AutomaticDCTransition))
1902                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
1903
1904         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1905                         PHM_PlatformCaps_StepVddc))
1906                 table->SystemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
1907
1908         if (hw_data->is_memory_gddr5)
1909                 table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
1910
1911         if (hw_data->ulv_supported && table_info->us_ulv_voltage_offset) {
1912                 result = polaris10_populate_ulv_state(hwmgr, table);
1913                 PP_ASSERT_WITH_CODE(0 == result,
1914                                 "Failed to initialize ULV state!", return result);
1915                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
1916                                 ixCG_ULV_PARAMETER, SMU7_CGULVPARAMETER_DFLT);
1917         }
1918
1919         result = polaris10_populate_smc_link_level(hwmgr, table);
1920         PP_ASSERT_WITH_CODE(0 == result,
1921                         "Failed to initialize Link Level!", return result);
1922
1923         result = polaris10_populate_all_graphic_levels(hwmgr);
1924         PP_ASSERT_WITH_CODE(0 == result,
1925                         "Failed to initialize Graphics Level!", return result);
1926
1927         result = polaris10_populate_all_memory_levels(hwmgr);
1928         PP_ASSERT_WITH_CODE(0 == result,
1929                         "Failed to initialize Memory Level!", return result);
1930
1931         result = polaris10_populate_smc_acpi_level(hwmgr, table);
1932         PP_ASSERT_WITH_CODE(0 == result,
1933                         "Failed to initialize ACPI Level!", return result);
1934
1935         result = polaris10_populate_smc_vce_level(hwmgr, table);
1936         PP_ASSERT_WITH_CODE(0 == result,
1937                         "Failed to initialize VCE Level!", return result);
1938
1939         result = polaris10_populate_smc_samu_level(hwmgr, table);
1940         PP_ASSERT_WITH_CODE(0 == result,
1941                         "Failed to initialize SAMU Level!", return result);
1942
1943         /* Since only the initial state is completely set up at this point
1944          * (the other states are just copies of the boot state) we only
1945          * need to populate the  ARB settings for the initial state.
1946          */
1947         result = polaris10_program_memory_timing_parameters(hwmgr);
1948         PP_ASSERT_WITH_CODE(0 == result,
1949                         "Failed to Write ARB settings for the initial state.", return result);
1950
1951         result = polaris10_populate_smc_uvd_level(hwmgr, table);
1952         PP_ASSERT_WITH_CODE(0 == result,
1953                         "Failed to initialize UVD Level!", return result);
1954
1955         result = polaris10_populate_smc_boot_level(hwmgr, table);
1956         PP_ASSERT_WITH_CODE(0 == result,
1957                         "Failed to initialize Boot Level!", return result);
1958
1959         result = polaris10_populate_smc_initailial_state(hwmgr);
1960         PP_ASSERT_WITH_CODE(0 == result,
1961                         "Failed to initialize Boot State!", return result);
1962
1963         result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr);
1964         PP_ASSERT_WITH_CODE(0 == result,
1965                         "Failed to populate BAPM Parameters!", return result);
1966
1967         polaris10_populate_zero_rpm_parameters(hwmgr);
1968
1969         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
1970                         PHM_PlatformCaps_ClockStretcher)) {
1971                 result = polaris10_populate_clock_stretcher_data_table(hwmgr);
1972                 PP_ASSERT_WITH_CODE(0 == result,
1973                                 "Failed to populate Clock Stretcher Data Table!",
1974                                 return result);
1975         }
1976
1977         result = polaris10_populate_avfs_parameters(hwmgr);
1978         PP_ASSERT_WITH_CODE(0 == result, "Failed to populate AVFS Parameters!", return result;);
1979
1980         table->CurrSclkPllRange = 0xff;
1981         table->GraphicsVoltageChangeEnable  = 1;
1982         table->GraphicsThermThrottleEnable  = 1;
1983         table->GraphicsInterval = 1;
1984         table->VoltageInterval  = 1;
1985         table->ThermalInterval  = 1;
1986         table->TemperatureLimitHigh =
1987                         table_info->cac_dtp_table->usTargetOperatingTemp *
1988                         SMU7_Q88_FORMAT_CONVERSION_UNIT;
1989         table->TemperatureLimitLow  =
1990                         (table_info->cac_dtp_table->usTargetOperatingTemp - 1) *
1991                         SMU7_Q88_FORMAT_CONVERSION_UNIT;
1992         table->MemoryVoltageChangeEnable = 1;
1993         table->MemoryInterval = 1;
1994         table->VoltageResponseTime = 0;
1995         table->PhaseResponseTime = 0;
1996         table->MemoryThermThrottleEnable = 1;
1997         table->PCIeBootLinkLevel = hw_data->dpm_table.pcie_speed_table.count;
1998         table->PCIeGenInterval = 1;
1999         table->VRConfig = 0;
2000
2001         result = polaris10_populate_vr_config(hwmgr, table);
2002         PP_ASSERT_WITH_CODE(0 == result,
2003                         "Failed to populate VRConfig setting!", return result);
2004         hw_data->vr_config = table->VRConfig;
2005         table->ThermGpio = 17;
2006         table->SclkStepSize = 0x4000;
2007
2008         if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) {
2009                 table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift;
2010                 if (gpio_table)
2011                         table->VRHotLevel = gpio_table->vrhot_triggered_sclk_dpm_index;
2012         } else {
2013                 table->VRHotGpio = SMU7_UNUSED_GPIO_PIN;
2014                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2015                                 PHM_PlatformCaps_RegulatorHot);
2016         }
2017
2018         if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
2019                         &gpio_pin)) {
2020                 table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
2021                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2022                                 PHM_PlatformCaps_AutomaticDCTransition);
2023         } else {
2024                 table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
2025                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2026                                 PHM_PlatformCaps_AutomaticDCTransition);
2027         }
2028
2029         /* Thermal Output GPIO */
2030         if (atomctrl_get_pp_assign_pin(hwmgr, THERMAL_INT_OUTPUT_GPIO_PINID,
2031                         &gpio_pin)) {
2032                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
2033                                 PHM_PlatformCaps_ThermalOutGPIO);
2034
2035                 table->ThermOutGpio = gpio_pin.uc_gpio_pin_bit_shift;
2036
2037                 /* For porlarity read GPIOPAD_A with assigned Gpio pin
2038                  * since VBIOS will program this register to set 'inactive state',
2039                  * driver can then determine 'active state' from this and
2040                  * program SMU with correct polarity
2041                  */
2042                 table->ThermOutPolarity = (0 == (cgs_read_register(hwmgr->device, mmGPIOPAD_A)
2043                                         & (1 << gpio_pin.uc_gpio_pin_bit_shift))) ? 1:0;
2044                 table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_ONLY;
2045
2046                 /* if required, combine VRHot/PCC with thermal out GPIO */
2047                 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)
2048                 && phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CombinePCCWithThermalSignal))
2049                         table->ThermOutMode = SMU7_THERM_OUT_MODE_THERM_VRHOT;
2050         } else {
2051                 table->ThermOutGpio = 17;
2052                 table->ThermOutPolarity = 1;
2053                 table->ThermOutMode = SMU7_THERM_OUT_MODE_DISABLE;
2054         }
2055
2056         /* Populate BIF_SCLK levels into SMC DPM table */
2057         for (i = 0; i <= hw_data->dpm_table.pcie_speed_table.count; i++) {
2058                 result = atomctrl_get_dfs_pll_dividers_vi(hwmgr, smu_data->bif_sclk_table[i], &dividers);
2059                 PP_ASSERT_WITH_CODE((result == 0), "Can not find DFS divide id for Sclk", return result);
2060
2061                 if (i == 0)
2062                         table->Ulv.BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2063                 else
2064                         table->LinkLevel[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
2065         }
2066
2067         for (i = 0; i < SMU74_MAX_ENTRIES_SMIO; i++)
2068                 table->Smio[i] = PP_HOST_TO_SMC_UL(table->Smio[i]);
2069
2070         CONVERT_FROM_HOST_TO_SMC_UL(table->SystemFlags);
2071         CONVERT_FROM_HOST_TO_SMC_UL(table->VRConfig);
2072         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask1);
2073         CONVERT_FROM_HOST_TO_SMC_UL(table->SmioMask2);
2074         CONVERT_FROM_HOST_TO_SMC_UL(table->SclkStepSize);
2075         CONVERT_FROM_HOST_TO_SMC_UL(table->CurrSclkPllRange);
2076         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitHigh);
2077         CONVERT_FROM_HOST_TO_SMC_US(table->TemperatureLimitLow);
2078         CONVERT_FROM_HOST_TO_SMC_US(table->VoltageResponseTime);
2079         CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime);
2080
2081         /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */
2082         result = smu7_copy_bytes_to_smc(hwmgr,
2083                         smu_data->smu7_data.dpm_table_start +
2084                         offsetof(SMU74_Discrete_DpmTable, SystemFlags),
2085                         (uint8_t *)&(table->SystemFlags),
2086                         sizeof(SMU74_Discrete_DpmTable) - 3 * sizeof(SMU74_PIDController),
2087                         SMC_RAM_END);
2088         PP_ASSERT_WITH_CODE(0 == result,
2089                         "Failed to upload dpm data to SMC memory!", return result);
2090
2091         result = polaris10_populate_pm_fuses(hwmgr);
2092         PP_ASSERT_WITH_CODE(0 == result,
2093                         "Failed to  populate PM fuses to SMC memory!", return result);
2094
2095         return 0;
2096 }
2097
2098 static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr)
2099 {
2100         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2101
2102         if (data->need_update_smu7_dpm_table &
2103                 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK))
2104                 return polaris10_program_memory_timing_parameters(hwmgr);
2105
2106         return 0;
2107 }
2108
2109 int polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr)
2110 {
2111         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2112
2113         if (!hwmgr->avfs_supported)
2114                 return 0;
2115
2116         smum_send_msg_to_smc_with_parameter(hwmgr,
2117                         PPSMC_MSG_SetGBDroopSettings, data->avfs_vdroop_override_setting,
2118                         NULL);
2119
2120         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAvfs, NULL);
2121
2122         /* Apply avfs cks-off voltages to avoid the overshoot
2123          * when switching to the highest sclk frequency
2124          */
2125         if (data->apply_avfs_cks_off_voltage)
2126                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ApplyAvfsCksOffVoltage, NULL);
2127
2128         return 0;
2129 }
2130
2131 static int polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
2132 {
2133         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2134         SMU74_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE };
2135         uint32_t duty100;
2136         uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2;
2137         uint16_t fdo_min, slope1, slope2;
2138         uint32_t reference_clock;
2139         int res;
2140         uint64_t tmp64;
2141
2142         if (hwmgr->thermal_controller.fanInfo.bNoFan) {
2143                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2144                         PHM_PlatformCaps_MicrocodeFanControl);
2145                 return 0;
2146         }
2147
2148         if (smu_data->smu7_data.fan_table_start == 0) {
2149                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2150                                 PHM_PlatformCaps_MicrocodeFanControl);
2151                 return 0;
2152         }
2153
2154         duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
2155                         CG_FDO_CTRL1, FMAX_DUTY100);
2156
2157         if (duty100 == 0) {
2158                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2159                                 PHM_PlatformCaps_MicrocodeFanControl);
2160                 return 0;
2161         }
2162
2163         /* use hardware fan control */
2164         if (hwmgr->thermal_controller.use_hw_fan_control)
2165                 return 0;
2166
2167         tmp64 = hwmgr->thermal_controller.advanceFanControlParameters.
2168                         usPWMMin * duty100;
2169         do_div(tmp64, 10000);
2170         fdo_min = (uint16_t)tmp64;
2171
2172         t_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usTMed -
2173                         hwmgr->thermal_controller.advanceFanControlParameters.usTMin;
2174         t_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usTHigh -
2175                         hwmgr->thermal_controller.advanceFanControlParameters.usTMed;
2176
2177         pwm_diff1 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed -
2178                         hwmgr->thermal_controller.advanceFanControlParameters.usPWMMin;
2179         pwm_diff2 = hwmgr->thermal_controller.advanceFanControlParameters.usPWMHigh -
2180                         hwmgr->thermal_controller.advanceFanControlParameters.usPWMMed;
2181
2182         slope1 = (uint16_t)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
2183         slope2 = (uint16_t)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
2184
2185         fan_table.TempMin = cpu_to_be16((50 + hwmgr->
2186                         thermal_controller.advanceFanControlParameters.usTMin) / 100);
2187         fan_table.TempMed = cpu_to_be16((50 + hwmgr->
2188                         thermal_controller.advanceFanControlParameters.usTMed) / 100);
2189         fan_table.TempMax = cpu_to_be16((50 + hwmgr->
2190                         thermal_controller.advanceFanControlParameters.usTMax) / 100);
2191
2192         fan_table.Slope1 = cpu_to_be16(slope1);
2193         fan_table.Slope2 = cpu_to_be16(slope2);
2194
2195         fan_table.FdoMin = cpu_to_be16(fdo_min);
2196
2197         fan_table.HystDown = cpu_to_be16(hwmgr->
2198                         thermal_controller.advanceFanControlParameters.ucTHyst);
2199
2200         fan_table.HystUp = cpu_to_be16(1);
2201
2202         fan_table.HystSlope = cpu_to_be16(1);
2203
2204         fan_table.TempRespLim = cpu_to_be16(5);
2205
2206         reference_clock = amdgpu_asic_get_xclk((struct amdgpu_device *)hwmgr->adev);
2207
2208         fan_table.RefreshPeriod = cpu_to_be32((hwmgr->
2209                         thermal_controller.advanceFanControlParameters.ulCycleDelay *
2210                         reference_clock) / 1600);
2211
2212         fan_table.FdoMax = cpu_to_be16((uint16_t)duty100);
2213
2214         fan_table.TempSrc = (uint8_t)PHM_READ_VFPF_INDIRECT_FIELD(
2215                         hwmgr->device, CGS_IND_REG__SMC,
2216                         CG_MULT_THERMAL_CTRL, TEMP_SEL);
2217
2218         res = smu7_copy_bytes_to_smc(hwmgr, smu_data->smu7_data.fan_table_start,
2219                         (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table),
2220                         SMC_RAM_END);
2221
2222         if (!res && hwmgr->thermal_controller.
2223                         advanceFanControlParameters.ucMinimumPWMLimit)
2224                 res = smum_send_msg_to_smc_with_parameter(hwmgr,
2225                                 PPSMC_MSG_SetFanMinPwm,
2226                                 hwmgr->thermal_controller.
2227                                 advanceFanControlParameters.ucMinimumPWMLimit,
2228                                 NULL);
2229
2230         if (!res && hwmgr->thermal_controller.
2231                         advanceFanControlParameters.ulMinFanSCLKAcousticLimit)
2232                 res = smum_send_msg_to_smc_with_parameter(hwmgr,
2233                                 PPSMC_MSG_SetFanSclkTarget,
2234                                 hwmgr->thermal_controller.
2235                                 advanceFanControlParameters.ulMinFanSCLKAcousticLimit,
2236                                 NULL);
2237
2238         if (res)
2239                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
2240                                 PHM_PlatformCaps_MicrocodeFanControl);
2241
2242         return 0;
2243 }
2244
2245 static int polaris10_update_uvd_smc_table(struct pp_hwmgr *hwmgr)
2246 {
2247         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2248         uint32_t mm_boot_level_offset, mm_boot_level_value;
2249         struct phm_ppt_v1_information *table_info =
2250                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2251
2252         smu_data->smc_state_table.UvdBootLevel = 0;
2253         if (table_info->mm_dep_table->count > 0)
2254                 smu_data->smc_state_table.UvdBootLevel =
2255                                 (uint8_t) (table_info->mm_dep_table->count - 1);
2256         mm_boot_level_offset = smu_data->smu7_data.dpm_table_start + offsetof(SMU74_Discrete_DpmTable,
2257                                                 UvdBootLevel);
2258         mm_boot_level_offset /= 4;
2259         mm_boot_level_offset *= 4;
2260         mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2261                         CGS_IND_REG__SMC, mm_boot_level_offset);
2262         mm_boot_level_value &= 0x00FFFFFF;
2263         mm_boot_level_value |= smu_data->smc_state_table.UvdBootLevel << 24;
2264         cgs_write_ind_register(hwmgr->device,
2265                         CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
2266
2267         if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2268                         PHM_PlatformCaps_UVDDPM) ||
2269                 phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2270                         PHM_PlatformCaps_StablePState))
2271                 smum_send_msg_to_smc_with_parameter(hwmgr,
2272                                 PPSMC_MSG_UVDDPM_SetEnabledMask,
2273                                 (uint32_t)(1 << smu_data->smc_state_table.UvdBootLevel),
2274                                 NULL);
2275         return 0;
2276 }
2277
2278 static int polaris10_update_vce_smc_table(struct pp_hwmgr *hwmgr)
2279 {
2280         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2281         uint32_t mm_boot_level_offset, mm_boot_level_value;
2282         struct phm_ppt_v1_information *table_info =
2283                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2284
2285         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2286                                         PHM_PlatformCaps_StablePState))
2287                 smu_data->smc_state_table.VceBootLevel =
2288                         (uint8_t) (table_info->mm_dep_table->count - 1);
2289         else
2290                 smu_data->smc_state_table.VceBootLevel = 0;
2291
2292         mm_boot_level_offset = smu_data->smu7_data.dpm_table_start +
2293                                         offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
2294         mm_boot_level_offset /= 4;
2295         mm_boot_level_offset *= 4;
2296         mm_boot_level_value = cgs_read_ind_register(hwmgr->device,
2297                         CGS_IND_REG__SMC, mm_boot_level_offset);
2298         mm_boot_level_value &= 0xFF00FFFF;
2299         mm_boot_level_value |= smu_data->smc_state_table.VceBootLevel << 16;
2300         cgs_write_ind_register(hwmgr->device,
2301                         CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
2302
2303         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
2304                 smum_send_msg_to_smc_with_parameter(hwmgr,
2305                                 PPSMC_MSG_VCEDPM_SetEnabledMask,
2306                                 (uint32_t)1 << smu_data->smc_state_table.VceBootLevel,
2307                                 NULL);
2308         return 0;
2309 }
2310
2311 static int polaris10_update_bif_smc_table(struct pp_hwmgr *hwmgr)
2312 {
2313         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2314         struct phm_ppt_v1_information *table_info =
2315                         (struct phm_ppt_v1_information *)(hwmgr->pptable);
2316         struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table;
2317         int max_entry, i;
2318
2319         max_entry = (SMU74_MAX_LEVELS_LINK < pcie_table->count) ?
2320                                                 SMU74_MAX_LEVELS_LINK :
2321                                                 pcie_table->count;
2322         /* Setup BIF_SCLK levels */
2323         for (i = 0; i < max_entry; i++)
2324                 smu_data->bif_sclk_table[i] = pcie_table->entries[i].pcie_sclk;
2325         return 0;
2326 }
2327
2328 static int polaris10_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type)
2329 {
2330         switch (type) {
2331         case SMU_UVD_TABLE:
2332                 polaris10_update_uvd_smc_table(hwmgr);
2333                 break;
2334         case SMU_VCE_TABLE:
2335                 polaris10_update_vce_smc_table(hwmgr);
2336                 break;
2337         case SMU_BIF_TABLE:
2338                 polaris10_update_bif_smc_table(hwmgr);
2339         default:
2340                 break;
2341         }
2342         return 0;
2343 }
2344
2345 static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr)
2346 {
2347         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2348         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2349
2350         int result = 0;
2351         uint32_t low_sclk_interrupt_threshold = 0;
2352
2353         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
2354                         PHM_PlatformCaps_SclkThrottleLowNotification)
2355                 && (data->low_sclk_interrupt_threshold != 0)) {
2356                 low_sclk_interrupt_threshold =
2357                                 data->low_sclk_interrupt_threshold;
2358
2359                 CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
2360
2361                 result = smu7_copy_bytes_to_smc(
2362                                 hwmgr,
2363                                 smu_data->smu7_data.dpm_table_start +
2364                                 offsetof(SMU74_Discrete_DpmTable,
2365                                         LowSclkInterruptThreshold),
2366                                 (uint8_t *)&low_sclk_interrupt_threshold,
2367                                 sizeof(uint32_t),
2368                                 SMC_RAM_END);
2369         }
2370         PP_ASSERT_WITH_CODE((result == 0),
2371                         "Failed to update SCLK threshold!", return result);
2372
2373         result = polaris10_program_mem_timing_parameters(hwmgr);
2374         PP_ASSERT_WITH_CODE((result == 0),
2375                         "Failed to program memory timing parameters!",
2376                         );
2377
2378         return result;
2379 }
2380
2381 static uint32_t polaris10_get_offsetof(uint32_t type, uint32_t member)
2382 {
2383         switch (type) {
2384         case SMU_SoftRegisters:
2385                 switch (member) {
2386                 case HandshakeDisables:
2387                         return offsetof(SMU74_SoftRegisters, HandshakeDisables);
2388                 case VoltageChangeTimeout:
2389                         return offsetof(SMU74_SoftRegisters, VoltageChangeTimeout);
2390                 case AverageGraphicsActivity:
2391                         return offsetof(SMU74_SoftRegisters, AverageGraphicsActivity);
2392                 case AverageMemoryActivity:
2393                         return offsetof(SMU74_SoftRegisters, AverageMemoryActivity);
2394                 case PreVBlankGap:
2395                         return offsetof(SMU74_SoftRegisters, PreVBlankGap);
2396                 case VBlankTimeout:
2397                         return offsetof(SMU74_SoftRegisters, VBlankTimeout);
2398                 case UcodeLoadStatus:
2399                         return offsetof(SMU74_SoftRegisters, UcodeLoadStatus);
2400                 case DRAM_LOG_ADDR_H:
2401                         return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_H);
2402                 case DRAM_LOG_ADDR_L:
2403                         return offsetof(SMU74_SoftRegisters, DRAM_LOG_ADDR_L);
2404                 case DRAM_LOG_PHY_ADDR_H:
2405                         return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_H);
2406                 case DRAM_LOG_PHY_ADDR_L:
2407                         return offsetof(SMU74_SoftRegisters, DRAM_LOG_PHY_ADDR_L);
2408                 case DRAM_LOG_BUFF_SIZE:
2409                         return offsetof(SMU74_SoftRegisters, DRAM_LOG_BUFF_SIZE);
2410                 }
2411                 break;
2412         case SMU_Discrete_DpmTable:
2413                 switch (member) {
2414                 case UvdBootLevel:
2415                         return offsetof(SMU74_Discrete_DpmTable, UvdBootLevel);
2416                 case VceBootLevel:
2417                         return offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
2418                 case LowSclkInterruptThreshold:
2419                         return offsetof(SMU74_Discrete_DpmTable, LowSclkInterruptThreshold);
2420                 }
2421                 break;
2422         }
2423         pr_warn("can't get the offset of type %x member %x\n", type, member);
2424         return 0;
2425 }
2426
2427 static uint32_t polaris10_get_mac_definition(uint32_t value)
2428 {
2429         switch (value) {
2430         case SMU_MAX_LEVELS_GRAPHICS:
2431                 return SMU74_MAX_LEVELS_GRAPHICS;
2432         case SMU_MAX_LEVELS_MEMORY:
2433                 return SMU74_MAX_LEVELS_MEMORY;
2434         case SMU_MAX_LEVELS_LINK:
2435                 return SMU74_MAX_LEVELS_LINK;
2436         case SMU_MAX_ENTRIES_SMIO:
2437                 return SMU74_MAX_ENTRIES_SMIO;
2438         case SMU_MAX_LEVELS_VDDC:
2439                 return SMU74_MAX_LEVELS_VDDC;
2440         case SMU_MAX_LEVELS_VDDGFX:
2441                 return SMU74_MAX_LEVELS_VDDGFX;
2442         case SMU_MAX_LEVELS_VDDCI:
2443                 return SMU74_MAX_LEVELS_VDDCI;
2444         case SMU_MAX_LEVELS_MVDD:
2445                 return SMU74_MAX_LEVELS_MVDD;
2446         case SMU_UVD_MCLK_HANDSHAKE_DISABLE:
2447                 return SMU7_UVD_MCLK_HANDSHAKE_DISABLE;
2448         }
2449
2450         pr_warn("can't get the mac of %x\n", value);
2451         return 0;
2452 }
2453
2454 static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr)
2455 {
2456         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2457         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2458         uint32_t tmp;
2459         int result;
2460         bool error = false;
2461
2462         result = smu7_read_smc_sram_dword(hwmgr,
2463                         SMU7_FIRMWARE_HEADER_LOCATION +
2464                         offsetof(SMU74_Firmware_Header, DpmTable),
2465                         &tmp, SMC_RAM_END);
2466
2467         if (0 == result)
2468                 smu_data->smu7_data.dpm_table_start = tmp;
2469
2470         error |= (0 != result);
2471
2472         result = smu7_read_smc_sram_dword(hwmgr,
2473                         SMU7_FIRMWARE_HEADER_LOCATION +
2474                         offsetof(SMU74_Firmware_Header, SoftRegisters),
2475                         &tmp, SMC_RAM_END);
2476
2477         if (!result) {
2478                 data->soft_regs_start = tmp;
2479                 smu_data->smu7_data.soft_regs_start = tmp;
2480         }
2481
2482         error |= (0 != result);
2483
2484         result = smu7_read_smc_sram_dword(hwmgr,
2485                         SMU7_FIRMWARE_HEADER_LOCATION +
2486                         offsetof(SMU74_Firmware_Header, mcRegisterTable),
2487                         &tmp, SMC_RAM_END);
2488
2489         if (!result)
2490                 smu_data->smu7_data.mc_reg_table_start = tmp;
2491
2492         result = smu7_read_smc_sram_dword(hwmgr,
2493                         SMU7_FIRMWARE_HEADER_LOCATION +
2494                         offsetof(SMU74_Firmware_Header, FanTable),
2495                         &tmp, SMC_RAM_END);
2496
2497         if (!result)
2498                 smu_data->smu7_data.fan_table_start = tmp;
2499
2500         error |= (0 != result);
2501
2502         result = smu7_read_smc_sram_dword(hwmgr,
2503                         SMU7_FIRMWARE_HEADER_LOCATION +
2504                         offsetof(SMU74_Firmware_Header, mcArbDramTimingTable),
2505                         &tmp, SMC_RAM_END);
2506
2507         if (!result)
2508                 smu_data->smu7_data.arb_table_start = tmp;
2509
2510         error |= (0 != result);
2511
2512         result = smu7_read_smc_sram_dword(hwmgr,
2513                         SMU7_FIRMWARE_HEADER_LOCATION +
2514                         offsetof(SMU74_Firmware_Header, Version),
2515                         &tmp, SMC_RAM_END);
2516
2517         if (!result)
2518                 hwmgr->microcode_version_info.SMC = tmp;
2519
2520         error |= (0 != result);
2521
2522         return error ? -1 : 0;
2523 }
2524
2525 static uint8_t polaris10_get_memory_modile_index(struct pp_hwmgr *hwmgr)
2526 {
2527         return (uint8_t) (0xFF & (cgs_read_register(hwmgr->device, mmBIOS_SCRATCH_4) >> 16));
2528 }
2529
2530 static int polaris10_initialize_mc_reg_table(struct pp_hwmgr *hwmgr)
2531 {
2532         int result;
2533         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smu_backend);
2534         pp_atomctrl_mc_reg_table *mc_reg_table = &smu_data->mc_reg_table;
2535         uint8_t module_index = polaris10_get_memory_modile_index(hwmgr);
2536
2537         memset(mc_reg_table, 0, sizeof(pp_atomctrl_mc_reg_table));
2538         result = atomctrl_initialize_mc_reg_table_v2_2(hwmgr, module_index, mc_reg_table);
2539
2540         return result;
2541 }
2542
2543 static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr)
2544 {
2545         return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device,
2546                         CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON))
2547                         ? true : false;
2548 }
2549
2550 static int polaris10_update_dpm_settings(struct pp_hwmgr *hwmgr,
2551                                 void *profile_setting)
2552 {
2553         struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
2554         struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)
2555                         (hwmgr->smu_backend);
2556         struct profile_mode_setting *setting;
2557         struct SMU74_Discrete_GraphicsLevel *levels =
2558                         smu_data->smc_state_table.GraphicsLevel;
2559         uint32_t array = smu_data->smu7_data.dpm_table_start +
2560                         offsetof(SMU74_Discrete_DpmTable, GraphicsLevel);
2561
2562         uint32_t mclk_array = smu_data->smu7_data.dpm_table_start +
2563                         offsetof(SMU74_Discrete_DpmTable, MemoryLevel);
2564         struct SMU74_Discrete_MemoryLevel *mclk_levels =
2565                         smu_data->smc_state_table.MemoryLevel;
2566         uint32_t i;
2567         uint32_t offset, up_hyst_offset, down_hyst_offset, clk_activity_offset, tmp;
2568
2569         if (profile_setting == NULL)
2570                 return -EINVAL;
2571
2572         setting = (struct profile_mode_setting *)profile_setting;
2573
2574         if (setting->bupdate_sclk) {
2575                 if (!data->sclk_dpm_key_disabled)
2576                         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_FreezeLevel, NULL);
2577                 for (i = 0; i < smu_data->smc_state_table.GraphicsDpmLevelCount; i++) {
2578                         if (levels[i].ActivityLevel !=
2579                                 cpu_to_be16(setting->sclk_activity)) {
2580                                 levels[i].ActivityLevel = cpu_to_be16(setting->sclk_activity);
2581
2582                                 clk_activity_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
2583                                                 + offsetof(SMU74_Discrete_GraphicsLevel, ActivityLevel);
2584                                 offset = clk_activity_offset & ~0x3;
2585                                 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2586                                 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, levels[i].ActivityLevel, sizeof(uint16_t));
2587                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2588
2589                         }
2590                         if (levels[i].UpHyst != setting->sclk_up_hyst ||
2591                                 levels[i].DownHyst != setting->sclk_down_hyst) {
2592                                 levels[i].UpHyst = setting->sclk_up_hyst;
2593                                 levels[i].DownHyst = setting->sclk_down_hyst;
2594                                 up_hyst_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
2595                                                 + offsetof(SMU74_Discrete_GraphicsLevel, UpHyst);
2596                                 down_hyst_offset = array + (sizeof(SMU74_Discrete_GraphicsLevel) * i)
2597                                                 + offsetof(SMU74_Discrete_GraphicsLevel, DownHyst);
2598                                 offset = up_hyst_offset & ~0x3;
2599                                 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2600                                 tmp = phm_set_field_to_u32(up_hyst_offset, tmp, levels[i].UpHyst, sizeof(uint8_t));
2601                                 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, levels[i].DownHyst, sizeof(uint8_t));
2602                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2603                         }
2604                 }
2605                 if (!data->sclk_dpm_key_disabled)
2606                         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SCLKDPM_UnfreezeLevel, NULL);
2607         }
2608
2609         if (setting->bupdate_mclk) {
2610                 if (!data->mclk_dpm_key_disabled)
2611                         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_FreezeLevel, NULL);
2612                 for (i = 0; i < smu_data->smc_state_table.MemoryDpmLevelCount; i++) {
2613                         if (mclk_levels[i].ActivityLevel !=
2614                                 cpu_to_be16(setting->mclk_activity)) {
2615                                 mclk_levels[i].ActivityLevel = cpu_to_be16(setting->mclk_activity);
2616
2617                                 clk_activity_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
2618                                                 + offsetof(SMU74_Discrete_MemoryLevel, ActivityLevel);
2619                                 offset = clk_activity_offset & ~0x3;
2620                                 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2621                                 tmp = phm_set_field_to_u32(clk_activity_offset, tmp, mclk_levels[i].ActivityLevel, sizeof(uint16_t));
2622                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2623
2624                         }
2625                         if (mclk_levels[i].UpHyst != setting->mclk_up_hyst ||
2626                                 mclk_levels[i].DownHyst != setting->mclk_down_hyst) {
2627                                 mclk_levels[i].UpHyst = setting->mclk_up_hyst;
2628                                 mclk_levels[i].DownHyst = setting->mclk_down_hyst;
2629                                 up_hyst_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
2630                                                 + offsetof(SMU74_Discrete_MemoryLevel, UpHyst);
2631                                 down_hyst_offset = mclk_array + (sizeof(SMU74_Discrete_MemoryLevel) * i)
2632                                                 + offsetof(SMU74_Discrete_MemoryLevel, DownHyst);
2633                                 offset = up_hyst_offset & ~0x3;
2634                                 tmp = PP_HOST_TO_SMC_UL(cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset));
2635                                 tmp = phm_set_field_to_u32(up_hyst_offset, tmp, mclk_levels[i].UpHyst, sizeof(uint8_t));
2636                                 tmp = phm_set_field_to_u32(down_hyst_offset, tmp, mclk_levels[i].DownHyst, sizeof(uint8_t));
2637                                 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, offset, PP_HOST_TO_SMC_UL(tmp));
2638                         }
2639                 }
2640                 if (!data->mclk_dpm_key_disabled)
2641                         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_MCLKDPM_UnfreezeLevel, NULL);
2642         }
2643         return 0;
2644 }
2645
2646 const struct pp_smumgr_func polaris10_smu_funcs = {
2647         .name = "polaris10_smu",
2648         .smu_init = polaris10_smu_init,
2649         .smu_fini = smu7_smu_fini,
2650         .start_smu = polaris10_start_smu,
2651         .check_fw_load_finish = smu7_check_fw_load_finish,
2652         .request_smu_load_fw = smu7_reload_firmware,
2653         .request_smu_load_specific_fw = NULL,
2654         .send_msg_to_smc = smu7_send_msg_to_smc,
2655         .send_msg_to_smc_with_parameter = smu7_send_msg_to_smc_with_parameter,
2656         .get_argument = smu7_get_argument,
2657         .download_pptable_settings = NULL,
2658         .upload_pptable_settings = NULL,
2659         .update_smc_table = polaris10_update_smc_table,
2660         .get_offsetof = polaris10_get_offsetof,
2661         .process_firmware_header = polaris10_process_firmware_header,
2662         .init_smc_table = polaris10_init_smc_table,
2663         .update_sclk_threshold = polaris10_update_sclk_threshold,
2664         .thermal_avfs_enable = polaris10_thermal_avfs_enable,
2665         .thermal_setup_fan_table = polaris10_thermal_setup_fan_table,
2666         .populate_all_graphic_levels = polaris10_populate_all_graphic_levels,
2667         .populate_all_memory_levels = polaris10_populate_all_memory_levels,
2668         .get_mac_definition = polaris10_get_mac_definition,
2669         .initialize_mc_reg_table = polaris10_initialize_mc_reg_table,
2670         .is_dpm_running = polaris10_is_dpm_running,
2671         .is_hw_avfs_present = polaris10_is_hw_avfs_present,
2672         .update_dpm_settings = polaris10_update_dpm_settings,
2673 };