drivers/gpu/drm/amd/pm/powerplay/si_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26
  27 #include "amdgpu.h"
  28 #include "amdgpu_pm.h"
  29 #include "amdgpu_dpm.h"
  30 #include "amdgpu_atombios.h"
  31 #include "amd_pcie.h"
  32 #include "sid.h"
  33 #include "r600_dpm.h"
  34 #include "si_dpm.h"
  35 #include "atom.h"
  36 #include "../include/pptable.h"
  37 #include <linux/math64.h>
  38 #include <linux/seq_file.h>
  39 #include <linux/firmware.h>
  40
  41 #define MC_CG_ARB_FREQ_F0           0x0a
  42 #define MC_CG_ARB_FREQ_F1           0x0b
  43 #define MC_CG_ARB_FREQ_F2           0x0c
  44 #define MC_CG_ARB_FREQ_F3           0x0d
  45
  46 #define SMC_RAM_END                 0x20000
  47
  48 #define SCLK_MIN_DEEPSLEEP_FREQ     1350
  49
  50
  51 /* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
  52 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
  53 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
  54 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
  55 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
  56 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
  57 #define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
  58
  59 #define BIOS_SCRATCH_4                                    0x5cd
  60
  61 MODULE_FIRMWARE("amdgpu/tahiti_smc.bin");
  62 MODULE_FIRMWARE("amdgpu/pitcairn_smc.bin");
  63 MODULE_FIRMWARE("amdgpu/pitcairn_k_smc.bin");
  64 MODULE_FIRMWARE("amdgpu/verde_smc.bin");
  65 MODULE_FIRMWARE("amdgpu/verde_k_smc.bin");
  66 MODULE_FIRMWARE("amdgpu/oland_smc.bin");
  67 MODULE_FIRMWARE("amdgpu/oland_k_smc.bin");
  68 MODULE_FIRMWARE("amdgpu/hainan_smc.bin");
  69 MODULE_FIRMWARE("amdgpu/hainan_k_smc.bin");
  70 MODULE_FIRMWARE("amdgpu/banks_k_2_smc.bin");
  71
  72 static const struct amd_pm_funcs si_dpm_funcs;
  73
  74 union power_info {
  75         struct _ATOM_POWERPLAY_INFO info;
  76         struct _ATOM_POWERPLAY_INFO_V2 info_2;
  77         struct _ATOM_POWERPLAY_INFO_V3 info_3;
  78         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
  79         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
  80         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
  81         struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
  82         struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
  83 };
  84
  85 union fan_info {
  86         struct _ATOM_PPLIB_FANTABLE fan;
  87         struct _ATOM_PPLIB_FANTABLE2 fan2;
  88         struct _ATOM_PPLIB_FANTABLE3 fan3;
  89 };
  90
  91 union pplib_clock_info {
  92         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
  93         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
  94         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
  95         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
  96         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
  97 };
  98
  99 static const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
 100 {
 101         R600_UTC_DFLT_00,
 102         R600_UTC_DFLT_01,
 103         R600_UTC_DFLT_02,
 104         R600_UTC_DFLT_03,
 105         R600_UTC_DFLT_04,
 106         R600_UTC_DFLT_05,
 107         R600_UTC_DFLT_06,
 108         R600_UTC_DFLT_07,
 109         R600_UTC_DFLT_08,
 110         R600_UTC_DFLT_09,
 111         R600_UTC_DFLT_10,
 112         R600_UTC_DFLT_11,
 113         R600_UTC_DFLT_12,
 114         R600_UTC_DFLT_13,
 115         R600_UTC_DFLT_14,
 116 };
 117
 118 static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
 119 {
 120         R600_DTC_DFLT_00,
 121         R600_DTC_DFLT_01,
 122         R600_DTC_DFLT_02,
 123         R600_DTC_DFLT_03,
 124         R600_DTC_DFLT_04,
 125         R600_DTC_DFLT_05,
 126         R600_DTC_DFLT_06,
 127         R600_DTC_DFLT_07,
 128         R600_DTC_DFLT_08,
 129         R600_DTC_DFLT_09,
 130         R600_DTC_DFLT_10,
 131         R600_DTC_DFLT_11,
 132         R600_DTC_DFLT_12,
 133         R600_DTC_DFLT_13,
 134         R600_DTC_DFLT_14,
 135 };
 136
 137 static const struct si_cac_config_reg cac_weights_tahiti[] =
 138 {
 139         { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
 140         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 141         { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
 142         { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
 143         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 144         { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 145         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 146         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 147         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 148         { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
 149         { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 150         { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
 151         { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
 152         { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
 153         { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
 154         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 155         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 156         { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
 157         { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 158         { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
 159         { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
 160         { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
 161         { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 162         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 163         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 164         { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 165         { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 166         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 167         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 168         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 169         { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
 170         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 171         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 172         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 173         { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 174         { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 175         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 176         { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
 177         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 178         { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
 179         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 180         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 181         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 182         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 183         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 184         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 185         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 186         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 187         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 188         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 189         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 190         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 191         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 192         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 193         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 194         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 195         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 196         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 197         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 198         { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
 199         { 0xFFFFFFFF }
 200 };
 201
 202 static const struct si_cac_config_reg lcac_tahiti[] =
 203 {
 204         { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 205         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 206         { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 207         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 208         { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 209         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 210         { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 211         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 212         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 213         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 214         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 215         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 216         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 217         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 218         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 219         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 220         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 221         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 222         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 223         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 224         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 225         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 226         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 227         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 228         { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 229         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 230         { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 231         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 232         { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 233         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 234         { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 235         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 236         { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 237         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 238         { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 239         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 240         { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 241         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 242         { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 243         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 244         { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 245         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 246         { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 247         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 248         { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 249         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 250         { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 251         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 252         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 253         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 254         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 255         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 256         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 257         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 258         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 259         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 260         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 261         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 262         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 263         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 264         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 265         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 266         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 267         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 268         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 269         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 270         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 271         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 272         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 273         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 274         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 275         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 276         { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
 277         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 278         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 279         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 280         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 281         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 282         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 283         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 284         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 285         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 286         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 287         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 288         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 289         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 290         { 0xFFFFFFFF }
 291
 292 };
 293
 294 static const struct si_cac_config_reg cac_override_tahiti[] =
 295 {
 296         { 0xFFFFFFFF }
 297 };
 298
 299 static const struct si_powertune_data powertune_data_tahiti =
 300 {
 301         ((1 << 16) | 27027),
 302         6,
 303         0,
 304         4,
 305         95,
 306         {
 307                 0UL,
 308                 0UL,
 309                 4521550UL,
 310                 309631529UL,
 311                 -1270850L,
 312                 4513710L,
 313                 40
 314         },
 315         595000000UL,
 316         12,
 317         {
 318                 0,
 319                 0,
 320                 0,
 321                 0,
 322                 0,
 323                 0,
 324                 0,
 325                 0
 326         },
 327         true
 328 };
 329
 330 static const struct si_dte_data dte_data_tahiti =
 331 {
 332         { 1159409, 0, 0, 0, 0 },
 333         { 777, 0, 0, 0, 0 },
 334         2,
 335         54000,
 336         127000,
 337         25,
 338         2,
 339         10,
 340         13,
 341         { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
 342         { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
 343         { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
 344         85,
 345         false
 346 };
 347
 348 static const struct si_dte_data dte_data_tahiti_pro =
 349 {
 350         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 351         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 352         5,
 353         45000,
 354         100,
 355         0xA,
 356         1,
 357         0,
 358         0x10,
 359         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 360         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 361         { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 362         90,
 363         true
 364 };
 365
 366 static const struct si_dte_data dte_data_new_zealand =
 367 {
 368         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
 369         { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
 370         0x5,
 371         0xAFC8,
 372         0x69,
 373         0x32,
 374         1,
 375         0,
 376         0x10,
 377         { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
 378         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 379         { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
 380         85,
 381         true
 382 };
 383
 384 static const struct si_dte_data dte_data_aruba_pro =
 385 {
 386         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 387         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 388         5,
 389         45000,
 390         100,
 391         0xA,
 392         1,
 393         0,
 394         0x10,
 395         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 396         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 397         { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 398         90,
 399         true
 400 };
 401
 402 static const struct si_dte_data dte_data_malta =
 403 {
 404         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 405         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 406         5,
 407         45000,
 408         100,
 409         0xA,
 410         1,
 411         0,
 412         0x10,
 413         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 414         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 415         { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 416         90,
 417         true
 418 };
 419
 420 static const struct si_cac_config_reg cac_weights_pitcairn[] =
 421 {
 422         { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
 423         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 424         { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 425         { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
 426         { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
 427         { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 428         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 429         { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
 430         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 431         { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
 432         { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
 433         { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
 434         { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
 435         { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
 436         { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 437         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 438         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 439         { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
 440         { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
 441         { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
 442         { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
 443         { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
 444         { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
 445         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 446         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 447         { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
 448         { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
 449         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 450         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 451         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 452         { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
 453         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 454         { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
 455         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 456         { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
 457         { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
 458         { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
 459         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 460         { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
 461         { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 462         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 463         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 464         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 465         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 466         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 467         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 468         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 469         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 470         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 471         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 472         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 473         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 474         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 475         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 476         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 477         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 478         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 479         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 480         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 481         { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
 482         { 0xFFFFFFFF }
 483 };
 484
 485 static const struct si_cac_config_reg lcac_pitcairn[] =
 486 {
 487         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 488         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 489         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 490         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 491         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 492         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 493         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 494         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 495         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 496         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 497         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 498         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 499         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 500         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 501         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 502         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 503         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 504         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 505         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 506         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 507         { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 508         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 509         { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 510         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 511         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 512         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 513         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 514         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 515         { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 516         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 517         { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 518         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 519         { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 520         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 521         { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 522         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 523         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 524         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 525         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 526         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 527         { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 528         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 529         { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 530         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 531         { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 532         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 533         { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 534         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 535         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 536         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 537         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 538         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 539         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 540         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 541         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 542         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 543         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 544         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 545         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 546         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 547         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 548         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 549         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 550         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 551         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 552         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 553         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 554         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 555         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 556         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 557         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 558         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 559         { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 560         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 561         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 562         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 563         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 564         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 565         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 566         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 567         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 568         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 569         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 570         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 571         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 572         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 573         { 0xFFFFFFFF }
 574 };
 575
 576 static const struct si_cac_config_reg cac_override_pitcairn[] =
 577 {
 578     { 0xFFFFFFFF }
 579 };
 580
 581 static const struct si_powertune_data powertune_data_pitcairn =
 582 {
 583         ((1 << 16) | 27027),
 584         5,
 585         0,
 586         6,
 587         100,
 588         {
 589                 51600000UL,
 590                 1800000UL,
 591                 7194395UL,
 592                 309631529UL,
 593                 -1270850L,
 594                 4513710L,
 595                 100
 596         },
 597         117830498UL,
 598         12,
 599         {
 600                 0,
 601                 0,
 602                 0,
 603                 0,
 604                 0,
 605                 0,
 606                 0,
 607                 0
 608         },
 609         true
 610 };
 611
 612 static const struct si_dte_data dte_data_pitcairn =
 613 {
 614         { 0, 0, 0, 0, 0 },
 615         { 0, 0, 0, 0, 0 },
 616         0,
 617         0,
 618         0,
 619         0,
 620         0,
 621         0,
 622         0,
 623         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 624         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 625         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 626         0,
 627         false
 628 };
 629
 630 static const struct si_dte_data dte_data_curacao_xt =
 631 {
 632         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 633         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 634         5,
 635         45000,
 636         100,
 637         0xA,
 638         1,
 639         0,
 640         0x10,
 641         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 642         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 643         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 644         90,
 645         true
 646 };
 647
 648 static const struct si_dte_data dte_data_curacao_pro =
 649 {
 650         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 651         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 652         5,
 653         45000,
 654         100,
 655         0xA,
 656         1,
 657         0,
 658         0x10,
 659         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 660         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 661         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 662         90,
 663         true
 664 };
 665
 666 static const struct si_dte_data dte_data_neptune_xt =
 667 {
 668         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 669         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 670         5,
 671         45000,
 672         100,
 673         0xA,
 674         1,
 675         0,
 676         0x10,
 677         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 678         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 679         { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 680         90,
 681         true
 682 };
 683
 684 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
 685 {
 686         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 687         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 688         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 689         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 690         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 691         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 692         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 693         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 694         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 695         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 696         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 697         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 698         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 699         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 700         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 701         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 702         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 703         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 704         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 705         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 706         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 707         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 708         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 709         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 710         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 711         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 712         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 713         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 714         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 715         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 716         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 717         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 718         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 719         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 720         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 721         { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
 722         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 723         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 724         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 725         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 726         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 727         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 728         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 729         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 730         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 731         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 732         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 733         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 734         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 735         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 736         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 737         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 738         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 739         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 740         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 741         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 742         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 743         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 744         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 745         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 746         { 0xFFFFFFFF }
 747 };
 748
 749 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
 750 {
 751         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 752         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 753         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 754         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 755         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 756         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 757         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 758         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 759         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 760         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 761         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 762         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 763         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 764         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 765         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 766         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 767         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 768         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 769         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 770         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 771         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 772         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 773         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 774         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 775         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 776         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 777         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 778         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 779         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 780         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 781         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 782         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 783         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 784         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 785         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 786         { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
 787         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 788         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 789         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 790         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 791         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 792         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 793         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 794         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 795         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 796         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 797         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 798         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 799         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 800         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 801         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 802         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 803         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 804         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 805         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 806         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 807         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 808         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 809         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 810         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 811         { 0xFFFFFFFF }
 812 };
 813
 814 static const struct si_cac_config_reg cac_weights_heathrow[] =
 815 {
 816         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 817         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 818         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 819         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 820         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 821         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 822         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 823         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 824         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 825         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 826         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 827         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 828         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 829         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 830         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 831         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 832         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 833         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 834         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 835         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 836         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 837         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 838         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 839         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 840         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 841         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 842         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 843         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 844         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 845         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 846         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 847         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 848         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 849         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 850         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 851         { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
 852         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 853         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 854         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 855         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 856         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 857         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 858         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 859         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 860         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 861         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 862         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 863         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 864         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 865         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 866         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 867         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 868         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 869         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 870         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 871         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 872         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 873         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 874         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 875         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 876         { 0xFFFFFFFF }
 877 };
 878
 879 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
 880 {
 881         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 882         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 883         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 884         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 885         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 886         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 887         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 888         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 889         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 890         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 891         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 892         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 893         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 894         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 895         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 896         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 897         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 898         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 899         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 900         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 901         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 902         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 903         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 904         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 905         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 906         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 907         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 908         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 909         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 910         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 911         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 912         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 913         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 914         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 915         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 916         { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
 917         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 918         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 919         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 920         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 921         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 922         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 923         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 924         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 925         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 926         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 927         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 928         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 929         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 930         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 931         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 932         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 933         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 934         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 935         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 936         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 937         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 938         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 939         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 940         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 941         { 0xFFFFFFFF }
 942 };
 943
 944 static const struct si_cac_config_reg cac_weights_cape_verde[] =
 945 {
 946         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 947         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 948         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 949         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 950         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 951         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 952         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 953         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 954         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 955         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 956         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 957         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 958         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 959         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 960         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 961         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 962         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 963         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 964         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 965         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 966         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 967         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 968         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 969         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 970         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 971         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 972         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 973         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 974         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 975         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 976         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 977         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 978         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 979         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 980         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 981         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
 982         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 983         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 984         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 985         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 986         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 987         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 988         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 989         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 990         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 991         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 992         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 993         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 994         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 995         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 996         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 997         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 998         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 999         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1000         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1001         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1002         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1003         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1004         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1005         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1006         { 0xFFFFFFFF }
1007 };
1008
1009 static const struct si_cac_config_reg lcac_cape_verde[] =
1010 {
1011         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1012         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1013         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1014         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1015         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1016         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1017         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1018         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1019         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1020         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1021         { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1022         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1023         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1024         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1025         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1026         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1027         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1028         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1029         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1030         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1031         { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1032         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1033         { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1034         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1035         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1036         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1037         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1038         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1039         { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1040         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1041         { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1042         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1043         { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1044         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1045         { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1046         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1047         { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1048         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1049         { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1050         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1051         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1052         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1053         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1054         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1055         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1056         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1057         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1058         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1059         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1060         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1061         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1062         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1063         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1064         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1065         { 0xFFFFFFFF }
1066 };
1067
1068 static const struct si_cac_config_reg cac_override_cape_verde[] =
1069 {
1070     { 0xFFFFFFFF }
1071 };
1072
1073 static const struct si_powertune_data powertune_data_cape_verde =
1074 {
1075         ((1 << 16) | 0x6993),
1076         5,
1077         0,
1078         7,
1079         105,
1080         {
1081                 0UL,
1082                 0UL,
1083                 7194395UL,
1084                 309631529UL,
1085                 -1270850L,
1086                 4513710L,
1087                 100
1088         },
1089         117830498UL,
1090         12,
1091         {
1092                 0,
1093                 0,
1094                 0,
1095                 0,
1096                 0,
1097                 0,
1098                 0,
1099                 0
1100         },
1101         true
1102 };
1103
1104 static const struct si_dte_data dte_data_cape_verde =
1105 {
1106         { 0, 0, 0, 0, 0 },
1107         { 0, 0, 0, 0, 0 },
1108         0,
1109         0,
1110         0,
1111         0,
1112         0,
1113         0,
1114         0,
1115         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1116         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1117         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1118         0,
1119         false
1120 };
1121
1122 static const struct si_dte_data dte_data_venus_xtx =
1123 {
1124         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1125         { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1126         5,
1127         55000,
1128         0x69,
1129         0xA,
1130         1,
1131         0,
1132         0x3,
1133         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1134         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1135         { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1136         90,
1137         true
1138 };
1139
1140 static const struct si_dte_data dte_data_venus_xt =
1141 {
1142         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1143         { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1144         5,
1145         55000,
1146         0x69,
1147         0xA,
1148         1,
1149         0,
1150         0x3,
1151         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1152         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1153         { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1154         90,
1155         true
1156 };
1157
1158 static const struct si_dte_data dte_data_venus_pro =
1159 {
1160         {  0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1161         { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1162         5,
1163         55000,
1164         0x69,
1165         0xA,
1166         1,
1167         0,
1168         0x3,
1169         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1170         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1171         { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1172         90,
1173         true
1174 };
1175
1176 static const struct si_cac_config_reg cac_weights_oland[] =
1177 {
1178         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1179         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1180         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1181         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1182         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1183         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1184         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1185         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1186         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1187         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1188         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1189         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1190         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1191         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1192         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1193         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1194         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1195         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1196         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1197         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1198         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1199         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1200         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1201         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1202         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1203         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1204         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1205         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1206         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1207         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1208         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1209         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1210         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1211         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1212         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1213         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1214         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1215         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1216         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1217         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1218         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1219         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1220         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1221         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1222         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1223         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1224         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1225         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1226         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1227         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1228         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1229         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1230         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1231         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1232         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1233         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1234         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1235         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1236         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1237         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1238         { 0xFFFFFFFF }
1239 };
1240
1241 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1242 {
1243         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1244         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1245         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1246         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1247         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1248         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1249         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1250         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1251         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1252         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1253         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1254         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1255         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1256         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1257         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1258         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1259         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1260         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1261         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1262         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1263         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1264         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1265         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1266         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1267         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1268         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1269         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1270         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1271         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1272         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1273         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1274         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1275         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1276         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1277         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1278         { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1279         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1280         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1281         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1282         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1283         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1284         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1285         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1286         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1287         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1288         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1289         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1290         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1291         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1292         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1293         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1294         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1295         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1296         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1297         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1298         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1299         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1300         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1301         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1302         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1303         { 0xFFFFFFFF }
1304 };
1305
1306 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1307 {
1308         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1309         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1310         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1311         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1312         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1313         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1314         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1315         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1316         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1317         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1318         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1319         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1320         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1321         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1322         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1323         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1324         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1325         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1326         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1327         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1328         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1329         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1330         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1331         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1332         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1333         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1334         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1335         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1336         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1337         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1338         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1339         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1340         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1341         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1342         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1343         { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1344         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1345         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1346         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1347         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1348         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1349         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1350         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1351         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1352         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1353         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1354         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1355         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1356         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1357         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1358         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1359         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1360         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1361         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1362         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1363         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1364         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1365         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1366         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1367         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1368         { 0xFFFFFFFF }
1369 };
1370
1371 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1372 {
1373         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1374         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1375         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1376         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1377         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1378         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1379         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1380         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1381         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1382         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1383         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1384         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1385         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1386         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1387         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1388         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1389         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1390         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1391         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1392         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1393         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1394         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1395         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1396         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1397         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1398         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1399         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1400         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1401         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1402         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1403         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1404         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1405         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1406         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1407         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1408         { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1409         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1410         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1411         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1412         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1413         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1414         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1415         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1416         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1417         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1418         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1419         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1420         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1421         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1422         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1423         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1424         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1425         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1426         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1427         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1428         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1429         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1430         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1431         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1432         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1433         { 0xFFFFFFFF }
1434 };
1435
1436 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1437 {
1438         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1439         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1440         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1441         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1442         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1443         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1444         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1445         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1446         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1447         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1448         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1449         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1450         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1451         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1452         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1453         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1454         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1455         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1456         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1457         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1458         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1459         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1460         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1461         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1462         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1463         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1464         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1465         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1466         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1467         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1468         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1469         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1470         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1471         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1472         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1473         { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1474         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1475         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1476         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1477         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1478         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1479         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1480         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1481         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1482         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1483         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1484         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1485         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1486         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1487         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1488         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1489         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1490         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1491         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1492         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1493         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1494         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1495         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1496         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1497         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1498         { 0xFFFFFFFF }
1499 };
1500
1501 static const struct si_cac_config_reg lcac_oland[] =
1502 {
1503         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1504         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1505         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1506         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1507         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1508         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1509         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1510         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1511         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1512         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1513         { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1514         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1515         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1516         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1517         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1518         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1519         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1520         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1521         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1522         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1523         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1524         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1525         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1526         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1527         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1528         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1529         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1530         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1531         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1532         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1533         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1534         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1535         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1536         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1537         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1538         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1539         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1540         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1541         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1542         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1543         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1544         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1545         { 0xFFFFFFFF }
1546 };
1547
1548 static const struct si_cac_config_reg lcac_mars_pro[] =
1549 {
1550         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1551         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1552         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1553         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1554         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1555         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1556         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1557         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1558         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1559         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1560         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1561         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1562         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1563         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1564         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1565         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1566         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1567         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1568         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1569         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1570         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1571         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1572         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1573         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1574         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1575         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1576         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1577         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1578         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1579         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1580         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1581         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1582         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1583         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1584         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1585         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1586         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1587         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1588         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1589         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1590         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1591         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1592         { 0xFFFFFFFF }
1593 };
1594
1595 static const struct si_cac_config_reg cac_override_oland[] =
1596 {
1597         { 0xFFFFFFFF }
1598 };
1599
1600 static const struct si_powertune_data powertune_data_oland =
1601 {
1602         ((1 << 16) | 0x6993),
1603         5,
1604         0,
1605         7,
1606         105,
1607         {
1608                 0UL,
1609                 0UL,
1610                 7194395UL,
1611                 309631529UL,
1612                 -1270850L,
1613                 4513710L,
1614                 100
1615         },
1616         117830498UL,
1617         12,
1618         {
1619                 0,
1620                 0,
1621                 0,
1622                 0,
1623                 0,
1624                 0,
1625                 0,
1626                 0
1627         },
1628         true
1629 };
1630
1631 static const struct si_powertune_data powertune_data_mars_pro =
1632 {
1633         ((1 << 16) | 0x6993),
1634         5,
1635         0,
1636         7,
1637         105,
1638         {
1639                 0UL,
1640                 0UL,
1641                 7194395UL,
1642                 309631529UL,
1643                 -1270850L,
1644                 4513710L,
1645                 100
1646         },
1647         117830498UL,
1648         12,
1649         {
1650                 0,
1651                 0,
1652                 0,
1653                 0,
1654                 0,
1655                 0,
1656                 0,
1657                 0
1658         },
1659         true
1660 };
1661
1662 static const struct si_dte_data dte_data_oland =
1663 {
1664         { 0, 0, 0, 0, 0 },
1665         { 0, 0, 0, 0, 0 },
1666         0,
1667         0,
1668         0,
1669         0,
1670         0,
1671         0,
1672         0,
1673         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1674         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1675         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1676         0,
1677         false
1678 };
1679
1680 static const struct si_dte_data dte_data_mars_pro =
1681 {
1682         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1683         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1684         5,
1685         55000,
1686         105,
1687         0xA,
1688         1,
1689         0,
1690         0x10,
1691         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1692         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1693         { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1694         90,
1695         true
1696 };
1697
1698 static const struct si_dte_data dte_data_sun_xt =
1699 {
1700         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1701         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1702         5,
1703         55000,
1704         105,
1705         0xA,
1706         1,
1707         0,
1708         0x10,
1709         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1710         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1711         { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1712         90,
1713         true
1714 };
1715
1716
1717 static const struct si_cac_config_reg cac_weights_hainan[] =
1718 {
1719         { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1720         { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1721         { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1722         { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1723         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1724         { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1725         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1726         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1727         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1728         { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1729         { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1730         { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1731         { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1732         { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1733         { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1734         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1735         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1736         { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1737         { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1738         { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1739         { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1740         { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1741         { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1742         { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1743         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1744         { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1745         { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1746         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1747         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1748         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1749         { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1750         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1751         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1752         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1753         { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1754         { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1755         { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1756         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1757         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1758         { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1759         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1760         { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1761         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1762         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1763         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1764         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1765         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1766         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1767         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1768         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1769         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1770         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1771         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1772         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1773         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1774         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1775         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1776         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1777         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1778         { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1779         { 0xFFFFFFFF }
1780 };
1781
1782 static const struct si_powertune_data powertune_data_hainan =
1783 {
1784         ((1 << 16) | 0x6993),
1785         5,
1786         0,
1787         9,
1788         105,
1789         {
1790                 0UL,
1791                 0UL,
1792                 7194395UL,
1793                 309631529UL,
1794                 -1270850L,
1795                 4513710L,
1796                 100
1797         },
1798         117830498UL,
1799         12,
1800         {
1801                 0,
1802                 0,
1803                 0,
1804                 0,
1805                 0,
1806                 0,
1807                 0,
1808                 0
1809         },
1810         true
1811 };
1812
1813 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev);
1814 static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
1815 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
1816 static struct  si_ps *si_get_ps(struct amdgpu_ps *rps);
1817
1818 static int si_populate_voltage_value(struct amdgpu_device *adev,
1819                                      const struct atom_voltage_table *table,
1820                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1821 static int si_get_std_voltage_value(struct amdgpu_device *adev,
1822                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1823                                     u16 *std_voltage);
1824 static int si_write_smc_soft_register(struct amdgpu_device *adev,
1825                                       u16 reg_offset, u32 value);
1826 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
1827                                          struct rv7xx_pl *pl,
1828                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1829 static int si_calculate_sclk_params(struct amdgpu_device *adev,
1830                                     u32 engine_clock,
1831                                     SISLANDS_SMC_SCLK_VALUE *sclk);
1832
1833 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
1834 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
1835 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
1836
1837 static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
1838 {
1839         struct si_power_info *pi = adev->pm.dpm.priv;
1840         return pi;
1841 }
1842
1843 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1844                                                      u16 v, s32 t, u32 ileakage, u32 *leakage)
1845 {
1846         s64 kt, kv, leakage_w, i_leakage, vddc;
1847         s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1848         s64 tmp;
1849
1850         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1851         vddc = div64_s64(drm_int2fixp(v), 1000);
1852         temperature = div64_s64(drm_int2fixp(t), 1000);
1853
1854         t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1855         t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1856         av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1857         bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1858         t_ref = drm_int2fixp(coeff->t_ref);
1859
1860         tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1861         kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1862         kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1863         kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1864
1865         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1866
1867         *leakage = drm_fixp2int(leakage_w * 1000);
1868 }
1869
1870 static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev,
1871                                              const struct ni_leakage_coeffients *coeff,
1872                                              u16 v,
1873                                              s32 t,
1874                                              u32 i_leakage,
1875                                              u32 *leakage)
1876 {
1877         si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1878 }
1879
1880 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1881                                                const u32 fixed_kt, u16 v,
1882                                                u32 ileakage, u32 *leakage)
1883 {
1884         s64 kt, kv, leakage_w, i_leakage, vddc;
1885
1886         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1887         vddc = div64_s64(drm_int2fixp(v), 1000);
1888
1889         kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1890         kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1891                           drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1892
1893         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1894
1895         *leakage = drm_fixp2int(leakage_w * 1000);
1896 }
1897
1898 static void si_calculate_leakage_for_v(struct amdgpu_device *adev,
1899                                        const struct ni_leakage_coeffients *coeff,
1900                                        const u32 fixed_kt,
1901                                        u16 v,
1902                                        u32 i_leakage,
1903                                        u32 *leakage)
1904 {
1905         si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1906 }
1907
1908
1909 static void si_update_dte_from_pl2(struct amdgpu_device *adev,
1910                                    struct si_dte_data *dte_data)
1911 {
1912         u32 p_limit1 = adev->pm.dpm.tdp_limit;
1913         u32 p_limit2 = adev->pm.dpm.near_tdp_limit;
1914         u32 k = dte_data->k;
1915         u32 t_max = dte_data->max_t;
1916         u32 t_split[5] = { 10, 15, 20, 25, 30 };
1917         u32 t_0 = dte_data->t0;
1918         u32 i;
1919
1920         if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1921                 dte_data->tdep_count = 3;
1922
1923                 for (i = 0; i < k; i++) {
1924                         dte_data->r[i] =
1925                                 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1926                                 (p_limit2  * (u32)100);
1927                 }
1928
1929                 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1930
1931                 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1932                         dte_data->tdep_r[i] = dte_data->r[4];
1933                 }
1934         } else {
1935                 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1936         }
1937 }
1938
1939 static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev)
1940 {
1941         struct rv7xx_power_info *pi = adev->pm.dpm.priv;
1942
1943         return pi;
1944 }
1945
1946 static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev)
1947 {
1948         struct ni_power_info *pi = adev->pm.dpm.priv;
1949
1950         return pi;
1951 }
1952
1953 static struct si_ps *si_get_ps(struct amdgpu_ps *aps)
1954 {
1955         struct  si_ps *ps = aps->ps_priv;
1956
1957         return ps;
1958 }
1959
1960 static void si_initialize_powertune_defaults(struct amdgpu_device *adev)
1961 {
1962         struct ni_power_info *ni_pi = ni_get_pi(adev);
1963         struct si_power_info *si_pi = si_get_pi(adev);
1964         bool update_dte_from_pl2 = false;
1965
1966         if (adev->asic_type == CHIP_TAHITI) {
1967                 si_pi->cac_weights = cac_weights_tahiti;
1968                 si_pi->lcac_config = lcac_tahiti;
1969                 si_pi->cac_override = cac_override_tahiti;
1970                 si_pi->powertune_data = &powertune_data_tahiti;
1971                 si_pi->dte_data = dte_data_tahiti;
1972
1973                 switch (adev->pdev->device) {
1974                 case 0x6798:
1975                         si_pi->dte_data.enable_dte_by_default = true;
1976                         break;
1977                 case 0x6799:
1978                         si_pi->dte_data = dte_data_new_zealand;
1979                         break;
1980                 case 0x6790:
1981                 case 0x6791:
1982                 case 0x6792:
1983                 case 0x679E:
1984                         si_pi->dte_data = dte_data_aruba_pro;
1985                         update_dte_from_pl2 = true;
1986                         break;
1987                 case 0x679B:
1988                         si_pi->dte_data = dte_data_malta;
1989                         update_dte_from_pl2 = true;
1990                         break;
1991                 case 0x679A:
1992                         si_pi->dte_data = dte_data_tahiti_pro;
1993                         update_dte_from_pl2 = true;
1994                         break;
1995                 default:
1996                         if (si_pi->dte_data.enable_dte_by_default == true)
1997                                 DRM_ERROR("DTE is not enabled!\n");
1998                         break;
1999                 }
2000         } else if (adev->asic_type == CHIP_PITCAIRN) {
2001                 si_pi->cac_weights = cac_weights_pitcairn;
2002                 si_pi->lcac_config = lcac_pitcairn;
2003                 si_pi->cac_override = cac_override_pitcairn;
2004                 si_pi->powertune_data = &powertune_data_pitcairn;
2005
2006                 switch (adev->pdev->device) {
2007                 case 0x6810:
2008                 case 0x6818:
2009                         si_pi->dte_data = dte_data_curacao_xt;
2010                         update_dte_from_pl2 = true;
2011                         break;
2012                 case 0x6819:
2013                 case 0x6811:
2014                         si_pi->dte_data = dte_data_curacao_pro;
2015                         update_dte_from_pl2 = true;
2016                         break;
2017                 case 0x6800:
2018                 case 0x6806:
2019                         si_pi->dte_data = dte_data_neptune_xt;
2020                         update_dte_from_pl2 = true;
2021                         break;
2022                 default:
2023                         si_pi->dte_data = dte_data_pitcairn;
2024                         break;
2025                 }
2026         } else if (adev->asic_type == CHIP_VERDE) {
2027                 si_pi->lcac_config = lcac_cape_verde;
2028                 si_pi->cac_override = cac_override_cape_verde;
2029                 si_pi->powertune_data = &powertune_data_cape_verde;
2030
2031                 switch (adev->pdev->device) {
2032                 case 0x683B:
2033                 case 0x683F:
2034                 case 0x6829:
2035                 case 0x6835:
2036                         si_pi->cac_weights = cac_weights_cape_verde_pro;
2037                         si_pi->dte_data = dte_data_cape_verde;
2038                         break;
2039                 case 0x682C:
2040                         si_pi->cac_weights = cac_weights_cape_verde_pro;
2041                         si_pi->dte_data = dte_data_sun_xt;
2042                         update_dte_from_pl2 = true;
2043                         break;
2044                 case 0x6825:
2045                 case 0x6827:
2046                         si_pi->cac_weights = cac_weights_heathrow;
2047                         si_pi->dte_data = dte_data_cape_verde;
2048                         break;
2049                 case 0x6824:
2050                 case 0x682D:
2051                         si_pi->cac_weights = cac_weights_chelsea_xt;
2052                         si_pi->dte_data = dte_data_cape_verde;
2053                         break;
2054                 case 0x682F:
2055                         si_pi->cac_weights = cac_weights_chelsea_pro;
2056                         si_pi->dte_data = dte_data_cape_verde;
2057                         break;
2058                 case 0x6820:
2059                         si_pi->cac_weights = cac_weights_heathrow;
2060                         si_pi->dte_data = dte_data_venus_xtx;
2061                         break;
2062                 case 0x6821:
2063                         si_pi->cac_weights = cac_weights_heathrow;
2064                         si_pi->dte_data = dte_data_venus_xt;
2065                         break;
2066                 case 0x6823:
2067                 case 0x682B:
2068                 case 0x6822:
2069                 case 0x682A:
2070                         si_pi->cac_weights = cac_weights_chelsea_pro;
2071                         si_pi->dte_data = dte_data_venus_pro;
2072                         break;
2073                 default:
2074                         si_pi->cac_weights = cac_weights_cape_verde;
2075                         si_pi->dte_data = dte_data_cape_verde;
2076                         break;
2077                 }
2078         } else if (adev->asic_type == CHIP_OLAND) {
2079                 si_pi->lcac_config = lcac_mars_pro;
2080                 si_pi->cac_override = cac_override_oland;
2081                 si_pi->powertune_data = &powertune_data_mars_pro;
2082                 si_pi->dte_data = dte_data_mars_pro;
2083
2084                 switch (adev->pdev->device) {
2085                 case 0x6601:
2086                 case 0x6621:
2087                 case 0x6603:
2088                 case 0x6605:
2089                         si_pi->cac_weights = cac_weights_mars_pro;
2090                         update_dte_from_pl2 = true;
2091                         break;
2092                 case 0x6600:
2093                 case 0x6606:
2094                 case 0x6620:
2095                 case 0x6604:
2096                         si_pi->cac_weights = cac_weights_mars_xt;
2097                         update_dte_from_pl2 = true;
2098                         break;
2099                 case 0x6611:
2100                 case 0x6613:
2101                 case 0x6608:
2102                         si_pi->cac_weights = cac_weights_oland_pro;
2103                         update_dte_from_pl2 = true;
2104                         break;
2105                 case 0x6610:
2106                         si_pi->cac_weights = cac_weights_oland_xt;
2107                         update_dte_from_pl2 = true;
2108                         break;
2109                 default:
2110                         si_pi->cac_weights = cac_weights_oland;
2111                         si_pi->lcac_config = lcac_oland;
2112                         si_pi->cac_override = cac_override_oland;
2113                         si_pi->powertune_data = &powertune_data_oland;
2114                         si_pi->dte_data = dte_data_oland;
2115                         break;
2116                 }
2117         } else if (adev->asic_type == CHIP_HAINAN) {
2118                 si_pi->cac_weights = cac_weights_hainan;
2119                 si_pi->lcac_config = lcac_oland;
2120                 si_pi->cac_override = cac_override_oland;
2121                 si_pi->powertune_data = &powertune_data_hainan;
2122                 si_pi->dte_data = dte_data_sun_xt;
2123                 update_dte_from_pl2 = true;
2124         } else {
2125                 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2126                 return;
2127         }
2128
2129         ni_pi->enable_power_containment = false;
2130         ni_pi->enable_cac = false;
2131         ni_pi->enable_sq_ramping = false;
2132         si_pi->enable_dte = false;
2133
2134         if (si_pi->powertune_data->enable_powertune_by_default) {
2135                 ni_pi->enable_power_containment = true;
2136                 ni_pi->enable_cac = true;
2137                 if (si_pi->dte_data.enable_dte_by_default) {
2138                         si_pi->enable_dte = true;
2139                         if (update_dte_from_pl2)
2140                                 si_update_dte_from_pl2(adev, &si_pi->dte_data);
2141
2142                 }
2143                 ni_pi->enable_sq_ramping = true;
2144         }
2145
2146         ni_pi->driver_calculate_cac_leakage = true;
2147         ni_pi->cac_configuration_required = true;
2148
2149         if (ni_pi->cac_configuration_required) {
2150                 ni_pi->support_cac_long_term_average = true;
2151                 si_pi->dyn_powertune_data.l2_lta_window_size =
2152                         si_pi->powertune_data->l2_lta_window_size_default;
2153                 si_pi->dyn_powertune_data.lts_truncate =
2154                         si_pi->powertune_data->lts_truncate_default;
2155         } else {
2156                 ni_pi->support_cac_long_term_average = false;
2157                 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2158                 si_pi->dyn_powertune_data.lts_truncate = 0;
2159         }
2160
2161         si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2162 }
2163
2164 static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev)
2165 {
2166         return 1;
2167 }
2168
2169 static u32 si_calculate_cac_wintime(struct amdgpu_device *adev)
2170 {
2171         u32 xclk;
2172         u32 wintime;
2173         u32 cac_window;
2174         u32 cac_window_size;
2175
2176         xclk = amdgpu_asic_get_xclk(adev);
2177
2178         if (xclk == 0)
2179                 return 0;
2180
2181         cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2182         cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2183
2184         wintime = (cac_window_size * 100) / xclk;
2185
2186         return wintime;
2187 }
2188
2189 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2190 {
2191         return power_in_watts;
2192 }
2193
2194 static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev,
2195                                             bool adjust_polarity,
2196                                             u32 tdp_adjustment,
2197                                             u32 *tdp_limit,
2198                                             u32 *near_tdp_limit)
2199 {
2200         u32 adjustment_delta, max_tdp_limit;
2201
2202         if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)
2203                 return -EINVAL;
2204
2205         max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100;
2206
2207         if (adjust_polarity) {
2208                 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2209                 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit);
2210         } else {
2211                 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2212                 adjustment_delta  = adev->pm.dpm.tdp_limit - *tdp_limit;
2213                 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted)
2214                         *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2215                 else
2216                         *near_tdp_limit = 0;
2217         }
2218
2219         if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2220                 return -EINVAL;
2221         if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2222                 return -EINVAL;
2223
2224         return 0;
2225 }
2226
2227 static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
2228                                       struct amdgpu_ps *amdgpu_state)
2229 {
2230         struct ni_power_info *ni_pi = ni_get_pi(adev);
2231         struct si_power_info *si_pi = si_get_pi(adev);
2232
2233         if (ni_pi->enable_power_containment) {
2234                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2235                 PP_SIslands_PAPMParameters *papm_parm;
2236                 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
2237                 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2238                 u32 tdp_limit;
2239                 u32 near_tdp_limit;
2240                 int ret;
2241
2242                 if (scaling_factor == 0)
2243                         return -EINVAL;
2244
2245                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2246
2247                 ret = si_calculate_adjusted_tdp_limits(adev,
2248                                                        false, /* ??? */
2249                                                        adev->pm.dpm.tdp_adjustment,
2250                                                        &tdp_limit,
2251                                                        &near_tdp_limit);
2252                 if (ret)
2253                         return ret;
2254
2255                 smc_table->dpm2Params.TDPLimit =
2256                         cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2257                 smc_table->dpm2Params.NearTDPLimit =
2258                         cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2259                 smc_table->dpm2Params.SafePowerLimit =
2260                         cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2261
2262                 ret = amdgpu_si_copy_bytes_to_smc(adev,
2263                                                   (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2264                                                    offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2265                                                   (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2266                                                   sizeof(u32) * 3,
2267                                                   si_pi->sram_end);
2268                 if (ret)
2269                         return ret;
2270
2271                 if (si_pi->enable_ppm) {
2272                         papm_parm = &si_pi->papm_parm;
2273                         memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2274                         papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2275                         papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2276                         papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2277                         papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2278                         papm_parm->PlatformPowerLimit = 0xffffffff;
2279                         papm_parm->NearTDPLimitPAPM = 0xffffffff;
2280
2281                         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
2282                                                           (u8 *)papm_parm,
2283                                                           sizeof(PP_SIslands_PAPMParameters),
2284                                                           si_pi->sram_end);
2285                         if (ret)
2286                                 return ret;
2287                 }
2288         }
2289         return 0;
2290 }
2291
2292 static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev,
2293                                         struct amdgpu_ps *amdgpu_state)
2294 {
2295         struct ni_power_info *ni_pi = ni_get_pi(adev);
2296         struct si_power_info *si_pi = si_get_pi(adev);
2297
2298         if (ni_pi->enable_power_containment) {
2299                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2300                 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2301                 int ret;
2302
2303                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2304
2305                 smc_table->dpm2Params.NearTDPLimit =
2306                         cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2307                 smc_table->dpm2Params.SafePowerLimit =
2308                         cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2309
2310                 ret = amdgpu_si_copy_bytes_to_smc(adev,
2311                                                   (si_pi->state_table_start +
2312                                                    offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2313                                                    offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2314                                                   (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2315                                                   sizeof(u32) * 2,
2316                                                   si_pi->sram_end);
2317                 if (ret)
2318                         return ret;
2319         }
2320
2321         return 0;
2322 }
2323
2324 static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev,
2325                                                const u16 prev_std_vddc,
2326                                                const u16 curr_std_vddc)
2327 {
2328         u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2329         u64 prev_vddc = (u64)prev_std_vddc;
2330         u64 curr_vddc = (u64)curr_std_vddc;
2331         u64 pwr_efficiency_ratio, n, d;
2332
2333         if ((prev_vddc == 0) || (curr_vddc == 0))
2334                 return 0;
2335
2336         n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2337         d = prev_vddc * prev_vddc;
2338         pwr_efficiency_ratio = div64_u64(n, d);
2339
2340         if (pwr_efficiency_ratio > (u64)0xFFFF)
2341                 return 0;
2342
2343         return (u16)pwr_efficiency_ratio;
2344 }
2345
2346 static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev,
2347                                             struct amdgpu_ps *amdgpu_state)
2348 {
2349         struct si_power_info *si_pi = si_get_pi(adev);
2350
2351         if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2352             amdgpu_state->vclk && amdgpu_state->dclk)
2353                 return true;
2354
2355         return false;
2356 }
2357
2358 struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev)
2359 {
2360         struct evergreen_power_info *pi = adev->pm.dpm.priv;
2361
2362         return pi;
2363 }
2364
2365 static int si_populate_power_containment_values(struct amdgpu_device *adev,
2366                                                 struct amdgpu_ps *amdgpu_state,
2367                                                 SISLANDS_SMC_SWSTATE *smc_state)
2368 {
2369         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
2370         struct ni_power_info *ni_pi = ni_get_pi(adev);
2371         struct  si_ps *state = si_get_ps(amdgpu_state);
2372         SISLANDS_SMC_VOLTAGE_VALUE vddc;
2373         u32 prev_sclk;
2374         u32 max_sclk;
2375         u32 min_sclk;
2376         u16 prev_std_vddc;
2377         u16 curr_std_vddc;
2378         int i;
2379         u16 pwr_efficiency_ratio;
2380         u8 max_ps_percent;
2381         bool disable_uvd_power_tune;
2382         int ret;
2383
2384         if (ni_pi->enable_power_containment == false)
2385                 return 0;
2386
2387         if (state->performance_level_count == 0)
2388                 return -EINVAL;
2389
2390         if (smc_state->levelCount != state->performance_level_count)
2391                 return -EINVAL;
2392
2393         disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state);
2394
2395         smc_state->levels[0].dpm2.MaxPS = 0;
2396         smc_state->levels[0].dpm2.NearTDPDec = 0;
2397         smc_state->levels[0].dpm2.AboveSafeInc = 0;
2398         smc_state->levels[0].dpm2.BelowSafeInc = 0;
2399         smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2400
2401         for (i = 1; i < state->performance_level_count; i++) {
2402                 prev_sclk = state->performance_levels[i-1].sclk;
2403                 max_sclk  = state->performance_levels[i].sclk;
2404                 if (i == 1)
2405                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2406                 else
2407                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2408
2409                 if (prev_sclk > max_sclk)
2410                         return -EINVAL;
2411
2412                 if ((max_ps_percent == 0) ||
2413                     (prev_sclk == max_sclk) ||
2414                     disable_uvd_power_tune)
2415                         min_sclk = max_sclk;
2416                 else if (i == 1)
2417                         min_sclk = prev_sclk;
2418                 else
2419                         min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2420
2421                 if (min_sclk < state->performance_levels[0].sclk)
2422                         min_sclk = state->performance_levels[0].sclk;
2423
2424                 if (min_sclk == 0)
2425                         return -EINVAL;
2426
2427                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2428                                                 state->performance_levels[i-1].vddc, &vddc);
2429                 if (ret)
2430                         return ret;
2431
2432                 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc);
2433                 if (ret)
2434                         return ret;
2435
2436                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2437                                                 state->performance_levels[i].vddc, &vddc);
2438                 if (ret)
2439                         return ret;
2440
2441                 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc);
2442                 if (ret)
2443                         return ret;
2444
2445                 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev,
2446                                                                            prev_std_vddc, curr_std_vddc);
2447
2448                 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2449                 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2450                 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2451                 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2452                 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2453         }
2454
2455         return 0;
2456 }
2457
2458 static int si_populate_sq_ramping_values(struct amdgpu_device *adev,
2459                                          struct amdgpu_ps *amdgpu_state,
2460                                          SISLANDS_SMC_SWSTATE *smc_state)
2461 {
2462         struct ni_power_info *ni_pi = ni_get_pi(adev);
2463         struct  si_ps *state = si_get_ps(amdgpu_state);
2464         u32 sq_power_throttle, sq_power_throttle2;
2465         bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2466         int i;
2467
2468         if (state->performance_level_count == 0)
2469                 return -EINVAL;
2470
2471         if (smc_state->levelCount != state->performance_level_count)
2472                 return -EINVAL;
2473
2474         if (adev->pm.dpm.sq_ramping_threshold == 0)
2475                 return -EINVAL;
2476
2477         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2478                 enable_sq_ramping = false;
2479
2480         if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2481                 enable_sq_ramping = false;
2482
2483         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2484                 enable_sq_ramping = false;
2485
2486         if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2487                 enable_sq_ramping = false;
2488
2489         if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2490                 enable_sq_ramping = false;
2491
2492         for (i = 0; i < state->performance_level_count; i++) {
2493                 sq_power_throttle = 0;
2494                 sq_power_throttle2 = 0;
2495
2496                 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) &&
2497                     enable_sq_ramping) {
2498                         sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2499                         sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2500                         sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2501                         sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2502                         sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2503                 } else {
2504                         sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2505                         sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2506                 }
2507
2508                 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2509                 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2510         }
2511
2512         return 0;
2513 }
2514
2515 static int si_enable_power_containment(struct amdgpu_device *adev,
2516                                        struct amdgpu_ps *amdgpu_new_state,
2517                                        bool enable)
2518 {
2519         struct ni_power_info *ni_pi = ni_get_pi(adev);
2520         PPSMC_Result smc_result;
2521         int ret = 0;
2522
2523         if (ni_pi->enable_power_containment) {
2524                 if (enable) {
2525                         if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2526                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
2527                                 if (smc_result != PPSMC_Result_OK) {
2528                                         ret = -EINVAL;
2529                                         ni_pi->pc_enabled = false;
2530                                 } else {
2531                                         ni_pi->pc_enabled = true;
2532                                 }
2533                         }
2534                 } else {
2535                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
2536                         if (smc_result != PPSMC_Result_OK)
2537                                 ret = -EINVAL;
2538                         ni_pi->pc_enabled = false;
2539                 }
2540         }
2541
2542         return ret;
2543 }
2544
2545 static int si_initialize_smc_dte_tables(struct amdgpu_device *adev)
2546 {
2547         struct si_power_info *si_pi = si_get_pi(adev);
2548         int ret = 0;
2549         struct si_dte_data *dte_data = &si_pi->dte_data;
2550         Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2551         u32 table_size;
2552         u8 tdep_count;
2553         u32 i;
2554
2555         if (dte_data == NULL)
2556                 si_pi->enable_dte = false;
2557
2558         if (si_pi->enable_dte == false)
2559                 return 0;
2560
2561         if (dte_data->k <= 0)
2562                 return -EINVAL;
2563
2564         dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2565         if (dte_tables == NULL) {
2566                 si_pi->enable_dte = false;
2567                 return -ENOMEM;
2568         }
2569
2570         table_size = dte_data->k;
2571
2572         if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2573                 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2574
2575         tdep_count = dte_data->tdep_count;
2576         if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2577                 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2578
2579         dte_tables->K = cpu_to_be32(table_size);
2580         dte_tables->T0 = cpu_to_be32(dte_data->t0);
2581         dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2582         dte_tables->WindowSize = dte_data->window_size;
2583         dte_tables->temp_select = dte_data->temp_select;
2584         dte_tables->DTE_mode = dte_data->dte_mode;
2585         dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2586
2587         if (tdep_count > 0)
2588                 table_size--;
2589
2590         for (i = 0; i < table_size; i++) {
2591                 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2592                 dte_tables->R[i]   = cpu_to_be32(dte_data->r[i]);
2593         }
2594
2595         dte_tables->Tdep_count = tdep_count;
2596
2597         for (i = 0; i < (u32)tdep_count; i++) {
2598                 dte_tables->T_limits[i] = dte_data->t_limits[i];
2599                 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2600                 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2601         }
2602
2603         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start,
2604                                           (u8 *)dte_tables,
2605                                           sizeof(Smc_SIslands_DTE_Configuration),
2606                                           si_pi->sram_end);
2607         kfree(dte_tables);
2608
2609         return ret;
2610 }
2611
2612 static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev,
2613                                           u16 *max, u16 *min)
2614 {
2615         struct si_power_info *si_pi = si_get_pi(adev);
2616         struct amdgpu_cac_leakage_table *table =
2617                 &adev->pm.dpm.dyn_state.cac_leakage_table;
2618         u32 i;
2619         u32 v0_loadline;
2620
2621         if (table == NULL)
2622                 return -EINVAL;
2623
2624         *max = 0;
2625         *min = 0xFFFF;
2626
2627         for (i = 0; i < table->count; i++) {
2628                 if (table->entries[i].vddc > *max)
2629                         *max = table->entries[i].vddc;
2630                 if (table->entries[i].vddc < *min)
2631                         *min = table->entries[i].vddc;
2632         }
2633
2634         if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2635                 return -EINVAL;
2636
2637         v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2638
2639         if (v0_loadline > 0xFFFFUL)
2640                 return -EINVAL;
2641
2642         *min = (u16)v0_loadline;
2643
2644         if ((*min > *max) || (*max == 0) || (*min == 0))
2645                 return -EINVAL;
2646
2647         return 0;
2648 }
2649
2650 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2651 {
2652         return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2653                 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2654 }
2655
2656 static int si_init_dte_leakage_table(struct amdgpu_device *adev,
2657                                      PP_SIslands_CacConfig *cac_tables,
2658                                      u16 vddc_max, u16 vddc_min, u16 vddc_step,
2659                                      u16 t0, u16 t_step)
2660 {
2661         struct si_power_info *si_pi = si_get_pi(adev);
2662         u32 leakage;
2663         unsigned int i, j;
2664         s32 t;
2665         u32 smc_leakage;
2666         u32 scaling_factor;
2667         u16 voltage;
2668
2669         scaling_factor = si_get_smc_power_scaling_factor(adev);
2670
2671         for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2672                 t = (1000 * (i * t_step + t0));
2673
2674                 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2675                         voltage = vddc_max - (vddc_step * j);
2676
2677                         si_calculate_leakage_for_v_and_t(adev,
2678                                                          &si_pi->powertune_data->leakage_coefficients,
2679                                                          voltage,
2680                                                          t,
2681                                                          si_pi->dyn_powertune_data.cac_leakage,
2682                                                          &leakage);
2683
2684                         smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2685
2686                         if (smc_leakage > 0xFFFF)
2687                                 smc_leakage = 0xFFFF;
2688
2689                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2690                                 cpu_to_be16((u16)smc_leakage);
2691                 }
2692         }
2693         return 0;
2694 }
2695
2696 static int si_init_simplified_leakage_table(struct amdgpu_device *adev,
2697                                             PP_SIslands_CacConfig *cac_tables,
2698                                             u16 vddc_max, u16 vddc_min, u16 vddc_step)
2699 {
2700         struct si_power_info *si_pi = si_get_pi(adev);
2701         u32 leakage;
2702         unsigned int i, j;
2703         u32 smc_leakage;
2704         u32 scaling_factor;
2705         u16 voltage;
2706
2707         scaling_factor = si_get_smc_power_scaling_factor(adev);
2708
2709         for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2710                 voltage = vddc_max - (vddc_step * j);
2711
2712                 si_calculate_leakage_for_v(adev,
2713                                            &si_pi->powertune_data->leakage_coefficients,
2714                                            si_pi->powertune_data->fixed_kt,
2715                                            voltage,
2716                                            si_pi->dyn_powertune_data.cac_leakage,
2717                                            &leakage);
2718
2719                 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2720
2721                 if (smc_leakage > 0xFFFF)
2722                         smc_leakage = 0xFFFF;
2723
2724                 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2725                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2726                                 cpu_to_be16((u16)smc_leakage);
2727         }
2728         return 0;
2729 }
2730
2731 static int si_initialize_smc_cac_tables(struct amdgpu_device *adev)
2732 {
2733         struct ni_power_info *ni_pi = ni_get_pi(adev);
2734         struct si_power_info *si_pi = si_get_pi(adev);
2735         PP_SIslands_CacConfig *cac_tables = NULL;
2736         u16 vddc_max, vddc_min, vddc_step;
2737         u16 t0, t_step;
2738         u32 load_line_slope, reg;
2739         int ret = 0;
2740         u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100;
2741
2742         if (ni_pi->enable_cac == false)
2743                 return 0;
2744
2745         cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2746         if (!cac_tables)
2747                 return -ENOMEM;
2748
2749         reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2750         reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2751         WREG32(CG_CAC_CTRL, reg);
2752
2753         si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage;
2754         si_pi->dyn_powertune_data.dc_pwr_value =
2755                 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2756         si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev);
2757         si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2758
2759         si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2760
2761         ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min);
2762         if (ret)
2763                 goto done_free;
2764
2765         vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2766         vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2767         t_step = 4;
2768         t0 = 60;
2769
2770         if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2771                 ret = si_init_dte_leakage_table(adev, cac_tables,
2772                                                 vddc_max, vddc_min, vddc_step,
2773                                                 t0, t_step);
2774         else
2775                 ret = si_init_simplified_leakage_table(adev, cac_tables,
2776                                                        vddc_max, vddc_min, vddc_step);
2777         if (ret)
2778                 goto done_free;
2779
2780         load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2781
2782         cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2783         cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2784         cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2785         cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2786         cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2787         cac_tables->R_LL = cpu_to_be32(load_line_slope);
2788         cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2789         cac_tables->calculation_repeats = cpu_to_be32(2);
2790         cac_tables->dc_cac = cpu_to_be32(0);
2791         cac_tables->log2_PG_LKG_SCALE = 12;
2792         cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2793         cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2794         cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2795
2796         ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start,
2797                                           (u8 *)cac_tables,
2798                                           sizeof(PP_SIslands_CacConfig),
2799                                           si_pi->sram_end);
2800
2801         if (ret)
2802                 goto done_free;
2803
2804         ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2805
2806 done_free:
2807         if (ret) {
2808                 ni_pi->enable_cac = false;
2809                 ni_pi->enable_power_containment = false;
2810         }
2811
2812         kfree(cac_tables);
2813
2814         return ret;
2815 }
2816
2817 static int si_program_cac_config_registers(struct amdgpu_device *adev,
2818                                            const struct si_cac_config_reg *cac_config_regs)
2819 {
2820         const struct si_cac_config_reg *config_regs = cac_config_regs;
2821         u32 data = 0, offset;
2822
2823         if (!config_regs)
2824                 return -EINVAL;
2825
2826         while (config_regs->offset != 0xFFFFFFFF) {
2827                 switch (config_regs->type) {
2828                 case SISLANDS_CACCONFIG_CGIND:
2829                         offset = SMC_CG_IND_START + config_regs->offset;
2830                         if (offset < SMC_CG_IND_END)
2831                                 data = RREG32_SMC(offset);
2832                         break;
2833                 default:
2834                         data = RREG32(config_regs->offset);
2835                         break;
2836                 }
2837
2838                 data &= ~config_regs->mask;
2839                 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2840
2841                 switch (config_regs->type) {
2842                 case SISLANDS_CACCONFIG_CGIND:
2843                         offset = SMC_CG_IND_START + config_regs->offset;
2844                         if (offset < SMC_CG_IND_END)
2845                                 WREG32_SMC(offset, data);
2846                         break;
2847                 default:
2848                         WREG32(config_regs->offset, data);
2849                         break;
2850                 }
2851                 config_regs++;
2852         }
2853         return 0;
2854 }
2855
2856 static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev)
2857 {
2858         struct ni_power_info *ni_pi = ni_get_pi(adev);
2859         struct si_power_info *si_pi = si_get_pi(adev);
2860         int ret;
2861
2862         if ((ni_pi->enable_cac == false) ||
2863             (ni_pi->cac_configuration_required == false))
2864                 return 0;
2865
2866         ret = si_program_cac_config_registers(adev, si_pi->lcac_config);
2867         if (ret)
2868                 return ret;
2869         ret = si_program_cac_config_registers(adev, si_pi->cac_override);
2870         if (ret)
2871                 return ret;
2872         ret = si_program_cac_config_registers(adev, si_pi->cac_weights);
2873         if (ret)
2874                 return ret;
2875
2876         return 0;
2877 }
2878
2879 static int si_enable_smc_cac(struct amdgpu_device *adev,
2880                              struct amdgpu_ps *amdgpu_new_state,
2881                              bool enable)
2882 {
2883         struct ni_power_info *ni_pi = ni_get_pi(adev);
2884         struct si_power_info *si_pi = si_get_pi(adev);
2885         PPSMC_Result smc_result;
2886         int ret = 0;
2887
2888         if (ni_pi->enable_cac) {
2889                 if (enable) {
2890                         if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2891                                 if (ni_pi->support_cac_long_term_average) {
2892                                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
2893                                         if (smc_result != PPSMC_Result_OK)
2894                                                 ni_pi->support_cac_long_term_average = false;
2895                                 }
2896
2897                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
2898                                 if (smc_result != PPSMC_Result_OK) {
2899                                         ret = -EINVAL;
2900                                         ni_pi->cac_enabled = false;
2901                                 } else {
2902                                         ni_pi->cac_enabled = true;
2903                                 }
2904
2905                                 if (si_pi->enable_dte) {
2906                                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
2907                                         if (smc_result != PPSMC_Result_OK)
2908                                                 ret = -EINVAL;
2909                                 }
2910                         }
2911                 } else if (ni_pi->cac_enabled) {
2912                         if (si_pi->enable_dte)
2913                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
2914
2915                         smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
2916
2917                         ni_pi->cac_enabled = false;
2918
2919                         if (ni_pi->support_cac_long_term_average)
2920                                 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
2921                 }
2922         }
2923         return ret;
2924 }
2925
2926 static int si_init_smc_spll_table(struct amdgpu_device *adev)
2927 {
2928         struct ni_power_info *ni_pi = ni_get_pi(adev);
2929         struct si_power_info *si_pi = si_get_pi(adev);
2930         SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2931         SISLANDS_SMC_SCLK_VALUE sclk_params;
2932         u32 fb_div, p_div;
2933         u32 clk_s, clk_v;
2934         u32 sclk = 0;
2935         int ret = 0;
2936         u32 tmp;
2937         int i;
2938
2939         if (si_pi->spll_table_start == 0)
2940                 return -EINVAL;
2941
2942         spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2943         if (spll_table == NULL)
2944                 return -ENOMEM;
2945
2946         for (i = 0; i < 256; i++) {
2947                 ret = si_calculate_sclk_params(adev, sclk, &sclk_params);
2948                 if (ret)
2949                         break;
2950                 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2951                 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2952                 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2953                 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2954
2955                 fb_div &= ~0x00001FFF;
2956                 fb_div >>= 1;
2957                 clk_v >>= 6;
2958
2959                 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2960                         ret = -EINVAL;
2961                 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2962                         ret = -EINVAL;
2963                 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2964                         ret = -EINVAL;
2965                 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2966                         ret = -EINVAL;
2967
2968                 if (ret)
2969                         break;
2970
2971                 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2972                         ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2973                 spll_table->freq[i] = cpu_to_be32(tmp);
2974
2975                 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2976                         ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2977                 spll_table->ss[i] = cpu_to_be32(tmp);
2978
2979                 sclk += 512;
2980         }
2981
2982
2983         if (!ret)
2984                 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start,
2985                                                   (u8 *)spll_table,
2986                                                   sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2987                                                   si_pi->sram_end);
2988
2989         if (ret)
2990                 ni_pi->enable_power_containment = false;
2991
2992         kfree(spll_table);
2993
2994         return ret;
2995 }
2996
2997 static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev,
2998                                                    u16 vce_voltage)
2999 {
3000         u16 highest_leakage = 0;
3001         struct si_power_info *si_pi = si_get_pi(adev);
3002         int i;
3003
3004         for (i = 0; i < si_pi->leakage_voltage.count; i++){
3005                 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
3006                         highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
3007         }
3008
3009         if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
3010                 return highest_leakage;
3011
3012         return vce_voltage;
3013 }
3014
3015 static int si_get_vce_clock_voltage(struct amdgpu_device *adev,
3016                                     u32 evclk, u32 ecclk, u16 *voltage)
3017 {
3018         u32 i;
3019         int ret = -EINVAL;
3020         struct amdgpu_vce_clock_voltage_dependency_table *table =
3021                 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3022
3023         if (((evclk == 0) && (ecclk == 0)) ||
3024             (table && (table->count == 0))) {
3025                 *voltage = 0;
3026                 return 0;
3027         }
3028
3029         for (i = 0; i < table->count; i++) {
3030                 if ((evclk <= table->entries[i].evclk) &&
3031                     (ecclk <= table->entries[i].ecclk)) {
3032                         *voltage = table->entries[i].v;
3033                         ret = 0;
3034                         break;
3035                 }
3036         }
3037
3038         /* if no match return the highest voltage */
3039         if (ret)
3040                 *voltage = table->entries[table->count - 1].v;
3041
3042         *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage);
3043
3044         return ret;
3045 }
3046
3047 static bool si_dpm_vblank_too_short(void *handle)
3048 {
3049         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3050         u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
3051         /* we never hit the non-gddr5 limit so disable it */
3052         u32 switch_limit = adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
3053
3054         if (vblank_time < switch_limit)
3055                 return true;
3056         else
3057                 return false;
3058
3059 }
3060
3061 static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev,
3062                                 u32 arb_freq_src, u32 arb_freq_dest)
3063 {
3064         u32 mc_arb_dram_timing;
3065         u32 mc_arb_dram_timing2;
3066         u32 burst_time;
3067         u32 mc_cg_config;
3068
3069         switch (arb_freq_src) {
3070         case MC_CG_ARB_FREQ_F0:
3071                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
3072                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
3073                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
3074                 break;
3075         case MC_CG_ARB_FREQ_F1:
3076                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_1);
3077                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
3078                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
3079                 break;
3080         case MC_CG_ARB_FREQ_F2:
3081                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_2);
3082                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
3083                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
3084                 break;
3085         case MC_CG_ARB_FREQ_F3:
3086                 mc_arb_dram_timing  = RREG32(MC_ARB_DRAM_TIMING_3);
3087                 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
3088                 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
3089                 break;
3090         default:
3091                 return -EINVAL;
3092         }
3093
3094         switch (arb_freq_dest) {
3095         case MC_CG_ARB_FREQ_F0:
3096                 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
3097                 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
3098                 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
3099                 break;
3100         case MC_CG_ARB_FREQ_F1:
3101                 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
3102                 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
3103                 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
3104                 break;
3105         case MC_CG_ARB_FREQ_F2:
3106                 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
3107                 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
3108                 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
3109                 break;
3110         case MC_CG_ARB_FREQ_F3:
3111                 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
3112                 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
3113                 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
3114                 break;
3115         default:
3116                 return -EINVAL;
3117         }
3118
3119         mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
3120         WREG32(MC_CG_CONFIG, mc_cg_config);
3121         WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
3122
3123         return 0;
3124 }
3125
3126 static void ni_update_current_ps(struct amdgpu_device *adev,
3127                           struct amdgpu_ps *rps)
3128 {
3129         struct si_ps *new_ps = si_get_ps(rps);
3130         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3131         struct ni_power_info *ni_pi = ni_get_pi(adev);
3132
3133         eg_pi->current_rps = *rps;
3134         ni_pi->current_ps = *new_ps;
3135         eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
3136         adev->pm.dpm.current_ps = &eg_pi->current_rps;
3137 }
3138
3139 static void ni_update_requested_ps(struct amdgpu_device *adev,
3140                             struct amdgpu_ps *rps)
3141 {
3142         struct si_ps *new_ps = si_get_ps(rps);
3143         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3144         struct ni_power_info *ni_pi = ni_get_pi(adev);
3145
3146         eg_pi->requested_rps = *rps;
3147         ni_pi->requested_ps = *new_ps;
3148         eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
3149         adev->pm.dpm.requested_ps = &eg_pi->requested_rps;
3150 }
3151
3152 static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev,
3153                                            struct amdgpu_ps *new_ps,
3154                                            struct amdgpu_ps *old_ps)
3155 {
3156         struct si_ps *new_state = si_get_ps(new_ps);
3157         struct si_ps *current_state = si_get_ps(old_ps);
3158
3159         if ((new_ps->vclk == old_ps->vclk) &&
3160             (new_ps->dclk == old_ps->dclk))
3161                 return;
3162
3163         if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3164             current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3165                 return;
3166
3167         amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3168 }
3169
3170 static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev,
3171                                           struct amdgpu_ps *new_ps,
3172                                           struct amdgpu_ps *old_ps)
3173 {
3174         struct si_ps *new_state = si_get_ps(new_ps);
3175         struct si_ps *current_state = si_get_ps(old_ps);
3176
3177         if ((new_ps->vclk == old_ps->vclk) &&
3178             (new_ps->dclk == old_ps->dclk))
3179                 return;
3180
3181         if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3182             current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3183                 return;
3184
3185         amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3186 }
3187
3188 static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)
3189 {
3190         unsigned int i;
3191
3192         for (i = 0; i < table->count; i++)
3193                 if (voltage <= table->entries[i].value)
3194                         return table->entries[i].value;
3195
3196         return table->entries[table->count - 1].value;
3197 }
3198
3199 static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,
3200                                 u32 max_clock, u32 requested_clock)
3201 {
3202         unsigned int i;
3203
3204         if ((clocks == NULL) || (clocks->count == 0))
3205                 return (requested_clock < max_clock) ? requested_clock : max_clock;
3206
3207         for (i = 0; i < clocks->count; i++) {
3208                 if (clocks->values[i] >= requested_clock)
3209                         return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;
3210         }
3211
3212         return (clocks->values[clocks->count - 1] < max_clock) ?
3213                 clocks->values[clocks->count - 1] : max_clock;
3214 }
3215
3216 static u32 btc_get_valid_mclk(struct amdgpu_device *adev,
3217                               u32 max_mclk, u32 requested_mclk)
3218 {
3219         return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values,
3220                                     max_mclk, requested_mclk);
3221 }
3222
3223 static u32 btc_get_valid_sclk(struct amdgpu_device *adev,
3224                               u32 max_sclk, u32 requested_sclk)
3225 {
3226         return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values,
3227                                     max_sclk, requested_sclk);
3228 }
3229
3230 static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,
3231                                                             u32 *max_clock)
3232 {
3233         u32 i, clock = 0;
3234
3235         if ((table == NULL) || (table->count == 0)) {
3236                 *max_clock = clock;
3237                 return;
3238         }
3239
3240         for (i = 0; i < table->count; i++) {
3241                 if (clock < table->entries[i].clk)
3242                         clock = table->entries[i].clk;
3243         }
3244         *max_clock = clock;
3245 }
3246
3247 static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table,
3248                                                u32 clock, u16 max_voltage, u16 *voltage)
3249 {
3250         u32 i;
3251
3252         if ((table == NULL) || (table->count == 0))
3253                 return;
3254
3255         for (i= 0; i < table->count; i++) {
3256                 if (clock <= table->entries[i].clk) {
3257                         if (*voltage < table->entries[i].v)
3258                                 *voltage = (u16)((table->entries[i].v < max_voltage) ?
3259                                            table->entries[i].v : max_voltage);
3260                         return;
3261                 }
3262         }
3263
3264         *voltage = (*voltage > max_voltage) ? *voltage : max_voltage;
3265 }
3266
3267 static void btc_adjust_clock_combinations(struct amdgpu_device *adev,
3268                                           const struct amdgpu_clock_and_voltage_limits *max_limits,
3269                                           struct rv7xx_pl *pl)
3270 {
3271
3272         if ((pl->mclk == 0) || (pl->sclk == 0))
3273                 return;
3274
3275         if (pl->mclk == pl->sclk)
3276                 return;
3277
3278         if (pl->mclk > pl->sclk) {
3279                 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio)
3280                         pl->sclk = btc_get_valid_sclk(adev,
3281                                                       max_limits->sclk,
3282                                                       (pl->mclk +
3283                                                       (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
3284                                                       adev->pm.dpm.dyn_state.mclk_sclk_ratio);
3285         } else {
3286                 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta)
3287                         pl->mclk = btc_get_valid_mclk(adev,
3288                                                       max_limits->mclk,
3289                                                       pl->sclk -
3290                                                       adev->pm.dpm.dyn_state.sclk_mclk_delta);
3291         }
3292 }
3293
3294 static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
3295                                           u16 max_vddc, u16 max_vddci,
3296                                           u16 *vddc, u16 *vddci)
3297 {
3298         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3299         u16 new_voltage;
3300
3301         if ((0 == *vddc) || (0 == *vddci))
3302                 return;
3303
3304         if (*vddc > *vddci) {
3305                 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3306                         new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table,
3307                                                        (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3308                         *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci;
3309                 }
3310         } else {
3311                 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3312                         new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table,
3313                                                        (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3314                         *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc;
3315                 }
3316         }
3317 }
3318
3319 static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
3320                             u32 *p, u32 *u)
3321 {
3322         u32 b_c = 0;
3323         u32 i_c;
3324         u32 tmp;
3325
3326         i_c = (i * r_c) / 100;
3327         tmp = i_c >> p_b;
3328
3329         while (tmp) {
3330                 b_c++;
3331                 tmp >>= 1;
3332         }
3333
3334         *u = (b_c + 1) / 2;
3335         *p = i_c / (1 << (2 * (*u)));
3336 }
3337
3338 static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
3339 {
3340         u32 k, a, ah, al;
3341         u32 t1;
3342
3343         if ((fl == 0) || (fh == 0) || (fl > fh))
3344                 return -EINVAL;
3345
3346         k = (100 * fh) / fl;
3347         t1 = (t * (k - 100));
3348         a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
3349         a = (a + 5) / 10;
3350         ah = ((a * t) + 5000) / 10000;
3351         al = a - ah;
3352
3353         *th = t - ah;
3354         *tl = t + al;
3355
3356         return 0;
3357 }
3358
3359 static bool r600_is_uvd_state(u32 class, u32 class2)
3360 {
3361         if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3362                 return true;
3363         if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3364                 return true;
3365         if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3366                 return true;
3367         if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3368                 return true;
3369         if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3370                 return true;
3371         return false;
3372 }
3373
3374 static u8 rv770_get_memory_module_index(struct amdgpu_device *adev)
3375 {
3376         return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
3377 }
3378
3379 static void rv770_get_max_vddc(struct amdgpu_device *adev)
3380 {
3381         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3382         u16 vddc;
3383
3384         if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc))
3385                 pi->max_vddc = 0;
3386         else
3387                 pi->max_vddc = vddc;
3388 }
3389
3390 static void rv770_get_engine_memory_ss(struct amdgpu_device *adev)
3391 {
3392         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3393         struct amdgpu_atom_ss ss;
3394
3395         pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3396                                                        ASIC_INTERNAL_ENGINE_SS, 0);
3397         pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3398                                                        ASIC_INTERNAL_MEMORY_SS, 0);
3399
3400         if (pi->sclk_ss || pi->mclk_ss)
3401                 pi->dynamic_ss = true;
3402         else
3403                 pi->dynamic_ss = false;
3404 }
3405
3406
3407 static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
3408                                         struct amdgpu_ps *rps)
3409 {
3410         struct  si_ps *ps = si_get_ps(rps);
3411         struct amdgpu_clock_and_voltage_limits *max_limits;
3412         bool disable_mclk_switching = false;
3413         bool disable_sclk_switching = false;
3414         u32 mclk, sclk;
3415         u16 vddc, vddci, min_vce_voltage = 0;
3416         u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
3417         u32 max_sclk = 0, max_mclk = 0;
3418         int i;
3419
3420         if (adev->asic_type == CHIP_HAINAN) {
3421                 if ((adev->pdev->revision == 0x81) ||
3422                     (adev->pdev->revision == 0xC3) ||
3423                     (adev->pdev->device == 0x6664) ||
3424                     (adev->pdev->device == 0x6665) ||
3425                     (adev->pdev->device == 0x6667)) {
3426                         max_sclk = 75000;
3427                 }
3428                 if ((adev->pdev->revision == 0xC3) ||
3429                     (adev->pdev->device == 0x6665)) {
3430                         max_sclk = 60000;
3431                         max_mclk = 80000;
3432                 }
3433         } else if (adev->asic_type == CHIP_OLAND) {
3434                 if ((adev->pdev->revision == 0xC7) ||
3435                     (adev->pdev->revision == 0x80) ||
3436                     (adev->pdev->revision == 0x81) ||
3437                     (adev->pdev->revision == 0x83) ||
3438                     (adev->pdev->revision == 0x87) ||
3439                     (adev->pdev->device == 0x6604) ||
3440                     (adev->pdev->device == 0x6605)) {
3441                         max_sclk = 75000;
3442                 }
3443         }
3444
3445         if (rps->vce_active) {
3446                 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
3447                 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
3448                 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk,
3449                                          &min_vce_voltage);
3450         } else {
3451                 rps->evclk = 0;
3452                 rps->ecclk = 0;
3453         }
3454
3455         if ((adev->pm.dpm.new_active_crtc_count > 1) ||
3456             si_dpm_vblank_too_short(adev))
3457                 disable_mclk_switching = true;
3458
3459         if (rps->vclk || rps->dclk) {
3460                 disable_mclk_switching = true;
3461                 disable_sclk_switching = true;
3462         }
3463
3464         if (adev->pm.ac_power)
3465                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3466         else
3467                 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3468
3469         for (i = ps->performance_level_count - 2; i >= 0; i--) {
3470                 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3471                         ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3472         }
3473         if (adev->pm.ac_power == false) {
3474                 for (i = 0; i < ps->performance_level_count; i++) {
3475                         if (ps->performance_levels[i].mclk > max_limits->mclk)
3476                                 ps->performance_levels[i].mclk = max_limits->mclk;
3477                         if (ps->performance_levels[i].sclk > max_limits->sclk)
3478                                 ps->performance_levels[i].sclk = max_limits->sclk;
3479                         if (ps->performance_levels[i].vddc > max_limits->vddc)
3480                                 ps->performance_levels[i].vddc = max_limits->vddc;
3481                         if (ps->performance_levels[i].vddci > max_limits->vddci)
3482                                 ps->performance_levels[i].vddci = max_limits->vddci;
3483                 }
3484         }
3485
3486         /* limit clocks to max supported clocks based on voltage dependency tables */
3487         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3488                                                         &max_sclk_vddc);
3489         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3490                                                         &max_mclk_vddci);
3491         btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3492                                                         &max_mclk_vddc);
3493
3494         for (i = 0; i < ps->performance_level_count; i++) {
3495                 if (max_sclk_vddc) {
3496                         if (ps->performance_levels[i].sclk > max_sclk_vddc)
3497                                 ps->performance_levels[i].sclk = max_sclk_vddc;
3498                 }
3499                 if (max_mclk_vddci) {
3500                         if (ps->performance_levels[i].mclk > max_mclk_vddci)
3501                                 ps->performance_levels[i].mclk = max_mclk_vddci;
3502                 }
3503                 if (max_mclk_vddc) {
3504                         if (ps->performance_levels[i].mclk > max_mclk_vddc)
3505                                 ps->performance_levels[i].mclk = max_mclk_vddc;
3506                 }
3507                 if (max_mclk) {
3508                         if (ps->performance_levels[i].mclk > max_mclk)
3509                                 ps->performance_levels[i].mclk = max_mclk;
3510                 }
3511                 if (max_sclk) {
3512                         if (ps->performance_levels[i].sclk > max_sclk)
3513                                 ps->performance_levels[i].sclk = max_sclk;
3514                 }
3515         }
3516
3517         /* XXX validate the min clocks required for display */
3518
3519         if (disable_mclk_switching) {
3520                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
3521                 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3522         } else {
3523                 mclk = ps->performance_levels[0].mclk;
3524                 vddci = ps->performance_levels[0].vddci;
3525         }
3526
3527         if (disable_sclk_switching) {
3528                 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3529                 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3530         } else {
3531                 sclk = ps->performance_levels[0].sclk;
3532                 vddc = ps->performance_levels[0].vddc;
3533         }
3534
3535         if (rps->vce_active) {
3536                 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
3537                         sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
3538                 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
3539                         mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
3540         }
3541
3542         /* adjusted low state */
3543         ps->performance_levels[0].sclk = sclk;
3544         ps->performance_levels[0].mclk = mclk;
3545         ps->performance_levels[0].vddc = vddc;
3546         ps->performance_levels[0].vddci = vddci;
3547
3548         if (disable_sclk_switching) {
3549                 sclk = ps->performance_levels[0].sclk;
3550                 for (i = 1; i < ps->performance_level_count; i++) {
3551                         if (sclk < ps->performance_levels[i].sclk)
3552                                 sclk = ps->performance_levels[i].sclk;
3553                 }
3554                 for (i = 0; i < ps->performance_level_count; i++) {
3555                         ps->performance_levels[i].sclk = sclk;
3556                         ps->performance_levels[i].vddc = vddc;
3557                 }
3558         } else {
3559                 for (i = 1; i < ps->performance_level_count; i++) {
3560                         if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3561                                 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3562                         if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3563                                 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3564                 }
3565         }
3566
3567         if (disable_mclk_switching) {
3568                 mclk = ps->performance_levels[0].mclk;
3569                 for (i = 1; i < ps->performance_level_count; i++) {
3570                         if (mclk < ps->performance_levels[i].mclk)
3571                                 mclk = ps->performance_levels[i].mclk;
3572                 }
3573                 for (i = 0; i < ps->performance_level_count; i++) {
3574                         ps->performance_levels[i].mclk = mclk;
3575                         ps->performance_levels[i].vddci = vddci;
3576                 }
3577         } else {
3578                 for (i = 1; i < ps->performance_level_count; i++) {
3579                         if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3580                                 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3581                         if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3582                                 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3583                 }
3584         }
3585
3586         for (i = 0; i < ps->performance_level_count; i++)
3587                 btc_adjust_clock_combinations(adev, max_limits,
3588                                               &ps->performance_levels[i]);
3589
3590         for (i = 0; i < ps->performance_level_count; i++) {
3591                 if (ps->performance_levels[i].vddc < min_vce_voltage)
3592                         ps->performance_levels[i].vddc = min_vce_voltage;
3593                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3594                                                    ps->performance_levels[i].sclk,
3595                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3596                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3597                                                    ps->performance_levels[i].mclk,
3598                                                    max_limits->vddci, &ps->performance_levels[i].vddci);
3599                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3600                                                    ps->performance_levels[i].mclk,
3601                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3602                 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3603                                                    adev->clock.current_dispclk,
3604                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3605         }
3606
3607         for (i = 0; i < ps->performance_level_count; i++) {
3608                 btc_apply_voltage_delta_rules(adev,
3609                                               max_limits->vddc, max_limits->vddci,
3610                                               &ps->performance_levels[i].vddc,
3611                                               &ps->performance_levels[i].vddci);
3612         }
3613
3614         ps->dc_compatible = true;
3615         for (i = 0; i < ps->performance_level_count; i++) {
3616                 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3617                         ps->dc_compatible = false;
3618         }
3619 }
3620
3621 #if 0
3622 static int si_read_smc_soft_register(struct amdgpu_device *adev,
3623                                      u16 reg_offset, u32 *value)
3624 {
3625         struct si_power_info *si_pi = si_get_pi(adev);
3626
3627         return amdgpu_si_read_smc_sram_dword(adev,
3628                                              si_pi->soft_regs_start + reg_offset, value,
3629                                              si_pi->sram_end);
3630 }
3631 #endif
3632
3633 static int si_write_smc_soft_register(struct amdgpu_device *adev,
3634                                       u16 reg_offset, u32 value)
3635 {
3636         struct si_power_info *si_pi = si_get_pi(adev);
3637
3638         return amdgpu_si_write_smc_sram_dword(adev,
3639                                               si_pi->soft_regs_start + reg_offset,
3640                                               value, si_pi->sram_end);
3641 }
3642
3643 static bool si_is_special_1gb_platform(struct amdgpu_device *adev)
3644 {
3645         bool ret = false;
3646         u32 tmp, width, row, column, bank, density;
3647         bool is_memory_gddr5, is_special;
3648
3649         tmp = RREG32(MC_SEQ_MISC0);
3650         is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3651         is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3652                 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3653
3654         WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3655         width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3656
3657         tmp = RREG32(MC_ARB_RAMCFG);
3658         row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3659         column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3660         bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3661
3662         density = (1 << (row + column - 20 + bank)) * width;
3663
3664         if ((adev->pdev->device == 0x6819) &&
3665             is_memory_gddr5 && is_special && (density == 0x400))
3666                 ret = true;
3667
3668         return ret;
3669 }
3670
3671 static void si_get_leakage_vddc(struct amdgpu_device *adev)
3672 {
3673         struct si_power_info *si_pi = si_get_pi(adev);
3674         u16 vddc, count = 0;
3675         int i, ret;
3676
3677         for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3678                 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3679
3680                 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3681                         si_pi->leakage_voltage.entries[count].voltage = vddc;
3682                         si_pi->leakage_voltage.entries[count].leakage_index =
3683                                 SISLANDS_LEAKAGE_INDEX0 + i;
3684                         count++;
3685                 }
3686         }
3687         si_pi->leakage_voltage.count = count;
3688 }
3689
3690 static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev,
3691                                                      u32 index, u16 *leakage_voltage)
3692 {
3693         struct si_power_info *si_pi = si_get_pi(adev);
3694         int i;
3695
3696         if (leakage_voltage == NULL)
3697                 return -EINVAL;
3698
3699         if ((index & 0xff00) != 0xff00)
3700                 return -EINVAL;
3701
3702         if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3703                 return -EINVAL;
3704
3705         if (index < SISLANDS_LEAKAGE_INDEX0)
3706                 return -EINVAL;
3707
3708         for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3709                 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3710                         *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3711                         return 0;
3712                 }
3713         }
3714         return -EAGAIN;
3715 }
3716
3717 static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
3718 {
3719         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3720         bool want_thermal_protection;
3721         enum amdgpu_dpm_event_src dpm_event_src;
3722
3723         switch (sources) {
3724         case 0:
3725         default:
3726                 want_thermal_protection = false;
3727                 break;
3728         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
3729                 want_thermal_protection = true;
3730                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
3731                 break;
3732         case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3733                 want_thermal_protection = true;
3734                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
3735                 break;
3736         case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3737               (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3738                 want_thermal_protection = true;
3739                 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3740                 break;
3741         }
3742
3743         if (want_thermal_protection) {
3744                 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3745                 if (pi->thermal_protection)
3746                         WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3747         } else {
3748                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3749         }
3750 }
3751
3752 static void si_enable_auto_throttle_source(struct amdgpu_device *adev,
3753                                            enum amdgpu_dpm_auto_throttle_src source,
3754                                            bool enable)
3755 {
3756         struct rv7xx_power_info *pi = rv770_get_pi(adev);
3757
3758         if (enable) {
3759                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3760                         pi->active_auto_throttle_sources |= 1 << source;
3761                         si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3762                 }
3763         } else {
3764                 if (pi->active_auto_throttle_sources & (1 << source)) {
3765                         pi->active_auto_throttle_sources &= ~(1 << source);
3766                         si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3767                 }
3768         }
3769 }
3770
3771 static void si_start_dpm(struct amdgpu_device *adev)
3772 {
3773         WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3774 }
3775
3776 static void si_stop_dpm(struct amdgpu_device *adev)
3777 {
3778         WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3779 }
3780
3781 static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable)
3782 {
3783         if (enable)
3784                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3785         else
3786                 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3787
3788 }
3789
3790 #if 0
3791 static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev,
3792                                                u32 thermal_level)
3793 {
3794         PPSMC_Result ret;
3795
3796         if (thermal_level == 0) {
3797                 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
3798                 if (ret == PPSMC_Result_OK)
3799                         return 0;
3800                 else
3801                         return -EINVAL;
3802         }
3803         return 0;
3804 }
3805
3806 static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev)
3807 {
3808         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3809 }
3810 #endif
3811
3812 #if 0
3813 static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)
3814 {
3815         if (ac_power)
3816                 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3817                         0 : -EINVAL;
3818
3819         return 0;
3820 }
3821 #endif
3822
3823 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
3824                                                       PPSMC_Msg msg, u32 parameter)
3825 {
3826         WREG32(SMC_SCRATCH0, parameter);
3827         return amdgpu_si_send_msg_to_smc(adev, msg);
3828 }
3829
3830 static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev)
3831 {
3832         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3833                 return -EINVAL;
3834
3835         return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3836                 0 : -EINVAL;
3837 }
3838
3839 static int si_dpm_force_performance_level(void *handle,
3840                                    enum amd_dpm_forced_level level)
3841 {
3842         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3843         struct amdgpu_ps *rps = adev->pm.dpm.current_ps;
3844         struct  si_ps *ps = si_get_ps(rps);
3845         u32 levels = ps->performance_level_count;
3846
3847         if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
3848                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3849                         return -EINVAL;
3850
3851                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3852                         return -EINVAL;
3853         } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
3854                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3855                         return -EINVAL;
3856
3857                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3858                         return -EINVAL;
3859         } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
3860                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3861                         return -EINVAL;
3862
3863                 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3864                         return -EINVAL;
3865         }
3866
3867         adev->pm.dpm.forced_level = level;
3868
3869         return 0;
3870 }
3871
3872 #if 0
3873 static int si_set_boot_state(struct amdgpu_device *adev)
3874 {
3875         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3876                 0 : -EINVAL;
3877 }
3878 #endif
3879
3880 static int si_set_sw_state(struct amdgpu_device *adev)
3881 {
3882         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3883                 0 : -EINVAL;
3884 }
3885
3886 static int si_halt_smc(struct amdgpu_device *adev)
3887 {
3888         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3889                 return -EINVAL;
3890
3891         return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?
3892                 0 : -EINVAL;
3893 }
3894
3895 static int si_resume_smc(struct amdgpu_device *adev)
3896 {
3897         if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3898                 return -EINVAL;
3899
3900         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3901                 0 : -EINVAL;
3902 }
3903
3904 static void si_dpm_start_smc(struct amdgpu_device *adev)
3905 {
3906         amdgpu_si_program_jump_on_start(adev);
3907         amdgpu_si_start_smc(adev);
3908         amdgpu_si_smc_clock(adev, true);
3909 }
3910
3911 static void si_dpm_stop_smc(struct amdgpu_device *adev)
3912 {
3913         amdgpu_si_reset_smc(adev);
3914         amdgpu_si_smc_clock(adev, false);
3915 }
3916
3917 static int si_process_firmware_header(struct amdgpu_device *adev)
3918 {
3919         struct si_power_info *si_pi = si_get_pi(adev);
3920         u32 tmp;
3921         int ret;
3922
3923         ret = amdgpu_si_read_smc_sram_dword(adev,
3924                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3925                                             SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3926                                             &tmp, si_pi->sram_end);
3927         if (ret)
3928                 return ret;
3929
3930         si_pi->state_table_start = tmp;
3931
3932         ret = amdgpu_si_read_smc_sram_dword(adev,
3933                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3934                                             SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3935                                             &tmp, si_pi->sram_end);
3936         if (ret)
3937                 return ret;
3938
3939         si_pi->soft_regs_start = tmp;
3940
3941         ret = amdgpu_si_read_smc_sram_dword(adev,
3942                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3943                                             SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3944                                             &tmp, si_pi->sram_end);
3945         if (ret)
3946                 return ret;
3947
3948         si_pi->mc_reg_table_start = tmp;
3949
3950         ret = amdgpu_si_read_smc_sram_dword(adev,
3951                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3952                                             SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3953                                             &tmp, si_pi->sram_end);
3954         if (ret)
3955                 return ret;
3956
3957         si_pi->fan_table_start = tmp;
3958
3959         ret = amdgpu_si_read_smc_sram_dword(adev,
3960                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3961                                             SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3962                                             &tmp, si_pi->sram_end);
3963         if (ret)
3964                 return ret;
3965
3966         si_pi->arb_table_start = tmp;
3967
3968         ret = amdgpu_si_read_smc_sram_dword(adev,
3969                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3970                                             SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3971                                             &tmp, si_pi->sram_end);
3972         if (ret)
3973                 return ret;
3974
3975         si_pi->cac_table_start = tmp;
3976
3977         ret = amdgpu_si_read_smc_sram_dword(adev,
3978                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3979                                             SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3980                                             &tmp, si_pi->sram_end);
3981         if (ret)
3982                 return ret;
3983
3984         si_pi->dte_table_start = tmp;
3985
3986         ret = amdgpu_si_read_smc_sram_dword(adev,
3987                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3988                                             SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3989                                             &tmp, si_pi->sram_end);
3990         if (ret)
3991                 return ret;
3992
3993         si_pi->spll_table_start = tmp;
3994
3995         ret = amdgpu_si_read_smc_sram_dword(adev,
3996                                             SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3997                                             SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3998                                             &tmp, si_pi->sram_end);
3999         if (ret)
4000                 return ret;
4001
4002         si_pi->papm_cfg_table_start = tmp;
4003
4004         return ret;
4005 }
4006
4007 static void si_read_clock_registers(struct amdgpu_device *adev)
4008 {
4009         struct si_power_info *si_pi = si_get_pi(adev);
4010
4011         si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
4012         si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
4013         si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
4014         si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
4015         si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
4016         si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
4017         si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
4018         si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
4019         si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
4020         si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
4021         si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
4022         si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
4023         si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
4024         si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
4025         si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
4026 }
4027
4028 static void si_enable_thermal_protection(struct amdgpu_device *adev,
4029                                           bool enable)
4030 {
4031         if (enable)
4032                 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
4033         else
4034                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
4035 }
4036
4037 static void si_enable_acpi_power_management(struct amdgpu_device *adev)
4038 {
4039         WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
4040 }
4041
4042 #if 0
4043 static int si_enter_ulp_state(struct amdgpu_device *adev)
4044 {
4045         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
4046
4047         udelay(25000);
4048
4049         return 0;
4050 }
4051
4052 static int si_exit_ulp_state(struct amdgpu_device *adev)
4053 {
4054         int i;
4055
4056         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
4057
4058         udelay(7000);
4059
4060         for (i = 0; i < adev->usec_timeout; i++) {
4061                 if (RREG32(SMC_RESP_0) == 1)
4062                         break;
4063                 udelay(1000);
4064         }
4065
4066         return 0;
4067 }
4068 #endif
4069
4070 static int si_notify_smc_display_change(struct amdgpu_device *adev,
4071                                      bool has_display)
4072 {
4073         PPSMC_Msg msg = has_display ?
4074                 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
4075
4076         return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?
4077                 0 : -EINVAL;
4078 }
4079
4080 static void si_program_response_times(struct amdgpu_device *adev)
4081 {
4082         u32 voltage_response_time, acpi_delay_time, vbi_time_out;
4083         u32 vddc_dly, acpi_dly, vbi_dly;
4084         u32 reference_clock;
4085
4086         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
4087
4088         voltage_response_time = (u32)adev->pm.dpm.voltage_response_time;
4089
4090         if (voltage_response_time == 0)
4091                 voltage_response_time = 1000;
4092
4093         acpi_delay_time = 15000;
4094         vbi_time_out = 100000;
4095
4096         reference_clock = amdgpu_asic_get_xclk(adev);
4097
4098         vddc_dly = (voltage_response_time  * reference_clock) / 100;
4099         acpi_dly = (acpi_delay_time * reference_clock) / 100;
4100         vbi_dly  = (vbi_time_out * reference_clock) / 100;
4101
4102         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
4103         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
4104         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
4105         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
4106 }
4107
4108 static void si_program_ds_registers(struct amdgpu_device *adev)
4109 {
4110         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4111         u32 tmp;
4112
4113         /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
4114         if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
4115                 tmp = 0x10;
4116         else
4117                 tmp = 0x1;
4118
4119         if (eg_pi->sclk_deep_sleep) {
4120                 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
4121                 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
4122                          ~AUTOSCALE_ON_SS_CLEAR);
4123         }
4124 }
4125
4126 static void si_program_display_gap(struct amdgpu_device *adev)
4127 {
4128         u32 tmp, pipe;
4129         int i;
4130
4131         tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4132         if (adev->pm.dpm.new_active_crtc_count > 0)
4133                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4134         else
4135                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4136
4137         if (adev->pm.dpm.new_active_crtc_count > 1)
4138                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4139         else
4140                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4141
4142         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4143
4144         tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
4145         pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
4146
4147         if ((adev->pm.dpm.new_active_crtc_count > 0) &&
4148             (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
4149                 /* find the first active crtc */
4150                 for (i = 0; i < adev->mode_info.num_crtc; i++) {
4151                         if (adev->pm.dpm.new_active_crtcs & (1 << i))
4152                                 break;
4153                 }
4154                 if (i == adev->mode_info.num_crtc)
4155                         pipe = 0;
4156                 else
4157                         pipe = i;
4158
4159                 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
4160                 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
4161                 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
4162         }
4163
4164         /* Setting this to false forces the performance state to low if the crtcs are disabled.
4165          * This can be a problem on PowerXpress systems or if you want to use the card
4166          * for offscreen rendering or compute if there are no crtcs enabled.
4167          */
4168         si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0);
4169 }
4170
4171 static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
4172 {
4173         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4174
4175         if (enable) {
4176                 if (pi->sclk_ss)
4177                         WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
4178         } else {
4179                 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
4180                 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
4181         }
4182 }
4183
4184 static void si_setup_bsp(struct amdgpu_device *adev)
4185 {
4186         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4187         u32 xclk = amdgpu_asic_get_xclk(adev);
4188
4189         r600_calculate_u_and_p(pi->asi,
4190                                xclk,
4191                                16,
4192                                &pi->bsp,
4193                                &pi->bsu);
4194
4195         r600_calculate_u_and_p(pi->pasi,
4196                                xclk,
4197                                16,
4198                                &pi->pbsp,
4199                                &pi->pbsu);
4200
4201
4202         pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
4203         pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
4204
4205         WREG32(CG_BSP, pi->dsp);
4206 }
4207
4208 static void si_program_git(struct amdgpu_device *adev)
4209 {
4210         WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
4211 }
4212
4213 static void si_program_tp(struct amdgpu_device *adev)
4214 {
4215         int i;
4216         enum r600_td td = R600_TD_DFLT;
4217
4218         for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
4219                 WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
4220
4221         if (td == R600_TD_AUTO)
4222                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
4223         else
4224                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
4225
4226         if (td == R600_TD_UP)
4227                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
4228
4229         if (td == R600_TD_DOWN)
4230                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
4231 }
4232
4233 static void si_program_tpp(struct amdgpu_device *adev)
4234 {
4235         WREG32(CG_TPC, R600_TPC_DFLT);
4236 }
4237
4238 static void si_program_sstp(struct amdgpu_device *adev)
4239 {
4240         WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
4241 }
4242
4243 static void si_enable_display_gap(struct amdgpu_device *adev)
4244 {
4245         u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
4246
4247         tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4248         tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
4249                 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
4250
4251         tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
4252         tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
4253                 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
4254         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4255 }
4256
4257 static void si_program_vc(struct amdgpu_device *adev)
4258 {
4259         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4260
4261         WREG32(CG_FTV, pi->vrc);
4262 }
4263
4264 static void si_clear_vc(struct amdgpu_device *adev)
4265 {
4266         WREG32(CG_FTV, 0);
4267 }
4268
4269 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
4270 {
4271         u8 mc_para_index;
4272
4273         if (memory_clock < 10000)
4274                 mc_para_index = 0;
4275         else if (memory_clock >= 80000)
4276                 mc_para_index = 0x0f;
4277         else
4278                 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
4279         return mc_para_index;
4280 }
4281
4282 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
4283 {
4284         u8 mc_para_index;
4285
4286         if (strobe_mode) {
4287                 if (memory_clock < 12500)
4288                         mc_para_index = 0x00;
4289                 else if (memory_clock > 47500)
4290                         mc_para_index = 0x0f;
4291                 else
4292                         mc_para_index = (u8)((memory_clock - 10000) / 2500);
4293         } else {
4294                 if (memory_clock < 65000)
4295                         mc_para_index = 0x00;
4296                 else if (memory_clock > 135000)
4297                         mc_para_index = 0x0f;
4298                 else
4299                         mc_para_index = (u8)((memory_clock - 60000) / 5000);
4300         }
4301         return mc_para_index;
4302 }
4303
4304 static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
4305 {
4306         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4307         bool strobe_mode = false;
4308         u8 result = 0;
4309
4310         if (mclk <= pi->mclk_strobe_mode_threshold)
4311                 strobe_mode = true;
4312
4313         if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
4314                 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
4315         else
4316                 result = si_get_ddr3_mclk_frequency_ratio(mclk);
4317
4318         if (strobe_mode)
4319                 result |= SISLANDS_SMC_STROBE_ENABLE;
4320
4321         return result;
4322 }
4323
4324 static int si_upload_firmware(struct amdgpu_device *adev)
4325 {
4326         struct si_power_info *si_pi = si_get_pi(adev);
4327
4328         amdgpu_si_reset_smc(adev);
4329         amdgpu_si_smc_clock(adev, false);
4330
4331         return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end);
4332 }
4333
4334 static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
4335                                               const struct atom_voltage_table *table,
4336                                               const struct amdgpu_phase_shedding_limits_table *limits)
4337 {
4338         u32 data, num_bits, num_levels;
4339
4340         if ((table == NULL) || (limits == NULL))
4341                 return false;
4342
4343         data = table->mask_low;
4344
4345         num_bits = hweight32(data);
4346
4347         if (num_bits == 0)
4348                 return false;
4349
4350         num_levels = (1 << num_bits);
4351
4352         if (table->count != num_levels)
4353                 return false;
4354
4355         if (limits->count != (num_levels - 1))
4356                 return false;
4357
4358         return true;
4359 }
4360
4361 static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
4362                                               u32 max_voltage_steps,
4363                                               struct atom_voltage_table *voltage_table)
4364 {
4365         unsigned int i, diff;
4366
4367         if (voltage_table->count <= max_voltage_steps)
4368                 return;
4369
4370         diff = voltage_table->count - max_voltage_steps;
4371
4372         for (i= 0; i < max_voltage_steps; i++)
4373                 voltage_table->entries[i] = voltage_table->entries[i + diff];
4374
4375         voltage_table->count = max_voltage_steps;
4376 }
4377
4378 static int si_get_svi2_voltage_table(struct amdgpu_device *adev,
4379                                      struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
4380                                      struct atom_voltage_table *voltage_table)
4381 {
4382         u32 i;
4383
4384         if (voltage_dependency_table == NULL)
4385                 return -EINVAL;
4386
4387         voltage_table->mask_low = 0;
4388         voltage_table->phase_delay = 0;
4389
4390         voltage_table->count = voltage_dependency_table->count;
4391         for (i = 0; i < voltage_table->count; i++) {
4392                 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4393                 voltage_table->entries[i].smio_low = 0;
4394         }
4395
4396         return 0;
4397 }
4398
4399 static int si_construct_voltage_tables(struct amdgpu_device *adev)
4400 {
4401         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4402         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4403         struct si_power_info *si_pi = si_get_pi(adev);
4404         int ret;
4405
4406         if (pi->voltage_control) {
4407                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4408                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4409                 if (ret)
4410                         return ret;
4411
4412                 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4413                         si_trim_voltage_table_to_fit_state_table(adev,
4414                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4415                                                                  &eg_pi->vddc_voltage_table);
4416         } else if (si_pi->voltage_control_svi2) {
4417                 ret = si_get_svi2_voltage_table(adev,
4418                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4419                                                 &eg_pi->vddc_voltage_table);
4420                 if (ret)
4421                         return ret;
4422         } else {
4423                 return -EINVAL;
4424         }
4425
4426         if (eg_pi->vddci_control) {
4427                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
4428                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4429                 if (ret)
4430                         return ret;
4431
4432                 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4433                         si_trim_voltage_table_to_fit_state_table(adev,
4434                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4435                                                                  &eg_pi->vddci_voltage_table);
4436         }
4437         if (si_pi->vddci_control_svi2) {
4438                 ret = si_get_svi2_voltage_table(adev,
4439                                                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4440                                                 &eg_pi->vddci_voltage_table);
4441                 if (ret)
4442                         return ret;
4443         }
4444
4445         if (pi->mvdd_control) {
4446                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
4447                                                     VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4448
4449                 if (ret) {
4450                         pi->mvdd_control = false;
4451                         return ret;
4452                 }
4453
4454                 if (si_pi->mvdd_voltage_table.count == 0) {
4455                         pi->mvdd_control = false;
4456                         return -EINVAL;
4457                 }
4458
4459                 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4460                         si_trim_voltage_table_to_fit_state_table(adev,
4461                                                                  SISLANDS_MAX_NO_VREG_STEPS,
4462                                                                  &si_pi->mvdd_voltage_table);
4463         }
4464
4465         if (si_pi->vddc_phase_shed_control) {
4466                 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4467                                                     VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4468                 if (ret)
4469                         si_pi->vddc_phase_shed_control = false;
4470
4471                 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4472                     (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4473                         si_pi->vddc_phase_shed_control = false;
4474         }
4475
4476         return 0;
4477 }
4478
4479 static void si_populate_smc_voltage_table(struct amdgpu_device *adev,
4480                                           const struct atom_voltage_table *voltage_table,
4481                                           SISLANDS_SMC_STATETABLE *table)
4482 {
4483         unsigned int i;
4484
4485         for (i = 0; i < voltage_table->count; i++)
4486                 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4487 }
4488
4489 static int si_populate_smc_voltage_tables(struct amdgpu_device *adev,
4490                                           SISLANDS_SMC_STATETABLE *table)
4491 {
4492         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4493         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4494         struct si_power_info *si_pi = si_get_pi(adev);
4495         u8 i;
4496
4497         if (si_pi->voltage_control_svi2) {
4498                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4499                         si_pi->svc_gpio_id);
4500                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4501                         si_pi->svd_gpio_id);
4502                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4503                                            2);
4504         } else {
4505                 if (eg_pi->vddc_voltage_table.count) {
4506                         si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table);
4507                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4508                                 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4509
4510                         for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4511                                 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4512                                         table->maxVDDCIndexInPPTable = i;
4513                                         break;
4514                                 }
4515                         }
4516                 }
4517
4518                 if (eg_pi->vddci_voltage_table.count) {
4519                         si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table);
4520
4521                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4522                                 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4523                 }
4524
4525
4526                 if (si_pi->mvdd_voltage_table.count) {
4527                         si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table);
4528
4529                         table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4530                                 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4531                 }
4532
4533                 if (si_pi->vddc_phase_shed_control) {
4534                         if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table,
4535                                                               &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4536                                 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);
4537
4538                                 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
4539                                         cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4540
4541                                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4542                                                            (u32)si_pi->vddc_phase_shed_table.phase_delay);
4543                         } else {
4544                                 si_pi->vddc_phase_shed_control = false;
4545                         }
4546                 }
4547         }
4548
4549         return 0;
4550 }
4551
4552 static int si_populate_voltage_value(struct amdgpu_device *adev,
4553                                      const struct atom_voltage_table *table,
4554                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4555 {
4556         unsigned int i;
4557
4558         for (i = 0; i < table->count; i++) {
4559                 if (value <= table->entries[i].value) {
4560                         voltage->index = (u8)i;
4561                         voltage->value = cpu_to_be16(table->entries[i].value);
4562                         break;
4563                 }
4564         }
4565
4566         if (i >= table->count)
4567                 return -EINVAL;
4568
4569         return 0;
4570 }
4571
4572 static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
4573                                   SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4574 {
4575         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4576         struct si_power_info *si_pi = si_get_pi(adev);
4577
4578         if (pi->mvdd_control) {
4579                 if (mclk <= pi->mvdd_split_frequency)
4580                         voltage->index = 0;
4581                 else
4582                         voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4583
4584                 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4585         }
4586         return 0;
4587 }
4588
4589 static int si_get_std_voltage_value(struct amdgpu_device *adev,
4590                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4591                                     u16 *std_voltage)
4592 {
4593         u16 v_index;
4594         bool voltage_found = false;
4595         *std_voltage = be16_to_cpu(voltage->value);
4596
4597         if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4598                 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4599                         if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4600                                 return -EINVAL;
4601
4602                         for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4603                                 if (be16_to_cpu(voltage->value) ==
4604                                     (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4605                                         voltage_found = true;
4606                                         if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4607                                                 *std_voltage =
4608                                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4609                                         else
4610                                                 *std_voltage =
4611                                                         adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4612                                         break;
4613                                 }
4614                         }
4615
4616                         if (!voltage_found) {
4617                                 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4618                                         if (be16_to_cpu(voltage->value) <=
4619                                             (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4620                                                 voltage_found = true;
4621                                                 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4622                                                         *std_voltage =
4623                                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4624                                                 else
4625                                                         *std_voltage =
4626                                                                 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4627                                                 break;
4628                                         }
4629                                 }
4630                         }
4631                 } else {
4632                         if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4633                                 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4634                 }
4635         }
4636
4637         return 0;
4638 }
4639
4640 static int si_populate_std_voltage_value(struct amdgpu_device *adev,
4641                                          u16 value, u8 index,
4642                                          SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4643 {
4644         voltage->index = index;
4645         voltage->value = cpu_to_be16(value);
4646
4647         return 0;
4648 }
4649
4650 static int si_populate_phase_shedding_value(struct amdgpu_device *adev,
4651                                             const struct amdgpu_phase_shedding_limits_table *limits,
4652                                             u16 voltage, u32 sclk, u32 mclk,
4653                                             SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4654 {
4655         unsigned int i;
4656
4657         for (i = 0; i < limits->count; i++) {
4658                 if ((voltage <= limits->entries[i].voltage) &&
4659                     (sclk <= limits->entries[i].sclk) &&
4660                     (mclk <= limits->entries[i].mclk))
4661                         break;
4662         }
4663
4664         smc_voltage->phase_settings = (u8)i;
4665
4666         return 0;
4667 }
4668
4669 static int si_init_arb_table_index(struct amdgpu_device *adev)
4670 {
4671         struct si_power_info *si_pi = si_get_pi(adev);
4672         u32 tmp;
4673         int ret;
4674
4675         ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4676                                             &tmp, si_pi->sram_end);
4677         if (ret)
4678                 return ret;
4679
4680         tmp &= 0x00FFFFFF;
4681         tmp |= MC_CG_ARB_FREQ_F1 << 24;
4682
4683         return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start,
4684                                               tmp, si_pi->sram_end);
4685 }
4686
4687 static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
4688 {
4689         return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4690 }
4691
4692 static int si_reset_to_default(struct amdgpu_device *adev)
4693 {
4694         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4695                 0 : -EINVAL;
4696 }
4697
4698 static int si_force_switch_to_arb_f0(struct amdgpu_device *adev)
4699 {
4700         struct si_power_info *si_pi = si_get_pi(adev);
4701         u32 tmp;
4702         int ret;
4703
4704         ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4705                                             &tmp, si_pi->sram_end);
4706         if (ret)
4707                 return ret;
4708
4709         tmp = (tmp >> 24) & 0xff;
4710
4711         if (tmp == MC_CG_ARB_FREQ_F0)
4712                 return 0;
4713
4714         return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
4715 }
4716
4717 static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev,
4718                                             u32 engine_clock)
4719 {
4720         u32 dram_rows;
4721         u32 dram_refresh_rate;
4722         u32 mc_arb_rfsh_rate;
4723         u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4724
4725         if (tmp >= 4)
4726                 dram_rows = 16384;
4727         else
4728                 dram_rows = 1 << (tmp + 10);
4729
4730         dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4731         mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4732
4733         return mc_arb_rfsh_rate;
4734 }
4735
4736 static int si_populate_memory_timing_parameters(struct amdgpu_device *adev,
4737                                                 struct rv7xx_pl *pl,
4738                                                 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4739 {
4740         u32 dram_timing;
4741         u32 dram_timing2;
4742         u32 burst_time;
4743
4744         arb_regs->mc_arb_rfsh_rate =
4745                 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk);
4746
4747         amdgpu_atombios_set_engine_dram_timings(adev,
4748                                             pl->sclk,
4749                                             pl->mclk);
4750
4751         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
4752         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4753         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4754
4755         arb_regs->mc_arb_dram_timing  = cpu_to_be32(dram_timing);
4756         arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4757         arb_regs->mc_arb_burst_time = (u8)burst_time;
4758
4759         return 0;
4760 }
4761
4762 static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev,
4763                                                   struct amdgpu_ps *amdgpu_state,
4764                                                   unsigned int first_arb_set)
4765 {
4766         struct si_power_info *si_pi = si_get_pi(adev);
4767         struct  si_ps *state = si_get_ps(amdgpu_state);
4768         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4769         int i, ret = 0;
4770
4771         for (i = 0; i < state->performance_level_count; i++) {
4772                 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);
4773                 if (ret)
4774                         break;
4775                 ret = amdgpu_si_copy_bytes_to_smc(adev,
4776                                                   si_pi->arb_table_start +
4777                                                   offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4778                                                   sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4779                                                   (u8 *)&arb_regs,
4780                                                   sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4781                                                   si_pi->sram_end);
4782                 if (ret)
4783                         break;
4784         }
4785
4786         return ret;
4787 }
4788
4789 static int si_program_memory_timing_parameters(struct amdgpu_device *adev,
4790                                                struct amdgpu_ps *amdgpu_new_state)
4791 {
4792         return si_do_program_memory_timing_parameters(adev, amdgpu_new_state,
4793                                                       SISLANDS_DRIVER_STATE_ARB_INDEX);
4794 }
4795
4796 static int si_populate_initial_mvdd_value(struct amdgpu_device *adev,
4797                                           struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4798 {
4799         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4800         struct si_power_info *si_pi = si_get_pi(adev);
4801
4802         if (pi->mvdd_control)
4803                 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table,
4804                                                  si_pi->mvdd_bootup_value, voltage);
4805
4806         return 0;
4807 }
4808
4809 static int si_populate_smc_initial_state(struct amdgpu_device *adev,
4810                                          struct amdgpu_ps *amdgpu_initial_state,
4811                                          SISLANDS_SMC_STATETABLE *table)
4812 {
4813         struct  si_ps *initial_state = si_get_ps(amdgpu_initial_state);
4814         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4815         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4816         struct si_power_info *si_pi = si_get_pi(adev);
4817         u32 reg;
4818         int ret;
4819
4820         table->initialState.level.mclk.vDLL_CNTL =
4821                 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4822         table->initialState.level.mclk.vMCLK_PWRMGT_CNTL =
4823                 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4824         table->initialState.level.mclk.vMPLL_AD_FUNC_CNTL =
4825                 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4826         table->initialState.level.mclk.vMPLL_DQ_FUNC_CNTL =
4827                 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4828         table->initialState.level.mclk.vMPLL_FUNC_CNTL =
4829                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4830         table->initialState.level.mclk.vMPLL_FUNC_CNTL_1 =
4831                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4832         table->initialState.level.mclk.vMPLL_FUNC_CNTL_2 =
4833                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4834         table->initialState.level.mclk.vMPLL_SS =
4835                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4836         table->initialState.level.mclk.vMPLL_SS2 =
4837                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4838
4839         table->initialState.level.mclk.mclk_value =
4840                 cpu_to_be32(initial_state->performance_levels[0].mclk);
4841
4842         table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL =
4843                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4844         table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_2 =
4845                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4846         table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_3 =
4847                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4848         table->initialState.level.sclk.vCG_SPLL_FUNC_CNTL_4 =
4849                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4850         table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM =
4851                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4852         table->initialState.level.sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =
4853                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4854
4855         table->initialState.level.sclk.sclk_value =
4856                 cpu_to_be32(initial_state->performance_levels[0].sclk);
4857
4858         table->initialState.level.arbRefreshState =
4859                 SISLANDS_INITIAL_STATE_ARB_INDEX;
4860
4861         table->initialState.level.ACIndex = 0;
4862
4863         ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4864                                         initial_state->performance_levels[0].vddc,
4865                                         &table->initialState.level.vddc);
4866
4867         if (!ret) {
4868                 u16 std_vddc;
4869
4870                 ret = si_get_std_voltage_value(adev,
4871                                                &table->initialState.level.vddc,
4872                                                &std_vddc);
4873                 if (!ret)
4874                         si_populate_std_voltage_value(adev, std_vddc,
4875                                                       table->initialState.level.vddc.index,
4876                                                       &table->initialState.level.std_vddc);
4877         }
4878
4879         if (eg_pi->vddci_control)
4880                 si_populate_voltage_value(adev,
4881                                           &eg_pi->vddci_voltage_table,
4882                                           initial_state->performance_levels[0].vddci,
4883                                           &table->initialState.level.vddci);
4884
4885         if (si_pi->vddc_phase_shed_control)
4886                 si_populate_phase_shedding_value(adev,
4887                                                  &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4888                                                  initial_state->performance_levels[0].vddc,
4889                                                  initial_state->performance_levels[0].sclk,
4890                                                  initial_state->performance_levels[0].mclk,
4891                                                  &table->initialState.level.vddc);
4892
4893         si_populate_initial_mvdd_value(adev, &table->initialState.level.mvdd);
4894
4895         reg = CG_R(0xffff) | CG_L(0);
4896         table->initialState.level.aT = cpu_to_be32(reg);
4897         table->initialState.level.bSP = cpu_to_be32(pi->dsp);
4898         table->initialState.level.gen2PCIE = (u8)si_pi->boot_pcie_gen;
4899
4900         if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
4901                 table->initialState.level.strobeMode =
4902                         si_get_strobe_mode_settings(adev,
4903                                                     initial_state->performance_levels[0].mclk);
4904
4905                 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4906                         table->initialState.level.mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4907                 else
4908                         table->initialState.level.mcFlags =  0;
4909         }
4910
4911         table->initialState.levelCount = 1;
4912
4913         table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4914
4915         table->initialState.level.dpm2.MaxPS = 0;
4916         table->initialState.level.dpm2.NearTDPDec = 0;
4917         table->initialState.level.dpm2.AboveSafeInc = 0;
4918         table->initialState.level.dpm2.BelowSafeInc = 0;
4919         table->initialState.level.dpm2.PwrEfficiencyRatio = 0;
4920
4921         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4922         table->initialState.level.SQPowerThrottle = cpu_to_be32(reg);
4923
4924         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4925         table->initialState.level.SQPowerThrottle_2 = cpu_to_be32(reg);
4926
4927         return 0;
4928 }
4929
4930 static int si_populate_smc_acpi_state(struct amdgpu_device *adev,
4931                                       SISLANDS_SMC_STATETABLE *table)
4932 {
4933         struct rv7xx_power_info *pi = rv770_get_pi(adev);
4934         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4935         struct si_power_info *si_pi = si_get_pi(adev);
4936         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4937         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4938         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4939         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4940         u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4941         u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4942         u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4943         u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4944         u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4945         u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4946         u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4947         u32 reg;
4948         int ret;
4949
4950         table->ACPIState = table->initialState;
4951
4952         table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4953
4954         if (pi->acpi_vddc) {
4955                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4956                                                 pi->acpi_vddc, &table->ACPIState.level.vddc);
4957                 if (!ret) {
4958                         u16 std_vddc;
4959
4960                         ret = si_get_std_voltage_value(adev,
4961                                                        &table->ACPIState.level.vddc, &std_vddc);
4962                         if (!ret)
4963                                 si_populate_std_voltage_value(adev, std_vddc,
4964                                                               table->ACPIState.level.vddc.index,
4965                                                               &table->ACPIState.level.std_vddc);
4966                 }
4967                 table->ACPIState.level.gen2PCIE = si_pi->acpi_pcie_gen;
4968
4969                 if (si_pi->vddc_phase_shed_control) {
4970                         si_populate_phase_shedding_value(adev,
4971                                                          &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4972                                                          pi->acpi_vddc,
4973                                                          0,
4974                                                          0,
4975                                                          &table->ACPIState.level.vddc);
4976                 }
4977         } else {
4978                 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4979                                                 pi->min_vddc_in_table, &table->ACPIState.level.vddc);
4980                 if (!ret) {
4981                         u16 std_vddc;
4982
4983                         ret = si_get_std_voltage_value(adev,
4984                                                        &table->ACPIState.level.vddc, &std_vddc);
4985
4986                         if (!ret)
4987                                 si_populate_std_voltage_value(adev, std_vddc,
4988                                                               table->ACPIState.level.vddc.index,
4989                                                               &table->ACPIState.level.std_vddc);
4990                 }
4991                 table->ACPIState.level.gen2PCIE =
4992                         (u8)amdgpu_get_pcie_gen_support(adev,
4993                                                         si_pi->sys_pcie_mask,
4994                                                         si_pi->boot_pcie_gen,
4995                                                         AMDGPU_PCIE_GEN1);
4996
4997                 if (si_pi->vddc_phase_shed_control)
4998                         si_populate_phase_shedding_value(adev,
4999                                                          &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5000                                                          pi->min_vddc_in_table,
5001                                                          0,
5002                                                          0,
5003                                                          &table->ACPIState.level.vddc);
5004         }
5005
5006         if (pi->acpi_vddc) {
5007                 if (eg_pi->acpi_vddci)
5008                         si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5009                                                   eg_pi->acpi_vddci,
5010                                                   &table->ACPIState.level.vddci);
5011         }
5012
5013         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
5014         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5015
5016         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
5017
5018         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5019         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
5020
5021         table->ACPIState.level.mclk.vDLL_CNTL =
5022                 cpu_to_be32(dll_cntl);
5023         table->ACPIState.level.mclk.vMCLK_PWRMGT_CNTL =
5024                 cpu_to_be32(mclk_pwrmgt_cntl);
5025         table->ACPIState.level.mclk.vMPLL_AD_FUNC_CNTL =
5026                 cpu_to_be32(mpll_ad_func_cntl);
5027         table->ACPIState.level.mclk.vMPLL_DQ_FUNC_CNTL =
5028                 cpu_to_be32(mpll_dq_func_cntl);
5029         table->ACPIState.level.mclk.vMPLL_FUNC_CNTL =
5030                 cpu_to_be32(mpll_func_cntl);
5031         table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_1 =
5032                 cpu_to_be32(mpll_func_cntl_1);
5033         table->ACPIState.level.mclk.vMPLL_FUNC_CNTL_2 =
5034                 cpu_to_be32(mpll_func_cntl_2);
5035         table->ACPIState.level.mclk.vMPLL_SS =
5036                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
5037         table->ACPIState.level.mclk.vMPLL_SS2 =
5038                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
5039
5040         table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL =
5041                 cpu_to_be32(spll_func_cntl);
5042         table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_2 =
5043                 cpu_to_be32(spll_func_cntl_2);
5044         table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_3 =
5045                 cpu_to_be32(spll_func_cntl_3);
5046         table->ACPIState.level.sclk.vCG_SPLL_FUNC_CNTL_4 =
5047                 cpu_to_be32(spll_func_cntl_4);
5048
5049         table->ACPIState.level.mclk.mclk_value = 0;
5050         table->ACPIState.level.sclk.sclk_value = 0;
5051
5052         si_populate_mvdd_value(adev, 0, &table->ACPIState.level.mvdd);
5053
5054         if (eg_pi->dynamic_ac_timing)
5055                 table->ACPIState.level.ACIndex = 0;
5056
5057         table->ACPIState.level.dpm2.MaxPS = 0;
5058         table->ACPIState.level.dpm2.NearTDPDec = 0;
5059         table->ACPIState.level.dpm2.AboveSafeInc = 0;
5060         table->ACPIState.level.dpm2.BelowSafeInc = 0;
5061         table->ACPIState.level.dpm2.PwrEfficiencyRatio = 0;
5062
5063         reg = MIN_POWER_MASK | MAX_POWER_MASK;
5064         table->ACPIState.level.SQPowerThrottle = cpu_to_be32(reg);
5065
5066         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
5067         table->ACPIState.level.SQPowerThrottle_2 = cpu_to_be32(reg);
5068
5069         return 0;
5070 }
5071
5072 static int si_populate_ulv_state(struct amdgpu_device *adev,
5073                                  struct SISLANDS_SMC_SWSTATE_SINGLE *state)
5074 {
5075         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5076         struct si_power_info *si_pi = si_get_pi(adev);
5077         struct si_ulv_param *ulv = &si_pi->ulv;
5078         u32 sclk_in_sr = 1350; /* ??? */
5079         int ret;
5080
5081         ret = si_convert_power_level_to_smc(adev, &ulv->pl,
5082                                             &state->level);
5083         if (!ret) {
5084                 if (eg_pi->sclk_deep_sleep) {
5085                         if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5086                                 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5087                         else
5088                                 state->level.stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5089                 }
5090                 if (ulv->one_pcie_lane_in_ulv)
5091                         state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
5092                 state->level.arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
5093                 state->level.ACIndex = 1;
5094                 state->level.std_vddc = state->level.vddc;
5095                 state->levelCount = 1;
5096
5097                 state->flags |= PPSMC_SWSTATE_FLAG_DC;
5098         }
5099
5100         return ret;
5101 }
5102
5103 static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev)
5104 {
5105         struct si_power_info *si_pi = si_get_pi(adev);
5106         struct si_ulv_param *ulv = &si_pi->ulv;
5107         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
5108         int ret;
5109
5110         ret = si_populate_memory_timing_parameters(adev, &ulv->pl,
5111                                                    &arb_regs);
5112         if (ret)
5113                 return ret;
5114
5115         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
5116                                    ulv->volt_change_delay);
5117
5118         ret = amdgpu_si_copy_bytes_to_smc(adev,
5119                                           si_pi->arb_table_start +
5120                                           offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
5121                                           sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
5122                                           (u8 *)&arb_regs,
5123                                           sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
5124                                           si_pi->sram_end);
5125
5126         return ret;
5127 }
5128
5129 static void si_get_mvdd_configuration(struct amdgpu_device *adev)
5130 {
5131         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5132
5133         pi->mvdd_split_frequency = 30000;
5134 }
5135
5136 static int si_init_smc_table(struct amdgpu_device *adev)
5137 {
5138         struct si_power_info *si_pi = si_get_pi(adev);
5139         struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
5140         const struct si_ulv_param *ulv = &si_pi->ulv;
5141         SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;
5142         int ret;
5143         u32 lane_width;
5144         u32 vr_hot_gpio;
5145
5146         si_populate_smc_voltage_tables(adev, table);
5147
5148         switch (adev->pm.int_thermal_type) {
5149         case THERMAL_TYPE_SI:
5150         case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
5151                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
5152                 break;
5153         case THERMAL_TYPE_NONE:
5154                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
5155                 break;
5156         default:
5157                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
5158                 break;
5159         }
5160
5161         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
5162                 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
5163
5164         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
5165                 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819))
5166                         table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
5167         }
5168
5169         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
5170                 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
5171
5172         if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5173                 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
5174
5175         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
5176                 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
5177
5178         if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
5179                 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
5180                 vr_hot_gpio = adev->pm.dpm.backbias_response_time;
5181                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
5182                                            vr_hot_gpio);
5183         }
5184
5185         ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table);
5186         if (ret)
5187                 return ret;
5188
5189         ret = si_populate_smc_acpi_state(adev, table);
5190         if (ret)
5191                 return ret;
5192
5193         table->driverState.flags = table->initialState.flags;
5194         table->driverState.levelCount = table->initialState.levelCount;
5195         table->driverState.levels[0] = table->initialState.level;
5196
5197         ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state,
5198                                                      SISLANDS_INITIAL_STATE_ARB_INDEX);
5199         if (ret)
5200                 return ret;
5201
5202         if (ulv->supported && ulv->pl.vddc) {
5203                 ret = si_populate_ulv_state(adev, &table->ULVState);
5204                 if (ret)
5205                         return ret;
5206
5207                 ret = si_program_ulv_memory_timing_parameters(adev);
5208                 if (ret)
5209                         return ret;
5210
5211                 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
5212                 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
5213
5214                 lane_width = amdgpu_get_pcie_lanes(adev);
5215                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5216         } else {
5217                 table->ULVState = table->initialState;
5218         }
5219
5220         return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start,
5221                                            (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
5222                                            si_pi->sram_end);
5223 }
5224
5225 static int si_calculate_sclk_params(struct amdgpu_device *adev,
5226                                     u32 engine_clock,
5227                                     SISLANDS_SMC_SCLK_VALUE *sclk)
5228 {
5229         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5230         struct si_power_info *si_pi = si_get_pi(adev);
5231         struct atom_clock_dividers dividers;
5232         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5233         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5234         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5235         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5236         u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
5237         u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
5238         u64 tmp;
5239         u32 reference_clock = adev->clock.spll.reference_freq;
5240         u32 reference_divider;
5241         u32 fbdiv;
5242         int ret;
5243
5244         ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
5245                                              engine_clock, false, &dividers);
5246         if (ret)
5247                 return ret;
5248
5249         reference_divider = 1 + dividers.ref_div;
5250
5251         tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
5252         do_div(tmp, reference_clock);
5253         fbdiv = (u32) tmp;
5254
5255         spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
5256         spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
5257         spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
5258
5259         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5260         spll_func_cntl_2 |= SCLK_MUX_SEL(2);
5261
5262         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
5263         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
5264         spll_func_cntl_3 |= SPLL_DITHEN;
5265
5266         if (pi->sclk_ss) {
5267                 struct amdgpu_atom_ss ss;
5268                 u32 vco_freq = engine_clock * dividers.post_div;
5269
5270                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5271                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
5272                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
5273                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
5274
5275                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
5276                         cg_spll_spread_spectrum |= CLK_S(clk_s);
5277                         cg_spll_spread_spectrum |= SSEN;
5278
5279                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
5280                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
5281                 }
5282         }
5283
5284         sclk->sclk_value = engine_clock;
5285         sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
5286         sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
5287         sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
5288         sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
5289         sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
5290         sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
5291
5292         return 0;
5293 }
5294
5295 static int si_populate_sclk_value(struct amdgpu_device *adev,
5296                                   u32 engine_clock,
5297                                   SISLANDS_SMC_SCLK_VALUE *sclk)
5298 {
5299         SISLANDS_SMC_SCLK_VALUE sclk_tmp;
5300         int ret;
5301
5302         ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp);
5303         if (!ret) {
5304                 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
5305                 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
5306                 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
5307                 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
5308                 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
5309                 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
5310                 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
5311         }
5312
5313         return ret;
5314 }
5315
5316 static int si_populate_mclk_value(struct amdgpu_device *adev,
5317                                   u32 engine_clock,
5318                                   u32 memory_clock,
5319                                   SISLANDS_SMC_MCLK_VALUE *mclk,
5320                                   bool strobe_mode,
5321                                   bool dll_state_on)
5322 {
5323         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5324         struct si_power_info *si_pi = si_get_pi(adev);
5325         u32  dll_cntl = si_pi->clock_registers.dll_cntl;
5326         u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5327         u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5328         u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5329         u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5330         u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5331         u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5332         u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;
5333         u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;
5334         struct atom_mpll_param mpll_param;
5335         int ret;
5336
5337         ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
5338         if (ret)
5339                 return ret;
5340
5341         mpll_func_cntl &= ~BWCTRL_MASK;
5342         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
5343
5344         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
5345         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
5346                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
5347
5348         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
5349         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
5350
5351         if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5352                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
5353                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
5354                         YCLK_POST_DIV(mpll_param.post_div);
5355         }
5356
5357         if (pi->mclk_ss) {
5358                 struct amdgpu_atom_ss ss;
5359                 u32 freq_nom;
5360                 u32 tmp;
5361                 u32 reference_clock = adev->clock.mpll.reference_freq;
5362
5363                 if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5364                         freq_nom = memory_clock * 4;
5365                 else
5366                         freq_nom = memory_clock * 2;
5367
5368                 tmp = freq_nom / reference_clock;
5369                 tmp = tmp * tmp;
5370                 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5371                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
5372                         u32 clks = reference_clock * 5 / ss.rate;
5373                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
5374
5375                         mpll_ss1 &= ~CLKV_MASK;
5376                         mpll_ss1 |= CLKV(clkv);
5377
5378                         mpll_ss2 &= ~CLKS_MASK;
5379                         mpll_ss2 |= CLKS(clks);
5380                 }
5381         }
5382
5383         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
5384         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
5385
5386         if (dll_state_on)
5387                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
5388         else
5389                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5390
5391         mclk->mclk_value = cpu_to_be32(memory_clock);
5392         mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5393         mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5394         mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5395         mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5396         mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5397         mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5398         mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5399         mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5400         mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5401
5402         return 0;
5403 }
5404
5405 static void si_populate_smc_sp(struct amdgpu_device *adev,
5406                                struct amdgpu_ps *amdgpu_state,
5407                                SISLANDS_SMC_SWSTATE *smc_state)
5408 {
5409         struct  si_ps *ps = si_get_ps(amdgpu_state);
5410         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5411         int i;
5412
5413         for (i = 0; i < ps->performance_level_count - 1; i++)
5414                 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5415
5416         smc_state->levels[ps->performance_level_count - 1].bSP =
5417                 cpu_to_be32(pi->psp);
5418 }
5419
5420 static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
5421                                          struct rv7xx_pl *pl,
5422                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5423 {
5424         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5425         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5426         struct si_power_info *si_pi = si_get_pi(adev);
5427         int ret;
5428         bool dll_state_on;
5429         u16 std_vddc;
5430         bool gmc_pg = false;
5431
5432         if (eg_pi->pcie_performance_request &&
5433             (si_pi->force_pcie_gen != AMDGPU_PCIE_GEN_INVALID))
5434                 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5435         else
5436                 level->gen2PCIE = (u8)pl->pcie_gen;
5437
5438         ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk);
5439         if (ret)
5440                 return ret;
5441
5442         level->mcFlags =  0;
5443
5444         if (pi->mclk_stutter_mode_threshold &&
5445             (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5446             !eg_pi->uvd_enabled &&
5447             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5448             (adev->pm.dpm.new_active_crtc_count <= 2)) {
5449                 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5450
5451                 if (gmc_pg)
5452                         level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5453         }
5454
5455         if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5456                 if (pl->mclk > pi->mclk_edc_enable_threshold)
5457                         level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5458
5459                 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5460                         level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5461
5462                 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk);
5463
5464                 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5465                         if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5466                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5467                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5468                         else
5469                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5470                 } else {
5471                         dll_state_on = false;
5472                 }
5473         } else {
5474                 level->strobeMode = si_get_strobe_mode_settings(adev,
5475                                                                 pl->mclk);
5476
5477                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5478         }
5479
5480         ret = si_populate_mclk_value(adev,
5481                                      pl->sclk,
5482                                      pl->mclk,
5483                                      &level->mclk,
5484                                      (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5485         if (ret)
5486                 return ret;
5487
5488         ret = si_populate_voltage_value(adev,
5489                                         &eg_pi->vddc_voltage_table,
5490                                         pl->vddc, &level->vddc);
5491         if (ret)
5492                 return ret;
5493
5494
5495         ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc);
5496         if (ret)
5497                 return ret;
5498
5499         ret = si_populate_std_voltage_value(adev, std_vddc,
5500                                             level->vddc.index, &level->std_vddc);
5501         if (ret)
5502                 return ret;
5503
5504         if (eg_pi->vddci_control) {
5505                 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5506                                                 pl->vddci, &level->vddci);
5507                 if (ret)
5508                         return ret;
5509         }
5510
5511         if (si_pi->vddc_phase_shed_control) {
5512                 ret = si_populate_phase_shedding_value(adev,
5513                                                        &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5514                                                        pl->vddc,
5515                                                        pl->sclk,
5516                                                        pl->mclk,
5517                                                        &level->vddc);
5518                 if (ret)
5519                         return ret;
5520         }
5521
5522         level->MaxPoweredUpCU = si_pi->max_cu;
5523
5524         ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd);
5525
5526         return ret;
5527 }
5528
5529 static int si_populate_smc_t(struct amdgpu_device *adev,
5530                              struct amdgpu_ps *amdgpu_state,
5531                              SISLANDS_SMC_SWSTATE *smc_state)
5532 {
5533         struct rv7xx_power_info *pi = rv770_get_pi(adev);
5534         struct  si_ps *state = si_get_ps(amdgpu_state);
5535         u32 a_t;
5536         u32 t_l, t_h;
5537         u32 high_bsp;
5538         int i, ret;
5539
5540         if (state->performance_level_count >= 9)
5541                 return -EINVAL;
5542
5543         if (state->performance_level_count < 2) {
5544                 a_t = CG_R(0xffff) | CG_L(0);
5545                 smc_state->levels[0].aT = cpu_to_be32(a_t);
5546                 return 0;
5547         }
5548
5549         smc_state->levels[0].aT = cpu_to_be32(0);
5550
5551         for (i = 0; i <= state->performance_level_count - 2; i++) {
5552                 ret = r600_calculate_at(
5553                         (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5554                         100 * R600_AH_DFLT,
5555                         state->performance_levels[i + 1].sclk,
5556                         state->performance_levels[i].sclk,
5557                         &t_l,
5558                         &t_h);
5559
5560                 if (ret) {
5561                         t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5562                         t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5563                 }
5564
5565                 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5566                 a_t |= CG_R(t_l * pi->bsp / 20000);
5567                 smc_state->levels[i].aT = cpu_to_be32(a_t);
5568
5569                 high_bsp = (i == state->performance_level_count - 2) ?
5570                         pi->pbsp : pi->bsp;
5571                 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5572                 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5573         }
5574
5575         return 0;
5576 }
5577
5578 static int si_disable_ulv(struct amdgpu_device *adev)
5579 {
5580         struct si_power_info *si_pi = si_get_pi(adev);
5581         struct si_ulv_param *ulv = &si_pi->ulv;
5582
5583         if (ulv->supported)
5584                 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
5585                         0 : -EINVAL;
5586
5587         return 0;
5588 }
5589
5590 static bool si_is_state_ulv_compatible(struct amdgpu_device *adev,
5591                                        struct amdgpu_ps *amdgpu_state)
5592 {
5593         const struct si_power_info *si_pi = si_get_pi(adev);
5594         const struct si_ulv_param *ulv = &si_pi->ulv;
5595         const struct  si_ps *state = si_get_ps(amdgpu_state);
5596         int i;
5597
5598         if (state->performance_levels[0].mclk != ulv->pl.mclk)
5599                 return false;
5600
5601         /* XXX validate against display requirements! */
5602
5603         for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5604                 if (adev->clock.current_dispclk <=
5605                     adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5606                         if (ulv->pl.vddc <
5607                             adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5608                                 return false;
5609                 }
5610         }
5611
5612         if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0))
5613                 return false;
5614
5615         return true;
5616 }
5617
5618 static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev,
5619                                                        struct amdgpu_ps *amdgpu_new_state)
5620 {
5621         const struct si_power_info *si_pi = si_get_pi(adev);
5622         const struct si_ulv_param *ulv = &si_pi->ulv;
5623
5624         if (ulv->supported) {
5625                 if (si_is_state_ulv_compatible(adev, amdgpu_new_state))
5626                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
5627                                 0 : -EINVAL;
5628         }
5629         return 0;
5630 }
5631
5632 static int si_convert_power_state_to_smc(struct amdgpu_device *adev,
5633                                          struct amdgpu_ps *amdgpu_state,
5634                                          SISLANDS_SMC_SWSTATE *smc_state)
5635 {
5636         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5637         struct ni_power_info *ni_pi = ni_get_pi(adev);
5638         struct si_power_info *si_pi = si_get_pi(adev);
5639         struct  si_ps *state = si_get_ps(amdgpu_state);
5640         int i, ret;
5641         u32 threshold;
5642         u32 sclk_in_sr = 1350; /* ??? */
5643
5644         if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5645                 return -EINVAL;
5646
5647         threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5648
5649         if (amdgpu_state->vclk && amdgpu_state->dclk) {
5650                 eg_pi->uvd_enabled = true;
5651                 if (eg_pi->smu_uvd_hs)
5652                         smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5653         } else {
5654                 eg_pi->uvd_enabled = false;
5655         }
5656
5657         if (state->dc_compatible)
5658                 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5659
5660         smc_state->levelCount = 0;
5661         for (i = 0; i < state->performance_level_count; i++) {
5662                 if (eg_pi->sclk_deep_sleep) {
5663                         if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5664                                 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5665                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5666                                 else
5667                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5668                         }
5669                 }
5670
5671                 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i],
5672                                                     &smc_state->levels[i]);
5673                 smc_state->levels[i].arbRefreshState =
5674                         (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5675
5676                 if (ret)
5677                         return ret;
5678
5679                 if (ni_pi->enable_power_containment)
5680                         smc_state->levels[i].displayWatermark =
5681                                 (state->performance_levels[i].sclk < threshold) ?
5682                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5683                 else
5684                         smc_state->levels[i].displayWatermark = (i < 2) ?
5685                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5686
5687                 if (eg_pi->dynamic_ac_timing)
5688                         smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5689                 else
5690                         smc_state->levels[i].ACIndex = 0;
5691
5692                 smc_state->levelCount++;
5693         }
5694
5695         si_write_smc_soft_register(adev,
5696                                    SI_SMC_SOFT_REGISTER_watermark_threshold,
5697                                    threshold / 512);
5698
5699         si_populate_smc_sp(adev, amdgpu_state, smc_state);
5700
5701         ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state);
5702         if (ret)
5703                 ni_pi->enable_power_containment = false;
5704
5705         ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state);
5706         if (ret)
5707                 ni_pi->enable_sq_ramping = false;
5708
5709         return si_populate_smc_t(adev, amdgpu_state, smc_state);
5710 }
5711
5712 static int si_upload_sw_state(struct amdgpu_device *adev,
5713                               struct amdgpu_ps *amdgpu_new_state)
5714 {
5715         struct si_power_info *si_pi = si_get_pi(adev);
5716         struct  si_ps *new_state = si_get_ps(amdgpu_new_state);
5717         int ret;
5718         u32 address = si_pi->state_table_start +
5719                 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5720         SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5721         size_t state_size = struct_size(smc_state, levels,
5722                                         new_state->performance_level_count);
5723         memset(smc_state, 0, state_size);
5724
5725         ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state);
5726         if (ret)
5727                 return ret;
5728
5729         return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5730                                            state_size, si_pi->sram_end);
5731 }
5732
5733 static int si_upload_ulv_state(struct amdgpu_device *adev)
5734 {
5735         struct si_power_info *si_pi = si_get_pi(adev);
5736         struct si_ulv_param *ulv = &si_pi->ulv;
5737         int ret = 0;
5738
5739         if (ulv->supported && ulv->pl.vddc) {
5740                 u32 address = si_pi->state_table_start +
5741                         offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5742                 struct SISLANDS_SMC_SWSTATE_SINGLE *smc_state = &si_pi->smc_statetable.ULVState;
5743                 u32 state_size = sizeof(struct SISLANDS_SMC_SWSTATE_SINGLE);
5744
5745                 memset(smc_state, 0, state_size);
5746
5747                 ret = si_populate_ulv_state(adev, smc_state);
5748                 if (!ret)
5749                         ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5750                                                           state_size, si_pi->sram_end);
5751         }
5752
5753         return ret;
5754 }
5755
5756 static int si_upload_smc_data(struct amdgpu_device *adev)
5757 {
5758         struct amdgpu_crtc *amdgpu_crtc = NULL;
5759         int i;
5760
5761         if (adev->pm.dpm.new_active_crtc_count == 0)
5762                 return 0;
5763
5764         for (i = 0; i < adev->mode_info.num_crtc; i++) {
5765                 if (adev->pm.dpm.new_active_crtcs & (1 << i)) {
5766                         amdgpu_crtc = adev->mode_info.crtcs[i];
5767                         break;
5768                 }
5769         }
5770
5771         if (amdgpu_crtc == NULL)
5772                 return 0;
5773
5774         if (amdgpu_crtc->line_time <= 0)
5775                 return 0;
5776
5777         if (si_write_smc_soft_register(adev,
5778                                        SI_SMC_SOFT_REGISTER_crtc_index,
5779                                        amdgpu_crtc->crtc_id) != PPSMC_Result_OK)
5780                 return 0;
5781
5782         if (si_write_smc_soft_register(adev,
5783                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5784                                        amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5785                 return 0;
5786
5787         if (si_write_smc_soft_register(adev,
5788                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5789                                        amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5790                 return 0;
5791
5792         return 0;
5793 }
5794
5795 static int si_set_mc_special_registers(struct amdgpu_device *adev,
5796                                        struct si_mc_reg_table *table)
5797 {
5798         u8 i, j, k;
5799         u32 temp_reg;
5800
5801         for (i = 0, j = table->last; i < table->last; i++) {
5802                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5803                         return -EINVAL;
5804                 switch (table->mc_reg_address[i].s1) {
5805                 case MC_SEQ_MISC1:
5806                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
5807                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS;
5808                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP;
5809                         for (k = 0; k < table->num_entries; k++)
5810                                 table->mc_reg_table_entry[k].mc_data[j] =
5811                                         ((temp_reg & 0xffff0000)) |
5812                                         ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5813                         j++;
5814
5815                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5816                                 return -EINVAL;
5817                         temp_reg = RREG32(MC_PMG_CMD_MRS);
5818                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
5819                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
5820                         for (k = 0; k < table->num_entries; k++) {
5821                                 table->mc_reg_table_entry[k].mc_data[j] =
5822                                         (temp_reg & 0xffff0000) |
5823                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5824                                 if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
5825                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5826                         }
5827                         j++;
5828
5829                         if (adev->gmc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
5830                                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5831                                         return -EINVAL;
5832                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
5833                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
5834                                 for (k = 0; k < table->num_entries; k++)
5835                                         table->mc_reg_table_entry[k].mc_data[j] =
5836                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5837                                 j++;
5838                         }
5839                         break;
5840                 case MC_SEQ_RESERVE_M:
5841                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
5842                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;
5843                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;
5844                         for(k = 0; k < table->num_entries; k++)
5845                                 table->mc_reg_table_entry[k].mc_data[j] =
5846                                         (temp_reg & 0xffff0000) |
5847                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5848                         j++;
5849                         break;
5850                 default:
5851                         break;
5852                 }
5853         }
5854
5855         table->last = j;
5856
5857         return 0;
5858 }
5859
5860 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5861 {
5862         bool result = true;
5863         switch (in_reg) {
5864         case  MC_SEQ_RAS_TIMING:
5865                 *out_reg = MC_SEQ_RAS_TIMING_LP;
5866                 break;
5867         case MC_SEQ_CAS_TIMING:
5868                 *out_reg = MC_SEQ_CAS_TIMING_LP;
5869                 break;
5870         case MC_SEQ_MISC_TIMING:
5871                 *out_reg = MC_SEQ_MISC_TIMING_LP;
5872                 break;
5873         case MC_SEQ_MISC_TIMING2:
5874                 *out_reg = MC_SEQ_MISC_TIMING2_LP;
5875                 break;
5876         case MC_SEQ_RD_CTL_D0:
5877                 *out_reg = MC_SEQ_RD_CTL_D0_LP;
5878                 break;
5879         case MC_SEQ_RD_CTL_D1:
5880                 *out_reg = MC_SEQ_RD_CTL_D1_LP;
5881                 break;
5882         case MC_SEQ_WR_CTL_D0:
5883                 *out_reg = MC_SEQ_WR_CTL_D0_LP;
5884                 break;
5885         case MC_SEQ_WR_CTL_D1:
5886                 *out_reg = MC_SEQ_WR_CTL_D1_LP;
5887                 break;
5888         case MC_PMG_CMD_EMRS:
5889                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP;
5890                 break;
5891         case MC_PMG_CMD_MRS:
5892                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP;
5893                 break;
5894         case MC_PMG_CMD_MRS1:
5895                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP;
5896                 break;
5897         case MC_SEQ_PMG_TIMING:
5898                 *out_reg = MC_SEQ_PMG_TIMING_LP;
5899                 break;
5900         case MC_PMG_CMD_MRS2:
5901                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP;
5902                 break;
5903         case MC_SEQ_WR_CTL_2:
5904                 *out_reg = MC_SEQ_WR_CTL_2_LP;
5905                 break;
5906         default:
5907                 result = false;
5908                 break;
5909         }
5910
5911         return result;
5912 }
5913
5914 static void si_set_valid_flag(struct si_mc_reg_table *table)
5915 {
5916         u8 i, j;
5917
5918         for (i = 0; i < table->last; i++) {
5919                 for (j = 1; j < table->num_entries; j++) {
5920                         if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5921                                 table->valid_flag |= 1 << i;
5922                                 break;
5923                         }
5924                 }
5925         }
5926 }
5927
5928 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5929 {
5930         u32 i;
5931         u16 address;
5932
5933         for (i = 0; i < table->last; i++)
5934                 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5935                         address : table->mc_reg_address[i].s1;
5936
5937 }
5938
5939 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5940                                       struct si_mc_reg_table *si_table)
5941 {
5942         u8 i, j;
5943
5944         if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5945                 return -EINVAL;
5946         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5947                 return -EINVAL;
5948
5949         for (i = 0; i < table->last; i++)
5950                 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5951         si_table->last = table->last;
5952
5953         for (i = 0; i < table->num_entries; i++) {
5954                 si_table->mc_reg_table_entry[i].mclk_max =
5955                         table->mc_reg_table_entry[i].mclk_max;
5956                 for (j = 0; j < table->last; j++) {
5957                         si_table->mc_reg_table_entry[i].mc_data[j] =
5958                                 table->mc_reg_table_entry[i].mc_data[j];
5959                 }
5960         }
5961         si_table->num_entries = table->num_entries;
5962
5963         return 0;
5964 }
5965
5966 static int si_initialize_mc_reg_table(struct amdgpu_device *adev)
5967 {
5968         struct si_power_info *si_pi = si_get_pi(adev);
5969         struct atom_mc_reg_table *table;
5970         struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5971         u8 module_index = rv770_get_memory_module_index(adev);
5972         int ret;
5973
5974         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5975         if (!table)
5976                 return -ENOMEM;
5977
5978         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5979         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5980         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5981         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5982         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5983         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5984         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5985         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5986         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5987         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5988         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5989         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5990         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5991         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5992
5993         ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
5994         if (ret)
5995                 goto init_mc_done;
5996
5997         ret = si_copy_vbios_mc_reg_table(table, si_table);
5998         if (ret)
5999                 goto init_mc_done;
6000
6001         si_set_s0_mc_reg_index(si_table);
6002
6003         ret = si_set_mc_special_registers(adev, si_table);
6004         if (ret)
6005                 goto init_mc_done;
6006
6007         si_set_valid_flag(si_table);
6008
6009 init_mc_done:
6010         kfree(table);
6011
6012         return ret;
6013
6014 }
6015
6016 static void si_populate_mc_reg_addresses(struct amdgpu_device *adev,
6017                                          SMC_SIslands_MCRegisters *mc_reg_table)
6018 {
6019         struct si_power_info *si_pi = si_get_pi(adev);
6020         u32 i, j;
6021
6022         for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
6023                 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
6024                         if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6025                                 break;
6026                         mc_reg_table->address[i].s0 =
6027                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
6028                         mc_reg_table->address[i].s1 =
6029                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
6030                         i++;
6031                 }
6032         }
6033         mc_reg_table->last = (u8)i;
6034 }
6035
6036 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
6037                                     SMC_SIslands_MCRegisterSet *data,
6038                                     u32 num_entries, u32 valid_flag)
6039 {
6040         u32 i, j;
6041
6042         for(i = 0, j = 0; j < num_entries; j++) {
6043                 if (valid_flag & (1 << j)) {
6044                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
6045                         i++;
6046                 }
6047         }
6048 }
6049
6050 static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
6051                                                  struct rv7xx_pl *pl,
6052                                                  SMC_SIslands_MCRegisterSet *mc_reg_table_data)
6053 {
6054         struct si_power_info *si_pi = si_get_pi(adev);
6055         u32 i = 0;
6056
6057         for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
6058                 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
6059                         break;
6060         }
6061
6062         if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
6063                 --i;
6064
6065         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
6066                                 mc_reg_table_data, si_pi->mc_reg_table.last,
6067                                 si_pi->mc_reg_table.valid_flag);
6068 }
6069
6070 static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
6071                                            struct amdgpu_ps *amdgpu_state,
6072                                            SMC_SIslands_MCRegisters *mc_reg_table)
6073 {
6074         struct si_ps *state = si_get_ps(amdgpu_state);
6075         int i;
6076
6077         for (i = 0; i < state->performance_level_count; i++) {
6078                 si_convert_mc_reg_table_entry_to_smc(adev,
6079                                                      &state->performance_levels[i],
6080                                                      &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
6081         }
6082 }
6083
6084 static int si_populate_mc_reg_table(struct amdgpu_device *adev,
6085                                     struct amdgpu_ps *amdgpu_boot_state)
6086 {
6087         struct  si_ps *boot_state = si_get_ps(amdgpu_boot_state);
6088         struct si_power_info *si_pi = si_get_pi(adev);
6089         struct si_ulv_param *ulv = &si_pi->ulv;
6090         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6091
6092         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6093
6094         si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1);
6095
6096         si_populate_mc_reg_addresses(adev, smc_mc_reg_table);
6097
6098         si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0],
6099                                              &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
6100
6101         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6102                                 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
6103                                 si_pi->mc_reg_table.last,
6104                                 si_pi->mc_reg_table.valid_flag);
6105
6106         if (ulv->supported && ulv->pl.vddc != 0)
6107                 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl,
6108                                                      &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
6109         else
6110                 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6111                                         &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
6112                                         si_pi->mc_reg_table.last,
6113                                         si_pi->mc_reg_table.valid_flag);
6114
6115         si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table);
6116
6117         return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,
6118                                            (u8 *)smc_mc_reg_table,
6119                                            sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
6120 }
6121
6122 static int si_upload_mc_reg_table(struct amdgpu_device *adev,
6123                                   struct amdgpu_ps *amdgpu_new_state)
6124 {
6125         struct si_ps *new_state = si_get_ps(amdgpu_new_state);
6126         struct si_power_info *si_pi = si_get_pi(adev);
6127         u32 address = si_pi->mc_reg_table_start +
6128                 offsetof(SMC_SIslands_MCRegisters,
6129                          data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
6130         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6131
6132         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6133
6134         si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);
6135
6136         return amdgpu_si_copy_bytes_to_smc(adev, address,
6137                                            (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
6138                                            sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
6139                                            si_pi->sram_end);
6140 }
6141
6142 static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
6143 {
6144         if (enable)
6145                 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
6146         else
6147                 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
6148 }
6149
6150 static enum amdgpu_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev,
6151                                                       struct amdgpu_ps *amdgpu_state)
6152 {
6153         struct si_ps *state = si_get_ps(amdgpu_state);
6154         int i;
6155         u16 pcie_speed, max_speed = 0;
6156
6157         for (i = 0; i < state->performance_level_count; i++) {
6158                 pcie_speed = state->performance_levels[i].pcie_gen;
6159                 if (max_speed < pcie_speed)
6160                         max_speed = pcie_speed;
6161         }
6162         return max_speed;
6163 }
6164
6165 static u16 si_get_current_pcie_speed(struct amdgpu_device *adev)
6166 {
6167         u32 speed_cntl;
6168
6169         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
6170         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
6171
6172         return (u16)speed_cntl;
6173 }
6174
6175 static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
6176                                                              struct amdgpu_ps *amdgpu_new_state,
6177                                                              struct amdgpu_ps *amdgpu_current_state)
6178 {
6179         struct si_power_info *si_pi = si_get_pi(adev);
6180         enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6181         enum amdgpu_pcie_gen current_link_speed;
6182
6183         if (si_pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
6184                 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state);
6185         else
6186                 current_link_speed = si_pi->force_pcie_gen;
6187
6188         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
6189         si_pi->pspp_notify_required = false;
6190         if (target_link_speed > current_link_speed) {
6191                 switch (target_link_speed) {
6192 #if defined(CONFIG_ACPI)
6193                 case AMDGPU_PCIE_GEN3:
6194                         if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
6195                                 break;
6196                         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
6197                         if (current_link_speed == AMDGPU_PCIE_GEN2)
6198                                 break;
6199                         fallthrough;
6200                 case AMDGPU_PCIE_GEN2:
6201                         if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
6202                                 break;
6203                         fallthrough;
6204 #endif
6205                 default:
6206                         si_pi->force_pcie_gen = si_get_current_pcie_speed(adev);
6207                         break;
6208                 }
6209         } else {
6210                 if (target_link_speed < current_link_speed)
6211                         si_pi->pspp_notify_required = true;
6212         }
6213 }
6214
6215 static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
6216                                                            struct amdgpu_ps *amdgpu_new_state,
6217                                                            struct amdgpu_ps *amdgpu_current_state)
6218 {
6219         struct si_power_info *si_pi = si_get_pi(adev);
6220         enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6221         u8 request;
6222
6223         if (si_pi->pspp_notify_required) {
6224                 if (target_link_speed == AMDGPU_PCIE_GEN3)
6225                         request = PCIE_PERF_REQ_PECI_GEN3;
6226                 else if (target_link_speed == AMDGPU_PCIE_GEN2)
6227                         request = PCIE_PERF_REQ_PECI_GEN2;
6228                 else
6229                         request = PCIE_PERF_REQ_PECI_GEN1;
6230
6231                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
6232                     (si_get_current_pcie_speed(adev) > 0))
6233                         return;
6234
6235 #if defined(CONFIG_ACPI)
6236                 amdgpu_acpi_pcie_performance_request(adev, request, false);
6237 #endif
6238         }
6239 }
6240
6241 #if 0
6242 static int si_ds_request(struct amdgpu_device *adev,
6243                          bool ds_status_on, u32 count_write)
6244 {
6245         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6246
6247         if (eg_pi->sclk_deep_sleep) {
6248                 if (ds_status_on)
6249                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
6250                                 PPSMC_Result_OK) ?
6251                                 0 : -EINVAL;
6252                 else
6253                         return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
6254                                 PPSMC_Result_OK) ? 0 : -EINVAL;
6255         }
6256         return 0;
6257 }
6258 #endif
6259
6260 static void si_set_max_cu_value(struct amdgpu_device *adev)
6261 {
6262         struct si_power_info *si_pi = si_get_pi(adev);
6263
6264         if (adev->asic_type == CHIP_VERDE) {
6265                 switch (adev->pdev->device) {
6266                 case 0x6820:
6267                 case 0x6825:
6268                 case 0x6821:
6269                 case 0x6823:
6270                 case 0x6827:
6271                         si_pi->max_cu = 10;
6272                         break;
6273                 case 0x682D:
6274                 case 0x6824:
6275                 case 0x682F:
6276                 case 0x6826:
6277                         si_pi->max_cu = 8;
6278                         break;
6279                 case 0x6828:
6280                 case 0x6830:
6281                 case 0x6831:
6282                 case 0x6838:
6283                 case 0x6839:
6284                 case 0x683D:
6285                         si_pi->max_cu = 10;
6286                         break;
6287                 case 0x683B:
6288                 case 0x683F:
6289                 case 0x6829:
6290                         si_pi->max_cu = 8;
6291                         break;
6292                 default:
6293                         si_pi->max_cu = 0;
6294                         break;
6295                 }
6296         } else {
6297                 si_pi->max_cu = 0;
6298         }
6299 }
6300
6301 static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev,
6302                                                              struct amdgpu_clock_voltage_dependency_table *table)
6303 {
6304         u32 i;
6305         int j;
6306         u16 leakage_voltage;
6307
6308         if (table) {
6309                 for (i = 0; i < table->count; i++) {
6310                         switch (si_get_leakage_voltage_from_leakage_index(adev,
6311                                                                           table->entries[i].v,
6312                                                                           &leakage_voltage)) {
6313                         case 0:
6314                                 table->entries[i].v = leakage_voltage;
6315                                 break;
6316                         case -EAGAIN:
6317                                 return -EINVAL;
6318                         case -EINVAL:
6319                         default:
6320                                 break;
6321                         }
6322                 }
6323
6324                 for (j = (table->count - 2); j >= 0; j--) {
6325                         table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
6326                                 table->entries[j].v : table->entries[j + 1].v;
6327                 }
6328         }
6329         return 0;
6330 }
6331
6332 static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev)
6333 {
6334         int ret = 0;
6335
6336         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6337                                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
6338         if (ret)
6339                 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n");
6340         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6341                                                                 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
6342         if (ret)
6343                 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n");
6344         ret = si_patch_single_dependency_table_based_on_leakage(adev,
6345                                                                 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
6346         if (ret)
6347                 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n");
6348         return ret;
6349 }
6350
6351 static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev,
6352                                           struct amdgpu_ps *amdgpu_new_state,
6353                                           struct amdgpu_ps *amdgpu_current_state)
6354 {
6355         u32 lane_width;
6356         u32 new_lane_width =
6357                 ((amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
6358         u32 current_lane_width =
6359                 ((amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
6360
6361         if (new_lane_width != current_lane_width) {
6362                 amdgpu_set_pcie_lanes(adev, new_lane_width);
6363                 lane_width = amdgpu_get_pcie_lanes(adev);
6364                 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
6365         }
6366 }
6367
6368 static void si_dpm_setup_asic(struct amdgpu_device *adev)
6369 {
6370         si_read_clock_registers(adev);
6371         si_enable_acpi_power_management(adev);
6372 }
6373
6374 static int si_thermal_enable_alert(struct amdgpu_device *adev,
6375                                    bool enable)
6376 {
6377         u32 thermal_int = RREG32(CG_THERMAL_INT);
6378
6379         if (enable) {
6380                 PPSMC_Result result;
6381
6382                 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6383                 WREG32(CG_THERMAL_INT, thermal_int);
6384                 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
6385                 if (result != PPSMC_Result_OK) {
6386                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6387                         return -EINVAL;
6388                 }
6389         } else {
6390                 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6391                 WREG32(CG_THERMAL_INT, thermal_int);
6392         }
6393
6394         return 0;
6395 }
6396
6397 static int si_thermal_set_temperature_range(struct amdgpu_device *adev,
6398                                             int min_temp, int max_temp)
6399 {
6400         int low_temp = 0 * 1000;
6401         int high_temp = 255 * 1000;
6402
6403         if (low_temp < min_temp)
6404                 low_temp = min_temp;
6405         if (high_temp > max_temp)
6406                 high_temp = max_temp;
6407         if (high_temp < low_temp) {
6408                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6409                 return -EINVAL;
6410         }
6411
6412         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6413         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6414         WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6415
6416         adev->pm.dpm.thermal.min_temp = low_temp;
6417         adev->pm.dpm.thermal.max_temp = high_temp;
6418
6419         return 0;
6420 }
6421
6422 static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
6423 {
6424         struct si_power_info *si_pi = si_get_pi(adev);
6425         u32 tmp;
6426
6427         if (si_pi->fan_ctrl_is_in_default_mode) {
6428                 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6429                 si_pi->fan_ctrl_default_mode = tmp;
6430                 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6431                 si_pi->t_min = tmp;
6432                 si_pi->fan_ctrl_is_in_default_mode = false;
6433         }
6434
6435         tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6436         tmp |= TMIN(0);
6437         WREG32(CG_FDO_CTRL2, tmp);
6438
6439         tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6440         tmp |= FDO_PWM_MODE(mode);
6441         WREG32(CG_FDO_CTRL2, tmp);
6442 }
6443
6444 static int si_thermal_setup_fan_table(struct amdgpu_device *adev)
6445 {
6446         struct si_power_info *si_pi = si_get_pi(adev);
6447         PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6448         u32 duty100;
6449         u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6450         u16 fdo_min, slope1, slope2;
6451         u32 reference_clock, tmp;
6452         int ret;
6453         u64 tmp64;
6454
6455         if (!si_pi->fan_table_start) {
6456                 adev->pm.dpm.fan.ucode_fan_control = false;
6457                 return 0;
6458         }
6459
6460         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6461
6462         if (duty100 == 0) {
6463                 adev->pm.dpm.fan.ucode_fan_control = false;
6464                 return 0;
6465         }
6466
6467         tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
6468         do_div(tmp64, 10000);
6469         fdo_min = (u16)tmp64;
6470
6471         t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
6472         t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
6473
6474         pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
6475         pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
6476
6477         slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6478         slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6479
6480         fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
6481         fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
6482         fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
6483         fan_table.slope1 = cpu_to_be16(slope1);
6484         fan_table.slope2 = cpu_to_be16(slope2);
6485         fan_table.fdo_min = cpu_to_be16(fdo_min);
6486         fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
6487         fan_table.hys_up = cpu_to_be16(1);
6488         fan_table.hys_slope = cpu_to_be16(1);
6489         fan_table.temp_resp_lim = cpu_to_be16(5);
6490         reference_clock = amdgpu_asic_get_xclk(adev);
6491
6492         fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
6493                                                 reference_clock) / 1600);
6494         fan_table.fdo_max = cpu_to_be16((u16)duty100);
6495
6496         tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6497         fan_table.temp_src = (uint8_t)tmp;
6498
6499         ret = amdgpu_si_copy_bytes_to_smc(adev,
6500                                           si_pi->fan_table_start,
6501                                           (u8 *)(&fan_table),
6502                                           sizeof(fan_table),
6503                                           si_pi->sram_end);
6504
6505         if (ret) {
6506                 DRM_ERROR("Failed to load fan table to the SMC.");
6507                 adev->pm.dpm.fan.ucode_fan_control = false;
6508         }
6509
6510         return ret;
6511 }
6512
6513 static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
6514 {
6515         struct si_power_info *si_pi = si_get_pi(adev);
6516         PPSMC_Result ret;
6517
6518         ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl);
6519         if (ret == PPSMC_Result_OK) {
6520                 si_pi->fan_is_controlled_by_smc = true;
6521                 return 0;
6522         } else {
6523                 return -EINVAL;
6524         }
6525 }
6526
6527 static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
6528 {
6529         struct si_power_info *si_pi = si_get_pi(adev);
6530         PPSMC_Result ret;
6531
6532         ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl);
6533
6534         if (ret == PPSMC_Result_OK) {
6535                 si_pi->fan_is_controlled_by_smc = false;
6536                 return 0;
6537         } else {
6538                 return -EINVAL;
6539         }
6540 }
6541
6542 static int si_dpm_get_fan_speed_pwm(void *handle,
6543                                       u32 *speed)
6544 {
6545         u32 duty, duty100;
6546         u64 tmp64;
6547         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6548
6549         if (adev->pm.no_fan)
6550                 return -ENOENT;
6551
6552         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6553         duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6554
6555         if (duty100 == 0)
6556                 return -EINVAL;
6557
6558         tmp64 = (u64)duty * 255;
6559         do_div(tmp64, duty100);
6560         *speed = MIN((u32)tmp64, 255);
6561
6562         return 0;
6563 }
6564
6565 static int si_dpm_set_fan_speed_pwm(void *handle,
6566                                       u32 speed)
6567 {
6568         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6569         struct si_power_info *si_pi = si_get_pi(adev);
6570         u32 tmp;
6571         u32 duty, duty100;
6572         u64 tmp64;
6573
6574         if (adev->pm.no_fan)
6575                 return -ENOENT;
6576
6577         if (si_pi->fan_is_controlled_by_smc)
6578                 return -EINVAL;
6579
6580         if (speed > 255)
6581                 return -EINVAL;
6582
6583         duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6584
6585         if (duty100 == 0)
6586                 return -EINVAL;
6587
6588         tmp64 = (u64)speed * duty100;
6589         do_div(tmp64, 255);
6590         duty = (u32)tmp64;
6591
6592         tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6593         tmp |= FDO_STATIC_DUTY(duty);
6594         WREG32(CG_FDO_CTRL0, tmp);
6595
6596         return 0;
6597 }
6598
6599 static void si_dpm_set_fan_control_mode(void *handle, u32 mode)
6600 {
6601         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6602
6603         if (mode) {
6604                 /* stop auto-manage */
6605                 if (adev->pm.dpm.fan.ucode_fan_control)
6606                         si_fan_ctrl_stop_smc_fan_control(adev);
6607                 si_fan_ctrl_set_static_mode(adev, mode);
6608         } else {
6609                 /* restart auto-manage */
6610                 if (adev->pm.dpm.fan.ucode_fan_control)
6611                         si_thermal_start_smc_fan_control(adev);
6612                 else
6613                         si_fan_ctrl_set_default_mode(adev);
6614         }
6615 }
6616
6617 static u32 si_dpm_get_fan_control_mode(void *handle)
6618 {
6619         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6620         struct si_power_info *si_pi = si_get_pi(adev);
6621         u32 tmp;
6622
6623         if (si_pi->fan_is_controlled_by_smc)
6624                 return 0;
6625
6626         tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6627         return (tmp >> FDO_PWM_MODE_SHIFT);
6628 }
6629
6630 #if 0
6631 static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
6632                                          u32 *speed)
6633 {
6634         u32 tach_period;
6635         u32 xclk = amdgpu_asic_get_xclk(adev);
6636
6637         if (adev->pm.no_fan)
6638                 return -ENOENT;
6639
6640         if (adev->pm.fan_pulses_per_revolution == 0)
6641                 return -ENOENT;
6642
6643         tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6644         if (tach_period == 0)
6645                 return -ENOENT;
6646
6647         *speed = 60 * xclk * 10000 / tach_period;
6648
6649         return 0;
6650 }
6651
6652 static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
6653                                          u32 speed)
6654 {
6655         u32 tach_period, tmp;
6656         u32 xclk = amdgpu_asic_get_xclk(adev);
6657
6658         if (adev->pm.no_fan)
6659                 return -ENOENT;
6660
6661         if (adev->pm.fan_pulses_per_revolution == 0)
6662                 return -ENOENT;
6663
6664         if ((speed < adev->pm.fan_min_rpm) ||
6665             (speed > adev->pm.fan_max_rpm))
6666                 return -EINVAL;
6667
6668         if (adev->pm.dpm.fan.ucode_fan_control)
6669                 si_fan_ctrl_stop_smc_fan_control(adev);
6670
6671         tach_period = 60 * xclk * 10000 / (8 * speed);
6672         tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6673         tmp |= TARGET_PERIOD(tach_period);
6674         WREG32(CG_TACH_CTRL, tmp);
6675
6676         si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
6677
6678         return 0;
6679 }
6680 #endif
6681
6682 static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
6683 {
6684         struct si_power_info *si_pi = si_get_pi(adev);
6685         u32 tmp;
6686
6687         if (!si_pi->fan_ctrl_is_in_default_mode) {
6688                 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6689                 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6690                 WREG32(CG_FDO_CTRL2, tmp);
6691
6692                 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6693                 tmp |= TMIN(si_pi->t_min);
6694                 WREG32(CG_FDO_CTRL2, tmp);
6695                 si_pi->fan_ctrl_is_in_default_mode = true;
6696         }
6697 }
6698
6699 static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev)
6700 {
6701         if (adev->pm.dpm.fan.ucode_fan_control) {
6702                 si_fan_ctrl_start_smc_fan_control(adev);
6703                 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
6704         }
6705 }
6706
6707 static void si_thermal_initialize(struct amdgpu_device *adev)
6708 {
6709         u32 tmp;
6710
6711         if (adev->pm.fan_pulses_per_revolution) {
6712                 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6713                 tmp |= EDGE_PER_REV(adev->pm.fan_pulses_per_revolution -1);
6714                 WREG32(CG_TACH_CTRL, tmp);
6715         }
6716
6717         tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6718         tmp |= TACH_PWM_RESP_RATE(0x28);
6719         WREG32(CG_FDO_CTRL2, tmp);
6720 }
6721
6722 static int si_thermal_start_thermal_controller(struct amdgpu_device *adev)
6723 {
6724         int ret;
6725
6726         si_thermal_initialize(adev);
6727         ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6728         if (ret)
6729                 return ret;
6730         ret = si_thermal_enable_alert(adev, true);
6731         if (ret)
6732                 return ret;
6733         if (adev->pm.dpm.fan.ucode_fan_control) {
6734                 ret = si_halt_smc(adev);
6735                 if (ret)
6736                         return ret;
6737                 ret = si_thermal_setup_fan_table(adev);
6738                 if (ret)
6739                         return ret;
6740                 ret = si_resume_smc(adev);
6741                 if (ret)
6742                         return ret;
6743                 si_thermal_start_smc_fan_control(adev);
6744         }
6745
6746         return 0;
6747 }
6748
6749 static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev)
6750 {
6751         if (!adev->pm.no_fan) {
6752                 si_fan_ctrl_set_default_mode(adev);
6753                 si_fan_ctrl_stop_smc_fan_control(adev);
6754         }
6755 }
6756
6757 static int si_dpm_enable(struct amdgpu_device *adev)
6758 {
6759         struct rv7xx_power_info *pi = rv770_get_pi(adev);
6760         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6761         struct si_power_info *si_pi = si_get_pi(adev);
6762         struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6763         int ret;
6764
6765         if (amdgpu_si_is_smc_running(adev))
6766                 return -EINVAL;
6767         if (pi->voltage_control || si_pi->voltage_control_svi2)
6768                 si_enable_voltage_control(adev, true);
6769         if (pi->mvdd_control)
6770                 si_get_mvdd_configuration(adev);
6771         if (pi->voltage_control || si_pi->voltage_control_svi2) {
6772                 ret = si_construct_voltage_tables(adev);
6773                 if (ret) {
6774                         DRM_ERROR("si_construct_voltage_tables failed\n");
6775                         return ret;
6776                 }
6777         }
6778         if (eg_pi->dynamic_ac_timing) {
6779                 ret = si_initialize_mc_reg_table(adev);
6780                 if (ret)
6781                         eg_pi->dynamic_ac_timing = false;
6782         }
6783         if (pi->dynamic_ss)
6784                 si_enable_spread_spectrum(adev, true);
6785         if (pi->thermal_protection)
6786                 si_enable_thermal_protection(adev, true);
6787         si_setup_bsp(adev);
6788         si_program_git(adev);
6789         si_program_tp(adev);
6790         si_program_tpp(adev);
6791         si_program_sstp(adev);
6792         si_enable_display_gap(adev);
6793         si_program_vc(adev);
6794         ret = si_upload_firmware(adev);
6795         if (ret) {
6796                 DRM_ERROR("si_upload_firmware failed\n");
6797                 return ret;
6798         }
6799         ret = si_process_firmware_header(adev);
6800         if (ret) {
6801                 DRM_ERROR("si_process_firmware_header failed\n");
6802                 return ret;
6803         }
6804         ret = si_initial_switch_from_arb_f0_to_f1(adev);
6805         if (ret) {
6806                 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6807                 return ret;
6808         }
6809         ret = si_init_smc_table(adev);
6810         if (ret) {
6811                 DRM_ERROR("si_init_smc_table failed\n");
6812                 return ret;
6813         }
6814         ret = si_init_smc_spll_table(adev);
6815         if (ret) {
6816                 DRM_ERROR("si_init_smc_spll_table failed\n");
6817                 return ret;
6818         }
6819         ret = si_init_arb_table_index(adev);
6820         if (ret) {
6821                 DRM_ERROR("si_init_arb_table_index failed\n");
6822                 return ret;
6823         }
6824         if (eg_pi->dynamic_ac_timing) {
6825                 ret = si_populate_mc_reg_table(adev, boot_ps);
6826                 if (ret) {
6827                         DRM_ERROR("si_populate_mc_reg_table failed\n");
6828                         return ret;
6829                 }
6830         }
6831         ret = si_initialize_smc_cac_tables(adev);
6832         if (ret) {
6833                 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6834                 return ret;
6835         }
6836         ret = si_initialize_hardware_cac_manager(adev);
6837         if (ret) {
6838                 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6839                 return ret;
6840         }
6841         ret = si_initialize_smc_dte_tables(adev);
6842         if (ret) {
6843                 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6844                 return ret;
6845         }
6846         ret = si_populate_smc_tdp_limits(adev, boot_ps);
6847         if (ret) {
6848                 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6849                 return ret;
6850         }
6851         ret = si_populate_smc_tdp_limits_2(adev, boot_ps);
6852         if (ret) {
6853                 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6854                 return ret;
6855         }
6856         si_program_response_times(adev);
6857         si_program_ds_registers(adev);
6858         si_dpm_start_smc(adev);
6859         ret = si_notify_smc_display_change(adev, false);
6860         if (ret) {
6861                 DRM_ERROR("si_notify_smc_display_change failed\n");
6862                 return ret;
6863         }
6864         si_enable_sclk_control(adev, true);
6865         si_start_dpm(adev);
6866
6867         si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
6868         si_thermal_start_thermal_controller(adev);
6869
6870         return 0;
6871 }
6872
6873 static int si_set_temperature_range(struct amdgpu_device *adev)
6874 {
6875         int ret;
6876
6877         ret = si_thermal_enable_alert(adev, false);
6878         if (ret)
6879                 return ret;
6880         ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6881         if (ret)
6882                 return ret;
6883         ret = si_thermal_enable_alert(adev, true);
6884         if (ret)
6885                 return ret;
6886
6887         return ret;
6888 }
6889
6890 static void si_dpm_disable(struct amdgpu_device *adev)
6891 {
6892         struct rv7xx_power_info *pi = rv770_get_pi(adev);
6893         struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6894
6895         if (!amdgpu_si_is_smc_running(adev))
6896                 return;
6897         si_thermal_stop_thermal_controller(adev);
6898         si_disable_ulv(adev);
6899         si_clear_vc(adev);
6900         if (pi->thermal_protection)
6901                 si_enable_thermal_protection(adev, false);
6902         si_enable_power_containment(adev, boot_ps, false);
6903         si_enable_smc_cac(adev, boot_ps, false);
6904         si_enable_spread_spectrum(adev, false);
6905         si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6906         si_stop_dpm(adev);
6907         si_reset_to_default(adev);
6908         si_dpm_stop_smc(adev);
6909         si_force_switch_to_arb_f0(adev);
6910
6911         ni_update_current_ps(adev, boot_ps);
6912 }
6913
6914 static int si_dpm_pre_set_power_state(void *handle)
6915 {
6916         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6917         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6918         struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
6919         struct amdgpu_ps *new_ps = &requested_ps;
6920
6921         ni_update_requested_ps(adev, new_ps);
6922         si_apply_state_adjust_rules(adev, &eg_pi->requested_rps);
6923
6924         return 0;
6925 }
6926
6927 static int si_power_control_set_level(struct amdgpu_device *adev)
6928 {
6929         struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps;
6930         int ret;
6931
6932         ret = si_restrict_performance_levels_before_switch(adev);
6933         if (ret)
6934                 return ret;
6935         ret = si_halt_smc(adev);
6936         if (ret)
6937                 return ret;
6938         ret = si_populate_smc_tdp_limits(adev, new_ps);
6939         if (ret)
6940                 return ret;
6941         ret = si_populate_smc_tdp_limits_2(adev, new_ps);
6942         if (ret)
6943                 return ret;
6944         ret = si_resume_smc(adev);
6945         if (ret)
6946                 return ret;
6947         ret = si_set_sw_state(adev);
6948         if (ret)
6949                 return ret;
6950         return 0;
6951 }
6952
6953 static void si_set_vce_clock(struct amdgpu_device *adev,
6954                              struct amdgpu_ps *new_rps,
6955                              struct amdgpu_ps *old_rps)
6956 {
6957         if ((old_rps->evclk != new_rps->evclk) ||
6958             (old_rps->ecclk != new_rps->ecclk)) {
6959                 /* Turn the clocks on when encoding, off otherwise */
6960                 if (new_rps->evclk || new_rps->ecclk) {
6961                         /* Place holder for future VCE1.0 porting to amdgpu
6962                         vce_v1_0_enable_mgcg(adev, false, false);*/
6963                 } else {
6964                         /* Place holder for future VCE1.0 porting to amdgpu
6965                         vce_v1_0_enable_mgcg(adev, true, false);
6966                         amdgpu_asic_set_vce_clocks(adev, new_rps->evclk, new_rps->ecclk);*/
6967                 }
6968         }
6969 }
6970
6971 static int si_dpm_set_power_state(void *handle)
6972 {
6973         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6974         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6975         struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
6976         struct amdgpu_ps *old_ps = &eg_pi->current_rps;
6977         int ret;
6978
6979         ret = si_disable_ulv(adev);
6980         if (ret) {
6981                 DRM_ERROR("si_disable_ulv failed\n");
6982                 return ret;
6983         }
6984         ret = si_restrict_performance_levels_before_switch(adev);
6985         if (ret) {
6986                 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6987                 return ret;
6988         }
6989         if (eg_pi->pcie_performance_request)
6990                 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
6991         ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps);
6992         ret = si_enable_power_containment(adev, new_ps, false);
6993         if (ret) {
6994                 DRM_ERROR("si_enable_power_containment failed\n");
6995                 return ret;
6996         }
6997         ret = si_enable_smc_cac(adev, new_ps, false);
6998         if (ret) {
6999                 DRM_ERROR("si_enable_smc_cac failed\n");
7000                 return ret;
7001         }
7002         ret = si_halt_smc(adev);
7003         if (ret) {
7004                 DRM_ERROR("si_halt_smc failed\n");
7005                 return ret;
7006         }
7007         ret = si_upload_sw_state(adev, new_ps);
7008         if (ret) {
7009                 DRM_ERROR("si_upload_sw_state failed\n");
7010                 return ret;
7011         }
7012         ret = si_upload_smc_data(adev);
7013         if (ret) {
7014                 DRM_ERROR("si_upload_smc_data failed\n");
7015                 return ret;
7016         }
7017         ret = si_upload_ulv_state(adev);
7018         if (ret) {
7019                 DRM_ERROR("si_upload_ulv_state failed\n");
7020                 return ret;
7021         }
7022         if (eg_pi->dynamic_ac_timing) {
7023                 ret = si_upload_mc_reg_table(adev, new_ps);
7024                 if (ret) {
7025                         DRM_ERROR("si_upload_mc_reg_table failed\n");
7026                         return ret;
7027                 }
7028         }
7029         ret = si_program_memory_timing_parameters(adev, new_ps);
7030         if (ret) {
7031                 DRM_ERROR("si_program_memory_timing_parameters failed\n");
7032                 return ret;
7033         }
7034         si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps);
7035
7036         ret = si_resume_smc(adev);
7037         if (ret) {
7038                 DRM_ERROR("si_resume_smc failed\n");
7039                 return ret;
7040         }
7041         ret = si_set_sw_state(adev);
7042         if (ret) {
7043                 DRM_ERROR("si_set_sw_state failed\n");
7044                 return ret;
7045         }
7046         ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps);
7047         si_set_vce_clock(adev, new_ps, old_ps);
7048         if (eg_pi->pcie_performance_request)
7049                 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
7050         ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps);
7051         if (ret) {
7052                 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
7053                 return ret;
7054         }
7055         ret = si_enable_smc_cac(adev, new_ps, true);
7056         if (ret) {
7057                 DRM_ERROR("si_enable_smc_cac failed\n");
7058                 return ret;
7059         }
7060         ret = si_enable_power_containment(adev, new_ps, true);
7061         if (ret) {
7062                 DRM_ERROR("si_enable_power_containment failed\n");
7063                 return ret;
7064         }
7065
7066         ret = si_power_control_set_level(adev);
7067         if (ret) {
7068                 DRM_ERROR("si_power_control_set_level failed\n");
7069                 return ret;
7070         }
7071
7072         return 0;
7073 }
7074
7075 static void si_dpm_post_set_power_state(void *handle)
7076 {
7077         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7078         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7079         struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7080
7081         ni_update_current_ps(adev, new_ps);
7082 }
7083
7084 #if 0
7085 void si_dpm_reset_asic(struct amdgpu_device *adev)
7086 {
7087         si_restrict_performance_levels_before_switch(adev);
7088         si_disable_ulv(adev);
7089         si_set_boot_state(adev);
7090 }
7091 #endif
7092
7093 static void si_dpm_display_configuration_changed(void *handle)
7094 {
7095         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7096
7097         si_program_display_gap(adev);
7098 }
7099
7100
7101 static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev,
7102                                           struct amdgpu_ps *rps,
7103                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
7104                                           u8 table_rev)
7105 {
7106         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
7107         rps->class = le16_to_cpu(non_clock_info->usClassification);
7108         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
7109
7110         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
7111                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
7112                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
7113         } else if (r600_is_uvd_state(rps->class, rps->class2)) {
7114                 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
7115                 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
7116         } else {
7117                 rps->vclk = 0;
7118                 rps->dclk = 0;
7119         }
7120
7121         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
7122                 adev->pm.dpm.boot_ps = rps;
7123         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
7124                 adev->pm.dpm.uvd_ps = rps;
7125 }
7126
7127 static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
7128                                       struct amdgpu_ps *rps, int index,
7129                                       union pplib_clock_info *clock_info)
7130 {
7131         struct rv7xx_power_info *pi = rv770_get_pi(adev);
7132         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7133         struct si_power_info *si_pi = si_get_pi(adev);
7134         struct  si_ps *ps = si_get_ps(rps);
7135         u16 leakage_voltage;
7136         struct rv7xx_pl *pl = &ps->performance_levels[index];
7137         int ret;
7138
7139         ps->performance_level_count = index + 1;
7140
7141         pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7142         pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
7143         pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7144         pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
7145
7146         pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
7147         pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
7148         pl->flags = le32_to_cpu(clock_info->si.ulFlags);
7149         pl->pcie_gen = amdgpu_get_pcie_gen_support(adev,
7150                                                    si_pi->sys_pcie_mask,
7151                                                    si_pi->boot_pcie_gen,
7152                                                    clock_info->si.ucPCIEGen);
7153
7154         /* patch up vddc if necessary */
7155         ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
7156                                                         &leakage_voltage);
7157         if (ret == 0)
7158                 pl->vddc = leakage_voltage;
7159
7160         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
7161                 pi->acpi_vddc = pl->vddc;
7162                 eg_pi->acpi_vddci = pl->vddci;
7163                 si_pi->acpi_pcie_gen = pl->pcie_gen;
7164         }
7165
7166         if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
7167             index == 0) {
7168                 /* XXX disable for A0 tahiti */
7169                 si_pi->ulv.supported = false;
7170                 si_pi->ulv.pl = *pl;
7171                 si_pi->ulv.one_pcie_lane_in_ulv = false;
7172                 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
7173                 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
7174                 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
7175         }
7176
7177         if (pi->min_vddc_in_table > pl->vddc)
7178                 pi->min_vddc_in_table = pl->vddc;
7179
7180         if (pi->max_vddc_in_table < pl->vddc)
7181                 pi->max_vddc_in_table = pl->vddc;
7182
7183         /* patch up boot state */
7184         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
7185                 u16 vddc, vddci, mvdd;
7186                 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd);
7187                 pl->mclk = adev->clock.default_mclk;
7188                 pl->sclk = adev->clock.default_sclk;
7189                 pl->vddc = vddc;
7190                 pl->vddci = vddci;
7191                 si_pi->mvdd_bootup_value = mvdd;
7192         }
7193
7194         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
7195             ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
7196                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
7197                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
7198                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
7199                 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
7200         }
7201 }
7202
7203 union pplib_power_state {
7204         struct _ATOM_PPLIB_STATE v1;
7205         struct _ATOM_PPLIB_STATE_V2 v2;
7206 };
7207
7208 static int si_parse_power_table(struct amdgpu_device *adev)
7209 {
7210         struct amdgpu_mode_info *mode_info = &adev->mode_info;
7211         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
7212         union pplib_power_state *power_state;
7213         int i, j, k, non_clock_array_index, clock_array_index;
7214         union pplib_clock_info *clock_info;
7215         struct _StateArray *state_array;
7216         struct _ClockInfoArray *clock_info_array;
7217         struct _NonClockInfoArray *non_clock_info_array;
7218         union power_info *power_info;
7219         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
7220         u16 data_offset;
7221         u8 frev, crev;
7222         u8 *power_state_offset;
7223         struct  si_ps *ps;
7224
7225         if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
7226                                    &frev, &crev, &data_offset))
7227                 return -EINVAL;
7228         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
7229
7230         amdgpu_add_thermal_controller(adev);
7231
7232         state_array = (struct _StateArray *)
7233                 (mode_info->atom_context->bios + data_offset +
7234                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
7235         clock_info_array = (struct _ClockInfoArray *)
7236                 (mode_info->atom_context->bios + data_offset +
7237                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
7238         non_clock_info_array = (struct _NonClockInfoArray *)
7239                 (mode_info->atom_context->bios + data_offset +
7240                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
7241
7242         adev->pm.dpm.ps = kcalloc(state_array->ucNumEntries,
7243                                   sizeof(struct amdgpu_ps),
7244                                   GFP_KERNEL);
7245         if (!adev->pm.dpm.ps)
7246                 return -ENOMEM;
7247         power_state_offset = (u8 *)state_array->states;
7248         for (i = 0; i < state_array->ucNumEntries; i++) {
7249                 u8 *idx;
7250                 power_state = (union pplib_power_state *)power_state_offset;
7251                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
7252                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
7253                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
7254                 ps = kzalloc(sizeof(struct  si_ps), GFP_KERNEL);
7255                 if (ps == NULL) {
7256                         kfree(adev->pm.dpm.ps);
7257                         return -ENOMEM;
7258                 }
7259                 adev->pm.dpm.ps[i].ps_priv = ps;
7260                 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
7261                                               non_clock_info,
7262                                               non_clock_info_array->ucEntrySize);
7263                 k = 0;
7264                 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
7265                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
7266                         clock_array_index = idx[j];
7267                         if (clock_array_index >= clock_info_array->ucNumEntries)
7268                                 continue;
7269                         if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
7270                                 break;
7271                         clock_info = (union pplib_clock_info *)
7272                                 ((u8 *)&clock_info_array->clockInfo[0] +
7273                                  (clock_array_index * clock_info_array->ucEntrySize));
7274                         si_parse_pplib_clock_info(adev,
7275                                                   &adev->pm.dpm.ps[i], k,
7276                                                   clock_info);
7277                         k++;
7278                 }
7279                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
7280         }
7281         adev->pm.dpm.num_ps = state_array->ucNumEntries;
7282
7283         /* fill in the vce power states */
7284         for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
7285                 u32 sclk, mclk;
7286                 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
7287                 clock_info = (union pplib_clock_info *)
7288                         &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
7289                 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7290                 sclk |= clock_info->si.ucEngineClockHigh << 16;
7291                 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7292                 mclk |= clock_info->si.ucMemoryClockHigh << 16;
7293                 adev->pm.dpm.vce_states[i].sclk = sclk;
7294                 adev->pm.dpm.vce_states[i].mclk = mclk;
7295         }
7296
7297         return 0;
7298 }
7299
7300 static int si_dpm_init(struct amdgpu_device *adev)
7301 {
7302         struct rv7xx_power_info *pi;
7303         struct evergreen_power_info *eg_pi;
7304         struct ni_power_info *ni_pi;
7305         struct si_power_info *si_pi;
7306         struct atom_clock_dividers dividers;
7307         int ret;
7308
7309         si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
7310         if (si_pi == NULL)
7311                 return -ENOMEM;
7312         adev->pm.dpm.priv = si_pi;
7313         ni_pi = &si_pi->ni;
7314         eg_pi = &ni_pi->eg;
7315         pi = &eg_pi->rv7xx;
7316
7317         si_pi->sys_pcie_mask =
7318                 adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_MASK;
7319         si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
7320         si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
7321
7322         si_set_max_cu_value(adev);
7323
7324         rv770_get_max_vddc(adev);
7325         si_get_leakage_vddc(adev);
7326         si_patch_dependency_tables_based_on_leakage(adev);
7327
7328         pi->acpi_vddc = 0;
7329         eg_pi->acpi_vddci = 0;
7330         pi->min_vddc_in_table = 0;
7331         pi->max_vddc_in_table = 0;
7332
7333         ret = amdgpu_get_platform_caps(adev);
7334         if (ret)
7335                 return ret;
7336
7337         ret = amdgpu_parse_extended_power_table(adev);
7338         if (ret)
7339                 return ret;
7340
7341         ret = si_parse_power_table(adev);
7342         if (ret)
7343                 return ret;
7344
7345         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
7346                 kcalloc(4,
7347                         sizeof(struct amdgpu_clock_voltage_dependency_entry),
7348                         GFP_KERNEL);
7349         if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
7350                 amdgpu_free_extended_power_table(adev);
7351                 return -ENOMEM;
7352         }
7353         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7354         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7355         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7356         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7357         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7358         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7359         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7360         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7361         adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7362
7363         if (adev->pm.dpm.voltage_response_time == 0)
7364                 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7365         if (adev->pm.dpm.backbias_response_time == 0)
7366                 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7367
7368         ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
7369                                              0, false, &dividers);
7370         if (ret)
7371                 pi->ref_div = dividers.ref_div + 1;
7372         else
7373                 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7374
7375         eg_pi->smu_uvd_hs = false;
7376
7377         pi->mclk_strobe_mode_threshold = 40000;
7378         if (si_is_special_1gb_platform(adev))
7379                 pi->mclk_stutter_mode_threshold = 0;
7380         else
7381                 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7382         pi->mclk_edc_enable_threshold = 40000;
7383         eg_pi->mclk_edc_wr_enable_threshold = 40000;
7384
7385         ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7386
7387         pi->voltage_control =
7388                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7389                                             VOLTAGE_OBJ_GPIO_LUT);
7390         if (!pi->voltage_control) {
7391                 si_pi->voltage_control_svi2 =
7392                         amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7393                                                     VOLTAGE_OBJ_SVID2);
7394                 if (si_pi->voltage_control_svi2)
7395                         amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7396                                                   &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7397         }
7398
7399         pi->mvdd_control =
7400                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7401                                             VOLTAGE_OBJ_GPIO_LUT);
7402
7403         eg_pi->vddci_control =
7404                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7405                                             VOLTAGE_OBJ_GPIO_LUT);
7406         if (!eg_pi->vddci_control)
7407                 si_pi->vddci_control_svi2 =
7408                         amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7409                                                     VOLTAGE_OBJ_SVID2);
7410
7411         si_pi->vddc_phase_shed_control =
7412                 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7413                                             VOLTAGE_OBJ_PHASE_LUT);
7414
7415         rv770_get_engine_memory_ss(adev);
7416
7417         pi->asi = RV770_ASI_DFLT;
7418         pi->pasi = CYPRESS_HASI_DFLT;
7419         pi->vrc = SISLANDS_VRC_DFLT;
7420
7421         pi->gfx_clock_gating = true;
7422
7423         eg_pi->sclk_deep_sleep = true;
7424         si_pi->sclk_deep_sleep_above_low = false;
7425
7426         if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7427                 pi->thermal_protection = true;
7428         else
7429                 pi->thermal_protection = false;
7430
7431         eg_pi->dynamic_ac_timing = true;
7432
7433         eg_pi->light_sleep = true;
7434 #if defined(CONFIG_ACPI)
7435         eg_pi->pcie_performance_request =
7436                 amdgpu_acpi_is_pcie_performance_request_supported(adev);
7437 #else
7438         eg_pi->pcie_performance_request = false;
7439 #endif
7440
7441         si_pi->sram_end = SMC_RAM_END;
7442
7443         adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7444         adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7445         adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7446         adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7447         adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7448         adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7449         adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7450
7451         si_initialize_powertune_defaults(adev);
7452
7453         /* make sure dc limits are valid */
7454         if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7455             (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7456                 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7457                         adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7458
7459         si_pi->fan_ctrl_is_in_default_mode = true;
7460
7461         return 0;
7462 }
7463
7464 static void si_dpm_fini(struct amdgpu_device *adev)
7465 {
7466         int i;
7467
7468         if (adev->pm.dpm.ps)
7469                 for (i = 0; i < adev->pm.dpm.num_ps; i++)
7470                         kfree(adev->pm.dpm.ps[i].ps_priv);
7471         kfree(adev->pm.dpm.ps);
7472         kfree(adev->pm.dpm.priv);
7473         kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7474         amdgpu_free_extended_power_table(adev);
7475 }
7476
7477 static void si_dpm_debugfs_print_current_performance_level(void *handle,
7478                                                     struct seq_file *m)
7479 {
7480         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7481         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7482         struct amdgpu_ps *rps = &eg_pi->current_rps;
7483         struct  si_ps *ps = si_get_ps(rps);
7484         struct rv7xx_pl *pl;
7485         u32 current_index =
7486                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7487                 CURRENT_STATE_INDEX_SHIFT;
7488
7489         if (current_index >= ps->performance_level_count) {
7490                 seq_printf(m, "invalid dpm profile %d\n", current_index);
7491         } else {
7492                 pl = &ps->performance_levels[current_index];
7493                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7494                 seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7495                            current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7496         }
7497 }
7498
7499 static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
7500                                       struct amdgpu_irq_src *source,
7501                                       unsigned type,
7502                                       enum amdgpu_interrupt_state state)
7503 {
7504         u32 cg_thermal_int;
7505
7506         switch (type) {
7507         case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
7508                 switch (state) {
7509                 case AMDGPU_IRQ_STATE_DISABLE:
7510                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7511                         cg_thermal_int |= THERM_INT_MASK_HIGH;
7512                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7513                         break;
7514                 case AMDGPU_IRQ_STATE_ENABLE:
7515                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7516                         cg_thermal_int &= ~THERM_INT_MASK_HIGH;
7517                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7518                         break;
7519                 default:
7520                         break;
7521                 }
7522                 break;
7523
7524         case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
7525                 switch (state) {
7526                 case AMDGPU_IRQ_STATE_DISABLE:
7527                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7528                         cg_thermal_int |= THERM_INT_MASK_LOW;
7529                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7530                         break;
7531                 case AMDGPU_IRQ_STATE_ENABLE:
7532                         cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7533                         cg_thermal_int &= ~THERM_INT_MASK_LOW;
7534                         WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7535                         break;
7536                 default:
7537                         break;
7538                 }
7539                 break;
7540
7541         default:
7542                 break;
7543         }
7544         return 0;
7545 }
7546
7547 static int si_dpm_process_interrupt(struct amdgpu_device *adev,
7548                                     struct amdgpu_irq_src *source,
7549                                     struct amdgpu_iv_entry *entry)
7550 {
7551         bool queue_thermal = false;
7552
7553         if (entry == NULL)
7554                 return -EINVAL;
7555
7556         switch (entry->src_id) {
7557         case 230: /* thermal low to high */
7558                 DRM_DEBUG("IH: thermal low to high\n");
7559                 adev->pm.dpm.thermal.high_to_low = false;
7560                 queue_thermal = true;
7561                 break;
7562         case 231: /* thermal high to low */
7563                 DRM_DEBUG("IH: thermal high to low\n");
7564                 adev->pm.dpm.thermal.high_to_low = true;
7565                 queue_thermal = true;
7566                 break;
7567         default:
7568                 break;
7569         }
7570
7571         if (queue_thermal)
7572                 schedule_work(&adev->pm.dpm.thermal.work);
7573
7574         return 0;
7575 }
7576
7577 static int si_dpm_late_init(void *handle)
7578 {
7579         int ret;
7580         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7581
7582         if (!adev->pm.dpm_enabled)
7583                 return 0;
7584
7585         ret = si_set_temperature_range(adev);
7586         if (ret)
7587                 return ret;
7588 #if 0 //TODO ?
7589         si_dpm_powergate_uvd(adev, true);
7590 #endif
7591         return 0;
7592 }
7593
7594 /**
7595  * si_dpm_init_microcode - load ucode images from disk
7596  *
7597  * @adev: amdgpu_device pointer
7598  *
7599  * Use the firmware interface to load the ucode images into
7600  * the driver (not loaded into hw).
7601  * Returns 0 on success, error on failure.
7602  */
7603 static int si_dpm_init_microcode(struct amdgpu_device *adev)
7604 {
7605         const char *chip_name;
7606         char fw_name[30];
7607         int err;
7608
7609         DRM_DEBUG("\n");
7610         switch (adev->asic_type) {
7611         case CHIP_TAHITI:
7612                 chip_name = "tahiti";
7613                 break;
7614         case CHIP_PITCAIRN:
7615                 if ((adev->pdev->revision == 0x81) &&
7616                     ((adev->pdev->device == 0x6810) ||
7617                     (adev->pdev->device == 0x6811)))
7618                         chip_name = "pitcairn_k";
7619                 else
7620                         chip_name = "pitcairn";
7621                 break;
7622         case CHIP_VERDE:
7623                 if (((adev->pdev->device == 0x6820) &&
7624                         ((adev->pdev->revision == 0x81) ||
7625                         (adev->pdev->revision == 0x83))) ||
7626                     ((adev->pdev->device == 0x6821) &&
7627                         ((adev->pdev->revision == 0x83) ||
7628                         (adev->pdev->revision == 0x87))) ||
7629                     ((adev->pdev->revision == 0x87) &&
7630                         ((adev->pdev->device == 0x6823) ||
7631                         (adev->pdev->device == 0x682b))))
7632                         chip_name = "verde_k";
7633                 else
7634                         chip_name = "verde";
7635                 break;
7636         case CHIP_OLAND:
7637                 if (((adev->pdev->revision == 0x81) &&
7638                         ((adev->pdev->device == 0x6600) ||
7639                         (adev->pdev->device == 0x6604) ||
7640                         (adev->pdev->device == 0x6605) ||
7641                         (adev->pdev->device == 0x6610))) ||
7642                     ((adev->pdev->revision == 0x83) &&
7643                         (adev->pdev->device == 0x6610)))
7644                         chip_name = "oland_k";
7645                 else
7646                         chip_name = "oland";
7647                 break;
7648         case CHIP_HAINAN:
7649                 if (((adev->pdev->revision == 0x81) &&
7650                         (adev->pdev->device == 0x6660)) ||
7651                     ((adev->pdev->revision == 0x83) &&
7652                         ((adev->pdev->device == 0x6660) ||
7653                         (adev->pdev->device == 0x6663) ||
7654                         (adev->pdev->device == 0x6665) ||
7655                          (adev->pdev->device == 0x6667))))
7656                         chip_name = "hainan_k";
7657                 else if ((adev->pdev->revision == 0xc3) &&
7658                          (adev->pdev->device == 0x6665))
7659                         chip_name = "banks_k_2";
7660                 else
7661                         chip_name = "hainan";
7662                 break;
7663         default: BUG();
7664         }
7665
7666         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_smc.bin", chip_name);
7667         err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
7668         if (err)
7669                 goto out;
7670         err = amdgpu_ucode_validate(adev->pm.fw);
7671
7672 out:
7673         if (err) {
7674                 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s\"\n",
7675                           err, fw_name);
7676                 release_firmware(adev->pm.fw);
7677                 adev->pm.fw = NULL;
7678         }
7679         return err;
7680
7681 }
7682
7683 static int si_dpm_sw_init(void *handle)
7684 {
7685         int ret;
7686         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7687
7688         ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq);
7689         if (ret)
7690                 return ret;
7691
7692         ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq);
7693         if (ret)
7694                 return ret;
7695
7696         /* default to balanced state */
7697         adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
7698         adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
7699         adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
7700         adev->pm.default_sclk = adev->clock.default_sclk;
7701         adev->pm.default_mclk = adev->clock.default_mclk;
7702         adev->pm.current_sclk = adev->clock.default_sclk;
7703         adev->pm.current_mclk = adev->clock.default_mclk;
7704         adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
7705
7706         if (amdgpu_dpm == 0)
7707                 return 0;
7708
7709         ret = si_dpm_init_microcode(adev);
7710         if (ret)
7711                 return ret;
7712
7713         INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
7714         mutex_lock(&adev->pm.mutex);
7715         ret = si_dpm_init(adev);
7716         if (ret)
7717                 goto dpm_failed;
7718         adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7719         if (amdgpu_dpm == 1)
7720                 amdgpu_pm_print_power_states(adev);
7721         mutex_unlock(&adev->pm.mutex);
7722         DRM_INFO("amdgpu: dpm initialized\n");
7723
7724         return 0;
7725
7726 dpm_failed:
7727         si_dpm_fini(adev);
7728         mutex_unlock(&adev->pm.mutex);
7729         DRM_ERROR("amdgpu: dpm initialization failed\n");
7730         return ret;
7731 }
7732
7733 static int si_dpm_sw_fini(void *handle)
7734 {
7735         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7736
7737         flush_work(&adev->pm.dpm.thermal.work);
7738
7739         mutex_lock(&adev->pm.mutex);
7740         si_dpm_fini(adev);
7741         mutex_unlock(&adev->pm.mutex);
7742
7743         return 0;
7744 }
7745
7746 static int si_dpm_hw_init(void *handle)
7747 {
7748         int ret;
7749
7750         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7751
7752         if (!amdgpu_dpm)
7753                 return 0;
7754
7755         mutex_lock(&adev->pm.mutex);
7756         si_dpm_setup_asic(adev);
7757         ret = si_dpm_enable(adev);
7758         if (ret)
7759                 adev->pm.dpm_enabled = false;
7760         else
7761                 adev->pm.dpm_enabled = true;
7762         mutex_unlock(&adev->pm.mutex);
7763         amdgpu_pm_compute_clocks(adev);
7764         return ret;
7765 }
7766
7767 static int si_dpm_hw_fini(void *handle)
7768 {
7769         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7770
7771         if (adev->pm.dpm_enabled) {
7772                 mutex_lock(&adev->pm.mutex);
7773                 si_dpm_disable(adev);
7774                 mutex_unlock(&adev->pm.mutex);
7775         }
7776
7777         return 0;
7778 }
7779
7780 static int si_dpm_suspend(void *handle)
7781 {
7782         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7783
7784         if (adev->pm.dpm_enabled) {
7785                 mutex_lock(&adev->pm.mutex);
7786                 /* disable dpm */
7787                 si_dpm_disable(adev);
7788                 /* reset the power state */
7789                 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7790                 mutex_unlock(&adev->pm.mutex);
7791         }
7792         return 0;
7793 }
7794
7795 static int si_dpm_resume(void *handle)
7796 {
7797         int ret;
7798         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7799
7800         if (adev->pm.dpm_enabled) {
7801                 /* asic init will reset to the boot state */
7802                 mutex_lock(&adev->pm.mutex);
7803                 si_dpm_setup_asic(adev);
7804                 ret = si_dpm_enable(adev);
7805                 if (ret)
7806                         adev->pm.dpm_enabled = false;
7807                 else
7808                         adev->pm.dpm_enabled = true;
7809                 mutex_unlock(&adev->pm.mutex);
7810                 if (adev->pm.dpm_enabled)
7811                         amdgpu_pm_compute_clocks(adev);
7812         }
7813         return 0;
7814 }
7815
7816 static bool si_dpm_is_idle(void *handle)
7817 {
7818         /* XXX */
7819         return true;
7820 }
7821
7822 static int si_dpm_wait_for_idle(void *handle)
7823 {
7824         /* XXX */
7825         return 0;
7826 }
7827
7828 static int si_dpm_soft_reset(void *handle)
7829 {
7830         return 0;
7831 }
7832
7833 static int si_dpm_set_clockgating_state(void *handle,
7834                                         enum amd_clockgating_state state)
7835 {
7836         return 0;
7837 }
7838
7839 static int si_dpm_set_powergating_state(void *handle,
7840                                         enum amd_powergating_state state)
7841 {
7842         return 0;
7843 }
7844
7845 /* get temperature in millidegrees */
7846 static int si_dpm_get_temp(void *handle)
7847 {
7848         u32 temp;
7849         int actual_temp = 0;
7850         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7851
7852         temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
7853                 CTF_TEMP_SHIFT;
7854
7855         if (temp & 0x200)
7856                 actual_temp = 255;
7857         else
7858                 actual_temp = temp & 0x1ff;
7859
7860         actual_temp = (actual_temp * 1000);
7861
7862         return actual_temp;
7863 }
7864
7865 static u32 si_dpm_get_sclk(void *handle, bool low)
7866 {
7867         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7868         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7869         struct  si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7870
7871         if (low)
7872                 return requested_state->performance_levels[0].sclk;
7873         else
7874                 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
7875 }
7876
7877 static u32 si_dpm_get_mclk(void *handle, bool low)
7878 {
7879         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7880         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7881         struct  si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
7882
7883         if (low)
7884                 return requested_state->performance_levels[0].mclk;
7885         else
7886                 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
7887 }
7888
7889 static void si_dpm_print_power_state(void *handle,
7890                                      void *current_ps)
7891 {
7892         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7893         struct amdgpu_ps *rps = (struct amdgpu_ps *)current_ps;
7894         struct  si_ps *ps = si_get_ps(rps);
7895         struct rv7xx_pl *pl;
7896         int i;
7897
7898         amdgpu_dpm_print_class_info(rps->class, rps->class2);
7899         amdgpu_dpm_print_cap_info(rps->caps);
7900         DRM_INFO("\tuvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7901         for (i = 0; i < ps->performance_level_count; i++) {
7902                 pl = &ps->performance_levels[i];
7903                 if (adev->asic_type >= CHIP_TAHITI)
7904                         DRM_INFO("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7905                                  i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7906                 else
7907                         DRM_INFO("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u\n",
7908                                  i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
7909         }
7910         amdgpu_dpm_print_ps_status(adev, rps);
7911 }
7912
7913 static int si_dpm_early_init(void *handle)
7914 {
7915
7916         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7917
7918         adev->powerplay.pp_funcs = &si_dpm_funcs;
7919         adev->powerplay.pp_handle = adev;
7920         si_dpm_set_irq_funcs(adev);
7921         return 0;
7922 }
7923
7924 static inline bool si_are_power_levels_equal(const struct rv7xx_pl  *si_cpl1,
7925                                                 const struct rv7xx_pl *si_cpl2)
7926 {
7927         return ((si_cpl1->mclk == si_cpl2->mclk) &&
7928                   (si_cpl1->sclk == si_cpl2->sclk) &&
7929                   (si_cpl1->pcie_gen == si_cpl2->pcie_gen) &&
7930                   (si_cpl1->vddc == si_cpl2->vddc) &&
7931                   (si_cpl1->vddci == si_cpl2->vddci));
7932 }
7933
7934 static int si_check_state_equal(void *handle,
7935                                 void *current_ps,
7936                                 void *request_ps,
7937                                 bool *equal)
7938 {
7939         struct si_ps *si_cps;
7940         struct si_ps *si_rps;
7941         int i;
7942         struct amdgpu_ps *cps = (struct amdgpu_ps *)current_ps;
7943         struct amdgpu_ps *rps = (struct amdgpu_ps *)request_ps;
7944         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7945
7946         if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
7947                 return -EINVAL;
7948
7949         si_cps = si_get_ps((struct amdgpu_ps *)cps);
7950         si_rps = si_get_ps((struct amdgpu_ps *)rps);
7951
7952         if (si_cps == NULL) {
7953                 printk("si_cps is NULL\n");
7954                 *equal = false;
7955                 return 0;
7956         }
7957
7958         if (si_cps->performance_level_count != si_rps->performance_level_count) {
7959                 *equal = false;
7960                 return 0;
7961         }
7962
7963         for (i = 0; i < si_cps->performance_level_count; i++) {
7964                 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]),
7965                                         &(si_rps->performance_levels[i]))) {
7966                         *equal = false;
7967                         return 0;
7968                 }
7969         }
7970
7971         /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
7972         *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
7973         *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
7974
7975         return 0;
7976 }
7977
7978 static int si_dpm_read_sensor(void *handle, int idx,
7979                               void *value, int *size)
7980 {
7981         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7982         struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7983         struct amdgpu_ps *rps = &eg_pi->current_rps;
7984         struct  si_ps *ps = si_get_ps(rps);
7985         uint32_t sclk, mclk;
7986         u32 pl_index =
7987                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7988                 CURRENT_STATE_INDEX_SHIFT;
7989
7990         /* size must be at least 4 bytes for all sensors */
7991         if (*size < 4)
7992                 return -EINVAL;
7993
7994         switch (idx) {
7995         case AMDGPU_PP_SENSOR_GFX_SCLK:
7996                 if (pl_index < ps->performance_level_count) {
7997                         sclk = ps->performance_levels[pl_index].sclk;
7998                         *((uint32_t *)value) = sclk;
7999                         *size = 4;
8000                         return 0;
8001                 }
8002                 return -EINVAL;
8003         case AMDGPU_PP_SENSOR_GFX_MCLK:
8004                 if (pl_index < ps->performance_level_count) {
8005                         mclk = ps->performance_levels[pl_index].mclk;
8006                         *((uint32_t *)value) = mclk;
8007                         *size = 4;
8008                         return 0;
8009                 }
8010                 return -EINVAL;
8011         case AMDGPU_PP_SENSOR_GPU_TEMP:
8012                 *((uint32_t *)value) = si_dpm_get_temp(adev);
8013                 *size = 4;
8014                 return 0;
8015         default:
8016                 return -EOPNOTSUPP;
8017         }
8018 }
8019
8020 static const struct amd_ip_funcs si_dpm_ip_funcs = {
8021         .name = "si_dpm",
8022         .early_init = si_dpm_early_init,
8023         .late_init = si_dpm_late_init,
8024         .sw_init = si_dpm_sw_init,
8025         .sw_fini = si_dpm_sw_fini,
8026         .hw_init = si_dpm_hw_init,
8027         .hw_fini = si_dpm_hw_fini,
8028         .suspend = si_dpm_suspend,
8029         .resume = si_dpm_resume,
8030         .is_idle = si_dpm_is_idle,
8031         .wait_for_idle = si_dpm_wait_for_idle,
8032         .soft_reset = si_dpm_soft_reset,
8033         .set_clockgating_state = si_dpm_set_clockgating_state,
8034         .set_powergating_state = si_dpm_set_powergating_state,
8035 };
8036
8037 const struct amdgpu_ip_block_version si_smu_ip_block =
8038 {
8039         .type = AMD_IP_BLOCK_TYPE_SMC,
8040         .major = 6,
8041         .minor = 0,
8042         .rev = 0,
8043         .funcs = &si_dpm_ip_funcs,
8044 };
8045
8046 static const struct amd_pm_funcs si_dpm_funcs = {
8047         .pre_set_power_state = &si_dpm_pre_set_power_state,
8048         .set_power_state = &si_dpm_set_power_state,
8049         .post_set_power_state = &si_dpm_post_set_power_state,
8050         .display_configuration_changed = &si_dpm_display_configuration_changed,
8051         .get_sclk = &si_dpm_get_sclk,
8052         .get_mclk = &si_dpm_get_mclk,
8053         .print_power_state = &si_dpm_print_power_state,
8054         .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
8055         .force_performance_level = &si_dpm_force_performance_level,
8056         .vblank_too_short = &si_dpm_vblank_too_short,
8057         .set_fan_control_mode = &si_dpm_set_fan_control_mode,
8058         .get_fan_control_mode = &si_dpm_get_fan_control_mode,
8059         .set_fan_speed_pwm = &si_dpm_set_fan_speed_pwm,
8060         .get_fan_speed_pwm = &si_dpm_get_fan_speed_pwm,
8061         .check_state_equal = &si_check_state_equal,
8062         .get_vce_clock_state = amdgpu_get_vce_clock_state,
8063         .read_sensor = &si_dpm_read_sensor,
8064 };
8065
8066 static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = {
8067         .set = si_dpm_set_interrupt_state,
8068         .process = si_dpm_process_interrupt,
8069 };
8070
8071 static void si_dpm_set_irq_funcs(struct amdgpu_device *adev)
8072 {
8073         adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
8074         adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;
8075 }
8076