drivers/gpu/drm/amd/pm/powerplay/hwmgr/vega12_hwmgr.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/fb.h>
  26 #include <linux/module.h>
  27 #include <linux/slab.h>
  28
  29 #include "hwmgr.h"
  30 #include "amd_powerplay.h"
  31 #include "vega12_smumgr.h"
  32 #include "hardwaremanager.h"
  33 #include "ppatomfwctrl.h"
  34 #include "atomfirmware.h"
  35 #include "cgs_common.h"
  36 #include "vega12_inc.h"
  37 #include "pppcielanes.h"
  38 #include "vega12_hwmgr.h"
  39 #include "vega12_processpptables.h"
  40 #include "vega12_pptable.h"
  41 #include "vega12_thermal.h"
  42 #include "vega12_ppsmc.h"
  43 #include "pp_debug.h"
  44 #include "amd_pcie_helpers.h"
  45 #include "ppinterrupt.h"
  46 #include "pp_overdriver.h"
  47 #include "pp_thermal.h"
  48 #include "vega12_baco.h"
  49
  50 #define smnPCIE_LC_SPEED_CNTL                   0x11140290
  51 #define smnPCIE_LC_LINK_WIDTH_CNTL              0x11140288
  52
  53 #define LINK_WIDTH_MAX                          6
  54 #define LINK_SPEED_MAX                          3
  55 static const int link_width[] = {0, 1, 2, 4, 8, 12, 16};
  56 static const int link_speed[] = {25, 50, 80, 160};
  57
  58 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
  59                 enum pp_clock_type type, uint32_t mask);
  60 static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr,
  61                 uint32_t *clock,
  62                 PPCLK_e clock_select,
  63                 bool max);
  64
  65 static void vega12_set_default_registry_data(struct pp_hwmgr *hwmgr)
  66 {
  67         struct vega12_hwmgr *data =
  68                         (struct vega12_hwmgr *)(hwmgr->backend);
  69
  70         data->gfxclk_average_alpha = PPVEGA12_VEGA12GFXCLKAVERAGEALPHA_DFLT;
  71         data->socclk_average_alpha = PPVEGA12_VEGA12SOCCLKAVERAGEALPHA_DFLT;
  72         data->uclk_average_alpha = PPVEGA12_VEGA12UCLKCLKAVERAGEALPHA_DFLT;
  73         data->gfx_activity_average_alpha = PPVEGA12_VEGA12GFXACTIVITYAVERAGEALPHA_DFLT;
  74         data->lowest_uclk_reserved_for_ulv = PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT;
  75
  76         data->display_voltage_mode = PPVEGA12_VEGA12DISPLAYVOLTAGEMODE_DFLT;
  77         data->dcef_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
  78         data->dcef_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
  79         data->dcef_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
  80         data->disp_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
  81         data->disp_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
  82         data->disp_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
  83         data->pixel_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
  84         data->pixel_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
  85         data->pixel_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
  86         data->phy_clk_quad_eqn_a = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
  87         data->phy_clk_quad_eqn_b = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
  88         data->phy_clk_quad_eqn_c = PPREGKEY_VEGA12QUADRATICEQUATION_DFLT;
  89
  90         data->registry_data.disallowed_features = 0x0;
  91         data->registry_data.od_state_in_dc_support = 0;
  92         data->registry_data.thermal_support = 1;
  93         data->registry_data.skip_baco_hardware = 0;
  94
  95         data->registry_data.log_avfs_param = 0;
  96         data->registry_data.sclk_throttle_low_notification = 1;
  97         data->registry_data.force_dpm_high = 0;
  98         data->registry_data.stable_pstate_sclk_dpm_percentage = 75;
  99
 100         data->registry_data.didt_support = 0;
 101         if (data->registry_data.didt_support) {
 102                 data->registry_data.didt_mode = 6;
 103                 data->registry_data.sq_ramping_support = 1;
 104                 data->registry_data.db_ramping_support = 0;
 105                 data->registry_data.td_ramping_support = 0;
 106                 data->registry_data.tcp_ramping_support = 0;
 107                 data->registry_data.dbr_ramping_support = 0;
 108                 data->registry_data.edc_didt_support = 1;
 109                 data->registry_data.gc_didt_support = 0;
 110                 data->registry_data.psm_didt_support = 0;
 111         }
 112
 113         data->registry_data.pcie_lane_override = 0xff;
 114         data->registry_data.pcie_speed_override = 0xff;
 115         data->registry_data.pcie_clock_override = 0xffffffff;
 116         data->registry_data.regulator_hot_gpio_support = 1;
 117         data->registry_data.ac_dc_switch_gpio_support = 0;
 118         data->registry_data.quick_transition_support = 0;
 119         data->registry_data.zrpm_start_temp = 0xffff;
 120         data->registry_data.zrpm_stop_temp = 0xffff;
 121         data->registry_data.odn_feature_enable = 1;
 122         data->registry_data.disable_water_mark = 0;
 123         data->registry_data.disable_pp_tuning = 0;
 124         data->registry_data.disable_xlpp_tuning = 0;
 125         data->registry_data.disable_workload_policy = 0;
 126         data->registry_data.perf_ui_tuning_profile_turbo = 0x19190F0F;
 127         data->registry_data.perf_ui_tuning_profile_powerSave = 0x19191919;
 128         data->registry_data.perf_ui_tuning_profile_xl = 0x00000F0A;
 129         data->registry_data.force_workload_policy_mask = 0;
 130         data->registry_data.disable_3d_fs_detection = 0;
 131         data->registry_data.fps_support = 1;
 132         data->registry_data.disable_auto_wattman = 1;
 133         data->registry_data.auto_wattman_debug = 0;
 134         data->registry_data.auto_wattman_sample_period = 100;
 135         data->registry_data.auto_wattman_threshold = 50;
 136         data->registry_data.pcie_dpm_key_disabled = !(hwmgr->feature_mask & PP_PCIE_DPM_MASK);
 137 }
 138
 139 static int vega12_set_features_platform_caps(struct pp_hwmgr *hwmgr)
 140 {
 141         struct vega12_hwmgr *data =
 142                         (struct vega12_hwmgr *)(hwmgr->backend);
 143         struct amdgpu_device *adev = hwmgr->adev;
 144
 145         if (data->vddci_control == VEGA12_VOLTAGE_CONTROL_NONE)
 146                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 147                                 PHM_PlatformCaps_ControlVDDCI);
 148
 149         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 150                         PHM_PlatformCaps_TablelessHardwareInterface);
 151
 152         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 153                         PHM_PlatformCaps_EnableSMU7ThermalManagement);
 154
 155         if (adev->pg_flags & AMD_PG_SUPPORT_UVD) {
 156                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 157                                 PHM_PlatformCaps_UVDPowerGating);
 158                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 159                                 PHM_PlatformCaps_UVDDynamicPowerGating);
 160         }
 161
 162         if (adev->pg_flags & AMD_PG_SUPPORT_VCE)
 163                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 164                                 PHM_PlatformCaps_VCEPowerGating);
 165
 166         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 167                         PHM_PlatformCaps_UnTabledHardwareInterface);
 168
 169         if (data->registry_data.odn_feature_enable)
 170                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 171                                 PHM_PlatformCaps_ODNinACSupport);
 172         else {
 173                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 174                                 PHM_PlatformCaps_OD6inACSupport);
 175                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 176                                 PHM_PlatformCaps_OD6PlusinACSupport);
 177         }
 178
 179         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 180                         PHM_PlatformCaps_ActivityReporting);
 181         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 182                         PHM_PlatformCaps_FanSpeedInTableIsRPM);
 183
 184         if (data->registry_data.od_state_in_dc_support) {
 185                 if (data->registry_data.odn_feature_enable)
 186                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 187                                         PHM_PlatformCaps_ODNinDCSupport);
 188                 else {
 189                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 190                                         PHM_PlatformCaps_OD6inDCSupport);
 191                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 192                                         PHM_PlatformCaps_OD6PlusinDCSupport);
 193                 }
 194         }
 195
 196         if (data->registry_data.thermal_support
 197                         && data->registry_data.fuzzy_fan_control_support
 198                         && hwmgr->thermal_controller.advanceFanControlParameters.usTMax)
 199                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 200                                 PHM_PlatformCaps_ODFuzzyFanControlSupport);
 201
 202         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 203                                 PHM_PlatformCaps_DynamicPowerManagement);
 204         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 205                         PHM_PlatformCaps_SMC);
 206         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 207                         PHM_PlatformCaps_ThermalPolicyDelay);
 208
 209         if (data->registry_data.force_dpm_high)
 210                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 211                                 PHM_PlatformCaps_ExclusiveModeAlwaysHigh);
 212
 213         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 214                         PHM_PlatformCaps_DynamicUVDState);
 215
 216         if (data->registry_data.sclk_throttle_low_notification)
 217                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 218                                 PHM_PlatformCaps_SclkThrottleLowNotification);
 219
 220         /* power tune caps */
 221         /* assume disabled */
 222         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 223                         PHM_PlatformCaps_PowerContainment);
 224         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 225                         PHM_PlatformCaps_DiDtSupport);
 226         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 227                         PHM_PlatformCaps_SQRamping);
 228         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 229                         PHM_PlatformCaps_DBRamping);
 230         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 231                         PHM_PlatformCaps_TDRamping);
 232         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 233                         PHM_PlatformCaps_TCPRamping);
 234         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 235                         PHM_PlatformCaps_DBRRamping);
 236         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 237                         PHM_PlatformCaps_DiDtEDCEnable);
 238         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 239                         PHM_PlatformCaps_GCEDC);
 240         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 241                         PHM_PlatformCaps_PSM);
 242
 243         if (data->registry_data.didt_support) {
 244                 phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtSupport);
 245                 if (data->registry_data.sq_ramping_support)
 246                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping);
 247                 if (data->registry_data.db_ramping_support)
 248                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping);
 249                 if (data->registry_data.td_ramping_support)
 250                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping);
 251                 if (data->registry_data.tcp_ramping_support)
 252                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping);
 253                 if (data->registry_data.dbr_ramping_support)
 254                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping);
 255                 if (data->registry_data.edc_didt_support)
 256                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable);
 257                 if (data->registry_data.gc_didt_support)
 258                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC);
 259                 if (data->registry_data.psm_didt_support)
 260                         phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM);
 261         }
 262
 263         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 264                         PHM_PlatformCaps_RegulatorHot);
 265
 266         if (data->registry_data.ac_dc_switch_gpio_support) {
 267                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 268                                 PHM_PlatformCaps_AutomaticDCTransition);
 269                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 270                                 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
 271         }
 272
 273         if (data->registry_data.quick_transition_support) {
 274                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 275                                 PHM_PlatformCaps_AutomaticDCTransition);
 276                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 277                                 PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
 278                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 279                                 PHM_PlatformCaps_Falcon_QuickTransition);
 280         }
 281
 282         if (data->lowest_uclk_reserved_for_ulv != PPVEGA12_VEGA12LOWESTUCLKRESERVEDFORULV_DFLT) {
 283                 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 284                                 PHM_PlatformCaps_LowestUclkReservedForUlv);
 285                 if (data->lowest_uclk_reserved_for_ulv == 1)
 286                         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 287                                         PHM_PlatformCaps_LowestUclkReservedForUlv);
 288         }
 289
 290         if (data->registry_data.custom_fan_support)
 291                 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 292                                 PHM_PlatformCaps_CustomFanControlSupport);
 293
 294         return 0;
 295 }
 296
 297 static void vega12_init_dpm_defaults(struct pp_hwmgr *hwmgr)
 298 {
 299         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
 300         struct amdgpu_device *adev = hwmgr->adev;
 301         uint32_t top32, bottom32;
 302         int i;
 303
 304         data->smu_features[GNLD_DPM_PREFETCHER].smu_feature_id =
 305                         FEATURE_DPM_PREFETCHER_BIT;
 306         data->smu_features[GNLD_DPM_GFXCLK].smu_feature_id =
 307                         FEATURE_DPM_GFXCLK_BIT;
 308         data->smu_features[GNLD_DPM_UCLK].smu_feature_id =
 309                         FEATURE_DPM_UCLK_BIT;
 310         data->smu_features[GNLD_DPM_SOCCLK].smu_feature_id =
 311                         FEATURE_DPM_SOCCLK_BIT;
 312         data->smu_features[GNLD_DPM_UVD].smu_feature_id =
 313                         FEATURE_DPM_UVD_BIT;
 314         data->smu_features[GNLD_DPM_VCE].smu_feature_id =
 315                         FEATURE_DPM_VCE_BIT;
 316         data->smu_features[GNLD_ULV].smu_feature_id =
 317                         FEATURE_ULV_BIT;
 318         data->smu_features[GNLD_DPM_MP0CLK].smu_feature_id =
 319                         FEATURE_DPM_MP0CLK_BIT;
 320         data->smu_features[GNLD_DPM_LINK].smu_feature_id =
 321                         FEATURE_DPM_LINK_BIT;
 322         data->smu_features[GNLD_DPM_DCEFCLK].smu_feature_id =
 323                         FEATURE_DPM_DCEFCLK_BIT;
 324         data->smu_features[GNLD_DS_GFXCLK].smu_feature_id =
 325                         FEATURE_DS_GFXCLK_BIT;
 326         data->smu_features[GNLD_DS_SOCCLK].smu_feature_id =
 327                         FEATURE_DS_SOCCLK_BIT;
 328         data->smu_features[GNLD_DS_LCLK].smu_feature_id =
 329                         FEATURE_DS_LCLK_BIT;
 330         data->smu_features[GNLD_PPT].smu_feature_id =
 331                         FEATURE_PPT_BIT;
 332         data->smu_features[GNLD_TDC].smu_feature_id =
 333                         FEATURE_TDC_BIT;
 334         data->smu_features[GNLD_THERMAL].smu_feature_id =
 335                         FEATURE_THERMAL_BIT;
 336         data->smu_features[GNLD_GFX_PER_CU_CG].smu_feature_id =
 337                         FEATURE_GFX_PER_CU_CG_BIT;
 338         data->smu_features[GNLD_RM].smu_feature_id =
 339                         FEATURE_RM_BIT;
 340         data->smu_features[GNLD_DS_DCEFCLK].smu_feature_id =
 341                         FEATURE_DS_DCEFCLK_BIT;
 342         data->smu_features[GNLD_ACDC].smu_feature_id =
 343                         FEATURE_ACDC_BIT;
 344         data->smu_features[GNLD_VR0HOT].smu_feature_id =
 345                         FEATURE_VR0HOT_BIT;
 346         data->smu_features[GNLD_VR1HOT].smu_feature_id =
 347                         FEATURE_VR1HOT_BIT;
 348         data->smu_features[GNLD_FW_CTF].smu_feature_id =
 349                         FEATURE_FW_CTF_BIT;
 350         data->smu_features[GNLD_LED_DISPLAY].smu_feature_id =
 351                         FEATURE_LED_DISPLAY_BIT;
 352         data->smu_features[GNLD_FAN_CONTROL].smu_feature_id =
 353                         FEATURE_FAN_CONTROL_BIT;
 354         data->smu_features[GNLD_DIDT].smu_feature_id = FEATURE_GFX_EDC_BIT;
 355         data->smu_features[GNLD_GFXOFF].smu_feature_id = FEATURE_GFXOFF_BIT;
 356         data->smu_features[GNLD_CG].smu_feature_id = FEATURE_CG_BIT;
 357         data->smu_features[GNLD_ACG].smu_feature_id = FEATURE_ACG_BIT;
 358
 359         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 360                 data->smu_features[i].smu_feature_bitmap =
 361                         (uint64_t)(1ULL << data->smu_features[i].smu_feature_id);
 362                 data->smu_features[i].allowed =
 363                         ((data->registry_data.disallowed_features >> i) & 1) ?
 364                         false : true;
 365         }
 366
 367         /* Get the SN to turn into a Unique ID */
 368         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumTop32, &top32);
 369         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ReadSerialNumBottom32, &bottom32);
 370
 371         adev->unique_id = ((uint64_t)bottom32 << 32) | top32;
 372 }
 373
 374 static int vega12_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr)
 375 {
 376         return 0;
 377 }
 378
 379 static int vega12_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 380 {
 381         kfree(hwmgr->backend);
 382         hwmgr->backend = NULL;
 383
 384         return 0;
 385 }
 386
 387 static int vega12_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 388 {
 389         int result = 0;
 390         struct vega12_hwmgr *data;
 391         struct amdgpu_device *adev = hwmgr->adev;
 392
 393         data = kzalloc(sizeof(struct vega12_hwmgr), GFP_KERNEL);
 394         if (data == NULL)
 395                 return -ENOMEM;
 396
 397         hwmgr->backend = data;
 398
 399         vega12_set_default_registry_data(hwmgr);
 400
 401         data->disable_dpm_mask = 0xff;
 402         data->workload_mask = 0xff;
 403
 404         /* need to set voltage control types before EVV patching */
 405         data->vddc_control = VEGA12_VOLTAGE_CONTROL_NONE;
 406         data->mvdd_control = VEGA12_VOLTAGE_CONTROL_NONE;
 407         data->vddci_control = VEGA12_VOLTAGE_CONTROL_NONE;
 408
 409         data->water_marks_bitmap = 0;
 410         data->avfs_exist = false;
 411
 412         vega12_set_features_platform_caps(hwmgr);
 413
 414         vega12_init_dpm_defaults(hwmgr);
 415
 416         /* Parse pptable data read from VBIOS */
 417         vega12_set_private_data_based_on_pptable(hwmgr);
 418
 419         data->is_tlu_enabled = false;
 420
 421         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
 422                         VEGA12_MAX_HARDWARE_POWERLEVELS;
 423         hwmgr->platform_descriptor.hardwarePerformanceLevels = 2;
 424         hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
 425
 426         hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */
 427         /* The true clock step depends on the frequency, typically 4.5 or 9 MHz. Here we use 5. */
 428         hwmgr->platform_descriptor.clockStep.engineClock = 500;
 429         hwmgr->platform_descriptor.clockStep.memoryClock = 500;
 430
 431         data->total_active_cus = adev->gfx.cu_info.number;
 432         /* Setup default Overdrive Fan control settings */
 433         data->odn_fan_table.target_fan_speed =
 434                         hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM;
 435         data->odn_fan_table.target_temperature =
 436                         hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature;
 437         data->odn_fan_table.min_performance_clock =
 438                         hwmgr->thermal_controller.advanceFanControlParameters.ulMinFanSCLKAcousticLimit;
 439         data->odn_fan_table.min_fan_limit =
 440                         hwmgr->thermal_controller.advanceFanControlParameters.usFanPWMMinLimit *
 441                         hwmgr->thermal_controller.fanInfo.ulMaxRPM / 100;
 442
 443         if (hwmgr->feature_mask & PP_GFXOFF_MASK)
 444                 data->gfxoff_controlled_by_driver = true;
 445         else
 446                 data->gfxoff_controlled_by_driver = false;
 447
 448         return result;
 449 }
 450
 451 static int vega12_init_sclk_threshold(struct pp_hwmgr *hwmgr)
 452 {
 453         struct vega12_hwmgr *data =
 454                         (struct vega12_hwmgr *)(hwmgr->backend);
 455
 456         data->low_sclk_interrupt_threshold = 0;
 457
 458         return 0;
 459 }
 460
 461 static int vega12_setup_asic_task(struct pp_hwmgr *hwmgr)
 462 {
 463         PP_ASSERT_WITH_CODE(!vega12_init_sclk_threshold(hwmgr),
 464                         "Failed to init sclk threshold!",
 465                         return -EINVAL);
 466
 467         return 0;
 468 }
 469
 470 /*
 471  * @fn vega12_init_dpm_state
 472  * @brief Function to initialize all Soft Min/Max and Hard Min/Max to 0xff.
 473  *
 474  * @param    dpm_state - the address of the DPM Table to initiailize.
 475  * @return   None.
 476  */
 477 static void vega12_init_dpm_state(struct vega12_dpm_state *dpm_state)
 478 {
 479         dpm_state->soft_min_level = 0x0;
 480         dpm_state->soft_max_level = 0xffff;
 481         dpm_state->hard_min_level = 0x0;
 482         dpm_state->hard_max_level = 0xffff;
 483 }
 484
 485 static int vega12_override_pcie_parameters(struct pp_hwmgr *hwmgr)
 486 {
 487         struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);
 488         struct vega12_hwmgr *data =
 489                         (struct vega12_hwmgr *)(hwmgr->backend);
 490         uint32_t pcie_gen = 0, pcie_width = 0, smu_pcie_arg, pcie_gen_arg, pcie_width_arg;
 491         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
 492         int i;
 493         int ret;
 494
 495         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
 496                 pcie_gen = 3;
 497         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
 498                 pcie_gen = 2;
 499         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
 500                 pcie_gen = 1;
 501         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
 502                 pcie_gen = 0;
 503
 504         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
 505                 pcie_width = 6;
 506         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
 507                 pcie_width = 5;
 508         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
 509                 pcie_width = 4;
 510         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
 511                 pcie_width = 3;
 512         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
 513                 pcie_width = 2;
 514         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
 515                 pcie_width = 1;
 516
 517         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
 518          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
 519          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
 520          */
 521         for (i = 0; i < NUM_LINK_LEVELS; i++) {
 522                 pcie_gen_arg = (pp_table->PcieGenSpeed[i] > pcie_gen) ? pcie_gen :
 523                         pp_table->PcieGenSpeed[i];
 524                 pcie_width_arg = (pp_table->PcieLaneCount[i] > pcie_width) ? pcie_width :
 525                         pp_table->PcieLaneCount[i];
 526
 527                 if (pcie_gen_arg != pp_table->PcieGenSpeed[i] || pcie_width_arg !=
 528                     pp_table->PcieLaneCount[i]) {
 529                         smu_pcie_arg = (i << 16) | (pcie_gen_arg << 8) | pcie_width_arg;
 530                         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 531                                 PPSMC_MSG_OverridePcieParameters, smu_pcie_arg,
 532                                 NULL);
 533                         PP_ASSERT_WITH_CODE(!ret,
 534                                 "[OverridePcieParameters] Attempt to override pcie params failed!",
 535                                 return ret);
 536                 }
 537
 538                 /* update the pptable */
 539                 pp_table->PcieGenSpeed[i] = pcie_gen_arg;
 540                 pp_table->PcieLaneCount[i] = pcie_width_arg;
 541         }
 542
 543         /* override to the highest if it's disabled from ppfeaturmask */
 544         if (data->registry_data.pcie_dpm_key_disabled) {
 545                 for (i = 0; i < NUM_LINK_LEVELS; i++) {
 546                         smu_pcie_arg = (i << 16) | (pcie_gen << 8) | pcie_width;
 547                         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 548                                 PPSMC_MSG_OverridePcieParameters, smu_pcie_arg,
 549                                 NULL);
 550                         PP_ASSERT_WITH_CODE(!ret,
 551                                 "[OverridePcieParameters] Attempt to override pcie params failed!",
 552                                 return ret);
 553
 554                         pp_table->PcieGenSpeed[i] = pcie_gen;
 555                         pp_table->PcieLaneCount[i] = pcie_width;
 556                 }
 557                 ret = vega12_enable_smc_features(hwmgr,
 558                                 false,
 559                                 data->smu_features[GNLD_DPM_LINK].smu_feature_bitmap);
 560                 PP_ASSERT_WITH_CODE(!ret,
 561                                 "Attempt to Disable DPM LINK Failed!",
 562                                 return ret);
 563                 data->smu_features[GNLD_DPM_LINK].enabled = false;
 564                 data->smu_features[GNLD_DPM_LINK].supported = false;
 565         }
 566         return 0;
 567 }
 568
 569 static int vega12_get_number_of_dpm_level(struct pp_hwmgr *hwmgr,
 570                 PPCLK_e clk_id, uint32_t *num_of_levels)
 571 {
 572         int ret = 0;
 573
 574         ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 575                         PPSMC_MSG_GetDpmFreqByIndex,
 576                         (clk_id << 16 | 0xFF),
 577                         num_of_levels);
 578         PP_ASSERT_WITH_CODE(!ret,
 579                         "[GetNumOfDpmLevel] failed to get dpm levels!",
 580                         return ret);
 581
 582         return ret;
 583 }
 584
 585 static int vega12_get_dpm_frequency_by_index(struct pp_hwmgr *hwmgr,
 586                 PPCLK_e clkID, uint32_t index, uint32_t *clock)
 587 {
 588         /*
 589          *SMU expects the Clock ID to be in the top 16 bits.
 590          *Lower 16 bits specify the level
 591          */
 592         PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
 593                 PPSMC_MSG_GetDpmFreqByIndex, (clkID << 16 | index),
 594                 clock) == 0,
 595                 "[GetDpmFrequencyByIndex] Failed to get dpm frequency from SMU!",
 596                 return -EINVAL);
 597
 598         return 0;
 599 }
 600
 601 static int vega12_setup_single_dpm_table(struct pp_hwmgr *hwmgr,
 602                 struct vega12_single_dpm_table *dpm_table, PPCLK_e clk_id)
 603 {
 604         int ret = 0;
 605         uint32_t i, num_of_levels, clk;
 606
 607         ret = vega12_get_number_of_dpm_level(hwmgr, clk_id, &num_of_levels);
 608         PP_ASSERT_WITH_CODE(!ret,
 609                         "[SetupSingleDpmTable] failed to get clk levels!",
 610                         return ret);
 611
 612         dpm_table->count = num_of_levels;
 613
 614         for (i = 0; i < num_of_levels; i++) {
 615                 ret = vega12_get_dpm_frequency_by_index(hwmgr, clk_id, i, &clk);
 616                 PP_ASSERT_WITH_CODE(!ret,
 617                         "[SetupSingleDpmTable] failed to get clk of specific level!",
 618                         return ret);
 619                 dpm_table->dpm_levels[i].value = clk;
 620                 dpm_table->dpm_levels[i].enabled = true;
 621         }
 622
 623         return ret;
 624 }
 625
 626 /*
 627  * This function is to initialize all DPM state tables
 628  * for SMU based on the dependency table.
 629  * Dynamic state patching function will then trim these
 630  * state tables to the allowed range based
 631  * on the power policy or external client requests,
 632  * such as UVD request, etc.
 633  */
 634 static int vega12_setup_default_dpm_tables(struct pp_hwmgr *hwmgr)
 635 {
 636
 637         struct vega12_hwmgr *data =
 638                         (struct vega12_hwmgr *)(hwmgr->backend);
 639         struct vega12_single_dpm_table *dpm_table;
 640         int ret = 0;
 641
 642         memset(&data->dpm_table, 0, sizeof(data->dpm_table));
 643
 644         /* socclk */
 645         dpm_table = &(data->dpm_table.soc_table);
 646         if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
 647                 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_SOCCLK);
 648                 PP_ASSERT_WITH_CODE(!ret,
 649                                 "[SetupDefaultDpmTable] failed to get socclk dpm levels!",
 650                                 return ret);
 651         } else {
 652                 dpm_table->count = 1;
 653                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.soc_clock / 100;
 654         }
 655         vega12_init_dpm_state(&(dpm_table->dpm_state));
 656
 657         /* gfxclk */
 658         dpm_table = &(data->dpm_table.gfx_table);
 659         if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
 660                 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_GFXCLK);
 661                 PP_ASSERT_WITH_CODE(!ret,
 662                                 "[SetupDefaultDpmTable] failed to get gfxclk dpm levels!",
 663                                 return ret);
 664         } else {
 665                 dpm_table->count = 1;
 666                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.gfx_clock / 100;
 667         }
 668         vega12_init_dpm_state(&(dpm_table->dpm_state));
 669
 670         /* memclk */
 671         dpm_table = &(data->dpm_table.mem_table);
 672         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
 673                 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK);
 674                 PP_ASSERT_WITH_CODE(!ret,
 675                                 "[SetupDefaultDpmTable] failed to get memclk dpm levels!",
 676                                 return ret);
 677         } else {
 678                 dpm_table->count = 1;
 679                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.mem_clock / 100;
 680         }
 681         vega12_init_dpm_state(&(dpm_table->dpm_state));
 682
 683         /* eclk */
 684         dpm_table = &(data->dpm_table.eclk_table);
 685         if (data->smu_features[GNLD_DPM_VCE].enabled) {
 686                 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_ECLK);
 687                 PP_ASSERT_WITH_CODE(!ret,
 688                                 "[SetupDefaultDpmTable] failed to get eclk dpm levels!",
 689                                 return ret);
 690         } else {
 691                 dpm_table->count = 1;
 692                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.eclock / 100;
 693         }
 694         vega12_init_dpm_state(&(dpm_table->dpm_state));
 695
 696         /* vclk */
 697         dpm_table = &(data->dpm_table.vclk_table);
 698         if (data->smu_features[GNLD_DPM_UVD].enabled) {
 699                 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_VCLK);
 700                 PP_ASSERT_WITH_CODE(!ret,
 701                                 "[SetupDefaultDpmTable] failed to get vclk dpm levels!",
 702                                 return ret);
 703         } else {
 704                 dpm_table->count = 1;
 705                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.vclock / 100;
 706         }
 707         vega12_init_dpm_state(&(dpm_table->dpm_state));
 708
 709         /* dclk */
 710         dpm_table = &(data->dpm_table.dclk_table);
 711         if (data->smu_features[GNLD_DPM_UVD].enabled) {
 712                 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCLK);
 713                 PP_ASSERT_WITH_CODE(!ret,
 714                                 "[SetupDefaultDpmTable] failed to get dclk dpm levels!",
 715                                 return ret);
 716         } else {
 717                 dpm_table->count = 1;
 718                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dclock / 100;
 719         }
 720         vega12_init_dpm_state(&(dpm_table->dpm_state));
 721
 722         /* dcefclk */
 723         dpm_table = &(data->dpm_table.dcef_table);
 724         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 725                 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DCEFCLK);
 726                 PP_ASSERT_WITH_CODE(!ret,
 727                                 "[SetupDefaultDpmTable] failed to get dcefclk dpm levels!",
 728                                 return ret);
 729         } else {
 730                 dpm_table->count = 1;
 731                 dpm_table->dpm_levels[0].value = data->vbios_boot_state.dcef_clock / 100;
 732         }
 733         vega12_init_dpm_state(&(dpm_table->dpm_state));
 734
 735         /* pixclk */
 736         dpm_table = &(data->dpm_table.pixel_table);
 737         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 738                 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PIXCLK);
 739                 PP_ASSERT_WITH_CODE(!ret,
 740                                 "[SetupDefaultDpmTable] failed to get pixclk dpm levels!",
 741                                 return ret);
 742         } else
 743                 dpm_table->count = 0;
 744         vega12_init_dpm_state(&(dpm_table->dpm_state));
 745
 746         /* dispclk */
 747         dpm_table = &(data->dpm_table.display_table);
 748         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 749                 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_DISPCLK);
 750                 PP_ASSERT_WITH_CODE(!ret,
 751                                 "[SetupDefaultDpmTable] failed to get dispclk dpm levels!",
 752                                 return ret);
 753         } else
 754                 dpm_table->count = 0;
 755         vega12_init_dpm_state(&(dpm_table->dpm_state));
 756
 757         /* phyclk */
 758         dpm_table = &(data->dpm_table.phy_table);
 759         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
 760                 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_PHYCLK);
 761                 PP_ASSERT_WITH_CODE(!ret,
 762                                 "[SetupDefaultDpmTable] failed to get phyclk dpm levels!",
 763                                 return ret);
 764         } else
 765                 dpm_table->count = 0;
 766         vega12_init_dpm_state(&(dpm_table->dpm_state));
 767
 768         /* save a copy of the default DPM table */
 769         memcpy(&(data->golden_dpm_table), &(data->dpm_table),
 770                         sizeof(struct vega12_dpm_table));
 771
 772         return 0;
 773 }
 774
 775 #if 0
 776 static int vega12_save_default_power_profile(struct pp_hwmgr *hwmgr)
 777 {
 778         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
 779         struct vega12_single_dpm_table *dpm_table = &(data->dpm_table.gfx_table);
 780         uint32_t min_level;
 781
 782         hwmgr->default_gfx_power_profile.type = AMD_PP_GFX_PROFILE;
 783         hwmgr->default_compute_power_profile.type = AMD_PP_COMPUTE_PROFILE;
 784
 785         /* Optimize compute power profile: Use only highest
 786          * 2 power levels (if more than 2 are available)
 787          */
 788         if (dpm_table->count > 2)
 789                 min_level = dpm_table->count - 2;
 790         else if (dpm_table->count == 2)
 791                 min_level = 1;
 792         else
 793                 min_level = 0;
 794
 795         hwmgr->default_compute_power_profile.min_sclk =
 796                         dpm_table->dpm_levels[min_level].value;
 797
 798         hwmgr->gfx_power_profile = hwmgr->default_gfx_power_profile;
 799         hwmgr->compute_power_profile = hwmgr->default_compute_power_profile;
 800
 801         return 0;
 802 }
 803 #endif
 804
 805 /**
 806  * vega12_init_smc_table - Initializes the SMC table and uploads it
 807  *
 808  * @hwmgr:  the address of the powerplay hardware manager.
 809  * return:  always 0
 810  */
 811 static int vega12_init_smc_table(struct pp_hwmgr *hwmgr)
 812 {
 813         int result;
 814         struct vega12_hwmgr *data =
 815                         (struct vega12_hwmgr *)(hwmgr->backend);
 816         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
 817         struct pp_atomfwctrl_bios_boot_up_values boot_up_values;
 818         struct phm_ppt_v3_information *pptable_information =
 819                 (struct phm_ppt_v3_information *)hwmgr->pptable;
 820
 821         result = pp_atomfwctrl_get_vbios_bootup_values(hwmgr, &boot_up_values);
 822         if (!result) {
 823                 data->vbios_boot_state.vddc     = boot_up_values.usVddc;
 824                 data->vbios_boot_state.vddci    = boot_up_values.usVddci;
 825                 data->vbios_boot_state.mvddc    = boot_up_values.usMvddc;
 826                 data->vbios_boot_state.gfx_clock = boot_up_values.ulGfxClk;
 827                 data->vbios_boot_state.mem_clock = boot_up_values.ulUClk;
 828                 data->vbios_boot_state.soc_clock = boot_up_values.ulSocClk;
 829                 data->vbios_boot_state.dcef_clock = boot_up_values.ulDCEFClk;
 830                 data->vbios_boot_state.uc_cooling_id = boot_up_values.ucCoolingID;
 831                 data->vbios_boot_state.eclock = boot_up_values.ulEClk;
 832                 data->vbios_boot_state.dclock = boot_up_values.ulDClk;
 833                 data->vbios_boot_state.vclock = boot_up_values.ulVClk;
 834                 smum_send_msg_to_smc_with_parameter(hwmgr,
 835                                 PPSMC_MSG_SetMinDeepSleepDcefclk,
 836                         (uint32_t)(data->vbios_boot_state.dcef_clock / 100),
 837                                 NULL);
 838         }
 839
 840         memcpy(pp_table, pptable_information->smc_pptable, sizeof(PPTable_t));
 841
 842         result = smum_smc_table_manager(hwmgr,
 843                                         (uint8_t *)pp_table, TABLE_PPTABLE, false);
 844         PP_ASSERT_WITH_CODE(!result,
 845                         "Failed to upload PPtable!", return result);
 846
 847         return 0;
 848 }
 849
 850 static int vega12_run_acg_btc(struct pp_hwmgr *hwmgr)
 851 {
 852         uint32_t result;
 853
 854         PP_ASSERT_WITH_CODE(
 855                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_RunAcgBtc, &result) == 0,
 856                 "[Run_ACG_BTC] Attempt to run ACG BTC failed!",
 857                 return -EINVAL);
 858
 859         PP_ASSERT_WITH_CODE(result == 1,
 860                         "Failed to run ACG BTC!", return -EINVAL);
 861
 862         return 0;
 863 }
 864
 865 static int vega12_set_allowed_featuresmask(struct pp_hwmgr *hwmgr)
 866 {
 867         struct vega12_hwmgr *data =
 868                         (struct vega12_hwmgr *)(hwmgr->backend);
 869         int i;
 870         uint32_t allowed_features_low = 0, allowed_features_high = 0;
 871
 872         for (i = 0; i < GNLD_FEATURES_MAX; i++)
 873                 if (data->smu_features[i].allowed)
 874                         data->smu_features[i].smu_feature_id > 31 ?
 875                                 (allowed_features_high |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_HIGH_SHIFT) & 0xFFFFFFFF)) :
 876                                 (allowed_features_low |= ((data->smu_features[i].smu_feature_bitmap >> SMU_FEATURES_LOW_SHIFT) & 0xFFFFFFFF));
 877
 878         PP_ASSERT_WITH_CODE(
 879                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskHigh, allowed_features_high,
 880                         NULL) == 0,
 881                 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (high) failed!",
 882                 return -1);
 883
 884         PP_ASSERT_WITH_CODE(
 885                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetAllowedFeaturesMaskLow, allowed_features_low,
 886                         NULL) == 0,
 887                 "[SetAllowedFeaturesMask] Attempt to set allowed features mask (low) failed!",
 888                 return -1);
 889
 890         return 0;
 891 }
 892
 893 static void vega12_init_powergate_state(struct pp_hwmgr *hwmgr)
 894 {
 895         struct vega12_hwmgr *data =
 896                         (struct vega12_hwmgr *)(hwmgr->backend);
 897
 898         data->uvd_power_gated = true;
 899         data->vce_power_gated = true;
 900
 901         if (data->smu_features[GNLD_DPM_UVD].enabled)
 902                 data->uvd_power_gated = false;
 903
 904         if (data->smu_features[GNLD_DPM_VCE].enabled)
 905                 data->vce_power_gated = false;
 906 }
 907
 908 static int vega12_enable_all_smu_features(struct pp_hwmgr *hwmgr)
 909 {
 910         struct vega12_hwmgr *data =
 911                         (struct vega12_hwmgr *)(hwmgr->backend);
 912         uint64_t features_enabled;
 913         int i;
 914         bool enabled;
 915
 916         PP_ASSERT_WITH_CODE(
 917                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableAllSmuFeatures, NULL) == 0,
 918                 "[EnableAllSMUFeatures] Failed to enable all smu features!",
 919                 return -1);
 920
 921         if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) {
 922                 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 923                         enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false;
 924                         data->smu_features[i].enabled = enabled;
 925                         data->smu_features[i].supported = enabled;
 926                 }
 927         }
 928
 929         vega12_init_powergate_state(hwmgr);
 930
 931         return 0;
 932 }
 933
 934 static int vega12_disable_all_smu_features(struct pp_hwmgr *hwmgr)
 935 {
 936         struct vega12_hwmgr *data =
 937                         (struct vega12_hwmgr *)(hwmgr->backend);
 938         uint64_t features_enabled;
 939         int i;
 940         bool enabled;
 941
 942         PP_ASSERT_WITH_CODE(
 943                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableAllSmuFeatures, NULL) == 0,
 944                 "[DisableAllSMUFeatures] Failed to disable all smu features!",
 945                 return -1);
 946
 947         if (vega12_get_enabled_smc_features(hwmgr, &features_enabled) == 0) {
 948                 for (i = 0; i < GNLD_FEATURES_MAX; i++) {
 949                         enabled = (features_enabled & data->smu_features[i].smu_feature_bitmap) ? true : false;
 950                         data->smu_features[i].enabled = enabled;
 951                         data->smu_features[i].supported = enabled;
 952                 }
 953         }
 954
 955         return 0;
 956 }
 957
 958 static int vega12_odn_initialize_default_settings(
 959                 struct pp_hwmgr *hwmgr)
 960 {
 961         return 0;
 962 }
 963
 964 static int vega12_set_overdrive_target_percentage(struct pp_hwmgr *hwmgr,
 965                 uint32_t adjust_percent)
 966 {
 967         return smum_send_msg_to_smc_with_parameter(hwmgr,
 968                         PPSMC_MSG_OverDriveSetPercentage, adjust_percent,
 969                         NULL);
 970 }
 971
 972 static int vega12_power_control_set_level(struct pp_hwmgr *hwmgr)
 973 {
 974         int adjust_percent, result = 0;
 975
 976         if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
 977                 adjust_percent =
 978                                 hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
 979                                 hwmgr->platform_descriptor.TDPAdjustment :
 980                                 (-1 * hwmgr->platform_descriptor.TDPAdjustment);
 981                 result = vega12_set_overdrive_target_percentage(hwmgr,
 982                                 (uint32_t)adjust_percent);
 983         }
 984         return result;
 985 }
 986
 987 static int vega12_get_all_clock_ranges_helper(struct pp_hwmgr *hwmgr,
 988                 PPCLK_e clkid, struct vega12_clock_range *clock)
 989 {
 990         /* AC Max */
 991         PP_ASSERT_WITH_CODE(
 992                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMaxDpmFreq, (clkid << 16),
 993                         &(clock->ACMax)) == 0,
 994                 "[GetClockRanges] Failed to get max ac clock from SMC!",
 995                 return -EINVAL);
 996
 997         /* AC Min */
 998         PP_ASSERT_WITH_CODE(
 999                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetMinDpmFreq, (clkid << 16),
1000                         &(clock->ACMin)) == 0,
1001                 "[GetClockRanges] Failed to get min ac clock from SMC!",
1002                 return -EINVAL);
1003
1004         /* DC Max */
1005         PP_ASSERT_WITH_CODE(
1006                 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDcModeMaxDpmFreq, (clkid << 16),
1007                         &(clock->DCMax)) == 0,
1008                 "[GetClockRanges] Failed to get max dc clock from SMC!",
1009                 return -EINVAL);
1010
1011         return 0;
1012 }
1013
1014 static int vega12_get_all_clock_ranges(struct pp_hwmgr *hwmgr)
1015 {
1016         struct vega12_hwmgr *data =
1017                         (struct vega12_hwmgr *)(hwmgr->backend);
1018         uint32_t i;
1019
1020         for (i = 0; i < PPCLK_COUNT; i++)
1021                 PP_ASSERT_WITH_CODE(!vega12_get_all_clock_ranges_helper(hwmgr,
1022                                         i, &(data->clk_range[i])),
1023                                 "Failed to get clk range from SMC!",
1024                                 return -EINVAL);
1025
1026         return 0;
1027 }
1028
1029 static int vega12_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
1030 {
1031         int tmp_result, result = 0;
1032
1033         smum_send_msg_to_smc_with_parameter(hwmgr,
1034                         PPSMC_MSG_NumOfDisplays, 0, NULL);
1035
1036         result = vega12_set_allowed_featuresmask(hwmgr);
1037         PP_ASSERT_WITH_CODE(result == 0,
1038                         "[EnableDPMTasks] Failed to set allowed featuresmask!\n",
1039                         return result);
1040
1041         tmp_result = vega12_init_smc_table(hwmgr);
1042         PP_ASSERT_WITH_CODE(!tmp_result,
1043                         "Failed to initialize SMC table!",
1044                         result = tmp_result);
1045
1046         tmp_result = vega12_run_acg_btc(hwmgr);
1047         PP_ASSERT_WITH_CODE(!tmp_result,
1048                         "Failed to run ACG BTC!",
1049                         result = tmp_result);
1050
1051         result = vega12_enable_all_smu_features(hwmgr);
1052         PP_ASSERT_WITH_CODE(!result,
1053                         "Failed to enable all smu features!",
1054                         return result);
1055
1056         result = vega12_override_pcie_parameters(hwmgr);
1057         PP_ASSERT_WITH_CODE(!result,
1058                         "[EnableDPMTasks] Failed to override pcie parameters!",
1059                         return result);
1060
1061         tmp_result = vega12_power_control_set_level(hwmgr);
1062         PP_ASSERT_WITH_CODE(!tmp_result,
1063                         "Failed to power control set level!",
1064                         result = tmp_result);
1065
1066         result = vega12_get_all_clock_ranges(hwmgr);
1067         PP_ASSERT_WITH_CODE(!result,
1068                         "Failed to get all clock ranges!",
1069                         return result);
1070
1071         result = vega12_odn_initialize_default_settings(hwmgr);
1072         PP_ASSERT_WITH_CODE(!result,
1073                         "Failed to power control set level!",
1074                         return result);
1075
1076         result = vega12_setup_default_dpm_tables(hwmgr);
1077         PP_ASSERT_WITH_CODE(!result,
1078                         "Failed to setup default DPM tables!",
1079                         return result);
1080         return result;
1081 }
1082
1083 static int vega12_patch_boot_state(struct pp_hwmgr *hwmgr,
1084              struct pp_hw_power_state *hw_ps)
1085 {
1086         return 0;
1087 }
1088
1089 static uint32_t vega12_find_lowest_dpm_level(
1090                 struct vega12_single_dpm_table *table)
1091 {
1092         uint32_t i;
1093
1094         for (i = 0; i < table->count; i++) {
1095                 if (table->dpm_levels[i].enabled)
1096                         break;
1097         }
1098
1099         if (i >= table->count) {
1100                 i = 0;
1101                 table->dpm_levels[i].enabled = true;
1102         }
1103
1104         return i;
1105 }
1106
1107 static uint32_t vega12_find_highest_dpm_level(
1108                 struct vega12_single_dpm_table *table)
1109 {
1110         int32_t i = 0;
1111         PP_ASSERT_WITH_CODE(table->count <= MAX_REGULAR_DPM_NUMBER,
1112                         "[FindHighestDPMLevel] DPM Table has too many entries!",
1113                         return MAX_REGULAR_DPM_NUMBER - 1);
1114
1115         for (i = table->count - 1; i >= 0; i--) {
1116                 if (table->dpm_levels[i].enabled)
1117                         break;
1118         }
1119
1120         if (i < 0) {
1121                 i = 0;
1122                 table->dpm_levels[i].enabled = true;
1123         }
1124
1125         return (uint32_t)i;
1126 }
1127
1128 static int vega12_upload_dpm_min_level(struct pp_hwmgr *hwmgr)
1129 {
1130         struct vega12_hwmgr *data = hwmgr->backend;
1131         uint32_t min_freq;
1132         int ret = 0;
1133
1134         if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1135                 min_freq = data->dpm_table.gfx_table.dpm_state.soft_min_level;
1136                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1137                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1138                                         (PPCLK_GFXCLK << 16) | (min_freq & 0xffff),
1139                                         NULL)),
1140                                         "Failed to set soft min gfxclk !",
1141                                         return ret);
1142         }
1143
1144         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1145                 min_freq = data->dpm_table.mem_table.dpm_state.soft_min_level;
1146                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1147                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1148                                         (PPCLK_UCLK << 16) | (min_freq & 0xffff),
1149                                         NULL)),
1150                                         "Failed to set soft min memclk !",
1151                                         return ret);
1152
1153                 min_freq = data->dpm_table.mem_table.dpm_state.hard_min_level;
1154                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1155                                         hwmgr, PPSMC_MSG_SetHardMinByFreq,
1156                                         (PPCLK_UCLK << 16) | (min_freq & 0xffff),
1157                                         NULL)),
1158                                         "Failed to set hard min memclk !",
1159                                         return ret);
1160         }
1161
1162         if (data->smu_features[GNLD_DPM_UVD].enabled) {
1163                 min_freq = data->dpm_table.vclk_table.dpm_state.soft_min_level;
1164
1165                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1166                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1167                                         (PPCLK_VCLK << 16) | (min_freq & 0xffff),
1168                                         NULL)),
1169                                         "Failed to set soft min vclk!",
1170                                         return ret);
1171
1172                 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level;
1173
1174                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1175                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1176                                         (PPCLK_DCLK << 16) | (min_freq & 0xffff),
1177                                         NULL)),
1178                                         "Failed to set soft min dclk!",
1179                                         return ret);
1180         }
1181
1182         if (data->smu_features[GNLD_DPM_VCE].enabled) {
1183                 min_freq = data->dpm_table.eclk_table.dpm_state.soft_min_level;
1184
1185                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1186                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1187                                         (PPCLK_ECLK << 16) | (min_freq & 0xffff),
1188                                         NULL)),
1189                                         "Failed to set soft min eclk!",
1190                                         return ret);
1191         }
1192
1193         if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
1194                 min_freq = data->dpm_table.soc_table.dpm_state.soft_min_level;
1195
1196                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1197                                         hwmgr, PPSMC_MSG_SetSoftMinByFreq,
1198                                         (PPCLK_SOCCLK << 16) | (min_freq & 0xffff),
1199                                         NULL)),
1200                                         "Failed to set soft min socclk!",
1201                                         return ret);
1202         }
1203
1204         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1205                 min_freq = data->dpm_table.dcef_table.dpm_state.hard_min_level;
1206
1207                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1208                                         hwmgr, PPSMC_MSG_SetHardMinByFreq,
1209                                         (PPCLK_DCEFCLK << 16) | (min_freq & 0xffff),
1210                                         NULL)),
1211                                         "Failed to set hard min dcefclk!",
1212                                         return ret);
1213         }
1214
1215         return ret;
1216
1217 }
1218
1219 static int vega12_upload_dpm_max_level(struct pp_hwmgr *hwmgr)
1220 {
1221         struct vega12_hwmgr *data = hwmgr->backend;
1222         uint32_t max_freq;
1223         int ret = 0;
1224
1225         if (data->smu_features[GNLD_DPM_GFXCLK].enabled) {
1226                 max_freq = data->dpm_table.gfx_table.dpm_state.soft_max_level;
1227
1228                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1229                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1230                                         (PPCLK_GFXCLK << 16) | (max_freq & 0xffff),
1231                                         NULL)),
1232                                         "Failed to set soft max gfxclk!",
1233                                         return ret);
1234         }
1235
1236         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
1237                 max_freq = data->dpm_table.mem_table.dpm_state.soft_max_level;
1238
1239                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1240                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1241                                         (PPCLK_UCLK << 16) | (max_freq & 0xffff),
1242                                         NULL)),
1243                                         "Failed to set soft max memclk!",
1244                                         return ret);
1245         }
1246
1247         if (data->smu_features[GNLD_DPM_UVD].enabled) {
1248                 max_freq = data->dpm_table.vclk_table.dpm_state.soft_max_level;
1249
1250                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1251                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1252                                         (PPCLK_VCLK << 16) | (max_freq & 0xffff),
1253                                         NULL)),
1254                                         "Failed to set soft max vclk!",
1255                                         return ret);
1256
1257                 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level;
1258                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1259                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1260                                         (PPCLK_DCLK << 16) | (max_freq & 0xffff),
1261                                         NULL)),
1262                                         "Failed to set soft max dclk!",
1263                                         return ret);
1264         }
1265
1266         if (data->smu_features[GNLD_DPM_VCE].enabled) {
1267                 max_freq = data->dpm_table.eclk_table.dpm_state.soft_max_level;
1268
1269                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1270                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1271                                         (PPCLK_ECLK << 16) | (max_freq & 0xffff),
1272                                         NULL)),
1273                                         "Failed to set soft max eclk!",
1274                                         return ret);
1275         }
1276
1277         if (data->smu_features[GNLD_DPM_SOCCLK].enabled) {
1278                 max_freq = data->dpm_table.soc_table.dpm_state.soft_max_level;
1279
1280                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(
1281                                         hwmgr, PPSMC_MSG_SetSoftMaxByFreq,
1282                                         (PPCLK_SOCCLK << 16) | (max_freq & 0xffff),
1283                                         NULL)),
1284                                         "Failed to set soft max socclk!",
1285                                         return ret);
1286         }
1287
1288         return ret;
1289 }
1290
1291 int vega12_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
1292 {
1293         struct vega12_hwmgr *data =
1294                         (struct vega12_hwmgr *)(hwmgr->backend);
1295
1296         if (data->smu_features[GNLD_DPM_VCE].supported) {
1297                 PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,
1298                                 enable,
1299                                 data->smu_features[GNLD_DPM_VCE].smu_feature_bitmap),
1300                                 "Attempt to Enable/Disable DPM VCE Failed!",
1301                                 return -1);
1302                 data->smu_features[GNLD_DPM_VCE].enabled = enable;
1303         }
1304
1305         return 0;
1306 }
1307
1308 static uint32_t vega12_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
1309 {
1310         struct vega12_hwmgr *data =
1311                         (struct vega12_hwmgr *)(hwmgr->backend);
1312         uint32_t gfx_clk;
1313
1314         if (!data->smu_features[GNLD_DPM_GFXCLK].enabled)
1315                 return -1;
1316
1317         if (low)
1318                 PP_ASSERT_WITH_CODE(
1319                         vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, false) == 0,
1320                         "[GetSclks]: fail to get min PPCLK_GFXCLK\n",
1321                         return -1);
1322         else
1323                 PP_ASSERT_WITH_CODE(
1324                         vega12_get_clock_ranges(hwmgr, &gfx_clk, PPCLK_GFXCLK, true) == 0,
1325                         "[GetSclks]: fail to get max PPCLK_GFXCLK\n",
1326                         return -1);
1327
1328         return (gfx_clk * 100);
1329 }
1330
1331 static uint32_t vega12_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
1332 {
1333         struct vega12_hwmgr *data =
1334                         (struct vega12_hwmgr *)(hwmgr->backend);
1335         uint32_t mem_clk;
1336
1337         if (!data->smu_features[GNLD_DPM_UCLK].enabled)
1338                 return -1;
1339
1340         if (low)
1341                 PP_ASSERT_WITH_CODE(
1342                         vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false) == 0,
1343                         "[GetMclks]: fail to get min PPCLK_UCLK\n",
1344                         return -1);
1345         else
1346                 PP_ASSERT_WITH_CODE(
1347                         vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true) == 0,
1348                         "[GetMclks]: fail to get max PPCLK_UCLK\n",
1349                         return -1);
1350
1351         return (mem_clk * 100);
1352 }
1353
1354 static int vega12_get_metrics_table(struct pp_hwmgr *hwmgr,
1355                                     SmuMetrics_t *metrics_table,
1356                                     bool bypass_cache)
1357 {
1358         struct vega12_hwmgr *data =
1359                         (struct vega12_hwmgr *)(hwmgr->backend);
1360         int ret = 0;
1361
1362         if (bypass_cache ||
1363             !data->metrics_time ||
1364             time_after(jiffies, data->metrics_time + msecs_to_jiffies(1))) {
1365                 ret = smum_smc_table_manager(hwmgr,
1366                                              (uint8_t *)(&data->metrics_table),
1367                                              TABLE_SMU_METRICS,
1368                                              true);
1369                 if (ret) {
1370                         pr_info("Failed to export SMU metrics table!\n");
1371                         return ret;
1372                 }
1373                 data->metrics_time = jiffies;
1374         }
1375
1376         if (metrics_table)
1377                 memcpy(metrics_table, &data->metrics_table, sizeof(SmuMetrics_t));
1378
1379         return ret;
1380 }
1381
1382 static int vega12_get_gpu_power(struct pp_hwmgr *hwmgr, uint32_t *query)
1383 {
1384         SmuMetrics_t metrics_table;
1385         int ret = 0;
1386
1387         ret = vega12_get_metrics_table(hwmgr, &metrics_table, false);
1388         if (ret)
1389                 return ret;
1390
1391         *query = metrics_table.CurrSocketPower << 8;
1392
1393         return ret;
1394 }
1395
1396 static int vega12_get_current_gfx_clk_freq(struct pp_hwmgr *hwmgr, uint32_t *gfx_freq)
1397 {
1398         uint32_t gfx_clk = 0;
1399
1400         *gfx_freq = 0;
1401
1402         PP_ASSERT_WITH_CODE(smum_send_msg_to_smc_with_parameter(hwmgr,
1403                         PPSMC_MSG_GetDpmClockFreq, (PPCLK_GFXCLK << 16),
1404                         &gfx_clk) == 0,
1405                         "[GetCurrentGfxClkFreq] Attempt to get Current GFXCLK Frequency Failed!",
1406                         return -EINVAL);
1407
1408         *gfx_freq = gfx_clk * 100;
1409
1410         return 0;
1411 }
1412
1413 static int vega12_get_current_mclk_freq(struct pp_hwmgr *hwmgr, uint32_t *mclk_freq)
1414 {
1415         uint32_t mem_clk = 0;
1416
1417         *mclk_freq = 0;
1418
1419         PP_ASSERT_WITH_CODE(
1420                         smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDpmClockFreq, (PPCLK_UCLK << 16),
1421                                 &mem_clk) == 0,
1422                         "[GetCurrentMClkFreq] Attempt to get Current MCLK Frequency Failed!",
1423                         return -EINVAL);
1424
1425         *mclk_freq = mem_clk * 100;
1426
1427         return 0;
1428 }
1429
1430 static int vega12_get_current_activity_percent(
1431                 struct pp_hwmgr *hwmgr,
1432                 int idx,
1433                 uint32_t *activity_percent)
1434 {
1435         SmuMetrics_t metrics_table;
1436         int ret = 0;
1437
1438         ret = vega12_get_metrics_table(hwmgr, &metrics_table, false);
1439         if (ret)
1440                 return ret;
1441
1442         switch (idx) {
1443         case AMDGPU_PP_SENSOR_GPU_LOAD:
1444                 *activity_percent = metrics_table.AverageGfxActivity;
1445                 break;
1446         case AMDGPU_PP_SENSOR_MEM_LOAD:
1447                 *activity_percent = metrics_table.AverageUclkActivity;
1448                 break;
1449         default:
1450                 pr_err("Invalid index for retrieving clock activity\n");
1451                 return -EINVAL;
1452         }
1453
1454         return ret;
1455 }
1456
1457 static int vega12_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1458                               void *value, int *size)
1459 {
1460         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1461         SmuMetrics_t metrics_table;
1462         int ret = 0;
1463
1464         switch (idx) {
1465         case AMDGPU_PP_SENSOR_GFX_SCLK:
1466                 ret = vega12_get_current_gfx_clk_freq(hwmgr, (uint32_t *)value);
1467                 if (!ret)
1468                         *size = 4;
1469                 break;
1470         case AMDGPU_PP_SENSOR_GFX_MCLK:
1471                 ret = vega12_get_current_mclk_freq(hwmgr, (uint32_t *)value);
1472                 if (!ret)
1473                         *size = 4;
1474                 break;
1475         case AMDGPU_PP_SENSOR_GPU_LOAD:
1476         case AMDGPU_PP_SENSOR_MEM_LOAD:
1477                 ret = vega12_get_current_activity_percent(hwmgr, idx, (uint32_t *)value);
1478                 if (!ret)
1479                         *size = 4;
1480                 break;
1481         case AMDGPU_PP_SENSOR_GPU_TEMP:
1482                 *((uint32_t *)value) = vega12_thermal_get_temperature(hwmgr);
1483                 *size = 4;
1484                 break;
1485         case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1486                 ret = vega12_get_metrics_table(hwmgr, &metrics_table, false);
1487                 if (ret)
1488                         return ret;
1489
1490                 *((uint32_t *)value) = metrics_table.TemperatureHotspot *
1491                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1492                 *size = 4;
1493                 break;
1494         case AMDGPU_PP_SENSOR_MEM_TEMP:
1495                 ret = vega12_get_metrics_table(hwmgr, &metrics_table, false);
1496                 if (ret)
1497                         return ret;
1498
1499                 *((uint32_t *)value) = metrics_table.TemperatureHBM *
1500                         PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1501                 *size = 4;
1502                 break;
1503         case AMDGPU_PP_SENSOR_UVD_POWER:
1504                 *((uint32_t *)value) = data->uvd_power_gated ? 0 : 1;
1505                 *size = 4;
1506                 break;
1507         case AMDGPU_PP_SENSOR_VCE_POWER:
1508                 *((uint32_t *)value) = data->vce_power_gated ? 0 : 1;
1509                 *size = 4;
1510                 break;
1511         case AMDGPU_PP_SENSOR_GPU_POWER:
1512                 ret = vega12_get_gpu_power(hwmgr, (uint32_t *)value);
1513                 if (!ret)
1514                         *size = 4;
1515                 break;
1516         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
1517                 ret = vega12_get_enabled_smc_features(hwmgr, (uint64_t *)value);
1518                 if (!ret)
1519                         *size = 8;
1520                 break;
1521         default:
1522                 ret = -EOPNOTSUPP;
1523                 break;
1524         }
1525         return ret;
1526 }
1527
1528 static int vega12_notify_smc_display_change(struct pp_hwmgr *hwmgr,
1529                 bool has_disp)
1530 {
1531         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1532
1533         if (data->smu_features[GNLD_DPM_UCLK].enabled)
1534                 return smum_send_msg_to_smc_with_parameter(hwmgr,
1535                         PPSMC_MSG_SetUclkFastSwitch,
1536                         has_disp ? 1 : 0,
1537                         NULL);
1538
1539         return 0;
1540 }
1541
1542 static int vega12_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
1543                 struct pp_display_clock_request *clock_req)
1544 {
1545         int result = 0;
1546         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1547         enum amd_pp_clock_type clk_type = clock_req->clock_type;
1548         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
1549         PPCLK_e clk_select = 0;
1550         uint32_t clk_request = 0;
1551
1552         if (data->smu_features[GNLD_DPM_DCEFCLK].enabled) {
1553                 switch (clk_type) {
1554                 case amd_pp_dcef_clock:
1555                         clk_select = PPCLK_DCEFCLK;
1556                         break;
1557                 case amd_pp_disp_clock:
1558                         clk_select = PPCLK_DISPCLK;
1559                         break;
1560                 case amd_pp_pixel_clock:
1561                         clk_select = PPCLK_PIXCLK;
1562                         break;
1563                 case amd_pp_phy_clock:
1564                         clk_select = PPCLK_PHYCLK;
1565                         break;
1566                 default:
1567                         pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
1568                         result = -1;
1569                         break;
1570                 }
1571
1572                 if (!result) {
1573                         clk_request = (clk_select << 16) | clk_freq;
1574                         result = smum_send_msg_to_smc_with_parameter(hwmgr,
1575                                         PPSMC_MSG_SetHardMinByFreq,
1576                                         clk_request,
1577                                         NULL);
1578                 }
1579         }
1580
1581         return result;
1582 }
1583
1584 static int vega12_notify_smc_display_config_after_ps_adjustment(
1585                 struct pp_hwmgr *hwmgr)
1586 {
1587         struct vega12_hwmgr *data =
1588                         (struct vega12_hwmgr *)(hwmgr->backend);
1589         struct PP_Clocks min_clocks = {0};
1590         struct pp_display_clock_request clock_req;
1591
1592         if ((hwmgr->display_config->num_display > 1) &&
1593              !hwmgr->display_config->multi_monitor_in_sync &&
1594              !hwmgr->display_config->nb_pstate_switch_disable)
1595                 vega12_notify_smc_display_change(hwmgr, false);
1596         else
1597                 vega12_notify_smc_display_change(hwmgr, true);
1598
1599         min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
1600         min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk;
1601         min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock;
1602
1603         if (data->smu_features[GNLD_DPM_DCEFCLK].supported) {
1604                 clock_req.clock_type = amd_pp_dcef_clock;
1605                 clock_req.clock_freq_in_khz = min_clocks.dcefClock/10;
1606                 if (!vega12_display_clock_voltage_request(hwmgr, &clock_req)) {
1607                         if (data->smu_features[GNLD_DS_DCEFCLK].supported)
1608                                 PP_ASSERT_WITH_CODE(
1609                                         !smum_send_msg_to_smc_with_parameter(
1610                                         hwmgr, PPSMC_MSG_SetMinDeepSleepDcefclk,
1611                                         min_clocks.dcefClockInSR /100,
1612                                         NULL),
1613                                         "Attempt to set divider for DCEFCLK Failed!",
1614                                         return -1);
1615                 } else {
1616                         pr_info("Attempt to set Hard Min for DCEFCLK Failed!");
1617                 }
1618         }
1619
1620         return 0;
1621 }
1622
1623 static int vega12_force_dpm_highest(struct pp_hwmgr *hwmgr)
1624 {
1625         struct vega12_hwmgr *data =
1626                         (struct vega12_hwmgr *)(hwmgr->backend);
1627
1628         uint32_t soft_level;
1629
1630         soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.gfx_table));
1631
1632         data->dpm_table.gfx_table.dpm_state.soft_min_level =
1633                 data->dpm_table.gfx_table.dpm_state.soft_max_level =
1634                 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
1635
1636         soft_level = vega12_find_highest_dpm_level(&(data->dpm_table.mem_table));
1637
1638         data->dpm_table.mem_table.dpm_state.soft_min_level =
1639                 data->dpm_table.mem_table.dpm_state.soft_max_level =
1640                 data->dpm_table.mem_table.dpm_levels[soft_level].value;
1641
1642         PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
1643                         "Failed to upload boot level to highest!",
1644                         return -1);
1645
1646         PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
1647                         "Failed to upload dpm max level to highest!",
1648                         return -1);
1649
1650         return 0;
1651 }
1652
1653 static int vega12_force_dpm_lowest(struct pp_hwmgr *hwmgr)
1654 {
1655         struct vega12_hwmgr *data =
1656                         (struct vega12_hwmgr *)(hwmgr->backend);
1657         uint32_t soft_level;
1658
1659         soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.gfx_table));
1660
1661         data->dpm_table.gfx_table.dpm_state.soft_min_level =
1662                 data->dpm_table.gfx_table.dpm_state.soft_max_level =
1663                 data->dpm_table.gfx_table.dpm_levels[soft_level].value;
1664
1665         soft_level = vega12_find_lowest_dpm_level(&(data->dpm_table.mem_table));
1666
1667         data->dpm_table.mem_table.dpm_state.soft_min_level =
1668                 data->dpm_table.mem_table.dpm_state.soft_max_level =
1669                 data->dpm_table.mem_table.dpm_levels[soft_level].value;
1670
1671         PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
1672                         "Failed to upload boot level to highest!",
1673                         return -1);
1674
1675         PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
1676                         "Failed to upload dpm max level to highest!",
1677                         return -1);
1678
1679         return 0;
1680
1681 }
1682
1683 static int vega12_unforce_dpm_levels(struct pp_hwmgr *hwmgr)
1684 {
1685         PP_ASSERT_WITH_CODE(!vega12_upload_dpm_min_level(hwmgr),
1686                         "Failed to upload DPM Bootup Levels!",
1687                         return -1);
1688
1689         PP_ASSERT_WITH_CODE(!vega12_upload_dpm_max_level(hwmgr),
1690                         "Failed to upload DPM Max Levels!",
1691                         return -1);
1692
1693         return 0;
1694 }
1695
1696 static int vega12_get_profiling_clk_mask(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level,
1697                                 uint32_t *sclk_mask, uint32_t *mclk_mask, uint32_t *soc_mask)
1698 {
1699         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1700         struct vega12_single_dpm_table *gfx_dpm_table = &(data->dpm_table.gfx_table);
1701         struct vega12_single_dpm_table *mem_dpm_table = &(data->dpm_table.mem_table);
1702         struct vega12_single_dpm_table *soc_dpm_table = &(data->dpm_table.soc_table);
1703
1704         *sclk_mask = 0;
1705         *mclk_mask = 0;
1706         *soc_mask  = 0;
1707
1708         if (gfx_dpm_table->count > VEGA12_UMD_PSTATE_GFXCLK_LEVEL &&
1709             mem_dpm_table->count > VEGA12_UMD_PSTATE_MCLK_LEVEL &&
1710             soc_dpm_table->count > VEGA12_UMD_PSTATE_SOCCLK_LEVEL) {
1711                 *sclk_mask = VEGA12_UMD_PSTATE_GFXCLK_LEVEL;
1712                 *mclk_mask = VEGA12_UMD_PSTATE_MCLK_LEVEL;
1713                 *soc_mask  = VEGA12_UMD_PSTATE_SOCCLK_LEVEL;
1714         }
1715
1716         if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
1717                 *sclk_mask = 0;
1718         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
1719                 *mclk_mask = 0;
1720         } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
1721                 *sclk_mask = gfx_dpm_table->count - 1;
1722                 *mclk_mask = mem_dpm_table->count - 1;
1723                 *soc_mask  = soc_dpm_table->count - 1;
1724         }
1725
1726         return 0;
1727 }
1728
1729 static void vega12_set_fan_control_mode(struct pp_hwmgr *hwmgr, uint32_t mode)
1730 {
1731         switch (mode) {
1732         case AMD_FAN_CTRL_NONE:
1733                 break;
1734         case AMD_FAN_CTRL_MANUAL:
1735                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
1736                         vega12_fan_ctrl_stop_smc_fan_control(hwmgr);
1737                 break;
1738         case AMD_FAN_CTRL_AUTO:
1739                 if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl))
1740                         vega12_fan_ctrl_start_smc_fan_control(hwmgr);
1741                 break;
1742         default:
1743                 break;
1744         }
1745 }
1746
1747 static int vega12_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
1748                                 enum amd_dpm_forced_level level)
1749 {
1750         int ret = 0;
1751         uint32_t sclk_mask = 0;
1752         uint32_t mclk_mask = 0;
1753         uint32_t soc_mask = 0;
1754
1755         switch (level) {
1756         case AMD_DPM_FORCED_LEVEL_HIGH:
1757                 ret = vega12_force_dpm_highest(hwmgr);
1758                 break;
1759         case AMD_DPM_FORCED_LEVEL_LOW:
1760                 ret = vega12_force_dpm_lowest(hwmgr);
1761                 break;
1762         case AMD_DPM_FORCED_LEVEL_AUTO:
1763                 ret = vega12_unforce_dpm_levels(hwmgr);
1764                 break;
1765         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1766         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1767         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1768         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1769                 ret = vega12_get_profiling_clk_mask(hwmgr, level, &sclk_mask, &mclk_mask, &soc_mask);
1770                 if (ret)
1771                         return ret;
1772                 vega12_force_clock_level(hwmgr, PP_SCLK, 1 << sclk_mask);
1773                 vega12_force_clock_level(hwmgr, PP_MCLK, 1 << mclk_mask);
1774                 break;
1775         case AMD_DPM_FORCED_LEVEL_MANUAL:
1776         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1777         default:
1778                 break;
1779         }
1780
1781         return ret;
1782 }
1783
1784 static uint32_t vega12_get_fan_control_mode(struct pp_hwmgr *hwmgr)
1785 {
1786         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1787
1788         if (data->smu_features[GNLD_FAN_CONTROL].enabled == false)
1789                 return AMD_FAN_CTRL_MANUAL;
1790         else
1791                 return AMD_FAN_CTRL_AUTO;
1792 }
1793
1794 static int vega12_get_dal_power_level(struct pp_hwmgr *hwmgr,
1795                 struct amd_pp_simple_clock_info *info)
1796 {
1797 #if 0
1798         struct phm_ppt_v2_information *table_info =
1799                         (struct phm_ppt_v2_information *)hwmgr->pptable;
1800         struct phm_clock_and_voltage_limits *max_limits =
1801                         &table_info->max_clock_voltage_on_ac;
1802
1803         info->engine_max_clock = max_limits->sclk;
1804         info->memory_max_clock = max_limits->mclk;
1805 #endif
1806         return 0;
1807 }
1808
1809 static int vega12_get_clock_ranges(struct pp_hwmgr *hwmgr,
1810                 uint32_t *clock,
1811                 PPCLK_e clock_select,
1812                 bool max)
1813 {
1814         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1815
1816         if (max)
1817                 *clock = data->clk_range[clock_select].ACMax;
1818         else
1819                 *clock = data->clk_range[clock_select].ACMin;
1820
1821         return 0;
1822 }
1823
1824 static int vega12_get_sclks(struct pp_hwmgr *hwmgr,
1825                 struct pp_clock_levels_with_latency *clocks)
1826 {
1827         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1828         uint32_t ucount;
1829         int i;
1830         struct vega12_single_dpm_table *dpm_table;
1831
1832         if (!data->smu_features[GNLD_DPM_GFXCLK].enabled)
1833                 return -1;
1834
1835         dpm_table = &(data->dpm_table.gfx_table);
1836         ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1837                 MAX_NUM_CLOCKS : dpm_table->count;
1838
1839         for (i = 0; i < ucount; i++) {
1840                 clocks->data[i].clocks_in_khz =
1841                         dpm_table->dpm_levels[i].value * 1000;
1842
1843                 clocks->data[i].latency_in_us = 0;
1844         }
1845
1846         clocks->num_levels = ucount;
1847
1848         return 0;
1849 }
1850
1851 static uint32_t vega12_get_mem_latency(struct pp_hwmgr *hwmgr,
1852                 uint32_t clock)
1853 {
1854         return 25;
1855 }
1856
1857 static int vega12_get_memclocks(struct pp_hwmgr *hwmgr,
1858                 struct pp_clock_levels_with_latency *clocks)
1859 {
1860         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1861         uint32_t ucount;
1862         int i;
1863         struct vega12_single_dpm_table *dpm_table;
1864         if (!data->smu_features[GNLD_DPM_UCLK].enabled)
1865                 return -1;
1866
1867         dpm_table = &(data->dpm_table.mem_table);
1868         ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1869                 MAX_NUM_CLOCKS : dpm_table->count;
1870
1871         for (i = 0; i < ucount; i++) {
1872                 clocks->data[i].clocks_in_khz = dpm_table->dpm_levels[i].value * 1000;
1873                 data->mclk_latency_table.entries[i].frequency = dpm_table->dpm_levels[i].value * 100;
1874                 clocks->data[i].latency_in_us =
1875                         data->mclk_latency_table.entries[i].latency =
1876                         vega12_get_mem_latency(hwmgr, dpm_table->dpm_levels[i].value);
1877         }
1878
1879         clocks->num_levels = data->mclk_latency_table.count = ucount;
1880
1881         return 0;
1882 }
1883
1884 static int vega12_get_dcefclocks(struct pp_hwmgr *hwmgr,
1885                 struct pp_clock_levels_with_latency *clocks)
1886 {
1887         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1888         uint32_t ucount;
1889         int i;
1890         struct vega12_single_dpm_table *dpm_table;
1891
1892         if (!data->smu_features[GNLD_DPM_DCEFCLK].enabled)
1893                 return -1;
1894
1895
1896         dpm_table = &(data->dpm_table.dcef_table);
1897         ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1898                 MAX_NUM_CLOCKS : dpm_table->count;
1899
1900         for (i = 0; i < ucount; i++) {
1901                 clocks->data[i].clocks_in_khz =
1902                         dpm_table->dpm_levels[i].value * 1000;
1903
1904                 clocks->data[i].latency_in_us = 0;
1905         }
1906
1907         clocks->num_levels = ucount;
1908
1909         return 0;
1910 }
1911
1912 static int vega12_get_socclocks(struct pp_hwmgr *hwmgr,
1913                 struct pp_clock_levels_with_latency *clocks)
1914 {
1915         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1916         uint32_t ucount;
1917         int i;
1918         struct vega12_single_dpm_table *dpm_table;
1919
1920         if (!data->smu_features[GNLD_DPM_SOCCLK].enabled)
1921                 return -1;
1922
1923
1924         dpm_table = &(data->dpm_table.soc_table);
1925         ucount = (dpm_table->count > MAX_NUM_CLOCKS) ?
1926                 MAX_NUM_CLOCKS : dpm_table->count;
1927
1928         for (i = 0; i < ucount; i++) {
1929                 clocks->data[i].clocks_in_khz =
1930                         dpm_table->dpm_levels[i].value * 1000;
1931
1932                 clocks->data[i].latency_in_us = 0;
1933         }
1934
1935         clocks->num_levels = ucount;
1936
1937         return 0;
1938
1939 }
1940
1941 static int vega12_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
1942                 enum amd_pp_clock_type type,
1943                 struct pp_clock_levels_with_latency *clocks)
1944 {
1945         int ret;
1946
1947         switch (type) {
1948         case amd_pp_sys_clock:
1949                 ret = vega12_get_sclks(hwmgr, clocks);
1950                 break;
1951         case amd_pp_mem_clock:
1952                 ret = vega12_get_memclocks(hwmgr, clocks);
1953                 break;
1954         case amd_pp_dcef_clock:
1955                 ret = vega12_get_dcefclocks(hwmgr, clocks);
1956                 break;
1957         case amd_pp_soc_clock:
1958                 ret = vega12_get_socclocks(hwmgr, clocks);
1959                 break;
1960         default:
1961                 return -EINVAL;
1962         }
1963
1964         return ret;
1965 }
1966
1967 static int vega12_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
1968                 enum amd_pp_clock_type type,
1969                 struct pp_clock_levels_with_voltage *clocks)
1970 {
1971         clocks->num_levels = 0;
1972
1973         return 0;
1974 }
1975
1976 static int vega12_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
1977                                                         void *clock_ranges)
1978 {
1979         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1980         Watermarks_t *table = &(data->smc_state_table.water_marks_table);
1981         struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
1982
1983         if (!data->registry_data.disable_water_mark &&
1984                         data->smu_features[GNLD_DPM_DCEFCLK].supported &&
1985                         data->smu_features[GNLD_DPM_SOCCLK].supported) {
1986                 smu_set_watermarks_for_clocks_ranges(table, wm_with_clock_ranges);
1987                 data->water_marks_bitmap |= WaterMarksExist;
1988                 data->water_marks_bitmap &= ~WaterMarksLoaded;
1989         }
1990
1991         return 0;
1992 }
1993
1994 static int vega12_force_clock_level(struct pp_hwmgr *hwmgr,
1995                 enum pp_clock_type type, uint32_t mask)
1996 {
1997         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
1998         uint32_t soft_min_level, soft_max_level, hard_min_level;
1999         int ret = 0;
2000
2001         switch (type) {
2002         case PP_SCLK:
2003                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2004                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2005
2006                 data->dpm_table.gfx_table.dpm_state.soft_min_level =
2007                         data->dpm_table.gfx_table.dpm_levels[soft_min_level].value;
2008                 data->dpm_table.gfx_table.dpm_state.soft_max_level =
2009                         data->dpm_table.gfx_table.dpm_levels[soft_max_level].value;
2010
2011                 ret = vega12_upload_dpm_min_level(hwmgr);
2012                 PP_ASSERT_WITH_CODE(!ret,
2013                         "Failed to upload boot level to lowest!",
2014                         return ret);
2015
2016                 ret = vega12_upload_dpm_max_level(hwmgr);
2017                 PP_ASSERT_WITH_CODE(!ret,
2018                         "Failed to upload dpm max level to highest!",
2019                         return ret);
2020                 break;
2021
2022         case PP_MCLK:
2023                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2024                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2025
2026                 data->dpm_table.mem_table.dpm_state.soft_min_level =
2027                         data->dpm_table.mem_table.dpm_levels[soft_min_level].value;
2028                 data->dpm_table.mem_table.dpm_state.soft_max_level =
2029                         data->dpm_table.mem_table.dpm_levels[soft_max_level].value;
2030
2031                 ret = vega12_upload_dpm_min_level(hwmgr);
2032                 PP_ASSERT_WITH_CODE(!ret,
2033                         "Failed to upload boot level to lowest!",
2034                         return ret);
2035
2036                 ret = vega12_upload_dpm_max_level(hwmgr);
2037                 PP_ASSERT_WITH_CODE(!ret,
2038                         "Failed to upload dpm max level to highest!",
2039                         return ret);
2040
2041                 break;
2042
2043         case PP_SOCCLK:
2044                 soft_min_level = mask ? (ffs(mask) - 1) : 0;
2045                 soft_max_level = mask ? (fls(mask) - 1) : 0;
2046
2047                 if (soft_max_level >= data->dpm_table.soc_table.count) {
2048                         pr_err("Clock level specified %d is over max allowed %d\n",
2049                                         soft_max_level,
2050                                         data->dpm_table.soc_table.count - 1);
2051                         return -EINVAL;
2052                 }
2053
2054                 data->dpm_table.soc_table.dpm_state.soft_min_level =
2055                         data->dpm_table.soc_table.dpm_levels[soft_min_level].value;
2056                 data->dpm_table.soc_table.dpm_state.soft_max_level =
2057                         data->dpm_table.soc_table.dpm_levels[soft_max_level].value;
2058
2059                 ret = vega12_upload_dpm_min_level(hwmgr);
2060                 PP_ASSERT_WITH_CODE(!ret,
2061                         "Failed to upload boot level to lowest!",
2062                         return ret);
2063
2064                 ret = vega12_upload_dpm_max_level(hwmgr);
2065                 PP_ASSERT_WITH_CODE(!ret,
2066                         "Failed to upload dpm max level to highest!",
2067                         return ret);
2068
2069                 break;
2070
2071         case PP_DCEFCLK:
2072                 hard_min_level = mask ? (ffs(mask) - 1) : 0;
2073
2074                 if (hard_min_level >= data->dpm_table.dcef_table.count) {
2075                         pr_err("Clock level specified %d is over max allowed %d\n",
2076                                         hard_min_level,
2077                                         data->dpm_table.dcef_table.count - 1);
2078                         return -EINVAL;
2079                 }
2080
2081                 data->dpm_table.dcef_table.dpm_state.hard_min_level =
2082                         data->dpm_table.dcef_table.dpm_levels[hard_min_level].value;
2083
2084                 ret = vega12_upload_dpm_min_level(hwmgr);
2085                 PP_ASSERT_WITH_CODE(!ret,
2086                         "Failed to upload boot level to lowest!",
2087                         return ret);
2088
2089                 //TODO: Setting DCEFCLK max dpm level is not supported
2090
2091                 break;
2092
2093         case PP_PCIE:
2094                 break;
2095
2096         default:
2097                 break;
2098         }
2099
2100         return 0;
2101 }
2102
2103 static int vega12_get_ppfeature_status(struct pp_hwmgr *hwmgr, char *buf)
2104 {
2105         static const char *ppfeature_name[] = {
2106                         "DPM_PREFETCHER",
2107                         "GFXCLK_DPM",
2108                         "UCLK_DPM",
2109                         "SOCCLK_DPM",
2110                         "UVD_DPM",
2111                         "VCE_DPM",
2112                         "ULV",
2113                         "MP0CLK_DPM",
2114                         "LINK_DPM",
2115                         "DCEFCLK_DPM",
2116                         "GFXCLK_DS",
2117                         "SOCCLK_DS",
2118                         "LCLK_DS",
2119                         "PPT",
2120                         "TDC",
2121                         "THERMAL",
2122                         "GFX_PER_CU_CG",
2123                         "RM",
2124                         "DCEFCLK_DS",
2125                         "ACDC",
2126                         "VR0HOT",
2127                         "VR1HOT",
2128                         "FW_CTF",
2129                         "LED_DISPLAY",
2130                         "FAN_CONTROL",
2131                         "DIDT",
2132                         "GFXOFF",
2133                         "CG",
2134                         "ACG"};
2135         static const char *output_title[] = {
2136                         "FEATURES",
2137                         "BITMASK",
2138                         "ENABLEMENT"};
2139         uint64_t features_enabled;
2140         int i;
2141         int ret = 0;
2142         int size = 0;
2143
2144         ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled);
2145         PP_ASSERT_WITH_CODE(!ret,
2146                 "[EnableAllSmuFeatures] Failed to get enabled smc features!",
2147                 return ret);
2148
2149         size += sysfs_emit_at(buf, size, "Current ppfeatures: 0x%016llx\n", features_enabled);
2150         size += sysfs_emit_at(buf, size, "%-19s %-22s %s\n",
2151                                 output_title[0],
2152                                 output_title[1],
2153                                 output_title[2]);
2154         for (i = 0; i < GNLD_FEATURES_MAX; i++) {
2155                 size += sysfs_emit_at(buf, size, "%-19s 0x%016llx %6s\n",
2156                                 ppfeature_name[i],
2157                                 1ULL << i,
2158                                 (features_enabled & (1ULL << i)) ? "Y" : "N");
2159         }
2160
2161         return size;
2162 }
2163
2164 static int vega12_set_ppfeature_status(struct pp_hwmgr *hwmgr, uint64_t new_ppfeature_masks)
2165 {
2166         uint64_t features_enabled;
2167         uint64_t features_to_enable;
2168         uint64_t features_to_disable;
2169         int ret = 0;
2170
2171         if (new_ppfeature_masks >= (1ULL << GNLD_FEATURES_MAX))
2172                 return -EINVAL;
2173
2174         ret = vega12_get_enabled_smc_features(hwmgr, &features_enabled);
2175         if (ret)
2176                 return ret;
2177
2178         features_to_disable =
2179                 features_enabled & ~new_ppfeature_masks;
2180         features_to_enable =
2181                 ~features_enabled & new_ppfeature_masks;
2182
2183         pr_debug("features_to_disable 0x%llx\n", features_to_disable);
2184         pr_debug("features_to_enable 0x%llx\n", features_to_enable);
2185
2186         if (features_to_disable) {
2187                 ret = vega12_enable_smc_features(hwmgr, false, features_to_disable);
2188                 if (ret)
2189                         return ret;
2190         }
2191
2192         if (features_to_enable) {
2193                 ret = vega12_enable_smc_features(hwmgr, true, features_to_enable);
2194                 if (ret)
2195                         return ret;
2196         }
2197
2198         return 0;
2199 }
2200
2201 static int vega12_get_current_pcie_link_width_level(struct pp_hwmgr *hwmgr)
2202 {
2203         struct amdgpu_device *adev = hwmgr->adev;
2204
2205         return (RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL) &
2206                 PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
2207                 >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
2208 }
2209
2210 static int vega12_get_current_pcie_link_width(struct pp_hwmgr *hwmgr)
2211 {
2212         uint32_t width_level;
2213
2214         width_level = vega12_get_current_pcie_link_width_level(hwmgr);
2215         if (width_level > LINK_WIDTH_MAX)
2216                 width_level = 0;
2217
2218         return link_width[width_level];
2219 }
2220
2221 static int vega12_get_current_pcie_link_speed_level(struct pp_hwmgr *hwmgr)
2222 {
2223         struct amdgpu_device *adev = hwmgr->adev;
2224
2225         return (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2226                 PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2227                 >> PSWUSP0_PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2228 }
2229
2230 static int vega12_get_current_pcie_link_speed(struct pp_hwmgr *hwmgr)
2231 {
2232         uint32_t speed_level;
2233
2234         speed_level = vega12_get_current_pcie_link_speed_level(hwmgr);
2235         if (speed_level > LINK_SPEED_MAX)
2236                 speed_level = 0;
2237
2238         return link_speed[speed_level];
2239 }
2240
2241 static int vega12_print_clock_levels(struct pp_hwmgr *hwmgr,
2242                 enum pp_clock_type type, char *buf)
2243 {
2244         int i, now, size = 0;
2245         struct pp_clock_levels_with_latency clocks;
2246
2247         switch (type) {
2248         case PP_SCLK:
2249                 PP_ASSERT_WITH_CODE(
2250                                 vega12_get_current_gfx_clk_freq(hwmgr, &now) == 0,
2251                                 "Attempt to get current gfx clk Failed!",
2252                                 return -1);
2253
2254                 PP_ASSERT_WITH_CODE(
2255                                 vega12_get_sclks(hwmgr, &clocks) == 0,
2256                                 "Attempt to get gfx clk levels Failed!",
2257                                 return -1);
2258                 for (i = 0; i < clocks.num_levels; i++)
2259                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
2260                                 i, clocks.data[i].clocks_in_khz / 1000,
2261                                 (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");
2262                 break;
2263
2264         case PP_MCLK:
2265                 PP_ASSERT_WITH_CODE(
2266                                 vega12_get_current_mclk_freq(hwmgr, &now) == 0,
2267                                 "Attempt to get current mclk freq Failed!",
2268                                 return -1);
2269
2270                 PP_ASSERT_WITH_CODE(
2271                                 vega12_get_memclocks(hwmgr, &clocks) == 0,
2272                                 "Attempt to get memory clk levels Failed!",
2273                                 return -1);
2274                 for (i = 0; i < clocks.num_levels; i++)
2275                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
2276                                 i, clocks.data[i].clocks_in_khz / 1000,
2277                                 (clocks.data[i].clocks_in_khz / 1000 == now / 100) ? "*" : "");
2278                 break;
2279
2280         case PP_SOCCLK:
2281                 PP_ASSERT_WITH_CODE(
2282                                 smum_send_msg_to_smc_with_parameter(hwmgr,
2283                                         PPSMC_MSG_GetDpmClockFreq, (PPCLK_SOCCLK << 16),
2284                                         &now) == 0,
2285                                 "Attempt to get Current SOCCLK Frequency Failed!",
2286                                 return -EINVAL);
2287
2288                 PP_ASSERT_WITH_CODE(
2289                                 vega12_get_socclocks(hwmgr, &clocks) == 0,
2290                                 "Attempt to get soc clk levels Failed!",
2291                                 return -1);
2292                 for (i = 0; i < clocks.num_levels; i++)
2293                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
2294                                 i, clocks.data[i].clocks_in_khz / 1000,
2295                                 (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");
2296                 break;
2297
2298         case PP_DCEFCLK:
2299                 PP_ASSERT_WITH_CODE(
2300                                 smum_send_msg_to_smc_with_parameter(hwmgr,
2301                                         PPSMC_MSG_GetDpmClockFreq, (PPCLK_DCEFCLK << 16),
2302                                         &now) == 0,
2303                                 "Attempt to get Current DCEFCLK Frequency Failed!",
2304                                 return -EINVAL);
2305
2306                 PP_ASSERT_WITH_CODE(
2307                                 vega12_get_dcefclocks(hwmgr, &clocks) == 0,
2308                                 "Attempt to get dcef clk levels Failed!",
2309                                 return -1);
2310                 for (i = 0; i < clocks.num_levels; i++)
2311                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
2312                                 i, clocks.data[i].clocks_in_khz / 1000,
2313                                 (clocks.data[i].clocks_in_khz / 1000 == now) ? "*" : "");
2314                 break;
2315
2316         case PP_PCIE:
2317                 break;
2318
2319         default:
2320                 break;
2321         }
2322         return size;
2323 }
2324
2325 static int vega12_apply_clocks_adjust_rules(struct pp_hwmgr *hwmgr)
2326 {
2327         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2328         struct vega12_single_dpm_table *dpm_table;
2329         bool vblank_too_short = false;
2330         bool disable_mclk_switching;
2331         uint32_t i, latency;
2332
2333         disable_mclk_switching = ((1 < hwmgr->display_config->num_display) &&
2334                                   !hwmgr->display_config->multi_monitor_in_sync) ||
2335                                   vblank_too_short;
2336         latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency;
2337
2338         /* gfxclk */
2339         dpm_table = &(data->dpm_table.gfx_table);
2340         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2341         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2342         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2343         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2344
2345         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2346                 if (VEGA12_UMD_PSTATE_GFXCLK_LEVEL < dpm_table->count) {
2347                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
2348                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_GFXCLK_LEVEL].value;
2349                 }
2350
2351                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
2352                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2353                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2354                 }
2355
2356                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2357                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2358                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2359                 }
2360         }
2361
2362         /* memclk */
2363         dpm_table = &(data->dpm_table.mem_table);
2364         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2365         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2366         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2367         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2368
2369         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2370                 if (VEGA12_UMD_PSTATE_MCLK_LEVEL < dpm_table->count) {
2371                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
2372                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_MCLK_LEVEL].value;
2373                 }
2374
2375                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
2376                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2377                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[0].value;
2378                 }
2379
2380                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2381                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2382                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2383                 }
2384         }
2385
2386         /* honour DAL's UCLK Hardmin */
2387         if (dpm_table->dpm_state.hard_min_level < (hwmgr->display_config->min_mem_set_clock / 100))
2388                 dpm_table->dpm_state.hard_min_level = hwmgr->display_config->min_mem_set_clock / 100;
2389
2390         /* Hardmin is dependent on displayconfig */
2391         if (disable_mclk_switching) {
2392                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2393                 for (i = 0; i < data->mclk_latency_table.count - 1; i++) {
2394                         if (data->mclk_latency_table.entries[i].latency <= latency) {
2395                                 if (dpm_table->dpm_levels[i].value >= (hwmgr->display_config->min_mem_set_clock / 100)) {
2396                                         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[i].value;
2397                                         break;
2398                                 }
2399                         }
2400                 }
2401         }
2402
2403         if (hwmgr->display_config->nb_pstate_switch_disable)
2404                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2405
2406         /* vclk */
2407         dpm_table = &(data->dpm_table.vclk_table);
2408         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2409         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2410         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2411         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2412
2413         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2414                 if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2415                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2416                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2417                 }
2418
2419                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2420                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2421                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2422                 }
2423         }
2424
2425         /* dclk */
2426         dpm_table = &(data->dpm_table.dclk_table);
2427         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2428         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2429         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2430         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2431
2432         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2433                 if (VEGA12_UMD_PSTATE_UVDCLK_LEVEL < dpm_table->count) {
2434                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2435                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_UVDCLK_LEVEL].value;
2436                 }
2437
2438                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2439                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2440                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2441                 }
2442         }
2443
2444         /* socclk */
2445         dpm_table = &(data->dpm_table.soc_table);
2446         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2447         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2448         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2449         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2450
2451         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2452                 if (VEGA12_UMD_PSTATE_SOCCLK_LEVEL < dpm_table->count) {
2453                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value;
2454                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_SOCCLK_LEVEL].value;
2455                 }
2456
2457                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2458                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2459                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2460                 }
2461         }
2462
2463         /* eclk */
2464         dpm_table = &(data->dpm_table.eclk_table);
2465         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[0].value;
2466         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2467         dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[0].value;
2468         dpm_table->dpm_state.hard_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2469
2470         if (PP_CAP(PHM_PlatformCaps_UMDPState)) {
2471                 if (VEGA12_UMD_PSTATE_VCEMCLK_LEVEL < dpm_table->count) {
2472                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value;
2473                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[VEGA12_UMD_PSTATE_VCEMCLK_LEVEL].value;
2474                 }
2475
2476                 if (hwmgr->dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
2477                         dpm_table->dpm_state.soft_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2478                         dpm_table->dpm_state.soft_max_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2479                 }
2480         }
2481
2482         return 0;
2483 }
2484
2485 static int vega12_set_uclk_to_highest_dpm_level(struct pp_hwmgr *hwmgr,
2486                 struct vega12_single_dpm_table *dpm_table)
2487 {
2488         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2489         int ret = 0;
2490
2491         if (data->smu_features[GNLD_DPM_UCLK].enabled) {
2492                 PP_ASSERT_WITH_CODE(dpm_table->count > 0,
2493                                 "[SetUclkToHightestDpmLevel] Dpm table has no entry!",
2494                                 return -EINVAL);
2495                 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS,
2496                                 "[SetUclkToHightestDpmLevel] Dpm table has too many entries!",
2497                                 return -EINVAL);
2498
2499                 dpm_table->dpm_state.hard_min_level = dpm_table->dpm_levels[dpm_table->count - 1].value;
2500                 PP_ASSERT_WITH_CODE(!(ret = smum_send_msg_to_smc_with_parameter(hwmgr,
2501                                 PPSMC_MSG_SetHardMinByFreq,
2502                                 (PPCLK_UCLK << 16 ) | dpm_table->dpm_state.hard_min_level,
2503                                 NULL)),
2504                                 "[SetUclkToHightestDpmLevel] Set hard min uclk failed!",
2505                                 return ret);
2506         }
2507
2508         return ret;
2509 }
2510
2511 static int vega12_pre_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2512 {
2513         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2514         int ret = 0;
2515
2516         smum_send_msg_to_smc_with_parameter(hwmgr,
2517                         PPSMC_MSG_NumOfDisplays, 0,
2518                         NULL);
2519
2520         ret = vega12_set_uclk_to_highest_dpm_level(hwmgr,
2521                         &data->dpm_table.mem_table);
2522
2523         return ret;
2524 }
2525
2526 static int vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
2527 {
2528         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2529         int result = 0;
2530         Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table);
2531
2532         if ((data->water_marks_bitmap & WaterMarksExist) &&
2533                         !(data->water_marks_bitmap & WaterMarksLoaded)) {
2534                 result = smum_smc_table_manager(hwmgr,
2535                                                 (uint8_t *)wm_table, TABLE_WATERMARKS, false);
2536                 PP_ASSERT_WITH_CODE(result, "Failed to update WMTABLE!", return -EINVAL);
2537                 data->water_marks_bitmap |= WaterMarksLoaded;
2538         }
2539
2540         if ((data->water_marks_bitmap & WaterMarksExist) &&
2541                 data->smu_features[GNLD_DPM_DCEFCLK].supported &&
2542                 data->smu_features[GNLD_DPM_SOCCLK].supported)
2543                 smum_send_msg_to_smc_with_parameter(hwmgr,
2544                         PPSMC_MSG_NumOfDisplays, hwmgr->display_config->num_display,
2545                         NULL);
2546
2547         return result;
2548 }
2549
2550 static int vega12_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
2551 {
2552         struct vega12_hwmgr *data =
2553                         (struct vega12_hwmgr *)(hwmgr->backend);
2554
2555         if (data->smu_features[GNLD_DPM_UVD].supported) {
2556                 PP_ASSERT_WITH_CODE(!vega12_enable_smc_features(hwmgr,
2557                                 enable,
2558                                 data->smu_features[GNLD_DPM_UVD].smu_feature_bitmap),
2559                                 "Attempt to Enable/Disable DPM UVD Failed!",
2560                                 return -1);
2561                 data->smu_features[GNLD_DPM_UVD].enabled = enable;
2562         }
2563
2564         return 0;
2565 }
2566
2567 static void vega12_power_gate_vce(struct pp_hwmgr *hwmgr, bool bgate)
2568 {
2569         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2570
2571         if (data->vce_power_gated == bgate)
2572                 return;
2573
2574         data->vce_power_gated = bgate;
2575         vega12_enable_disable_vce_dpm(hwmgr, !bgate);
2576 }
2577
2578 static void vega12_power_gate_uvd(struct pp_hwmgr *hwmgr, bool bgate)
2579 {
2580         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2581
2582         if (data->uvd_power_gated == bgate)
2583                 return;
2584
2585         data->uvd_power_gated = bgate;
2586         vega12_enable_disable_uvd_dpm(hwmgr, !bgate);
2587 }
2588
2589 static bool
2590 vega12_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
2591 {
2592         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2593         bool is_update_required = false;
2594
2595         if (data->display_timing.num_existing_displays != hwmgr->display_config->num_display)
2596                 is_update_required = true;
2597
2598         if (data->registry_data.gfx_clk_deep_sleep_support) {
2599                 if (data->display_timing.min_clock_in_sr != hwmgr->display_config->min_core_set_clock_in_sr)
2600                         is_update_required = true;
2601         }
2602
2603         return is_update_required;
2604 }
2605
2606 static int vega12_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
2607 {
2608         int tmp_result, result = 0;
2609
2610         tmp_result = vega12_disable_all_smu_features(hwmgr);
2611         PP_ASSERT_WITH_CODE((tmp_result == 0),
2612                         "Failed to disable all smu features!", result = tmp_result);
2613
2614         return result;
2615 }
2616
2617 static int vega12_power_off_asic(struct pp_hwmgr *hwmgr)
2618 {
2619         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2620         int result;
2621
2622         result = vega12_disable_dpm_tasks(hwmgr);
2623         PP_ASSERT_WITH_CODE((0 == result),
2624                         "[disable_dpm_tasks] Failed to disable DPM!",
2625                         );
2626         data->water_marks_bitmap &= ~(WaterMarksLoaded);
2627
2628         return result;
2629 }
2630
2631 #if 0
2632 static void vega12_find_min_clock_index(struct pp_hwmgr *hwmgr,
2633                 uint32_t *sclk_idx, uint32_t *mclk_idx,
2634                 uint32_t min_sclk, uint32_t min_mclk)
2635 {
2636         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2637         struct vega12_dpm_table *dpm_table = &(data->dpm_table);
2638         uint32_t i;
2639
2640         for (i = 0; i < dpm_table->gfx_table.count; i++) {
2641                 if (dpm_table->gfx_table.dpm_levels[i].enabled &&
2642                         dpm_table->gfx_table.dpm_levels[i].value >= min_sclk) {
2643                         *sclk_idx = i;
2644                         break;
2645                 }
2646         }
2647
2648         for (i = 0; i < dpm_table->mem_table.count; i++) {
2649                 if (dpm_table->mem_table.dpm_levels[i].enabled &&
2650                         dpm_table->mem_table.dpm_levels[i].value >= min_mclk) {
2651                         *mclk_idx = i;
2652                         break;
2653                 }
2654         }
2655 }
2656 #endif
2657
2658 #if 0
2659 static int vega12_set_power_profile_state(struct pp_hwmgr *hwmgr,
2660                 struct amd_pp_profile *request)
2661 {
2662         return 0;
2663 }
2664
2665 static int vega12_get_sclk_od(struct pp_hwmgr *hwmgr)
2666 {
2667         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2668         struct vega12_single_dpm_table *sclk_table = &(data->dpm_table.gfx_table);
2669         struct vega12_single_dpm_table *golden_sclk_table =
2670                         &(data->golden_dpm_table.gfx_table);
2671         int value = sclk_table->dpm_levels[sclk_table->count - 1].value;
2672         int golden_value = golden_sclk_table->dpm_levels
2673                         [golden_sclk_table->count - 1].value;
2674
2675         value -= golden_value;
2676         value = DIV_ROUND_UP(value * 100, golden_value);
2677
2678         return value;
2679 }
2680
2681 static int vega12_set_sclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
2682 {
2683         return 0;
2684 }
2685
2686 static int vega12_get_mclk_od(struct pp_hwmgr *hwmgr)
2687 {
2688         struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
2689         struct vega12_single_dpm_table *mclk_table = &(data->dpm_table.mem_table);
2690         struct vega12_single_dpm_table *golden_mclk_table =
2691                         &(data->golden_dpm_table.mem_table);
2692         int value = mclk_table->dpm_levels[mclk_table->count - 1].value;
2693         int golden_value = golden_mclk_table->dpm_levels
2694                         [golden_mclk_table->count - 1].value;
2695
2696         value -= golden_value;
2697         value = DIV_ROUND_UP(value * 100, golden_value);
2698
2699         return value;
2700 }
2701
2702 static int vega12_set_mclk_od(struct pp_hwmgr *hwmgr, uint32_t value)
2703 {
2704         return 0;
2705 }
2706 #endif
2707
2708 static int vega12_notify_cac_buffer_info(struct pp_hwmgr *hwmgr,
2709                                         uint32_t virtual_addr_low,
2710                                         uint32_t virtual_addr_hi,
2711                                         uint32_t mc_addr_low,
2712                                         uint32_t mc_addr_hi,
2713                                         uint32_t size)
2714 {
2715         smum_send_msg_to_smc_with_parameter(hwmgr,
2716                                         PPSMC_MSG_SetSystemVirtualDramAddrHigh,
2717                                         virtual_addr_hi,
2718                                         NULL);
2719         smum_send_msg_to_smc_with_parameter(hwmgr,
2720                                         PPSMC_MSG_SetSystemVirtualDramAddrLow,
2721                                         virtual_addr_low,
2722                                         NULL);
2723         smum_send_msg_to_smc_with_parameter(hwmgr,
2724                                         PPSMC_MSG_DramLogSetDramAddrHigh,
2725                                         mc_addr_hi,
2726                                         NULL);
2727
2728         smum_send_msg_to_smc_with_parameter(hwmgr,
2729                                         PPSMC_MSG_DramLogSetDramAddrLow,
2730                                         mc_addr_low,
2731                                         NULL);
2732
2733         smum_send_msg_to_smc_with_parameter(hwmgr,
2734                                         PPSMC_MSG_DramLogSetDramSize,
2735                                         size,
2736                                         NULL);
2737         return 0;
2738 }
2739
2740 static int vega12_get_thermal_temperature_range(struct pp_hwmgr *hwmgr,
2741                 struct PP_TemperatureRange *thermal_data)
2742 {
2743         struct vega12_hwmgr *data =
2744                         (struct vega12_hwmgr *)(hwmgr->backend);
2745         PPTable_t *pp_table = &(data->smc_state_table.pp_table);
2746
2747         memcpy(thermal_data, &SMU7ThermalWithDelayPolicy[0], sizeof(struct PP_TemperatureRange));
2748
2749         thermal_data->max = pp_table->TedgeLimit *
2750                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2751         thermal_data->edge_emergency_max = (pp_table->TedgeLimit + CTF_OFFSET_EDGE) *
2752                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2753         thermal_data->hotspot_crit_max = pp_table->ThotspotLimit *
2754                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2755         thermal_data->hotspot_emergency_max = (pp_table->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
2756                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2757         thermal_data->mem_crit_max = pp_table->ThbmLimit *
2758                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2759         thermal_data->mem_emergency_max = (pp_table->ThbmLimit + CTF_OFFSET_HBM)*
2760                 PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
2761
2762         return 0;
2763 }
2764
2765 static int vega12_enable_gfx_off(struct pp_hwmgr *hwmgr)
2766 {
2767         struct vega12_hwmgr *data =
2768                         (struct vega12_hwmgr *)(hwmgr->backend);
2769         int ret = 0;
2770
2771         if (data->gfxoff_controlled_by_driver)
2772                 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_AllowGfxOff, NULL);
2773
2774         return ret;
2775 }
2776
2777 static int vega12_disable_gfx_off(struct pp_hwmgr *hwmgr)
2778 {
2779         struct vega12_hwmgr *data =
2780                         (struct vega12_hwmgr *)(hwmgr->backend);
2781         int ret = 0;
2782
2783         if (data->gfxoff_controlled_by_driver)
2784                 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisallowGfxOff, NULL);
2785
2786         return ret;
2787 }
2788
2789 static int vega12_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
2790 {
2791         if (enable)
2792                 return vega12_enable_gfx_off(hwmgr);
2793         else
2794                 return vega12_disable_gfx_off(hwmgr);
2795 }
2796
2797 static int vega12_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
2798                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
2799                                 PHM_PerformanceLevel *level)
2800 {
2801         return 0;
2802 }
2803
2804 static int vega12_set_mp1_state(struct pp_hwmgr *hwmgr,
2805                                 enum pp_mp1_state mp1_state)
2806 {
2807         uint16_t msg;
2808         int ret;
2809
2810         switch (mp1_state) {
2811         case PP_MP1_STATE_UNLOAD:
2812                 msg = PPSMC_MSG_PrepareMp1ForUnload;
2813                 break;
2814         case PP_MP1_STATE_SHUTDOWN:
2815         case PP_MP1_STATE_RESET:
2816         case PP_MP1_STATE_NONE:
2817         default:
2818                 return 0;
2819         }
2820
2821         PP_ASSERT_WITH_CODE((ret = smum_send_msg_to_smc(hwmgr, msg, NULL)) == 0,
2822                             "[PrepareMp1] Failed!",
2823                             return ret);
2824
2825         return 0;
2826 }
2827
2828 static void vega12_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics)
2829 {
2830         memset(gpu_metrics, 0xFF, sizeof(struct gpu_metrics_v1_0));
2831
2832         gpu_metrics->common_header.structure_size =
2833                                 sizeof(struct gpu_metrics_v1_0);
2834         gpu_metrics->common_header.format_revision = 1;
2835         gpu_metrics->common_header.content_revision = 0;
2836
2837         gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2838 }
2839
2840 static ssize_t vega12_get_gpu_metrics(struct pp_hwmgr *hwmgr,
2841                                       void **table)
2842 {
2843         struct vega12_hwmgr *data =
2844                         (struct vega12_hwmgr *)(hwmgr->backend);
2845         struct gpu_metrics_v1_0 *gpu_metrics =
2846                         &data->gpu_metrics_table;
2847         SmuMetrics_t metrics;
2848         uint32_t fan_speed_rpm;
2849         int ret;
2850
2851         ret = vega12_get_metrics_table(hwmgr, &metrics, true);
2852         if (ret)
2853                 return ret;
2854
2855         vega12_init_gpu_metrics_v1_0(gpu_metrics);
2856
2857         gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2858         gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2859         gpu_metrics->temperature_mem = metrics.TemperatureHBM;
2860         gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2861         gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem;
2862
2863         gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2864         gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2865
2866         gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2867         gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2868         gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2869
2870         gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2871         gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2872         gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2873         gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2874         gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2875
2876         gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2877
2878         vega12_fan_ctrl_get_fan_speed_rpm(hwmgr, &fan_speed_rpm);
2879         gpu_metrics->current_fan_speed = (uint16_t)fan_speed_rpm;
2880
2881         gpu_metrics->pcie_link_width =
2882                         vega12_get_current_pcie_link_width(hwmgr);
2883         gpu_metrics->pcie_link_speed =
2884                         vega12_get_current_pcie_link_speed(hwmgr);
2885
2886         *table = (void *)gpu_metrics;
2887
2888         return sizeof(struct gpu_metrics_v1_0);
2889 }
2890
2891 static const struct pp_hwmgr_func vega12_hwmgr_funcs = {
2892         .backend_init = vega12_hwmgr_backend_init,
2893         .backend_fini = vega12_hwmgr_backend_fini,
2894         .asic_setup = vega12_setup_asic_task,
2895         .dynamic_state_management_enable = vega12_enable_dpm_tasks,
2896         .dynamic_state_management_disable = vega12_disable_dpm_tasks,
2897         .patch_boot_state = vega12_patch_boot_state,
2898         .get_sclk = vega12_dpm_get_sclk,
2899         .get_mclk = vega12_dpm_get_mclk,
2900         .notify_smc_display_config_after_ps_adjustment =
2901                         vega12_notify_smc_display_config_after_ps_adjustment,
2902         .force_dpm_level = vega12_dpm_force_dpm_level,
2903         .stop_thermal_controller = vega12_thermal_stop_thermal_controller,
2904         .get_fan_speed_info = vega12_fan_ctrl_get_fan_speed_info,
2905         .reset_fan_speed_to_default =
2906                         vega12_fan_ctrl_reset_fan_speed_to_default,
2907         .get_fan_speed_rpm = vega12_fan_ctrl_get_fan_speed_rpm,
2908         .set_fan_control_mode = vega12_set_fan_control_mode,
2909         .get_fan_control_mode = vega12_get_fan_control_mode,
2910         .read_sensor = vega12_read_sensor,
2911         .get_dal_power_level = vega12_get_dal_power_level,
2912         .get_clock_by_type_with_latency = vega12_get_clock_by_type_with_latency,
2913         .get_clock_by_type_with_voltage = vega12_get_clock_by_type_with_voltage,
2914         .set_watermarks_for_clocks_ranges = vega12_set_watermarks_for_clocks_ranges,
2915         .display_clock_voltage_request = vega12_display_clock_voltage_request,
2916         .force_clock_level = vega12_force_clock_level,
2917         .print_clock_levels = vega12_print_clock_levels,
2918         .apply_clocks_adjust_rules =
2919                 vega12_apply_clocks_adjust_rules,
2920         .pre_display_config_changed =
2921                 vega12_pre_display_configuration_changed_task,
2922         .display_config_changed = vega12_display_configuration_changed_task,
2923         .powergate_uvd = vega12_power_gate_uvd,
2924         .powergate_vce = vega12_power_gate_vce,
2925         .check_smc_update_required_for_display_configuration =
2926                         vega12_check_smc_update_required_for_display_configuration,
2927         .power_off_asic = vega12_power_off_asic,
2928         .disable_smc_firmware_ctf = vega12_thermal_disable_alert,
2929 #if 0
2930         .set_power_profile_state = vega12_set_power_profile_state,
2931         .get_sclk_od = vega12_get_sclk_od,
2932         .set_sclk_od = vega12_set_sclk_od,
2933         .get_mclk_od = vega12_get_mclk_od,
2934         .set_mclk_od = vega12_set_mclk_od,
2935 #endif
2936         .notify_cac_buffer_info = vega12_notify_cac_buffer_info,
2937         .get_thermal_temperature_range = vega12_get_thermal_temperature_range,
2938         .register_irq_handlers = smu9_register_irq_handlers,
2939         .start_thermal_controller = vega12_start_thermal_controller,
2940         .powergate_gfx = vega12_gfx_off_control,
2941         .get_performance_level = vega12_get_performance_level,
2942         .get_asic_baco_capability = smu9_baco_get_capability,
2943         .get_asic_baco_state = smu9_baco_get_state,
2944         .set_asic_baco_state = vega12_baco_set_state,
2945         .get_ppfeature_status = vega12_get_ppfeature_status,
2946         .set_ppfeature_status = vega12_set_ppfeature_status,
2947         .set_mp1_state = vega12_set_mp1_state,
2948         .get_gpu_metrics = vega12_get_gpu_metrics,
2949 };
2950
2951 int vega12_hwmgr_init(struct pp_hwmgr *hwmgr)
2952 {
2953         hwmgr->hwmgr_func = &vega12_hwmgr_funcs;
2954         hwmgr->pptable_func = &vega12_pptable_funcs;
2955
2956         return 0;
2957 }