2 * Copyright 2015 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/slab.h>
27 #include "atom-types.h"
29 #include "processpptables.h"
30 #include "cgs_common.h"
33 #include "hardwaremanager.h"
35 #include "smu10_hwmgr.h"
36 #include "power_state.h"
37 #include "soc15_common.h"
39 #include "asic_reg/pwr/pwr_10_0_offset.h"
40 #include "asic_reg/pwr/pwr_10_0_sh_mask.h"
42 #define SMU10_MAX_DEEPSLEEP_DIVIDER_ID 5
43 #define SMU10_MINIMUM_ENGINE_CLOCK 800 /* 8Mhz, the low boundary of engine clock allowed on this chip */
44 #define SCLK_MIN_DIV_INTV_SHIFT 12
45 #define SMU10_DISPCLK_BYPASS_THRESHOLD 10000 /* 100Mhz */
46 #define SMC_RAM_END 0x40000
48 static const unsigned long SMU10_Magic = (unsigned long) PHM_Rv_Magic;
51 static int smu10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
52 struct pp_display_clock_request *clock_req)
54 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
55 enum amd_pp_clock_type clk_type = clock_req->clock_type;
56 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
60 case amd_pp_dcf_clock:
61 if (clk_freq == smu10_data->dcf_actual_hard_min_freq)
63 msg = PPSMC_MSG_SetHardMinDcefclkByFreq;
64 smu10_data->dcf_actual_hard_min_freq = clk_freq;
66 case amd_pp_soc_clock:
67 msg = PPSMC_MSG_SetHardMinSocclkByFreq;
70 if (clk_freq == smu10_data->f_actual_hard_min_freq)
72 smu10_data->f_actual_hard_min_freq = clk_freq;
73 msg = PPSMC_MSG_SetHardMinFclkByFreq;
76 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
79 smum_send_msg_to_smc_with_parameter(hwmgr, msg, clk_freq, NULL);
84 static struct smu10_power_state *cast_smu10_ps(struct pp_hw_power_state *hw_ps)
86 if (SMU10_Magic != hw_ps->magic)
89 return (struct smu10_power_state *)hw_ps;
92 static const struct smu10_power_state *cast_const_smu10_ps(
93 const struct pp_hw_power_state *hw_ps)
95 if (SMU10_Magic != hw_ps->magic)
98 return (struct smu10_power_state *)hw_ps;
101 static int smu10_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
103 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
105 smu10_data->dce_slow_sclk_threshold = 30000;
106 smu10_data->thermal_auto_throttling_treshold = 0;
107 smu10_data->is_nb_dpm_enabled = 1;
108 smu10_data->dpm_flags = 1;
109 smu10_data->need_min_deep_sleep_dcefclk = true;
110 smu10_data->num_active_display = 0;
111 smu10_data->deep_sleep_dcefclk = 0;
113 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
114 PHM_PlatformCaps_SclkDeepSleep);
116 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
117 PHM_PlatformCaps_SclkThrottleLowNotification);
119 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
120 PHM_PlatformCaps_PowerPlaySupport);
124 static int smu10_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
125 struct phm_clock_and_voltage_limits *table)
130 static int smu10_init_dynamic_state_adjustment_rule_settings(
131 struct pp_hwmgr *hwmgr)
134 struct phm_clock_voltage_dependency_table *table_clk_vlt;
136 table_clk_vlt = kzalloc(struct_size(table_clk_vlt, entries, count),
139 if (NULL == table_clk_vlt) {
140 pr_err("Can not allocate memory!\n");
144 table_clk_vlt->count = count;
145 table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
146 table_clk_vlt->entries[0].v = 0;
147 table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
148 table_clk_vlt->entries[1].v = 1;
149 table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
150 table_clk_vlt->entries[2].v = 2;
151 table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
152 table_clk_vlt->entries[3].v = 3;
153 table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
154 table_clk_vlt->entries[4].v = 4;
155 table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
156 table_clk_vlt->entries[5].v = 5;
157 table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
158 table_clk_vlt->entries[6].v = 6;
159 table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
160 table_clk_vlt->entries[7].v = 7;
161 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
166 static int smu10_get_system_info_data(struct pp_hwmgr *hwmgr)
168 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)hwmgr->backend;
170 smu10_data->sys_info.htc_hyst_lmt = 5;
171 smu10_data->sys_info.htc_tmp_lmt = 203;
173 if (smu10_data->thermal_auto_throttling_treshold == 0)
174 smu10_data->thermal_auto_throttling_treshold = 203;
176 smu10_construct_max_power_limits_table (hwmgr,
177 &hwmgr->dyn_state.max_clock_voltage_on_ac);
179 smu10_init_dynamic_state_adjustment_rule_settings(hwmgr);
184 static int smu10_construct_boot_state(struct pp_hwmgr *hwmgr)
189 static int smu10_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
191 struct PP_Clocks clocks = {0};
192 struct pp_display_clock_request clock_req;
194 clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
195 clock_req.clock_type = amd_pp_dcf_clock;
196 clock_req.clock_freq_in_khz = clocks.dcefClock * 10;
198 PP_ASSERT_WITH_CODE(!smu10_display_clock_voltage_request(hwmgr, &clock_req),
199 "Attempt to set DCF Clock Failed!", return -EINVAL);
204 static int smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
206 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
208 if (clock && smu10_data->deep_sleep_dcefclk != clock) {
209 smu10_data->deep_sleep_dcefclk = clock;
210 smum_send_msg_to_smc_with_parameter(hwmgr,
211 PPSMC_MSG_SetMinDeepSleepDcefclk,
212 smu10_data->deep_sleep_dcefclk,
218 static int smu10_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
220 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
222 if (clock && smu10_data->dcf_actual_hard_min_freq != clock) {
223 smu10_data->dcf_actual_hard_min_freq = clock;
224 smum_send_msg_to_smc_with_parameter(hwmgr,
225 PPSMC_MSG_SetHardMinDcefclkByFreq,
226 smu10_data->dcf_actual_hard_min_freq,
232 static int smu10_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
234 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
236 if (clock && smu10_data->f_actual_hard_min_freq != clock) {
237 smu10_data->f_actual_hard_min_freq = clock;
238 smum_send_msg_to_smc_with_parameter(hwmgr,
239 PPSMC_MSG_SetHardMinFclkByFreq,
240 smu10_data->f_actual_hard_min_freq,
246 static int smu10_set_hard_min_gfxclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
248 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
250 if (clock && smu10_data->gfx_actual_soft_min_freq != clock) {
251 smu10_data->gfx_actual_soft_min_freq = clock;
252 smum_send_msg_to_smc_with_parameter(hwmgr,
253 PPSMC_MSG_SetHardMinGfxClk,
260 static int smu10_set_soft_max_gfxclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
262 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
264 if (clock && smu10_data->gfx_max_freq_limit != (clock * 100)) {
265 smu10_data->gfx_max_freq_limit = clock * 100;
266 smum_send_msg_to_smc_with_parameter(hwmgr,
267 PPSMC_MSG_SetSoftMaxGfxClk,
274 static int smu10_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)
276 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
278 if (smu10_data->num_active_display != count) {
279 smu10_data->num_active_display = count;
280 smum_send_msg_to_smc_with_parameter(hwmgr,
281 PPSMC_MSG_SetDisplayCount,
282 smu10_data->num_active_display,
289 static int smu10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
291 return smu10_set_clock_limit(hwmgr, input);
294 static int smu10_init_power_gate_state(struct pp_hwmgr *hwmgr)
296 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
297 struct amdgpu_device *adev = hwmgr->adev;
299 smu10_data->vcn_power_gated = true;
300 smu10_data->isp_tileA_power_gated = true;
301 smu10_data->isp_tileB_power_gated = true;
303 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)
304 return smum_send_msg_to_smc_with_parameter(hwmgr,
305 PPSMC_MSG_SetGfxCGPG,
313 static int smu10_setup_asic_task(struct pp_hwmgr *hwmgr)
315 return smu10_init_power_gate_state(hwmgr);
318 static int smu10_reset_cc6_data(struct pp_hwmgr *hwmgr)
320 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
322 smu10_data->separation_time = 0;
323 smu10_data->cc6_disable = false;
324 smu10_data->pstate_disable = false;
325 smu10_data->cc6_setting_changed = false;
330 static int smu10_power_off_asic(struct pp_hwmgr *hwmgr)
332 return smu10_reset_cc6_data(hwmgr);
335 static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)
338 struct amdgpu_device *adev = hwmgr->adev;
340 reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS);
341 if ((reg & PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK) ==
342 (0x2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT))
348 static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
350 struct amdgpu_device *adev = hwmgr->adev;
352 if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
353 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableGfxOff, NULL);
355 /* confirm gfx is back to "on" state */
356 while (!smu10_is_gfx_on(hwmgr))
363 static int smu10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
368 static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr)
370 struct amdgpu_device *adev = hwmgr->adev;
372 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
373 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableGfxOff, NULL);
378 static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
383 static int smu10_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
386 return smu10_enable_gfx_off(hwmgr);
388 return smu10_disable_gfx_off(hwmgr);
391 static int smu10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
392 struct pp_power_state *prequest_ps,
393 const struct pp_power_state *pcurrent_ps)
398 /* temporary hardcoded clock voltage breakdown tables */
399 static const DpmClock_t VddDcfClk[]= {
405 static const DpmClock_t VddSocClk[]= {
411 static const DpmClock_t VddFClk[]= {
417 static const DpmClock_t VddDispClk[]= {
423 static const DpmClock_t VddDppClk[]= {
429 static const DpmClock_t VddPhyClk[]= {
435 static int smu10_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
436 struct smu10_voltage_dependency_table **pptable,
437 uint32_t num_entry, const DpmClock_t *pclk_dependency_table)
440 struct smu10_voltage_dependency_table *ptable;
442 ptable = kzalloc(struct_size(ptable, entries, num_entry), GFP_KERNEL);
446 ptable->count = num_entry;
448 for (i = 0; i < ptable->count; i++) {
449 ptable->entries[i].clk = pclk_dependency_table->Freq * 100;
450 ptable->entries[i].vol = pclk_dependency_table->Vol;
451 pclk_dependency_table++;
460 static int smu10_populate_clock_table(struct pp_hwmgr *hwmgr)
464 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
465 DpmClocks_t *table = &(smu10_data->clock_table);
466 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
468 result = smum_smc_table_manager(hwmgr, (uint8_t *)table, SMU10_CLOCKTABLE, true);
470 PP_ASSERT_WITH_CODE((0 == result),
471 "Attempt to copy clock table from smc failed",
474 if (0 == result && table->DcefClocks[0].Freq != 0) {
475 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
476 NUM_DCEFCLK_DPM_LEVELS,
477 &smu10_data->clock_table.DcefClocks[0]);
478 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
479 NUM_SOCCLK_DPM_LEVELS,
480 &smu10_data->clock_table.SocClocks[0]);
481 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
483 &smu10_data->clock_table.FClocks[0]);
484 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_mclk,
485 NUM_MEMCLK_DPM_LEVELS,
486 &smu10_data->clock_table.MemClocks[0]);
488 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
489 ARRAY_SIZE(VddDcfClk),
491 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
492 ARRAY_SIZE(VddSocClk),
494 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
498 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dispclk,
499 ARRAY_SIZE(VddDispClk),
501 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dppclk,
502 ARRAY_SIZE(VddDppClk), &VddDppClk[0]);
503 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk,
504 ARRAY_SIZE(VddPhyClk), &VddPhyClk[0]);
506 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &result);
507 smu10_data->gfx_min_freq_limit = result / 10 * 1000;
509 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &result);
510 smu10_data->gfx_max_freq_limit = result / 10 * 1000;
515 static int smu10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
518 struct smu10_hwmgr *data;
520 data = kzalloc(sizeof(struct smu10_hwmgr), GFP_KERNEL);
524 hwmgr->backend = data;
526 result = smu10_initialize_dpm_defaults(hwmgr);
528 pr_err("smu10_initialize_dpm_defaults failed\n");
532 smu10_populate_clock_table(hwmgr);
534 result = smu10_get_system_info_data(hwmgr);
536 pr_err("smu10_get_system_info_data failed\n");
540 smu10_construct_boot_state(hwmgr);
542 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
543 SMU10_MAX_HARDWARE_POWERLEVELS;
545 hwmgr->platform_descriptor.hardwarePerformanceLevels =
546 SMU10_MAX_HARDWARE_POWERLEVELS;
548 hwmgr->platform_descriptor.vbiosInterruptId = 0;
550 hwmgr->platform_descriptor.clockStep.engineClock = 500;
552 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
554 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
556 hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK * 100;
557 hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK * 100;
559 /* enable the pp_od_clk_voltage sysfs file */
560 hwmgr->od_enabled = 1;
561 /* disabled fine grain tuning function by default */
562 data->fine_grain_enabled = 0;
566 static int smu10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
568 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
569 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
571 kfree(pinfo->vdd_dep_on_dcefclk);
572 pinfo->vdd_dep_on_dcefclk = NULL;
573 kfree(pinfo->vdd_dep_on_socclk);
574 pinfo->vdd_dep_on_socclk = NULL;
575 kfree(pinfo->vdd_dep_on_fclk);
576 pinfo->vdd_dep_on_fclk = NULL;
577 kfree(pinfo->vdd_dep_on_dispclk);
578 pinfo->vdd_dep_on_dispclk = NULL;
579 kfree(pinfo->vdd_dep_on_dppclk);
580 pinfo->vdd_dep_on_dppclk = NULL;
581 kfree(pinfo->vdd_dep_on_phyclk);
582 pinfo->vdd_dep_on_phyclk = NULL;
584 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
585 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
587 kfree(hwmgr->backend);
588 hwmgr->backend = NULL;
593 static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
594 enum amd_dpm_forced_level level)
596 struct smu10_hwmgr *data = hwmgr->backend;
597 uint32_t min_sclk = hwmgr->display_config->min_core_set_clock;
598 uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100;
599 uint32_t index_fclk = data->clock_vol_info.vdd_dep_on_fclk->count - 1;
600 uint32_t index_socclk = data->clock_vol_info.vdd_dep_on_socclk->count - 1;
601 uint32_t fine_grain_min_freq = 0, fine_grain_max_freq = 0;
603 if (hwmgr->smu_version < 0x1E3700) {
604 pr_info("smu firmware version too old, can not set dpm level\n");
608 if (min_sclk < data->gfx_min_freq_limit)
609 min_sclk = data->gfx_min_freq_limit;
611 min_sclk /= 100; /* transfer 10KHz to MHz */
612 if (min_mclk < data->clock_table.FClocks[0].Freq)
613 min_mclk = data->clock_table.FClocks[0].Freq;
616 case AMD_DPM_FORCED_LEVEL_HIGH:
617 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
618 data->fine_grain_enabled = 0;
620 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
621 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
623 data->gfx_actual_soft_min_freq = fine_grain_min_freq;
624 data->gfx_actual_soft_max_freq = fine_grain_max_freq;
626 smum_send_msg_to_smc_with_parameter(hwmgr,
627 PPSMC_MSG_SetHardMinGfxClk,
628 data->gfx_max_freq_limit/100,
630 smum_send_msg_to_smc_with_parameter(hwmgr,
631 PPSMC_MSG_SetHardMinFclkByFreq,
632 SMU10_UMD_PSTATE_PEAK_FCLK,
634 smum_send_msg_to_smc_with_parameter(hwmgr,
635 PPSMC_MSG_SetHardMinSocclkByFreq,
636 SMU10_UMD_PSTATE_PEAK_SOCCLK,
638 smum_send_msg_to_smc_with_parameter(hwmgr,
639 PPSMC_MSG_SetHardMinVcn,
640 SMU10_UMD_PSTATE_VCE,
643 smum_send_msg_to_smc_with_parameter(hwmgr,
644 PPSMC_MSG_SetSoftMaxGfxClk,
645 data->gfx_max_freq_limit/100,
647 smum_send_msg_to_smc_with_parameter(hwmgr,
648 PPSMC_MSG_SetSoftMaxFclkByFreq,
649 SMU10_UMD_PSTATE_PEAK_FCLK,
651 smum_send_msg_to_smc_with_parameter(hwmgr,
652 PPSMC_MSG_SetSoftMaxSocclkByFreq,
653 SMU10_UMD_PSTATE_PEAK_SOCCLK,
655 smum_send_msg_to_smc_with_parameter(hwmgr,
656 PPSMC_MSG_SetSoftMaxVcn,
657 SMU10_UMD_PSTATE_VCE,
660 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
661 data->fine_grain_enabled = 0;
663 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
664 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
666 data->gfx_actual_soft_min_freq = fine_grain_min_freq;
667 data->gfx_actual_soft_max_freq = fine_grain_max_freq;
669 smum_send_msg_to_smc_with_parameter(hwmgr,
670 PPSMC_MSG_SetHardMinGfxClk,
673 smum_send_msg_to_smc_with_parameter(hwmgr,
674 PPSMC_MSG_SetSoftMaxGfxClk,
678 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
679 data->fine_grain_enabled = 0;
681 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
682 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
684 data->gfx_actual_soft_min_freq = fine_grain_min_freq;
685 data->gfx_actual_soft_max_freq = fine_grain_max_freq;
687 smum_send_msg_to_smc_with_parameter(hwmgr,
688 PPSMC_MSG_SetHardMinFclkByFreq,
691 smum_send_msg_to_smc_with_parameter(hwmgr,
692 PPSMC_MSG_SetSoftMaxFclkByFreq,
696 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
697 data->fine_grain_enabled = 0;
699 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
700 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
702 data->gfx_actual_soft_min_freq = fine_grain_min_freq;
703 data->gfx_actual_soft_max_freq = fine_grain_max_freq;
705 smum_send_msg_to_smc_with_parameter(hwmgr,
706 PPSMC_MSG_SetHardMinGfxClk,
707 SMU10_UMD_PSTATE_GFXCLK,
709 smum_send_msg_to_smc_with_parameter(hwmgr,
710 PPSMC_MSG_SetHardMinFclkByFreq,
711 SMU10_UMD_PSTATE_FCLK,
713 smum_send_msg_to_smc_with_parameter(hwmgr,
714 PPSMC_MSG_SetHardMinSocclkByFreq,
715 SMU10_UMD_PSTATE_SOCCLK,
717 smum_send_msg_to_smc_with_parameter(hwmgr,
718 PPSMC_MSG_SetHardMinVcn,
719 SMU10_UMD_PSTATE_PROFILE_VCE,
722 smum_send_msg_to_smc_with_parameter(hwmgr,
723 PPSMC_MSG_SetSoftMaxGfxClk,
724 SMU10_UMD_PSTATE_GFXCLK,
726 smum_send_msg_to_smc_with_parameter(hwmgr,
727 PPSMC_MSG_SetSoftMaxFclkByFreq,
728 SMU10_UMD_PSTATE_FCLK,
730 smum_send_msg_to_smc_with_parameter(hwmgr,
731 PPSMC_MSG_SetSoftMaxSocclkByFreq,
732 SMU10_UMD_PSTATE_SOCCLK,
734 smum_send_msg_to_smc_with_parameter(hwmgr,
735 PPSMC_MSG_SetSoftMaxVcn,
736 SMU10_UMD_PSTATE_PROFILE_VCE,
739 case AMD_DPM_FORCED_LEVEL_AUTO:
740 data->fine_grain_enabled = 0;
742 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
743 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
745 data->gfx_actual_soft_min_freq = fine_grain_min_freq;
746 data->gfx_actual_soft_max_freq = fine_grain_max_freq;
748 smum_send_msg_to_smc_with_parameter(hwmgr,
749 PPSMC_MSG_SetHardMinGfxClk,
752 smum_send_msg_to_smc_with_parameter(hwmgr,
753 PPSMC_MSG_SetHardMinFclkByFreq,
754 hwmgr->display_config->num_display > 3 ?
755 data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk :
759 smum_send_msg_to_smc_with_parameter(hwmgr,
760 PPSMC_MSG_SetHardMinSocclkByFreq,
761 data->clock_vol_info.vdd_dep_on_socclk->entries[0].clk,
763 smum_send_msg_to_smc_with_parameter(hwmgr,
764 PPSMC_MSG_SetHardMinVcn,
765 SMU10_UMD_PSTATE_MIN_VCE,
768 smum_send_msg_to_smc_with_parameter(hwmgr,
769 PPSMC_MSG_SetSoftMaxGfxClk,
770 data->gfx_max_freq_limit/100,
772 smum_send_msg_to_smc_with_parameter(hwmgr,
773 PPSMC_MSG_SetSoftMaxFclkByFreq,
774 data->clock_vol_info.vdd_dep_on_fclk->entries[index_fclk].clk,
776 smum_send_msg_to_smc_with_parameter(hwmgr,
777 PPSMC_MSG_SetSoftMaxSocclkByFreq,
778 data->clock_vol_info.vdd_dep_on_socclk->entries[index_socclk].clk,
780 smum_send_msg_to_smc_with_parameter(hwmgr,
781 PPSMC_MSG_SetSoftMaxVcn,
782 SMU10_UMD_PSTATE_VCE,
785 case AMD_DPM_FORCED_LEVEL_LOW:
786 data->fine_grain_enabled = 0;
788 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
789 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
791 data->gfx_actual_soft_min_freq = fine_grain_min_freq;
792 data->gfx_actual_soft_max_freq = fine_grain_max_freq;
794 smum_send_msg_to_smc_with_parameter(hwmgr,
795 PPSMC_MSG_SetHardMinGfxClk,
796 data->gfx_min_freq_limit/100,
798 smum_send_msg_to_smc_with_parameter(hwmgr,
799 PPSMC_MSG_SetSoftMaxGfxClk,
800 data->gfx_min_freq_limit/100,
802 smum_send_msg_to_smc_with_parameter(hwmgr,
803 PPSMC_MSG_SetHardMinFclkByFreq,
806 smum_send_msg_to_smc_with_parameter(hwmgr,
807 PPSMC_MSG_SetSoftMaxFclkByFreq,
811 case AMD_DPM_FORCED_LEVEL_MANUAL:
812 data->fine_grain_enabled = 1;
814 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
821 static uint32_t smu10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
823 struct smu10_hwmgr *data;
828 data = (struct smu10_hwmgr *)(hwmgr->backend);
831 return data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
833 return data->clock_vol_info.vdd_dep_on_fclk->entries[
834 data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;
837 static uint32_t smu10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
839 struct smu10_hwmgr *data;
844 data = (struct smu10_hwmgr *)(hwmgr->backend);
847 return data->gfx_min_freq_limit;
849 return data->gfx_max_freq_limit;
852 static int smu10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
853 struct pp_hw_power_state *hw_ps)
858 static int smu10_dpm_get_pp_table_entry_callback(
859 struct pp_hwmgr *hwmgr,
860 struct pp_hw_power_state *hw_ps,
862 const void *clock_info)
864 struct smu10_power_state *smu10_ps = cast_smu10_ps(hw_ps);
866 smu10_ps->levels[index].engine_clock = 0;
868 smu10_ps->levels[index].vddc_index = 0;
869 smu10_ps->level = index + 1;
871 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
872 smu10_ps->levels[index].ds_divider_index = 5;
873 smu10_ps->levels[index].ss_divider_index = 5;
879 static int smu10_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
882 unsigned long ret = 0;
884 result = pp_tables_get_num_of_entries(hwmgr, &ret);
886 return result ? 0 : ret;
889 static int smu10_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
890 unsigned long entry, struct pp_power_state *ps)
893 struct smu10_power_state *smu10_ps;
895 ps->hardware.magic = SMU10_Magic;
897 smu10_ps = cast_smu10_ps(&(ps->hardware));
899 result = pp_tables_get_entry(hwmgr, entry, ps,
900 smu10_dpm_get_pp_table_entry_callback);
902 smu10_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
903 smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
908 static int smu10_get_power_state_size(struct pp_hwmgr *hwmgr)
910 return sizeof(struct smu10_power_state);
913 static int smu10_set_cpu_power_state(struct pp_hwmgr *hwmgr)
919 static int smu10_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
920 bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
922 struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend);
924 if (separation_time != data->separation_time ||
925 cc6_disable != data->cc6_disable ||
926 pstate_disable != data->pstate_disable) {
927 data->separation_time = separation_time;
928 data->cc6_disable = cc6_disable;
929 data->pstate_disable = pstate_disable;
930 data->cc6_setting_changed = true;
935 static int smu10_get_dal_power_level(struct pp_hwmgr *hwmgr,
936 struct amd_pp_simple_clock_info *info)
941 static int smu10_force_clock_level(struct pp_hwmgr *hwmgr,
942 enum pp_clock_type type, uint32_t mask)
944 struct smu10_hwmgr *data = hwmgr->backend;
945 struct smu10_voltage_dependency_table *mclk_table =
946 data->clock_vol_info.vdd_dep_on_fclk;
949 low = mask ? (ffs(mask) - 1) : 0;
950 high = mask ? (fls(mask) - 1) : 0;
954 if (low > 2 || high > 2) {
955 pr_info("Currently sclk only support 3 levels on RV\n");
959 smum_send_msg_to_smc_with_parameter(hwmgr,
960 PPSMC_MSG_SetHardMinGfxClk,
961 low == 2 ? data->gfx_max_freq_limit/100 :
962 low == 1 ? SMU10_UMD_PSTATE_GFXCLK :
963 data->gfx_min_freq_limit/100,
966 smum_send_msg_to_smc_with_parameter(hwmgr,
967 PPSMC_MSG_SetSoftMaxGfxClk,
968 high == 0 ? data->gfx_min_freq_limit/100 :
969 high == 1 ? SMU10_UMD_PSTATE_GFXCLK :
970 data->gfx_max_freq_limit/100,
975 if (low > mclk_table->count - 1 || high > mclk_table->count - 1)
978 smum_send_msg_to_smc_with_parameter(hwmgr,
979 PPSMC_MSG_SetHardMinFclkByFreq,
980 mclk_table->entries[low].clk/100,
983 smum_send_msg_to_smc_with_parameter(hwmgr,
984 PPSMC_MSG_SetSoftMaxFclkByFreq,
985 mclk_table->entries[high].clk/100,
996 static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr,
997 enum pp_clock_type type, char *buf)
999 struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend);
1000 struct smu10_voltage_dependency_table *mclk_table =
1001 data->clock_vol_info.vdd_dep_on_fclk;
1002 uint32_t i, now, size = 0;
1003 uint32_t min_freq, max_freq = 0;
1008 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &now);
1010 /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
1011 if (now == data->gfx_max_freq_limit/100)
1013 else if (now == data->gfx_min_freq_limit/100)
1018 size += sprintf(buf + size, "0: %uMhz %s\n",
1019 data->gfx_min_freq_limit/100,
1021 size += sprintf(buf + size, "1: %uMhz %s\n",
1022 i == 1 ? now : SMU10_UMD_PSTATE_GFXCLK,
1024 size += sprintf(buf + size, "2: %uMhz %s\n",
1025 data->gfx_max_freq_limit/100,
1029 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &now);
1031 for (i = 0; i < mclk_table->count; i++)
1032 size += sprintf(buf + size, "%d: %uMhz %s\n",
1034 mclk_table->entries[i].clk / 100,
1035 ((mclk_table->entries[i].clk / 100)
1036 == now) ? "*" : "");
1039 if (hwmgr->od_enabled) {
1040 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
1043 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
1047 size = sprintf(buf, "%s:\n", "OD_SCLK");
1048 size += sprintf(buf + size, "0: %10uMhz\n",
1049 (data->gfx_actual_soft_min_freq > 0) ? data->gfx_actual_soft_min_freq : min_freq);
1050 size += sprintf(buf + size, "1: %10uMhz\n",
1051 (data->gfx_actual_soft_max_freq > 0) ? data->gfx_actual_soft_max_freq : max_freq);
1055 if (hwmgr->od_enabled) {
1056 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
1059 ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
1063 size = sprintf(buf, "%s:\n", "OD_RANGE");
1064 size += sprintf(buf + size, "SCLK: %7uMHz %10uMHz\n",
1065 min_freq, max_freq);
1075 static int smu10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
1076 PHM_PerformanceLevelDesignation designation, uint32_t index,
1077 PHM_PerformanceLevel *level)
1079 struct smu10_hwmgr *data;
1081 if (level == NULL || hwmgr == NULL || state == NULL)
1084 data = (struct smu10_hwmgr *)(hwmgr->backend);
1087 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
1088 level->coreClock = data->gfx_min_freq_limit;
1090 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[
1091 data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;
1092 level->coreClock = data->gfx_max_freq_limit;
1095 level->nonLocalMemoryFreq = 0;
1096 level->nonLocalMemoryWidth = 0;
1101 static int smu10_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
1102 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
1104 const struct smu10_power_state *ps = cast_const_smu10_ps(state);
1106 clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index));
1107 clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1].ss_divider_index));
1112 #define MEM_FREQ_LOW_LATENCY 25000
1113 #define MEM_FREQ_HIGH_LATENCY 80000
1114 #define MEM_LATENCY_HIGH 245
1115 #define MEM_LATENCY_LOW 35
1116 #define MEM_LATENCY_ERR 0xFFFF
1119 static uint32_t smu10_get_mem_latency(struct pp_hwmgr *hwmgr,
1122 if (clock >= MEM_FREQ_LOW_LATENCY &&
1123 clock < MEM_FREQ_HIGH_LATENCY)
1124 return MEM_LATENCY_HIGH;
1125 else if (clock >= MEM_FREQ_HIGH_LATENCY)
1126 return MEM_LATENCY_LOW;
1128 return MEM_LATENCY_ERR;
1131 static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
1132 enum amd_pp_clock_type type,
1133 struct pp_clock_levels_with_latency *clocks)
1136 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1137 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
1138 struct smu10_voltage_dependency_table *pclk_vol_table;
1139 bool latency_required = false;
1145 case amd_pp_mem_clock:
1146 pclk_vol_table = pinfo->vdd_dep_on_mclk;
1147 latency_required = true;
1149 case amd_pp_f_clock:
1150 pclk_vol_table = pinfo->vdd_dep_on_fclk;
1151 latency_required = true;
1153 case amd_pp_dcf_clock:
1154 pclk_vol_table = pinfo->vdd_dep_on_dcefclk;
1156 case amd_pp_disp_clock:
1157 pclk_vol_table = pinfo->vdd_dep_on_dispclk;
1159 case amd_pp_phy_clock:
1160 pclk_vol_table = pinfo->vdd_dep_on_phyclk;
1162 case amd_pp_dpp_clock:
1163 pclk_vol_table = pinfo->vdd_dep_on_dppclk;
1169 if (pclk_vol_table == NULL || pclk_vol_table->count == 0)
1172 clocks->num_levels = 0;
1173 for (i = 0; i < pclk_vol_table->count; i++) {
1174 if (pclk_vol_table->entries[i].clk) {
1175 clocks->data[clocks->num_levels].clocks_in_khz =
1176 pclk_vol_table->entries[i].clk * 10;
1177 clocks->data[clocks->num_levels].latency_in_us = latency_required ?
1178 smu10_get_mem_latency(hwmgr,
1179 pclk_vol_table->entries[i].clk) :
1181 clocks->num_levels++;
1188 static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
1189 enum amd_pp_clock_type type,
1190 struct pp_clock_levels_with_voltage *clocks)
1193 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1194 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
1195 struct smu10_voltage_dependency_table *pclk_vol_table = NULL;
1201 case amd_pp_mem_clock:
1202 pclk_vol_table = pinfo->vdd_dep_on_mclk;
1204 case amd_pp_f_clock:
1205 pclk_vol_table = pinfo->vdd_dep_on_fclk;
1207 case amd_pp_dcf_clock:
1208 pclk_vol_table = pinfo->vdd_dep_on_dcefclk;
1210 case amd_pp_soc_clock:
1211 pclk_vol_table = pinfo->vdd_dep_on_socclk;
1213 case amd_pp_disp_clock:
1214 pclk_vol_table = pinfo->vdd_dep_on_dispclk;
1216 case amd_pp_phy_clock:
1217 pclk_vol_table = pinfo->vdd_dep_on_phyclk;
1223 if (pclk_vol_table == NULL || pclk_vol_table->count == 0)
1226 clocks->num_levels = 0;
1227 for (i = 0; i < pclk_vol_table->count; i++) {
1228 if (pclk_vol_table->entries[i].clk) {
1229 clocks->data[clocks->num_levels].clocks_in_khz = pclk_vol_table->entries[i].clk * 10;
1230 clocks->data[clocks->num_levels].voltage_in_mv = pclk_vol_table->entries[i].vol;
1231 clocks->num_levels++;
1240 static int smu10_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
1242 clocks->engine_max_clock = 80000; /* driver can't get engine clock, temp hard code to 800MHz */
1246 static int smu10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
1248 struct amdgpu_device *adev = hwmgr->adev;
1249 uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP);
1251 (reg_value & THM_TCON_CUR_TMP__CUR_TEMP_MASK) >> THM_TCON_CUR_TMP__CUR_TEMP__SHIFT;
1253 if (cur_temp & THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK)
1254 cur_temp = ((cur_temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1256 cur_temp = (cur_temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1261 static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1262 void *value, int *size)
1264 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1265 struct amdgpu_device *adev = hwmgr->adev;
1266 uint32_t sclk, mclk, activity_percent;
1270 /* GetGfxBusy support was added on RV SMU FW 30.85.00 and PCO 4.30.59 */
1271 if ((adev->apu_flags & AMD_APU_IS_PICASSO) &&
1272 (hwmgr->smu_version >= 0x41e3b))
1273 has_gfx_busy = true;
1274 else if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
1275 (hwmgr->smu_version >= 0x1e5500))
1276 has_gfx_busy = true;
1278 has_gfx_busy = false;
1281 case AMDGPU_PP_SENSOR_GFX_SCLK:
1282 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &sclk);
1283 /* in units of 10KHZ */
1284 *((uint32_t *)value) = sclk * 100;
1287 case AMDGPU_PP_SENSOR_GFX_MCLK:
1288 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &mclk);
1289 /* in units of 10KHZ */
1290 *((uint32_t *)value) = mclk * 100;
1293 case AMDGPU_PP_SENSOR_GPU_TEMP:
1294 *((uint32_t *)value) = smu10_thermal_get_temperature(hwmgr);
1296 case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
1297 *(uint32_t *)value = smu10_data->vcn_power_gated ? 0 : 1;
1300 case AMDGPU_PP_SENSOR_GPU_LOAD:
1304 ret = smum_send_msg_to_smc(hwmgr,
1305 PPSMC_MSG_GetGfxBusy,
1308 *((uint32_t *)value) = min(activity_percent, (u32)100);
1321 static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
1324 struct smu10_hwmgr *data = hwmgr->backend;
1325 struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
1326 Watermarks_t *table = &(data->water_marks_table);
1327 struct amdgpu_device *adev = hwmgr->adev;
1330 smu_set_watermarks_for_clocks_ranges(table,wm_with_clock_ranges);
1332 if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1333 for (i = 0; i < NUM_WM_RANGES; i++)
1334 table->WatermarkRow[WM_DCFCLK][i].WmType = (uint8_t)0;
1336 for (i = 0; i < NUM_WM_RANGES; i++)
1337 table->WatermarkRow[WM_SOCCLK][i].WmType = (uint8_t)0;
1340 smum_smc_table_manager(hwmgr, (uint8_t *)table, (uint16_t)SMU10_WMTABLE, false);
1341 data->water_marks_exist = true;
1345 static int smu10_smus_notify_pwe(struct pp_hwmgr *hwmgr)
1348 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SetRccPfcPmeRestoreRegister, NULL);
1351 static int smu10_powergate_mmhub(struct pp_hwmgr *hwmgr)
1353 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub, NULL);
1356 static int smu10_powergate_sdma(struct pp_hwmgr *hwmgr, bool gate)
1359 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerDownSdma, NULL);
1361 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerUpSdma, NULL);
1364 static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
1366 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1369 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
1370 AMD_IP_BLOCK_TYPE_VCN,
1372 smum_send_msg_to_smc_with_parameter(hwmgr,
1373 PPSMC_MSG_PowerDownVcn, 0, NULL);
1374 smu10_data->vcn_power_gated = true;
1376 smum_send_msg_to_smc_with_parameter(hwmgr,
1377 PPSMC_MSG_PowerUpVcn, 0, NULL);
1378 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
1379 AMD_IP_BLOCK_TYPE_VCN,
1380 AMD_PG_STATE_UNGATE);
1381 smu10_data->vcn_power_gated = false;
1385 static int conv_power_profile_to_pplib_workload(int power_profile)
1387 int pplib_workload = 0;
1389 switch (power_profile) {
1390 case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
1391 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
1393 case PP_SMC_POWER_PROFILE_VIDEO:
1394 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
1396 case PP_SMC_POWER_PROFILE_VR:
1397 pplib_workload = WORKLOAD_PPLIB_VR_BIT;
1399 case PP_SMC_POWER_PROFILE_COMPUTE:
1400 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
1402 case PP_SMC_POWER_PROFILE_CUSTOM:
1403 pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
1407 return pplib_workload;
1410 static int smu10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
1412 uint32_t i, size = 0;
1413 static const uint8_t
1414 profile_mode_setting[6][4] = {{70, 60, 0, 0,},
1421 static const char *profile_name[6] = {
1428 static const char *title[6] = {"NUM",
1433 "MIN_ACTIVE_LEVEL"};
1438 size += sprintf(buf + size, "%s %16s %s %s %s %s\n",title[0],
1439 title[1], title[2], title[3], title[4], title[5]);
1441 for (i = 0; i <= PP_SMC_POWER_PROFILE_COMPUTE; i++)
1442 size += sprintf(buf + size, "%3d %14s%s: %14d %3d %10d %14d\n",
1443 i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
1444 profile_mode_setting[i][0], profile_mode_setting[i][1],
1445 profile_mode_setting[i][2], profile_mode_setting[i][3]);
1450 static bool smu10_is_raven1_refresh(struct pp_hwmgr *hwmgr)
1452 struct amdgpu_device *adev = hwmgr->adev;
1453 if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
1454 (hwmgr->smu_version >= 0x41e2b))
1460 static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
1462 int workload_type = 0;
1465 if (input[size] > PP_SMC_POWER_PROFILE_COMPUTE) {
1466 pr_err("Invalid power profile mode %ld\n", input[size]);
1469 if (hwmgr->power_profile_mode == input[size])
1472 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1474 conv_power_profile_to_pplib_workload(input[size]);
1475 if (workload_type &&
1476 smu10_is_raven1_refresh(hwmgr) &&
1477 !hwmgr->gfxoff_state_changed_by_workload) {
1478 smu10_gfx_off_control(hwmgr, false);
1479 hwmgr->gfxoff_state_changed_by_workload = true;
1481 result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ActiveProcessNotify,
1485 hwmgr->power_profile_mode = input[size];
1486 if (workload_type && hwmgr->gfxoff_state_changed_by_workload) {
1487 smu10_gfx_off_control(hwmgr, true);
1488 hwmgr->gfxoff_state_changed_by_workload = false;
1494 static int smu10_asic_reset(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode)
1496 return smum_send_msg_to_smc_with_parameter(hwmgr,
1497 PPSMC_MSG_DeviceDriverReset,
1502 static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr *hwmgr,
1503 enum PP_OD_DPM_TABLE_COMMAND type,
1504 long *input, uint32_t size)
1506 uint32_t min_freq, max_freq = 0;
1507 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1510 if (!hwmgr->od_enabled) {
1511 pr_err("Fine grain not support\n");
1515 if (!smu10_data->fine_grain_enabled) {
1516 pr_err("pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n");
1520 if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
1522 pr_err("Input parameter number not correct\n");
1526 if (input[0] == 0) {
1527 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
1528 if (input[1] < min_freq) {
1529 pr_err("Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
1530 input[1], min_freq);
1533 smu10_data->gfx_actual_soft_min_freq = input[1];
1534 } else if (input[0] == 1) {
1535 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
1536 if (input[1] > max_freq) {
1537 pr_err("Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
1538 input[1], max_freq);
1541 smu10_data->gfx_actual_soft_max_freq = input[1];
1545 } else if (type == PP_OD_RESTORE_DEFAULT_TABLE) {
1547 pr_err("Input parameter number not correct\n");
1550 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
1551 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
1553 smu10_data->gfx_actual_soft_min_freq = min_freq;
1554 smu10_data->gfx_actual_soft_max_freq = max_freq;
1555 } else if (type == PP_OD_COMMIT_DPM_TABLE) {
1557 pr_err("Input parameter number not correct\n");
1561 if (smu10_data->gfx_actual_soft_min_freq > smu10_data->gfx_actual_soft_max_freq) {
1562 pr_err("The setting minimun sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
1563 smu10_data->gfx_actual_soft_min_freq, smu10_data->gfx_actual_soft_max_freq);
1567 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1568 PPSMC_MSG_SetHardMinGfxClk,
1569 smu10_data->gfx_actual_soft_min_freq,
1574 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1575 PPSMC_MSG_SetSoftMaxGfxClk,
1576 smu10_data->gfx_actual_soft_max_freq,
1587 static int smu10_gfx_state_change(struct pp_hwmgr *hwmgr, uint32_t state)
1589 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GpuChangeState, state, NULL);
1594 static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
1595 .backend_init = smu10_hwmgr_backend_init,
1596 .backend_fini = smu10_hwmgr_backend_fini,
1597 .apply_state_adjust_rules = smu10_apply_state_adjust_rules,
1598 .force_dpm_level = smu10_dpm_force_dpm_level,
1599 .get_power_state_size = smu10_get_power_state_size,
1600 .powerdown_uvd = NULL,
1601 .powergate_uvd = smu10_powergate_vcn,
1602 .powergate_vce = NULL,
1603 .get_mclk = smu10_dpm_get_mclk,
1604 .get_sclk = smu10_dpm_get_sclk,
1605 .patch_boot_state = smu10_dpm_patch_boot_state,
1606 .get_pp_table_entry = smu10_dpm_get_pp_table_entry,
1607 .get_num_of_pp_table_entries = smu10_dpm_get_num_of_pp_table_entries,
1608 .set_cpu_power_state = smu10_set_cpu_power_state,
1609 .store_cc6_data = smu10_store_cc6_data,
1610 .force_clock_level = smu10_force_clock_level,
1611 .print_clock_levels = smu10_print_clock_levels,
1612 .get_dal_power_level = smu10_get_dal_power_level,
1613 .get_performance_level = smu10_get_performance_level,
1614 .get_current_shallow_sleep_clocks = smu10_get_current_shallow_sleep_clocks,
1615 .get_clock_by_type_with_latency = smu10_get_clock_by_type_with_latency,
1616 .get_clock_by_type_with_voltage = smu10_get_clock_by_type_with_voltage,
1617 .set_watermarks_for_clocks_ranges = smu10_set_watermarks_for_clocks_ranges,
1618 .get_max_high_clocks = smu10_get_max_high_clocks,
1619 .read_sensor = smu10_read_sensor,
1620 .set_active_display_count = smu10_set_active_display_count,
1621 .set_min_deep_sleep_dcefclk = smu10_set_min_deep_sleep_dcefclk,
1622 .dynamic_state_management_enable = smu10_enable_dpm_tasks,
1623 .power_off_asic = smu10_power_off_asic,
1624 .asic_setup = smu10_setup_asic_task,
1625 .power_state_set = smu10_set_power_state_tasks,
1626 .dynamic_state_management_disable = smu10_disable_dpm_tasks,
1627 .powergate_mmhub = smu10_powergate_mmhub,
1628 .smus_notify_pwe = smu10_smus_notify_pwe,
1629 .display_clock_voltage_request = smu10_display_clock_voltage_request,
1630 .powergate_gfx = smu10_gfx_off_control,
1631 .powergate_sdma = smu10_powergate_sdma,
1632 .set_hard_min_dcefclk_by_freq = smu10_set_hard_min_dcefclk_by_freq,
1633 .set_hard_min_fclk_by_freq = smu10_set_hard_min_fclk_by_freq,
1634 .set_hard_min_gfxclk_by_freq = smu10_set_hard_min_gfxclk_by_freq,
1635 .set_soft_max_gfxclk_by_freq = smu10_set_soft_max_gfxclk_by_freq,
1636 .get_power_profile_mode = smu10_get_power_profile_mode,
1637 .set_power_profile_mode = smu10_set_power_profile_mode,
1638 .asic_reset = smu10_asic_reset,
1639 .set_fine_grain_clk_vol = smu10_set_fine_grain_clk_vol,
1640 .gfx_state_change = smu10_gfx_state_change,
1643 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
1645 hwmgr->hwmgr_func = &smu10_hwmgr_funcs;
1646 hwmgr->pptable_func = &pptable_funcs;