drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "pp_debug.h"
  24 #include <linux/types.h>
  25 #include <linux/kernel.h>
  26 #include <linux/slab.h>
  27 #include "atom-types.h"
  28 #include "atombios.h"
  29 #include "processpptables.h"
  30 #include "cgs_common.h"
  31 #include "smumgr.h"
  32 #include "hwmgr.h"
  33 #include "hardwaremanager.h"
  34 #include "rv_ppsmc.h"
  35 #include "smu10_hwmgr.h"
  36 #include "power_state.h"
  37 #include "soc15_common.h"
  38 #include "smu10.h"
  39 #include "asic_reg/pwr/pwr_10_0_offset.h"
  40 #include "asic_reg/pwr/pwr_10_0_sh_mask.h"
  41
  42 #define SMU10_MAX_DEEPSLEEP_DIVIDER_ID     5
  43 #define SMU10_MINIMUM_ENGINE_CLOCK         800   /* 8Mhz, the low boundary of engine clock allowed on this chip */
  44 #define SCLK_MIN_DIV_INTV_SHIFT         12
  45 #define SMU10_DISPCLK_BYPASS_THRESHOLD     10000 /* 100Mhz */
  46 #define SMC_RAM_END                     0x40000
  47
  48 static const unsigned long SMU10_Magic = (unsigned long) PHM_Rv_Magic;
  49
  50
  51 static int smu10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
  52                 struct pp_display_clock_request *clock_req)
  53 {
  54         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
  55         enum amd_pp_clock_type clk_type = clock_req->clock_type;
  56         uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
  57         PPSMC_Msg        msg;
  58
  59         switch (clk_type) {
  60         case amd_pp_dcf_clock:
  61                 if (clk_freq == smu10_data->dcf_actual_hard_min_freq)
  62                         return 0;
  63                 msg =  PPSMC_MSG_SetHardMinDcefclkByFreq;
  64                 smu10_data->dcf_actual_hard_min_freq = clk_freq;
  65                 break;
  66         case amd_pp_soc_clock:
  67                  msg = PPSMC_MSG_SetHardMinSocclkByFreq;
  68                 break;
  69         case amd_pp_f_clock:
  70                 if (clk_freq == smu10_data->f_actual_hard_min_freq)
  71                         return 0;
  72                 smu10_data->f_actual_hard_min_freq = clk_freq;
  73                 msg = PPSMC_MSG_SetHardMinFclkByFreq;
  74                 break;
  75         default:
  76                 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
  77                 return -EINVAL;
  78         }
  79         smum_send_msg_to_smc_with_parameter(hwmgr, msg, clk_freq, NULL);
  80
  81         return 0;
  82 }
  83
  84 static struct smu10_power_state *cast_smu10_ps(struct pp_hw_power_state *hw_ps)
  85 {
  86         if (SMU10_Magic != hw_ps->magic)
  87                 return NULL;
  88
  89         return (struct smu10_power_state *)hw_ps;
  90 }
  91
  92 static const struct smu10_power_state *cast_const_smu10_ps(
  93                                 const struct pp_hw_power_state *hw_ps)
  94 {
  95         if (SMU10_Magic != hw_ps->magic)
  96                 return NULL;
  97
  98         return (struct smu10_power_state *)hw_ps;
  99 }
 100
 101 static int smu10_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
 102 {
 103         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 104
 105         smu10_data->dce_slow_sclk_threshold = 30000;
 106         smu10_data->thermal_auto_throttling_treshold = 0;
 107         smu10_data->is_nb_dpm_enabled = 1;
 108         smu10_data->dpm_flags = 1;
 109         smu10_data->need_min_deep_sleep_dcefclk = true;
 110         smu10_data->num_active_display = 0;
 111         smu10_data->deep_sleep_dcefclk = 0;
 112
 113         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 114                                         PHM_PlatformCaps_SclkDeepSleep);
 115
 116         phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
 117                                 PHM_PlatformCaps_SclkThrottleLowNotification);
 118
 119         phm_cap_set(hwmgr->platform_descriptor.platformCaps,
 120                                 PHM_PlatformCaps_PowerPlaySupport);
 121         return 0;
 122 }
 123
 124 static int smu10_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
 125                         struct phm_clock_and_voltage_limits *table)
 126 {
 127         return 0;
 128 }
 129
 130 static int smu10_init_dynamic_state_adjustment_rule_settings(
 131                                                         struct pp_hwmgr *hwmgr)
 132 {
 133         int count = 8;
 134         struct phm_clock_voltage_dependency_table *table_clk_vlt;
 135
 136         table_clk_vlt = kzalloc(struct_size(table_clk_vlt, entries, count),
 137                                 GFP_KERNEL);
 138
 139         if (NULL == table_clk_vlt) {
 140                 pr_err("Can not allocate memory!\n");
 141                 return -ENOMEM;
 142         }
 143
 144         table_clk_vlt->count = count;
 145         table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
 146         table_clk_vlt->entries[0].v = 0;
 147         table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
 148         table_clk_vlt->entries[1].v = 1;
 149         table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
 150         table_clk_vlt->entries[2].v = 2;
 151         table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
 152         table_clk_vlt->entries[3].v = 3;
 153         table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
 154         table_clk_vlt->entries[4].v = 4;
 155         table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
 156         table_clk_vlt->entries[5].v = 5;
 157         table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
 158         table_clk_vlt->entries[6].v = 6;
 159         table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
 160         table_clk_vlt->entries[7].v = 7;
 161         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
 162
 163         return 0;
 164 }
 165
 166 static int smu10_get_system_info_data(struct pp_hwmgr *hwmgr)
 167 {
 168         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)hwmgr->backend;
 169
 170         smu10_data->sys_info.htc_hyst_lmt = 5;
 171         smu10_data->sys_info.htc_tmp_lmt = 203;
 172
 173         if (smu10_data->thermal_auto_throttling_treshold == 0)
 174                  smu10_data->thermal_auto_throttling_treshold = 203;
 175
 176         smu10_construct_max_power_limits_table (hwmgr,
 177                                     &hwmgr->dyn_state.max_clock_voltage_on_ac);
 178
 179         smu10_init_dynamic_state_adjustment_rule_settings(hwmgr);
 180
 181         return 0;
 182 }
 183
 184 static int smu10_construct_boot_state(struct pp_hwmgr *hwmgr)
 185 {
 186         return 0;
 187 }
 188
 189 static int smu10_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
 190 {
 191         struct PP_Clocks clocks = {0};
 192         struct pp_display_clock_request clock_req;
 193
 194         clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk;
 195         clock_req.clock_type = amd_pp_dcf_clock;
 196         clock_req.clock_freq_in_khz = clocks.dcefClock * 10;
 197
 198         PP_ASSERT_WITH_CODE(!smu10_display_clock_voltage_request(hwmgr, &clock_req),
 199                                 "Attempt to set DCF Clock Failed!", return -EINVAL);
 200
 201         return 0;
 202 }
 203
 204 static int smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
 205 {
 206         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 207
 208         if (clock && smu10_data->deep_sleep_dcefclk != clock) {
 209                 smu10_data->deep_sleep_dcefclk = clock;
 210                 smum_send_msg_to_smc_with_parameter(hwmgr,
 211                                         PPSMC_MSG_SetMinDeepSleepDcefclk,
 212                                         smu10_data->deep_sleep_dcefclk,
 213                                         NULL);
 214         }
 215         return 0;
 216 }
 217
 218 static int smu10_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
 219 {
 220         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 221
 222         if (clock && smu10_data->dcf_actual_hard_min_freq != clock) {
 223                 smu10_data->dcf_actual_hard_min_freq = clock;
 224                 smum_send_msg_to_smc_with_parameter(hwmgr,
 225                                         PPSMC_MSG_SetHardMinDcefclkByFreq,
 226                                         smu10_data->dcf_actual_hard_min_freq,
 227                                         NULL);
 228         }
 229         return 0;
 230 }
 231
 232 static int smu10_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
 233 {
 234         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 235
 236         if (clock && smu10_data->f_actual_hard_min_freq != clock) {
 237                 smu10_data->f_actual_hard_min_freq = clock;
 238                 smum_send_msg_to_smc_with_parameter(hwmgr,
 239                                         PPSMC_MSG_SetHardMinFclkByFreq,
 240                                         smu10_data->f_actual_hard_min_freq,
 241                                         NULL);
 242         }
 243         return 0;
 244 }
 245
 246 static int smu10_set_hard_min_gfxclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
 247 {
 248         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 249
 250         if (clock && smu10_data->gfx_actual_soft_min_freq != clock) {
 251                 smu10_data->gfx_actual_soft_min_freq = clock;
 252                 smum_send_msg_to_smc_with_parameter(hwmgr,
 253                                         PPSMC_MSG_SetHardMinGfxClk,
 254                                         clock,
 255                                         NULL);
 256         }
 257         return 0;
 258 }
 259
 260 static int smu10_set_soft_max_gfxclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
 261 {
 262         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 263
 264         if (clock && smu10_data->gfx_max_freq_limit != (clock * 100))  {
 265                 smu10_data->gfx_max_freq_limit = clock * 100;
 266                 smum_send_msg_to_smc_with_parameter(hwmgr,
 267                                         PPSMC_MSG_SetSoftMaxGfxClk,
 268                                         clock,
 269                                         NULL);
 270         }
 271         return 0;
 272 }
 273
 274 static int smu10_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)
 275 {
 276         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 277
 278         if (smu10_data->num_active_display != count) {
 279                 smu10_data->num_active_display = count;
 280                 smum_send_msg_to_smc_with_parameter(hwmgr,
 281                                 PPSMC_MSG_SetDisplayCount,
 282                                 smu10_data->num_active_display,
 283                                 NULL);
 284         }
 285
 286         return 0;
 287 }
 288
 289 static int smu10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
 290 {
 291         return smu10_set_clock_limit(hwmgr, input);
 292 }
 293
 294 static int smu10_init_power_gate_state(struct pp_hwmgr *hwmgr)
 295 {
 296         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 297         struct amdgpu_device *adev = hwmgr->adev;
 298
 299         smu10_data->vcn_power_gated = true;
 300         smu10_data->isp_tileA_power_gated = true;
 301         smu10_data->isp_tileB_power_gated = true;
 302
 303         if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)
 304                 return smum_send_msg_to_smc_with_parameter(hwmgr,
 305                                                            PPSMC_MSG_SetGfxCGPG,
 306                                                            true,
 307                                                            NULL);
 308         else
 309                 return 0;
 310 }
 311
 312
 313 static int smu10_setup_asic_task(struct pp_hwmgr *hwmgr)
 314 {
 315         return smu10_init_power_gate_state(hwmgr);
 316 }
 317
 318 static int smu10_reset_cc6_data(struct pp_hwmgr *hwmgr)
 319 {
 320         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 321
 322         smu10_data->separation_time = 0;
 323         smu10_data->cc6_disable = false;
 324         smu10_data->pstate_disable = false;
 325         smu10_data->cc6_setting_changed = false;
 326
 327         return 0;
 328 }
 329
 330 static int smu10_power_off_asic(struct pp_hwmgr *hwmgr)
 331 {
 332         return smu10_reset_cc6_data(hwmgr);
 333 }
 334
 335 static bool smu10_is_gfx_on(struct pp_hwmgr *hwmgr)
 336 {
 337         uint32_t reg;
 338         struct amdgpu_device *adev = hwmgr->adev;
 339
 340         reg = RREG32_SOC15(PWR, 0, mmPWR_MISC_CNTL_STATUS);
 341         if ((reg & PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK) ==
 342             (0x2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT))
 343                 return true;
 344
 345         return false;
 346 }
 347
 348 static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
 349 {
 350         struct amdgpu_device *adev = hwmgr->adev;
 351
 352         if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
 353                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableGfxOff, NULL);
 354
 355                 /* confirm gfx is back to "on" state */
 356                 while (!smu10_is_gfx_on(hwmgr))
 357                         msleep(1);
 358         }
 359
 360         return 0;
 361 }
 362
 363 static int smu10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
 364 {
 365         return 0;
 366 }
 367
 368 static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr)
 369 {
 370         struct amdgpu_device *adev = hwmgr->adev;
 371
 372         if (adev->pm.pp_feature & PP_GFXOFF_MASK)
 373                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableGfxOff, NULL);
 374
 375         return 0;
 376 }
 377
 378 static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
 379 {
 380         struct amdgpu_device *adev = hwmgr->adev;
 381         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 382         int ret = -EINVAL;
 383
 384         if (adev->in_suspend) {
 385                 pr_info("restore the fine grain parameters\n");
 386
 387                 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 388                                         PPSMC_MSG_SetHardMinGfxClk,
 389                                         smu10_data->gfx_actual_soft_min_freq,
 390                                         NULL);
 391                 if (ret)
 392                         return ret;
 393                 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
 394                                         PPSMC_MSG_SetSoftMaxGfxClk,
 395                                         smu10_data->gfx_actual_soft_max_freq,
 396                                         NULL);
 397                 if (ret)
 398                         return ret;
 399         }
 400
 401         return 0;
 402 }
 403
 404 static int smu10_gfx_off_control(struct pp_hwmgr *hwmgr, bool enable)
 405 {
 406         if (enable)
 407                 return smu10_enable_gfx_off(hwmgr);
 408         else
 409                 return smu10_disable_gfx_off(hwmgr);
 410 }
 411
 412 static int smu10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
 413                                 struct pp_power_state  *prequest_ps,
 414                         const struct pp_power_state *pcurrent_ps)
 415 {
 416         return 0;
 417 }
 418
 419 /* temporary hardcoded clock voltage breakdown tables */
 420 static const DpmClock_t VddDcfClk[]= {
 421         { 300, 2600},
 422         { 600, 3200},
 423         { 600, 3600},
 424 };
 425
 426 static const DpmClock_t VddSocClk[]= {
 427         { 478, 2600},
 428         { 722, 3200},
 429         { 722, 3600},
 430 };
 431
 432 static const DpmClock_t VddFClk[]= {
 433         { 400, 2600},
 434         {1200, 3200},
 435         {1200, 3600},
 436 };
 437
 438 static const DpmClock_t VddDispClk[]= {
 439         { 435, 2600},
 440         { 661, 3200},
 441         {1086, 3600},
 442 };
 443
 444 static const DpmClock_t VddDppClk[]= {
 445         { 435, 2600},
 446         { 661, 3200},
 447         { 661, 3600},
 448 };
 449
 450 static const DpmClock_t VddPhyClk[]= {
 451         { 540, 2600},
 452         { 810, 3200},
 453         { 810, 3600},
 454 };
 455
 456 static int smu10_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
 457                         struct smu10_voltage_dependency_table **pptable,
 458                         uint32_t num_entry, const DpmClock_t *pclk_dependency_table)
 459 {
 460         uint32_t i;
 461         struct smu10_voltage_dependency_table *ptable;
 462
 463         ptable = kzalloc(struct_size(ptable, entries, num_entry), GFP_KERNEL);
 464         if (NULL == ptable)
 465                 return -ENOMEM;
 466
 467         ptable->count = num_entry;
 468
 469         for (i = 0; i < ptable->count; i++) {
 470                 ptable->entries[i].clk         = pclk_dependency_table->Freq * 100;
 471                 ptable->entries[i].vol         = pclk_dependency_table->Vol;
 472                 pclk_dependency_table++;
 473         }
 474
 475         *pptable = ptable;
 476
 477         return 0;
 478 }
 479
 480
 481 static int smu10_populate_clock_table(struct pp_hwmgr *hwmgr)
 482 {
 483         uint32_t result;
 484
 485         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 486         DpmClocks_t  *table = &(smu10_data->clock_table);
 487         struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
 488
 489         result = smum_smc_table_manager(hwmgr, (uint8_t *)table, SMU10_CLOCKTABLE, true);
 490
 491         PP_ASSERT_WITH_CODE((0 == result),
 492                         "Attempt to copy clock table from smc failed",
 493                         return result);
 494
 495         if (0 == result && table->DcefClocks[0].Freq != 0) {
 496                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
 497                                                 NUM_DCEFCLK_DPM_LEVELS,
 498                                                 &smu10_data->clock_table.DcefClocks[0]);
 499                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
 500                                                 NUM_SOCCLK_DPM_LEVELS,
 501                                                 &smu10_data->clock_table.SocClocks[0]);
 502                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
 503                                                 NUM_FCLK_DPM_LEVELS,
 504                                                 &smu10_data->clock_table.FClocks[0]);
 505                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_mclk,
 506                                                 NUM_MEMCLK_DPM_LEVELS,
 507                                                 &smu10_data->clock_table.MemClocks[0]);
 508         } else {
 509                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
 510                                                 ARRAY_SIZE(VddDcfClk),
 511                                                 &VddDcfClk[0]);
 512                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
 513                                                 ARRAY_SIZE(VddSocClk),
 514                                                 &VddSocClk[0]);
 515                 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
 516                                                 ARRAY_SIZE(VddFClk),
 517                                                 &VddFClk[0]);
 518         }
 519         smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dispclk,
 520                                         ARRAY_SIZE(VddDispClk),
 521                                         &VddDispClk[0]);
 522         smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dppclk,
 523                                         ARRAY_SIZE(VddDppClk), &VddDppClk[0]);
 524         smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk,
 525                                         ARRAY_SIZE(VddPhyClk), &VddPhyClk[0]);
 526
 527         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &result);
 528         smu10_data->gfx_min_freq_limit = result / 10 * 1000;
 529
 530         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &result);
 531         smu10_data->gfx_max_freq_limit = result / 10 * 1000;
 532
 533         return 0;
 534 }
 535
 536 static int smu10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
 537 {
 538         int result = 0;
 539         struct smu10_hwmgr *data;
 540
 541         data = kzalloc(sizeof(struct smu10_hwmgr), GFP_KERNEL);
 542         if (data == NULL)
 543                 return -ENOMEM;
 544
 545         hwmgr->backend = data;
 546
 547         result = smu10_initialize_dpm_defaults(hwmgr);
 548         if (result != 0) {
 549                 pr_err("smu10_initialize_dpm_defaults failed\n");
 550                 return result;
 551         }
 552
 553         smu10_populate_clock_table(hwmgr);
 554
 555         result = smu10_get_system_info_data(hwmgr);
 556         if (result != 0) {
 557                 pr_err("smu10_get_system_info_data failed\n");
 558                 return result;
 559         }
 560
 561         smu10_construct_boot_state(hwmgr);
 562
 563         hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
 564                                                 SMU10_MAX_HARDWARE_POWERLEVELS;
 565
 566         hwmgr->platform_descriptor.hardwarePerformanceLevels =
 567                                                 SMU10_MAX_HARDWARE_POWERLEVELS;
 568
 569         hwmgr->platform_descriptor.vbiosInterruptId = 0;
 570
 571         hwmgr->platform_descriptor.clockStep.engineClock = 500;
 572
 573         hwmgr->platform_descriptor.clockStep.memoryClock = 500;
 574
 575         hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
 576
 577         hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK * 100;
 578         hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK * 100;
 579
 580         /* enable the pp_od_clk_voltage sysfs file */
 581         hwmgr->od_enabled = 1;
 582         /* disabled fine grain tuning function by default */
 583         data->fine_grain_enabled = 0;
 584         return result;
 585 }
 586
 587 static int smu10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
 588 {
 589         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
 590         struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
 591
 592         kfree(pinfo->vdd_dep_on_dcefclk);
 593         pinfo->vdd_dep_on_dcefclk = NULL;
 594         kfree(pinfo->vdd_dep_on_socclk);
 595         pinfo->vdd_dep_on_socclk = NULL;
 596         kfree(pinfo->vdd_dep_on_fclk);
 597         pinfo->vdd_dep_on_fclk = NULL;
 598         kfree(pinfo->vdd_dep_on_dispclk);
 599         pinfo->vdd_dep_on_dispclk = NULL;
 600         kfree(pinfo->vdd_dep_on_dppclk);
 601         pinfo->vdd_dep_on_dppclk = NULL;
 602         kfree(pinfo->vdd_dep_on_phyclk);
 603         pinfo->vdd_dep_on_phyclk = NULL;
 604
 605         kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
 606         hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
 607
 608         kfree(hwmgr->backend);
 609         hwmgr->backend = NULL;
 610
 611         return 0;
 612 }
 613
 614 static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
 615                                 enum amd_dpm_forced_level level)
 616 {
 617         struct smu10_hwmgr *data = hwmgr->backend;
 618         uint32_t min_sclk = hwmgr->display_config->min_core_set_clock;
 619         uint32_t min_mclk = hwmgr->display_config->min_mem_set_clock/100;
 620         uint32_t index_fclk = data->clock_vol_info.vdd_dep_on_fclk->count - 1;
 621         uint32_t index_socclk = data->clock_vol_info.vdd_dep_on_socclk->count - 1;
 622         uint32_t fine_grain_min_freq = 0, fine_grain_max_freq = 0;
 623
 624         if (hwmgr->smu_version < 0x1E3700) {
 625                 pr_info("smu firmware version too old, can not set dpm level\n");
 626                 return 0;
 627         }
 628
 629         if (min_sclk < data->gfx_min_freq_limit)
 630                 min_sclk = data->gfx_min_freq_limit;
 631
 632         min_sclk /= 100; /* transfer 10KHz to MHz */
 633         if (min_mclk < data->clock_table.FClocks[0].Freq)
 634                 min_mclk = data->clock_table.FClocks[0].Freq;
 635
 636         switch (level) {
 637         case AMD_DPM_FORCED_LEVEL_HIGH:
 638         case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
 639                 data->fine_grain_enabled = 0;
 640
 641                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
 642                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
 643
 644                 data->gfx_actual_soft_min_freq = fine_grain_min_freq;
 645                 data->gfx_actual_soft_max_freq = fine_grain_max_freq;
 646
 647                 smum_send_msg_to_smc_with_parameter(hwmgr,
 648                                                 PPSMC_MSG_SetHardMinGfxClk,
 649                                                 data->gfx_max_freq_limit/100,
 650                                                 NULL);
 651                 smum_send_msg_to_smc_with_parameter(hwmgr,
 652                                                 PPSMC_MSG_SetHardMinFclkByFreq,
 653                                                 SMU10_UMD_PSTATE_PEAK_FCLK,
 654                                                 NULL);
 655                 smum_send_msg_to_smc_with_parameter(hwmgr,
 656                                                 PPSMC_MSG_SetHardMinSocclkByFreq,
 657                                                 SMU10_UMD_PSTATE_PEAK_SOCCLK,
 658                                                 NULL);
 659                 smum_send_msg_to_smc_with_parameter(hwmgr,
 660                                                 PPSMC_MSG_SetHardMinVcn,
 661                                                 SMU10_UMD_PSTATE_VCE,
 662                                                 NULL);
 663
 664                 smum_send_msg_to_smc_with_parameter(hwmgr,
 665                                                 PPSMC_MSG_SetSoftMaxGfxClk,
 666                                                 data->gfx_max_freq_limit/100,
 667                                                 NULL);
 668                 smum_send_msg_to_smc_with_parameter(hwmgr,
 669                                                 PPSMC_MSG_SetSoftMaxFclkByFreq,
 670                                                 SMU10_UMD_PSTATE_PEAK_FCLK,
 671                                                 NULL);
 672                 smum_send_msg_to_smc_with_parameter(hwmgr,
 673                                                 PPSMC_MSG_SetSoftMaxSocclkByFreq,
 674                                                 SMU10_UMD_PSTATE_PEAK_SOCCLK,
 675                                                 NULL);
 676                 smum_send_msg_to_smc_with_parameter(hwmgr,
 677                                                 PPSMC_MSG_SetSoftMaxVcn,
 678                                                 SMU10_UMD_PSTATE_VCE,
 679                                                 NULL);
 680                 break;
 681         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
 682                 data->fine_grain_enabled = 0;
 683
 684                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
 685                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
 686
 687                 data->gfx_actual_soft_min_freq = fine_grain_min_freq;
 688                 data->gfx_actual_soft_max_freq = fine_grain_max_freq;
 689
 690                 smum_send_msg_to_smc_with_parameter(hwmgr,
 691                                                 PPSMC_MSG_SetHardMinGfxClk,
 692                                                 min_sclk,
 693                                                 NULL);
 694                 smum_send_msg_to_smc_with_parameter(hwmgr,
 695                                                 PPSMC_MSG_SetSoftMaxGfxClk,
 696                                                 min_sclk,
 697                                                 NULL);
 698                 break;
 699         case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
 700                 data->fine_grain_enabled = 0;
 701
 702                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
 703                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
 704
 705                 data->gfx_actual_soft_min_freq = fine_grain_min_freq;
 706                 data->gfx_actual_soft_max_freq = fine_grain_max_freq;
 707
 708                 smum_send_msg_to_smc_with_parameter(hwmgr,
 709                                                 PPSMC_MSG_SetHardMinFclkByFreq,
 710                                                 min_mclk,
 711                                                 NULL);
 712                 smum_send_msg_to_smc_with_parameter(hwmgr,
 713                                                 PPSMC_MSG_SetSoftMaxFclkByFreq,
 714                                                 min_mclk,
 715                                                 NULL);
 716                 break;
 717         case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
 718                 data->fine_grain_enabled = 0;
 719
 720                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
 721                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
 722
 723                 data->gfx_actual_soft_min_freq = fine_grain_min_freq;
 724                 data->gfx_actual_soft_max_freq = fine_grain_max_freq;
 725
 726                 smum_send_msg_to_smc_with_parameter(hwmgr,
 727                                                 PPSMC_MSG_SetHardMinGfxClk,
 728                                                 SMU10_UMD_PSTATE_GFXCLK,
 729                                                 NULL);
 730                 smum_send_msg_to_smc_with_parameter(hwmgr,
 731                                                 PPSMC_MSG_SetHardMinFclkByFreq,
 732                                                 SMU10_UMD_PSTATE_FCLK,
 733                                                 NULL);
 734                 smum_send_msg_to_smc_with_parameter(hwmgr,
 735                                                 PPSMC_MSG_SetHardMinSocclkByFreq,
 736                                                 SMU10_UMD_PSTATE_SOCCLK,
 737                                                 NULL);
 738                 smum_send_msg_to_smc_with_parameter(hwmgr,
 739                                                 PPSMC_MSG_SetHardMinVcn,
 740                                                 SMU10_UMD_PSTATE_PROFILE_VCE,
 741                                                 NULL);
 742
 743                 smum_send_msg_to_smc_with_parameter(hwmgr,
 744                                                 PPSMC_MSG_SetSoftMaxGfxClk,
 745                                                 SMU10_UMD_PSTATE_GFXCLK,
 746                                                 NULL);
 747                 smum_send_msg_to_smc_with_parameter(hwmgr,
 748                                                 PPSMC_MSG_SetSoftMaxFclkByFreq,
 749                                                 SMU10_UMD_PSTATE_FCLK,
 750                                                 NULL);
 751                 smum_send_msg_to_smc_with_parameter(hwmgr,
 752                                                 PPSMC_MSG_SetSoftMaxSocclkByFreq,
 753                                                 SMU10_UMD_PSTATE_SOCCLK,
 754                                                 NULL);
 755                 smum_send_msg_to_smc_with_parameter(hwmgr,
 756                                                 PPSMC_MSG_SetSoftMaxVcn,
 757                                                 SMU10_UMD_PSTATE_PROFILE_VCE,
 758                                                 NULL);
 759                 break;
 760         case AMD_DPM_FORCED_LEVEL_AUTO:
 761                 data->fine_grain_enabled = 0;
 762
 763                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
 764                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
 765
 766                 data->gfx_actual_soft_min_freq = fine_grain_min_freq;
 767                 data->gfx_actual_soft_max_freq = fine_grain_max_freq;
 768
 769                 smum_send_msg_to_smc_with_parameter(hwmgr,
 770                                                 PPSMC_MSG_SetHardMinGfxClk,
 771                                                 min_sclk,
 772                                                 NULL);
 773                 smum_send_msg_to_smc_with_parameter(hwmgr,
 774                                                 PPSMC_MSG_SetHardMinFclkByFreq,
 775                                                 hwmgr->display_config->num_display > 3 ?
 776                                                 data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk :
 777                                                 min_mclk,
 778                                                 NULL);
 779
 780                 smum_send_msg_to_smc_with_parameter(hwmgr,
 781                                                 PPSMC_MSG_SetHardMinSocclkByFreq,
 782                                                 data->clock_vol_info.vdd_dep_on_socclk->entries[0].clk,
 783                                                 NULL);
 784                 smum_send_msg_to_smc_with_parameter(hwmgr,
 785                                                 PPSMC_MSG_SetHardMinVcn,
 786                                                 SMU10_UMD_PSTATE_MIN_VCE,
 787                                                 NULL);
 788
 789                 smum_send_msg_to_smc_with_parameter(hwmgr,
 790                                                 PPSMC_MSG_SetSoftMaxGfxClk,
 791                                                 data->gfx_max_freq_limit/100,
 792                                                 NULL);
 793                 smum_send_msg_to_smc_with_parameter(hwmgr,
 794                                                 PPSMC_MSG_SetSoftMaxFclkByFreq,
 795                                                 data->clock_vol_info.vdd_dep_on_fclk->entries[index_fclk].clk,
 796                                                 NULL);
 797                 smum_send_msg_to_smc_with_parameter(hwmgr,
 798                                                 PPSMC_MSG_SetSoftMaxSocclkByFreq,
 799                                                 data->clock_vol_info.vdd_dep_on_socclk->entries[index_socclk].clk,
 800                                                 NULL);
 801                 smum_send_msg_to_smc_with_parameter(hwmgr,
 802                                                 PPSMC_MSG_SetSoftMaxVcn,
 803                                                 SMU10_UMD_PSTATE_VCE,
 804                                                 NULL);
 805                 break;
 806         case AMD_DPM_FORCED_LEVEL_LOW:
 807                 data->fine_grain_enabled = 0;
 808
 809                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &fine_grain_min_freq);
 810                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &fine_grain_max_freq);
 811
 812                 data->gfx_actual_soft_min_freq = fine_grain_min_freq;
 813                 data->gfx_actual_soft_max_freq = fine_grain_max_freq;
 814
 815                 smum_send_msg_to_smc_with_parameter(hwmgr,
 816                                                 PPSMC_MSG_SetHardMinGfxClk,
 817                                                 data->gfx_min_freq_limit/100,
 818                                                 NULL);
 819                 smum_send_msg_to_smc_with_parameter(hwmgr,
 820                                                 PPSMC_MSG_SetSoftMaxGfxClk,
 821                                                 data->gfx_min_freq_limit/100,
 822                                                 NULL);
 823                 smum_send_msg_to_smc_with_parameter(hwmgr,
 824                                                 PPSMC_MSG_SetHardMinFclkByFreq,
 825                                                 min_mclk,
 826                                                 NULL);
 827                 smum_send_msg_to_smc_with_parameter(hwmgr,
 828                                                 PPSMC_MSG_SetSoftMaxFclkByFreq,
 829                                                 min_mclk,
 830                                                 NULL);
 831                 break;
 832         case AMD_DPM_FORCED_LEVEL_MANUAL:
 833                 data->fine_grain_enabled = 1;
 834                 break;
 835         case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
 836         default:
 837                 break;
 838         }
 839         return 0;
 840 }
 841
 842 static uint32_t smu10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
 843 {
 844         struct smu10_hwmgr *data;
 845
 846         if (hwmgr == NULL)
 847                 return -EINVAL;
 848
 849         data = (struct smu10_hwmgr *)(hwmgr->backend);
 850
 851         if (low)
 852                 return data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
 853         else
 854                 return data->clock_vol_info.vdd_dep_on_fclk->entries[
 855                         data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;
 856 }
 857
 858 static uint32_t smu10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
 859 {
 860         struct smu10_hwmgr *data;
 861
 862         if (hwmgr == NULL)
 863                 return -EINVAL;
 864
 865         data = (struct smu10_hwmgr *)(hwmgr->backend);
 866
 867         if (low)
 868                 return data->gfx_min_freq_limit;
 869         else
 870                 return data->gfx_max_freq_limit;
 871 }
 872
 873 static int smu10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
 874                                         struct pp_hw_power_state *hw_ps)
 875 {
 876         return 0;
 877 }
 878
 879 static int smu10_dpm_get_pp_table_entry_callback(
 880                                                      struct pp_hwmgr *hwmgr,
 881                                            struct pp_hw_power_state *hw_ps,
 882                                                           unsigned int index,
 883                                                      const void *clock_info)
 884 {
 885         struct smu10_power_state *smu10_ps = cast_smu10_ps(hw_ps);
 886
 887         smu10_ps->levels[index].engine_clock = 0;
 888
 889         smu10_ps->levels[index].vddc_index = 0;
 890         smu10_ps->level = index + 1;
 891
 892         if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
 893                 smu10_ps->levels[index].ds_divider_index = 5;
 894                 smu10_ps->levels[index].ss_divider_index = 5;
 895         }
 896
 897         return 0;
 898 }
 899
 900 static int smu10_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
 901 {
 902         int result;
 903         unsigned long ret = 0;
 904
 905         result = pp_tables_get_num_of_entries(hwmgr, &ret);
 906
 907         return result ? 0 : ret;
 908 }
 909
 910 static int smu10_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
 911                     unsigned long entry, struct pp_power_state *ps)
 912 {
 913         int result;
 914         struct smu10_power_state *smu10_ps;
 915
 916         ps->hardware.magic = SMU10_Magic;
 917
 918         smu10_ps = cast_smu10_ps(&(ps->hardware));
 919
 920         result = pp_tables_get_entry(hwmgr, entry, ps,
 921                         smu10_dpm_get_pp_table_entry_callback);
 922
 923         smu10_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
 924         smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
 925
 926         return result;
 927 }
 928
 929 static int smu10_get_power_state_size(struct pp_hwmgr *hwmgr)
 930 {
 931         return sizeof(struct smu10_power_state);
 932 }
 933
 934 static int smu10_set_cpu_power_state(struct pp_hwmgr *hwmgr)
 935 {
 936         return 0;
 937 }
 938
 939
 940 static int smu10_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
 941                         bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
 942 {
 943         struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend);
 944
 945         if (separation_time != data->separation_time ||
 946                         cc6_disable != data->cc6_disable ||
 947                         pstate_disable != data->pstate_disable) {
 948                 data->separation_time = separation_time;
 949                 data->cc6_disable = cc6_disable;
 950                 data->pstate_disable = pstate_disable;
 951                 data->cc6_setting_changed = true;
 952         }
 953         return 0;
 954 }
 955
 956 static int smu10_get_dal_power_level(struct pp_hwmgr *hwmgr,
 957                 struct amd_pp_simple_clock_info *info)
 958 {
 959         return -EINVAL;
 960 }
 961
 962 static int smu10_force_clock_level(struct pp_hwmgr *hwmgr,
 963                 enum pp_clock_type type, uint32_t mask)
 964 {
 965         struct smu10_hwmgr *data = hwmgr->backend;
 966         struct smu10_voltage_dependency_table *mclk_table =
 967                                         data->clock_vol_info.vdd_dep_on_fclk;
 968         uint32_t low, high;
 969
 970         low = mask ? (ffs(mask) - 1) : 0;
 971         high = mask ? (fls(mask) - 1) : 0;
 972
 973         switch (type) {
 974         case PP_SCLK:
 975                 if (low > 2 || high > 2) {
 976                         pr_info("Currently sclk only support 3 levels on RV\n");
 977                         return -EINVAL;
 978                 }
 979
 980                 smum_send_msg_to_smc_with_parameter(hwmgr,
 981                                                 PPSMC_MSG_SetHardMinGfxClk,
 982                                                 low == 2 ? data->gfx_max_freq_limit/100 :
 983                                                 low == 1 ? SMU10_UMD_PSTATE_GFXCLK :
 984                                                 data->gfx_min_freq_limit/100,
 985                                                 NULL);
 986
 987                 smum_send_msg_to_smc_with_parameter(hwmgr,
 988                                                 PPSMC_MSG_SetSoftMaxGfxClk,
 989                                                 high == 0 ? data->gfx_min_freq_limit/100 :
 990                                                 high == 1 ? SMU10_UMD_PSTATE_GFXCLK :
 991                                                 data->gfx_max_freq_limit/100,
 992                                                 NULL);
 993                 break;
 994
 995         case PP_MCLK:
 996                 if (low > mclk_table->count - 1 || high > mclk_table->count - 1)
 997                         return -EINVAL;
 998
 999                 smum_send_msg_to_smc_with_parameter(hwmgr,
1000                                                 PPSMC_MSG_SetHardMinFclkByFreq,
1001                                                 mclk_table->entries[low].clk/100,
1002                                                 NULL);
1003
1004                 smum_send_msg_to_smc_with_parameter(hwmgr,
1005                                                 PPSMC_MSG_SetSoftMaxFclkByFreq,
1006                                                 mclk_table->entries[high].clk/100,
1007                                                 NULL);
1008                 break;
1009
1010         case PP_PCIE:
1011         default:
1012                 break;
1013         }
1014         return 0;
1015 }
1016
1017 static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr,
1018                 enum pp_clock_type type, char *buf)
1019 {
1020         struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend);
1021         struct smu10_voltage_dependency_table *mclk_table =
1022                         data->clock_vol_info.vdd_dep_on_fclk;
1023         uint32_t i, now, size = 0;
1024         uint32_t min_freq, max_freq = 0;
1025         uint32_t ret = 0;
1026
1027         switch (type) {
1028         case PP_SCLK:
1029                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &now);
1030
1031         /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
1032                 if (now == data->gfx_max_freq_limit/100)
1033                         i = 2;
1034                 else if (now == data->gfx_min_freq_limit/100)
1035                         i = 0;
1036                 else
1037                         i = 1;
1038
1039                 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n",
1040                                         data->gfx_min_freq_limit/100,
1041                                         i == 0 ? "*" : "");
1042                 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
1043                                         i == 1 ? now : SMU10_UMD_PSTATE_GFXCLK,
1044                                         i == 1 ? "*" : "");
1045                 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n",
1046                                         data->gfx_max_freq_limit/100,
1047                                         i == 2 ? "*" : "");
1048                 break;
1049         case PP_MCLK:
1050                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &now);
1051
1052                 for (i = 0; i < mclk_table->count; i++)
1053                         size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n",
1054                                         i,
1055                                         mclk_table->entries[i].clk / 100,
1056                                         ((mclk_table->entries[i].clk / 100)
1057                                          == now) ? "*" : "");
1058                 break;
1059         case OD_SCLK:
1060                 if (hwmgr->od_enabled) {
1061                         ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
1062                         if (ret)
1063                                 return ret;
1064                         ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
1065                         if (ret)
1066                                 return ret;
1067
1068                         size = sysfs_emit(buf, "%s:\n", "OD_SCLK");
1069                         size += sysfs_emit_at(buf, size, "0: %10uMhz\n",
1070                         (data->gfx_actual_soft_min_freq > 0) ? data->gfx_actual_soft_min_freq : min_freq);
1071                         size += sysfs_emit_at(buf, size, "1: %10uMhz\n",
1072                         (data->gfx_actual_soft_max_freq > 0) ? data->gfx_actual_soft_max_freq : max_freq);
1073                 }
1074                 break;
1075         case OD_RANGE:
1076                 if (hwmgr->od_enabled) {
1077                         ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
1078                         if (ret)
1079                                 return ret;
1080                         ret = smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
1081                         if (ret)
1082                                 return ret;
1083
1084                         size = sysfs_emit(buf, "%s:\n", "OD_RANGE");
1085                         size += sysfs_emit_at(buf, size, "SCLK: %7uMHz %10uMHz\n",
1086                                 min_freq, max_freq);
1087                 }
1088                 break;
1089         default:
1090                 break;
1091         }
1092
1093         return size;
1094 }
1095
1096 static int smu10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
1097                                 PHM_PerformanceLevelDesignation designation, uint32_t index,
1098                                 PHM_PerformanceLevel *level)
1099 {
1100         struct smu10_hwmgr *data;
1101
1102         if (level == NULL || hwmgr == NULL || state == NULL)
1103                 return -EINVAL;
1104
1105         data = (struct smu10_hwmgr *)(hwmgr->backend);
1106
1107         if (index == 0) {
1108                 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
1109                 level->coreClock = data->gfx_min_freq_limit;
1110         } else {
1111                 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[
1112                         data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;
1113                 level->coreClock = data->gfx_max_freq_limit;
1114         }
1115
1116         level->nonLocalMemoryFreq = 0;
1117         level->nonLocalMemoryWidth = 0;
1118
1119         return 0;
1120 }
1121
1122 static int smu10_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
1123         const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
1124 {
1125         const struct smu10_power_state *ps = cast_const_smu10_ps(state);
1126
1127         clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index));
1128         clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1].ss_divider_index));
1129
1130         return 0;
1131 }
1132
1133 #define MEM_FREQ_LOW_LATENCY        25000
1134 #define MEM_FREQ_HIGH_LATENCY       80000
1135 #define MEM_LATENCY_HIGH            245
1136 #define MEM_LATENCY_LOW             35
1137 #define MEM_LATENCY_ERR             0xFFFF
1138
1139
1140 static uint32_t smu10_get_mem_latency(struct pp_hwmgr *hwmgr,
1141                 uint32_t clock)
1142 {
1143         if (clock >= MEM_FREQ_LOW_LATENCY &&
1144                         clock < MEM_FREQ_HIGH_LATENCY)
1145                 return MEM_LATENCY_HIGH;
1146         else if (clock >= MEM_FREQ_HIGH_LATENCY)
1147                 return MEM_LATENCY_LOW;
1148         else
1149                 return MEM_LATENCY_ERR;
1150 }
1151
1152 static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
1153                 enum amd_pp_clock_type type,
1154                 struct pp_clock_levels_with_latency *clocks)
1155 {
1156         uint32_t i;
1157         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1158         struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
1159         struct smu10_voltage_dependency_table *pclk_vol_table;
1160         bool latency_required = false;
1161
1162         if (pinfo == NULL)
1163                 return -EINVAL;
1164
1165         switch (type) {
1166         case amd_pp_mem_clock:
1167                 pclk_vol_table = pinfo->vdd_dep_on_mclk;
1168                 latency_required = true;
1169                 break;
1170         case amd_pp_f_clock:
1171                 pclk_vol_table = pinfo->vdd_dep_on_fclk;
1172                 latency_required = true;
1173                 break;
1174         case amd_pp_dcf_clock:
1175                 pclk_vol_table = pinfo->vdd_dep_on_dcefclk;
1176                 break;
1177         case amd_pp_disp_clock:
1178                 pclk_vol_table = pinfo->vdd_dep_on_dispclk;
1179                 break;
1180         case amd_pp_phy_clock:
1181                 pclk_vol_table = pinfo->vdd_dep_on_phyclk;
1182                 break;
1183         case amd_pp_dpp_clock:
1184                 pclk_vol_table = pinfo->vdd_dep_on_dppclk;
1185                 break;
1186         default:
1187                 return -EINVAL;
1188         }
1189
1190         if (pclk_vol_table == NULL || pclk_vol_table->count == 0)
1191                 return -EINVAL;
1192
1193         clocks->num_levels = 0;
1194         for (i = 0; i < pclk_vol_table->count; i++) {
1195                 if (pclk_vol_table->entries[i].clk) {
1196                         clocks->data[clocks->num_levels].clocks_in_khz =
1197                                 pclk_vol_table->entries[i].clk * 10;
1198                         clocks->data[clocks->num_levels].latency_in_us = latency_required ?
1199                                 smu10_get_mem_latency(hwmgr,
1200                                                       pclk_vol_table->entries[i].clk) :
1201                                 0;
1202                         clocks->num_levels++;
1203                 }
1204         }
1205
1206         return 0;
1207 }
1208
1209 static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
1210                 enum amd_pp_clock_type type,
1211                 struct pp_clock_levels_with_voltage *clocks)
1212 {
1213         uint32_t i;
1214         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1215         struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
1216         struct smu10_voltage_dependency_table *pclk_vol_table = NULL;
1217
1218         if (pinfo == NULL)
1219                 return -EINVAL;
1220
1221         switch (type) {
1222         case amd_pp_mem_clock:
1223                 pclk_vol_table = pinfo->vdd_dep_on_mclk;
1224                 break;
1225         case amd_pp_f_clock:
1226                 pclk_vol_table = pinfo->vdd_dep_on_fclk;
1227                 break;
1228         case amd_pp_dcf_clock:
1229                 pclk_vol_table = pinfo->vdd_dep_on_dcefclk;
1230                 break;
1231         case amd_pp_soc_clock:
1232                 pclk_vol_table = pinfo->vdd_dep_on_socclk;
1233                 break;
1234         case amd_pp_disp_clock:
1235                 pclk_vol_table = pinfo->vdd_dep_on_dispclk;
1236                 break;
1237         case amd_pp_phy_clock:
1238                 pclk_vol_table = pinfo->vdd_dep_on_phyclk;
1239                 break;
1240         default:
1241                 return -EINVAL;
1242         }
1243
1244         if (pclk_vol_table == NULL || pclk_vol_table->count == 0)
1245                 return -EINVAL;
1246
1247         clocks->num_levels = 0;
1248         for (i = 0; i < pclk_vol_table->count; i++) {
1249                 if (pclk_vol_table->entries[i].clk) {
1250                         clocks->data[clocks->num_levels].clocks_in_khz = pclk_vol_table->entries[i].clk  * 10;
1251                         clocks->data[clocks->num_levels].voltage_in_mv = pclk_vol_table->entries[i].vol;
1252                         clocks->num_levels++;
1253                 }
1254         }
1255
1256         return 0;
1257 }
1258
1259
1260
1261 static int smu10_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
1262 {
1263         clocks->engine_max_clock = 80000; /* driver can't get engine clock, temp hard code to 800MHz */
1264         return 0;
1265 }
1266
1267 static int smu10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
1268 {
1269         struct amdgpu_device *adev = hwmgr->adev;
1270         uint32_t reg_value = RREG32_SOC15(THM, 0, mmTHM_TCON_CUR_TMP);
1271         int cur_temp =
1272                 (reg_value & THM_TCON_CUR_TMP__CUR_TEMP_MASK) >> THM_TCON_CUR_TMP__CUR_TEMP__SHIFT;
1273
1274         if (cur_temp & THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK)
1275                 cur_temp = ((cur_temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1276         else
1277                 cur_temp = (cur_temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
1278
1279         return cur_temp;
1280 }
1281
1282 static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
1283                           void *value, int *size)
1284 {
1285         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1286         struct amdgpu_device *adev = hwmgr->adev;
1287         uint32_t sclk, mclk, activity_percent;
1288         bool has_gfx_busy;
1289         int ret = 0;
1290
1291         /* GetGfxBusy support was added on RV SMU FW 30.85.00 and PCO 4.30.59 */
1292         if ((adev->apu_flags & AMD_APU_IS_PICASSO) &&
1293             (hwmgr->smu_version >= 0x41e3b))
1294                 has_gfx_busy = true;
1295         else if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
1296                  (hwmgr->smu_version >= 0x1e5500))
1297                 has_gfx_busy = true;
1298         else
1299                 has_gfx_busy = false;
1300
1301         switch (idx) {
1302         case AMDGPU_PP_SENSOR_GFX_SCLK:
1303                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency, &sclk);
1304                         /* in units of 10KHZ */
1305                 *((uint32_t *)value) = sclk * 100;
1306                 *size = 4;
1307                 break;
1308         case AMDGPU_PP_SENSOR_GFX_MCLK:
1309                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency, &mclk);
1310                         /* in units of 10KHZ */
1311                 *((uint32_t *)value) = mclk * 100;
1312                 *size = 4;
1313                 break;
1314         case AMDGPU_PP_SENSOR_GPU_TEMP:
1315                 *((uint32_t *)value) = smu10_thermal_get_temperature(hwmgr);
1316                 break;
1317         case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
1318                 *(uint32_t *)value =  smu10_data->vcn_power_gated ? 0 : 1;
1319                 *size = 4;
1320                 break;
1321         case AMDGPU_PP_SENSOR_GPU_LOAD:
1322                 if (!has_gfx_busy)
1323                         ret = -EOPNOTSUPP;
1324                 else {
1325                         ret = smum_send_msg_to_smc(hwmgr,
1326                                                    PPSMC_MSG_GetGfxBusy,
1327                                                    &activity_percent);
1328                         if (!ret)
1329                                 *((uint32_t *)value) = min(activity_percent, (u32)100);
1330                         else
1331                                 ret = -EIO;
1332                 }
1333                 break;
1334         default:
1335                 ret = -EOPNOTSUPP;
1336                 break;
1337         }
1338
1339         return ret;
1340 }
1341
1342 static int smu10_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
1343                 void *clock_ranges)
1344 {
1345         struct smu10_hwmgr *data = hwmgr->backend;
1346         struct dm_pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges = clock_ranges;
1347         Watermarks_t *table = &(data->water_marks_table);
1348         struct amdgpu_device *adev = hwmgr->adev;
1349         int i;
1350
1351         smu_set_watermarks_for_clocks_ranges(table,wm_with_clock_ranges);
1352
1353         if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
1354                 for (i = 0; i < NUM_WM_RANGES; i++)
1355                         table->WatermarkRow[WM_DCFCLK][i].WmType = (uint8_t)0;
1356
1357                 for (i = 0; i < NUM_WM_RANGES; i++)
1358                         table->WatermarkRow[WM_SOCCLK][i].WmType = (uint8_t)0;
1359         }
1360
1361         smum_smc_table_manager(hwmgr, (uint8_t *)table, (uint16_t)SMU10_WMTABLE, false);
1362         data->water_marks_exist = true;
1363         return 0;
1364 }
1365
1366 static int smu10_smus_notify_pwe(struct pp_hwmgr *hwmgr)
1367 {
1368
1369         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_SetRccPfcPmeRestoreRegister, NULL);
1370 }
1371
1372 static int smu10_powergate_mmhub(struct pp_hwmgr *hwmgr)
1373 {
1374         return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub, NULL);
1375 }
1376
1377 static int smu10_powergate_sdma(struct pp_hwmgr *hwmgr, bool gate)
1378 {
1379         if (gate)
1380                 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerDownSdma, NULL);
1381         else
1382                 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerUpSdma, NULL);
1383 }
1384
1385 static void smu10_powergate_vcn(struct pp_hwmgr *hwmgr, bool bgate)
1386 {
1387         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1388
1389         if (bgate) {
1390                 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
1391                                                 AMD_IP_BLOCK_TYPE_VCN,
1392                                                 AMD_PG_STATE_GATE);
1393                 smum_send_msg_to_smc_with_parameter(hwmgr,
1394                                         PPSMC_MSG_PowerDownVcn, 0, NULL);
1395                 smu10_data->vcn_power_gated = true;
1396         } else {
1397                 smum_send_msg_to_smc_with_parameter(hwmgr,
1398                                                 PPSMC_MSG_PowerUpVcn, 0, NULL);
1399                 amdgpu_device_ip_set_powergating_state(hwmgr->adev,
1400                                                 AMD_IP_BLOCK_TYPE_VCN,
1401                                                 AMD_PG_STATE_UNGATE);
1402                 smu10_data->vcn_power_gated = false;
1403         }
1404 }
1405
1406 static int conv_power_profile_to_pplib_workload(int power_profile)
1407 {
1408         int pplib_workload = 0;
1409
1410         switch (power_profile) {
1411         case PP_SMC_POWER_PROFILE_FULLSCREEN3D:
1412                 pplib_workload = WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT;
1413                 break;
1414         case PP_SMC_POWER_PROFILE_VIDEO:
1415                 pplib_workload = WORKLOAD_PPLIB_VIDEO_BIT;
1416                 break;
1417         case PP_SMC_POWER_PROFILE_VR:
1418                 pplib_workload = WORKLOAD_PPLIB_VR_BIT;
1419                 break;
1420         case PP_SMC_POWER_PROFILE_COMPUTE:
1421                 pplib_workload = WORKLOAD_PPLIB_COMPUTE_BIT;
1422                 break;
1423         case PP_SMC_POWER_PROFILE_CUSTOM:
1424                 pplib_workload = WORKLOAD_PPLIB_CUSTOM_BIT;
1425                 break;
1426         }
1427
1428         return pplib_workload;
1429 }
1430
1431 static int smu10_get_power_profile_mode(struct pp_hwmgr *hwmgr, char *buf)
1432 {
1433         uint32_t i, size = 0;
1434         static const uint8_t
1435                 profile_mode_setting[6][4] = {{70, 60, 0, 0,},
1436                                                 {70, 60, 1, 3,},
1437                                                 {90, 60, 0, 0,},
1438                                                 {70, 60, 0, 0,},
1439                                                 {70, 90, 0, 0,},
1440                                                 {30, 60, 0, 6,},
1441                                                 };
1442         static const char *profile_name[6] = {
1443                                         "BOOTUP_DEFAULT",
1444                                         "3D_FULL_SCREEN",
1445                                         "POWER_SAVING",
1446                                         "VIDEO",
1447                                         "VR",
1448                                         "COMPUTE"};
1449         static const char *title[6] = {"NUM",
1450                         "MODE_NAME",
1451                         "BUSY_SET_POINT",
1452                         "FPS",
1453                         "USE_RLC_BUSY",
1454                         "MIN_ACTIVE_LEVEL"};
1455
1456         if (!buf)
1457                 return -EINVAL;
1458
1459         size += sysfs_emit_at(buf, size, "%s %16s %s %s %s %s\n",title[0],
1460                         title[1], title[2], title[3], title[4], title[5]);
1461
1462         for (i = 0; i <= PP_SMC_POWER_PROFILE_COMPUTE; i++)
1463                 size += sysfs_emit_at(buf, size, "%3d %14s%s: %14d %3d %10d %14d\n",
1464                         i, profile_name[i], (i == hwmgr->power_profile_mode) ? "*" : " ",
1465                         profile_mode_setting[i][0], profile_mode_setting[i][1],
1466                         profile_mode_setting[i][2], profile_mode_setting[i][3]);
1467
1468         return size;
1469 }
1470
1471 static bool smu10_is_raven1_refresh(struct pp_hwmgr *hwmgr)
1472 {
1473         struct amdgpu_device *adev = hwmgr->adev;
1474         if ((adev->apu_flags & AMD_APU_IS_RAVEN) &&
1475             (hwmgr->smu_version >= 0x41e2b))
1476                 return true;
1477         else
1478                 return false;
1479 }
1480
1481 static int smu10_set_power_profile_mode(struct pp_hwmgr *hwmgr, long *input, uint32_t size)
1482 {
1483         int workload_type = 0;
1484         int result = 0;
1485
1486         if (input[size] > PP_SMC_POWER_PROFILE_COMPUTE) {
1487                 pr_err("Invalid power profile mode %ld\n", input[size]);
1488                 return -EINVAL;
1489         }
1490         if (hwmgr->power_profile_mode == input[size])
1491                 return 0;
1492
1493         /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1494         workload_type =
1495                 conv_power_profile_to_pplib_workload(input[size]);
1496         if (workload_type &&
1497             smu10_is_raven1_refresh(hwmgr) &&
1498             !hwmgr->gfxoff_state_changed_by_workload) {
1499                 smu10_gfx_off_control(hwmgr, false);
1500                 hwmgr->gfxoff_state_changed_by_workload = true;
1501         }
1502         result = smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_ActiveProcessNotify,
1503                                                 1 << workload_type,
1504                                                 NULL);
1505         if (!result)
1506                 hwmgr->power_profile_mode = input[size];
1507         if (workload_type && hwmgr->gfxoff_state_changed_by_workload) {
1508                 smu10_gfx_off_control(hwmgr, true);
1509                 hwmgr->gfxoff_state_changed_by_workload = false;
1510         }
1511
1512         return 0;
1513 }
1514
1515 static int smu10_asic_reset(struct pp_hwmgr *hwmgr, enum SMU_ASIC_RESET_MODE mode)
1516 {
1517         return smum_send_msg_to_smc_with_parameter(hwmgr,
1518                                                    PPSMC_MSG_DeviceDriverReset,
1519                                                    mode,
1520                                                    NULL);
1521 }
1522
1523 static int smu10_set_fine_grain_clk_vol(struct pp_hwmgr *hwmgr,
1524                                         enum PP_OD_DPM_TABLE_COMMAND type,
1525                                         long *input, uint32_t size)
1526 {
1527         uint32_t min_freq, max_freq = 0;
1528         struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
1529         int ret = 0;
1530
1531         if (!hwmgr->od_enabled) {
1532                 pr_err("Fine grain not support\n");
1533                 return -EINVAL;
1534         }
1535
1536         if (!smu10_data->fine_grain_enabled) {
1537                 pr_err("pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n");
1538                 return -EINVAL;
1539         }
1540
1541         if (type == PP_OD_EDIT_SCLK_VDDC_TABLE) {
1542                 if (size != 2) {
1543                         pr_err("Input parameter number not correct\n");
1544                         return -EINVAL;
1545                 }
1546
1547                 if (input[0] == 0) {
1548                         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
1549                         if (input[1] < min_freq) {
1550                                 pr_err("Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
1551                                         input[1], min_freq);
1552                                 return -EINVAL;
1553                         }
1554                         smu10_data->gfx_actual_soft_min_freq = input[1];
1555                 } else if (input[0] == 1) {
1556                         smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
1557                         if (input[1] > max_freq) {
1558                                 pr_err("Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
1559                                         input[1], max_freq);
1560                                 return -EINVAL;
1561                         }
1562                         smu10_data->gfx_actual_soft_max_freq = input[1];
1563                 } else {
1564                         return -EINVAL;
1565                 }
1566         } else if (type == PP_OD_RESTORE_DEFAULT_TABLE) {
1567                 if (size != 0) {
1568                         pr_err("Input parameter number not correct\n");
1569                         return -EINVAL;
1570                 }
1571                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency, &min_freq);
1572                 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency, &max_freq);
1573
1574                 smu10_data->gfx_actual_soft_min_freq = min_freq;
1575                 smu10_data->gfx_actual_soft_max_freq = max_freq;
1576         } else if (type == PP_OD_COMMIT_DPM_TABLE) {
1577                 if (size != 0) {
1578                         pr_err("Input parameter number not correct\n");
1579                         return -EINVAL;
1580                 }
1581
1582                 if (smu10_data->gfx_actual_soft_min_freq > smu10_data->gfx_actual_soft_max_freq) {
1583                         pr_err("The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
1584                                         smu10_data->gfx_actual_soft_min_freq, smu10_data->gfx_actual_soft_max_freq);
1585                         return -EINVAL;
1586                 }
1587
1588                 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1589                                         PPSMC_MSG_SetHardMinGfxClk,
1590                                         smu10_data->gfx_actual_soft_min_freq,
1591                                         NULL);
1592                 if (ret)
1593                         return ret;
1594
1595                 ret = smum_send_msg_to_smc_with_parameter(hwmgr,
1596                                         PPSMC_MSG_SetSoftMaxGfxClk,
1597                                         smu10_data->gfx_actual_soft_max_freq,
1598                                         NULL);
1599                 if (ret)
1600                         return ret;
1601         } else {
1602                 return -EINVAL;
1603         }
1604
1605         return 0;
1606 }
1607
1608 static int smu10_gfx_state_change(struct pp_hwmgr *hwmgr, uint32_t state)
1609 {
1610         smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GpuChangeState, state, NULL);
1611
1612         return 0;
1613 }
1614
1615 static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
1616         .backend_init = smu10_hwmgr_backend_init,
1617         .backend_fini = smu10_hwmgr_backend_fini,
1618         .apply_state_adjust_rules = smu10_apply_state_adjust_rules,
1619         .force_dpm_level = smu10_dpm_force_dpm_level,
1620         .get_power_state_size = smu10_get_power_state_size,
1621         .powerdown_uvd = NULL,
1622         .powergate_uvd = smu10_powergate_vcn,
1623         .powergate_vce = NULL,
1624         .get_mclk = smu10_dpm_get_mclk,
1625         .get_sclk = smu10_dpm_get_sclk,
1626         .patch_boot_state = smu10_dpm_patch_boot_state,
1627         .get_pp_table_entry = smu10_dpm_get_pp_table_entry,
1628         .get_num_of_pp_table_entries = smu10_dpm_get_num_of_pp_table_entries,
1629         .set_cpu_power_state = smu10_set_cpu_power_state,
1630         .store_cc6_data = smu10_store_cc6_data,
1631         .force_clock_level = smu10_force_clock_level,
1632         .print_clock_levels = smu10_print_clock_levels,
1633         .get_dal_power_level = smu10_get_dal_power_level,
1634         .get_performance_level = smu10_get_performance_level,
1635         .get_current_shallow_sleep_clocks = smu10_get_current_shallow_sleep_clocks,
1636         .get_clock_by_type_with_latency = smu10_get_clock_by_type_with_latency,
1637         .get_clock_by_type_with_voltage = smu10_get_clock_by_type_with_voltage,
1638         .set_watermarks_for_clocks_ranges = smu10_set_watermarks_for_clocks_ranges,
1639         .get_max_high_clocks = smu10_get_max_high_clocks,
1640         .read_sensor = smu10_read_sensor,
1641         .set_active_display_count = smu10_set_active_display_count,
1642         .set_min_deep_sleep_dcefclk = smu10_set_min_deep_sleep_dcefclk,
1643         .dynamic_state_management_enable = smu10_enable_dpm_tasks,
1644         .power_off_asic = smu10_power_off_asic,
1645         .asic_setup = smu10_setup_asic_task,
1646         .power_state_set = smu10_set_power_state_tasks,
1647         .dynamic_state_management_disable = smu10_disable_dpm_tasks,
1648         .powergate_mmhub = smu10_powergate_mmhub,
1649         .smus_notify_pwe = smu10_smus_notify_pwe,
1650         .display_clock_voltage_request = smu10_display_clock_voltage_request,
1651         .powergate_gfx = smu10_gfx_off_control,
1652         .powergate_sdma = smu10_powergate_sdma,
1653         .set_hard_min_dcefclk_by_freq = smu10_set_hard_min_dcefclk_by_freq,
1654         .set_hard_min_fclk_by_freq = smu10_set_hard_min_fclk_by_freq,
1655         .set_hard_min_gfxclk_by_freq = smu10_set_hard_min_gfxclk_by_freq,
1656         .set_soft_max_gfxclk_by_freq = smu10_set_soft_max_gfxclk_by_freq,
1657         .get_power_profile_mode = smu10_get_power_profile_mode,
1658         .set_power_profile_mode = smu10_set_power_profile_mode,
1659         .asic_reset = smu10_asic_reset,
1660         .set_fine_grain_clk_vol = smu10_set_fine_grain_clk_vol,
1661         .gfx_state_change = smu10_gfx_state_change,
1662 };
1663
1664 int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
1665 {
1666         hwmgr->hwmgr_func = &smu10_hwmgr_funcs;
1667         hwmgr->pptable_func = &pptable_funcs;
1668         return 0;
1669 }