2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
23 #ifndef __SMU_V11_0_H__
24 #define __SMU_V11_0_H__
26 #include "amdgpu_smu.h"
28 #define SMU11_DRIVER_IF_VERSION_INV 0xFFFFFFFF
29 #define SMU11_DRIVER_IF_VERSION_ARCT 0x17
30 #define SMU11_DRIVER_IF_VERSION_NV10 0x36
31 #define SMU11_DRIVER_IF_VERSION_NV12 0x36
32 #define SMU11_DRIVER_IF_VERSION_NV14 0x36
33 #define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x3B
34 #define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0xC
35 #define SMU11_DRIVER_IF_VERSION_VANGOGH 0x02
36 #define SMU11_DRIVER_IF_VERSION_Dimgrey_Cavefish 0xF
39 #define MP0_Public 0x03800000
40 #define MP0_SRAM 0x03900000
41 #define MP1_Public 0x03b00000
42 #define MP1_SRAM 0x03c00004
45 #define smnMP1_FIRMWARE_FLAGS 0x3010024
46 #define smnMP0_FW_INTF 0x30101c0
47 #define smnMP1_PUB_CTRL 0x3010b14
49 #define TEMP_RANGE_MIN (0)
50 #define TEMP_RANGE_MAX (80 * 1000)
52 #define SMU11_TOOL_SIZE 0x19000
54 #define MAX_DPM_LEVELS 16
55 #define MAX_PCIE_CONF 2
57 #define CTF_OFFSET_EDGE 5
58 #define CTF_OFFSET_HOTSPOT 5
59 #define CTF_OFFSET_MEM 5
62 struct smu_temperature_range __maybe_unused smu11_thermal_policy[] =
64 {-273150, 99000, 99000, -273150, 99000, 99000, -273150, 99000, 99000},
65 { 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000, 120000},
68 struct smu_11_0_max_sustainable_clocks {
69 uint32_t display_clock;
77 struct smu_11_0_dpm_clk_level {
82 struct smu_11_0_dpm_table {
83 uint32_t min; /* MHz */
84 uint32_t max; /* MHz */
87 struct smu_11_0_dpm_clk_level dpm_levels[MAX_DPM_LEVELS];
90 struct smu_11_0_pcie_table {
91 uint8_t pcie_gen[MAX_PCIE_CONF];
92 uint8_t pcie_lane[MAX_PCIE_CONF];
95 struct smu_11_0_dpm_tables {
96 struct smu_11_0_dpm_table soc_table;
97 struct smu_11_0_dpm_table gfx_table;
98 struct smu_11_0_dpm_table uclk_table;
99 struct smu_11_0_dpm_table eclk_table;
100 struct smu_11_0_dpm_table vclk_table;
101 struct smu_11_0_dpm_table vclk1_table;
102 struct smu_11_0_dpm_table dclk_table;
103 struct smu_11_0_dpm_table dclk1_table;
104 struct smu_11_0_dpm_table dcef_table;
105 struct smu_11_0_dpm_table pixel_table;
106 struct smu_11_0_dpm_table display_table;
107 struct smu_11_0_dpm_table phy_table;
108 struct smu_11_0_dpm_table fclk_table;
109 struct smu_11_0_pcie_table pcie_table;
112 struct smu_11_0_dpm_context {
113 struct smu_11_0_dpm_tables dpm_tables;
114 uint32_t workload_policy_mask;
115 uint32_t dcef_min_ds_clk;
118 enum smu_11_0_power_state {
119 SMU_11_0_POWER_STATE__D0 = 0,
120 SMU_11_0_POWER_STATE__D1,
121 SMU_11_0_POWER_STATE__D3, /* Sleep*/
122 SMU_11_0_POWER_STATE__D4, /* Hibernate*/
123 SMU_11_0_POWER_STATE__D5, /* Power off*/
126 struct smu_11_0_power_context {
127 uint32_t power_source;
128 uint8_t in_power_limit_boost_mode;
129 enum smu_11_0_power_state power_state;
132 enum smu_v11_0_baco_seq {
140 #if defined(SWSMU_CODE_LAYER_L2) || defined(SWSMU_CODE_LAYER_L3)
142 int smu_v11_0_init_microcode(struct smu_context *smu);
144 void smu_v11_0_fini_microcode(struct smu_context *smu);
146 int smu_v11_0_load_microcode(struct smu_context *smu);
148 int smu_v11_0_init_smc_tables(struct smu_context *smu);
150 int smu_v11_0_fini_smc_tables(struct smu_context *smu);
152 int smu_v11_0_init_power(struct smu_context *smu);
154 int smu_v11_0_fini_power(struct smu_context *smu);
156 int smu_v11_0_check_fw_status(struct smu_context *smu);
158 int smu_v11_0_setup_pptable(struct smu_context *smu);
160 int smu_v11_0_get_vbios_bootup_values(struct smu_context *smu);
162 int smu_v11_0_check_fw_version(struct smu_context *smu);
164 int smu_v11_0_set_driver_table_location(struct smu_context *smu);
166 int smu_v11_0_set_tool_table_location(struct smu_context *smu);
168 int smu_v11_0_notify_memory_pool_location(struct smu_context *smu);
170 int smu_v11_0_system_features_control(struct smu_context *smu,
173 int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count);
175 int smu_v11_0_set_allowed_mask(struct smu_context *smu);
177 int smu_v11_0_notify_display_change(struct smu_context *smu);
179 int smu_v11_0_get_current_power_limit(struct smu_context *smu,
180 uint32_t *power_limit);
182 int smu_v11_0_set_power_limit(struct smu_context *smu, uint32_t n);
184 int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu);
186 int smu_v11_0_enable_thermal_alert(struct smu_context *smu);
188 int smu_v11_0_disable_thermal_alert(struct smu_context *smu);
190 int smu_v11_0_get_gfx_vdd(struct smu_context *smu, uint32_t *value);
192 int smu_v11_0_set_min_deep_sleep_dcefclk(struct smu_context *smu, uint32_t clk);
195 smu_v11_0_display_clock_voltage_request(struct smu_context *smu,
196 struct pp_display_clock_request
200 smu_v11_0_get_fan_control_mode(struct smu_context *smu);
203 smu_v11_0_set_fan_control_mode(struct smu_context *smu,
206 int smu_v11_0_set_fan_speed_rpm(struct smu_context *smu,
209 int smu_v11_0_get_fan_speed_rpm(struct smu_context *smu,
212 int smu_v11_0_set_xgmi_pstate(struct smu_context *smu,
215 int smu_v11_0_gfx_off_control(struct smu_context *smu, bool enable);
217 int smu_v11_0_register_irq_handler(struct smu_context *smu);
219 int smu_v11_0_set_azalia_d3_pme(struct smu_context *smu);
221 int smu_v11_0_get_max_sustainable_clocks_by_dc(struct smu_context *smu,
222 struct pp_smu_nv_clock_table *max_clocks);
224 bool smu_v11_0_baco_is_support(struct smu_context *smu);
226 enum smu_baco_state smu_v11_0_baco_get_state(struct smu_context *smu);
228 int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state);
230 int smu_v11_0_baco_enter(struct smu_context *smu);
231 int smu_v11_0_baco_exit(struct smu_context *smu);
233 int smu_v11_0_mode1_reset(struct smu_context *smu);
235 int smu_v11_0_get_dpm_ultimate_freq(struct smu_context *smu, enum smu_clk_type clk_type,
236 uint32_t *min, uint32_t *max);
238 int smu_v11_0_set_soft_freq_limited_range(struct smu_context *smu, enum smu_clk_type clk_type,
239 uint32_t min, uint32_t max);
241 int smu_v11_0_set_hard_freq_limited_range(struct smu_context *smu,
242 enum smu_clk_type clk_type,
246 int smu_v11_0_set_performance_level(struct smu_context *smu,
247 enum amd_dpm_forced_level level);
249 int smu_v11_0_set_power_source(struct smu_context *smu,
250 enum smu_power_src_type power_src);
252 int smu_v11_0_get_dpm_freq_by_index(struct smu_context *smu,
253 enum smu_clk_type clk_type,
257 int smu_v11_0_get_dpm_level_count(struct smu_context *smu,
258 enum smu_clk_type clk_type,
261 int smu_v11_0_set_single_dpm_table(struct smu_context *smu,
262 enum smu_clk_type clk_type,
263 struct smu_11_0_dpm_table *single_dpm_table);
265 int smu_v11_0_get_dpm_level_range(struct smu_context *smu,
266 enum smu_clk_type clk_type,
268 uint32_t *max_value);
270 int smu_v11_0_get_current_pcie_link_width_level(struct smu_context *smu);
272 int smu_v11_0_get_current_pcie_link_width(struct smu_context *smu);
274 int smu_v11_0_get_current_pcie_link_speed_level(struct smu_context *smu);
276 int smu_v11_0_get_current_pcie_link_speed(struct smu_context *smu);
278 void smu_v11_0_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics);
280 void smu_v11_0_init_gpu_metrics_v2_0(struct gpu_metrics_v2_0 *gpu_metrics);
282 int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
285 int smu_v11_0_deep_sleep_control(struct smu_context *smu,
288 void smu_v11_0_interrupt_work(struct smu_context *smu);