2 * Copyright 2017 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
24 #ifndef __KGD_PP_INTERFACE_H__
25 #define __KGD_PP_INTERFACE_H__
27 extern const struct amdgpu_ip_block_version pp_smu_ip_block;
29 struct amd_vce_state {
41 enum amd_dpm_forced_level {
42 AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
43 AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
44 AMD_DPM_FORCED_LEVEL_LOW = 0x4,
45 AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
46 AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
47 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
48 AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
49 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
50 AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
53 enum amd_pm_state_type {
54 /* not used for dpm */
55 POWER_STATE_TYPE_DEFAULT,
56 POWER_STATE_TYPE_POWERSAVE,
57 /* user selectable states */
58 POWER_STATE_TYPE_BATTERY,
59 POWER_STATE_TYPE_BALANCED,
60 POWER_STATE_TYPE_PERFORMANCE,
62 POWER_STATE_TYPE_INTERNAL_UVD,
63 POWER_STATE_TYPE_INTERNAL_UVD_SD,
64 POWER_STATE_TYPE_INTERNAL_UVD_HD,
65 POWER_STATE_TYPE_INTERNAL_UVD_HD2,
66 POWER_STATE_TYPE_INTERNAL_UVD_MVC,
67 POWER_STATE_TYPE_INTERNAL_BOOT,
68 POWER_STATE_TYPE_INTERNAL_THERMAL,
69 POWER_STATE_TYPE_INTERNAL_ACPI,
70 POWER_STATE_TYPE_INTERNAL_ULV,
71 POWER_STATE_TYPE_INTERNAL_3DPERF,
74 #define AMD_MAX_VCE_LEVELS 6
77 AMD_VCE_LEVEL_AC_ALL = 0, /* AC, All cases */
78 AMD_VCE_LEVEL_DC_EE = 1, /* DC, entropy encoding */
79 AMD_VCE_LEVEL_DC_LL_LOW = 2, /* DC, low latency queue, res <= 720 */
80 AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
81 AMD_VCE_LEVEL_DC_GP_LOW = 4, /* DC, general purpose queue, res <= 720 */
82 AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
85 enum amd_fan_ctrl_mode {
86 AMD_FAN_CTRL_NONE = 0,
87 AMD_FAN_CTRL_MANUAL = 1,
88 AMD_FAN_CTRL_AUTO = 2,
108 enum amd_pp_sensors {
109 AMDGPU_PP_SENSOR_GFX_SCLK = 0,
110 AMDGPU_PP_SENSOR_CPU_CLK,
111 AMDGPU_PP_SENSOR_VDDNB,
112 AMDGPU_PP_SENSOR_VDDGFX,
113 AMDGPU_PP_SENSOR_UVD_VCLK,
114 AMDGPU_PP_SENSOR_UVD_DCLK,
115 AMDGPU_PP_SENSOR_VCE_ECCLK,
116 AMDGPU_PP_SENSOR_GPU_LOAD,
117 AMDGPU_PP_SENSOR_MEM_LOAD,
118 AMDGPU_PP_SENSOR_GFX_MCLK,
119 AMDGPU_PP_SENSOR_GPU_TEMP,
120 AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP,
121 AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
122 AMDGPU_PP_SENSOR_MEM_TEMP,
123 AMDGPU_PP_SENSOR_VCE_POWER,
124 AMDGPU_PP_SENSOR_UVD_POWER,
125 AMDGPU_PP_SENSOR_GPU_POWER,
126 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
127 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
128 AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
129 AMDGPU_PP_SENSOR_MIN_FAN_RPM,
130 AMDGPU_PP_SENSOR_MAX_FAN_RPM,
131 AMDGPU_PP_SENSOR_VCN_POWER_STATE,
135 AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
136 AMD_PP_TASK_ENABLE_USER_STATE,
137 AMD_PP_TASK_READJUST_POWER_STATE,
138 AMD_PP_TASK_COMPLETE_INIT,
142 enum PP_SMC_POWER_PROFILE {
143 PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0,
144 PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1,
145 PP_SMC_POWER_PROFILE_POWERSAVING = 0x2,
146 PP_SMC_POWER_PROFILE_VIDEO = 0x3,
147 PP_SMC_POWER_PROFILE_VR = 0x4,
148 PP_SMC_POWER_PROFILE_COMPUTE = 0x5,
149 PP_SMC_POWER_PROFILE_CUSTOM = 0x6,
150 PP_SMC_POWER_PROFILE_COUNT,
154 PP_GROUP_UNKNOWN = 0,
160 enum PP_OD_DPM_TABLE_COMMAND {
161 PP_OD_EDIT_SCLK_VDDC_TABLE,
162 PP_OD_EDIT_MCLK_VDDC_TABLE,
163 PP_OD_EDIT_CCLK_VDDC_TABLE,
164 PP_OD_EDIT_VDDC_CURVE,
165 PP_OD_RESTORE_DEFAULT_TABLE,
166 PP_OD_COMMIT_DPM_TABLE,
167 PP_OD_EDIT_VDDGFX_OFFSET
170 struct pp_states_info {
184 PP_MP1_STATE_SHUTDOWN,
190 DF_CSTATE_DISALLOW = 0,
194 #define PP_GROUP_MASK 0xF0000000
195 #define PP_GROUP_SHIFT 28
197 #define PP_BLOCK_MASK 0x0FFFFF00
198 #define PP_BLOCK_SHIFT 8
200 #define PP_BLOCK_GFX_CG 0x01
201 #define PP_BLOCK_GFX_MG 0x02
202 #define PP_BLOCK_GFX_3D 0x04
203 #define PP_BLOCK_GFX_RLC 0x08
204 #define PP_BLOCK_GFX_CP 0x10
205 #define PP_BLOCK_SYS_BIF 0x01
206 #define PP_BLOCK_SYS_MC 0x02
207 #define PP_BLOCK_SYS_ROM 0x04
208 #define PP_BLOCK_SYS_DRM 0x08
209 #define PP_BLOCK_SYS_HDP 0x10
210 #define PP_BLOCK_SYS_SDMA 0x20
212 #define PP_STATE_MASK 0x0000000F
213 #define PP_STATE_SHIFT 0
214 #define PP_STATE_SUPPORT_MASK 0x000000F0
215 #define PP_STATE_SUPPORT_SHIFT 0
217 #define PP_STATE_CG 0x01
218 #define PP_STATE_LS 0x02
219 #define PP_STATE_DS 0x04
220 #define PP_STATE_SD 0x08
221 #define PP_STATE_SUPPORT_CG 0x10
222 #define PP_STATE_SUPPORT_LS 0x20
223 #define PP_STATE_SUPPORT_DS 0x40
224 #define PP_STATE_SUPPORT_SD 0x80
226 #define PP_CG_MSG_ID(group, block, support, state) \
227 ((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
228 (support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
230 #define XGMI_MODE_PSTATE_D3 0
231 #define XGMI_MODE_PSTATE_D0 1
234 enum amd_pp_clock_type;
235 struct amd_pp_simple_clock_info;
236 struct amd_pp_display_configuration;
237 struct amd_pp_clock_info;
238 struct pp_display_clock_request;
239 struct pp_clock_levels_with_voltage;
240 struct pp_clock_levels_with_latency;
241 struct amd_pp_clocks;
243 struct amd_pm_funcs {
244 /* export for dpm on ci and si */
245 int (*pre_set_power_state)(void *handle);
246 int (*set_power_state)(void *handle);
247 void (*post_set_power_state)(void *handle);
248 void (*display_configuration_changed)(void *handle);
249 void (*print_power_state)(void *handle, void *ps);
250 bool (*vblank_too_short)(void *handle);
251 void (*enable_bapm)(void *handle, bool enable);
252 int (*check_state_equal)(void *handle,
256 /* export for sysfs */
257 void (*set_fan_control_mode)(void *handle, u32 mode);
258 u32 (*get_fan_control_mode)(void *handle);
259 int (*set_fan_speed_percent)(void *handle, u32 speed);
260 int (*get_fan_speed_percent)(void *handle, u32 *speed);
261 int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
262 int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
263 int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
264 int (*get_sclk_od)(void *handle);
265 int (*set_sclk_od)(void *handle, uint32_t value);
266 int (*get_mclk_od)(void *handle);
267 int (*set_mclk_od)(void *handle, uint32_t value);
268 int (*read_sensor)(void *handle, int idx, void *value, int *size);
269 enum amd_dpm_forced_level (*get_performance_level)(void *handle);
270 enum amd_pm_state_type (*get_current_power_state)(void *handle);
271 int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
272 int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
273 int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
274 int (*get_pp_table)(void *handle, char **table);
275 int (*set_pp_table)(void *handle, const char *buf, size_t size);
276 void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
277 int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
278 /* export to amdgpu */
279 struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
280 int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
281 enum amd_pm_state_type *user_state);
282 int (*load_firmware)(void *handle);
283 int (*wait_for_fw_loading_complete)(void *handle);
284 int (*set_powergating_by_smu)(void *handle,
285 uint32_t block_type, bool gate);
286 int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
287 int (*set_power_limit)(void *handle, uint32_t n);
288 int (*get_power_limit)(void *handle, uint32_t *limit, bool default_limit);
289 int (*get_power_profile_mode)(void *handle, char *buf);
290 int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
291 int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size);
292 int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
293 int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
294 int (*smu_i2c_bus_access)(void *handle, bool acquire);
295 int (*gfx_state_change_set)(void *handle, uint32_t state);
297 u32 (*get_sclk)(void *handle, bool low);
298 u32 (*get_mclk)(void *handle, bool low);
299 int (*display_configuration_change)(void *handle,
300 const struct amd_pp_display_configuration *input);
301 int (*get_display_power_level)(void *handle,
302 struct amd_pp_simple_clock_info *output);
303 int (*get_current_clocks)(void *handle,
304 struct amd_pp_clock_info *clocks);
305 int (*get_clock_by_type)(void *handle,
306 enum amd_pp_clock_type type,
307 struct amd_pp_clocks *clocks);
308 int (*get_clock_by_type_with_latency)(void *handle,
309 enum amd_pp_clock_type type,
310 struct pp_clock_levels_with_latency *clocks);
311 int (*get_clock_by_type_with_voltage)(void *handle,
312 enum amd_pp_clock_type type,
313 struct pp_clock_levels_with_voltage *clocks);
314 int (*set_watermarks_for_clocks_ranges)(void *handle,
316 int (*display_clock_voltage_request)(void *handle,
317 struct pp_display_clock_request *clock);
318 int (*get_display_mode_validation_clocks)(void *handle,
319 struct amd_pp_simple_clock_info *clocks);
320 int (*notify_smu_enable_pwe)(void *handle);
321 int (*enable_mgpu_fan_boost)(void *handle);
322 int (*set_active_display_count)(void *handle, uint32_t count);
323 int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
324 int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
325 int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
326 int (*get_asic_baco_capability)(void *handle, bool *cap);
327 int (*get_asic_baco_state)(void *handle, int *state);
328 int (*set_asic_baco_state)(void *handle, int state);
329 int (*get_ppfeature_status)(void *handle, char *buf);
330 int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
331 int (*asic_reset_mode_2)(void *handle);
332 int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
333 int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
334 ssize_t (*get_gpu_metrics)(void *handle, void **table);
337 struct metrics_table_header {
338 uint16_t structure_size;
339 uint8_t format_revision;
340 uint8_t content_revision;
344 * gpu_metrics_v1_0 is not recommended as it's not naturally aligned.
345 * Use gpu_metrics_v1_1 or later instead.
347 struct gpu_metrics_v1_0 {
348 struct metrics_table_header common_header;
350 /* Driver attached timestamp (in ns) */
351 uint64_t system_clock_counter;
354 uint16_t temperature_edge;
355 uint16_t temperature_hotspot;
356 uint16_t temperature_mem;
357 uint16_t temperature_vrgfx;
358 uint16_t temperature_vrsoc;
359 uint16_t temperature_vrmem;
362 uint16_t average_gfx_activity;
363 uint16_t average_umc_activity; // memory controller
364 uint16_t average_mm_activity; // UVD or VCN
367 uint16_t average_socket_power;
368 uint32_t energy_accumulator;
371 uint16_t average_gfxclk_frequency;
372 uint16_t average_socclk_frequency;
373 uint16_t average_uclk_frequency;
374 uint16_t average_vclk0_frequency;
375 uint16_t average_dclk0_frequency;
376 uint16_t average_vclk1_frequency;
377 uint16_t average_dclk1_frequency;
380 uint16_t current_gfxclk;
381 uint16_t current_socclk;
382 uint16_t current_uclk;
383 uint16_t current_vclk0;
384 uint16_t current_dclk0;
385 uint16_t current_vclk1;
386 uint16_t current_dclk1;
388 /* Throttle status */
389 uint32_t throttle_status;
392 uint16_t current_fan_speed;
394 /* Link width/speed */
395 uint8_t pcie_link_width;
396 uint8_t pcie_link_speed; // in 0.1 GT/s
399 struct gpu_metrics_v1_1 {
400 struct metrics_table_header common_header;
403 uint16_t temperature_edge;
404 uint16_t temperature_hotspot;
405 uint16_t temperature_mem;
406 uint16_t temperature_vrgfx;
407 uint16_t temperature_vrsoc;
408 uint16_t temperature_vrmem;
411 uint16_t average_gfx_activity;
412 uint16_t average_umc_activity; // memory controller
413 uint16_t average_mm_activity; // UVD or VCN
416 uint16_t average_socket_power;
417 uint64_t energy_accumulator;
419 /* Driver attached timestamp (in ns) */
420 uint64_t system_clock_counter;
423 uint16_t average_gfxclk_frequency;
424 uint16_t average_socclk_frequency;
425 uint16_t average_uclk_frequency;
426 uint16_t average_vclk0_frequency;
427 uint16_t average_dclk0_frequency;
428 uint16_t average_vclk1_frequency;
429 uint16_t average_dclk1_frequency;
432 uint16_t current_gfxclk;
433 uint16_t current_socclk;
434 uint16_t current_uclk;
435 uint16_t current_vclk0;
436 uint16_t current_dclk0;
437 uint16_t current_vclk1;
438 uint16_t current_dclk1;
440 /* Throttle status */
441 uint32_t throttle_status;
444 uint16_t current_fan_speed;
446 /* Link width/speed */
447 uint16_t pcie_link_width;
448 uint16_t pcie_link_speed; // in 0.1 GT/s
454 * gpu_metrics_v2_0 is not recommended as it's not naturally aligned.
455 * Use gpu_metrics_v2_1 or later instead.
457 struct gpu_metrics_v2_0 {
458 struct metrics_table_header common_header;
460 /* Driver attached timestamp (in ns) */
461 uint64_t system_clock_counter;
464 uint16_t temperature_gfx; // gfx temperature on APUs
465 uint16_t temperature_soc; // soc temperature on APUs
466 uint16_t temperature_core[8]; // CPU core temperature on APUs
467 uint16_t temperature_l3[2];
470 uint16_t average_gfx_activity;
471 uint16_t average_mm_activity; // UVD or VCN
474 uint16_t average_socket_power; // dGPU + APU power on A + A platform
475 uint16_t average_cpu_power;
476 uint16_t average_soc_power;
477 uint16_t average_gfx_power;
478 uint16_t average_core_power[8]; // CPU core power on APUs
481 uint16_t average_gfxclk_frequency;
482 uint16_t average_socclk_frequency;
483 uint16_t average_uclk_frequency;
484 uint16_t average_fclk_frequency;
485 uint16_t average_vclk_frequency;
486 uint16_t average_dclk_frequency;
489 uint16_t current_gfxclk;
490 uint16_t current_socclk;
491 uint16_t current_uclk;
492 uint16_t current_fclk;
493 uint16_t current_vclk;
494 uint16_t current_dclk;
495 uint16_t current_coreclk[8]; // CPU core clocks
496 uint16_t current_l3clk[2];
498 /* Throttle status */
499 uint32_t throttle_status;
507 struct gpu_metrics_v2_1 {
508 struct metrics_table_header common_header;
511 uint16_t temperature_gfx; // gfx temperature on APUs
512 uint16_t temperature_soc; // soc temperature on APUs
513 uint16_t temperature_core[8]; // CPU core temperature on APUs
514 uint16_t temperature_l3[2];
517 uint16_t average_gfx_activity;
518 uint16_t average_mm_activity; // UVD or VCN
520 /* Driver attached timestamp (in ns) */
521 uint64_t system_clock_counter;
524 uint16_t average_socket_power; // dGPU + APU power on A + A platform
525 uint16_t average_cpu_power;
526 uint16_t average_soc_power;
527 uint16_t average_gfx_power;
528 uint16_t average_core_power[8]; // CPU core power on APUs
531 uint16_t average_gfxclk_frequency;
532 uint16_t average_socclk_frequency;
533 uint16_t average_uclk_frequency;
534 uint16_t average_fclk_frequency;
535 uint16_t average_vclk_frequency;
536 uint16_t average_dclk_frequency;
539 uint16_t current_gfxclk;
540 uint16_t current_socclk;
541 uint16_t current_uclk;
542 uint16_t current_fclk;
543 uint16_t current_vclk;
544 uint16_t current_dclk;
545 uint16_t current_coreclk[8]; // CPU core clocks
546 uint16_t current_l3clk[2];
548 /* Throttle status */
549 uint32_t throttle_status;