2 * Copyright 2014 Advanced Micro Devices, Inc.
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11 * The above copyright notice and this permission notice shall be included in
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24 * This file defines the private interface between the
25 * AMD kernel graphics drivers and the AMD KFD.
28 #ifndef KGD_KFD_INTERFACE_H_INCLUDED
29 #define KGD_KFD_INTERFACE_H_INCLUDED
31 #include <linux/types.h>
32 #include <linux/bitmap.h>
33 #include <linux/dma-fence.h>
37 #define KGD_MAX_QUEUES 128
44 enum kfd_preempt_type {
45 KFD_PREEMPT_TYPE_WAVEFRONT_DRAIN = 0,
46 KFD_PREEMPT_TYPE_WAVEFRONT_RESET,
47 KFD_PREEMPT_TYPE_WAVEFRONT_SAVE
50 struct kfd_vm_fault_info {
62 uint32_t num_shader_engines;
63 uint32_t num_shader_arrays_per_engine;
64 uint32_t num_cu_per_sh;
65 uint32_t cu_active_number;
68 uint32_t max_waves_per_simd;
69 uint32_t wave_front_size;
70 uint32_t max_scratch_slots_per_cu;
72 uint32_t cu_bitmap[4][4];
75 /* For getting GPU local memory information from KGD */
76 struct kfd_local_mem_info {
77 uint64_t local_mem_size_private;
78 uint64_t local_mem_size_public;
83 enum kgd_memory_pool {
84 KGD_POOL_SYSTEM_CACHEABLE = 1,
85 KGD_POOL_SYSTEM_WRITECOMBINE = 2,
86 KGD_POOL_FRAMEBUFFER = 3,
90 * enum kfd_sched_policy
92 * @KFD_SCHED_POLICY_HWS: H/W scheduling policy known as command processor (cp)
93 * scheduling. In this scheduling mode we're using the firmware code to
94 * schedule the user mode queues and kernel queues such as HIQ and DIQ.
95 * the HIQ queue is used as a special queue that dispatches the configuration
96 * to the cp and the user mode queues list that are currently running.
97 * the DIQ queue is a debugging queue that dispatches debugging commands to the
99 * in this scheduling mode user mode queues over subscription feature is
102 * @KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION: The same as above but the over
103 * subscription feature disabled.
105 * @KFD_SCHED_POLICY_NO_HWS: no H/W scheduling policy is a mode which directly
106 * set the command processor registers and sets the queues "manually". This
107 * mode is used *ONLY* for debugging proposes.
110 enum kfd_sched_policy {
111 KFD_SCHED_POLICY_HWS = 0,
112 KFD_SCHED_POLICY_HWS_NO_OVERSUBSCRIPTION,
113 KFD_SCHED_POLICY_NO_HWS
116 struct kgd2kfd_shared_resources {
117 /* Bit n == 1 means VMID n is available for KFD. */
118 unsigned int compute_vmid_bitmap;
120 /* number of pipes per mec */
121 uint32_t num_pipe_per_mec;
123 /* number of queues per pipe */
124 uint32_t num_queue_per_pipe;
126 /* Bit n == 1 means Queue n is available for KFD */
127 DECLARE_BITMAP(cp_queue_bitmap, KGD_MAX_QUEUES);
129 /* SDMA doorbell assignments (SOC15 and later chips only). Only
130 * specific doorbells are routed to each SDMA engine. Others
131 * are routed to IH and VCN. They are not usable by the CP.
133 uint32_t *sdma_doorbell_idx;
135 /* From SOC15 onward, the doorbell index range not usable for CP
138 uint32_t non_cp_doorbells_start;
139 uint32_t non_cp_doorbells_end;
141 /* Base address of doorbell aperture. */
142 phys_addr_t doorbell_physical_address;
144 /* Size in bytes of doorbell aperture. */
145 size_t doorbell_aperture_size;
147 /* Number of bytes at start of aperture reserved for KGD. */
148 size_t doorbell_start_offset;
150 /* GPUVM address space size in bytes */
153 /* Minor device number of the render node */
154 int drm_render_minor;
159 uint32_t *tile_config_ptr;
160 uint32_t *macro_tile_config_ptr;
161 uint32_t num_tile_configs;
162 uint32_t num_macro_tile_configs;
164 uint32_t gb_addr_config;
169 #define KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT 4096
172 * struct kfd2kgd_calls
174 * @program_sh_mem_settings: A function that should initiate the memory
175 * properties such as main aperture memory type (cache / non cached) and
176 * secondary aperture base address, size and memory type.
177 * This function is used only for no cp scheduling mode.
179 * @set_pasid_vmid_mapping: Exposes pasid/vmid pair to the H/W for no cp
180 * scheduling mode. Only used for no cp scheduling mode.
182 * @hqd_load: Loads the mqd structure to a H/W hqd slot. used only for no cp
185 * @hqd_sdma_load: Loads the SDMA mqd structure to a H/W SDMA hqd slot.
186 * used only for no HWS mode.
188 * @hqd_dump: Dumps CPC HQD registers to an array of address-value pairs.
189 * Array is allocated with kmalloc, needs to be freed with kfree by caller.
191 * @hqd_sdma_dump: Dumps SDMA HQD registers to an array of address-value pairs.
192 * Array is allocated with kmalloc, needs to be freed with kfree by caller.
194 * @hqd_is_occupies: Checks if a hqd slot is occupied.
196 * @hqd_destroy: Destructs and preempts the queue assigned to that hqd slot.
198 * @hqd_sdma_is_occupied: Checks if an SDMA hqd slot is occupied.
200 * @hqd_sdma_destroy: Destructs and preempts the SDMA queue assigned to that
203 * @set_scratch_backing_va: Sets VA for scratch backing memory of a VMID.
204 * Only used for no cp scheduling mode
206 * @set_vm_context_page_table_base: Program page table base for a VMID
208 * @invalidate_tlbs: Invalidate TLBs for a specific PASID
210 * @invalidate_tlbs_vmid: Invalidate TLBs for a specific VMID
212 * @read_vmid_from_vmfault_reg: On Hawaii the VMID is not set in the
213 * IH ring entry. This function allows the KFD ISR to get the VMID
214 * from the fault status register as early as possible.
216 * @get_cu_occupancy: Function pointer that returns to caller the number
217 * of wave fronts that are in flight for all of the queues of a process
218 * as identified by its pasid. It is important to note that the value
219 * returned by this function is a snapshot of current moment and cannot
220 * guarantee any minimum for the number of waves in-flight. This function
221 * is defined for devices that belong to GFX9 and later GFX families. Care
222 * must be taken in calling this function as it is not defined for devices
223 * that belong to GFX8 and below GFX families.
225 * This structure contains function pointers to services that the kgd driver
226 * provides to amdkfd driver.
229 struct kfd2kgd_calls {
230 /* Register access functions */
231 void (*program_sh_mem_settings)(struct kgd_dev *kgd, uint32_t vmid,
232 uint32_t sh_mem_config, uint32_t sh_mem_ape1_base,
233 uint32_t sh_mem_ape1_limit, uint32_t sh_mem_bases);
235 int (*set_pasid_vmid_mapping)(struct kgd_dev *kgd, u32 pasid,
238 int (*init_interrupts)(struct kgd_dev *kgd, uint32_t pipe_id);
240 int (*hqd_load)(struct kgd_dev *kgd, void *mqd, uint32_t pipe_id,
241 uint32_t queue_id, uint32_t __user *wptr,
242 uint32_t wptr_shift, uint32_t wptr_mask,
243 struct mm_struct *mm);
245 int (*hiq_mqd_load)(struct kgd_dev *kgd, void *mqd,
246 uint32_t pipe_id, uint32_t queue_id,
247 uint32_t doorbell_off);
249 int (*hqd_sdma_load)(struct kgd_dev *kgd, void *mqd,
250 uint32_t __user *wptr, struct mm_struct *mm);
252 int (*hqd_dump)(struct kgd_dev *kgd,
253 uint32_t pipe_id, uint32_t queue_id,
254 uint32_t (**dump)[2], uint32_t *n_regs);
256 int (*hqd_sdma_dump)(struct kgd_dev *kgd,
257 uint32_t engine_id, uint32_t queue_id,
258 uint32_t (**dump)[2], uint32_t *n_regs);
260 bool (*hqd_is_occupied)(struct kgd_dev *kgd, uint64_t queue_address,
261 uint32_t pipe_id, uint32_t queue_id);
263 int (*hqd_destroy)(struct kgd_dev *kgd, void *mqd, uint32_t reset_type,
264 unsigned int timeout, uint32_t pipe_id,
267 bool (*hqd_sdma_is_occupied)(struct kgd_dev *kgd, void *mqd);
269 int (*hqd_sdma_destroy)(struct kgd_dev *kgd, void *mqd,
270 unsigned int timeout);
272 int (*address_watch_disable)(struct kgd_dev *kgd);
273 int (*address_watch_execute)(struct kgd_dev *kgd,
274 unsigned int watch_point_id,
278 int (*wave_control_execute)(struct kgd_dev *kgd,
279 uint32_t gfx_index_val,
281 uint32_t (*address_watch_get_offset)(struct kgd_dev *kgd,
282 unsigned int watch_point_id,
283 unsigned int reg_offset);
284 bool (*get_atc_vmid_pasid_mapping_info)(
289 /* No longer needed from GFXv9 onward. The scratch base address is
290 * passed to the shader by the CP. It's the user mode driver's
293 void (*set_scratch_backing_va)(struct kgd_dev *kgd,
294 uint64_t va, uint32_t vmid);
296 void (*set_vm_context_page_table_base)(struct kgd_dev *kgd,
297 uint32_t vmid, uint64_t page_table_base);
298 uint32_t (*read_vmid_from_vmfault_reg)(struct kgd_dev *kgd);
300 void (*get_cu_occupancy)(struct kgd_dev *kgd, int pasid, int *wave_cnt,
301 int *max_waves_per_cu);
302 void (*program_trap_handler_settings)(struct kgd_dev *kgd,
303 uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr);
306 #endif /* KGD_KFD_INTERFACE_H_INCLUDED */