drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h

   1 /*
   2  * Copyright (C) 2018  Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included
  12  * in all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  */
  21
  22 #ifndef _thm_11_0_2_OFFSET_HEADER
  23 #define _thm_11_0_2_OFFSET_HEADER
  24
  25
  26 #define mmCG_MULT_THERMAL_STATUS                                                                       0x005f
  27 #define mmCG_MULT_THERMAL_STATUS_BASE_IDX                                                              0
  28
  29 #define mmCG_FDO_CTRL0                                                                                 0x0067
  30 #define mmCG_FDO_CTRL0_BASE_IDX                                                                        0
  31
  32 #define mmCG_FDO_CTRL1                                                                                 0x0068
  33 #define mmCG_FDO_CTRL1_BASE_IDX                                                                        0
  34
  35 #define mmCG_FDO_CTRL2                                                                                 0x0069
  36 #define mmCG_FDO_CTRL2_BASE_IDX                                                                        0
  37
  38 #define mmCG_TACH_CTRL                                                                                 0x006a
  39 #define mmCG_TACH_CTRL_BASE_IDX                                                                        0
  40
  41 #define mmCG_TACH_STATUS                                                                               0x006b
  42 #define mmCG_TACH_STATUS_BASE_IDX                                                                      0
  43
  44 #define mmTHM_THERMAL_INT_ENA                                                                          0x000a
  45 #define mmTHM_THERMAL_INT_ENA_BASE_IDX                                                                 0
  46 #define mmTHM_THERMAL_INT_CTRL                                                                         0x000b
  47 #define mmTHM_THERMAL_INT_CTRL_BASE_IDX                                                                0
  48
  49 #define mmTHM_TCON_THERM_TRIP                                                                          0x0002
  50 #define mmTHM_TCON_THERM_TRIP_BASE_IDX                                                                 0
  51
  52 #define mmTHM_BACO_CNTL                                                                                0x0081
  53 #define mmTHM_BACO_CNTL_BASE_IDX                                                                       0
  54
  55 #define mmCG_THERMAL_STATUS                                                                            0x006C
  56 #define mmCG_THERMAL_STATUS_BASE_IDX                                                                   0
  57
  58 #endif