2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4)
30 #include "dmub_fw_types.h"
31 #include "include_legacy/atomfirmware.h"
33 #if defined(_TEST_HARNESS)
38 #include <asm/byteorder.h>
39 #include <linux/types.h>
40 #include <linux/string.h>
41 #include <linux/delay.h>
44 #include "atomfirmware.h"
46 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4)
48 /* Firmware versioning. */
49 #ifdef DMUB_EXPOSE_VERSION
50 #define DMUB_FW_VERSION_GIT_HASH 0xa18e25995
51 #define DMUB_FW_VERSION_MAJOR 0
52 #define DMUB_FW_VERSION_MINOR 0
53 #define DMUB_FW_VERSION_REVISION 46
54 #define DMUB_FW_VERSION_TEST 0
55 #define DMUB_FW_VERSION_VBIOS 0
56 #define DMUB_FW_VERSION_HOTFIX 0
57 #define DMUB_FW_VERSION_UCODE (((DMUB_FW_VERSION_MAJOR & 0xFF) << 24) | \
58 ((DMUB_FW_VERSION_MINOR & 0xFF) << 16) | \
59 ((DMUB_FW_VERSION_REVISION & 0xFF) << 8) | \
60 ((DMUB_FW_VERSION_TEST & 0x1) << 7) | \
61 ((DMUB_FW_VERSION_VBIOS & 0x1) << 6) | \
62 (DMUB_FW_VERSION_HOTFIX & 0x3F))
66 //<DMUB_TYPES>==================================================================
67 /* Basic type definitions. */
69 #define __forceinline inline
71 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0
72 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255
73 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254
74 #define SET_ABM_PIPE_NORMAL 1
76 /* Maximum number of streams on any ASIC. */
77 #define DMUB_MAX_STREAMS 6
79 /* Maximum number of planes on any ASIC. */
80 #define DMUB_MAX_PLANES 6
82 #ifndef PHYSICAL_ADDRESS_LOC
83 #define PHYSICAL_ADDRESS_LOC union large_integer
87 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes))
91 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))
94 #if defined(__cplusplus)
99 #define dmub_udelay(microseconds) udelay(microseconds)
110 union dmub_psr_debug_flags {
112 uint32_t visual_confirm : 1;
113 uint32_t use_hw_lock_mgr : 1;
114 uint32_t log_line_nums : 1;
120 struct dmub_feature_caps {
125 #if defined(__cplusplus)
129 //==============================================================================
130 //</DMUB_TYPES>=================================================================
131 //==============================================================================
132 //< DMUB_META>==================================================================
133 //==============================================================================
134 #pragma pack(push, 1)
136 /* Magic value for identifying dmub_fw_meta_info */
137 #define DMUB_FW_META_MAGIC 0x444D5542
139 /* Offset from the end of the file to the dmub_fw_meta_info */
140 #define DMUB_FW_META_OFFSET 0x24
143 * struct dmub_fw_meta_info - metadata associated with fw binary
145 * NOTE: This should be considered a stable API. Fields should
146 * not be repurposed or reordered. New fields should be
147 * added instead to extend the structure.
149 * @magic_value: magic value identifying DMUB firmware meta info
150 * @fw_region_size: size of the firmware state region
151 * @trace_buffer_size: size of the tracebuffer region
152 * @fw_version: the firmware version information
153 * @dal_fw: 1 if the firmware is DAL
155 struct dmub_fw_meta_info {
156 uint32_t magic_value;
157 uint32_t fw_region_size;
158 uint32_t trace_buffer_size;
164 /* Ensure that the structure remains 64 bytes. */
166 struct dmub_fw_meta_info info;
167 uint8_t reserved[64];
172 //==============================================================================
173 //< DMUB_STATUS>================================================================
174 //==============================================================================
177 * DMCUB scratch registers can be used to determine firmware status.
178 * Current scratch register usage is as follows:
180 * SCRATCH0: FW Boot Status register
181 * SCRATCH15: FW Boot Options register
184 /* Register bit definition for SCRATCH0 */
185 union dmub_fw_boot_status {
188 uint32_t mailbox_rdy : 1;
189 uint32_t optimized_init_done : 1;
190 uint32_t restore_required : 1;
195 enum dmub_fw_boot_status_bit {
196 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0),
197 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1),
198 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2),
199 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3),
202 /* Register bit definition for SCRATCH15 */
203 union dmub_fw_boot_options {
205 uint32_t pemu_env : 1;
206 uint32_t fpga_env : 1;
207 uint32_t optimized_init : 1;
208 uint32_t skip_phy_access : 1;
209 uint32_t disable_clk_gate: 1;
210 uint32_t skip_phy_init_panel_sequence: 1;
211 uint32_t reserved : 26;
216 enum dmub_fw_boot_options_bit {
217 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0),
218 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1),
219 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2),
222 //==============================================================================
223 //</DMUB_STATUS>================================================================
224 //==============================================================================
225 //< DMUB_VBIOS>=================================================================
226 //==============================================================================
229 * Command IDs should be treated as stable ABI.
230 * Do not reuse or modify IDs.
233 enum dmub_cmd_vbios_type {
234 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0,
235 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1,
236 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2,
237 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3,
238 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15,
241 //==============================================================================
242 //</DMUB_VBIOS>=================================================================
243 //==============================================================================
244 //< DMUB_GPINT>=================================================================
245 //==============================================================================
248 * The shifts and masks below may alternatively be used to format and read
249 * the command register bits.
252 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF
253 #define DMUB_GPINT_DATA_PARAM_SHIFT 0
255 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF
256 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16
258 #define DMUB_GPINT_DATA_STATUS_MASK 0xF
259 #define DMUB_GPINT_DATA_STATUS_SHIFT 28
265 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD
268 * The register format for sending a command via the GPINT.
270 union dmub_gpint_data_register {
273 uint32_t command_code : 12;
280 * Command IDs should be treated as stable ABI.
281 * Do not reuse or modify IDs.
284 enum dmub_gpint_command {
285 DMUB_GPINT__INVALID_COMMAND = 0,
286 DMUB_GPINT__GET_FW_VERSION = 1,
287 DMUB_GPINT__STOP_FW = 2,
288 DMUB_GPINT__GET_PSR_STATE = 7,
290 * DESC: Notifies DMCUB of the currently active streams.
291 * ARGS: Stream mask, 1 bit per active stream index.
293 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8,
294 DMUB_GPINT__PSR_RESIDENCY = 9,
297 //==============================================================================
298 //</DMUB_GPINT>=================================================================
299 //==============================================================================
300 //< DMUB_CMD>===================================================================
301 //==============================================================================
303 #define DMUB_RB_CMD_SIZE 64
304 #define DMUB_RB_MAX_ENTRY 128
305 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
306 #define REG_SET_MASK 0xFFFF
309 * Command IDs should be treated as stable ABI.
310 * Do not reuse or modify IDs.
315 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1,
316 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2,
317 DMUB_CMD__REG_SEQ_BURST_WRITE = 3,
318 DMUB_CMD__REG_REG_WAIT = 4,
319 DMUB_CMD__PLAT_54186_WA = 5,
320 DMUB_CMD__QUERY_FEATURE_CAPS = 6,
324 DMUB_CMD__HW_LOCK = 69,
325 DMUB_CMD__DP_AUX_ACCESS = 70,
326 DMUB_CMD__OUTBOX1_ENABLE = 71,
327 DMUB_CMD__VBIOS = 128,
330 enum dmub_out_cmd_type {
331 DMUB_OUT_CMD__NULL = 0,
332 DMUB_OUT_CMD__DP_AUX_REPLY = 1,
333 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2,
336 #pragma pack(push, 1)
338 struct dmub_cmd_header {
339 unsigned int type : 8;
340 unsigned int sub_type : 8;
341 unsigned int ret_status : 1;
342 unsigned int reserved0 : 7;
343 unsigned int payload_bytes : 6; /* up to 60 bytes */
344 unsigned int reserved1 : 2;
350 * 60 payload bytes can hold up to 5 sets of read modify writes,
351 * each take 3 dwords.
353 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence)
355 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case
356 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
358 struct dmub_cmd_read_modify_write_sequence {
360 uint32_t modify_mask;
361 uint32_t modify_value;
364 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5
365 struct dmub_rb_cmd_read_modify_write {
366 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE
367 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];
371 * Update a register with specified masks and values sequeunce
373 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword
375 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence)
379 * 1. auto-increment register where additional read would update pointer and produce wrong result
380 * 2. toggle a bit without read in the middle
383 struct dmub_cmd_reg_field_update_sequence {
384 uint32_t modify_mask; // 0xffff'ffff to skip initial read
385 uint32_t modify_value;
388 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7
389 struct dmub_rb_cmd_reg_field_update_sequence {
390 struct dmub_cmd_header header;
392 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX];
398 * support use case such as writing out LUTs.
400 * 60 payload bytes can hold up to 14 values to write to given address
402 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
404 #define DMUB_BURST_WRITE_VALUES__MAX 14
405 struct dmub_rb_cmd_burst_write {
406 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_BURST_WRITE
408 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];
412 struct dmub_rb_cmd_common {
413 struct dmub_cmd_header header;
414 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];
417 struct dmub_cmd_reg_wait_data {
420 uint32_t condition_field_value;
421 uint32_t time_out_us;
424 struct dmub_rb_cmd_reg_wait {
425 struct dmub_cmd_header header;
426 struct dmub_cmd_reg_wait_data reg_wait;
429 struct dmub_cmd_PLAT_54186_wa {
430 uint32_t DCSURF_SURFACE_CONTROL;
431 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH;
432 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS;
433 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C;
434 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C;
436 uint8_t hubp_inst : 4;
437 uint8_t tmz_surface : 1;
438 uint8_t immediate :1;
440 uint8_t grph_stereo : 1;
441 uint32_t reserved : 21;
443 uint32_t reserved[9];
446 struct dmub_rb_cmd_PLAT_54186_wa {
447 struct dmub_cmd_header header;
448 struct dmub_cmd_PLAT_54186_wa flip;
451 struct dmub_rb_cmd_mall {
452 struct dmub_cmd_header header;
453 union dmub_addr cursor_copy_src;
454 union dmub_addr cursor_copy_dst;
457 uint16_t cursor_width;
458 uint16_t cursor_pitch;
459 uint16_t cursor_height;
463 struct dmub_cmd_digx_encoder_control_data {
464 union dig_encoder_control_parameters_v1_5 dig;
467 struct dmub_rb_cmd_digx_encoder_control {
468 struct dmub_cmd_header header;
469 struct dmub_cmd_digx_encoder_control_data encoder_control;
472 struct dmub_cmd_set_pixel_clock_data {
473 struct set_pixel_clock_parameter_v1_7 clk;
476 struct dmub_rb_cmd_set_pixel_clock {
477 struct dmub_cmd_header header;
478 struct dmub_cmd_set_pixel_clock_data pixel_clock;
481 struct dmub_cmd_enable_disp_power_gating_data {
482 struct enable_disp_power_gating_parameters_v2_1 pwr;
485 struct dmub_rb_cmd_enable_disp_power_gating {
486 struct dmub_cmd_header header;
487 struct dmub_cmd_enable_disp_power_gating_data power_gating;
490 struct dmub_cmd_dig1_transmitter_control_data {
491 struct dig_transmitter_control_parameters_v1_6 dig;
494 struct dmub_rb_cmd_dig1_transmitter_control {
495 struct dmub_cmd_header header;
496 struct dmub_cmd_dig1_transmitter_control_data transmitter_control;
499 struct dmub_rb_cmd_dpphy_init {
500 struct dmub_cmd_header header;
501 uint8_t reserved[60];
504 enum dp_aux_request_action {
505 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00,
506 DP_AUX_REQ_ACTION_I2C_READ = 0x10,
507 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20,
508 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40,
509 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50,
510 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60,
511 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80,
512 DP_AUX_REQ_ACTION_DPCD_READ = 0x90
515 enum aux_return_code_type {
517 AUX_RET_ERROR_UNKNOWN,
518 AUX_RET_ERROR_INVALID_REPLY,
519 AUX_RET_ERROR_TIMEOUT,
520 AUX_RET_ERROR_HPD_DISCON,
521 AUX_RET_ERROR_ENGINE_ACQUIRE,
522 AUX_RET_ERROR_INVALID_OPERATION,
523 AUX_RET_ERROR_PROTOCOL_ERROR,
526 enum aux_channel_type {
527 AUX_CHANNEL_LEGACY_DDC,
532 struct aux_transaction_parameters {
533 uint8_t is_i2c_over_aux;
541 struct dmub_cmd_dp_aux_control_data {
544 uint8_t sw_crc_enabled;
546 enum aux_channel_type type;
547 struct aux_transaction_parameters dpaux;
550 struct dmub_rb_cmd_dp_aux_access {
551 struct dmub_cmd_header header;
552 struct dmub_cmd_dp_aux_control_data aux_control;
555 struct dmub_rb_cmd_outbox1_enable {
556 struct dmub_cmd_header header;
560 /* DP AUX Reply command - OutBox Cmd */
561 struct aux_reply_data {
568 struct aux_reply_control_data {
575 struct dmub_rb_cmd_dp_aux_reply {
576 struct dmub_cmd_header header;
577 struct aux_reply_control_data control;
578 struct aux_reply_data reply_data;
581 /* DP HPD Notify command - OutBox Cmd */
599 struct dmub_rb_cmd_dp_hpd_notify {
600 struct dmub_cmd_header header;
601 struct dp_hpd_data hpd_data;
605 * Command IDs should be treated as stable ABI.
606 * Do not reuse or modify IDs.
609 enum dmub_cmd_psr_type {
610 DMUB_CMD__PSR_SET_VERSION = 0,
611 DMUB_CMD__PSR_COPY_SETTINGS = 1,
612 DMUB_CMD__PSR_ENABLE = 2,
613 DMUB_CMD__PSR_DISABLE = 3,
614 DMUB_CMD__PSR_SET_LEVEL = 4,
615 DMUB_CMD__PSR_FORCE_STATIC = 5,
620 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF,
623 enum dmub_cmd_mall_type {
624 DMUB_CMD__MALL_ACTION_ALLOW = 0,
625 DMUB_CMD__MALL_ACTION_DISALLOW = 1,
626 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2,
629 struct dmub_cmd_psr_copy_settings_data {
630 union dmub_psr_debug_flags debug;
633 /* opp_inst and mpcc_inst will not be used in dmub fw,
634 * dmub fw will get active opp by reading odm registers.
644 uint8_t smu_optimizations_en;
646 uint8_t frame_cap_ind;
648 uint8_t multi_disp_optimizations_en;
649 uint16_t init_sdp_deadline;
653 struct dmub_rb_cmd_psr_copy_settings {
654 struct dmub_cmd_header header;
655 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data;
658 struct dmub_cmd_psr_set_level_data {
663 struct dmub_rb_cmd_psr_set_level {
664 struct dmub_cmd_header header;
665 struct dmub_cmd_psr_set_level_data psr_set_level_data;
668 struct dmub_rb_cmd_psr_enable {
669 struct dmub_cmd_header header;
672 struct dmub_cmd_psr_set_version_data {
673 enum psr_version version; // PSR version 1 or 2
676 struct dmub_rb_cmd_psr_set_version {
677 struct dmub_cmd_header header;
678 struct dmub_cmd_psr_set_version_data psr_set_version_data;
681 struct dmub_rb_cmd_psr_force_static {
682 struct dmub_cmd_header header;
685 union dmub_hw_lock_flags {
687 uint8_t lock_pipe : 1;
688 uint8_t lock_cursor : 1;
689 uint8_t lock_dig : 1;
690 uint8_t triple_buffer_lock : 1;
696 struct dmub_hw_lock_inst_flags {
703 enum hw_lock_client {
704 HW_LOCK_CLIENT_DRIVER = 0,
706 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF,
709 struct dmub_cmd_lock_hw_data {
710 enum hw_lock_client client;
711 struct dmub_hw_lock_inst_flags inst_flags;
712 union dmub_hw_lock_flags hw_locks;
714 uint8_t should_release;
718 struct dmub_rb_cmd_lock_hw {
719 struct dmub_cmd_header header;
720 struct dmub_cmd_lock_hw_data lock_hw_data;
723 enum dmub_cmd_abm_type {
724 DMUB_CMD__ABM_INIT_CONFIG = 0,
725 DMUB_CMD__ABM_SET_PIPE = 1,
726 DMUB_CMD__ABM_SET_BACKLIGHT = 2,
727 DMUB_CMD__ABM_SET_LEVEL = 3,
728 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4,
729 DMUB_CMD__ABM_SET_PWM_FRAC = 5,
732 #define NUM_AMBI_LEVEL 5
733 #define NUM_AGGR_LEVEL 4
734 #define NUM_POWER_FN_SEGS 8
735 #define NUM_BL_CURVE_SEGS 16
738 * Parameters for ABM2.4 algorithm.
739 * Padded explicitly to 32-bit boundary.
741 struct abm_config_table {
742 /* Parameters for crgb conversion */
743 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B
744 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B
745 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B
747 /* Parameters for custom curve */
748 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B
749 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B
751 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B
752 uint16_t min_abm_backlight; // 122B
754 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B
755 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B
756 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B
757 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B
758 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B
759 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B
760 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B
761 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B
762 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B
763 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B
764 uint8_t pad3[3]; // 229B
766 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B
767 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B
770 struct dmub_cmd_abm_set_pipe_data {
773 uint8_t set_pipe_option;
774 uint8_t ramping_boundary; // TODO: Remove this
777 struct dmub_rb_cmd_abm_set_pipe {
778 struct dmub_cmd_header header;
779 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data;
782 struct dmub_cmd_abm_set_backlight_data {
784 uint32_t backlight_user_level;
787 struct dmub_rb_cmd_abm_set_backlight {
788 struct dmub_cmd_header header;
789 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data;
792 struct dmub_cmd_abm_set_level_data {
796 struct dmub_rb_cmd_abm_set_level {
797 struct dmub_cmd_header header;
798 struct dmub_cmd_abm_set_level_data abm_set_level_data;
801 struct dmub_cmd_abm_set_ambient_level_data {
802 uint32_t ambient_lux;
805 struct dmub_rb_cmd_abm_set_ambient_level {
806 struct dmub_cmd_header header;
807 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data;
810 struct dmub_cmd_abm_set_pwm_frac_data {
811 uint32_t fractional_pwm;
814 struct dmub_rb_cmd_abm_set_pwm_frac {
815 struct dmub_cmd_header header;
816 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data;
819 struct dmub_cmd_abm_init_config_data {
824 struct dmub_rb_cmd_abm_init_config {
825 struct dmub_cmd_header header;
826 struct dmub_cmd_abm_init_config_data abm_init_config_data;
829 struct dmub_cmd_query_feature_caps_data {
830 struct dmub_feature_caps feature_caps;
833 struct dmub_rb_cmd_query_feature_caps {
834 struct dmub_cmd_header header;
835 struct dmub_cmd_query_feature_caps_data query_feature_caps_data;
839 struct dmub_rb_cmd_lock_hw lock_hw;
840 struct dmub_rb_cmd_read_modify_write read_modify_write;
841 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq;
842 struct dmub_rb_cmd_burst_write burst_write;
843 struct dmub_rb_cmd_reg_wait reg_wait;
844 struct dmub_rb_cmd_common cmd_common;
845 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control;
846 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock;
847 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating;
848 struct dmub_rb_cmd_dpphy_init dpphy_init;
849 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control;
850 struct dmub_rb_cmd_psr_set_version psr_set_version;
851 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
852 struct dmub_rb_cmd_psr_enable psr_enable;
853 struct dmub_rb_cmd_psr_set_level psr_set_level;
854 struct dmub_rb_cmd_psr_force_static psr_force_static;
855 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa;
856 struct dmub_rb_cmd_mall mall;
857 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe;
858 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight;
859 struct dmub_rb_cmd_abm_set_level abm_set_level;
860 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level;
861 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac;
862 struct dmub_rb_cmd_abm_init_config abm_init_config;
863 struct dmub_rb_cmd_dp_aux_access dp_aux_access;
864 struct dmub_rb_cmd_outbox1_enable outbox1_enable;
865 struct dmub_rb_cmd_query_feature_caps query_feature_caps;
868 union dmub_rb_out_cmd {
869 struct dmub_rb_cmd_common cmd_common;
870 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply;
871 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify;
876 //==============================================================================
877 //</DMUB_CMD>===================================================================
878 //==============================================================================
879 //< DMUB_RB>====================================================================
880 //==============================================================================
882 #if defined(__cplusplus)
886 struct dmub_rb_init_params {
906 static inline bool dmub_rb_empty(struct dmub_rb *rb)
908 return (rb->wrpt == rb->rptr);
911 static inline bool dmub_rb_full(struct dmub_rb *rb)
915 if (rb->wrpt >= rb->rptr)
916 data_count = rb->wrpt - rb->rptr;
918 data_count = rb->capacity - (rb->rptr - rb->wrpt);
920 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE));
923 static inline bool dmub_rb_push_front(struct dmub_rb *rb,
924 const union dmub_rb_cmd *cmd)
926 uint64_t volatile *dst = (uint64_t volatile *)(rb->base_address) + rb->wrpt / sizeof(uint64_t);
927 const uint64_t *src = (const uint64_t *)cmd;
930 if (dmub_rb_full(rb))
934 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
937 rb->wrpt += DMUB_RB_CMD_SIZE;
939 if (rb->wrpt >= rb->capacity)
940 rb->wrpt %= rb->capacity;
945 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb,
946 const union dmub_rb_out_cmd *cmd)
948 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt;
949 const uint8_t *src = (uint8_t *)cmd;
951 if (dmub_rb_full(rb))
954 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE);
956 rb->wrpt += DMUB_RB_CMD_SIZE;
958 if (rb->wrpt >= rb->capacity)
959 rb->wrpt %= rb->capacity;
964 static inline bool dmub_rb_front(struct dmub_rb *rb,
965 union dmub_rb_cmd **cmd)
967 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr;
969 if (dmub_rb_empty(rb))
972 *cmd = (union dmub_rb_cmd *)rb_cmd;
977 static inline bool dmub_rb_out_front(struct dmub_rb *rb,
978 union dmub_rb_out_cmd *cmd)
980 const uint64_t volatile *src = (const uint64_t volatile *)(rb->base_address) + rb->rptr / sizeof(uint64_t);
981 uint64_t *dst = (uint64_t *)cmd;
984 if (dmub_rb_empty(rb))
988 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
994 static inline bool dmub_rb_pop_front(struct dmub_rb *rb)
996 if (dmub_rb_empty(rb))
999 rb->rptr += DMUB_RB_CMD_SIZE;
1001 if (rb->rptr >= rb->capacity)
1002 rb->rptr %= rb->capacity;
1007 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb)
1009 uint32_t rptr = rb->rptr;
1010 uint32_t wptr = rb->wrpt;
1012 while (rptr != wptr) {
1013 uint64_t volatile *data = (uint64_t volatile *)rb->base_address + rptr / sizeof(uint64_t);
1016 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
1019 rptr += DMUB_RB_CMD_SIZE;
1020 if (rptr >= rb->capacity)
1021 rptr %= rb->capacity;
1025 static inline void dmub_rb_init(struct dmub_rb *rb,
1026 struct dmub_rb_init_params *init_params)
1028 rb->base_address = init_params->base_address;
1029 rb->capacity = init_params->capacity;
1030 rb->rptr = init_params->read_ptr;
1031 rb->wrpt = init_params->write_ptr;
1034 static inline void dmub_rb_get_return_data(struct dmub_rb *rb,
1035 union dmub_rb_cmd *cmd)
1037 // Copy rb entry back into command
1038 uint8_t *rd_ptr = (rb->rptr == 0) ?
1039 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE :
1040 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE;
1042 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE);
1045 #if defined(__cplusplus)
1049 //==============================================================================
1050 //</DMUB_RB>====================================================================
1051 //==============================================================================
1053 #endif /* _DMUB_CMD_H_ */