2 * Copyright 2019 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
29 #include "dmub_types.h"
30 #include "dmub_cmd_dal.h"
31 #include "dmub_cmd_vbios.h"
32 #include "atomfirmware.h"
34 #define DMUB_RB_CMD_SIZE 64
35 #define DMUB_RB_MAX_ENTRY 128
36 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
37 #define REG_SET_MASK 0xFFFF
39 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0
40 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255
41 #define SET_ABM_PIPE_NORMAL 1
44 * Command IDs should be treated as stable ABI.
45 * Do not reuse or modify IDs.
50 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1,
51 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2,
52 DMUB_CMD__REG_SEQ_BURST_WRITE = 3,
53 DMUB_CMD__REG_REG_WAIT = 4,
54 DMUB_CMD__PLAT_54186_WA = 5,
57 DMUB_CMD__VBIOS = 128,
62 struct dmub_cmd_header {
63 unsigned int type : 8;
64 unsigned int sub_type : 8;
65 unsigned int reserved0 : 8;
66 unsigned int payload_bytes : 6; /* up to 60 bytes */
67 unsigned int reserved1 : 2;
73 * 60 payload bytes can hold up to 5 sets of read modify writes,
76 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence)
78 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case
79 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
81 struct dmub_cmd_read_modify_write_sequence {
84 uint32_t modify_value;
87 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5
88 struct dmub_rb_cmd_read_modify_write {
89 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE
90 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];
94 * Update a register with specified masks and values sequeunce
96 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword
98 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence)
102 * 1. auto-increment register where additional read would update pointer and produce wrong result
103 * 2. toggle a bit without read in the middle
106 struct dmub_cmd_reg_field_update_sequence {
107 uint32_t modify_mask; // 0xffff'ffff to skip initial read
108 uint32_t modify_value;
111 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7
113 struct dmub_rb_cmd_reg_field_update_sequence {
114 struct dmub_cmd_header header;
116 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX];
123 * support use case such as writing out LUTs.
125 * 60 payload bytes can hold up to 14 values to write to given address
127 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
129 #define DMUB_BURST_WRITE_VALUES__MAX 14
130 struct dmub_rb_cmd_burst_write {
131 struct dmub_cmd_header header; // type = DMUB_CMD__REG_SEQ_BURST_WRITE
133 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];
137 struct dmub_rb_cmd_common {
138 struct dmub_cmd_header header;
139 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];
142 struct dmub_cmd_reg_wait_data {
145 uint32_t condition_field_value;
146 uint32_t time_out_us;
149 struct dmub_rb_cmd_reg_wait {
150 struct dmub_cmd_header header;
151 struct dmub_cmd_reg_wait_data reg_wait;
154 #ifndef PHYSICAL_ADDRESS_LOC
155 #define PHYSICAL_ADDRESS_LOC union large_integer
158 struct dmub_cmd_PLAT_54186_wa {
159 uint32_t DCSURF_SURFACE_CONTROL;
160 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH;
161 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS;
162 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C;
163 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C;
165 uint8_t hubp_inst : 4;
166 uint8_t tmz_surface : 1;
167 uint8_t immediate :1;
169 uint8_t grph_stereo : 1;
170 uint32_t reserved : 21;
172 uint32_t reserved[9];
175 struct dmub_rb_cmd_PLAT_54186_wa {
176 struct dmub_cmd_header header;
177 struct dmub_cmd_PLAT_54186_wa flip;
180 struct dmub_cmd_digx_encoder_control_data {
181 union dig_encoder_control_parameters_v1_5 dig;
184 struct dmub_rb_cmd_digx_encoder_control {
185 struct dmub_cmd_header header;
186 struct dmub_cmd_digx_encoder_control_data encoder_control;
189 struct dmub_cmd_set_pixel_clock_data {
190 struct set_pixel_clock_parameter_v1_7 clk;
193 struct dmub_rb_cmd_set_pixel_clock {
194 struct dmub_cmd_header header;
195 struct dmub_cmd_set_pixel_clock_data pixel_clock;
198 struct dmub_cmd_enable_disp_power_gating_data {
199 struct enable_disp_power_gating_parameters_v2_1 pwr;
202 struct dmub_rb_cmd_enable_disp_power_gating {
203 struct dmub_cmd_header header;
204 struct dmub_cmd_enable_disp_power_gating_data power_gating;
207 struct dmub_cmd_dig1_transmitter_control_data {
208 struct dig_transmitter_control_parameters_v1_6 dig;
211 struct dmub_rb_cmd_dig1_transmitter_control {
212 struct dmub_cmd_header header;
213 struct dmub_cmd_dig1_transmitter_control_data transmitter_control;
216 struct dmub_rb_cmd_dpphy_init {
217 struct dmub_cmd_header header;
218 uint8_t reserved[60];
221 struct dmub_cmd_psr_copy_settings_data {
222 union dmub_psr_debug_flags debug;
232 uint8_t smu_optimizations_en;
234 uint8_t frame_cap_ind;
238 struct dmub_rb_cmd_psr_copy_settings {
239 struct dmub_cmd_header header;
240 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data;
243 struct dmub_cmd_psr_set_level_data {
248 struct dmub_rb_cmd_psr_set_level {
249 struct dmub_cmd_header header;
250 struct dmub_cmd_psr_set_level_data psr_set_level_data;
253 struct dmub_rb_cmd_psr_enable {
254 struct dmub_cmd_header header;
257 struct dmub_cmd_psr_set_version_data {
258 enum psr_version version; // PSR version 1 or 2
261 struct dmub_rb_cmd_psr_set_version {
262 struct dmub_cmd_header header;
263 struct dmub_cmd_psr_set_version_data psr_set_version_data;
266 struct dmub_cmd_abm_set_pipe_data {
269 uint8_t set_pipe_option;
270 uint8_t ramping_boundary; // TODO: Remove this
273 struct dmub_rb_cmd_abm_set_pipe {
274 struct dmub_cmd_header header;
275 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data;
278 struct dmub_cmd_abm_set_backlight_data {
280 uint32_t backlight_user_level;
283 struct dmub_rb_cmd_abm_set_backlight {
284 struct dmub_cmd_header header;
285 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data;
288 struct dmub_cmd_abm_set_level_data {
292 struct dmub_rb_cmd_abm_set_level {
293 struct dmub_cmd_header header;
294 struct dmub_cmd_abm_set_level_data abm_set_level_data;
297 struct dmub_cmd_abm_set_ambient_level_data {
298 uint32_t ambient_lux;
301 struct dmub_rb_cmd_abm_set_ambient_level {
302 struct dmub_cmd_header header;
303 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data;
306 struct dmub_cmd_abm_set_pwm_frac_data {
307 uint32_t fractional_pwm;
310 struct dmub_rb_cmd_abm_set_pwm_frac {
311 struct dmub_cmd_header header;
312 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data;
315 struct dmub_cmd_abm_init_config_data {
320 struct dmub_rb_cmd_abm_init_config {
321 struct dmub_cmd_header header;
322 struct dmub_cmd_abm_init_config_data abm_init_config_data;
326 struct dmub_rb_cmd_read_modify_write read_modify_write;
327 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq;
328 struct dmub_rb_cmd_burst_write burst_write;
329 struct dmub_rb_cmd_reg_wait reg_wait;
330 struct dmub_rb_cmd_common cmd_common;
331 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control;
332 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock;
333 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating;
334 struct dmub_rb_cmd_dpphy_init dpphy_init;
335 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control;
336 struct dmub_rb_cmd_psr_set_version psr_set_version;
337 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
338 struct dmub_rb_cmd_psr_enable psr_enable;
339 struct dmub_rb_cmd_psr_set_level psr_set_level;
340 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa;
341 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe;
342 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight;
343 struct dmub_rb_cmd_abm_set_level abm_set_level;
344 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level;
345 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac;
346 struct dmub_rb_cmd_abm_init_config abm_init_config;
351 #endif /* _DMUB_CMD_H_ */