drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c

   1 /*
   2  * Copyright 2018 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/slab.h>
  27
  28 #include "dm_services.h"
  29
  30 #include "include/logger_interface.h"
  31
  32 #include "../dce110/irq_service_dce110.h"
  33
  34 #include "dcn/dcn_2_1_0_offset.h"
  35 #include "dcn/dcn_2_1_0_sh_mask.h"
  36 #include "renoir_ip_offset.h"
  37
  38
  39 #include "irq_service_dcn21.h"
  40
  41 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  42
  43 enum dc_irq_source to_dal_irq_source_dcn21(
  44                 struct irq_service *irq_service,
  45                 uint32_t src_id,
  46                 uint32_t ext_id)
  47 {
  48         switch (src_id) {
  49         case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
  50                 return DC_IRQ_SOURCE_VBLANK1;
  51         case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
  52                 return DC_IRQ_SOURCE_VBLANK2;
  53         case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
  54                 return DC_IRQ_SOURCE_VBLANK3;
  55         case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
  56                 return DC_IRQ_SOURCE_VBLANK4;
  57         case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
  58                 return DC_IRQ_SOURCE_VBLANK5;
  59         case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
  60                 return DC_IRQ_SOURCE_VBLANK6;
  61         case DCN_1_0__SRCID__DMCUB_OUTBOX_HIGH_PRIORITY_READY_INT:
  62                 return DC_IRQ_SOURCE_DMCUB_OUTBOX0;
  63         case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
  64                 return DC_IRQ_SOURCE_DC1_VLINE0;
  65         case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
  66                 return DC_IRQ_SOURCE_DC2_VLINE0;
  67         case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
  68                 return DC_IRQ_SOURCE_DC3_VLINE0;
  69         case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
  70                 return DC_IRQ_SOURCE_DC4_VLINE0;
  71         case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
  72                 return DC_IRQ_SOURCE_DC5_VLINE0;
  73         case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
  74                 return DC_IRQ_SOURCE_DC6_VLINE0;
  75         case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
  76                 return DC_IRQ_SOURCE_PFLIP1;
  77         case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
  78                 return DC_IRQ_SOURCE_PFLIP2;
  79         case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
  80                 return DC_IRQ_SOURCE_PFLIP3;
  81         case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
  82                 return DC_IRQ_SOURCE_PFLIP4;
  83         case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
  84                 return DC_IRQ_SOURCE_PFLIP5;
  85         case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
  86                 return DC_IRQ_SOURCE_PFLIP6;
  87         case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
  88                 return DC_IRQ_SOURCE_VUPDATE1;
  89         case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
  90                 return DC_IRQ_SOURCE_VUPDATE2;
  91         case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
  92                 return DC_IRQ_SOURCE_VUPDATE3;
  93         case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
  94                 return DC_IRQ_SOURCE_VUPDATE4;
  95         case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
  96                 return DC_IRQ_SOURCE_VUPDATE5;
  97         case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
  98                 return DC_IRQ_SOURCE_VUPDATE6;
  99
 100         case DCN_1_0__SRCID__DC_HPD1_INT:
 101                 /* generic src_id for all HPD and HPDRX interrupts */
 102                 switch (ext_id) {
 103                 case DCN_1_0__CTXID__DC_HPD1_INT:
 104                         return DC_IRQ_SOURCE_HPD1;
 105                 case DCN_1_0__CTXID__DC_HPD2_INT:
 106                         return DC_IRQ_SOURCE_HPD2;
 107                 case DCN_1_0__CTXID__DC_HPD3_INT:
 108                         return DC_IRQ_SOURCE_HPD3;
 109                 case DCN_1_0__CTXID__DC_HPD4_INT:
 110                         return DC_IRQ_SOURCE_HPD4;
 111                 case DCN_1_0__CTXID__DC_HPD5_INT:
 112                         return DC_IRQ_SOURCE_HPD5;
 113                 case DCN_1_0__CTXID__DC_HPD6_INT:
 114                         return DC_IRQ_SOURCE_HPD6;
 115                 case DCN_1_0__CTXID__DC_HPD1_RX_INT:
 116                         return DC_IRQ_SOURCE_HPD1RX;
 117                 case DCN_1_0__CTXID__DC_HPD2_RX_INT:
 118                         return DC_IRQ_SOURCE_HPD2RX;
 119                 case DCN_1_0__CTXID__DC_HPD3_RX_INT:
 120                         return DC_IRQ_SOURCE_HPD3RX;
 121                 case DCN_1_0__CTXID__DC_HPD4_RX_INT:
 122                         return DC_IRQ_SOURCE_HPD4RX;
 123                 case DCN_1_0__CTXID__DC_HPD5_RX_INT:
 124                         return DC_IRQ_SOURCE_HPD5RX;
 125                 case DCN_1_0__CTXID__DC_HPD6_RX_INT:
 126                         return DC_IRQ_SOURCE_HPD6RX;
 127                 default:
 128                         return DC_IRQ_SOURCE_INVALID;
 129                 }
 130                 break;
 131
 132         default:
 133                 break;
 134         }
 135         return DC_IRQ_SOURCE_INVALID;
 136 }
 137
 138 static bool hpd_ack(
 139         struct irq_service *irq_service,
 140         const struct irq_source_info *info)
 141 {
 142         uint32_t addr = info->status_reg;
 143         uint32_t value = dm_read_reg(irq_service->ctx, addr);
 144         uint32_t current_status =
 145                 get_reg_field_value(
 146                         value,
 147                         HPD0_DC_HPD_INT_STATUS,
 148                         DC_HPD_SENSE_DELAYED);
 149
 150         dal_irq_service_ack_generic(irq_service, info);
 151
 152         value = dm_read_reg(irq_service->ctx, info->enable_reg);
 153
 154         set_reg_field_value(
 155                 value,
 156                 current_status ? 0 : 1,
 157                 HPD0_DC_HPD_INT_CONTROL,
 158                 DC_HPD_INT_POLARITY);
 159
 160         dm_write_reg(irq_service->ctx, info->enable_reg, value);
 161
 162         return true;
 163 }
 164
 165 static const struct irq_source_info_funcs hpd_irq_info_funcs = {
 166         .set = NULL,
 167         .ack = hpd_ack
 168 };
 169
 170 static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
 171         .set = NULL,
 172         .ack = NULL
 173 };
 174
 175 static const struct irq_source_info_funcs pflip_irq_info_funcs = {
 176         .set = NULL,
 177         .ack = NULL
 178 };
 179
 180 static const struct irq_source_info_funcs vblank_irq_info_funcs = {
 181         .set = NULL,
 182         .ack = NULL
 183 };
 184
 185 static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
 186         .set = NULL,
 187         .ack = NULL
 188 };
 189
 190 static const struct irq_source_info_funcs dmub_trace_irq_info_funcs = {
 191         .set = NULL,
 192         .ack = NULL
 193 };
 194
 195 static const struct irq_source_info_funcs vline0_irq_info_funcs = {
 196         .set = NULL,
 197         .ack = NULL
 198 };
 199
 200 #undef BASE_INNER
 201 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
 202
 203 /* compile time expand base address. */
 204 #define BASE(seg) \
 205         BASE_INNER(seg)
 206
 207
 208 #define SRI(reg_name, block, id)\
 209         BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 210                         mm ## block ## id ## _ ## reg_name
 211
 212
 213 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
 214         .enable_reg = SRI(reg1, block, reg_num),\
 215         .enable_mask = \
 216                 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
 217         .enable_value = {\
 218                 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
 219                 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
 220         },\
 221         .ack_reg = SRI(reg2, block, reg_num),\
 222         .ack_mask = \
 223                 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
 224         .ack_value = \
 225                 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
 226
 227
 228
 229 #define hpd_int_entry(reg_num)\
 230         [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
 231                 IRQ_REG_ENTRY(HPD, reg_num,\
 232                         DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
 233                         DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
 234                 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
 235                 .funcs = &hpd_irq_info_funcs\
 236         }
 237
 238 #define hpd_rx_int_entry(reg_num)\
 239         [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
 240                 IRQ_REG_ENTRY(HPD, reg_num,\
 241                         DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
 242                         DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
 243                 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
 244                 .funcs = &hpd_rx_irq_info_funcs\
 245         }
 246 #define pflip_int_entry(reg_num)\
 247         [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
 248                 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
 249                         DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
 250                         DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
 251                 .funcs = &pflip_irq_info_funcs\
 252         }
 253
 254 #define vupdate_int_entry(reg_num)\
 255         [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
 256                 IRQ_REG_ENTRY(OTG, reg_num,\
 257                         OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\
 258                         OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\
 259                 .funcs = &vblank_irq_info_funcs\
 260         }
 261
 262 /* vupdate_no_lock_int_entry maps to DC_IRQ_SOURCE_VUPDATEx, to match semantic
 263  * of DCE's DC_IRQ_SOURCE_VUPDATEx.
 264  */
 265 #define vupdate_no_lock_int_entry(reg_num)\
 266         [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
 267                 IRQ_REG_ENTRY(OTG, reg_num,\
 268                         OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
 269                         OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
 270                 .funcs = &vupdate_no_lock_irq_info_funcs\
 271         }
 272
 273 #define vblank_int_entry(reg_num)\
 274         [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
 275                 IRQ_REG_ENTRY(OTG, reg_num,\
 276                         OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
 277                         OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
 278                 .funcs = &vblank_irq_info_funcs\
 279         }
 280
 281 #define vline0_int_entry(reg_num)\
 282         [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
 283                 IRQ_REG_ENTRY(OTG, reg_num,\
 284                         OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
 285                         OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
 286                 .funcs = &vline0_irq_info_funcs\
 287         }
 288
 289 #define dummy_irq_entry() \
 290         {\
 291                 .funcs = &dummy_irq_info_funcs\
 292         }
 293
 294 #define i2c_int_entry(reg_num) \
 295         [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
 296
 297 #define dp_sink_int_entry(reg_num) \
 298         [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
 299
 300 #define gpio_pad_int_entry(reg_num) \
 301         [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
 302
 303 #define dc_underflow_int_entry(reg_num) \
 304         [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
 305
 306 static const struct irq_source_info_funcs dummy_irq_info_funcs = {
 307         .set = dal_irq_service_dummy_set,
 308         .ack = dal_irq_service_dummy_ack
 309 };
 310
 311 static const struct irq_source_info
 312 irq_source_info_dcn21[DAL_IRQ_SOURCES_NUMBER] = {
 313         [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
 314         hpd_int_entry(0),
 315         hpd_int_entry(1),
 316         hpd_int_entry(2),
 317         hpd_int_entry(3),
 318         hpd_int_entry(4),
 319         hpd_rx_int_entry(0),
 320         hpd_rx_int_entry(1),
 321         hpd_rx_int_entry(2),
 322         hpd_rx_int_entry(3),
 323         hpd_rx_int_entry(4),
 324         i2c_int_entry(1),
 325         i2c_int_entry(2),
 326         i2c_int_entry(3),
 327         i2c_int_entry(4),
 328         i2c_int_entry(5),
 329         i2c_int_entry(6),
 330         dp_sink_int_entry(1),
 331         dp_sink_int_entry(2),
 332         dp_sink_int_entry(3),
 333         dp_sink_int_entry(4),
 334         dp_sink_int_entry(5),
 335         dp_sink_int_entry(6),
 336         [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
 337         pflip_int_entry(0),
 338         pflip_int_entry(1),
 339         pflip_int_entry(2),
 340         pflip_int_entry(3),
 341         [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
 342         [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
 343         [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
 344         gpio_pad_int_entry(0),
 345         gpio_pad_int_entry(1),
 346         gpio_pad_int_entry(2),
 347         gpio_pad_int_entry(3),
 348         gpio_pad_int_entry(4),
 349         gpio_pad_int_entry(5),
 350         gpio_pad_int_entry(6),
 351         gpio_pad_int_entry(7),
 352         gpio_pad_int_entry(8),
 353         gpio_pad_int_entry(9),
 354         gpio_pad_int_entry(10),
 355         gpio_pad_int_entry(11),
 356         gpio_pad_int_entry(12),
 357         gpio_pad_int_entry(13),
 358         gpio_pad_int_entry(14),
 359         gpio_pad_int_entry(15),
 360         gpio_pad_int_entry(16),
 361         gpio_pad_int_entry(17),
 362         gpio_pad_int_entry(18),
 363         gpio_pad_int_entry(19),
 364         gpio_pad_int_entry(20),
 365         gpio_pad_int_entry(21),
 366         gpio_pad_int_entry(22),
 367         gpio_pad_int_entry(23),
 368         gpio_pad_int_entry(24),
 369         gpio_pad_int_entry(25),
 370         gpio_pad_int_entry(26),
 371         gpio_pad_int_entry(27),
 372         gpio_pad_int_entry(28),
 373         gpio_pad_int_entry(29),
 374         gpio_pad_int_entry(30),
 375         dc_underflow_int_entry(1),
 376         dc_underflow_int_entry(2),
 377         dc_underflow_int_entry(3),
 378         dc_underflow_int_entry(4),
 379         dc_underflow_int_entry(5),
 380         dc_underflow_int_entry(6),
 381         [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
 382         [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
 383         vupdate_int_entry(0),
 384         vupdate_int_entry(1),
 385         vupdate_int_entry(2),
 386         vupdate_int_entry(3),
 387         vupdate_int_entry(4),
 388         vupdate_int_entry(5),
 389         vupdate_no_lock_int_entry(0),
 390         vupdate_no_lock_int_entry(1),
 391         vupdate_no_lock_int_entry(2),
 392         vupdate_no_lock_int_entry(3),
 393         vupdate_no_lock_int_entry(4),
 394         vupdate_no_lock_int_entry(5),
 395         vblank_int_entry(0),
 396         vblank_int_entry(1),
 397         vblank_int_entry(2),
 398         vblank_int_entry(3),
 399         vblank_int_entry(4),
 400         vblank_int_entry(5),
 401         vline0_int_entry(0),
 402         vline0_int_entry(1),
 403         vline0_int_entry(2),
 404         vline0_int_entry(3),
 405         vline0_int_entry(4),
 406         vline0_int_entry(5),
 407 };
 408
 409 static const struct irq_service_funcs irq_service_funcs_dcn21 = {
 410                 .to_dal_irq_source = to_dal_irq_source_dcn21
 411 };
 412
 413 static void dcn21_irq_construct(
 414         struct irq_service *irq_service,
 415         struct irq_service_init_data *init_data)
 416 {
 417         dal_irq_service_construct(irq_service, init_data);
 418
 419         irq_service->info = irq_source_info_dcn21;
 420         irq_service->funcs = &irq_service_funcs_dcn21;
 421 }
 422
 423 struct irq_service *dal_irq_service_dcn21_create(
 424         struct irq_service_init_data *init_data)
 425 {
 426         struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
 427                                                   GFP_KERNEL);
 428
 429         if (!irq_service)
 430                 return NULL;
 431
 432         dcn21_irq_construct(irq_service, init_data);
 433         return irq_service;
 434 }