2 * Copyright 2015 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
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9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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26 #ifndef __DC_LINK_DP_H__
27 #define __DC_LINK_DP_H__
29 #define LINK_TRAINING_ATTEMPTS 4
30 #define LINK_TRAINING_RETRY_DELAY 50 /* ms */
31 #define LINK_AUX_DEFAULT_LTTPR_TIMEOUT_PERIOD 3200 /*us*/
32 #define LINK_AUX_DEFAULT_TIMEOUT_PERIOD 552 /*us*/
33 #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50
34 #define TRAINING_AUX_RD_INTERVAL 100 //us
37 struct dc_stream_state;
38 struct dc_link_settings;
41 LINK_TRAINING_MAX_RETRY_COUNT = 5,
42 /* to avoid infinite loop where-in the receiver
43 * switches between different VS
45 LINK_TRAINING_MAX_CR_RETRY = 100
48 bool dp_verify_link_cap(
50 struct dc_link_settings *known_limit_link_setting,
53 bool dp_verify_link_cap_with_retries(
55 struct dc_link_settings *known_limit_link_setting,
58 bool dp_verify_mst_link_cap(
59 struct dc_link *link);
61 bool dp_validate_mode_timing(
63 const struct dc_crtc_timing *timing);
65 bool decide_edp_link_settings(struct dc_link *link,
66 struct dc_link_settings *link_setting,
69 void decide_link_settings(
70 struct dc_stream_state *stream,
71 struct dc_link_settings *link_setting);
73 bool perform_link_training_with_retries(
74 const struct dc_link_settings *link_setting,
75 bool skip_video_pattern,
77 struct pipe_ctx *pipe_ctx,
78 enum signal_type signal,
81 bool hpd_rx_irq_check_link_loss_status(
83 union hpd_irq_data *hpd_irq_dpcd_data);
85 bool is_mst_supported(struct dc_link *link);
87 bool detect_dp_sink_caps(struct dc_link *link);
89 void detect_edp_sink_caps(struct dc_link *link);
91 bool is_dp_active_dongle(const struct dc_link *link);
93 bool is_dp_branch_device(const struct dc_link *link);
95 bool is_edp_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing);
97 void dp_enable_mst_on_sink(struct dc_link *link, bool enable);
99 enum dp_panel_mode dp_get_panel_mode(struct dc_link *link);
100 void dp_set_panel_mode(struct dc_link *link, enum dp_panel_mode panel_mode);
102 bool dp_overwrite_extended_receiver_cap(struct dc_link *link);
104 void dpcd_set_source_specific_data(struct dc_link *link);
105 /* Write DPCD link configuration data. */
106 enum dc_status dpcd_set_link_settings(
107 struct dc_link *link,
108 const struct link_training_settings *lt_settings);
109 /* Write DPCD drive settings. */
110 enum dc_status dpcd_set_lane_settings(
111 struct dc_link *link,
112 const struct link_training_settings *link_training_setting,
114 /* Read training status and adjustment requests from DPCD. */
115 enum dc_status dp_get_lane_status_and_drive_settings(
116 struct dc_link *link,
117 const struct link_training_settings *link_training_setting,
118 union lane_status *ln_status,
119 union lane_align_status_updated *ln_status_updated,
120 struct link_training_settings *req_settings,
123 void dp_wait_for_training_aux_rd_interval(
124 struct dc_link *link,
125 uint32_t wait_in_micro_secs);
127 bool dp_is_cr_done(enum dc_lane_count ln_count,
128 union lane_status *dpcd_lane_status);
130 enum link_training_result dp_get_cr_failure(enum dc_lane_count ln_count,
131 union lane_status *dpcd_lane_status);
133 bool dp_is_max_vs_reached(
134 const struct link_training_settings *lt_settings);
136 void dp_update_drive_settings(
137 struct link_training_settings *dest,
138 struct link_training_settings src);
140 enum dpcd_training_patterns
141 dc_dp_training_pattern_to_dpcd_training_pattern(
142 struct dc_link *link,
143 enum dc_dp_training_pattern pattern);
145 uint8_t dc_dp_initialize_scrambling_data_symbols(
146 struct dc_link *link,
147 enum dc_dp_training_pattern pattern);
149 enum dc_status dp_set_fec_ready(struct dc_link *link, bool ready);
150 void dp_set_fec_enable(struct dc_link *link, bool enable);
151 bool dp_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable);
152 bool dp_set_dsc_pps_sdp(struct pipe_ctx *pipe_ctx, bool enable);
153 void dp_set_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable);
154 bool dp_update_dsc_config(struct pipe_ctx *pipe_ctx);
155 bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable);
157 /* Initialize output parameter lt_settings. */
158 void dp_decide_training_settings(
159 struct dc_link *link,
160 const struct dc_link_settings *link_setting,
161 const struct dc_link_training_overrides *overrides,
162 struct link_training_settings *lt_settings);
164 /* Convert PHY repeater count read from DPCD uint8_t. */
165 uint8_t dp_convert_to_count(uint8_t lttpr_repeater_count);
167 /* Check DPCD training status registers to detect link loss. */
168 enum link_training_result dp_check_link_loss_status(
169 struct dc_link *link,
170 const struct link_training_settings *link_training_setting);
172 enum dc_status dpcd_configure_lttpr_mode(
173 struct dc_link *link,
174 struct link_training_settings *lt_settings);
176 enum dp_link_encoding dp_get_link_encoding_format(const struct dc_link_settings *link_settings);
177 #endif /* __DC_LINK_DP_H__ */