drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "dm_services.h"
  28 #include "dc.h"
  29
  30 #include "dcn31/dcn31_init.h"
  31
  32 #include "resource.h"
  33 #include "include/irq_service_interface.h"
  34 #include "dcn31_resource.h"
  35
  36 #include "dcn20/dcn20_resource.h"
  37 #include "dcn30/dcn30_resource.h"
  38
  39 #include "dcn10/dcn10_ipp.h"
  40 #include "dcn30/dcn30_hubbub.h"
  41 #include "dcn31/dcn31_hubbub.h"
  42 #include "dcn30/dcn30_mpc.h"
  43 #include "dcn31/dcn31_hubp.h"
  44 #include "irq/dcn31/irq_service_dcn31.h"
  45 #include "dcn30/dcn30_dpp.h"
  46 #include "dcn31/dcn31_optc.h"
  47 #include "dcn20/dcn20_hwseq.h"
  48 #include "dcn30/dcn30_hwseq.h"
  49 #include "dce110/dce110_hw_sequencer.h"
  50 #include "dcn30/dcn30_opp.h"
  51 #include "dcn20/dcn20_dsc.h"
  52 #include "dcn30/dcn30_vpg.h"
  53 #include "dcn30/dcn30_afmt.h"
  54 #include "dcn30/dcn30_dio_stream_encoder.h"
  55 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
  56 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
  57 #include "dcn31/dcn31_apg.h"
  58 #include "dcn31/dcn31_dio_link_encoder.h"
  59 #include "dcn31/dcn31_vpg.h"
  60 #include "dcn31/dcn31_afmt.h"
  61 #include "dce/dce_clock_source.h"
  62 #include "dce/dce_audio.h"
  63 #include "dce/dce_hwseq.h"
  64 #include "clk_mgr.h"
  65 #include "virtual/virtual_stream_encoder.h"
  66 #include "dce110/dce110_resource.h"
  67 #include "dml/display_mode_vba.h"
  68 #include "dcn31/dcn31_dccg.h"
  69 #include "dcn10/dcn10_resource.h"
  70 #include "dcn31_panel_cntl.h"
  71
  72 #include "dcn30/dcn30_dwb.h"
  73 #include "dcn30/dcn30_mmhubbub.h"
  74
  75 // TODO: change include headers /amd/include/asic_reg after upstream
  76 #include "yellow_carp_offset.h"
  77 #include "dcn/dcn_3_1_2_offset.h"
  78 #include "dcn/dcn_3_1_2_sh_mask.h"
  79 #include "nbio/nbio_7_2_0_offset.h"
  80 #include "dpcs/dpcs_4_2_0_offset.h"
  81 #include "dpcs/dpcs_4_2_0_sh_mask.h"
  82 #include "mmhub/mmhub_2_3_0_offset.h"
  83 #include "mmhub/mmhub_2_3_0_sh_mask.h"
  84
  85
  86 #define regDCHUBBUB_DEBUG_CTRL_0                                              0x04d6
  87 #define regDCHUBBUB_DEBUG_CTRL_0_BASE_IDX                                     2
  88 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH__SHIFT                               0x10
  89 #define DCHUBBUB_DEBUG_CTRL_0__DET_DEPTH_MASK                                 0x01FF0000L
  90
  91 #include "reg_helper.h"
  92 #include "dce/dmub_abm.h"
  93 #include "dce/dmub_psr.h"
  94 #include "dce/dce_aux.h"
  95 #include "dce/dce_i2c.h"
  96
  97 #include "dml/dcn30/display_mode_vba_30.h"
  98 #include "vm_helper.h"
  99 #include "dcn20/dcn20_vmid.h"
 100
 101 #include "link_enc_cfg.h"
 102
 103 #define DC_LOGGER_INIT(logger)
 104
 105 #define DCN3_1_DEFAULT_DET_SIZE 384
 106
 107 struct _vcs_dpi_ip_params_st dcn3_1_ip = {
 108         .gpuvm_enable = 1,
 109         .gpuvm_max_page_table_levels = 1,
 110         .hostvm_enable = 1,
 111         .hostvm_max_page_table_levels = 2,
 112         .rob_buffer_size_kbytes = 64,
 113         .det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE,
 114         .config_return_buffer_size_in_kbytes = 1792,
 115         .compressed_buffer_segment_size_in_kbytes = 64,
 116         .meta_fifo_size_in_kentries = 32,
 117         .zero_size_buffer_entries = 512,
 118         .compbuf_reserved_space_64b = 256,
 119         .compbuf_reserved_space_zs = 64,
 120         .dpp_output_buffer_pixels = 2560,
 121         .opp_output_buffer_lines = 1,
 122         .pixel_chunk_size_kbytes = 8,
 123         .meta_chunk_size_kbytes = 2,
 124         .min_meta_chunk_size_bytes = 256,
 125         .writeback_chunk_size_kbytes = 8,
 126         .ptoi_supported = false,
 127         .num_dsc = 3,
 128         .maximum_dsc_bits_per_component = 10,
 129         .dsc422_native_support = false,
 130         .is_line_buffer_bpp_fixed = true,
 131         .line_buffer_fixed_bpp = 48,
 132         .line_buffer_size_bits = 789504,
 133         .max_line_buffer_lines = 12,
 134         .writeback_interface_buffer_size_kbytes = 90,
 135         .max_num_dpp = 4,
 136         .max_num_otg = 4,
 137         .max_num_hdmi_frl_outputs = 1,
 138         .max_num_wb = 1,
 139         .max_dchub_pscl_bw_pix_per_clk = 4,
 140         .max_pscl_lb_bw_pix_per_clk = 2,
 141         .max_lb_vscl_bw_pix_per_clk = 4,
 142         .max_vscl_hscl_bw_pix_per_clk = 4,
 143         .max_hscl_ratio = 6,
 144         .max_vscl_ratio = 6,
 145         .max_hscl_taps = 8,
 146         .max_vscl_taps = 8,
 147         .dpte_buffer_size_in_pte_reqs_luma = 64,
 148         .dpte_buffer_size_in_pte_reqs_chroma = 34,
 149         .dispclk_ramp_margin_percent = 1,
 150         .max_inter_dcn_tile_repeaters = 8,
 151         .cursor_buffer_size = 16,
 152         .cursor_chunk_size = 2,
 153         .writeback_line_buffer_buffer_size = 0,
 154         .writeback_min_hscl_ratio = 1,
 155         .writeback_min_vscl_ratio = 1,
 156         .writeback_max_hscl_ratio = 1,
 157         .writeback_max_vscl_ratio = 1,
 158         .writeback_max_hscl_taps = 1,
 159         .writeback_max_vscl_taps = 1,
 160         .dppclk_delay_subtotal = 46,
 161         .dppclk_delay_scl = 50,
 162         .dppclk_delay_scl_lb_only = 16,
 163         .dppclk_delay_cnvc_formatter = 27,
 164         .dppclk_delay_cnvc_cursor = 6,
 165         .dispclk_delay_subtotal = 119,
 166         .dynamic_metadata_vm_enabled = false,
 167         .odm_combine_4to1_supported = false,
 168         .dcc_supported = true,
 169 };
 170
 171 struct _vcs_dpi_soc_bounding_box_st dcn3_1_soc = {
 172                 /*TODO: correct dispclk/dppclk voltage level determination*/
 173         .clock_limits = {
 174                 {
 175                         .state = 0,
 176                         .dispclk_mhz = 1200.0,
 177                         .dppclk_mhz = 1200.0,
 178                         .phyclk_mhz = 600.0,
 179                         .phyclk_d18_mhz = 667.0,
 180                         .dscclk_mhz = 186.0,
 181                         .dtbclk_mhz = 625.0,
 182                 },
 183                 {
 184                         .state = 1,
 185                         .dispclk_mhz = 1200.0,
 186                         .dppclk_mhz = 1200.0,
 187                         .phyclk_mhz = 810.0,
 188                         .phyclk_d18_mhz = 667.0,
 189                         .dscclk_mhz = 209.0,
 190                         .dtbclk_mhz = 625.0,
 191                 },
 192                 {
 193                         .state = 2,
 194                         .dispclk_mhz = 1200.0,
 195                         .dppclk_mhz = 1200.0,
 196                         .phyclk_mhz = 810.0,
 197                         .phyclk_d18_mhz = 667.0,
 198                         .dscclk_mhz = 209.0,
 199                         .dtbclk_mhz = 625.0,
 200                 },
 201                 {
 202                         .state = 3,
 203                         .dispclk_mhz = 1200.0,
 204                         .dppclk_mhz = 1200.0,
 205                         .phyclk_mhz = 810.0,
 206                         .phyclk_d18_mhz = 667.0,
 207                         .dscclk_mhz = 371.0,
 208                         .dtbclk_mhz = 625.0,
 209                 },
 210                 {
 211                         .state = 4,
 212                         .dispclk_mhz = 1200.0,
 213                         .dppclk_mhz = 1200.0,
 214                         .phyclk_mhz = 810.0,
 215                         .phyclk_d18_mhz = 667.0,
 216                         .dscclk_mhz = 417.0,
 217                         .dtbclk_mhz = 625.0,
 218                 },
 219         },
 220         .num_states = 5,
 221         .sr_exit_time_us = 9.0,
 222         .sr_enter_plus_exit_time_us = 11.0,
 223         .sr_exit_z8_time_us = 442.0,
 224         .sr_enter_plus_exit_z8_time_us = 560.0,
 225         .writeback_latency_us = 12.0,
 226         .dram_channel_width_bytes = 4,
 227         .round_trip_ping_latency_dcfclk_cycles = 106,
 228         .urgent_latency_pixel_data_only_us = 4.0,
 229         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 230         .urgent_latency_vm_data_only_us = 4.0,
 231         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 232         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 233         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 234         .pct_ideal_sdp_bw_after_urgent = 80.0,
 235         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 65.0,
 236         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
 237         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 30.0,
 238         .max_avg_sdp_bw_use_normal_percent = 60.0,
 239         .max_avg_dram_bw_use_normal_percent = 60.0,
 240         .fabric_datapath_to_dcn_data_return_bytes = 32,
 241         .return_bus_width_bytes = 64,
 242         .downspread_percent = 0.38,
 243         .dcn_downspread_percent = 0.5,
 244         .gpuvm_min_page_size_bytes = 4096,
 245         .hostvm_min_page_size_bytes = 4096,
 246         .do_urgent_latency_adjustment = false,
 247         .urgent_latency_adjustment_fabric_clock_component_us = 0,
 248         .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
 249 };
 250
 251 enum dcn31_clk_src_array_id {
 252         DCN31_CLK_SRC_PLL0,
 253         DCN31_CLK_SRC_PLL1,
 254         DCN31_CLK_SRC_PLL2,
 255         DCN31_CLK_SRC_PLL3,
 256         DCN31_CLK_SRC_PLL4,
 257         DCN30_CLK_SRC_TOTAL
 258 };
 259
 260 /* begin *********************
 261  * macros to expend register list macro defined in HW object header file
 262  */
 263
 264 /* DCN */
 265 /* TODO awful hack. fixup dcn20_dwb.h */
 266 #undef BASE_INNER
 267 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 268
 269 #define BASE(seg) BASE_INNER(seg)
 270
 271 #define SR(reg_name)\
 272                 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) +  \
 273                                         reg ## reg_name
 274
 275 #define SRI(reg_name, block, id)\
 276         .reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 277                                         reg ## block ## id ## _ ## reg_name
 278
 279 #define SRI2(reg_name, block, id)\
 280         .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
 281                                         reg ## reg_name
 282
 283 #define SRIR(var_name, reg_name, block, id)\
 284         .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 285                                         reg ## block ## id ## _ ## reg_name
 286
 287 #define SRII(reg_name, block, id)\
 288         .reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 289                                         reg ## block ## id ## _ ## reg_name
 290
 291 #define SRII_MPC_RMU(reg_name, block, id)\
 292         .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 293                                         reg ## block ## id ## _ ## reg_name
 294
 295 #define SRII_DWB(reg_name, temp_name, block, id)\
 296         .reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 297                                         reg ## block ## id ## _ ## temp_name
 298
 299 #define DCCG_SRII(reg_name, block, id)\
 300         .block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 301                                         reg ## block ## id ## _ ## reg_name
 302
 303 #define VUPDATE_SRII(reg_name, block, id)\
 304         .reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 305                                         reg ## reg_name ## _ ## block ## id
 306
 307 /* NBIO */
 308 #define NBIO_BASE_INNER(seg) \
 309         NBIO_BASE__INST0_SEG ## seg
 310
 311 #define NBIO_BASE(seg) \
 312         NBIO_BASE_INNER(seg)
 313
 314 #define NBIO_SR(reg_name)\
 315                 .reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
 316                                         regBIF_BX1_ ## reg_name
 317
 318 /* MMHUB */
 319 #define MMHUB_BASE_INNER(seg) \
 320         MMHUB_BASE__INST0_SEG ## seg
 321
 322 #define MMHUB_BASE(seg) \
 323         MMHUB_BASE_INNER(seg)
 324
 325 #define MMHUB_SR(reg_name)\
 326                 .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \
 327                                         mm ## reg_name
 328
 329 /* CLOCK */
 330 #define CLK_BASE_INNER(seg) \
 331         CLK_BASE__INST0_SEG ## seg
 332
 333 #define CLK_BASE(seg) \
 334         CLK_BASE_INNER(seg)
 335
 336 #define CLK_SRI(reg_name, block, inst)\
 337         .reg_name = CLK_BASE(reg ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
 338                                         reg ## block ## _ ## inst ## _ ## reg_name
 339
 340
 341 static const struct bios_registers bios_regs = {
 342                 NBIO_SR(BIOS_SCRATCH_3),
 343                 NBIO_SR(BIOS_SCRATCH_6)
 344 };
 345
 346 #define clk_src_regs(index, pllid)\
 347 [index] = {\
 348         CS_COMMON_REG_LIST_DCN3_0(index, pllid),\
 349 }
 350
 351 static const struct dce110_clk_src_regs clk_src_regs[] = {
 352         clk_src_regs(0, A),
 353         clk_src_regs(1, B),
 354         clk_src_regs(2, C),
 355         clk_src_regs(3, D),
 356         clk_src_regs(4, E)
 357 };
 358 /*pll_id being rempped in dmub, in driver it is logical instance*/
 359 static const struct dce110_clk_src_regs clk_src_regs_b0[] = {
 360         clk_src_regs(0, A),
 361         clk_src_regs(1, B),
 362         clk_src_regs(2, F),
 363         clk_src_regs(3, G),
 364         clk_src_regs(4, E)
 365 };
 366
 367 static const struct dce110_clk_src_shift cs_shift = {
 368                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 369 };
 370
 371 static const struct dce110_clk_src_mask cs_mask = {
 372                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 373 };
 374
 375 #define abm_regs(id)\
 376 [id] = {\
 377                 ABM_DCN302_REG_LIST(id)\
 378 }
 379
 380 static const struct dce_abm_registers abm_regs[] = {
 381                 abm_regs(0),
 382                 abm_regs(1),
 383                 abm_regs(2),
 384                 abm_regs(3),
 385 };
 386
 387 static const struct dce_abm_shift abm_shift = {
 388                 ABM_MASK_SH_LIST_DCN30(__SHIFT)
 389 };
 390
 391 static const struct dce_abm_mask abm_mask = {
 392                 ABM_MASK_SH_LIST_DCN30(_MASK)
 393 };
 394
 395 #define audio_regs(id)\
 396 [id] = {\
 397                 AUD_COMMON_REG_LIST(id)\
 398 }
 399
 400 static const struct dce_audio_registers audio_regs[] = {
 401         audio_regs(0),
 402         audio_regs(1),
 403         audio_regs(2),
 404         audio_regs(3),
 405         audio_regs(4),
 406         audio_regs(5),
 407         audio_regs(6)
 408 };
 409
 410 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 411                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 412                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 413                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 414
 415 static const struct dce_audio_shift audio_shift = {
 416                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 417 };
 418
 419 static const struct dce_audio_mask audio_mask = {
 420                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 421 };
 422
 423 #define vpg_regs(id)\
 424 [id] = {\
 425         VPG_DCN31_REG_LIST(id)\
 426 }
 427
 428 static const struct dcn31_vpg_registers vpg_regs[] = {
 429         vpg_regs(0),
 430         vpg_regs(1),
 431         vpg_regs(2),
 432         vpg_regs(3),
 433         vpg_regs(4),
 434         vpg_regs(5),
 435         vpg_regs(6),
 436         vpg_regs(7),
 437         vpg_regs(8),
 438         vpg_regs(9),
 439 };
 440
 441 static const struct dcn31_vpg_shift vpg_shift = {
 442         DCN31_VPG_MASK_SH_LIST(__SHIFT)
 443 };
 444
 445 static const struct dcn31_vpg_mask vpg_mask = {
 446         DCN31_VPG_MASK_SH_LIST(_MASK)
 447 };
 448
 449 #define afmt_regs(id)\
 450 [id] = {\
 451         AFMT_DCN31_REG_LIST(id)\
 452 }
 453
 454 static const struct dcn31_afmt_registers afmt_regs[] = {
 455         afmt_regs(0),
 456         afmt_regs(1),
 457         afmt_regs(2),
 458         afmt_regs(3),
 459         afmt_regs(4),
 460         afmt_regs(5)
 461 };
 462
 463 static const struct dcn31_afmt_shift afmt_shift = {
 464         DCN31_AFMT_MASK_SH_LIST(__SHIFT)
 465 };
 466
 467 static const struct dcn31_afmt_mask afmt_mask = {
 468         DCN31_AFMT_MASK_SH_LIST(_MASK)
 469 };
 470
 471 #define apg_regs(id)\
 472 [id] = {\
 473         APG_DCN31_REG_LIST(id)\
 474 }
 475
 476 static const struct dcn31_apg_registers apg_regs[] = {
 477         apg_regs(0),
 478         apg_regs(1),
 479         apg_regs(2),
 480         apg_regs(3)
 481 };
 482
 483 static const struct dcn31_apg_shift apg_shift = {
 484         DCN31_APG_MASK_SH_LIST(__SHIFT)
 485 };
 486
 487 static const struct dcn31_apg_mask apg_mask = {
 488                 DCN31_APG_MASK_SH_LIST(_MASK)
 489 };
 490
 491 #define stream_enc_regs(id)\
 492 [id] = {\
 493         SE_DCN3_REG_LIST(id)\
 494 }
 495
 496 /* Some encoders won't be initialized here - but they're logical, not physical. */
 497 static const struct dcn10_stream_enc_registers stream_enc_regs[ENGINE_ID_COUNT] = {
 498         stream_enc_regs(0),
 499         stream_enc_regs(1),
 500         stream_enc_regs(2),
 501         stream_enc_regs(3),
 502         stream_enc_regs(4)
 503 };
 504
 505 static const struct dcn10_stream_encoder_shift se_shift = {
 506                 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 507 };
 508
 509 static const struct dcn10_stream_encoder_mask se_mask = {
 510                 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
 511 };
 512
 513
 514 #define aux_regs(id)\
 515 [id] = {\
 516         DCN2_AUX_REG_LIST(id)\
 517 }
 518
 519 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 520                 aux_regs(0),
 521                 aux_regs(1),
 522                 aux_regs(2),
 523                 aux_regs(3),
 524                 aux_regs(4)
 525 };
 526
 527 #define hpd_regs(id)\
 528 [id] = {\
 529         HPD_REG_LIST(id)\
 530 }
 531
 532 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 533                 hpd_regs(0),
 534                 hpd_regs(1),
 535                 hpd_regs(2),
 536                 hpd_regs(3),
 537                 hpd_regs(4)
 538 };
 539
 540 #define link_regs(id, phyid)\
 541 [id] = {\
 542         LE_DCN31_REG_LIST(id), \
 543         UNIPHY_DCN2_REG_LIST(phyid), \
 544         DPCS_DCN31_REG_LIST(id), \
 545 }
 546
 547 static const struct dce110_aux_registers_shift aux_shift = {
 548         DCN_AUX_MASK_SH_LIST(__SHIFT)
 549 };
 550
 551 static const struct dce110_aux_registers_mask aux_mask = {
 552         DCN_AUX_MASK_SH_LIST(_MASK)
 553 };
 554
 555 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 556         link_regs(0, A),
 557         link_regs(1, B),
 558         link_regs(2, C),
 559         link_regs(3, D),
 560         link_regs(4, E)
 561 };
 562
 563 static const struct dcn10_link_enc_shift le_shift = {
 564         LINK_ENCODER_MASK_SH_LIST_DCN31(__SHIFT), \
 565         DPCS_DCN31_MASK_SH_LIST(__SHIFT)
 566 };
 567
 568 static const struct dcn10_link_enc_mask le_mask = {
 569         LINK_ENCODER_MASK_SH_LIST_DCN31(_MASK), \
 570         DPCS_DCN31_MASK_SH_LIST(_MASK)
 571 };
 572
 573 #define hpo_dp_stream_encoder_reg_list(id)\
 574 [id] = {\
 575         DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\
 576 }
 577
 578 static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {
 579         hpo_dp_stream_encoder_reg_list(0),
 580         hpo_dp_stream_encoder_reg_list(1),
 581         hpo_dp_stream_encoder_reg_list(2),
 582         hpo_dp_stream_encoder_reg_list(3),
 583 };
 584
 585 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
 586         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
 587 };
 588
 589 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
 590         DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
 591 };
 592
 593 #define hpo_dp_link_encoder_reg_list(id)\
 594 [id] = {\
 595         DCN3_1_HPO_DP_LINK_ENC_REG_LIST(id),\
 596         DCN3_1_RDPCSTX_REG_LIST(0),\
 597         DCN3_1_RDPCSTX_REG_LIST(1),\
 598         DCN3_1_RDPCSTX_REG_LIST(2),\
 599         DCN3_1_RDPCSTX_REG_LIST(3),\
 600         DCN3_1_RDPCSTX_REG_LIST(4)\
 601 }
 602
 603 static const struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[] = {
 604         hpo_dp_link_encoder_reg_list(0),
 605         hpo_dp_link_encoder_reg_list(1),
 606 };
 607
 608 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
 609         DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
 610 };
 611
 612 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
 613         DCN3_1_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
 614 };
 615
 616 #define dpp_regs(id)\
 617 [id] = {\
 618         DPP_REG_LIST_DCN30(id),\
 619 }
 620
 621 static const struct dcn3_dpp_registers dpp_regs[] = {
 622         dpp_regs(0),
 623         dpp_regs(1),
 624         dpp_regs(2),
 625         dpp_regs(3)
 626 };
 627
 628 static const struct dcn3_dpp_shift tf_shift = {
 629                 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
 630 };
 631
 632 static const struct dcn3_dpp_mask tf_mask = {
 633                 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
 634 };
 635
 636 #define opp_regs(id)\
 637 [id] = {\
 638         OPP_REG_LIST_DCN30(id),\
 639 }
 640
 641 static const struct dcn20_opp_registers opp_regs[] = {
 642         opp_regs(0),
 643         opp_regs(1),
 644         opp_regs(2),
 645         opp_regs(3)
 646 };
 647
 648 static const struct dcn20_opp_shift opp_shift = {
 649         OPP_MASK_SH_LIST_DCN20(__SHIFT)
 650 };
 651
 652 static const struct dcn20_opp_mask opp_mask = {
 653         OPP_MASK_SH_LIST_DCN20(_MASK)
 654 };
 655
 656 #define aux_engine_regs(id)\
 657 [id] = {\
 658         AUX_COMMON_REG_LIST0(id), \
 659         .AUXN_IMPCAL = 0, \
 660         .AUXP_IMPCAL = 0, \
 661         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 662 }
 663
 664 static const struct dce110_aux_registers aux_engine_regs[] = {
 665                 aux_engine_regs(0),
 666                 aux_engine_regs(1),
 667                 aux_engine_regs(2),
 668                 aux_engine_regs(3),
 669                 aux_engine_regs(4)
 670 };
 671
 672 #define dwbc_regs_dcn3(id)\
 673 [id] = {\
 674         DWBC_COMMON_REG_LIST_DCN30(id),\
 675 }
 676
 677 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
 678         dwbc_regs_dcn3(0),
 679 };
 680
 681 static const struct dcn30_dwbc_shift dwbc30_shift = {
 682         DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 683 };
 684
 685 static const struct dcn30_dwbc_mask dwbc30_mask = {
 686         DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 687 };
 688
 689 #define mcif_wb_regs_dcn3(id)\
 690 [id] = {\
 691         MCIF_WB_COMMON_REG_LIST_DCN30(id),\
 692 }
 693
 694 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
 695         mcif_wb_regs_dcn3(0)
 696 };
 697
 698 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
 699         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 700 };
 701
 702 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
 703         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
 704 };
 705
 706 #define dsc_regsDCN20(id)\
 707 [id] = {\
 708         DSC_REG_LIST_DCN20(id)\
 709 }
 710
 711 static const struct dcn20_dsc_registers dsc_regs[] = {
 712         dsc_regsDCN20(0),
 713         dsc_regsDCN20(1),
 714         dsc_regsDCN20(2)
 715 };
 716
 717 static const struct dcn20_dsc_shift dsc_shift = {
 718         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 719 };
 720
 721 static const struct dcn20_dsc_mask dsc_mask = {
 722         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 723 };
 724
 725 static const struct dcn30_mpc_registers mpc_regs = {
 726                 MPC_REG_LIST_DCN3_0(0),
 727                 MPC_REG_LIST_DCN3_0(1),
 728                 MPC_REG_LIST_DCN3_0(2),
 729                 MPC_REG_LIST_DCN3_0(3),
 730                 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
 731                 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
 732                 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
 733                 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
 734                 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
 735                 MPC_RMU_REG_LIST_DCN3AG(0),
 736                 MPC_RMU_REG_LIST_DCN3AG(1),
 737                 //MPC_RMU_REG_LIST_DCN3AG(2),
 738                 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
 739 };
 740
 741 static const struct dcn30_mpc_shift mpc_shift = {
 742         MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 743 };
 744
 745 static const struct dcn30_mpc_mask mpc_mask = {
 746         MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 747 };
 748
 749 #define optc_regs(id)\
 750 [id] = {OPTC_COMMON_REG_LIST_DCN3_1(id)}
 751
 752 static const struct dcn_optc_registers optc_regs[] = {
 753         optc_regs(0),
 754         optc_regs(1),
 755         optc_regs(2),
 756         optc_regs(3)
 757 };
 758
 759 static const struct dcn_optc_shift optc_shift = {
 760         OPTC_COMMON_MASK_SH_LIST_DCN3_1(__SHIFT)
 761 };
 762
 763 static const struct dcn_optc_mask optc_mask = {
 764         OPTC_COMMON_MASK_SH_LIST_DCN3_1(_MASK)
 765 };
 766
 767 #define hubp_regs(id)\
 768 [id] = {\
 769         HUBP_REG_LIST_DCN30(id)\
 770 }
 771
 772 static const struct dcn_hubp2_registers hubp_regs[] = {
 773                 hubp_regs(0),
 774                 hubp_regs(1),
 775                 hubp_regs(2),
 776                 hubp_regs(3)
 777 };
 778
 779
 780 static const struct dcn_hubp2_shift hubp_shift = {
 781                 HUBP_MASK_SH_LIST_DCN31(__SHIFT)
 782 };
 783
 784 static const struct dcn_hubp2_mask hubp_mask = {
 785                 HUBP_MASK_SH_LIST_DCN31(_MASK)
 786 };
 787 static const struct dcn_hubbub_registers hubbub_reg = {
 788                 HUBBUB_REG_LIST_DCN31(0)
 789 };
 790
 791 static const struct dcn_hubbub_shift hubbub_shift = {
 792                 HUBBUB_MASK_SH_LIST_DCN31(__SHIFT)
 793 };
 794
 795 static const struct dcn_hubbub_mask hubbub_mask = {
 796                 HUBBUB_MASK_SH_LIST_DCN31(_MASK)
 797 };
 798
 799 static const struct dccg_registers dccg_regs = {
 800                 DCCG_REG_LIST_DCN31()
 801 };
 802
 803 static const struct dccg_shift dccg_shift = {
 804                 DCCG_MASK_SH_LIST_DCN31(__SHIFT)
 805 };
 806
 807 static const struct dccg_mask dccg_mask = {
 808                 DCCG_MASK_SH_LIST_DCN31(_MASK)
 809 };
 810
 811
 812 #define SRII2(reg_name_pre, reg_name_post, id)\
 813         .reg_name_pre ## _ ##  reg_name_post[id] = BASE(reg ## reg_name_pre \
 814                         ## id ## _ ## reg_name_post ## _BASE_IDX) + \
 815                         reg ## reg_name_pre ## id ## _ ## reg_name_post
 816
 817
 818 #define HWSEQ_DCN31_REG_LIST()\
 819         SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
 820         SR(DCHUBBUB_ARB_HOSTVM_CNTL), \
 821         SR(DIO_MEM_PWR_CTRL), \
 822         SR(ODM_MEM_PWR_CTRL3), \
 823         SR(DMU_MEM_PWR_CNTL), \
 824         SR(MMHUBBUB_MEM_PWR_CNTL), \
 825         SR(DCCG_GATE_DISABLE_CNTL), \
 826         SR(DCCG_GATE_DISABLE_CNTL2), \
 827         SR(DCFCLK_CNTL),\
 828         SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
 829         SRII(PIXEL_RATE_CNTL, OTG, 0), \
 830         SRII(PIXEL_RATE_CNTL, OTG, 1),\
 831         SRII(PIXEL_RATE_CNTL, OTG, 2),\
 832         SRII(PIXEL_RATE_CNTL, OTG, 3),\
 833         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
 834         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
 835         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
 836         SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
 837         SR(MICROSECOND_TIME_BASE_DIV), \
 838         SR(MILLISECOND_TIME_BASE_DIV), \
 839         SR(DISPCLK_FREQ_CHANGE_CNTL), \
 840         SR(RBBMIF_TIMEOUT_DIS), \
 841         SR(RBBMIF_TIMEOUT_DIS_2), \
 842         SR(DCHUBBUB_CRC_CTRL), \
 843         SR(DPP_TOP0_DPP_CRC_CTRL), \
 844         SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
 845         SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
 846         SR(MPC_CRC_CTRL), \
 847         SR(MPC_CRC_RESULT_GB), \
 848         SR(MPC_CRC_RESULT_C), \
 849         SR(MPC_CRC_RESULT_AR), \
 850         SR(DOMAIN0_PG_CONFIG), \
 851         SR(DOMAIN1_PG_CONFIG), \
 852         SR(DOMAIN2_PG_CONFIG), \
 853         SR(DOMAIN3_PG_CONFIG), \
 854         SR(DOMAIN16_PG_CONFIG), \
 855         SR(DOMAIN17_PG_CONFIG), \
 856         SR(DOMAIN18_PG_CONFIG), \
 857         SR(DOMAIN0_PG_STATUS), \
 858         SR(DOMAIN1_PG_STATUS), \
 859         SR(DOMAIN2_PG_STATUS), \
 860         SR(DOMAIN3_PG_STATUS), \
 861         SR(DOMAIN16_PG_STATUS), \
 862         SR(DOMAIN17_PG_STATUS), \
 863         SR(DOMAIN18_PG_STATUS), \
 864         SR(D1VGA_CONTROL), \
 865         SR(D2VGA_CONTROL), \
 866         SR(D3VGA_CONTROL), \
 867         SR(D4VGA_CONTROL), \
 868         SR(D5VGA_CONTROL), \
 869         SR(D6VGA_CONTROL), \
 870         SR(DC_IP_REQUEST_CNTL), \
 871         SR(AZALIA_AUDIO_DTO), \
 872         SR(AZALIA_CONTROLLER_CLOCK_GATING), \
 873         SR(HPO_TOP_HW_CONTROL)
 874
 875 static const struct dce_hwseq_registers hwseq_reg = {
 876                 HWSEQ_DCN31_REG_LIST()
 877 };
 878
 879 #define HWSEQ_DCN31_MASK_SH_LIST(mask_sh)\
 880         HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
 881         HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
 882         HWS_SF(, DCHUBBUB_ARB_HOSTVM_CNTL, DISABLE_HOSTVM_FORCE_ALLOW_PSTATE, mask_sh), \
 883         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 884         HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 885         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 886         HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 887         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 888         HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 889         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 890         HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 891         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 892         HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 893         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 894         HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 895         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
 896         HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
 897         HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 898         HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 899         HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 900         HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 901         HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 902         HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 903         HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
 904         HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
 905         HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
 906         HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
 907         HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
 908         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
 909         HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
 910         HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
 911         HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh), \
 912         HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh)
 913
 914 static const struct dce_hwseq_shift hwseq_shift = {
 915                 HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)
 916 };
 917
 918 static const struct dce_hwseq_mask hwseq_mask = {
 919                 HWSEQ_DCN31_MASK_SH_LIST(_MASK)
 920 };
 921 #define vmid_regs(id)\
 922 [id] = {\
 923                 DCN20_VMID_REG_LIST(id)\
 924 }
 925
 926 static const struct dcn_vmid_registers vmid_regs[] = {
 927         vmid_regs(0),
 928         vmid_regs(1),
 929         vmid_regs(2),
 930         vmid_regs(3),
 931         vmid_regs(4),
 932         vmid_regs(5),
 933         vmid_regs(6),
 934         vmid_regs(7),
 935         vmid_regs(8),
 936         vmid_regs(9),
 937         vmid_regs(10),
 938         vmid_regs(11),
 939         vmid_regs(12),
 940         vmid_regs(13),
 941         vmid_regs(14),
 942         vmid_regs(15)
 943 };
 944
 945 static const struct dcn20_vmid_shift vmid_shifts = {
 946                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 947 };
 948
 949 static const struct dcn20_vmid_mask vmid_masks = {
 950                 DCN20_VMID_MASK_SH_LIST(_MASK)
 951 };
 952
 953 static const struct resource_caps res_cap_dcn31 = {
 954         .num_timing_generator = 4,
 955         .num_opp = 4,
 956         .num_video_plane = 4,
 957         .num_audio = 5,
 958         .num_stream_encoder = 5,
 959         .num_dig_link_enc = 5,
 960         .num_hpo_dp_stream_encoder = 4,
 961         .num_hpo_dp_link_encoder = 2,
 962         .num_pll = 5,
 963         .num_dwb = 1,
 964         .num_ddc = 5,
 965         .num_vmid = 16,
 966         .num_mpc_3dlut = 2,
 967         .num_dsc = 3,
 968 };
 969
 970 static const struct dc_plane_cap plane_cap = {
 971         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 972         .blends_with_above = true,
 973         .blends_with_below = true,
 974         .per_pixel_alpha = true,
 975
 976         .pixel_format_support = {
 977                         .argb8888 = true,
 978                         .nv12 = true,
 979                         .fp16 = true,
 980                         .p010 = true,
 981                         .ayuv = false,
 982         },
 983
 984         .max_upscale_factor = {
 985                         .argb8888 = 16000,
 986                         .nv12 = 16000,
 987                         .fp16 = 16000
 988         },
 989
 990         // 6:1 downscaling ratio: 1000/6 = 166.666
 991         .max_downscale_factor = {
 992                         .argb8888 = 167,
 993                         .nv12 = 167,
 994                         .fp16 = 167
 995         },
 996         64,
 997         64
 998 };
 999
1000 static const struct dc_debug_options debug_defaults_drv = {
1001         .disable_dmcu = true,
1002         .force_abm_enable = false,
1003         .timing_trace = false,
1004         .clock_trace = true,
1005         .disable_pplib_clock_request = false,
1006         .pipe_split_policy = MPC_SPLIT_DYNAMIC,
1007         .force_single_disp_pipe_split = false,
1008         .disable_dcc = DCC_ENABLE,
1009         .vsr_support = true,
1010         .performance_trace = false,
1011         .max_downscale_src_width = 4096,/*upto true 4K*/
1012         .disable_pplib_wm_range = false,
1013         .scl_reset_length10 = true,
1014         .sanity_checks = true,
1015         .underflow_assert_delay_us = 0xFFFFFFFF,
1016         .dwb_fi_phase = -1, // -1 = disable,
1017         .dmub_command_table = true,
1018         .pstate_enabled = true,
1019         .use_max_lb = true,
1020         .enable_mem_low_power = {
1021                 .bits = {
1022                         .vga = true,
1023                         .i2c = true,
1024                         .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
1025                         .dscl = true,
1026                         .cm = true,
1027                         .mpc = true,
1028                         .optc = true,
1029                         .vpg = true,
1030                         .afmt = true,
1031                 }
1032         },
1033         .optimize_edp_link_rate = true,
1034         .enable_sw_cntl_psr = true,
1035         .apply_vendor_specific_lttpr_wa = true,
1036         .enable_z9_disable_interface = true, /* Allow support for the PMFW interface for disable Z9*/
1037 };
1038
1039 static const struct dc_debug_options debug_defaults_diags = {
1040         .disable_dmcu = true,
1041         .force_abm_enable = false,
1042         .timing_trace = true,
1043         .clock_trace = true,
1044         .disable_dpp_power_gate = true,
1045         .disable_hubp_power_gate = true,
1046         .disable_clock_gate = true,
1047         .disable_pplib_clock_request = true,
1048         .disable_pplib_wm_range = true,
1049         .disable_stutter = false,
1050         .scl_reset_length10 = true,
1051         .dwb_fi_phase = -1, // -1 = disable
1052         .dmub_command_table = true,
1053         .enable_tri_buf = true,
1054         .use_max_lb = true
1055 };
1056
1057 static void dcn31_dpp_destroy(struct dpp **dpp)
1058 {
1059         kfree(TO_DCN20_DPP(*dpp));
1060         *dpp = NULL;
1061 }
1062
1063 static struct dpp *dcn31_dpp_create(
1064         struct dc_context *ctx,
1065         uint32_t inst)
1066 {
1067         struct dcn3_dpp *dpp =
1068                 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
1069
1070         if (!dpp)
1071                 return NULL;
1072
1073         if (dpp3_construct(dpp, ctx, inst,
1074                         &dpp_regs[inst], &tf_shift, &tf_mask))
1075                 return &dpp->base;
1076
1077         BREAK_TO_DEBUGGER();
1078         kfree(dpp);
1079         return NULL;
1080 }
1081
1082 static struct output_pixel_processor *dcn31_opp_create(
1083         struct dc_context *ctx, uint32_t inst)
1084 {
1085         struct dcn20_opp *opp =
1086                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1087
1088         if (!opp) {
1089                 BREAK_TO_DEBUGGER();
1090                 return NULL;
1091         }
1092
1093         dcn20_opp_construct(opp, ctx, inst,
1094                         &opp_regs[inst], &opp_shift, &opp_mask);
1095         return &opp->base;
1096 }
1097
1098 static struct dce_aux *dcn31_aux_engine_create(
1099         struct dc_context *ctx,
1100         uint32_t inst)
1101 {
1102         struct aux_engine_dce110 *aux_engine =
1103                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
1104
1105         if (!aux_engine)
1106                 return NULL;
1107
1108         dce110_aux_engine_construct(aux_engine, ctx, inst,
1109                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1110                                     &aux_engine_regs[inst],
1111                                         &aux_mask,
1112                                         &aux_shift,
1113                                         ctx->dc->caps.extended_aux_timeout_support);
1114
1115         return &aux_engine->base;
1116 }
1117 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
1118
1119 static const struct dce_i2c_registers i2c_hw_regs[] = {
1120                 i2c_inst_regs(1),
1121                 i2c_inst_regs(2),
1122                 i2c_inst_regs(3),
1123                 i2c_inst_regs(4),
1124                 i2c_inst_regs(5),
1125 };
1126
1127 static const struct dce_i2c_shift i2c_shifts = {
1128                 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
1129 };
1130
1131 static const struct dce_i2c_mask i2c_masks = {
1132                 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
1133 };
1134
1135 static struct dce_i2c_hw *dcn31_i2c_hw_create(
1136         struct dc_context *ctx,
1137         uint32_t inst)
1138 {
1139         struct dce_i2c_hw *dce_i2c_hw =
1140                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1141
1142         if (!dce_i2c_hw)
1143                 return NULL;
1144
1145         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1146                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1147
1148         return dce_i2c_hw;
1149 }
1150 static struct mpc *dcn31_mpc_create(
1151                 struct dc_context *ctx,
1152                 int num_mpcc,
1153                 int num_rmu)
1154 {
1155         struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
1156                                           GFP_KERNEL);
1157
1158         if (!mpc30)
1159                 return NULL;
1160
1161         dcn30_mpc_construct(mpc30, ctx,
1162                         &mpc_regs,
1163                         &mpc_shift,
1164                         &mpc_mask,
1165                         num_mpcc,
1166                         num_rmu);
1167
1168         return &mpc30->base;
1169 }
1170
1171 static struct hubbub *dcn31_hubbub_create(struct dc_context *ctx)
1172 {
1173         int i;
1174
1175         struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1176                                           GFP_KERNEL);
1177
1178         if (!hubbub3)
1179                 return NULL;
1180
1181         hubbub31_construct(hubbub3, ctx,
1182                         &hubbub_reg,
1183                         &hubbub_shift,
1184                         &hubbub_mask,
1185                         dcn3_1_ip.det_buffer_size_kbytes,
1186                         dcn3_1_ip.pixel_chunk_size_kbytes,
1187                         dcn3_1_ip.config_return_buffer_size_in_kbytes);
1188
1189
1190         for (i = 0; i < res_cap_dcn31.num_vmid; i++) {
1191                 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1192
1193                 vmid->ctx = ctx;
1194
1195                 vmid->regs = &vmid_regs[i];
1196                 vmid->shifts = &vmid_shifts;
1197                 vmid->masks = &vmid_masks;
1198         }
1199
1200         return &hubbub3->base;
1201 }
1202
1203 static struct timing_generator *dcn31_timing_generator_create(
1204                 struct dc_context *ctx,
1205                 uint32_t instance)
1206 {
1207         struct optc *tgn10 =
1208                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1209
1210         if (!tgn10)
1211                 return NULL;
1212
1213         tgn10->base.inst = instance;
1214         tgn10->base.ctx = ctx;
1215
1216         tgn10->tg_regs = &optc_regs[instance];
1217         tgn10->tg_shift = &optc_shift;
1218         tgn10->tg_mask = &optc_mask;
1219
1220         dcn31_timing_generator_init(tgn10);
1221
1222         return &tgn10->base;
1223 }
1224
1225 static const struct encoder_feature_support link_enc_feature = {
1226                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1227                 .max_hdmi_pixel_clock = 600000,
1228                 .hdmi_ycbcr420_supported = true,
1229                 .dp_ycbcr420_supported = true,
1230                 .fec_supported = true,
1231                 .flags.bits.IS_HBR2_CAPABLE = true,
1232                 .flags.bits.IS_HBR3_CAPABLE = true,
1233                 .flags.bits.IS_TPS3_CAPABLE = true,
1234                 .flags.bits.IS_TPS4_CAPABLE = true
1235 };
1236
1237 static struct link_encoder *dcn31_link_encoder_create(
1238         const struct encoder_init_data *enc_init_data)
1239 {
1240         struct dcn20_link_encoder *enc20 =
1241                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1242
1243         if (!enc20)
1244                 return NULL;
1245
1246         dcn31_link_encoder_construct(enc20,
1247                         enc_init_data,
1248                         &link_enc_feature,
1249                         &link_enc_regs[enc_init_data->transmitter],
1250                         &link_enc_aux_regs[enc_init_data->channel - 1],
1251                         &link_enc_hpd_regs[enc_init_data->hpd_source],
1252                         &le_shift,
1253                         &le_mask);
1254
1255         return &enc20->enc10.base;
1256 }
1257
1258 /* Create a minimal link encoder object not associated with a particular
1259  * physical connector.
1260  * resource_funcs.link_enc_create_minimal
1261  */
1262 static struct link_encoder *dcn31_link_enc_create_minimal(
1263                 struct dc_context *ctx, enum engine_id eng_id)
1264 {
1265         struct dcn20_link_encoder *enc20;
1266
1267         if ((eng_id - ENGINE_ID_DIGA) > ctx->dc->res_pool->res_cap->num_dig_link_enc)
1268                 return NULL;
1269
1270         enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1271         if (!enc20)
1272                 return NULL;
1273
1274         dcn31_link_encoder_construct_minimal(
1275                         enc20,
1276                         ctx,
1277                         &link_enc_feature,
1278                         &link_enc_regs[eng_id - ENGINE_ID_DIGA],
1279                         eng_id);
1280
1281         return &enc20->enc10.base;
1282 }
1283
1284 static struct panel_cntl *dcn31_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1285 {
1286         struct dcn31_panel_cntl *panel_cntl =
1287                 kzalloc(sizeof(struct dcn31_panel_cntl), GFP_KERNEL);
1288
1289         if (!panel_cntl)
1290                 return NULL;
1291
1292         dcn31_panel_cntl_construct(panel_cntl, init_data);
1293
1294         return &panel_cntl->base;
1295 }
1296
1297 static void read_dce_straps(
1298         struct dc_context *ctx,
1299         struct resource_straps *straps)
1300 {
1301         generic_reg_get(ctx, regDC_PINSTRAPS + BASE(regDC_PINSTRAPS_BASE_IDX),
1302                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1303
1304 }
1305
1306 static struct audio *dcn31_create_audio(
1307                 struct dc_context *ctx, unsigned int inst)
1308 {
1309         return dce_audio_create(ctx, inst,
1310                         &audio_regs[inst], &audio_shift, &audio_mask);
1311 }
1312
1313 static struct vpg *dcn31_vpg_create(
1314         struct dc_context *ctx,
1315         uint32_t inst)
1316 {
1317         struct dcn31_vpg *vpg31 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1318
1319         if (!vpg31)
1320                 return NULL;
1321
1322         vpg31_construct(vpg31, ctx, inst,
1323                         &vpg_regs[inst],
1324                         &vpg_shift,
1325                         &vpg_mask);
1326
1327         return &vpg31->base;
1328 }
1329
1330 static struct afmt *dcn31_afmt_create(
1331         struct dc_context *ctx,
1332         uint32_t inst)
1333 {
1334         struct dcn31_afmt *afmt31 = kzalloc(sizeof(struct dcn31_afmt), GFP_KERNEL);
1335
1336         if (!afmt31)
1337                 return NULL;
1338
1339         afmt31_construct(afmt31, ctx, inst,
1340                         &afmt_regs[inst],
1341                         &afmt_shift,
1342                         &afmt_mask);
1343
1344         // Light sleep by default, no need to power down here
1345
1346         return &afmt31->base;
1347 }
1348
1349 static struct apg *dcn31_apg_create(
1350         struct dc_context *ctx,
1351         uint32_t inst)
1352 {
1353         struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1354
1355         if (!apg31)
1356                 return NULL;
1357
1358         apg31_construct(apg31, ctx, inst,
1359                         &apg_regs[inst],
1360                         &apg_shift,
1361                         &apg_mask);
1362
1363         return &apg31->base;
1364 }
1365
1366 static struct stream_encoder *dcn31_stream_encoder_create(
1367         enum engine_id eng_id,
1368         struct dc_context *ctx)
1369 {
1370         struct dcn10_stream_encoder *enc1;
1371         struct vpg *vpg;
1372         struct afmt *afmt;
1373         int vpg_inst;
1374         int afmt_inst;
1375
1376         /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1377         if (eng_id <= ENGINE_ID_DIGF) {
1378                 vpg_inst = eng_id;
1379                 afmt_inst = eng_id;
1380         } else
1381                 return NULL;
1382
1383         enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1384         vpg = dcn31_vpg_create(ctx, vpg_inst);
1385         afmt = dcn31_afmt_create(ctx, afmt_inst);
1386
1387         if (!enc1 || !vpg || !afmt) {
1388                 kfree(enc1);
1389                 kfree(vpg);
1390                 kfree(afmt);
1391                 return NULL;
1392         }
1393
1394         if (ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
1395                         ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
1396                 if ((eng_id == ENGINE_ID_DIGC) || (eng_id == ENGINE_ID_DIGD))
1397                         eng_id = eng_id + 3; // For B0 only. C->F, D->G.
1398         }
1399
1400         dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1401                                         eng_id, vpg, afmt,
1402                                         &stream_enc_regs[eng_id],
1403                                         &se_shift, &se_mask);
1404
1405         return &enc1->base;
1406 }
1407
1408 static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(
1409         enum engine_id eng_id,
1410         struct dc_context *ctx)
1411 {
1412         struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1413         struct vpg *vpg;
1414         struct apg *apg;
1415         uint32_t hpo_dp_inst;
1416         uint32_t vpg_inst;
1417         uint32_t apg_inst;
1418
1419         ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1420         hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1421
1422         /* Mapping of VPG register blocks to HPO DP block instance:
1423          * VPG[6] -> HPO_DP[0]
1424          * VPG[7] -> HPO_DP[1]
1425          * VPG[8] -> HPO_DP[2]
1426          * VPG[9] -> HPO_DP[3]
1427          */
1428         vpg_inst = hpo_dp_inst + 6;
1429
1430         /* Mapping of APG register blocks to HPO DP block instance:
1431          * APG[0] -> HPO_DP[0]
1432          * APG[1] -> HPO_DP[1]
1433          * APG[2] -> HPO_DP[2]
1434          * APG[3] -> HPO_DP[3]
1435          */
1436         apg_inst = hpo_dp_inst;
1437
1438         /* allocate HPO stream encoder and create VPG sub-block */
1439         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1440         vpg = dcn31_vpg_create(ctx, vpg_inst);
1441         apg = dcn31_apg_create(ctx, apg_inst);
1442
1443         if (!hpo_dp_enc31 || !vpg || !apg) {
1444                 kfree(hpo_dp_enc31);
1445                 kfree(vpg);
1446                 kfree(apg);
1447                 return NULL;
1448         }
1449
1450         dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1451                                         hpo_dp_inst, eng_id, vpg, apg,
1452                                         &hpo_dp_stream_enc_regs[hpo_dp_inst],
1453                                         &hpo_dp_se_shift, &hpo_dp_se_mask);
1454
1455         return &hpo_dp_enc31->base;
1456 }
1457
1458 static struct hpo_dp_link_encoder *dcn31_hpo_dp_link_encoder_create(
1459         uint8_t inst,
1460         struct dc_context *ctx)
1461 {
1462         struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1463
1464         /* allocate HPO link encoder */
1465         hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1466
1467         hpo_dp_link_encoder31_construct(hpo_dp_enc31, ctx, inst,
1468                                         &hpo_dp_link_enc_regs[inst],
1469                                         &hpo_dp_le_shift, &hpo_dp_le_mask);
1470
1471         return &hpo_dp_enc31->base;
1472 }
1473
1474 static struct dce_hwseq *dcn31_hwseq_create(
1475         struct dc_context *ctx)
1476 {
1477         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1478
1479         if (hws) {
1480                 hws->ctx = ctx;
1481                 hws->regs = &hwseq_reg;
1482                 hws->shifts = &hwseq_shift;
1483                 hws->masks = &hwseq_mask;
1484                 /* DCN3.1 FPGA Workaround
1485                  * Need to enable HPO DP Stream Encoder before setting OTG master enable.
1486                  * To do so, move calling function enable_stream_timing to only be done AFTER calling
1487                  * function core_link_enable_stream
1488                  */
1489                 if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
1490                         hws->wa.dp_hpo_and_otg_sequence = true;
1491         }
1492         return hws;
1493 }
1494 static const struct resource_create_funcs res_create_funcs = {
1495         .read_dce_straps = read_dce_straps,
1496         .create_audio = dcn31_create_audio,
1497         .create_stream_encoder = dcn31_stream_encoder_create,
1498         .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1499         .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1500         .create_hwseq = dcn31_hwseq_create,
1501 };
1502
1503 static const struct resource_create_funcs res_create_maximus_funcs = {
1504         .read_dce_straps = NULL,
1505         .create_audio = NULL,
1506         .create_stream_encoder = NULL,
1507         .create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,
1508         .create_hpo_dp_link_encoder = dcn31_hpo_dp_link_encoder_create,
1509         .create_hwseq = dcn31_hwseq_create,
1510 };
1511
1512 static void dcn31_resource_destruct(struct dcn31_resource_pool *pool)
1513 {
1514         unsigned int i;
1515
1516         for (i = 0; i < pool->base.stream_enc_count; i++) {
1517                 if (pool->base.stream_enc[i] != NULL) {
1518                         if (pool->base.stream_enc[i]->vpg != NULL) {
1519                                 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1520                                 pool->base.stream_enc[i]->vpg = NULL;
1521                         }
1522                         if (pool->base.stream_enc[i]->afmt != NULL) {
1523                                 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1524                                 pool->base.stream_enc[i]->afmt = NULL;
1525                         }
1526                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1527                         pool->base.stream_enc[i] = NULL;
1528                 }
1529         }
1530
1531         for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1532                 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1533                         if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1534                                 kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1535                                 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1536                         }
1537                         if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1538                                 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1539                                 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1540                         }
1541                         kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1542                         pool->base.hpo_dp_stream_enc[i] = NULL;
1543                 }
1544         }
1545
1546         for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1547                 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1548                         kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1549                         pool->base.hpo_dp_link_enc[i] = NULL;
1550                 }
1551         }
1552
1553         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1554                 if (pool->base.dscs[i] != NULL)
1555                         dcn20_dsc_destroy(&pool->base.dscs[i]);
1556         }
1557
1558         if (pool->base.mpc != NULL) {
1559                 kfree(TO_DCN20_MPC(pool->base.mpc));
1560                 pool->base.mpc = NULL;
1561         }
1562         if (pool->base.hubbub != NULL) {
1563                 kfree(pool->base.hubbub);
1564                 pool->base.hubbub = NULL;
1565         }
1566         for (i = 0; i < pool->base.pipe_count; i++) {
1567                 if (pool->base.dpps[i] != NULL)
1568                         dcn31_dpp_destroy(&pool->base.dpps[i]);
1569
1570                 if (pool->base.ipps[i] != NULL)
1571                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1572
1573                 if (pool->base.hubps[i] != NULL) {
1574                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1575                         pool->base.hubps[i] = NULL;
1576                 }
1577
1578                 if (pool->base.irqs != NULL) {
1579                         dal_irq_service_destroy(&pool->base.irqs);
1580                 }
1581         }
1582
1583         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1584                 if (pool->base.engines[i] != NULL)
1585                         dce110_engine_destroy(&pool->base.engines[i]);
1586                 if (pool->base.hw_i2cs[i] != NULL) {
1587                         kfree(pool->base.hw_i2cs[i]);
1588                         pool->base.hw_i2cs[i] = NULL;
1589                 }
1590                 if (pool->base.sw_i2cs[i] != NULL) {
1591                         kfree(pool->base.sw_i2cs[i]);
1592                         pool->base.sw_i2cs[i] = NULL;
1593                 }
1594         }
1595
1596         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1597                 if (pool->base.opps[i] != NULL)
1598                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1599         }
1600
1601         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1602                 if (pool->base.timing_generators[i] != NULL)    {
1603                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1604                         pool->base.timing_generators[i] = NULL;
1605                 }
1606         }
1607
1608         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1609                 if (pool->base.dwbc[i] != NULL) {
1610                         kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1611                         pool->base.dwbc[i] = NULL;
1612                 }
1613                 if (pool->base.mcif_wb[i] != NULL) {
1614                         kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1615                         pool->base.mcif_wb[i] = NULL;
1616                 }
1617         }
1618
1619         for (i = 0; i < pool->base.audio_count; i++) {
1620                 if (pool->base.audios[i])
1621                         dce_aud_destroy(&pool->base.audios[i]);
1622         }
1623
1624         for (i = 0; i < pool->base.clk_src_count; i++) {
1625                 if (pool->base.clock_sources[i] != NULL) {
1626                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1627                         pool->base.clock_sources[i] = NULL;
1628                 }
1629         }
1630
1631         for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1632                 if (pool->base.mpc_lut[i] != NULL) {
1633                         dc_3dlut_func_release(pool->base.mpc_lut[i]);
1634                         pool->base.mpc_lut[i] = NULL;
1635                 }
1636                 if (pool->base.mpc_shaper[i] != NULL) {
1637                         dc_transfer_func_release(pool->base.mpc_shaper[i]);
1638                         pool->base.mpc_shaper[i] = NULL;
1639                 }
1640         }
1641
1642         if (pool->base.dp_clock_source != NULL) {
1643                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1644                 pool->base.dp_clock_source = NULL;
1645         }
1646
1647         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1648                 if (pool->base.multiple_abms[i] != NULL)
1649                         dce_abm_destroy(&pool->base.multiple_abms[i]);
1650         }
1651
1652         if (pool->base.psr != NULL)
1653                 dmub_psr_destroy(&pool->base.psr);
1654
1655         if (pool->base.dccg != NULL)
1656                 dcn_dccg_destroy(&pool->base.dccg);
1657 }
1658
1659 static struct hubp *dcn31_hubp_create(
1660         struct dc_context *ctx,
1661         uint32_t inst)
1662 {
1663         struct dcn20_hubp *hubp2 =
1664                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1665
1666         if (!hubp2)
1667                 return NULL;
1668
1669         if (hubp31_construct(hubp2, ctx, inst,
1670                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1671                 return &hubp2->base;
1672
1673         BREAK_TO_DEBUGGER();
1674         kfree(hubp2);
1675         return NULL;
1676 }
1677
1678 static bool dcn31_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1679 {
1680         int i;
1681         uint32_t pipe_count = pool->res_cap->num_dwb;
1682
1683         for (i = 0; i < pipe_count; i++) {
1684                 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1685                                                     GFP_KERNEL);
1686
1687                 if (!dwbc30) {
1688                         dm_error("DC: failed to create dwbc30!\n");
1689                         return false;
1690                 }
1691
1692                 dcn30_dwbc_construct(dwbc30, ctx,
1693                                 &dwbc30_regs[i],
1694                                 &dwbc30_shift,
1695                                 &dwbc30_mask,
1696                                 i);
1697
1698                 pool->dwbc[i] = &dwbc30->base;
1699         }
1700         return true;
1701 }
1702
1703 static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1704 {
1705         int i;
1706         uint32_t pipe_count = pool->res_cap->num_dwb;
1707
1708         for (i = 0; i < pipe_count; i++) {
1709                 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1710                                                     GFP_KERNEL);
1711
1712                 if (!mcif_wb30) {
1713                         dm_error("DC: failed to create mcif_wb30!\n");
1714                         return false;
1715                 }
1716
1717                 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1718                                 &mcif_wb30_regs[i],
1719                                 &mcif_wb30_shift,
1720                                 &mcif_wb30_mask,
1721                                 i);
1722
1723                 pool->mcif_wb[i] = &mcif_wb30->base;
1724         }
1725         return true;
1726 }
1727
1728 static struct display_stream_compressor *dcn31_dsc_create(
1729         struct dc_context *ctx, uint32_t inst)
1730 {
1731         struct dcn20_dsc *dsc =
1732                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1733
1734         if (!dsc) {
1735                 BREAK_TO_DEBUGGER();
1736                 return NULL;
1737         }
1738
1739         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1740         return &dsc->base;
1741 }
1742
1743 static void dcn31_destroy_resource_pool(struct resource_pool **pool)
1744 {
1745         struct dcn31_resource_pool *dcn31_pool = TO_DCN31_RES_POOL(*pool);
1746
1747         dcn31_resource_destruct(dcn31_pool);
1748         kfree(dcn31_pool);
1749         *pool = NULL;
1750 }
1751
1752 static struct clock_source *dcn31_clock_source_create(
1753                 struct dc_context *ctx,
1754                 struct dc_bios *bios,
1755                 enum clock_source_id id,
1756                 const struct dce110_clk_src_regs *regs,
1757                 bool dp_clk_src)
1758 {
1759         struct dce110_clk_src *clk_src =
1760                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1761
1762         if (!clk_src)
1763                 return NULL;
1764
1765         if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1766                         regs, &cs_shift, &cs_mask)) {
1767                 clk_src->base.dp_clk_src = dp_clk_src;
1768                 return &clk_src->base;
1769         }
1770
1771         BREAK_TO_DEBUGGER();
1772         return NULL;
1773 }
1774
1775 static bool is_dual_plane(enum surface_pixel_format format)
1776 {
1777         return format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN || format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA;
1778 }
1779
1780 int dcn31_populate_dml_pipes_from_context(
1781         struct dc *dc, struct dc_state *context,
1782         display_e2e_pipe_params_st *pipes,
1783         bool fast_validate)
1784 {
1785         int i, pipe_cnt;
1786         struct resource_context *res_ctx = &context->res_ctx;
1787         struct pipe_ctx *pipe;
1788         bool upscaled = false;
1789
1790         DC_FP_START();
1791         dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1792         DC_FP_END();
1793
1794         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1795                 struct dc_crtc_timing *timing;
1796
1797                 if (!res_ctx->pipe_ctx[i].stream)
1798                         continue;
1799                 pipe = &res_ctx->pipe_ctx[i];
1800                 timing = &pipe->stream->timing;
1801
1802                 if (pipe->plane_state &&
1803                                 (pipe->plane_state->src_rect.height < pipe->plane_state->dst_rect.height ||
1804                                 pipe->plane_state->src_rect.width < pipe->plane_state->dst_rect.width))
1805                         upscaled = true;
1806
1807                 /*
1808                  * Immediate flip can be set dynamically after enabling the plane.
1809                  * We need to require support for immediate flip or underflow can be
1810                  * intermittently experienced depending on peak b/w requirements.
1811                  */
1812                 pipes[pipe_cnt].pipe.src.immediate_flip = true;
1813
1814                 pipes[pipe_cnt].pipe.src.unbounded_req_mode = false;
1815                 pipes[pipe_cnt].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
1816                 pipes[pipe_cnt].pipe.src.gpuvm = true;
1817                 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_luma = 0;
1818                 pipes[pipe_cnt].pipe.src.dcc_fraction_of_zs_req_chroma = 0;
1819                 pipes[pipe_cnt].pipe.dest.vfront_porch = timing->v_front_porch;
1820                 pipes[pipe_cnt].pipe.src.dcc_rate = 3;
1821                 pipes[pipe_cnt].dout.dsc_input_bpc = 0;
1822
1823                 if (pipes[pipe_cnt].dout.dsc_enable) {
1824                         switch (timing->display_color_depth) {
1825                         case COLOR_DEPTH_888:
1826                                 pipes[pipe_cnt].dout.dsc_input_bpc = 8;
1827                                 break;
1828                         case COLOR_DEPTH_101010:
1829                                 pipes[pipe_cnt].dout.dsc_input_bpc = 10;
1830                                 break;
1831                         case COLOR_DEPTH_121212:
1832                                 pipes[pipe_cnt].dout.dsc_input_bpc = 12;
1833                                 break;
1834                         default:
1835                                 ASSERT(0);
1836                                 break;
1837                         }
1838                 }
1839
1840                 pipe_cnt++;
1841         }
1842         context->bw_ctx.dml.ip.det_buffer_size_kbytes = DCN3_1_DEFAULT_DET_SIZE;
1843         dc->config.enable_4to1MPC = false;
1844         if (pipe_cnt == 1 && pipe->plane_state && !dc->debug.disable_z9_mpc) {
1845                 if (is_dual_plane(pipe->plane_state->format)
1846                                 && pipe->plane_state->src_rect.width <= 1920 && pipe->plane_state->src_rect.height <= 1080) {
1847                         dc->config.enable_4to1MPC = true;
1848                 } else if (!is_dual_plane(pipe->plane_state->format) && pipe->plane_state->src_rect.width <= 5120) {
1849                         /* Limit to 5k max to avoid forced pipe split when there is not enough detile for swath */
1850                         context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1851                         pipes[0].pipe.src.unbounded_req_mode = true;
1852                 }
1853         } else if (context->stream_count >= dc->debug.crb_alloc_policy_min_disp_count
1854                         && dc->debug.crb_alloc_policy > DET_SIZE_DEFAULT) {
1855                 context->bw_ctx.dml.ip.det_buffer_size_kbytes = dc->debug.crb_alloc_policy * 64;
1856         } else if (context->stream_count >= 3 && upscaled) {
1857                 context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
1858         }
1859
1860         return pipe_cnt;
1861 }
1862
1863 void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
1864 {
1865         if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) {
1866                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].pstate_latency_us;
1867                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us;
1868                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us;
1869         }
1870 }
1871
1872 static void dcn31_calculate_wm_and_dlg_fp(
1873                 struct dc *dc, struct dc_state *context,
1874                 display_e2e_pipe_params_st *pipes,
1875                 int pipe_cnt,
1876                 int vlevel)
1877 {
1878         int i, pipe_idx;
1879         double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
1880
1881         if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)
1882                 dcfclk = context->bw_ctx.dml.soc.min_dcfclk;
1883
1884         /* We don't recalculate clocks for 0 pipe configs, which can block
1885          * S0i3 as high clocks will block low power states
1886          * Override any clocks that can block S0i3 to min here
1887          */
1888         if (pipe_cnt == 0) {
1889                 context->bw_ctx.bw.dcn.clk.dcfclk_khz = dcfclk; // always should be vlevel 0
1890                 return;
1891         }
1892
1893         pipes[0].clks_cfg.voltage = vlevel;
1894         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
1895         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
1896
1897 #if 0 // TODO
1898         /* Set B:
1899          * TODO
1900          */
1901         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
1902                 if (vlevel == 0) {
1903                         pipes[0].clks_cfg.voltage = 1;
1904                         pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz;
1905                 }
1906                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
1907                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
1908                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
1909         }
1910         context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1911         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1912         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1913         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1914         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1915         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1916         context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1917         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1918         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1919         context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1920
1921         pipes[0].clks_cfg.voltage = vlevel;
1922         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
1923
1924         /* Set C:
1925          * TODO
1926          */
1927         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
1928                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.pstate_latency_us;
1929                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
1930                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
1931         }
1932         context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1933         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1934         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1935         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1936         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1937         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1938         context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1939         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1940         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1941         context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1942
1943         /* Set D:
1944          * TODO
1945          */
1946         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
1947                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
1948                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
1949                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
1950         }
1951         context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1952         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1953         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1954         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1955         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1956         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1957         context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1958         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1959         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1960         context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1961 #endif
1962
1963         /* Set A:
1964          * All clocks min required
1965          *
1966          * Set A calculated last so that following calculations are based on Set A
1967          */
1968         dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1969         context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1970         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1971         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1972         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1973         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_z8_ns = get_wm_z8_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1974         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_z8_ns = get_wm_z8_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1975         context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1976         context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1977         context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1978         context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
1979         /* TODO: remove: */
1980         context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
1981         context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
1982         context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
1983         /* end remove*/
1984
1985         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1986                 if (!context->res_ctx.pipe_ctx[i].stream)
1987                         continue;
1988
1989                 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
1990                 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
1991
1992                 if (dc->config.forced_clocks || dc->debug.max_disp_clk) {
1993                         pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
1994                         pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
1995                 }
1996                 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
1997                         pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
1998                 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
1999                         pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2000
2001                 pipe_idx++;
2002         }
2003
2004         DC_FP_START();
2005         dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2006         DC_FP_END();
2007 }
2008
2009 void dcn31_calculate_wm_and_dlg(
2010                 struct dc *dc, struct dc_state *context,
2011                 display_e2e_pipe_params_st *pipes,
2012                 int pipe_cnt,
2013                 int vlevel)
2014 {
2015         DC_FP_START();
2016         dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
2017         DC_FP_END();
2018 }
2019
2020 bool dcn31_validate_bandwidth(struct dc *dc,
2021                 struct dc_state *context,
2022                 bool fast_validate)
2023 {
2024         bool out = false;
2025
2026         BW_VAL_TRACE_SETUP();
2027
2028         int vlevel = 0;
2029         int pipe_cnt = 0;
2030         display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2031         DC_LOGGER_INIT(dc->ctx->logger);
2032
2033         BW_VAL_TRACE_COUNT();
2034
2035         DC_FP_START();
2036         out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
2037         DC_FP_END();
2038
2039         // Disable fast_validate to set min dcfclk in alculate_wm_and_dlg
2040         if (pipe_cnt == 0)
2041                 fast_validate = false;
2042
2043         if (!out)
2044                 goto validate_fail;
2045
2046         BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2047
2048         if (fast_validate) {
2049                 BW_VAL_TRACE_SKIP(fast);
2050                 goto validate_out;
2051         }
2052
2053         dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2054
2055         BW_VAL_TRACE_END_WATERMARKS();
2056
2057         goto validate_out;
2058
2059 validate_fail:
2060         DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2061                 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2062
2063         BW_VAL_TRACE_SKIP(fail);
2064         out = false;
2065
2066 validate_out:
2067         kfree(pipes);
2068
2069         BW_VAL_TRACE_FINISH();
2070
2071         return out;
2072 }
2073
2074 static struct dc_cap_funcs cap_funcs = {
2075         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
2076 };
2077
2078 void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2079 {
2080         struct clk_limit_table *clk_table = &bw_params->clk_table;
2081         struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
2082         unsigned int i, closest_clk_lvl;
2083         int j;
2084
2085         // Default clock levels are used for diags, which may lead to overclocking.
2086         if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
2087                 int max_dispclk_mhz = 0, max_dppclk_mhz = 0;
2088
2089                 dcn3_1_ip.max_num_otg = dc->res_pool->res_cap->num_timing_generator;
2090                 dcn3_1_ip.max_num_dpp = dc->res_pool->pipe_count;
2091                 dcn3_1_soc.num_chans = bw_params->num_channels;
2092
2093                 ASSERT(clk_table->num_entries);
2094
2095                 /* Prepass to find max clocks independent of voltage level. */
2096                 for (i = 0; i < clk_table->num_entries; ++i) {
2097                         if (clk_table->entries[i].dispclk_mhz > max_dispclk_mhz)
2098                                 max_dispclk_mhz = clk_table->entries[i].dispclk_mhz;
2099                         if (clk_table->entries[i].dppclk_mhz > max_dppclk_mhz)
2100                                 max_dppclk_mhz = clk_table->entries[i].dppclk_mhz;
2101                 }
2102
2103                 for (i = 0; i < clk_table->num_entries; i++) {
2104                         /* loop backwards*/
2105                         for (closest_clk_lvl = 0, j = dcn3_1_soc.num_states - 1; j >= 0; j--) {
2106                                 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
2107                                         closest_clk_lvl = j;
2108                                         break;
2109                                 }
2110                         }
2111
2112                         clock_limits[i].state = i;
2113
2114                         /* Clocks dependent on voltage level. */
2115                         clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
2116                         clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
2117                         clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
2118                         clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->entries[i].wck_ratio;
2119
2120                         /* Clocks independent of voltage level. */
2121                         clock_limits[i].dispclk_mhz = max_dispclk_mhz ? max_dispclk_mhz :
2122                                 dcn3_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
2123
2124                         clock_limits[i].dppclk_mhz = max_dppclk_mhz ? max_dppclk_mhz :
2125                                 dcn3_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
2126
2127                         clock_limits[i].dram_bw_per_chan_gbps = dcn3_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
2128                         clock_limits[i].dscclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
2129                         clock_limits[i].dtbclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
2130                         clock_limits[i].phyclk_d18_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
2131                         clock_limits[i].phyclk_mhz = dcn3_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
2132                 }
2133                 for (i = 0; i < clk_table->num_entries; i++)
2134                         dcn3_1_soc.clock_limits[i] = clock_limits[i];
2135                 if (clk_table->num_entries) {
2136                         dcn3_1_soc.num_states = clk_table->num_entries;
2137                 }
2138         }
2139
2140         dcn3_1_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2141         dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2142
2143         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
2144                 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31);
2145         else
2146                 dml_init_instance(&dc->dml, &dcn3_1_soc, &dcn3_1_ip, DML_PROJECT_DCN31_FPGA);
2147 }
2148
2149 static struct resource_funcs dcn31_res_pool_funcs = {
2150         .destroy = dcn31_destroy_resource_pool,
2151         .link_enc_create = dcn31_link_encoder_create,
2152         .link_enc_create_minimal = dcn31_link_enc_create_minimal,
2153         .link_encs_assign = link_enc_cfg_link_encs_assign,
2154         .link_enc_unassign = link_enc_cfg_link_enc_unassign,
2155         .panel_cntl_create = dcn31_panel_cntl_create,
2156         .validate_bandwidth = dcn31_validate_bandwidth,
2157         .calculate_wm_and_dlg = dcn31_calculate_wm_and_dlg,
2158         .update_soc_for_wm_a = dcn31_update_soc_for_wm_a,
2159         .populate_dml_pipes = dcn31_populate_dml_pipes_from_context,
2160         .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
2161         .add_stream_to_ctx = dcn30_add_stream_to_ctx,
2162         .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2163         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2164         .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
2165         .set_mcif_arb_params = dcn30_set_mcif_arb_params,
2166         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2167         .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
2168         .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
2169         .update_bw_bounding_box = dcn31_update_bw_bounding_box,
2170         .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2171 };
2172
2173 static struct clock_source *dcn30_clock_source_create(
2174                 struct dc_context *ctx,
2175                 struct dc_bios *bios,
2176                 enum clock_source_id id,
2177                 const struct dce110_clk_src_regs *regs,
2178                 bool dp_clk_src)
2179 {
2180         struct dce110_clk_src *clk_src =
2181                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
2182
2183         if (!clk_src)
2184                 return NULL;
2185
2186         if (dcn31_clk_src_construct(clk_src, ctx, bios, id,
2187                         regs, &cs_shift, &cs_mask)) {
2188                 clk_src->base.dp_clk_src = dp_clk_src;
2189                 return &clk_src->base;
2190         }
2191
2192         BREAK_TO_DEBUGGER();
2193         return NULL;
2194 }
2195
2196 static bool dcn31_resource_construct(
2197         uint8_t num_virtual_links,
2198         struct dc *dc,
2199         struct dcn31_resource_pool *pool)
2200 {
2201         int i;
2202         struct dc_context *ctx = dc->ctx;
2203         struct irq_service_init_data init_data;
2204
2205         DC_FP_START();
2206
2207         ctx->dc_bios->regs = &bios_regs;
2208
2209         pool->base.res_cap = &res_cap_dcn31;
2210
2211         pool->base.funcs = &dcn31_res_pool_funcs;
2212
2213         /*************************************************
2214          *  Resource + asic cap harcoding                *
2215          *************************************************/
2216         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2217         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
2218         pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
2219         dc->caps.max_downscale_ratio = 600;
2220         dc->caps.i2c_speed_in_khz = 100;
2221         dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
2222         dc->caps.max_cursor_size = 256;
2223         dc->caps.min_horizontal_blanking_period = 80;
2224         dc->caps.dmdata_alloc_size = 2048;
2225
2226         dc->caps.max_slave_planes = 1;
2227         dc->caps.max_slave_yuv_planes = 1;
2228         dc->caps.max_slave_rgb_planes = 1;
2229         dc->caps.post_blend_color_processing = true;
2230         dc->caps.force_dp_tps4_for_cp2520 = true;
2231         dc->caps.dp_hpo = true;
2232         dc->caps.hdmi_frl_pcon_support = true;
2233         dc->caps.edp_dsc_support = true;
2234         dc->caps.extended_aux_timeout_support = true;
2235         dc->caps.dmcub_support = true;
2236         dc->caps.is_apu = true;
2237         dc->caps.zstate_support = true;
2238
2239         /* Color pipeline capabilities */
2240         dc->caps.color.dpp.dcn_arch = 1;
2241         dc->caps.color.dpp.input_lut_shared = 0;
2242         dc->caps.color.dpp.icsc = 1;
2243         dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2244         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2245         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2246         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2247         dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2248         dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2249         dc->caps.color.dpp.post_csc = 1;
2250         dc->caps.color.dpp.gamma_corr = 1;
2251         dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2252
2253         dc->caps.color.dpp.hw_3d_lut = 1;
2254         dc->caps.color.dpp.ogam_ram = 1;
2255         // no OGAM ROM on DCN301
2256         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2257         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2258         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2259         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2260         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2261         dc->caps.color.dpp.ocsc = 0;
2262
2263         dc->caps.color.mpc.gamut_remap = 1;
2264         dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
2265         dc->caps.color.mpc.ogam_ram = 1;
2266         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2267         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2268         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2269         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2270         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2271         dc->caps.color.mpc.ocsc = 1;
2272
2273         /* Use pipe context based otg sync logic */
2274         dc->config.use_pipe_ctx_sync_logic = true;
2275
2276         /* read VBIOS LTTPR caps */
2277         {
2278                 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2279                         enum bp_result bp_query_result;
2280                         uint8_t is_vbios_lttpr_enable = 0;
2281
2282                         bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2283                         dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2284                 }
2285
2286                 /* interop bit is implicit */
2287                 {
2288                         dc->caps.vbios_lttpr_aware = true;
2289                 }
2290         }
2291
2292         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2293                 dc->debug = debug_defaults_drv;
2294         else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2295                 dc->debug = debug_defaults_diags;
2296         } else
2297                 dc->debug = debug_defaults_diags;
2298         // Init the vm_helper
2299         if (dc->vm_helper)
2300                 vm_helper_init(dc->vm_helper, 16);
2301
2302         /*************************************************
2303          *  Create resources                             *
2304          *************************************************/
2305
2306         /* Clock Sources for Pixel Clock*/
2307         pool->base.clock_sources[DCN31_CLK_SRC_PLL0] =
2308                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2309                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
2310                                 &clk_src_regs[0], false);
2311         pool->base.clock_sources[DCN31_CLK_SRC_PLL1] =
2312                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2313                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
2314                                 &clk_src_regs[1], false);
2315         /*move phypllx_pixclk_resync to dmub next*/
2316         if (dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
2317                 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
2318                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2319                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
2320                                 &clk_src_regs_b0[2], false);
2321                 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
2322                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2323                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
2324                                 &clk_src_regs_b0[3], false);
2325         } else {
2326                 pool->base.clock_sources[DCN31_CLK_SRC_PLL2] =
2327                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2328                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
2329                                 &clk_src_regs[2], false);
2330                 pool->base.clock_sources[DCN31_CLK_SRC_PLL3] =
2331                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2332                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
2333                                 &clk_src_regs[3], false);
2334         }
2335
2336         pool->base.clock_sources[DCN31_CLK_SRC_PLL4] =
2337                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2338                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
2339                                 &clk_src_regs[4], false);
2340
2341         pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2342
2343         /* todo: not reuse phy_pll registers */
2344         pool->base.dp_clock_source =
2345                         dcn31_clock_source_create(ctx, ctx->dc_bios,
2346                                 CLOCK_SOURCE_ID_DP_DTO,
2347                                 &clk_src_regs[0], true);
2348
2349         for (i = 0; i < pool->base.clk_src_count; i++) {
2350                 if (pool->base.clock_sources[i] == NULL) {
2351                         dm_error("DC: failed to create clock sources!\n");
2352                         BREAK_TO_DEBUGGER();
2353                         goto create_fail;
2354                 }
2355         }
2356
2357         /* TODO: DCCG */
2358         pool->base.dccg = dccg31_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2359         if (pool->base.dccg == NULL) {
2360                 dm_error("DC: failed to create dccg!\n");
2361                 BREAK_TO_DEBUGGER();
2362                 goto create_fail;
2363         }
2364
2365         /* TODO: IRQ */
2366         init_data.ctx = dc->ctx;
2367         pool->base.irqs = dal_irq_service_dcn31_create(&init_data);
2368         if (!pool->base.irqs)
2369                 goto create_fail;
2370
2371         /* HUBBUB */
2372         pool->base.hubbub = dcn31_hubbub_create(ctx);
2373         if (pool->base.hubbub == NULL) {
2374                 BREAK_TO_DEBUGGER();
2375                 dm_error("DC: failed to create hubbub!\n");
2376                 goto create_fail;
2377         }
2378
2379         /* HUBPs, DPPs, OPPs and TGs */
2380         for (i = 0; i < pool->base.pipe_count; i++) {
2381                 pool->base.hubps[i] = dcn31_hubp_create(ctx, i);
2382                 if (pool->base.hubps[i] == NULL) {
2383                         BREAK_TO_DEBUGGER();
2384                         dm_error(
2385                                 "DC: failed to create hubps!\n");
2386                         goto create_fail;
2387                 }
2388
2389                 pool->base.dpps[i] = dcn31_dpp_create(ctx, i);
2390                 if (pool->base.dpps[i] == NULL) {
2391                         BREAK_TO_DEBUGGER();
2392                         dm_error(
2393                                 "DC: failed to create dpps!\n");
2394                         goto create_fail;
2395                 }
2396         }
2397
2398         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2399                 pool->base.opps[i] = dcn31_opp_create(ctx, i);
2400                 if (pool->base.opps[i] == NULL) {
2401                         BREAK_TO_DEBUGGER();
2402                         dm_error(
2403                                 "DC: failed to create output pixel processor!\n");
2404                         goto create_fail;
2405                 }
2406         }
2407
2408         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2409                 pool->base.timing_generators[i] = dcn31_timing_generator_create(
2410                                 ctx, i);
2411                 if (pool->base.timing_generators[i] == NULL) {
2412                         BREAK_TO_DEBUGGER();
2413                         dm_error("DC: failed to create tg!\n");
2414                         goto create_fail;
2415                 }
2416         }
2417         pool->base.timing_generator_count = i;
2418
2419         /* PSR */
2420         pool->base.psr = dmub_psr_create(ctx);
2421         if (pool->base.psr == NULL) {
2422                 dm_error("DC: failed to create psr obj!\n");
2423                 BREAK_TO_DEBUGGER();
2424                 goto create_fail;
2425         }
2426
2427         /* ABM */
2428         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2429                 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2430                                 &abm_regs[i],
2431                                 &abm_shift,
2432                                 &abm_mask);
2433                 if (pool->base.multiple_abms[i] == NULL) {
2434                         dm_error("DC: failed to create abm for pipe %d!\n", i);
2435                         BREAK_TO_DEBUGGER();
2436                         goto create_fail;
2437                 }
2438         }
2439
2440         /* MPC and DSC */
2441         pool->base.mpc = dcn31_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2442         if (pool->base.mpc == NULL) {
2443                 BREAK_TO_DEBUGGER();
2444                 dm_error("DC: failed to create mpc!\n");
2445                 goto create_fail;
2446         }
2447
2448         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2449                 pool->base.dscs[i] = dcn31_dsc_create(ctx, i);
2450                 if (pool->base.dscs[i] == NULL) {
2451                         BREAK_TO_DEBUGGER();
2452                         dm_error("DC: failed to create display stream compressor %d!\n", i);
2453                         goto create_fail;
2454                 }
2455         }
2456
2457         /* DWB and MMHUBBUB */
2458         if (!dcn31_dwbc_create(ctx, &pool->base)) {
2459                 BREAK_TO_DEBUGGER();
2460                 dm_error("DC: failed to create dwbc!\n");
2461                 goto create_fail;
2462         }
2463
2464         if (!dcn31_mmhubbub_create(ctx, &pool->base)) {
2465                 BREAK_TO_DEBUGGER();
2466                 dm_error("DC: failed to create mcif_wb!\n");
2467                 goto create_fail;
2468         }
2469
2470         /* AUX and I2C */
2471         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2472                 pool->base.engines[i] = dcn31_aux_engine_create(ctx, i);
2473                 if (pool->base.engines[i] == NULL) {
2474                         BREAK_TO_DEBUGGER();
2475                         dm_error(
2476                                 "DC:failed to create aux engine!!\n");
2477                         goto create_fail;
2478                 }
2479                 pool->base.hw_i2cs[i] = dcn31_i2c_hw_create(ctx, i);
2480                 if (pool->base.hw_i2cs[i] == NULL) {
2481                         BREAK_TO_DEBUGGER();
2482                         dm_error(
2483                                 "DC:failed to create hw i2c!!\n");
2484                         goto create_fail;
2485                 }
2486                 pool->base.sw_i2cs[i] = NULL;
2487         }
2488
2489         if (dc->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP &&
2490             dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0 &&
2491             !dc->debug.dpia_debug.bits.disable_dpia) {
2492                 /* YELLOW CARP B0 has 4 DPIA's */
2493                 pool->base.usb4_dpia_count = 4;
2494         }
2495
2496         /* Audio, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2497         if (!resource_construct(num_virtual_links, dc, &pool->base,
2498                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2499                         &res_create_funcs : &res_create_maximus_funcs)))
2500                         goto create_fail;
2501
2502         /* HW Sequencer and Plane caps */
2503         dcn31_hw_sequencer_construct(dc);
2504
2505         dc->caps.max_planes =  pool->base.pipe_count;
2506
2507         for (i = 0; i < dc->caps.max_planes; ++i)
2508                 dc->caps.planes[i] = plane_cap;
2509
2510         dc->cap_funcs = cap_funcs;
2511
2512         dc->dcn_ip->max_num_dpp = dcn3_1_ip.max_num_dpp;
2513
2514         DC_FP_END();
2515
2516         return true;
2517
2518 create_fail:
2519
2520         DC_FP_END();
2521         dcn31_resource_destruct(pool);
2522
2523         return false;
2524 }
2525
2526 struct resource_pool *dcn31_create_resource_pool(
2527                 const struct dc_init_data *init_data,
2528                 struct dc *dc)
2529 {
2530         struct dcn31_resource_pool *pool =
2531                 kzalloc(sizeof(struct dcn31_resource_pool), GFP_KERNEL);
2532
2533         if (!pool)
2534                 return NULL;
2535
2536         if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool))
2537                 return &pool->base;
2538
2539         BREAK_TO_DEBUGGER();
2540         kfree(pool);
2541         return NULL;
2542 }