2 * Copyright 2020 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
27 #include "dm_services.h"
30 #include "dcn30_init.h"
33 #include "include/irq_service_interface.h"
34 #include "dcn20/dcn20_resource.h"
36 #include "dcn30_resource.h"
38 #include "dcn10/dcn10_ipp.h"
39 #include "dcn30/dcn30_hubbub.h"
40 #include "dcn30/dcn30_mpc.h"
41 #include "dcn30/dcn30_hubp.h"
42 #include "irq/dcn30/irq_service_dcn30.h"
43 #include "dcn30/dcn30_dpp.h"
44 #include "dcn30/dcn30_optc.h"
45 #include "dcn20/dcn20_hwseq.h"
46 #include "dcn30/dcn30_hwseq.h"
47 #include "dce110/dce110_hw_sequencer.h"
48 #include "dcn30/dcn30_opp.h"
49 #include "dcn20/dcn20_dsc.h"
50 #include "dcn30/dcn30_vpg.h"
51 #include "dcn30/dcn30_afmt.h"
52 #include "dcn30/dcn30_dio_stream_encoder.h"
53 #include "dcn30/dcn30_dio_link_encoder.h"
54 #include "dce/dce_clock_source.h"
55 #include "dce/dce_audio.h"
56 #include "dce/dce_hwseq.h"
58 #include "virtual/virtual_stream_encoder.h"
59 #include "dce110/dce110_resource.h"
60 #include "dml/display_mode_vba.h"
61 #include "dcn30/dcn30_dccg.h"
62 #include "dcn10/dcn10_resource.h"
63 #include "dc_link_ddc.h"
64 #include "dce/dce_panel_cntl.h"
66 #include "dcn30/dcn30_dwb.h"
67 #include "dcn30/dcn30_mmhubbub.h"
69 #include "sienna_cichlid_ip_offset.h"
70 #include "dcn/dcn_3_0_0_offset.h"
71 #include "dcn/dcn_3_0_0_sh_mask.h"
73 #include "nbio/nbio_7_4_offset.h"
75 #include "dcn/dpcs_3_0_0_offset.h"
76 #include "dcn/dpcs_3_0_0_sh_mask.h"
78 #include "mmhub/mmhub_2_0_0_offset.h"
79 #include "mmhub/mmhub_2_0_0_sh_mask.h"
81 #include "reg_helper.h"
82 #include "dce/dmub_abm.h"
83 #include "dce/dmub_psr.h"
84 #include "dce/dce_aux.h"
85 #include "dce/dce_i2c.h"
87 #include "dml/dcn30/display_mode_vba_30.h"
88 #include "vm_helper.h"
89 #include "dcn20/dcn20_vmid.h"
90 #include "amdgpu_socbb.h"
92 #define DC_LOGGER_INIT(logger)
94 struct _vcs_dpi_ip_params_st dcn3_0_ip = {
96 .clamp_min_dcfclk = 0,
100 .gpuvm_max_page_table_levels = 4,
101 .hostvm_max_page_table_levels = 4,
102 .hostvm_cached_page_table_levels = 0,
103 .pte_group_size_bytes = 2048,
105 .rob_buffer_size_kbytes = 184,
106 .det_buffer_size_kbytes = 184,
107 .dpte_buffer_size_in_pte_reqs_luma = 84,
108 .pde_proc_buffer_size_64k_reqs = 48,
109 .dpp_output_buffer_pixels = 2560,
110 .opp_output_buffer_lines = 1,
111 .pixel_chunk_size_kbytes = 8,
113 .max_page_table_levels = 2,
114 .pte_chunk_size_kbytes = 2, // ?
115 .meta_chunk_size_kbytes = 2,
116 .writeback_chunk_size_kbytes = 8,
117 .line_buffer_size_bits = 789504,
118 .is_line_buffer_bpp_fixed = 0, // ?
119 .line_buffer_fixed_bpp = 0, // ?
120 .dcc_supported = true,
121 .writeback_interface_buffer_size_kbytes = 90,
122 .writeback_line_buffer_buffer_size = 0,
123 .max_line_buffer_lines = 12,
124 .writeback_luma_buffer_size_kbytes = 12, // writeback_line_buffer_buffer_size = 656640
125 .writeback_chroma_buffer_size_kbytes = 8,
126 .writeback_chroma_line_buffer_width_pixels = 4,
127 .writeback_max_hscl_ratio = 1,
128 .writeback_max_vscl_ratio = 1,
129 .writeback_min_hscl_ratio = 1,
130 .writeback_min_vscl_ratio = 1,
131 .writeback_max_hscl_taps = 1,
132 .writeback_max_vscl_taps = 1,
133 .writeback_line_buffer_luma_buffer_size = 0,
134 .writeback_line_buffer_chroma_buffer_size = 14643,
135 .cursor_buffer_size = 8,
136 .cursor_chunk_size = 2,
140 .max_dchub_pscl_bw_pix_per_clk = 4,
141 .max_pscl_lb_bw_pix_per_clk = 2,
142 .max_lb_vscl_bw_pix_per_clk = 4,
143 .max_vscl_hscl_bw_pix_per_clk = 4,
150 .dispclk_ramp_margin_percent = 1,
151 .underscan_factor = 1.11,
152 .min_vblank_lines = 32,
153 .dppclk_delay_subtotal = 46,
154 .dynamic_metadata_vm_enabled = true,
155 .dppclk_delay_scl_lb_only = 16,
156 .dppclk_delay_scl = 50,
157 .dppclk_delay_cnvc_formatter = 27,
158 .dppclk_delay_cnvc_cursor = 6,
159 .dispclk_delay_subtotal = 119,
160 .dcfclk_cstate_latency = 5.2, // SRExitTime
161 .max_inter_dcn_tile_repeaters = 8,
162 .odm_combine_4to1_supported = true,
164 .xfc_supported = false,
165 .xfc_fill_bw_overhead_percent = 10.0,
166 .xfc_fill_constant_bytes = 0,
167 .gfx7_compat_tiling_supported = 0,
168 .number_of_cursors = 1,
171 struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = {
175 .dispclk_mhz = 562.0,
178 .phyclk_d18_mhz = 667.0,
182 .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */
184 .sr_exit_time_us = 15.5,
185 .sr_enter_plus_exit_time_us = 20,
186 .urgent_latency_us = 4.0,
187 .urgent_latency_pixel_data_only_us = 4.0,
188 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
189 .urgent_latency_vm_data_only_us = 4.0,
190 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
191 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
192 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
193 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
194 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
195 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
196 .max_avg_sdp_bw_use_normal_percent = 60.0,
197 .max_avg_dram_bw_use_normal_percent = 40.0,
198 .writeback_latency_us = 12.0,
199 .max_request_size_bytes = 256,
200 .fabric_datapath_to_dcn_data_return_bytes = 64,
201 .dcn_downspread_percent = 0.5,
202 .downspread_percent = 0.38,
203 .dram_page_open_time_ns = 50.0,
204 .dram_rw_turnaround_time_ns = 17.5,
205 .dram_return_buffer_per_channel_bytes = 8192,
206 .round_trip_ping_latency_dcfclk_cycles = 191,
207 .urgent_out_of_order_return_per_channel_bytes = 4096,
208 .channel_interleave_bytes = 256,
210 .gpuvm_min_page_size_bytes = 4096,
211 .hostvm_min_page_size_bytes = 4096,
212 .dram_clock_change_latency_us = 404,
213 .dummy_pstate_latency_us = 5,
214 .writeback_dram_clock_change_latency_us = 23.0,
215 .return_bus_width_bytes = 64,
216 .dispclk_dppclk_vco_speed_mhz = 3650,
217 .xfc_bus_transport_time_us = 20, // ?
218 .xfc_xbuf_latency_tolerance_us = 4, // ?
219 .use_urgent_burst_bw = 1, // ?
220 .do_urgent_latency_adjustment = true,
221 .urgent_latency_adjustment_fabric_clock_component_us = 1.0,
222 .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
225 enum dcn30_clk_src_array_id {
235 /* begin *********************
236 * macros to expend register list macro defined in HW object header file
240 /* TODO awful hack. fixup dcn20_dwb.h */
242 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
244 #define BASE(seg) BASE_INNER(seg)
246 #define SR(reg_name)\
247 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
250 #define SRI(reg_name, block, id)\
251 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
252 mm ## block ## id ## _ ## reg_name
254 #define SRI2(reg_name, block, id)\
255 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
258 #define SRIR(var_name, reg_name, block, id)\
259 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
260 mm ## block ## id ## _ ## reg_name
262 #define SRII(reg_name, block, id)\
263 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
264 mm ## block ## id ## _ ## reg_name
266 #define SRII_MPC_RMU(reg_name, block, id)\
267 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
268 mm ## block ## id ## _ ## reg_name
270 #define SRII_DWB(reg_name, temp_name, block, id)\
271 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
272 mm ## block ## id ## _ ## temp_name
274 #define DCCG_SRII(reg_name, block, id)\
275 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
276 mm ## block ## id ## _ ## reg_name
278 #define VUPDATE_SRII(reg_name, block, id)\
279 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
280 mm ## reg_name ## _ ## block ## id
283 #define NBIO_BASE_INNER(seg) \
284 NBIO_BASE__INST0_SEG ## seg
286 #define NBIO_BASE(seg) \
289 #define NBIO_SR(reg_name)\
290 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
294 #define MMHUB_BASE_INNER(seg) \
295 MMHUB_BASE__INST0_SEG ## seg
297 #define MMHUB_BASE(seg) \
298 MMHUB_BASE_INNER(seg)
300 #define MMHUB_SR(reg_name)\
301 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
305 #define CLK_BASE_INNER(seg) \
306 CLK_BASE__INST0_SEG ## seg
308 #define CLK_BASE(seg) \
311 #define CLK_SRI(reg_name, block, inst)\
312 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
313 mm ## block ## _ ## inst ## _ ## reg_name
316 static const struct bios_registers bios_regs = {
317 NBIO_SR(BIOS_SCRATCH_3),
318 NBIO_SR(BIOS_SCRATCH_6)
321 #define clk_src_regs(index, pllid)\
323 CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
326 static const struct dce110_clk_src_regs clk_src_regs[] = {
335 static const struct dce110_clk_src_shift cs_shift = {
336 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
339 static const struct dce110_clk_src_mask cs_mask = {
340 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
343 #define abm_regs(id)\
345 ABM_DCN30_REG_LIST(id)\
348 static const struct dce_abm_registers abm_regs[] = {
357 static const struct dce_abm_shift abm_shift = {
358 ABM_MASK_SH_LIST_DCN30(__SHIFT)
361 static const struct dce_abm_mask abm_mask = {
362 ABM_MASK_SH_LIST_DCN30(_MASK)
367 #define audio_regs(id)\
369 AUD_COMMON_REG_LIST(id)\
372 static const struct dce_audio_registers audio_regs[] = {
382 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
383 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
384 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
385 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
387 static const struct dce_audio_shift audio_shift = {
388 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
391 static const struct dce_audio_mask audio_mask = {
392 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
395 #define vpg_regs(id)\
397 VPG_DCN3_REG_LIST(id)\
400 static const struct dcn30_vpg_registers vpg_regs[] = {
410 static const struct dcn30_vpg_shift vpg_shift = {
411 DCN3_VPG_MASK_SH_LIST(__SHIFT)
414 static const struct dcn30_vpg_mask vpg_mask = {
415 DCN3_VPG_MASK_SH_LIST(_MASK)
418 #define afmt_regs(id)\
420 AFMT_DCN3_REG_LIST(id)\
423 static const struct dcn30_afmt_registers afmt_regs[] = {
433 static const struct dcn30_afmt_shift afmt_shift = {
434 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
437 static const struct dcn30_afmt_mask afmt_mask = {
438 DCN3_AFMT_MASK_SH_LIST(_MASK)
441 #define stream_enc_regs(id)\
443 SE_DCN3_REG_LIST(id)\
446 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
455 static const struct dcn10_stream_encoder_shift se_shift = {
456 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
459 static const struct dcn10_stream_encoder_mask se_mask = {
460 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
464 #define aux_regs(id)\
466 DCN2_AUX_REG_LIST(id)\
469 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
478 #define hpd_regs(id)\
483 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
492 #define link_regs(id, phyid)\
494 LE_DCN3_REG_LIST(id), \
495 UNIPHY_DCN2_REG_LIST(phyid), \
496 DPCS_DCN2_REG_LIST(id), \
497 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
500 static const struct dce110_aux_registers_shift aux_shift = {
501 DCN_AUX_MASK_SH_LIST(__SHIFT)
504 static const struct dce110_aux_registers_mask aux_mask = {
505 DCN_AUX_MASK_SH_LIST(_MASK)
508 static const struct dcn10_link_enc_registers link_enc_regs[] = {
517 static const struct dcn10_link_enc_shift le_shift = {
518 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),\
519 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
522 static const struct dcn10_link_enc_mask le_mask = {
523 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),\
524 DPCS_DCN2_MASK_SH_LIST(_MASK)
528 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
529 { DCN_PANEL_CNTL_REG_LIST() }
532 static const struct dce_panel_cntl_shift panel_cntl_shift = {
533 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
536 static const struct dce_panel_cntl_mask panel_cntl_mask = {
537 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
540 #define dpp_regs(id)\
542 DPP_REG_LIST_DCN30(id),\
545 static const struct dcn3_dpp_registers dpp_regs[] = {
554 static const struct dcn3_dpp_shift tf_shift = {
555 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
558 static const struct dcn3_dpp_mask tf_mask = {
559 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
562 #define opp_regs(id)\
564 OPP_REG_LIST_DCN30(id),\
567 static const struct dcn20_opp_registers opp_regs[] = {
576 static const struct dcn20_opp_shift opp_shift = {
577 OPP_MASK_SH_LIST_DCN20(__SHIFT)
580 static const struct dcn20_opp_mask opp_mask = {
581 OPP_MASK_SH_LIST_DCN20(_MASK)
584 #define aux_engine_regs(id)\
586 AUX_COMMON_REG_LIST0(id), \
589 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
592 static const struct dce110_aux_registers aux_engine_regs[] = {
601 #define dwbc_regs_dcn3(id)\
603 DWBC_COMMON_REG_LIST_DCN30(id),\
606 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
610 static const struct dcn30_dwbc_shift dwbc30_shift = {
611 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
614 static const struct dcn30_dwbc_mask dwbc30_mask = {
615 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
618 #define mcif_wb_regs_dcn3(id)\
620 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
623 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
627 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
628 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
631 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
632 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
635 #define dsc_regsDCN20(id)\
637 DSC_REG_LIST_DCN20(id)\
640 static const struct dcn20_dsc_registers dsc_regs[] = {
649 static const struct dcn20_dsc_shift dsc_shift = {
650 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
653 static const struct dcn20_dsc_mask dsc_mask = {
654 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
657 static const struct dcn30_mpc_registers mpc_regs = {
658 MPC_REG_LIST_DCN3_0(0),
659 MPC_REG_LIST_DCN3_0(1),
660 MPC_REG_LIST_DCN3_0(2),
661 MPC_REG_LIST_DCN3_0(3),
662 MPC_REG_LIST_DCN3_0(4),
663 MPC_REG_LIST_DCN3_0(5),
664 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
665 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
666 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
667 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
668 MPC_OUT_MUX_REG_LIST_DCN3_0(4),
669 MPC_OUT_MUX_REG_LIST_DCN3_0(5),
670 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
671 MPC_RMU_REG_LIST_DCN3AG(0),
672 MPC_RMU_REG_LIST_DCN3AG(1),
673 MPC_RMU_REG_LIST_DCN3AG(2),
674 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
677 static const struct dcn30_mpc_shift mpc_shift = {
678 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
681 static const struct dcn30_mpc_mask mpc_mask = {
682 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
685 #define optc_regs(id)\
686 [id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)}
689 static const struct dcn_optc_registers optc_regs[] = {
698 static const struct dcn_optc_shift optc_shift = {
699 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
702 static const struct dcn_optc_mask optc_mask = {
703 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
706 #define hubp_regs(id)\
708 HUBP_REG_LIST_DCN30(id)\
711 static const struct dcn_hubp2_registers hubp_regs[] = {
720 static const struct dcn_hubp2_shift hubp_shift = {
721 HUBP_MASK_SH_LIST_DCN30(__SHIFT)
724 static const struct dcn_hubp2_mask hubp_mask = {
725 HUBP_MASK_SH_LIST_DCN30(_MASK)
728 static const struct dcn_hubbub_registers hubbub_reg = {
729 HUBBUB_REG_LIST_DCN30(0)
732 static const struct dcn_hubbub_shift hubbub_shift = {
733 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
736 static const struct dcn_hubbub_mask hubbub_mask = {
737 HUBBUB_MASK_SH_LIST_DCN30(_MASK)
740 static const struct dccg_registers dccg_regs = {
741 DCCG_REG_LIST_DCN30()
744 static const struct dccg_shift dccg_shift = {
745 DCCG_MASK_SH_LIST_DCN3(__SHIFT)
748 static const struct dccg_mask dccg_mask = {
749 DCCG_MASK_SH_LIST_DCN3(_MASK)
752 static const struct dce_hwseq_registers hwseq_reg = {
753 HWSEQ_DCN30_REG_LIST()
756 static const struct dce_hwseq_shift hwseq_shift = {
757 HWSEQ_DCN30_MASK_SH_LIST(__SHIFT)
760 static const struct dce_hwseq_mask hwseq_mask = {
761 HWSEQ_DCN30_MASK_SH_LIST(_MASK)
763 #define vmid_regs(id)\
765 DCN20_VMID_REG_LIST(id)\
768 static const struct dcn_vmid_registers vmid_regs[] = {
787 static const struct dcn20_vmid_shift vmid_shifts = {
788 DCN20_VMID_MASK_SH_LIST(__SHIFT)
791 static const struct dcn20_vmid_mask vmid_masks = {
792 DCN20_VMID_MASK_SH_LIST(_MASK)
795 static const struct resource_caps res_cap_dcn3 = {
796 .num_timing_generator = 6,
798 .num_video_plane = 6,
800 .num_stream_encoder = 6,
809 static const struct dc_plane_cap plane_cap = {
810 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
811 .blends_with_above = true,
812 .blends_with_below = true,
813 .per_pixel_alpha = true,
815 .pixel_format_support = {
823 .max_upscale_factor = {
829 /* 6:1 downscaling ratio: 1000/6 = 166.666 */
830 .max_downscale_factor = {
837 static const struct dc_debug_options debug_defaults_drv = {
838 .disable_dmcu = true, //No DMCU on DCN30
839 .force_abm_enable = false,
840 .timing_trace = false,
842 .disable_pplib_clock_request = true,
843 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
844 .force_single_disp_pipe_split = false,
845 .disable_dcc = DCC_ENABLE,
847 .performance_trace = false,
848 .max_downscale_src_width = 7680,/*upto 8K*/
849 .disable_pplib_wm_range = false,
850 .scl_reset_length10 = true,
851 .sanity_checks = false,
852 .underflow_assert_delay_us = 0xFFFFFFFF,
853 .dwb_fi_phase = -1, // -1 = disable,
854 .dmub_command_table = true,
855 .disable_psr = false,
859 static const struct dc_debug_options debug_defaults_diags = {
860 .disable_dmcu = true, //No dmcu on DCN30
861 .force_abm_enable = false,
862 .timing_trace = true,
864 .disable_dpp_power_gate = true,
865 .disable_hubp_power_gate = true,
866 .disable_clock_gate = true,
867 .disable_pplib_clock_request = true,
868 .disable_pplib_wm_range = true,
869 .disable_stutter = false,
870 .scl_reset_length10 = true,
871 .dwb_fi_phase = -1, // -1 = disable
872 .dmub_command_table = true,
874 .enable_tri_buf = true,
878 static void dcn30_dpp_destroy(struct dpp **dpp)
880 kfree(TO_DCN20_DPP(*dpp));
884 static struct dpp *dcn30_dpp_create(
885 struct dc_context *ctx,
888 struct dcn3_dpp *dpp =
889 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
894 if (dpp3_construct(dpp, ctx, inst,
895 &dpp_regs[inst], &tf_shift, &tf_mask))
903 static struct output_pixel_processor *dcn30_opp_create(
904 struct dc_context *ctx, uint32_t inst)
906 struct dcn20_opp *opp =
907 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
914 dcn20_opp_construct(opp, ctx, inst,
915 &opp_regs[inst], &opp_shift, &opp_mask);
919 static struct dce_aux *dcn30_aux_engine_create(
920 struct dc_context *ctx,
923 struct aux_engine_dce110 *aux_engine =
924 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
929 dce110_aux_engine_construct(aux_engine, ctx, inst,
930 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
931 &aux_engine_regs[inst],
934 ctx->dc->caps.extended_aux_timeout_support);
936 return &aux_engine->base;
939 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
941 static const struct dce_i2c_registers i2c_hw_regs[] = {
950 static const struct dce_i2c_shift i2c_shifts = {
951 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
954 static const struct dce_i2c_mask i2c_masks = {
955 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
958 static struct dce_i2c_hw *dcn30_i2c_hw_create(
959 struct dc_context *ctx,
962 struct dce_i2c_hw *dce_i2c_hw =
963 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
968 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
969 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
974 static struct mpc *dcn30_mpc_create(
975 struct dc_context *ctx,
979 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
985 dcn30_mpc_construct(mpc30, ctx,
995 static struct hubbub *dcn30_hubbub_create(struct dc_context *ctx)
999 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1005 hubbub3_construct(hubbub3, ctx,
1011 for (i = 0; i < res_cap_dcn3.num_vmid; i++) {
1012 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1016 vmid->regs = &vmid_regs[i];
1017 vmid->shifts = &vmid_shifts;
1018 vmid->masks = &vmid_masks;
1021 return &hubbub3->base;
1024 static struct timing_generator *dcn30_timing_generator_create(
1025 struct dc_context *ctx,
1028 struct optc *tgn10 =
1029 kzalloc(sizeof(struct optc), GFP_KERNEL);
1034 tgn10->base.inst = instance;
1035 tgn10->base.ctx = ctx;
1037 tgn10->tg_regs = &optc_regs[instance];
1038 tgn10->tg_shift = &optc_shift;
1039 tgn10->tg_mask = &optc_mask;
1041 dcn30_timing_generator_init(tgn10);
1043 return &tgn10->base;
1046 static const struct encoder_feature_support link_enc_feature = {
1047 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1048 .max_hdmi_pixel_clock = 600000,
1049 .hdmi_ycbcr420_supported = true,
1050 .dp_ycbcr420_supported = true,
1051 .fec_supported = true,
1052 .flags.bits.IS_HBR2_CAPABLE = true,
1053 .flags.bits.IS_HBR3_CAPABLE = true,
1054 .flags.bits.IS_TPS3_CAPABLE = true,
1055 .flags.bits.IS_TPS4_CAPABLE = true
1058 static struct link_encoder *dcn30_link_encoder_create(
1059 const struct encoder_init_data *enc_init_data)
1061 struct dcn20_link_encoder *enc20 =
1062 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1067 dcn30_link_encoder_construct(enc20,
1070 &link_enc_regs[enc_init_data->transmitter],
1071 &link_enc_aux_regs[enc_init_data->channel - 1],
1072 &link_enc_hpd_regs[enc_init_data->hpd_source],
1076 return &enc20->enc10.base;
1079 static struct panel_cntl *dcn30_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1081 struct dce_panel_cntl *panel_cntl =
1082 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
1087 dce_panel_cntl_construct(panel_cntl,
1089 &panel_cntl_regs[init_data->inst],
1093 return &panel_cntl->base;
1096 static void read_dce_straps(
1097 struct dc_context *ctx,
1098 struct resource_straps *straps)
1100 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1101 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1105 static struct audio *dcn30_create_audio(
1106 struct dc_context *ctx, unsigned int inst)
1108 return dce_audio_create(ctx, inst,
1109 &audio_regs[inst], &audio_shift, &audio_mask);
1112 static struct vpg *dcn30_vpg_create(
1113 struct dc_context *ctx,
1116 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
1121 vpg3_construct(vpg3, ctx, inst,
1129 static struct afmt *dcn30_afmt_create(
1130 struct dc_context *ctx,
1133 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1138 afmt3_construct(afmt3, ctx, inst,
1143 return &afmt3->base;
1146 static struct stream_encoder *dcn30_stream_encoder_create(enum engine_id eng_id,
1147 struct dc_context *ctx)
1149 struct dcn10_stream_encoder *enc1;
1155 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1156 if (eng_id <= ENGINE_ID_DIGF) {
1162 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1163 vpg = dcn30_vpg_create(ctx, vpg_inst);
1164 afmt = dcn30_afmt_create(ctx, afmt_inst);
1166 if (!enc1 || !vpg || !afmt) {
1173 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1175 &stream_enc_regs[eng_id],
1176 &se_shift, &se_mask);
1181 static struct dce_hwseq *dcn30_hwseq_create(struct dc_context *ctx)
1183 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1187 hws->regs = &hwseq_reg;
1188 hws->shifts = &hwseq_shift;
1189 hws->masks = &hwseq_mask;
1193 static const struct resource_create_funcs res_create_funcs = {
1194 .read_dce_straps = read_dce_straps,
1195 .create_audio = dcn30_create_audio,
1196 .create_stream_encoder = dcn30_stream_encoder_create,
1197 .create_hwseq = dcn30_hwseq_create,
1200 static const struct resource_create_funcs res_create_maximus_funcs = {
1201 .read_dce_straps = NULL,
1202 .create_audio = NULL,
1203 .create_stream_encoder = NULL,
1204 .create_hwseq = dcn30_hwseq_create,
1207 static void dcn30_resource_destruct(struct dcn30_resource_pool *pool)
1211 for (i = 0; i < pool->base.stream_enc_count; i++) {
1212 if (pool->base.stream_enc[i] != NULL) {
1213 if (pool->base.stream_enc[i]->vpg != NULL) {
1214 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1215 pool->base.stream_enc[i]->vpg = NULL;
1217 if (pool->base.stream_enc[i]->afmt != NULL) {
1218 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1219 pool->base.stream_enc[i]->afmt = NULL;
1221 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1222 pool->base.stream_enc[i] = NULL;
1226 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1227 if (pool->base.dscs[i] != NULL)
1228 dcn20_dsc_destroy(&pool->base.dscs[i]);
1231 if (pool->base.mpc != NULL) {
1232 kfree(TO_DCN20_MPC(pool->base.mpc));
1233 pool->base.mpc = NULL;
1235 if (pool->base.hubbub != NULL) {
1236 kfree(pool->base.hubbub);
1237 pool->base.hubbub = NULL;
1239 for (i = 0; i < pool->base.pipe_count; i++) {
1240 if (pool->base.dpps[i] != NULL)
1241 dcn30_dpp_destroy(&pool->base.dpps[i]);
1243 if (pool->base.ipps[i] != NULL)
1244 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1246 if (pool->base.hubps[i] != NULL) {
1247 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1248 pool->base.hubps[i] = NULL;
1251 if (pool->base.irqs != NULL) {
1252 dal_irq_service_destroy(&pool->base.irqs);
1256 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1257 if (pool->base.engines[i] != NULL)
1258 dce110_engine_destroy(&pool->base.engines[i]);
1259 if (pool->base.hw_i2cs[i] != NULL) {
1260 kfree(pool->base.hw_i2cs[i]);
1261 pool->base.hw_i2cs[i] = NULL;
1263 if (pool->base.sw_i2cs[i] != NULL) {
1264 kfree(pool->base.sw_i2cs[i]);
1265 pool->base.sw_i2cs[i] = NULL;
1269 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1270 if (pool->base.opps[i] != NULL)
1271 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1274 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1275 if (pool->base.timing_generators[i] != NULL) {
1276 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1277 pool->base.timing_generators[i] = NULL;
1281 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1282 if (pool->base.dwbc[i] != NULL) {
1283 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1284 pool->base.dwbc[i] = NULL;
1286 if (pool->base.mcif_wb[i] != NULL) {
1287 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1288 pool->base.mcif_wb[i] = NULL;
1292 for (i = 0; i < pool->base.audio_count; i++) {
1293 if (pool->base.audios[i])
1294 dce_aud_destroy(&pool->base.audios[i]);
1297 for (i = 0; i < pool->base.clk_src_count; i++) {
1298 if (pool->base.clock_sources[i] != NULL) {
1299 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1300 pool->base.clock_sources[i] = NULL;
1304 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1305 if (pool->base.mpc_lut[i] != NULL) {
1306 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1307 pool->base.mpc_lut[i] = NULL;
1309 if (pool->base.mpc_shaper[i] != NULL) {
1310 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1311 pool->base.mpc_shaper[i] = NULL;
1315 if (pool->base.dp_clock_source != NULL) {
1316 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1317 pool->base.dp_clock_source = NULL;
1320 for (i = 0; i < pool->base.pipe_count; i++) {
1321 if (pool->base.multiple_abms[i] != NULL)
1322 dce_abm_destroy(&pool->base.multiple_abms[i]);
1325 if (pool->base.psr != NULL)
1326 dmub_psr_destroy(&pool->base.psr);
1328 if (pool->base.dccg != NULL)
1329 dcn_dccg_destroy(&pool->base.dccg);
1331 if (pool->base.oem_device != NULL)
1332 dal_ddc_service_destroy(&pool->base.oem_device);
1335 static struct hubp *dcn30_hubp_create(
1336 struct dc_context *ctx,
1339 struct dcn20_hubp *hubp2 =
1340 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1345 if (hubp3_construct(hubp2, ctx, inst,
1346 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1347 return &hubp2->base;
1349 BREAK_TO_DEBUGGER();
1354 static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1357 uint32_t pipe_count = pool->res_cap->num_dwb;
1359 for (i = 0; i < pipe_count; i++) {
1360 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1364 dm_error("DC: failed to create dwbc30!\n");
1368 dcn30_dwbc_construct(dwbc30, ctx,
1374 pool->dwbc[i] = &dwbc30->base;
1379 static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1382 uint32_t pipe_count = pool->res_cap->num_dwb;
1384 for (i = 0; i < pipe_count; i++) {
1385 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1389 dm_error("DC: failed to create mcif_wb30!\n");
1393 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1399 pool->mcif_wb[i] = &mcif_wb30->base;
1404 static struct display_stream_compressor *dcn30_dsc_create(
1405 struct dc_context *ctx, uint32_t inst)
1407 struct dcn20_dsc *dsc =
1408 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1411 BREAK_TO_DEBUGGER();
1415 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1419 enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1422 return dcn20_add_stream_to_ctx(dc, new_ctx, dc_stream);
1425 static void dcn30_destroy_resource_pool(struct resource_pool **pool)
1427 struct dcn30_resource_pool *dcn30_pool = TO_DCN30_RES_POOL(*pool);
1429 dcn30_resource_destruct(dcn30_pool);
1434 static struct clock_source *dcn30_clock_source_create(
1435 struct dc_context *ctx,
1436 struct dc_bios *bios,
1437 enum clock_source_id id,
1438 const struct dce110_clk_src_regs *regs,
1441 struct dce110_clk_src *clk_src =
1442 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1447 if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1448 regs, &cs_shift, &cs_mask)) {
1449 clk_src->base.dp_clk_src = dp_clk_src;
1450 return &clk_src->base;
1453 BREAK_TO_DEBUGGER();
1457 int dcn30_populate_dml_pipes_from_context(
1458 struct dc *dc, struct dc_state *context,
1459 display_e2e_pipe_params_st *pipes,
1463 struct resource_context *res_ctx = &context->res_ctx;
1465 dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1467 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1468 if (!res_ctx->pipe_ctx[i].stream)
1471 pipes[pipe_cnt++].pipe.scale_ratio_depth.lb_depth =
1478 void dcn30_populate_dml_writeback_from_context(
1479 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1482 double max_calc_writeback_dispclk;
1483 double writeback_dispclk;
1484 struct writeback_st dout_wb;
1486 for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1487 struct dc_stream_state *stream = res_ctx->pipe_ctx[i].stream;
1491 max_calc_writeback_dispclk = 0;
1493 /* Set writeback information */
1494 pipes[pipe_cnt].dout.wb_enable = 0;
1495 pipes[pipe_cnt].dout.num_active_wb = 0;
1496 for (j = 0; j < stream->num_wb_info; j++) {
1497 struct dc_writeback_info *wb_info = &stream->writeback_info[j];
1499 if (wb_info->wb_enabled && wb_info->writeback_source_plane &&
1500 (wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) {
1501 pipes[pipe_cnt].dout.wb_enable = 1;
1502 pipes[pipe_cnt].dout.num_active_wb++;
1503 dout_wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_en ?
1504 wb_info->dwb_params.cnv_params.crop_height :
1505 wb_info->dwb_params.cnv_params.src_height;
1506 dout_wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_en ?
1507 wb_info->dwb_params.cnv_params.crop_width :
1508 wb_info->dwb_params.cnv_params.src_width;
1509 dout_wb.wb_dst_width = wb_info->dwb_params.dest_width;
1510 dout_wb.wb_dst_height = wb_info->dwb_params.dest_height;
1512 /* For IP that doesn't support WB scaling, set h/v taps to 1 to avoid DML validation failure */
1513 if (dc->dml.ip.writeback_max_hscl_taps > 1) {
1514 dout_wb.wb_htaps_luma = wb_info->dwb_params.scaler_taps.h_taps;
1515 dout_wb.wb_vtaps_luma = wb_info->dwb_params.scaler_taps.v_taps;
1517 dout_wb.wb_htaps_luma = 1;
1518 dout_wb.wb_vtaps_luma = 1;
1520 dout_wb.wb_htaps_chroma = 0;
1521 dout_wb.wb_vtaps_chroma = 0;
1522 dout_wb.wb_hratio = wb_info->dwb_params.cnv_params.crop_en ?
1523 (double)wb_info->dwb_params.cnv_params.crop_width /
1524 (double)wb_info->dwb_params.dest_width :
1525 (double)wb_info->dwb_params.cnv_params.src_width /
1526 (double)wb_info->dwb_params.dest_width;
1527 dout_wb.wb_vratio = wb_info->dwb_params.cnv_params.crop_en ?
1528 (double)wb_info->dwb_params.cnv_params.crop_height /
1529 (double)wb_info->dwb_params.dest_height :
1530 (double)wb_info->dwb_params.cnv_params.src_height /
1531 (double)wb_info->dwb_params.dest_height;
1532 if (wb_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB ||
1533 wb_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA)
1534 dout_wb.wb_pixel_format = dm_444_64;
1536 dout_wb.wb_pixel_format = dm_444_32;
1538 /* Workaround for cases where multiple writebacks are connected to same plane
1539 * In which case, need to compute worst case and set the associated writeback parameters
1540 * This workaround is necessary due to DML computation assuming only 1 set of writeback
1541 * parameters per pipe
1543 writeback_dispclk = dml30_CalculateWriteBackDISPCLK(
1544 dout_wb.wb_pixel_format,
1545 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz,
1548 dout_wb.wb_htaps_luma,
1549 dout_wb.wb_vtaps_luma,
1550 dout_wb.wb_src_width,
1551 dout_wb.wb_dst_width,
1552 pipes[pipe_cnt].pipe.dest.htotal,
1553 dc->current_state->bw_ctx.dml.ip.writeback_line_buffer_buffer_size);
1555 if (writeback_dispclk > max_calc_writeback_dispclk) {
1556 max_calc_writeback_dispclk = writeback_dispclk;
1557 pipes[pipe_cnt].dout.wb = dout_wb;
1567 unsigned int dcn30_calc_max_scaled_time(
1568 unsigned int time_per_pixel,
1569 enum mmhubbub_wbif_mode mode,
1570 unsigned int urgent_watermark)
1572 unsigned int time_per_byte = 0;
1573 unsigned int total_free_entry = 0xb40;
1574 unsigned int buf_lh_capability;
1575 unsigned int max_scaled_time;
1577 if (mode == PACKED_444) /* packed mode 32 bpp */
1578 time_per_byte = time_per_pixel/4;
1579 else if (mode == PACKED_444_FP16) /* packed mode 64 bpp */
1580 time_per_byte = time_per_pixel/8;
1582 if (time_per_byte == 0)
1585 buf_lh_capability = (total_free_entry*time_per_byte*32) >> 6; /* time_per_byte is in u6.6*/
1586 max_scaled_time = buf_lh_capability - urgent_watermark;
1587 return max_scaled_time;
1590 void dcn30_set_mcif_arb_params(
1592 struct dc_state *context,
1593 display_e2e_pipe_params_st *pipes,
1596 enum mmhubbub_wbif_mode wbif_mode;
1597 struct display_mode_lib *dml = &context->bw_ctx.dml;
1598 struct mcif_arb_params *wb_arb_params;
1599 int i, j, k, dwb_pipe;
1601 /* Writeback MCIF_WB arbitration parameters */
1603 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1605 if (!context->res_ctx.pipe_ctx[i].stream)
1608 for (j = 0; j < MAX_DWB_PIPES; j++) {
1609 struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j];
1611 if (writeback_info->wb_enabled == false)
1614 //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
1615 wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
1617 if (writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB ||
1618 writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA)
1619 wbif_mode = PACKED_444_FP16;
1621 wbif_mode = PACKED_444;
1623 for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
1624 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000;
1625 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
1627 wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* time_per_pixel should be in u6.6 format */
1628 wb_arb_params->slice_lines = 32;
1629 wb_arb_params->arbitration_slice = 2; /* irrelevant since there is no YUV output */
1630 wb_arb_params->max_scaled_time = dcn30_calc_max_scaled_time(wb_arb_params->time_per_pixel,
1632 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
1633 wb_arb_params->dram_speed_change_duration = dml->vba.WritebackAllowDRAMClockChangeEndPosition[j] * pipes[0].clks_cfg.refclk_mhz; /* num_clock_cycles = us * MHz */
1637 if (dwb_pipe >= MAX_DWB_PIPES)
1640 if (dwb_pipe >= MAX_DWB_PIPES)
1646 static struct dc_cap_funcs cap_funcs = {
1647 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1650 bool dcn30_acquire_post_bldn_3dlut(
1651 struct resource_context *res_ctx,
1652 const struct resource_pool *pool,
1654 struct dc_3dlut **lut,
1655 struct dc_transfer_func **shaper)
1659 union dc_3dlut_state *state;
1661 ASSERT(*lut == NULL && *shaper == NULL);
1665 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1666 if (!res_ctx->is_mpc_3dlut_acquired[i]) {
1667 *lut = pool->mpc_lut[i];
1668 *shaper = pool->mpc_shaper[i];
1669 state = &pool->mpc_lut[i]->state;
1670 res_ctx->is_mpc_3dlut_acquired[i] = true;
1671 state->bits.rmu_idx_valid = 1;
1672 state->bits.rmu_mux_num = i;
1673 if (state->bits.rmu_mux_num == 0)
1674 state->bits.mpc_rmu0_mux = mpcc_id;
1675 else if (state->bits.rmu_mux_num == 1)
1676 state->bits.mpc_rmu1_mux = mpcc_id;
1677 else if (state->bits.rmu_mux_num == 2)
1678 state->bits.mpc_rmu2_mux = mpcc_id;
1686 bool dcn30_release_post_bldn_3dlut(
1687 struct resource_context *res_ctx,
1688 const struct resource_pool *pool,
1689 struct dc_3dlut **lut,
1690 struct dc_transfer_func **shaper)
1695 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1696 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {
1697 res_ctx->is_mpc_3dlut_acquired[i] = false;
1698 pool->mpc_lut[i]->state.raw = 0;
1708 static bool is_soc_bounding_box_valid(struct dc *dc)
1710 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1712 if (ASICREV_IS_SIENNA_CICHLID_P(hw_internal_rev))
1718 static bool init_soc_bounding_box(struct dc *dc,
1719 struct dcn30_resource_pool *pool)
1721 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_0_soc;
1722 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_0_ip;
1724 DC_LOGGER_INIT(dc->ctx->logger);
1726 if (!is_soc_bounding_box_valid(dc)) {
1727 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
1731 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
1732 loaded_ip->max_num_dpp = pool->base.pipe_count;
1733 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
1734 dcn20_patch_bounding_box(dc, loaded_bb);
1736 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
1737 struct bp_soc_bb_info bb_info = {0};
1739 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
1740 if (bb_info.dram_clock_change_latency_100ns > 0)
1741 dcn3_0_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;
1743 if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
1744 dcn3_0_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;
1746 if (bb_info.dram_sr_exit_latency_100ns > 0)
1747 dcn3_0_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
1754 static bool dcn30_split_stream_for_mpc_or_odm(
1755 const struct dc *dc,
1756 struct resource_context *res_ctx,
1757 struct pipe_ctx *pri_pipe,
1758 struct pipe_ctx *sec_pipe,
1761 int pipe_idx = sec_pipe->pipe_idx;
1762 const struct resource_pool *pool = dc->res_pool;
1764 *sec_pipe = *pri_pipe;
1766 sec_pipe->pipe_idx = pipe_idx;
1767 sec_pipe->plane_res.mi = pool->mis[pipe_idx];
1768 sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
1769 sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
1770 sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
1771 sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
1772 sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
1773 sec_pipe->stream_res.dsc = NULL;
1775 if (pri_pipe->next_odm_pipe) {
1776 ASSERT(pri_pipe->next_odm_pipe != sec_pipe);
1777 sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe;
1778 sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe;
1780 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) {
1781 pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe;
1782 sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe;
1784 if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) {
1785 pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe;
1786 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe;
1788 pri_pipe->next_odm_pipe = sec_pipe;
1789 sec_pipe->prev_odm_pipe = pri_pipe;
1791 if (!sec_pipe->top_pipe)
1792 sec_pipe->stream_res.opp = pool->opps[pipe_idx];
1794 sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
1795 if (sec_pipe->stream->timing.flags.DSC == 1) {
1796 dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
1797 ASSERT(sec_pipe->stream_res.dsc);
1798 if (sec_pipe->stream_res.dsc == NULL)
1802 if (pri_pipe->bottom_pipe) {
1803 ASSERT(pri_pipe->bottom_pipe != sec_pipe);
1804 sec_pipe->bottom_pipe = pri_pipe->bottom_pipe;
1805 sec_pipe->bottom_pipe->top_pipe = sec_pipe;
1807 pri_pipe->bottom_pipe = sec_pipe;
1808 sec_pipe->top_pipe = pri_pipe;
1810 ASSERT(pri_pipe->plane_state);
1816 static struct pipe_ctx *dcn30_find_split_pipe(
1818 struct dc_state *context,
1821 struct pipe_ctx *pipe = NULL;
1824 if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
1825 pipe = &context->res_ctx.pipe_ctx[old_index];
1826 pipe->pipe_idx = old_index;
1830 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1831 if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL
1832 && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
1833 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1834 pipe = &context->res_ctx.pipe_ctx[i];
1842 * May need to fix pipes getting tossed from 1 opp to another on flip
1843 * Add for debugging transient underflow during topology updates:
1847 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1848 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1849 pipe = &context->res_ctx.pipe_ctx[i];
1858 noinline bool dcn30_internal_validate_bw(
1860 struct dc_state *context,
1861 display_e2e_pipe_params_st *pipes,
1867 bool repopulate_pipes = false;
1868 int split[MAX_PIPES] = { 0 };
1869 bool merge[MAX_PIPES] = { false };
1870 bool newly_split[MAX_PIPES] = { false };
1871 int pipe_cnt, i, pipe_idx, vlevel;
1872 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1878 dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1879 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1886 dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
1888 if (!fast_validate) {
1890 * DML favors voltage over p-state, but we're more interested in
1891 * supporting p-state over voltage. We can't support p-state in
1892 * prefetch mode > 0 so try capping the prefetch mode to start.
1894 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1895 dm_allow_self_refresh_and_mclk_switch;
1896 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1897 /* This may adjust vlevel and maxMpcComb */
1898 if (vlevel < context->bw_ctx.dml.soc.num_states)
1899 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1901 if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
1902 vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
1904 * If mode is unsupported or there's still no p-state support then
1905 * fall back to favoring voltage.
1907 * We don't actually support prefetch mode 2, so require that we
1908 * at least support prefetch mode 1.
1910 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1911 dm_allow_self_refresh;
1913 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1914 if (vlevel < context->bw_ctx.dml.soc.num_states) {
1915 memset(split, 0, sizeof(split));
1916 memset(merge, 0, sizeof(merge));
1917 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1921 dml_log_mode_support_params(&context->bw_ctx.dml);
1923 if (vlevel == context->bw_ctx.dml.soc.num_states)
1926 if (!dc->config.enable_windowed_mpo_odm) {
1927 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1928 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1929 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
1934 /* We only support full screen mpo with ODM */
1935 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
1936 && pipe->plane_state && mpo_pipe
1937 && memcmp(&mpo_pipe->plane_res.scl_data.recout,
1938 &pipe->plane_res.scl_data.recout,
1939 sizeof(struct rect)) != 0) {
1940 ASSERT(mpo_pipe->plane_state != pipe->plane_state);
1947 /* merge pipes if necessary */
1948 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1949 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1951 /*skip pipes that don't need merging*/
1955 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
1956 if (pipe->prev_odm_pipe) {
1957 /*split off odm pipe*/
1958 pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
1959 if (pipe->next_odm_pipe)
1960 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
1962 pipe->bottom_pipe = NULL;
1963 pipe->next_odm_pipe = NULL;
1964 pipe->plane_state = NULL;
1965 pipe->stream = NULL;
1966 pipe->top_pipe = NULL;
1967 pipe->prev_odm_pipe = NULL;
1968 if (pipe->stream_res.dsc)
1969 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
1970 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1971 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1972 repopulate_pipes = true;
1973 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
1974 struct pipe_ctx *top_pipe = pipe->top_pipe;
1975 struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
1977 top_pipe->bottom_pipe = bottom_pipe;
1979 bottom_pipe->top_pipe = top_pipe;
1981 pipe->top_pipe = NULL;
1982 pipe->bottom_pipe = NULL;
1983 pipe->plane_state = NULL;
1984 pipe->stream = NULL;
1985 memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1986 memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1987 repopulate_pipes = true;
1989 ASSERT(0); /* Should never try to merge master pipe */
1993 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
1994 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1995 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1996 struct pipe_ctx *hsplit_pipe = NULL;
2000 if (!pipe->stream || newly_split[i])
2004 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
2006 if (!pipe->plane_state && !odm)
2011 if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
2012 old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
2013 else if (old_pipe->next_odm_pipe)
2014 old_index = old_pipe->next_odm_pipe->pipe_idx;
2016 if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
2017 old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2018 old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
2019 else if (old_pipe->bottom_pipe &&
2020 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2021 old_index = old_pipe->bottom_pipe->pipe_idx;
2023 hsplit_pipe = dcn30_find_split_pipe(dc, context, old_index);
2024 ASSERT(hsplit_pipe);
2028 if (!dcn30_split_stream_for_mpc_or_odm(
2029 dc, &context->res_ctx,
2030 pipe, hsplit_pipe, odm))
2033 newly_split[hsplit_pipe->pipe_idx] = true;
2034 repopulate_pipes = true;
2036 if (split[i] == 4) {
2037 struct pipe_ctx *pipe_4to1;
2039 if (odm && old_pipe->next_odm_pipe)
2040 old_index = old_pipe->next_odm_pipe->pipe_idx;
2041 else if (!odm && old_pipe->bottom_pipe &&
2042 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2043 old_index = old_pipe->bottom_pipe->pipe_idx;
2046 pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
2050 if (!dcn30_split_stream_for_mpc_or_odm(
2051 dc, &context->res_ctx,
2052 pipe, pipe_4to1, odm))
2054 newly_split[pipe_4to1->pipe_idx] = true;
2056 if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
2057 && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
2058 old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
2059 else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
2060 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
2061 old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2062 old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
2065 pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
2069 if (!dcn30_split_stream_for_mpc_or_odm(
2070 dc, &context->res_ctx,
2071 hsplit_pipe, pipe_4to1, odm))
2073 newly_split[pipe_4to1->pipe_idx] = true;
2076 dcn20_build_mapped_resource(dc, context, pipe->stream);
2079 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2080 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2082 if (pipe->plane_state) {
2083 if (!resource_build_scaling_params(pipe))
2088 /* Actual dsc count per stream dsc validation*/
2089 if (!dcn20_validate_dsc(dc, context)) {
2090 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
2094 if (repopulate_pipes)
2095 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
2096 *vlevel_out = vlevel;
2097 *pipe_cnt_out = pipe_cnt;
2110 * This must be noinline to ensure anything that deals with FP registers
2111 * is contained within this call; previously our compiling with hard-float
2112 * would result in fp instructions being emitted outside of the boundaries
2113 * of the DC_FP_START/END macros, which makes sense as the compiler has no
2114 * idea about what is wrapped and what is not
2116 * This is largely just a workaround to avoid breakage introduced with 5.6,
2117 * ideally all fp-using code should be moved into its own file, only that
2118 * should be compiled with hard-float, and all code exported from there
2119 * should be strictly wrapped with DC_FP_START/END
2121 static noinline void dcn30_calculate_wm_and_dlg_fp(
2122 struct dc *dc, struct dc_state *context,
2123 display_e2e_pipe_params_st *pipes,
2127 int maxMpcComb = context->bw_ctx.dml.vba.maxMpcComb;
2129 double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][maxMpcComb];
2130 bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][maxMpcComb] != dm_dram_clock_change_unsupported;
2132 if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)
2133 dcfclk = context->bw_ctx.dml.soc.min_dcfclk;
2135 pipes[0].clks_cfg.voltage = vlevel;
2136 pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
2137 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2140 * DCFCLK: 1GHz or min required above 1GHz
2143 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
2145 pipes[0].clks_cfg.voltage = 1;
2146 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz;
2148 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
2149 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
2150 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
2152 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2153 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2154 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2155 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2156 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2157 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2158 context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2159 context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2161 pipes[0].clks_cfg.voltage = vlevel;
2162 pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
2165 * DCFCLK: Min Required
2166 * FCLK(proportional to UCLK): 1GHz or Max
2167 * MALL stutter, sr_enter_exit = 4, sr_exit = 2us
2170 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
2171 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
2172 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
2173 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
2175 context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2176 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2177 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2178 context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2179 context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2180 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2181 context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2182 context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2186 * DCFCLK: Min Required
2187 * FCLK(proportional to UCLK): 1GHz or Max
2188 * pstate latency overridden to 5us
2190 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
2191 unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;
2192 unsigned int min_dram_speed_mts_margin = 160;
2194 if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_dram_clock_change_unsupported)
2195 min_dram_speed_mts = dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz * 16;
2197 /* find largest table entry that is lower than dram speed, but lower than DPM0 still uses DPM0 */
2198 for (i = 3; i > 0; i--)
2199 if (min_dram_speed_mts + min_dram_speed_mts_margin > dc->clk_mgr->bw_params->dummy_pstate_table[i].dram_speed_mts)
2202 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[i].dummy_pstate_latency_us;
2203 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
2204 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
2207 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2208 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2209 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2210 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2211 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2212 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2213 context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2214 context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2217 /* The only difference between A and C is p-state latency, if p-state is not supported we want to
2218 * calculate DLG based on dummy p-state latency, and max out the set A p-state watermark
2220 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c;
2221 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0;
2224 * DCFCLK: Min Required
2225 * FCLK(proportional to UCLK): 1GHz or Max
2227 * Set A calculated last so that following calculations are based on Set A
2229 dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
2230 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2231 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2232 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2233 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2234 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2235 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2236 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2237 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2240 context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod;
2242 /* Make set D = set A until set D is enabled */
2243 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
2245 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2246 if (!context->res_ctx.pipe_ctx[i].stream)
2249 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
2250 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
2252 if (dc->config.forced_clocks) {
2253 pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2254 pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2256 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
2257 pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2258 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
2259 pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2264 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2267 /* Restore full p-state latency */
2268 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2269 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2272 void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
2274 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) {
2275 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2276 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;
2277 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;
2281 void dcn30_calculate_wm_and_dlg(
2282 struct dc *dc, struct dc_state *context,
2283 display_e2e_pipe_params_st *pipes,
2288 dcn30_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
2292 bool dcn30_validate_bandwidth(struct dc *dc,
2293 struct dc_state *context,
2298 BW_VAL_TRACE_SETUP();
2302 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2303 DC_LOGGER_INIT(dc->ctx->logger);
2305 BW_VAL_TRACE_COUNT();
2308 out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
2317 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2319 if (fast_validate) {
2320 BW_VAL_TRACE_SKIP(fast);
2325 dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2328 BW_VAL_TRACE_END_WATERMARKS();
2333 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2334 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2336 BW_VAL_TRACE_SKIP(fail);
2342 BW_VAL_TRACE_FINISH();
2348 * This must be noinline to ensure anything that deals with FP registers
2349 * is contained within this call; previously our compiling with hard-float
2350 * would result in fp instructions being emitted outside of the boundaries
2351 * of the DC_FP_START/END macros, which makes sense as the compiler has no
2352 * idea about what is wrapped and what is not
2354 * This is largely just a workaround to avoid breakage introduced with 5.6,
2355 * ideally all fp-using code should be moved into its own file, only that
2356 * should be compiled with hard-float, and all code exported from there
2357 * should be strictly wrapped with DC_FP_START/END
2359 static noinline void dcn30_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
2360 unsigned int *optimal_dcfclk,
2361 unsigned int *optimal_fclk)
2363 double bw_from_dram, bw_from_dram1, bw_from_dram2;
2365 bw_from_dram1 = uclk_mts * dcn3_0_soc.num_chans *
2366 dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_dram_bw_use_normal_percent / 100);
2367 bw_from_dram2 = uclk_mts * dcn3_0_soc.num_chans *
2368 dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100);
2370 bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
2373 *optimal_fclk = bw_from_dram /
2374 (dcn3_0_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100));
2377 *optimal_dcfclk = bw_from_dram /
2378 (dcn3_0_soc.return_bus_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100));
2381 void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2384 unsigned int num_states = 0;
2386 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
2387 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
2388 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
2389 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
2391 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200};
2392 unsigned int num_dcfclk_sta_targets = 4;
2393 unsigned int num_uclk_states;
2395 if (dc->ctx->dc_bios->vram_info.num_chans)
2396 dcn3_0_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
2398 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
2399 dcn3_0_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
2401 dcn3_0_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2402 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2404 if (bw_params->clk_table.entries[0].memclk_mhz) {
2405 int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
2407 for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
2408 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
2409 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2410 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
2411 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
2412 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
2413 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
2414 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
2415 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
2418 if (!max_dcfclk_mhz)
2419 max_dcfclk_mhz = dcn3_0_soc.clock_limits[0].dcfclk_mhz;
2420 if (!max_dispclk_mhz)
2421 max_dispclk_mhz = dcn3_0_soc.clock_limits[0].dispclk_mhz;
2422 if (!max_dppclk_mhz)
2423 max_dppclk_mhz = dcn3_0_soc.clock_limits[0].dppclk_mhz;
2424 if (!max_phyclk_mhz)
2425 max_phyclk_mhz = dcn3_0_soc.clock_limits[0].phyclk_mhz;
2427 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2428 // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
2429 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
2430 num_dcfclk_sta_targets++;
2431 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2432 // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
2433 for (i = 0; i < num_dcfclk_sta_targets; i++) {
2434 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
2435 dcfclk_sta_targets[i] = max_dcfclk_mhz;
2439 // Update size of array since we "removed" duplicates
2440 num_dcfclk_sta_targets = i + 1;
2443 num_uclk_states = bw_params->clk_table.num_entries;
2445 // Calculate optimal dcfclk for each uclk
2446 for (i = 0; i < num_uclk_states; i++) {
2448 dcn30_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
2449 &optimal_dcfclk_for_uclk[i], NULL);
2451 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
2452 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
2456 // Calculate optimal uclk for each dcfclk sta target
2457 for (i = 0; i < num_dcfclk_sta_targets; i++) {
2458 for (j = 0; j < num_uclk_states; j++) {
2459 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
2460 optimal_uclk_for_dcfclk_sta_targets[i] =
2461 bw_params->clk_table.entries[j].memclk_mhz * 16;
2469 // create the final dcfclk and uclk table
2470 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
2471 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
2472 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2473 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2475 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
2476 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2477 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2479 j = num_uclk_states;
2484 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
2485 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2486 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2489 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
2490 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
2491 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2492 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2495 dcn3_0_soc.num_states = num_states;
2496 for (i = 0; i < dcn3_0_soc.num_states; i++) {
2497 dcn3_0_soc.clock_limits[i].state = i;
2498 dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
2499 dcn3_0_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
2500 dcn3_0_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
2502 /* Fill all states with max values of all other clocks */
2503 dcn3_0_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
2504 dcn3_0_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz;
2505 dcn3_0_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz;
2506 dcn3_0_soc.clock_limits[i].dtbclk_mhz = dcn3_0_soc.clock_limits[0].dtbclk_mhz;
2507 /* These clocks cannot come from bw_params, always fill from dcn3_0_soc[1] */
2508 /* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */
2509 dcn3_0_soc.clock_limits[i].phyclk_d18_mhz = dcn3_0_soc.clock_limits[0].phyclk_d18_mhz;
2510 dcn3_0_soc.clock_limits[i].socclk_mhz = dcn3_0_soc.clock_limits[0].socclk_mhz;
2511 dcn3_0_soc.clock_limits[i].dscclk_mhz = dcn3_0_soc.clock_limits[0].dscclk_mhz;
2513 /* re-init DML with updated bb */
2514 dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2515 if (dc->current_state)
2516 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2520 static const struct resource_funcs dcn30_res_pool_funcs = {
2521 .destroy = dcn30_destroy_resource_pool,
2522 .link_enc_create = dcn30_link_encoder_create,
2523 .panel_cntl_create = dcn30_panel_cntl_create,
2524 .validate_bandwidth = dcn30_validate_bandwidth,
2525 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
2526 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
2527 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
2528 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
2529 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
2530 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2531 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2532 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
2533 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
2534 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2535 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
2536 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
2537 .update_bw_bounding_box = dcn30_update_bw_bounding_box,
2538 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2543 #define REG(reg_name) \
2544 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
2546 static uint32_t read_pipe_fuses(struct dc_context *ctx)
2548 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
2549 /* Support for max 6 pipes */
2550 value = value & 0x3f;
2554 static bool dcn30_resource_construct(
2555 uint8_t num_virtual_links,
2557 struct dcn30_resource_pool *pool)
2560 struct dc_context *ctx = dc->ctx;
2561 struct irq_service_init_data init_data;
2562 struct ddc_service_init_data ddc_init_data = {0};
2563 uint32_t pipe_fuses = read_pipe_fuses(ctx);
2564 uint32_t num_pipes = 0;
2566 if (!(pipe_fuses == 0 || pipe_fuses == 0x3e)) {
2567 BREAK_TO_DEBUGGER();
2568 dm_error("DC: Unexpected fuse recipe for navi2x !\n");
2569 /* fault to single pipe */
2575 ctx->dc_bios->regs = &bios_regs;
2577 pool->base.res_cap = &res_cap_dcn3;
2579 pool->base.funcs = &dcn30_res_pool_funcs;
2581 /*************************************************
2582 * Resource + asic cap harcoding *
2583 *************************************************/
2584 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2585 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
2586 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
2587 dc->caps.max_downscale_ratio = 600;
2588 dc->caps.i2c_speed_in_khz = 100;
2589 dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
2590 dc->caps.max_cursor_size = 256;
2591 dc->caps.min_horizontal_blanking_period = 80;
2592 dc->caps.dmdata_alloc_size = 2048;
2593 dc->caps.mall_size_per_mem_channel = 8;
2594 /* total size = mall per channel * num channels * 1024 * 1024 */
2595 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
2596 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
2598 dc->caps.max_slave_planes = 1;
2599 dc->caps.max_slave_yuv_planes = 1;
2600 dc->caps.max_slave_rgb_planes = 1;
2601 dc->caps.post_blend_color_processing = true;
2602 dc->caps.force_dp_tps4_for_cp2520 = true;
2603 dc->caps.extended_aux_timeout_support = true;
2604 dc->caps.dmcub_support = true;
2606 /* Color pipeline capabilities */
2607 dc->caps.color.dpp.dcn_arch = 1;
2608 dc->caps.color.dpp.input_lut_shared = 0;
2609 dc->caps.color.dpp.icsc = 1;
2610 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2611 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2612 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2613 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2614 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2615 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2616 dc->caps.color.dpp.post_csc = 1;
2617 dc->caps.color.dpp.gamma_corr = 1;
2618 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2620 dc->caps.color.dpp.hw_3d_lut = 1;
2621 dc->caps.color.dpp.ogam_ram = 1;
2622 // no OGAM ROM on DCN3
2623 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2624 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2625 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2626 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2627 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2628 dc->caps.color.dpp.ocsc = 0;
2630 dc->caps.color.mpc.gamut_remap = 1;
2631 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //3
2632 dc->caps.color.mpc.ogam_ram = 1;
2633 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2634 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2635 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2636 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2637 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2638 dc->caps.color.mpc.ocsc = 1;
2640 dc->caps.hdmi_frl_pcon_support = true;
2642 /* read VBIOS LTTPR caps */
2644 if (ctx->dc_bios->funcs->get_lttpr_caps) {
2645 enum bp_result bp_query_result;
2646 uint8_t is_vbios_lttpr_enable = 0;
2648 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
2649 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
2652 if (ctx->dc_bios->funcs->get_lttpr_interop) {
2653 enum bp_result bp_query_result;
2654 uint8_t is_vbios_interop_enabled = 0;
2656 bp_query_result = ctx->dc_bios->funcs->get_lttpr_interop(ctx->dc_bios,
2657 &is_vbios_interop_enabled);
2658 dc->caps.vbios_lttpr_aware = (bp_query_result == BP_RESULT_OK) && !!is_vbios_interop_enabled;
2662 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2663 dc->debug = debug_defaults_drv;
2664 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2665 dc->debug = debug_defaults_diags;
2667 dc->debug = debug_defaults_diags;
2668 // Init the vm_helper
2670 vm_helper_init(dc->vm_helper, 16);
2672 /*************************************************
2673 * Create resources *
2674 *************************************************/
2676 /* Clock Sources for Pixel Clock*/
2677 pool->base.clock_sources[DCN30_CLK_SRC_PLL0] =
2678 dcn30_clock_source_create(ctx, ctx->dc_bios,
2679 CLOCK_SOURCE_COMBO_PHY_PLL0,
2680 &clk_src_regs[0], false);
2681 pool->base.clock_sources[DCN30_CLK_SRC_PLL1] =
2682 dcn30_clock_source_create(ctx, ctx->dc_bios,
2683 CLOCK_SOURCE_COMBO_PHY_PLL1,
2684 &clk_src_regs[1], false);
2685 pool->base.clock_sources[DCN30_CLK_SRC_PLL2] =
2686 dcn30_clock_source_create(ctx, ctx->dc_bios,
2687 CLOCK_SOURCE_COMBO_PHY_PLL2,
2688 &clk_src_regs[2], false);
2689 pool->base.clock_sources[DCN30_CLK_SRC_PLL3] =
2690 dcn30_clock_source_create(ctx, ctx->dc_bios,
2691 CLOCK_SOURCE_COMBO_PHY_PLL3,
2692 &clk_src_regs[3], false);
2693 pool->base.clock_sources[DCN30_CLK_SRC_PLL4] =
2694 dcn30_clock_source_create(ctx, ctx->dc_bios,
2695 CLOCK_SOURCE_COMBO_PHY_PLL4,
2696 &clk_src_regs[4], false);
2697 pool->base.clock_sources[DCN30_CLK_SRC_PLL5] =
2698 dcn30_clock_source_create(ctx, ctx->dc_bios,
2699 CLOCK_SOURCE_COMBO_PHY_PLL5,
2700 &clk_src_regs[5], false);
2702 pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2704 /* todo: not reuse phy_pll registers */
2705 pool->base.dp_clock_source =
2706 dcn30_clock_source_create(ctx, ctx->dc_bios,
2707 CLOCK_SOURCE_ID_DP_DTO,
2708 &clk_src_regs[0], true);
2710 for (i = 0; i < pool->base.clk_src_count; i++) {
2711 if (pool->base.clock_sources[i] == NULL) {
2712 dm_error("DC: failed to create clock sources!\n");
2713 BREAK_TO_DEBUGGER();
2719 pool->base.dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2720 if (pool->base.dccg == NULL) {
2721 dm_error("DC: failed to create dccg!\n");
2722 BREAK_TO_DEBUGGER();
2726 /* PP Lib and SMU interfaces */
2727 init_soc_bounding_box(dc, pool);
2729 num_pipes = dcn3_0_ip.max_num_dpp;
2731 for (i = 0; i < dcn3_0_ip.max_num_dpp; i++)
2732 if (pipe_fuses & 1 << i)
2735 dcn3_0_ip.max_num_dpp = num_pipes;
2736 dcn3_0_ip.max_num_otg = num_pipes;
2738 dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2741 init_data.ctx = dc->ctx;
2742 pool->base.irqs = dal_irq_service_dcn30_create(&init_data);
2743 if (!pool->base.irqs)
2747 pool->base.hubbub = dcn30_hubbub_create(ctx);
2748 if (pool->base.hubbub == NULL) {
2749 BREAK_TO_DEBUGGER();
2750 dm_error("DC: failed to create hubbub!\n");
2754 /* HUBPs, DPPs, OPPs and TGs */
2755 for (i = 0; i < pool->base.pipe_count; i++) {
2756 pool->base.hubps[i] = dcn30_hubp_create(ctx, i);
2757 if (pool->base.hubps[i] == NULL) {
2758 BREAK_TO_DEBUGGER();
2760 "DC: failed to create hubps!\n");
2764 pool->base.dpps[i] = dcn30_dpp_create(ctx, i);
2765 if (pool->base.dpps[i] == NULL) {
2766 BREAK_TO_DEBUGGER();
2768 "DC: failed to create dpps!\n");
2773 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2774 pool->base.opps[i] = dcn30_opp_create(ctx, i);
2775 if (pool->base.opps[i] == NULL) {
2776 BREAK_TO_DEBUGGER();
2778 "DC: failed to create output pixel processor!\n");
2783 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2784 pool->base.timing_generators[i] = dcn30_timing_generator_create(
2786 if (pool->base.timing_generators[i] == NULL) {
2787 BREAK_TO_DEBUGGER();
2788 dm_error("DC: failed to create tg!\n");
2792 pool->base.timing_generator_count = i;
2794 pool->base.psr = dmub_psr_create(ctx);
2796 if (pool->base.psr == NULL) {
2797 dm_error("DC: failed to create PSR obj!\n");
2798 BREAK_TO_DEBUGGER();
2803 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2804 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2808 if (pool->base.multiple_abms[i] == NULL) {
2809 dm_error("DC: failed to create abm for pipe %d!\n", i);
2810 BREAK_TO_DEBUGGER();
2815 pool->base.mpc = dcn30_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2816 if (pool->base.mpc == NULL) {
2817 BREAK_TO_DEBUGGER();
2818 dm_error("DC: failed to create mpc!\n");
2822 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2823 pool->base.dscs[i] = dcn30_dsc_create(ctx, i);
2824 if (pool->base.dscs[i] == NULL) {
2825 BREAK_TO_DEBUGGER();
2826 dm_error("DC: failed to create display stream compressor %d!\n", i);
2831 /* DWB and MMHUBBUB */
2832 if (!dcn30_dwbc_create(ctx, &pool->base)) {
2833 BREAK_TO_DEBUGGER();
2834 dm_error("DC: failed to create dwbc!\n");
2838 if (!dcn30_mmhubbub_create(ctx, &pool->base)) {
2839 BREAK_TO_DEBUGGER();
2840 dm_error("DC: failed to create mcif_wb!\n");
2845 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2846 pool->base.engines[i] = dcn30_aux_engine_create(ctx, i);
2847 if (pool->base.engines[i] == NULL) {
2848 BREAK_TO_DEBUGGER();
2850 "DC:failed to create aux engine!!\n");
2853 pool->base.hw_i2cs[i] = dcn30_i2c_hw_create(ctx, i);
2854 if (pool->base.hw_i2cs[i] == NULL) {
2855 BREAK_TO_DEBUGGER();
2857 "DC:failed to create hw i2c!!\n");
2860 pool->base.sw_i2cs[i] = NULL;
2863 /* Audio, Stream Encoders including DIG and virtual, MPC 3D LUTs */
2864 if (!resource_construct(num_virtual_links, dc, &pool->base,
2865 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2866 &res_create_funcs : &res_create_maximus_funcs)))
2869 /* HW Sequencer and Plane caps */
2870 dcn30_hw_sequencer_construct(dc);
2872 dc->caps.max_planes = pool->base.pipe_count;
2874 for (i = 0; i < dc->caps.max_planes; ++i)
2875 dc->caps.planes[i] = plane_cap;
2877 dc->cap_funcs = cap_funcs;
2879 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2880 ddc_init_data.ctx = dc->ctx;
2881 ddc_init_data.link = NULL;
2882 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2883 ddc_init_data.id.enum_id = 0;
2884 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2885 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
2887 pool->base.oem_device = NULL;
2897 dcn30_resource_destruct(pool);
2902 struct resource_pool *dcn30_create_resource_pool(
2903 const struct dc_init_data *init_data,
2906 struct dcn30_resource_pool *pool =
2907 kzalloc(sizeof(struct dcn30_resource_pool), GFP_KERNEL);
2912 if (dcn30_resource_construct(init_data->num_virtual_links, dc, pool))
2915 BREAK_TO_DEBUGGER();