drivers/gpu/drm/amd/display/dc/dcn30/dcn30_resource.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26
  27 #include "dm_services.h"
  28 #include "dc.h"
  29
  30 #include "dcn30_init.h"
  31
  32 #include "resource.h"
  33 #include "include/irq_service_interface.h"
  34 #include "dcn20/dcn20_resource.h"
  35
  36 #include "dcn30_resource.h"
  37
  38 #include "dcn10/dcn10_ipp.h"
  39 #include "dcn30/dcn30_hubbub.h"
  40 #include "dcn30/dcn30_mpc.h"
  41 #include "dcn30/dcn30_hubp.h"
  42 #include "irq/dcn30/irq_service_dcn30.h"
  43 #include "dcn30/dcn30_dpp.h"
  44 #include "dcn30/dcn30_optc.h"
  45 #include "dcn20/dcn20_hwseq.h"
  46 #include "dcn30/dcn30_hwseq.h"
  47 #include "dce110/dce110_hw_sequencer.h"
  48 #include "dcn30/dcn30_opp.h"
  49 #include "dcn20/dcn20_dsc.h"
  50 #include "dcn30/dcn30_vpg.h"
  51 #include "dcn30/dcn30_afmt.h"
  52 #include "dcn30/dcn30_dio_stream_encoder.h"
  53 #include "dcn30/dcn30_dio_link_encoder.h"
  54 #include "dce/dce_clock_source.h"
  55 #include "dce/dce_audio.h"
  56 #include "dce/dce_hwseq.h"
  57 #include "clk_mgr.h"
  58 #include "virtual/virtual_stream_encoder.h"
  59 #include "dce110/dce110_resource.h"
  60 #include "dml/display_mode_vba.h"
  61 #include "dcn30/dcn30_dccg.h"
  62 #include "dcn10/dcn10_resource.h"
  63 #include "dc_link_ddc.h"
  64 #include "dce/dce_panel_cntl.h"
  65
  66 #include "dcn30/dcn30_dwb.h"
  67 #include "dcn30/dcn30_mmhubbub.h"
  68
  69 #include "sienna_cichlid_ip_offset.h"
  70 #include "dcn/dcn_3_0_0_offset.h"
  71 #include "dcn/dcn_3_0_0_sh_mask.h"
  72
  73 #include "nbio/nbio_7_4_offset.h"
  74
  75 #include "dcn/dpcs_3_0_0_offset.h"
  76 #include "dcn/dpcs_3_0_0_sh_mask.h"
  77
  78 #include "mmhub/mmhub_2_0_0_offset.h"
  79 #include "mmhub/mmhub_2_0_0_sh_mask.h"
  80
  81 #include "reg_helper.h"
  82 #include "dce/dmub_abm.h"
  83 #include "dce/dmub_psr.h"
  84 #include "dce/dce_aux.h"
  85 #include "dce/dce_i2c.h"
  86
  87 #include "dml/dcn30/display_mode_vba_30.h"
  88 #include "vm_helper.h"
  89 #include "dcn20/dcn20_vmid.h"
  90 #include "amdgpu_socbb.h"
  91
  92 #define DC_LOGGER_INIT(logger)
  93
  94 struct _vcs_dpi_ip_params_st dcn3_0_ip = {
  95         .use_min_dcfclk = 1,
  96         .clamp_min_dcfclk = 0,
  97         .odm_capable = 1,
  98         .gpuvm_enable = 0,
  99         .hostvm_enable = 0,
 100         .gpuvm_max_page_table_levels = 4,
 101         .hostvm_max_page_table_levels = 4,
 102         .hostvm_cached_page_table_levels = 0,
 103         .pte_group_size_bytes = 2048,
 104         .num_dsc = 6,
 105         .rob_buffer_size_kbytes = 184,
 106         .det_buffer_size_kbytes = 184,
 107         .dpte_buffer_size_in_pte_reqs_luma = 84,
 108         .pde_proc_buffer_size_64k_reqs = 48,
 109         .dpp_output_buffer_pixels = 2560,
 110         .opp_output_buffer_lines = 1,
 111         .pixel_chunk_size_kbytes = 8,
 112         .pte_enable = 1,
 113         .max_page_table_levels = 2,
 114         .pte_chunk_size_kbytes = 2,  // ?
 115         .meta_chunk_size_kbytes = 2,
 116         .writeback_chunk_size_kbytes = 8,
 117         .line_buffer_size_bits = 789504,
 118         .is_line_buffer_bpp_fixed = 0,  // ?
 119         .line_buffer_fixed_bpp = 0,     // ?
 120         .dcc_supported = true,
 121         .writeback_interface_buffer_size_kbytes = 90,
 122         .writeback_line_buffer_buffer_size = 0,
 123         .max_line_buffer_lines = 12,
 124         .writeback_luma_buffer_size_kbytes = 12,  // writeback_line_buffer_buffer_size = 656640
 125         .writeback_chroma_buffer_size_kbytes = 8,
 126         .writeback_chroma_line_buffer_width_pixels = 4,
 127         .writeback_max_hscl_ratio = 1,
 128         .writeback_max_vscl_ratio = 1,
 129         .writeback_min_hscl_ratio = 1,
 130         .writeback_min_vscl_ratio = 1,
 131         .writeback_max_hscl_taps = 1,
 132         .writeback_max_vscl_taps = 1,
 133         .writeback_line_buffer_luma_buffer_size = 0,
 134         .writeback_line_buffer_chroma_buffer_size = 14643,
 135         .cursor_buffer_size = 8,
 136         .cursor_chunk_size = 2,
 137         .max_num_otg = 6,
 138         .max_num_dpp = 6,
 139         .max_num_wb = 1,
 140         .max_dchub_pscl_bw_pix_per_clk = 4,
 141         .max_pscl_lb_bw_pix_per_clk = 2,
 142         .max_lb_vscl_bw_pix_per_clk = 4,
 143         .max_vscl_hscl_bw_pix_per_clk = 4,
 144         .max_hscl_ratio = 6,
 145         .max_vscl_ratio = 6,
 146         .hscl_mults = 4,
 147         .vscl_mults = 4,
 148         .max_hscl_taps = 8,
 149         .max_vscl_taps = 8,
 150         .dispclk_ramp_margin_percent = 1,
 151         .underscan_factor = 1.11,
 152         .min_vblank_lines = 32,
 153         .dppclk_delay_subtotal = 46,
 154         .dynamic_metadata_vm_enabled = true,
 155         .dppclk_delay_scl_lb_only = 16,
 156         .dppclk_delay_scl = 50,
 157         .dppclk_delay_cnvc_formatter = 27,
 158         .dppclk_delay_cnvc_cursor = 6,
 159         .dispclk_delay_subtotal = 119,
 160         .dcfclk_cstate_latency = 5.2, // SRExitTime
 161         .max_inter_dcn_tile_repeaters = 8,
 162         .odm_combine_4to1_supported = true,
 163
 164         .xfc_supported = false,
 165         .xfc_fill_bw_overhead_percent = 10.0,
 166         .xfc_fill_constant_bytes = 0,
 167         .gfx7_compat_tiling_supported = 0,
 168         .number_of_cursors = 1,
 169 };
 170
 171 struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = {
 172         .clock_limits = {
 173                         {
 174                                 .state = 0,
 175                                 .dispclk_mhz = 562.0,
 176                                 .dppclk_mhz = 300.0,
 177                                 .phyclk_mhz = 300.0,
 178                                 .phyclk_d18_mhz = 667.0,
 179                                 .dscclk_mhz = 405.6,
 180                         },
 181                 },
 182         .min_dcfclk = 500.0, /* TODO: set this to actual min DCFCLK */
 183         .num_states = 1,
 184         .sr_exit_time_us = 15.5,
 185         .sr_enter_plus_exit_time_us = 20,
 186         .urgent_latency_us = 4.0,
 187         .urgent_latency_pixel_data_only_us = 4.0,
 188         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 189         .urgent_latency_vm_data_only_us = 4.0,
 190         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 191         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 192         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 193         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
 194         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
 195         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
 196         .max_avg_sdp_bw_use_normal_percent = 60.0,
 197         .max_avg_dram_bw_use_normal_percent = 40.0,
 198         .writeback_latency_us = 12.0,
 199         .max_request_size_bytes = 256,
 200         .fabric_datapath_to_dcn_data_return_bytes = 64,
 201         .dcn_downspread_percent = 0.5,
 202         .downspread_percent = 0.38,
 203         .dram_page_open_time_ns = 50.0,
 204         .dram_rw_turnaround_time_ns = 17.5,
 205         .dram_return_buffer_per_channel_bytes = 8192,
 206         .round_trip_ping_latency_dcfclk_cycles = 191,
 207         .urgent_out_of_order_return_per_channel_bytes = 4096,
 208         .channel_interleave_bytes = 256,
 209         .num_banks = 8,
 210         .gpuvm_min_page_size_bytes = 4096,
 211         .hostvm_min_page_size_bytes = 4096,
 212         .dram_clock_change_latency_us = 404,
 213         .dummy_pstate_latency_us = 5,
 214         .writeback_dram_clock_change_latency_us = 23.0,
 215         .return_bus_width_bytes = 64,
 216         .dispclk_dppclk_vco_speed_mhz = 3650,
 217         .xfc_bus_transport_time_us = 20,      // ?
 218         .xfc_xbuf_latency_tolerance_us = 4,  // ?
 219         .use_urgent_burst_bw = 1,            // ?
 220         .do_urgent_latency_adjustment = true,
 221         .urgent_latency_adjustment_fabric_clock_component_us = 1.0,
 222         .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
 223 };
 224
 225 enum dcn30_clk_src_array_id {
 226         DCN30_CLK_SRC_PLL0,
 227         DCN30_CLK_SRC_PLL1,
 228         DCN30_CLK_SRC_PLL2,
 229         DCN30_CLK_SRC_PLL3,
 230         DCN30_CLK_SRC_PLL4,
 231         DCN30_CLK_SRC_PLL5,
 232         DCN30_CLK_SRC_TOTAL
 233 };
 234
 235 /* begin *********************
 236  * macros to expend register list macro defined in HW object header file
 237  */
 238
 239 /* DCN */
 240 /* TODO awful hack. fixup dcn20_dwb.h */
 241 #undef BASE_INNER
 242 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 243
 244 #define BASE(seg) BASE_INNER(seg)
 245
 246 #define SR(reg_name)\
 247                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 248                                         mm ## reg_name
 249
 250 #define SRI(reg_name, block, id)\
 251         .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 252                                         mm ## block ## id ## _ ## reg_name
 253
 254 #define SRI2(reg_name, block, id)\
 255         .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
 256                                         mm ## reg_name
 257
 258 #define SRIR(var_name, reg_name, block, id)\
 259         .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 260                                         mm ## block ## id ## _ ## reg_name
 261
 262 #define SRII(reg_name, block, id)\
 263         .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 264                                         mm ## block ## id ## _ ## reg_name
 265
 266 #define SRII_MPC_RMU(reg_name, block, id)\
 267         .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 268                                         mm ## block ## id ## _ ## reg_name
 269
 270 #define SRII_DWB(reg_name, temp_name, block, id)\
 271         .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
 272                                         mm ## block ## id ## _ ## temp_name
 273
 274 #define DCCG_SRII(reg_name, block, id)\
 275         .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 276                                         mm ## block ## id ## _ ## reg_name
 277
 278 #define VUPDATE_SRII(reg_name, block, id)\
 279         .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
 280                                         mm ## reg_name ## _ ## block ## id
 281
 282 /* NBIO */
 283 #define NBIO_BASE_INNER(seg) \
 284         NBIO_BASE__INST0_SEG ## seg
 285
 286 #define NBIO_BASE(seg) \
 287         NBIO_BASE_INNER(seg)
 288
 289 #define NBIO_SR(reg_name)\
 290                 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
 291                                         mm ## reg_name
 292
 293 /* MMHUB */
 294 #define MMHUB_BASE_INNER(seg) \
 295         MMHUB_BASE__INST0_SEG ## seg
 296
 297 #define MMHUB_BASE(seg) \
 298         MMHUB_BASE_INNER(seg)
 299
 300 #define MMHUB_SR(reg_name)\
 301                 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
 302                                         mmMM ## reg_name
 303
 304 /* CLOCK */
 305 #define CLK_BASE_INNER(seg) \
 306         CLK_BASE__INST0_SEG ## seg
 307
 308 #define CLK_BASE(seg) \
 309         CLK_BASE_INNER(seg)
 310
 311 #define CLK_SRI(reg_name, block, inst)\
 312         .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
 313                                         mm ## block ## _ ## inst ## _ ## reg_name
 314
 315
 316 static const struct bios_registers bios_regs = {
 317                 NBIO_SR(BIOS_SCRATCH_3),
 318                 NBIO_SR(BIOS_SCRATCH_6)
 319 };
 320
 321 #define clk_src_regs(index, pllid)\
 322 [index] = {\
 323         CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
 324 }
 325
 326 static const struct dce110_clk_src_regs clk_src_regs[] = {
 327         clk_src_regs(0, A),
 328         clk_src_regs(1, B),
 329         clk_src_regs(2, C),
 330         clk_src_regs(3, D),
 331         clk_src_regs(4, E),
 332         clk_src_regs(5, F)
 333 };
 334
 335 static const struct dce110_clk_src_shift cs_shift = {
 336                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 337 };
 338
 339 static const struct dce110_clk_src_mask cs_mask = {
 340                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 341 };
 342
 343 #define abm_regs(id)\
 344 [id] = {\
 345                 ABM_DCN30_REG_LIST(id)\
 346 }
 347
 348 static const struct dce_abm_registers abm_regs[] = {
 349                 abm_regs(0),
 350                 abm_regs(1),
 351                 abm_regs(2),
 352                 abm_regs(3),
 353                 abm_regs(4),
 354                 abm_regs(5),
 355 };
 356
 357 static const struct dce_abm_shift abm_shift = {
 358                 ABM_MASK_SH_LIST_DCN30(__SHIFT)
 359 };
 360
 361 static const struct dce_abm_mask abm_mask = {
 362                 ABM_MASK_SH_LIST_DCN30(_MASK)
 363 };
 364
 365
 366
 367 #define audio_regs(id)\
 368 [id] = {\
 369                 AUD_COMMON_REG_LIST(id)\
 370 }
 371
 372 static const struct dce_audio_registers audio_regs[] = {
 373         audio_regs(0),
 374         audio_regs(1),
 375         audio_regs(2),
 376         audio_regs(3),
 377         audio_regs(4),
 378         audio_regs(5),
 379         audio_regs(6)
 380 };
 381
 382 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 383                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 384                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 385                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 386
 387 static const struct dce_audio_shift audio_shift = {
 388                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 389 };
 390
 391 static const struct dce_audio_mask audio_mask = {
 392                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 393 };
 394
 395 #define vpg_regs(id)\
 396 [id] = {\
 397         VPG_DCN3_REG_LIST(id)\
 398 }
 399
 400 static const struct dcn30_vpg_registers vpg_regs[] = {
 401         vpg_regs(0),
 402         vpg_regs(1),
 403         vpg_regs(2),
 404         vpg_regs(3),
 405         vpg_regs(4),
 406         vpg_regs(5),
 407         vpg_regs(6),
 408 };
 409
 410 static const struct dcn30_vpg_shift vpg_shift = {
 411         DCN3_VPG_MASK_SH_LIST(__SHIFT)
 412 };
 413
 414 static const struct dcn30_vpg_mask vpg_mask = {
 415         DCN3_VPG_MASK_SH_LIST(_MASK)
 416 };
 417
 418 #define afmt_regs(id)\
 419 [id] = {\
 420         AFMT_DCN3_REG_LIST(id)\
 421 }
 422
 423 static const struct dcn30_afmt_registers afmt_regs[] = {
 424         afmt_regs(0),
 425         afmt_regs(1),
 426         afmt_regs(2),
 427         afmt_regs(3),
 428         afmt_regs(4),
 429         afmt_regs(5),
 430         afmt_regs(6),
 431 };
 432
 433 static const struct dcn30_afmt_shift afmt_shift = {
 434         DCN3_AFMT_MASK_SH_LIST(__SHIFT)
 435 };
 436
 437 static const struct dcn30_afmt_mask afmt_mask = {
 438         DCN3_AFMT_MASK_SH_LIST(_MASK)
 439 };
 440
 441 #define stream_enc_regs(id)\
 442 [id] = {\
 443         SE_DCN3_REG_LIST(id)\
 444 }
 445
 446 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 447         stream_enc_regs(0),
 448         stream_enc_regs(1),
 449         stream_enc_regs(2),
 450         stream_enc_regs(3),
 451         stream_enc_regs(4),
 452         stream_enc_regs(5)
 453 };
 454
 455 static const struct dcn10_stream_encoder_shift se_shift = {
 456                 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 457 };
 458
 459 static const struct dcn10_stream_encoder_mask se_mask = {
 460                 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
 461 };
 462
 463
 464 #define aux_regs(id)\
 465 [id] = {\
 466         DCN2_AUX_REG_LIST(id)\
 467 }
 468
 469 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 470                 aux_regs(0),
 471                 aux_regs(1),
 472                 aux_regs(2),
 473                 aux_regs(3),
 474                 aux_regs(4),
 475                 aux_regs(5)
 476 };
 477
 478 #define hpd_regs(id)\
 479 [id] = {\
 480         HPD_REG_LIST(id)\
 481 }
 482
 483 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 484                 hpd_regs(0),
 485                 hpd_regs(1),
 486                 hpd_regs(2),
 487                 hpd_regs(3),
 488                 hpd_regs(4),
 489                 hpd_regs(5)
 490 };
 491
 492 #define link_regs(id, phyid)\
 493 [id] = {\
 494         LE_DCN3_REG_LIST(id), \
 495         UNIPHY_DCN2_REG_LIST(phyid), \
 496         DPCS_DCN2_REG_LIST(id), \
 497         SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
 498 }
 499
 500 static const struct dce110_aux_registers_shift aux_shift = {
 501         DCN_AUX_MASK_SH_LIST(__SHIFT)
 502 };
 503
 504 static const struct dce110_aux_registers_mask aux_mask = {
 505         DCN_AUX_MASK_SH_LIST(_MASK)
 506 };
 507
 508 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 509         link_regs(0, A),
 510         link_regs(1, B),
 511         link_regs(2, C),
 512         link_regs(3, D),
 513         link_regs(4, E),
 514         link_regs(5, F)
 515 };
 516
 517 static const struct dcn10_link_enc_shift le_shift = {
 518         LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),\
 519         DPCS_DCN2_MASK_SH_LIST(__SHIFT)
 520 };
 521
 522 static const struct dcn10_link_enc_mask le_mask = {
 523         LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),\
 524         DPCS_DCN2_MASK_SH_LIST(_MASK)
 525 };
 526
 527
 528 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
 529         { DCN_PANEL_CNTL_REG_LIST() }
 530 };
 531
 532 static const struct dce_panel_cntl_shift panel_cntl_shift = {
 533         DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
 534 };
 535
 536 static const struct dce_panel_cntl_mask panel_cntl_mask = {
 537         DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
 538 };
 539
 540 #define dpp_regs(id)\
 541 [id] = {\
 542         DPP_REG_LIST_DCN30(id),\
 543 }
 544
 545 static const struct dcn3_dpp_registers dpp_regs[] = {
 546         dpp_regs(0),
 547         dpp_regs(1),
 548         dpp_regs(2),
 549         dpp_regs(3),
 550         dpp_regs(4),
 551         dpp_regs(5),
 552 };
 553
 554 static const struct dcn3_dpp_shift tf_shift = {
 555                 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
 556 };
 557
 558 static const struct dcn3_dpp_mask tf_mask = {
 559                 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
 560 };
 561
 562 #define opp_regs(id)\
 563 [id] = {\
 564         OPP_REG_LIST_DCN30(id),\
 565 }
 566
 567 static const struct dcn20_opp_registers opp_regs[] = {
 568         opp_regs(0),
 569         opp_regs(1),
 570         opp_regs(2),
 571         opp_regs(3),
 572         opp_regs(4),
 573         opp_regs(5)
 574 };
 575
 576 static const struct dcn20_opp_shift opp_shift = {
 577         OPP_MASK_SH_LIST_DCN20(__SHIFT)
 578 };
 579
 580 static const struct dcn20_opp_mask opp_mask = {
 581         OPP_MASK_SH_LIST_DCN20(_MASK)
 582 };
 583
 584 #define aux_engine_regs(id)\
 585 [id] = {\
 586         AUX_COMMON_REG_LIST0(id), \
 587         .AUXN_IMPCAL = 0, \
 588         .AUXP_IMPCAL = 0, \
 589         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 590 }
 591
 592 static const struct dce110_aux_registers aux_engine_regs[] = {
 593                 aux_engine_regs(0),
 594                 aux_engine_regs(1),
 595                 aux_engine_regs(2),
 596                 aux_engine_regs(3),
 597                 aux_engine_regs(4),
 598                 aux_engine_regs(5)
 599 };
 600
 601 #define dwbc_regs_dcn3(id)\
 602 [id] = {\
 603         DWBC_COMMON_REG_LIST_DCN30(id),\
 604 }
 605
 606 static const struct dcn30_dwbc_registers dwbc30_regs[] = {
 607         dwbc_regs_dcn3(0),
 608 };
 609
 610 static const struct dcn30_dwbc_shift dwbc30_shift = {
 611         DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 612 };
 613
 614 static const struct dcn30_dwbc_mask dwbc30_mask = {
 615         DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 616 };
 617
 618 #define mcif_wb_regs_dcn3(id)\
 619 [id] = {\
 620         MCIF_WB_COMMON_REG_LIST_DCN30(id),\
 621 }
 622
 623 static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
 624         mcif_wb_regs_dcn3(0)
 625 };
 626
 627 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
 628         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 629 };
 630
 631 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
 632         MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
 633 };
 634
 635 #define dsc_regsDCN20(id)\
 636 [id] = {\
 637         DSC_REG_LIST_DCN20(id)\
 638 }
 639
 640 static const struct dcn20_dsc_registers dsc_regs[] = {
 641         dsc_regsDCN20(0),
 642         dsc_regsDCN20(1),
 643         dsc_regsDCN20(2),
 644         dsc_regsDCN20(3),
 645         dsc_regsDCN20(4),
 646         dsc_regsDCN20(5)
 647 };
 648
 649 static const struct dcn20_dsc_shift dsc_shift = {
 650         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 651 };
 652
 653 static const struct dcn20_dsc_mask dsc_mask = {
 654         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 655 };
 656
 657 static const struct dcn30_mpc_registers mpc_regs = {
 658                 MPC_REG_LIST_DCN3_0(0),
 659                 MPC_REG_LIST_DCN3_0(1),
 660                 MPC_REG_LIST_DCN3_0(2),
 661                 MPC_REG_LIST_DCN3_0(3),
 662                 MPC_REG_LIST_DCN3_0(4),
 663                 MPC_REG_LIST_DCN3_0(5),
 664                 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
 665                 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
 666                 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
 667                 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
 668                 MPC_OUT_MUX_REG_LIST_DCN3_0(4),
 669                 MPC_OUT_MUX_REG_LIST_DCN3_0(5),
 670                 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
 671                 MPC_RMU_REG_LIST_DCN3AG(0),
 672                 MPC_RMU_REG_LIST_DCN3AG(1),
 673                 MPC_RMU_REG_LIST_DCN3AG(2),
 674                 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
 675 };
 676
 677 static const struct dcn30_mpc_shift mpc_shift = {
 678         MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 679 };
 680
 681 static const struct dcn30_mpc_mask mpc_mask = {
 682         MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 683 };
 684
 685 #define optc_regs(id)\
 686 [id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)}
 687
 688
 689 static const struct dcn_optc_registers optc_regs[] = {
 690         optc_regs(0),
 691         optc_regs(1),
 692         optc_regs(2),
 693         optc_regs(3),
 694         optc_regs(4),
 695         optc_regs(5)
 696 };
 697
 698 static const struct dcn_optc_shift optc_shift = {
 699         OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 700 };
 701
 702 static const struct dcn_optc_mask optc_mask = {
 703         OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
 704 };
 705
 706 #define hubp_regs(id)\
 707 [id] = {\
 708         HUBP_REG_LIST_DCN30(id)\
 709 }
 710
 711 static const struct dcn_hubp2_registers hubp_regs[] = {
 712                 hubp_regs(0),
 713                 hubp_regs(1),
 714                 hubp_regs(2),
 715                 hubp_regs(3),
 716                 hubp_regs(4),
 717                 hubp_regs(5)
 718 };
 719
 720 static const struct dcn_hubp2_shift hubp_shift = {
 721                 HUBP_MASK_SH_LIST_DCN30(__SHIFT)
 722 };
 723
 724 static const struct dcn_hubp2_mask hubp_mask = {
 725                 HUBP_MASK_SH_LIST_DCN30(_MASK)
 726 };
 727
 728 static const struct dcn_hubbub_registers hubbub_reg = {
 729                 HUBBUB_REG_LIST_DCN30(0)
 730 };
 731
 732 static const struct dcn_hubbub_shift hubbub_shift = {
 733                 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
 734 };
 735
 736 static const struct dcn_hubbub_mask hubbub_mask = {
 737                 HUBBUB_MASK_SH_LIST_DCN30(_MASK)
 738 };
 739
 740 static const struct dccg_registers dccg_regs = {
 741                 DCCG_REG_LIST_DCN30()
 742 };
 743
 744 static const struct dccg_shift dccg_shift = {
 745                 DCCG_MASK_SH_LIST_DCN3(__SHIFT)
 746 };
 747
 748 static const struct dccg_mask dccg_mask = {
 749                 DCCG_MASK_SH_LIST_DCN3(_MASK)
 750 };
 751
 752 static const struct dce_hwseq_registers hwseq_reg = {
 753                 HWSEQ_DCN30_REG_LIST()
 754 };
 755
 756 static const struct dce_hwseq_shift hwseq_shift = {
 757                 HWSEQ_DCN30_MASK_SH_LIST(__SHIFT)
 758 };
 759
 760 static const struct dce_hwseq_mask hwseq_mask = {
 761                 HWSEQ_DCN30_MASK_SH_LIST(_MASK)
 762 };
 763 #define vmid_regs(id)\
 764 [id] = {\
 765                 DCN20_VMID_REG_LIST(id)\
 766 }
 767
 768 static const struct dcn_vmid_registers vmid_regs[] = {
 769         vmid_regs(0),
 770         vmid_regs(1),
 771         vmid_regs(2),
 772         vmid_regs(3),
 773         vmid_regs(4),
 774         vmid_regs(5),
 775         vmid_regs(6),
 776         vmid_regs(7),
 777         vmid_regs(8),
 778         vmid_regs(9),
 779         vmid_regs(10),
 780         vmid_regs(11),
 781         vmid_regs(12),
 782         vmid_regs(13),
 783         vmid_regs(14),
 784         vmid_regs(15)
 785 };
 786
 787 static const struct dcn20_vmid_shift vmid_shifts = {
 788                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 789 };
 790
 791 static const struct dcn20_vmid_mask vmid_masks = {
 792                 DCN20_VMID_MASK_SH_LIST(_MASK)
 793 };
 794
 795 static const struct resource_caps res_cap_dcn3 = {
 796         .num_timing_generator = 6,
 797         .num_opp = 6,
 798         .num_video_plane = 6,
 799         .num_audio = 6,
 800         .num_stream_encoder = 6,
 801         .num_pll = 6,
 802         .num_dwb = 1,
 803         .num_ddc = 6,
 804         .num_vmid = 16,
 805         .num_mpc_3dlut = 3,
 806         .num_dsc = 6,
 807 };
 808
 809 static const struct dc_plane_cap plane_cap = {
 810         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 811         .blends_with_above = true,
 812         .blends_with_below = true,
 813         .per_pixel_alpha = true,
 814
 815         .pixel_format_support = {
 816                         .argb8888 = true,
 817                         .nv12 = true,
 818                         .fp16 = true,
 819                         .p010 = false,
 820                         .ayuv = false,
 821         },
 822
 823         .max_upscale_factor = {
 824                         .argb8888 = 16000,
 825                         .nv12 = 16000,
 826                         .fp16 = 16000
 827         },
 828
 829         .max_downscale_factor = {
 830                         .argb8888 = 600,
 831                         .nv12 = 600,
 832                         .fp16 = 600
 833         }
 834 };
 835
 836 static const struct dc_debug_options debug_defaults_drv = {
 837         .disable_dmcu = true, //No DMCU on DCN30
 838         .force_abm_enable = false,
 839         .timing_trace = false,
 840         .clock_trace = true,
 841         .disable_pplib_clock_request = true,
 842         .pipe_split_policy = MPC_SPLIT_DYNAMIC,
 843         .force_single_disp_pipe_split = false,
 844         .disable_dcc = DCC_ENABLE,
 845         .vsr_support = true,
 846         .performance_trace = false,
 847         .max_downscale_src_width = 7680,/*upto 8K*/
 848         .disable_pplib_wm_range = false,
 849         .scl_reset_length10 = true,
 850         .sanity_checks = false,
 851         .underflow_assert_delay_us = 0xFFFFFFFF,
 852         .dwb_fi_phase = -1, // -1 = disable,
 853         .dmub_command_table = true,
 854         .disable_psr = false,
 855         .use_max_lb = true
 856 };
 857
 858 static const struct dc_debug_options debug_defaults_diags = {
 859         .disable_dmcu = true, //No dmcu on DCN30
 860         .force_abm_enable = false,
 861         .timing_trace = true,
 862         .clock_trace = true,
 863         .disable_dpp_power_gate = true,
 864         .disable_hubp_power_gate = true,
 865         .disable_clock_gate = true,
 866         .disable_pplib_clock_request = true,
 867         .disable_pplib_wm_range = true,
 868         .disable_stutter = false,
 869         .scl_reset_length10 = true,
 870         .dwb_fi_phase = -1, // -1 = disable
 871         .dmub_command_table = true,
 872         .disable_psr = true,
 873         .enable_tri_buf = true,
 874         .use_max_lb = true
 875 };
 876
 877 void dcn30_dpp_destroy(struct dpp **dpp)
 878 {
 879         kfree(TO_DCN20_DPP(*dpp));
 880         *dpp = NULL;
 881 }
 882
 883 static struct dpp *dcn30_dpp_create(
 884         struct dc_context *ctx,
 885         uint32_t inst)
 886 {
 887         struct dcn3_dpp *dpp =
 888                 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
 889
 890         if (!dpp)
 891                 return NULL;
 892
 893         if (dpp3_construct(dpp, ctx, inst,
 894                         &dpp_regs[inst], &tf_shift, &tf_mask))
 895                 return &dpp->base;
 896
 897         BREAK_TO_DEBUGGER();
 898         kfree(dpp);
 899         return NULL;
 900 }
 901
 902 static struct output_pixel_processor *dcn30_opp_create(
 903         struct dc_context *ctx, uint32_t inst)
 904 {
 905         struct dcn20_opp *opp =
 906                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
 907
 908         if (!opp) {
 909                 BREAK_TO_DEBUGGER();
 910                 return NULL;
 911         }
 912
 913         dcn20_opp_construct(opp, ctx, inst,
 914                         &opp_regs[inst], &opp_shift, &opp_mask);
 915         return &opp->base;
 916 }
 917
 918 static struct dce_aux *dcn30_aux_engine_create(
 919         struct dc_context *ctx,
 920         uint32_t inst)
 921 {
 922         struct aux_engine_dce110 *aux_engine =
 923                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 924
 925         if (!aux_engine)
 926                 return NULL;
 927
 928         dce110_aux_engine_construct(aux_engine, ctx, inst,
 929                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 930                                     &aux_engine_regs[inst],
 931                                         &aux_mask,
 932                                         &aux_shift,
 933                                         ctx->dc->caps.extended_aux_timeout_support);
 934
 935         return &aux_engine->base;
 936 }
 937
 938 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST_DCN30(id) }
 939
 940 static const struct dce_i2c_registers i2c_hw_regs[] = {
 941                 i2c_inst_regs(1),
 942                 i2c_inst_regs(2),
 943                 i2c_inst_regs(3),
 944                 i2c_inst_regs(4),
 945                 i2c_inst_regs(5),
 946                 i2c_inst_regs(6),
 947 };
 948
 949 static const struct dce_i2c_shift i2c_shifts = {
 950                 I2C_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
 951 };
 952
 953 static const struct dce_i2c_mask i2c_masks = {
 954                 I2C_COMMON_MASK_SH_LIST_DCN30(_MASK)
 955 };
 956
 957 static struct dce_i2c_hw *dcn30_i2c_hw_create(
 958         struct dc_context *ctx,
 959         uint32_t inst)
 960 {
 961         struct dce_i2c_hw *dce_i2c_hw =
 962                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 963
 964         if (!dce_i2c_hw)
 965                 return NULL;
 966
 967         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 968                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 969
 970         return dce_i2c_hw;
 971 }
 972
 973 static struct mpc *dcn30_mpc_create(
 974                 struct dc_context *ctx,
 975                 int num_mpcc,
 976                 int num_rmu)
 977 {
 978         struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
 979                                           GFP_KERNEL);
 980
 981         if (!mpc30)
 982                 return NULL;
 983
 984         dcn30_mpc_construct(mpc30, ctx,
 985                         &mpc_regs,
 986                         &mpc_shift,
 987                         &mpc_mask,
 988                         num_mpcc,
 989                         num_rmu);
 990
 991         return &mpc30->base;
 992 }
 993
 994 struct hubbub *dcn30_hubbub_create(struct dc_context *ctx)
 995 {
 996         int i;
 997
 998         struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
 999                                           GFP_KERNEL);
1000
1001         if (!hubbub3)
1002                 return NULL;
1003
1004         hubbub3_construct(hubbub3, ctx,
1005                         &hubbub_reg,
1006                         &hubbub_shift,
1007                         &hubbub_mask);
1008
1009
1010         for (i = 0; i < res_cap_dcn3.num_vmid; i++) {
1011                 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1012
1013                 vmid->ctx = ctx;
1014
1015                 vmid->regs = &vmid_regs[i];
1016                 vmid->shifts = &vmid_shifts;
1017                 vmid->masks = &vmid_masks;
1018         }
1019
1020         return &hubbub3->base;
1021 }
1022
1023 static struct timing_generator *dcn30_timing_generator_create(
1024                 struct dc_context *ctx,
1025                 uint32_t instance)
1026 {
1027         struct optc *tgn10 =
1028                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1029
1030         if (!tgn10)
1031                 return NULL;
1032
1033         tgn10->base.inst = instance;
1034         tgn10->base.ctx = ctx;
1035
1036         tgn10->tg_regs = &optc_regs[instance];
1037         tgn10->tg_shift = &optc_shift;
1038         tgn10->tg_mask = &optc_mask;
1039
1040         dcn30_timing_generator_init(tgn10);
1041
1042         return &tgn10->base;
1043 }
1044
1045 static const struct encoder_feature_support link_enc_feature = {
1046                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1047                 .max_hdmi_pixel_clock = 600000,
1048                 .hdmi_ycbcr420_supported = true,
1049                 .dp_ycbcr420_supported = true,
1050                 .fec_supported = true,
1051                 .flags.bits.IS_HBR2_CAPABLE = true,
1052                 .flags.bits.IS_HBR3_CAPABLE = true,
1053                 .flags.bits.IS_TPS3_CAPABLE = true,
1054                 .flags.bits.IS_TPS4_CAPABLE = true
1055 };
1056
1057 static struct link_encoder *dcn30_link_encoder_create(
1058         const struct encoder_init_data *enc_init_data)
1059 {
1060         struct dcn20_link_encoder *enc20 =
1061                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1062
1063         if (!enc20)
1064                 return NULL;
1065
1066         dcn30_link_encoder_construct(enc20,
1067                         enc_init_data,
1068                         &link_enc_feature,
1069                         &link_enc_regs[enc_init_data->transmitter],
1070                         &link_enc_aux_regs[enc_init_data->channel - 1],
1071                         &link_enc_hpd_regs[enc_init_data->hpd_source],
1072                         &le_shift,
1073                         &le_mask);
1074
1075         return &enc20->enc10.base;
1076 }
1077
1078 static struct panel_cntl *dcn30_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1079 {
1080         struct dce_panel_cntl *panel_cntl =
1081                 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
1082
1083         if (!panel_cntl)
1084                 return NULL;
1085
1086         dce_panel_cntl_construct(panel_cntl,
1087                         init_data,
1088                         &panel_cntl_regs[init_data->inst],
1089                         &panel_cntl_shift,
1090                         &panel_cntl_mask);
1091
1092         return &panel_cntl->base;
1093 }
1094
1095 static void read_dce_straps(
1096         struct dc_context *ctx,
1097         struct resource_straps *straps)
1098 {
1099         generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1100                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1101
1102 }
1103
1104 static struct audio *dcn30_create_audio(
1105                 struct dc_context *ctx, unsigned int inst)
1106 {
1107         return dce_audio_create(ctx, inst,
1108                         &audio_regs[inst], &audio_shift, &audio_mask);
1109 }
1110
1111 static struct vpg *dcn30_vpg_create(
1112         struct dc_context *ctx,
1113         uint32_t inst)
1114 {
1115         struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
1116
1117         if (!vpg3)
1118                 return NULL;
1119
1120         vpg3_construct(vpg3, ctx, inst,
1121                         &vpg_regs[inst],
1122                         &vpg_shift,
1123                         &vpg_mask);
1124
1125         return &vpg3->base;
1126 }
1127
1128 static struct afmt *dcn30_afmt_create(
1129         struct dc_context *ctx,
1130         uint32_t inst)
1131 {
1132         struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1133
1134         if (!afmt3)
1135                 return NULL;
1136
1137         afmt3_construct(afmt3, ctx, inst,
1138                         &afmt_regs[inst],
1139                         &afmt_shift,
1140                         &afmt_mask);
1141
1142         return &afmt3->base;
1143 }
1144
1145 struct stream_encoder *dcn30_stream_encoder_create(
1146         enum engine_id eng_id,
1147         struct dc_context *ctx)
1148 {
1149         struct dcn10_stream_encoder *enc1;
1150         struct vpg *vpg;
1151         struct afmt *afmt;
1152         int vpg_inst;
1153         int afmt_inst;
1154
1155         /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1156         if (eng_id <= ENGINE_ID_DIGF) {
1157                 vpg_inst = eng_id;
1158                 afmt_inst = eng_id;
1159         } else
1160                 return NULL;
1161
1162         enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1163         vpg = dcn30_vpg_create(ctx, vpg_inst);
1164         afmt = dcn30_afmt_create(ctx, afmt_inst);
1165
1166         if (!enc1 || !vpg || !afmt)
1167                 return NULL;
1168
1169         dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1170                                         eng_id, vpg, afmt,
1171                                         &stream_enc_regs[eng_id],
1172                                         &se_shift, &se_mask);
1173
1174         return &enc1->base;
1175 }
1176
1177 struct dce_hwseq *dcn30_hwseq_create(
1178         struct dc_context *ctx)
1179 {
1180         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1181
1182         if (hws) {
1183                 hws->ctx = ctx;
1184                 hws->regs = &hwseq_reg;
1185                 hws->shifts = &hwseq_shift;
1186                 hws->masks = &hwseq_mask;
1187         }
1188         return hws;
1189 }
1190 static const struct resource_create_funcs res_create_funcs = {
1191         .read_dce_straps = read_dce_straps,
1192         .create_audio = dcn30_create_audio,
1193         .create_stream_encoder = dcn30_stream_encoder_create,
1194         .create_hwseq = dcn30_hwseq_create,
1195 };
1196
1197 static const struct resource_create_funcs res_create_maximus_funcs = {
1198         .read_dce_straps = NULL,
1199         .create_audio = NULL,
1200         .create_stream_encoder = NULL,
1201         .create_hwseq = dcn30_hwseq_create,
1202 };
1203
1204 static void dcn30_resource_destruct(struct dcn30_resource_pool *pool)
1205 {
1206         unsigned int i;
1207
1208         for (i = 0; i < pool->base.stream_enc_count; i++) {
1209                 if (pool->base.stream_enc[i] != NULL) {
1210                         if (pool->base.stream_enc[i]->vpg != NULL) {
1211                                 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1212                                 pool->base.stream_enc[i]->vpg = NULL;
1213                         }
1214                         if (pool->base.stream_enc[i]->afmt != NULL) {
1215                                 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1216                                 pool->base.stream_enc[i]->afmt = NULL;
1217                         }
1218                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1219                         pool->base.stream_enc[i] = NULL;
1220                 }
1221         }
1222
1223         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1224                 if (pool->base.dscs[i] != NULL)
1225                         dcn20_dsc_destroy(&pool->base.dscs[i]);
1226         }
1227
1228         if (pool->base.mpc != NULL) {
1229                 kfree(TO_DCN20_MPC(pool->base.mpc));
1230                 pool->base.mpc = NULL;
1231         }
1232         if (pool->base.hubbub != NULL) {
1233                 kfree(pool->base.hubbub);
1234                 pool->base.hubbub = NULL;
1235         }
1236         for (i = 0; i < pool->base.pipe_count; i++) {
1237                 if (pool->base.dpps[i] != NULL)
1238                         dcn30_dpp_destroy(&pool->base.dpps[i]);
1239
1240                 if (pool->base.ipps[i] != NULL)
1241                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1242
1243                 if (pool->base.hubps[i] != NULL) {
1244                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1245                         pool->base.hubps[i] = NULL;
1246                 }
1247
1248                 if (pool->base.irqs != NULL) {
1249                         dal_irq_service_destroy(&pool->base.irqs);
1250                 }
1251         }
1252
1253         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1254                 if (pool->base.engines[i] != NULL)
1255                         dce110_engine_destroy(&pool->base.engines[i]);
1256                 if (pool->base.hw_i2cs[i] != NULL) {
1257                         kfree(pool->base.hw_i2cs[i]);
1258                         pool->base.hw_i2cs[i] = NULL;
1259                 }
1260                 if (pool->base.sw_i2cs[i] != NULL) {
1261                         kfree(pool->base.sw_i2cs[i]);
1262                         pool->base.sw_i2cs[i] = NULL;
1263                 }
1264         }
1265
1266         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1267                 if (pool->base.opps[i] != NULL)
1268                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1269         }
1270
1271         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1272                 if (pool->base.timing_generators[i] != NULL)    {
1273                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1274                         pool->base.timing_generators[i] = NULL;
1275                 }
1276         }
1277
1278         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1279                 if (pool->base.dwbc[i] != NULL) {
1280                         kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1281                         pool->base.dwbc[i] = NULL;
1282                 }
1283                 if (pool->base.mcif_wb[i] != NULL) {
1284                         kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1285                         pool->base.mcif_wb[i] = NULL;
1286                 }
1287         }
1288
1289         for (i = 0; i < pool->base.audio_count; i++) {
1290                 if (pool->base.audios[i])
1291                         dce_aud_destroy(&pool->base.audios[i]);
1292         }
1293
1294         for (i = 0; i < pool->base.clk_src_count; i++) {
1295                 if (pool->base.clock_sources[i] != NULL) {
1296                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1297                         pool->base.clock_sources[i] = NULL;
1298                 }
1299         }
1300
1301         for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1302                 if (pool->base.mpc_lut[i] != NULL) {
1303                         dc_3dlut_func_release(pool->base.mpc_lut[i]);
1304                         pool->base.mpc_lut[i] = NULL;
1305                 }
1306                 if (pool->base.mpc_shaper[i] != NULL) {
1307                         dc_transfer_func_release(pool->base.mpc_shaper[i]);
1308                         pool->base.mpc_shaper[i] = NULL;
1309                 }
1310         }
1311
1312         if (pool->base.dp_clock_source != NULL) {
1313                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1314                 pool->base.dp_clock_source = NULL;
1315         }
1316
1317         for (i = 0; i < pool->base.pipe_count; i++) {
1318                 if (pool->base.multiple_abms[i] != NULL)
1319                         dce_abm_destroy(&pool->base.multiple_abms[i]);
1320         }
1321
1322         if (pool->base.psr != NULL)
1323                 dmub_psr_destroy(&pool->base.psr);
1324
1325         if (pool->base.dccg != NULL)
1326                 dcn_dccg_destroy(&pool->base.dccg);
1327
1328         if (pool->base.oem_device != NULL)
1329                 dal_ddc_service_destroy(&pool->base.oem_device);
1330 }
1331
1332 static struct hubp *dcn30_hubp_create(
1333         struct dc_context *ctx,
1334         uint32_t inst)
1335 {
1336         struct dcn20_hubp *hubp2 =
1337                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1338
1339         if (!hubp2)
1340                 return NULL;
1341
1342         if (hubp3_construct(hubp2, ctx, inst,
1343                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1344                 return &hubp2->base;
1345
1346         BREAK_TO_DEBUGGER();
1347         kfree(hubp2);
1348         return NULL;
1349 }
1350
1351 static bool dcn30_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1352 {
1353         int i;
1354         uint32_t pipe_count = pool->res_cap->num_dwb;
1355
1356         for (i = 0; i < pipe_count; i++) {
1357                 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1358                                                     GFP_KERNEL);
1359
1360                 if (!dwbc30) {
1361                         dm_error("DC: failed to create dwbc30!\n");
1362                         return false;
1363                 }
1364
1365                 dcn30_dwbc_construct(dwbc30, ctx,
1366                                 &dwbc30_regs[i],
1367                                 &dwbc30_shift,
1368                                 &dwbc30_mask,
1369                                 i);
1370
1371                 pool->dwbc[i] = &dwbc30->base;
1372         }
1373         return true;
1374 }
1375
1376 static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1377 {
1378         int i;
1379         uint32_t pipe_count = pool->res_cap->num_dwb;
1380
1381         for (i = 0; i < pipe_count; i++) {
1382                 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1383                                                     GFP_KERNEL);
1384
1385                 if (!mcif_wb30) {
1386                         dm_error("DC: failed to create mcif_wb30!\n");
1387                         return false;
1388                 }
1389
1390                 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1391                                 &mcif_wb30_regs[i],
1392                                 &mcif_wb30_shift,
1393                                 &mcif_wb30_mask,
1394                                 i);
1395
1396                 pool->mcif_wb[i] = &mcif_wb30->base;
1397         }
1398         return true;
1399 }
1400
1401 static struct display_stream_compressor *dcn30_dsc_create(
1402         struct dc_context *ctx, uint32_t inst)
1403 {
1404         struct dcn20_dsc *dsc =
1405                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1406
1407         if (!dsc) {
1408                 BREAK_TO_DEBUGGER();
1409                 return NULL;
1410         }
1411
1412         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1413         return &dsc->base;
1414 }
1415
1416 enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1417 {
1418
1419         return dcn20_add_stream_to_ctx(dc, new_ctx, dc_stream);
1420 }
1421
1422 static void dcn30_destroy_resource_pool(struct resource_pool **pool)
1423 {
1424         struct dcn30_resource_pool *dcn30_pool = TO_DCN30_RES_POOL(*pool);
1425
1426         dcn30_resource_destruct(dcn30_pool);
1427         kfree(dcn30_pool);
1428         *pool = NULL;
1429 }
1430
1431 static struct clock_source *dcn30_clock_source_create(
1432                 struct dc_context *ctx,
1433                 struct dc_bios *bios,
1434                 enum clock_source_id id,
1435                 const struct dce110_clk_src_regs *regs,
1436                 bool dp_clk_src)
1437 {
1438         struct dce110_clk_src *clk_src =
1439                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1440
1441         if (!clk_src)
1442                 return NULL;
1443
1444         if (dcn3_clk_src_construct(clk_src, ctx, bios, id,
1445                         regs, &cs_shift, &cs_mask)) {
1446                 clk_src->base.dp_clk_src = dp_clk_src;
1447                 return &clk_src->base;
1448         }
1449
1450         BREAK_TO_DEBUGGER();
1451         return NULL;
1452 }
1453
1454 int dcn30_populate_dml_pipes_from_context(
1455         struct dc *dc, struct dc_state *context,
1456         display_e2e_pipe_params_st *pipes,
1457         bool fast_validate)
1458 {
1459         int i, pipe_cnt;
1460         struct resource_context *res_ctx = &context->res_ctx;
1461
1462         dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1463
1464         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1465                 if (!res_ctx->pipe_ctx[i].stream)
1466                         continue;
1467
1468                 pipes[pipe_cnt++].pipe.scale_ratio_depth.lb_depth =
1469                         dm_lb_16;
1470         }
1471
1472         return pipe_cnt;
1473 }
1474
1475 void dcn30_populate_dml_writeback_from_context(
1476         struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1477 {
1478         int pipe_cnt, i, j;
1479         double max_calc_writeback_dispclk;
1480         double writeback_dispclk;
1481         struct writeback_st dout_wb;
1482
1483         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1484                 struct dc_stream_state *stream = res_ctx->pipe_ctx[i].stream;
1485
1486                 if (!stream)
1487                         continue;
1488                 max_calc_writeback_dispclk = 0;
1489
1490                 /* Set writeback information */
1491                 pipes[pipe_cnt].dout.wb_enable = 0;
1492                 pipes[pipe_cnt].dout.num_active_wb = 0;
1493                 for (j = 0; j < stream->num_wb_info; j++) {
1494                         struct dc_writeback_info *wb_info = &stream->writeback_info[j];
1495
1496                         if (wb_info->wb_enabled && wb_info->writeback_source_plane &&
1497                                         (wb_info->writeback_source_plane == res_ctx->pipe_ctx[i].plane_state)) {
1498                                 pipes[pipe_cnt].dout.wb_enable = 1;
1499                                 pipes[pipe_cnt].dout.num_active_wb++;
1500                                 dout_wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_en ?
1501                                         wb_info->dwb_params.cnv_params.crop_height :
1502                                         wb_info->dwb_params.cnv_params.src_height;
1503                                 dout_wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_en ?
1504                                         wb_info->dwb_params.cnv_params.crop_width :
1505                                         wb_info->dwb_params.cnv_params.src_width;
1506                                 dout_wb.wb_dst_width = wb_info->dwb_params.dest_width;
1507                                 dout_wb.wb_dst_height = wb_info->dwb_params.dest_height;
1508
1509                                 /* For IP that doesn't support WB scaling, set h/v taps to 1 to avoid DML validation failure */
1510                                 if (dc->dml.ip.writeback_max_hscl_taps > 1) {
1511                                         dout_wb.wb_htaps_luma = wb_info->dwb_params.scaler_taps.h_taps;
1512                                         dout_wb.wb_vtaps_luma = wb_info->dwb_params.scaler_taps.v_taps;
1513                                 } else {
1514                                         dout_wb.wb_htaps_luma = 1;
1515                                         dout_wb.wb_vtaps_luma = 1;
1516                                 }
1517                                 dout_wb.wb_htaps_chroma = 0;
1518                                 dout_wb.wb_vtaps_chroma = 0;
1519                                 dout_wb.wb_hratio = wb_info->dwb_params.cnv_params.crop_en ?
1520                                         (double)wb_info->dwb_params.cnv_params.crop_width /
1521                                                 (double)wb_info->dwb_params.dest_width :
1522                                         (double)wb_info->dwb_params.cnv_params.src_width /
1523                                                 (double)wb_info->dwb_params.dest_width;
1524                                 dout_wb.wb_vratio = wb_info->dwb_params.cnv_params.crop_en ?
1525                                         (double)wb_info->dwb_params.cnv_params.crop_height /
1526                                                 (double)wb_info->dwb_params.dest_height :
1527                                         (double)wb_info->dwb_params.cnv_params.src_height /
1528                                                 (double)wb_info->dwb_params.dest_height;
1529                                 if (wb_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB ||
1530                                         wb_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA)
1531                                         dout_wb.wb_pixel_format = dm_444_64;
1532                                 else
1533                                         dout_wb.wb_pixel_format = dm_444_32;
1534
1535                                 /* Workaround for cases where multiple writebacks are connected to same plane
1536                                  * In which case, need to compute worst case and set the associated writeback parameters
1537                                  * This workaround is necessary due to DML computation assuming only 1 set of writeback
1538                                  * parameters per pipe
1539                                  */
1540                                 writeback_dispclk = dml30_CalculateWriteBackDISPCLK(
1541                                                 dout_wb.wb_pixel_format,
1542                                                 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz,
1543                                                 dout_wb.wb_hratio,
1544                                                 dout_wb.wb_vratio,
1545                                                 dout_wb.wb_htaps_luma,
1546                                                 dout_wb.wb_vtaps_luma,
1547                                                 dout_wb.wb_src_width,
1548                                                 dout_wb.wb_dst_width,
1549                                                 pipes[pipe_cnt].pipe.dest.htotal,
1550                                                 dc->current_state->bw_ctx.dml.ip.writeback_line_buffer_buffer_size);
1551
1552                                 if (writeback_dispclk > max_calc_writeback_dispclk) {
1553                                         max_calc_writeback_dispclk = writeback_dispclk;
1554                                         pipes[pipe_cnt].dout.wb = dout_wb;
1555                                 }
1556                         }
1557                 }
1558
1559                 pipe_cnt++;
1560         }
1561
1562 }
1563
1564 unsigned int dcn30_calc_max_scaled_time(
1565                 unsigned int time_per_pixel,
1566                 enum mmhubbub_wbif_mode mode,
1567                 unsigned int urgent_watermark)
1568 {
1569         unsigned int time_per_byte = 0;
1570         unsigned int total_free_entry = 0xb40;
1571         unsigned int buf_lh_capability;
1572         unsigned int max_scaled_time;
1573
1574         if (mode == PACKED_444) /* packed mode 32 bpp */
1575                 time_per_byte = time_per_pixel/4;
1576         else if (mode == PACKED_444_FP16) /* packed mode 64 bpp */
1577                 time_per_byte = time_per_pixel/8;
1578
1579         if (time_per_byte == 0)
1580                 time_per_byte = 1;
1581
1582         buf_lh_capability = (total_free_entry*time_per_byte*32) >> 6; /* time_per_byte is in u6.6*/
1583         max_scaled_time   = buf_lh_capability - urgent_watermark;
1584         return max_scaled_time;
1585 }
1586
1587 void dcn30_set_mcif_arb_params(
1588                 struct dc *dc,
1589                 struct dc_state *context,
1590                 display_e2e_pipe_params_st *pipes,
1591                 int pipe_cnt)
1592 {
1593         enum mmhubbub_wbif_mode wbif_mode;
1594         struct display_mode_lib *dml = &context->bw_ctx.dml;
1595         struct mcif_arb_params *wb_arb_params;
1596         int i, j, k, dwb_pipe;
1597
1598         /* Writeback MCIF_WB arbitration parameters */
1599         dwb_pipe = 0;
1600         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1601
1602                 if (!context->res_ctx.pipe_ctx[i].stream)
1603                         continue;
1604
1605                 for (j = 0; j < MAX_DWB_PIPES; j++) {
1606                         struct dc_writeback_info *writeback_info = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j];
1607
1608                         if (writeback_info->wb_enabled == false)
1609                                 continue;
1610
1611                         //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
1612                         wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
1613
1614                         if (writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_ARGB ||
1615                                 writeback_info->dwb_params.cnv_params.fc_out_format == DWB_OUT_FORMAT_64BPP_RGBA)
1616                                 wbif_mode = PACKED_444_FP16;
1617                         else
1618                                 wbif_mode = PACKED_444;
1619
1620                         for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
1621                                 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(dml, pipes, pipe_cnt) * 1000;
1622                                 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
1623                         }
1624                         wb_arb_params->time_per_pixel = (1000000 << 6) / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* time_per_pixel should be in u6.6 format */
1625                         wb_arb_params->slice_lines = 32;
1626                         wb_arb_params->arbitration_slice = 2; /* irrelevant since there is no YUV output */
1627                         wb_arb_params->max_scaled_time = dcn30_calc_max_scaled_time(wb_arb_params->time_per_pixel,
1628                                         wbif_mode,
1629                                         wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
1630                         wb_arb_params->dram_speed_change_duration = dml->vba.WritebackAllowDRAMClockChangeEndPosition[j] * pipes[0].clks_cfg.refclk_mhz; /* num_clock_cycles = us * MHz */
1631
1632                         dwb_pipe++;
1633
1634                         if (dwb_pipe >= MAX_DWB_PIPES)
1635                                 return;
1636                 }
1637                 if (dwb_pipe >= MAX_DWB_PIPES)
1638                         return;
1639         }
1640
1641 }
1642
1643 static struct dc_cap_funcs cap_funcs = {
1644         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1645 };
1646
1647 bool dcn30_acquire_post_bldn_3dlut(
1648                 struct resource_context *res_ctx,
1649                 const struct resource_pool *pool,
1650                 int mpcc_id,
1651                 struct dc_3dlut **lut,
1652                 struct dc_transfer_func **shaper)
1653 {
1654         int i;
1655         bool ret = false;
1656         union dc_3dlut_state *state;
1657
1658         ASSERT(*lut == NULL && *shaper == NULL);
1659         *lut = NULL;
1660         *shaper = NULL;
1661
1662         for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1663                 if (!res_ctx->is_mpc_3dlut_acquired[i]) {
1664                         *lut = pool->mpc_lut[i];
1665                         *shaper = pool->mpc_shaper[i];
1666                         state = &pool->mpc_lut[i]->state;
1667                         res_ctx->is_mpc_3dlut_acquired[i] = true;
1668                         state->bits.rmu_idx_valid = 1;
1669                         state->bits.rmu_mux_num = i;
1670                         if (state->bits.rmu_mux_num == 0)
1671                                 state->bits.mpc_rmu0_mux = mpcc_id;
1672                         else if (state->bits.rmu_mux_num == 1)
1673                                 state->bits.mpc_rmu1_mux = mpcc_id;
1674                         else if (state->bits.rmu_mux_num == 2)
1675                                 state->bits.mpc_rmu2_mux = mpcc_id;
1676                         ret = true;
1677                         break;
1678                         }
1679                 }
1680         return ret;
1681 }
1682
1683 bool dcn30_release_post_bldn_3dlut(
1684                 struct resource_context *res_ctx,
1685                 const struct resource_pool *pool,
1686                 struct dc_3dlut **lut,
1687                 struct dc_transfer_func **shaper)
1688 {
1689         int i;
1690         bool ret = false;
1691
1692         for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1693                 if (pool->mpc_lut[i] == *lut && pool->mpc_shaper[i] == *shaper) {
1694                         res_ctx->is_mpc_3dlut_acquired[i] = false;
1695                         pool->mpc_lut[i]->state.raw = 0;
1696                         *lut = NULL;
1697                         *shaper = NULL;
1698                         ret = true;
1699                         break;
1700                 }
1701         }
1702         return ret;
1703 }
1704
1705 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
1706 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
1707
1708 static bool is_soc_bounding_box_valid(struct dc *dc)
1709 {
1710         uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1711
1712         if (ASICREV_IS_SIENNA_CICHLID_P(hw_internal_rev))
1713                 return true;
1714
1715         return false;
1716 }
1717
1718 static bool init_soc_bounding_box(struct dc *dc,
1719                                   struct dcn30_resource_pool *pool)
1720 {
1721         struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_0_soc;
1722         struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_0_ip;
1723
1724         DC_LOGGER_INIT(dc->ctx->logger);
1725
1726         if (!is_soc_bounding_box_valid(dc)) {
1727                 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
1728                 return false;
1729         }
1730
1731         loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
1732         loaded_ip->max_num_dpp = pool->base.pipe_count;
1733         loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
1734         dcn20_patch_bounding_box(dc, loaded_bb);
1735
1736         if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
1737                 struct bp_soc_bb_info bb_info = {0};
1738
1739                 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
1740                         if (bb_info.dram_clock_change_latency_100ns > 0)
1741                                 dcn3_0_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;
1742
1743                         if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
1744                                 dcn3_0_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;
1745
1746                         if (bb_info.dram_sr_exit_latency_100ns > 0)
1747                                 dcn3_0_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
1748                 }
1749         }
1750
1751         return true;
1752 }
1753
1754 static bool dcn30_split_stream_for_mpc_or_odm(
1755                 const struct dc *dc,
1756                 struct resource_context *res_ctx,
1757                 struct pipe_ctx *pri_pipe,
1758                 struct pipe_ctx *sec_pipe,
1759                 bool odm)
1760 {
1761         int pipe_idx = sec_pipe->pipe_idx;
1762         const struct resource_pool *pool = dc->res_pool;
1763
1764         *sec_pipe = *pri_pipe;
1765
1766         sec_pipe->pipe_idx = pipe_idx;
1767         sec_pipe->plane_res.mi = pool->mis[pipe_idx];
1768         sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
1769         sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
1770         sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
1771         sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
1772         sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
1773         sec_pipe->stream_res.dsc = NULL;
1774         if (odm) {
1775                 if (pri_pipe->next_odm_pipe) {
1776                         ASSERT(pri_pipe->next_odm_pipe != sec_pipe);
1777                         sec_pipe->next_odm_pipe = pri_pipe->next_odm_pipe;
1778                         sec_pipe->next_odm_pipe->prev_odm_pipe = sec_pipe;
1779                 }
1780                 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) {
1781                         pri_pipe->top_pipe->next_odm_pipe->bottom_pipe = sec_pipe;
1782                         sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe;
1783                 }
1784                 if (pri_pipe->bottom_pipe && pri_pipe->bottom_pipe->next_odm_pipe) {
1785                         pri_pipe->bottom_pipe->next_odm_pipe->top_pipe = sec_pipe;
1786                         sec_pipe->bottom_pipe = pri_pipe->bottom_pipe->next_odm_pipe;
1787                 }
1788                 pri_pipe->next_odm_pipe = sec_pipe;
1789                 sec_pipe->prev_odm_pipe = pri_pipe;
1790                 ASSERT(sec_pipe->top_pipe == NULL);
1791
1792                 if (!sec_pipe->top_pipe)
1793                         sec_pipe->stream_res.opp = pool->opps[pipe_idx];
1794                 else
1795                         sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp;
1796                 if (sec_pipe->stream->timing.flags.DSC == 1) {
1797                         dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx);
1798                         ASSERT(sec_pipe->stream_res.dsc);
1799                         if (sec_pipe->stream_res.dsc == NULL)
1800                                 return false;
1801                 }
1802         } else {
1803                 if (pri_pipe->bottom_pipe) {
1804                         ASSERT(pri_pipe->bottom_pipe != sec_pipe);
1805                         sec_pipe->bottom_pipe = pri_pipe->bottom_pipe;
1806                         sec_pipe->bottom_pipe->top_pipe = sec_pipe;
1807                 }
1808                 pri_pipe->bottom_pipe = sec_pipe;
1809                 sec_pipe->top_pipe = pri_pipe;
1810
1811                 ASSERT(pri_pipe->plane_state);
1812         }
1813
1814         return true;
1815 }
1816
1817 static struct pipe_ctx *dcn30_find_split_pipe(
1818                 struct dc *dc,
1819                 struct dc_state *context,
1820                 int old_index)
1821 {
1822         struct pipe_ctx *pipe = NULL;
1823         int i;
1824
1825         if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
1826                 pipe = &context->res_ctx.pipe_ctx[old_index];
1827                 pipe->pipe_idx = old_index;
1828         }
1829
1830         if (!pipe)
1831                 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1832                         if (dc->current_state->res_ctx.pipe_ctx[i].top_pipe == NULL
1833                                         && dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
1834                                 if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1835                                         pipe = &context->res_ctx.pipe_ctx[i];
1836                                         pipe->pipe_idx = i;
1837                                         break;
1838                                 }
1839                         }
1840                 }
1841
1842         /*
1843          * May need to fix pipes getting tossed from 1 opp to another on flip
1844          * Add for debugging transient underflow during topology updates:
1845          * ASSERT(pipe);
1846          */
1847         if (!pipe)
1848                 for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
1849                         if (context->res_ctx.pipe_ctx[i].stream == NULL) {
1850                                 pipe = &context->res_ctx.pipe_ctx[i];
1851                                 pipe->pipe_idx = i;
1852                                 break;
1853                         }
1854                 }
1855
1856         return pipe;
1857 }
1858
1859 static noinline bool dcn30_internal_validate_bw(
1860                 struct dc *dc,
1861                 struct dc_state *context,
1862                 display_e2e_pipe_params_st *pipes,
1863                 int *pipe_cnt_out,
1864                 int *vlevel_out,
1865                 bool fast_validate)
1866 {
1867         bool out = false;
1868         bool repopulate_pipes = false;
1869         int split[MAX_PIPES] = { 0 };
1870         bool merge[MAX_PIPES] = { false };
1871         bool newly_split[MAX_PIPES] = { false };
1872         int pipe_cnt, i, pipe_idx, vlevel;
1873         struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1874
1875         ASSERT(pipes);
1876         if (!pipes)
1877                 return false;
1878
1879         dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
1880         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1881
1882         DC_FP_START();
1883         if (!pipe_cnt) {
1884                 out = true;
1885                 goto validate_out;
1886         }
1887
1888         dml_log_pipe_params(&context->bw_ctx.dml, pipes, pipe_cnt);
1889
1890         if (!fast_validate) {
1891                 /*
1892                  * DML favors voltage over p-state, but we're more interested in
1893                  * supporting p-state over voltage. We can't support p-state in
1894                  * prefetch mode > 0 so try capping the prefetch mode to start.
1895                  */
1896                 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1897                         dm_allow_self_refresh_and_mclk_switch;
1898                 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1899                 /* This may adjust vlevel and maxMpcComb */
1900                 if (vlevel < context->bw_ctx.dml.soc.num_states)
1901                         vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1902         }
1903         if (fast_validate || vlevel == context->bw_ctx.dml.soc.num_states ||
1904                         vba->DRAMClockChangeSupport[vlevel][vba->maxMpcComb] == dm_dram_clock_change_unsupported) {
1905                 /*
1906                  * If mode is unsupported or there's still no p-state support then
1907                  * fall back to favoring voltage.
1908                  *
1909                  * We don't actually support prefetch mode 2, so require that we
1910                  * at least support prefetch mode 1.
1911                  */
1912                 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1913                         dm_allow_self_refresh;
1914
1915                 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1916                 if (vlevel < context->bw_ctx.dml.soc.num_states) {
1917                         memset(split, 0, sizeof(split));
1918                         memset(merge, 0, sizeof(merge));
1919                         vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
1920                 }
1921         }
1922
1923         dml_log_mode_support_params(&context->bw_ctx.dml);
1924
1925         if (vlevel == context->bw_ctx.dml.soc.num_states)
1926                 goto validate_fail;
1927
1928         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1929                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1930                 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
1931
1932                 if (!pipe->stream)
1933                         continue;
1934
1935                 /* We only support full screen mpo with ODM */
1936                 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
1937                                 && pipe->plane_state && mpo_pipe
1938                                 && memcmp(&mpo_pipe->plane_res.scl_data.recout,
1939                                                 &pipe->plane_res.scl_data.recout,
1940                                                 sizeof(struct rect)) != 0) {
1941                         ASSERT(mpo_pipe->plane_state != pipe->plane_state);
1942                         goto validate_fail;
1943                 }
1944                 pipe_idx++;
1945         }
1946
1947         /* merge pipes if necessary */
1948         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1949                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1950
1951                 /*skip pipes that don't need merging*/
1952                 if (!merge[i])
1953                         continue;
1954
1955                 /* if ODM merge we ignore mpc tree, mpo pipes will have their own flags */
1956                 if (pipe->prev_odm_pipe) {
1957                         /*split off odm pipe*/
1958                         pipe->prev_odm_pipe->next_odm_pipe = pipe->next_odm_pipe;
1959                         if (pipe->next_odm_pipe)
1960                                 pipe->next_odm_pipe->prev_odm_pipe = pipe->prev_odm_pipe;
1961
1962                         pipe->bottom_pipe = NULL;
1963                         pipe->next_odm_pipe = NULL;
1964                         pipe->plane_state = NULL;
1965                         pipe->stream = NULL;
1966                         pipe->top_pipe = NULL;
1967                         pipe->prev_odm_pipe = NULL;
1968                         if (pipe->stream_res.dsc)
1969                                 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc);
1970                         memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1971                         memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1972                         repopulate_pipes = true;
1973                 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
1974                         struct pipe_ctx *top_pipe = pipe->top_pipe;
1975                         struct pipe_ctx *bottom_pipe = pipe->bottom_pipe;
1976
1977                         top_pipe->bottom_pipe = bottom_pipe;
1978                         if (bottom_pipe)
1979                                 bottom_pipe->top_pipe = top_pipe;
1980
1981                         pipe->top_pipe = NULL;
1982                         pipe->bottom_pipe = NULL;
1983                         pipe->plane_state = NULL;
1984                         pipe->stream = NULL;
1985                         memset(&pipe->plane_res, 0, sizeof(pipe->plane_res));
1986                         memset(&pipe->stream_res, 0, sizeof(pipe->stream_res));
1987                         repopulate_pipes = true;
1988                 } else
1989                         ASSERT(0); /* Should never try to merge master pipe */
1990
1991         }
1992
1993         for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
1994                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1995                 struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i];
1996                 struct pipe_ctx *hsplit_pipe = NULL;
1997                 bool odm;
1998                 int old_index = -1;
1999
2000                 if (!pipe->stream || newly_split[i])
2001                         continue;
2002
2003                 pipe_idx++;
2004                 odm = vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled;
2005
2006                 if (!pipe->plane_state && !odm)
2007                         continue;
2008
2009                 if (split[i]) {
2010                         if (odm) {
2011                                 if (split[i] == 4 && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe)
2012                                         old_index = old_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
2013                                 else if (old_pipe->next_odm_pipe)
2014                                         old_index = old_pipe->next_odm_pipe->pipe_idx;
2015                         } else {
2016                                 if (split[i] == 4 && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
2017                                                 old_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2018                                         old_index = old_pipe->bottom_pipe->bottom_pipe->pipe_idx;
2019                                 else if (old_pipe->bottom_pipe &&
2020                                                 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2021                                         old_index = old_pipe->bottom_pipe->pipe_idx;
2022                         }
2023                         hsplit_pipe = dcn30_find_split_pipe(dc, context, old_index);
2024                         ASSERT(hsplit_pipe);
2025                         if (!hsplit_pipe)
2026                                 goto validate_fail;
2027
2028                         if (!dcn30_split_stream_for_mpc_or_odm(
2029                                         dc, &context->res_ctx,
2030                                         pipe, hsplit_pipe, odm))
2031                                 goto validate_fail;
2032
2033                         newly_split[hsplit_pipe->pipe_idx] = true;
2034                         repopulate_pipes = true;
2035                 }
2036                 if (split[i] == 4) {
2037                         struct pipe_ctx *pipe_4to1;
2038
2039                         if (odm && old_pipe->next_odm_pipe)
2040                                 old_index = old_pipe->next_odm_pipe->pipe_idx;
2041                         else if (!odm && old_pipe->bottom_pipe &&
2042                                                 old_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2043                                 old_index = old_pipe->bottom_pipe->pipe_idx;
2044                         else
2045                                 old_index = -1;
2046                         pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
2047                         ASSERT(pipe_4to1);
2048                         if (!pipe_4to1)
2049                                 goto validate_fail;
2050                         if (!dcn30_split_stream_for_mpc_or_odm(
2051                                         dc, &context->res_ctx,
2052                                         pipe, pipe_4to1, odm))
2053                                 goto validate_fail;
2054                         newly_split[pipe_4to1->pipe_idx] = true;
2055
2056                         if (odm && old_pipe->next_odm_pipe && old_pipe->next_odm_pipe->next_odm_pipe
2057                                         && old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe)
2058                                 old_index = old_pipe->next_odm_pipe->next_odm_pipe->next_odm_pipe->pipe_idx;
2059                         else if (!odm && old_pipe->bottom_pipe && old_pipe->bottom_pipe->bottom_pipe &&
2060                                         old_pipe->bottom_pipe->bottom_pipe->bottom_pipe &&
2061                                         old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->plane_state == old_pipe->plane_state)
2062                                 old_index = old_pipe->bottom_pipe->bottom_pipe->bottom_pipe->pipe_idx;
2063                         else
2064                                 old_index = -1;
2065                         pipe_4to1 = dcn30_find_split_pipe(dc, context, old_index);
2066                         ASSERT(pipe_4to1);
2067                         if (!pipe_4to1)
2068                                 goto validate_fail;
2069                         if (!dcn30_split_stream_for_mpc_or_odm(
2070                                         dc, &context->res_ctx,
2071                                         hsplit_pipe, pipe_4to1, odm))
2072                                 goto validate_fail;
2073                         newly_split[pipe_4to1->pipe_idx] = true;
2074                 }
2075                 if (odm)
2076                         dcn20_build_mapped_resource(dc, context, pipe->stream);
2077         }
2078
2079         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2080                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2081
2082                 if (pipe->plane_state) {
2083                         if (!resource_build_scaling_params(pipe))
2084                                 goto validate_fail;
2085                 }
2086         }
2087
2088         /* Actual dsc count per stream dsc validation*/
2089         if (!dcn20_validate_dsc(dc, context)) {
2090                 vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE;
2091                 goto validate_fail;
2092         }
2093
2094         if (repopulate_pipes)
2095                 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
2096         *vlevel_out = vlevel;
2097         *pipe_cnt_out = pipe_cnt;
2098
2099         out = true;
2100         goto validate_out;
2101
2102 validate_fail:
2103         out = false;
2104
2105 validate_out:
2106         DC_FP_END();
2107         return out;
2108 }
2109
2110 /*
2111  * This must be noinline to ensure anything that deals with FP registers
2112  * is contained within this call; previously our compiling with hard-float
2113  * would result in fp instructions being emitted outside of the boundaries
2114  * of the DC_FP_START/END macros, which makes sense as the compiler has no
2115  * idea about what is wrapped and what is not
2116  *
2117  * This is largely just a workaround to avoid breakage introduced with 5.6,
2118  * ideally all fp-using code should be moved into its own file, only that
2119  * should be compiled with hard-float, and all code exported from there
2120  * should be strictly wrapped with DC_FP_START/END
2121  */
2122 static noinline void dcn30_calculate_wm_and_dlg_fp(
2123                 struct dc *dc, struct dc_state *context,
2124                 display_e2e_pipe_params_st *pipes,
2125                 int pipe_cnt,
2126                 int vlevel)
2127 {
2128         int i, pipe_idx;
2129         double dcfclk = context->bw_ctx.dml.vba.DCFCLKState[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2130         bool pstate_en = context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] !=
2131                         dm_dram_clock_change_unsupported;
2132
2133         if (context->bw_ctx.dml.soc.min_dcfclk > dcfclk)
2134                 dcfclk = context->bw_ctx.dml.soc.min_dcfclk;
2135
2136         pipes[0].clks_cfg.voltage = vlevel;
2137         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
2138         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2139
2140         /* Set B:
2141          * DCFCLK: 1GHz or min required above 1GHz
2142          * FCLK/UCLK: Max
2143          */
2144         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) {
2145                 if (vlevel == 0) {
2146                         pipes[0].clks_cfg.voltage = 1;
2147                         pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz;
2148                 }
2149                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.pstate_latency_us;
2150                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_enter_plus_exit_time_us;
2151                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_input.sr_exit_time_us;
2152         }
2153         context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2154         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2155         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2156         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2157         context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2158         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2159         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2160         context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2161
2162         pipes[0].clks_cfg.voltage = vlevel;
2163         pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
2164
2165         /* Set D:
2166          * DCFCLK: Min Required
2167          * FCLK(proportional to UCLK): 1GHz or Max
2168          * MALL stutter, sr_enter_exit = 4, sr_exit = 2us
2169          */
2170         /*
2171         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].valid) {
2172                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.pstate_latency_us;
2173                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_enter_plus_exit_time_us;
2174                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_D].dml_input.sr_exit_time_us;
2175         }
2176         context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2177         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2178         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2179         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2180         context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2181         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2182         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2183         context->bw_ctx.bw.dcn.watermarks.d.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2184         */
2185
2186         /* Set C:
2187          * DCFCLK: Min Required
2188          * FCLK(proportional to UCLK): 1GHz or Max
2189          * pstate latency overridden to 5us
2190          */
2191         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) {
2192                 unsigned int min_dram_speed_mts = context->bw_ctx.dml.vba.DRAMSpeed;
2193                 unsigned int min_dram_speed_mts_margin = 160;
2194
2195                 if (context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb] == dm_dram_clock_change_unsupported)
2196                         min_dram_speed_mts = dc->clk_mgr->bw_params->clk_table.entries[dc->clk_mgr->bw_params->clk_table.num_entries - 1].memclk_mhz * 16;
2197
2198                 /* find largest table entry that is lower than dram speed, but lower than DPM0 still uses DPM0 */
2199                 for (i = 3; i > 0; i--)
2200                         if (min_dram_speed_mts + min_dram_speed_mts_margin > dc->clk_mgr->bw_params->dummy_pstate_table[i].dram_speed_mts)
2201                                 break;
2202
2203                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->dummy_pstate_table[i].dummy_pstate_latency_us;
2204                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_enter_plus_exit_time_us;
2205                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].dml_input.sr_exit_time_us;
2206         }
2207         context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2208         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2209         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2210         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2211         context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2212         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2213         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2214         context->bw_ctx.bw.dcn.watermarks.c.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2215
2216         if (!pstate_en) {
2217                 /* The only difference between A and C is p-state latency, if p-state is not supported we want to
2218                  * calculate DLG based on dummy p-state latency, and max out the set A p-state watermark
2219                  */
2220                 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c;
2221                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0;
2222         } else {
2223                 /* Set A:
2224                  * DCFCLK: Min Required
2225                  * FCLK(proportional to UCLK): 1GHz or Max
2226                  *
2227                  * Set A calculated last so that following calculations are based on Set A
2228                  */
2229                 dc->res_pool->funcs->update_soc_for_wm_a(dc, context);
2230                 context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2231                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2232                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2233                 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2234                 context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2235                 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2236                 context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2237                 context->bw_ctx.bw.dcn.watermarks.a.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2238         }
2239
2240         context->perf_params.stutter_period_us = context->bw_ctx.dml.vba.StutterPeriod;
2241
2242         /* Make set D = set A until set D is enabled */
2243         context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
2244
2245         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2246                 if (!context->res_ctx.pipe_ctx[i].stream)
2247                         continue;
2248
2249                 pipes[pipe_idx].clks_cfg.dispclk_mhz = get_dispclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt);
2250                 pipes[pipe_idx].clks_cfg.dppclk_mhz = get_dppclk_calculated(&context->bw_ctx.dml, pipes, pipe_cnt, pipe_idx);
2251
2252                 if (dc->config.forced_clocks) {
2253                         pipes[pipe_idx].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2254                         pipes[pipe_idx].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2255                 }
2256                 if (dc->debug.min_disp_clk_khz > pipes[pipe_idx].clks_cfg.dispclk_mhz * 1000)
2257                         pipes[pipe_idx].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2258                 if (dc->debug.min_dpp_clk_khz > pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
2259                         pipes[pipe_idx].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2260
2261                 pipe_idx++;
2262         }
2263
2264         dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
2265
2266         if (!pstate_en)
2267                 /* Restore full p-state latency */
2268                 context->bw_ctx.dml.soc.dram_clock_change_latency_us =
2269                                 dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2270 }
2271
2272 void dcn30_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
2273 {
2274         if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) {
2275                 context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;
2276                 context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;
2277                 context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;
2278         }
2279 }
2280
2281 void dcn30_calculate_wm_and_dlg(
2282                 struct dc *dc, struct dc_state *context,
2283                 display_e2e_pipe_params_st *pipes,
2284                 int pipe_cnt,
2285                 int vlevel)
2286 {
2287         DC_FP_START();
2288         dcn30_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
2289         DC_FP_END();
2290 }
2291
2292 bool dcn30_validate_bandwidth(struct dc *dc,
2293                 struct dc_state *context,
2294                 bool fast_validate)
2295 {
2296         bool out = false;
2297
2298         BW_VAL_TRACE_SETUP();
2299
2300         int vlevel = 0;
2301         int pipe_cnt = 0;
2302         display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
2303         DC_LOGGER_INIT(dc->ctx->logger);
2304
2305         BW_VAL_TRACE_COUNT();
2306
2307         out = dcn30_internal_validate_bw(dc, context, pipes, &pipe_cnt, &vlevel, fast_validate);
2308
2309         if (pipe_cnt == 0)
2310                 goto validate_out;
2311
2312         if (!out)
2313                 goto validate_fail;
2314
2315         BW_VAL_TRACE_END_VOLTAGE_LEVEL();
2316
2317         if (fast_validate) {
2318                 BW_VAL_TRACE_SKIP(fast);
2319                 goto validate_out;
2320         }
2321
2322         dc->res_pool->funcs->calculate_wm_and_dlg(dc, context, pipes, pipe_cnt, vlevel);
2323
2324         BW_VAL_TRACE_END_WATERMARKS();
2325
2326         goto validate_out;
2327
2328 validate_fail:
2329         DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
2330                 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
2331
2332         BW_VAL_TRACE_SKIP(fail);
2333         out = false;
2334
2335 validate_out:
2336         kfree(pipes);
2337
2338         BW_VAL_TRACE_FINISH();
2339
2340         return out;
2341 }
2342
2343 /*
2344  * This must be noinline to ensure anything that deals with FP registers
2345  * is contained within this call; previously our compiling with hard-float
2346  * would result in fp instructions being emitted outside of the boundaries
2347  * of the DC_FP_START/END macros, which makes sense as the compiler has no
2348  * idea about what is wrapped and what is not
2349  *
2350  * This is largely just a workaround to avoid breakage introduced with 5.6,
2351  * ideally all fp-using code should be moved into its own file, only that
2352  * should be compiled with hard-float, and all code exported from there
2353  * should be strictly wrapped with DC_FP_START/END
2354  */
2355 static noinline void dcn30_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
2356                 unsigned int *optimal_dcfclk,
2357                 unsigned int *optimal_fclk)
2358 {
2359        double bw_from_dram, bw_from_dram1, bw_from_dram2;
2360
2361        bw_from_dram1 = uclk_mts * dcn3_0_soc.num_chans *
2362                 dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_dram_bw_use_normal_percent / 100);
2363        bw_from_dram2 = uclk_mts * dcn3_0_soc.num_chans *
2364                 dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100);
2365
2366        bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
2367
2368        if (optimal_fclk)
2369                *optimal_fclk = bw_from_dram /
2370                (dcn3_0_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100));
2371
2372        if (optimal_dcfclk)
2373                *optimal_dcfclk =  bw_from_dram /
2374                (dcn3_0_soc.return_bus_width_bytes * (dcn3_0_soc.max_avg_sdp_bw_use_normal_percent / 100));
2375 }
2376
2377 void dcn30_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
2378 {
2379         unsigned int i, j;
2380         unsigned int num_states = 0;
2381
2382         unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
2383         unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
2384         unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
2385         unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
2386
2387         unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200};
2388         unsigned int num_dcfclk_sta_targets = 4;
2389         unsigned int num_uclk_states;
2390
2391         if (dc->ctx->dc_bios->vram_info.num_chans)
2392                 dcn3_0_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
2393
2394         if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
2395                 dcn3_0_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
2396
2397         dcn3_0_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2398         dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
2399
2400         if (bw_params->clk_table.entries[0].memclk_mhz) {
2401
2402                 if (bw_params->clk_table.entries[1].dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2403                         // If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array
2404                         dcfclk_sta_targets[num_dcfclk_sta_targets] = bw_params->clk_table.entries[1].dcfclk_mhz;
2405                         num_dcfclk_sta_targets++;
2406                 } else if (bw_params->clk_table.entries[1].dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
2407                         // If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates
2408                         for (i = 0; i < num_dcfclk_sta_targets; i++) {
2409                                 if (dcfclk_sta_targets[i] > bw_params->clk_table.entries[1].dcfclk_mhz) {
2410                                         dcfclk_sta_targets[i] = bw_params->clk_table.entries[1].dcfclk_mhz;
2411                                         break;
2412                                 }
2413                         }
2414                         // Update size of array since we "removed" duplicates
2415                         num_dcfclk_sta_targets = i + 1;
2416                 }
2417
2418                 num_uclk_states = bw_params->clk_table.num_entries;
2419
2420                 // Calculate optimal dcfclk for each uclk
2421                 for (i = 0; i < num_uclk_states; i++) {
2422                         DC_FP_START();
2423                         dcn30_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
2424                                         &optimal_dcfclk_for_uclk[i], NULL);
2425                         DC_FP_END();
2426                         if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
2427                                 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
2428                         }
2429                 }
2430
2431                 // Calculate optimal uclk for each dcfclk sta target
2432                 for (i = 0; i < num_dcfclk_sta_targets; i++) {
2433                         for (j = 0; j < num_uclk_states; j++) {
2434                                 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
2435                                         optimal_uclk_for_dcfclk_sta_targets[i] =
2436                                                         bw_params->clk_table.entries[j].memclk_mhz * 16;
2437                                         break;
2438                                 }
2439                         }
2440                 }
2441
2442                 i = 0;
2443                 j = 0;
2444                 // create the final dcfclk and uclk table
2445                 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
2446                         if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
2447                                 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2448                                 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2449                         } else {
2450                                 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= bw_params->clk_table.entries[1].dcfclk_mhz) {
2451                                         dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2452                                         dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2453                                 } else {
2454                                         j = num_uclk_states;
2455                                 }
2456                         }
2457                 }
2458
2459                 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
2460                         dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2461                         dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
2462                 }
2463
2464                 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
2465                                 optimal_dcfclk_for_uclk[j] <= bw_params->clk_table.entries[1].dcfclk_mhz) {
2466                         dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2467                         dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
2468                 }
2469
2470                 for (i = 0; i < dcn3_0_soc.num_states; i++) {
2471                         dcn3_0_soc.clock_limits[i].state = i;
2472                         dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
2473                         dcn3_0_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
2474                         dcn3_0_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
2475
2476                         /* Fill all states with max values of all other clocks */
2477                         dcn3_0_soc.clock_limits[i].dispclk_mhz = bw_params->clk_table.entries[1].dispclk_mhz;
2478                         dcn3_0_soc.clock_limits[i].dppclk_mhz  = bw_params->clk_table.entries[1].dppclk_mhz;
2479                         dcn3_0_soc.clock_limits[i].phyclk_mhz  = bw_params->clk_table.entries[1].phyclk_mhz;
2480                         dcn3_0_soc.clock_limits[i].dtbclk_mhz = dcn3_0_soc.clock_limits[0].dtbclk_mhz;
2481                         /* These clocks cannot come from bw_params, always fill from dcn3_0_soc[1] */
2482                         /* FCLK, PHYCLK_D18, SOCCLK, DSCCLK */
2483                         dcn3_0_soc.clock_limits[i].phyclk_d18_mhz = dcn3_0_soc.clock_limits[0].phyclk_d18_mhz;
2484                         dcn3_0_soc.clock_limits[i].socclk_mhz = dcn3_0_soc.clock_limits[0].socclk_mhz;
2485                         dcn3_0_soc.clock_limits[i].dscclk_mhz = dcn3_0_soc.clock_limits[0].dscclk_mhz;
2486                 }
2487                 /* re-init DML with updated bb */
2488                 dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2489                 if (dc->current_state)
2490                         dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2491         }
2492
2493         /* re-init DML with updated bb */
2494         dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2495         if (dc->current_state)
2496                 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2497 }
2498
2499 static const struct resource_funcs dcn30_res_pool_funcs = {
2500         .destroy = dcn30_destroy_resource_pool,
2501         .link_enc_create = dcn30_link_encoder_create,
2502         .panel_cntl_create = dcn30_panel_cntl_create,
2503         .validate_bandwidth = dcn30_validate_bandwidth,
2504         .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
2505         .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
2506         .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
2507         .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
2508         .add_stream_to_ctx = dcn30_add_stream_to_ctx,
2509         .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2510         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2511         .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
2512         .set_mcif_arb_params = dcn30_set_mcif_arb_params,
2513         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
2514         .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
2515         .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
2516         .update_bw_bounding_box = dcn30_update_bw_bounding_box,
2517         .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2518 };
2519
2520 #define CTX ctx
2521
2522 #define REG(reg_name) \
2523         (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
2524
2525 static uint32_t read_pipe_fuses(struct dc_context *ctx)
2526 {
2527         uint32_t value = REG_READ(CC_DC_PIPE_DIS);
2528         /* Support for max 6 pipes */
2529         value = value & 0x3f;
2530         return value;
2531 }
2532
2533 static bool dcn30_resource_construct(
2534         uint8_t num_virtual_links,
2535         struct dc *dc,
2536         struct dcn30_resource_pool *pool)
2537 {
2538         int i;
2539         struct dc_context *ctx = dc->ctx;
2540         struct irq_service_init_data init_data;
2541         struct ddc_service_init_data ddc_init_data;
2542         uint32_t pipe_fuses = read_pipe_fuses(ctx);
2543         uint32_t num_pipes = 0;
2544
2545         if (!(pipe_fuses == 0 || pipe_fuses == 0x3e)) {
2546                 BREAK_TO_DEBUGGER();
2547                 dm_error("DC: Unexpected fuse recipe for navi2x !\n");
2548                 /* fault to single pipe */
2549                 pipe_fuses = 0x3e;
2550         }
2551
2552         DC_FP_START();
2553
2554         ctx->dc_bios->regs = &bios_regs;
2555
2556         pool->base.res_cap = &res_cap_dcn3;
2557
2558         pool->base.funcs = &dcn30_res_pool_funcs;
2559
2560         /*************************************************
2561          *  Resource + asic cap harcoding                *
2562          *************************************************/
2563         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2564         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
2565         pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
2566         dc->caps.max_downscale_ratio = 600;
2567         dc->caps.i2c_speed_in_khz = 100;
2568         dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
2569         dc->caps.max_cursor_size = 256;
2570         dc->caps.min_horizontal_blanking_period = 80;
2571         dc->caps.dmdata_alloc_size = 2048;
2572         dc->caps.mall_size_per_mem_channel = 8;
2573         /* total size = mall per channel * num channels * 1024 * 1024 */
2574         dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
2575         dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
2576
2577         dc->caps.max_slave_planes = 1;
2578         dc->caps.max_slave_yuv_planes = 1;
2579         dc->caps.max_slave_rgb_planes = 1;
2580         dc->caps.post_blend_color_processing = true;
2581         dc->caps.force_dp_tps4_for_cp2520 = true;
2582         dc->caps.extended_aux_timeout_support = true;
2583         dc->caps.dmcub_support = true;
2584
2585         /* Color pipeline capabilities */
2586         dc->caps.color.dpp.dcn_arch = 1;
2587         dc->caps.color.dpp.input_lut_shared = 0;
2588         dc->caps.color.dpp.icsc = 1;
2589         dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
2590         dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2591         dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2592         dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
2593         dc->caps.color.dpp.dgam_rom_caps.pq = 1;
2594         dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
2595         dc->caps.color.dpp.post_csc = 1;
2596         dc->caps.color.dpp.gamma_corr = 1;
2597         dc->caps.color.dpp.dgam_rom_for_yuv = 0;
2598
2599         dc->caps.color.dpp.hw_3d_lut = 1;
2600         dc->caps.color.dpp.ogam_ram = 1;
2601         // no OGAM ROM on DCN3
2602         dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2603         dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2604         dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2605         dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2606         dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2607         dc->caps.color.dpp.ocsc = 0;
2608
2609         dc->caps.color.mpc.gamut_remap = 1;
2610         dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //3
2611         dc->caps.color.mpc.ogam_ram = 1;
2612         dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2613         dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2614         dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2615         dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2616         dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2617         dc->caps.color.mpc.ocsc = 1;
2618
2619         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2620                 dc->debug = debug_defaults_drv;
2621         else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2622                 dc->debug = debug_defaults_diags;
2623         } else
2624                 dc->debug = debug_defaults_diags;
2625         // Init the vm_helper
2626         if (dc->vm_helper)
2627                 vm_helper_init(dc->vm_helper, 16);
2628
2629         /*************************************************
2630          *  Create resources                             *
2631          *************************************************/
2632
2633         /* Clock Sources for Pixel Clock*/
2634         pool->base.clock_sources[DCN30_CLK_SRC_PLL0] =
2635                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2636                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
2637                                 &clk_src_regs[0], false);
2638         pool->base.clock_sources[DCN30_CLK_SRC_PLL1] =
2639                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2640                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
2641                                 &clk_src_regs[1], false);
2642         pool->base.clock_sources[DCN30_CLK_SRC_PLL2] =
2643                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2644                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
2645                                 &clk_src_regs[2], false);
2646         pool->base.clock_sources[DCN30_CLK_SRC_PLL3] =
2647                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2648                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
2649                                 &clk_src_regs[3], false);
2650         pool->base.clock_sources[DCN30_CLK_SRC_PLL4] =
2651                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2652                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
2653                                 &clk_src_regs[4], false);
2654         pool->base.clock_sources[DCN30_CLK_SRC_PLL5] =
2655                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2656                                 CLOCK_SOURCE_COMBO_PHY_PLL5,
2657                                 &clk_src_regs[5], false);
2658
2659         pool->base.clk_src_count = DCN30_CLK_SRC_TOTAL;
2660
2661         /* todo: not reuse phy_pll registers */
2662         pool->base.dp_clock_source =
2663                         dcn30_clock_source_create(ctx, ctx->dc_bios,
2664                                 CLOCK_SOURCE_ID_DP_DTO,
2665                                 &clk_src_regs[0], true);
2666
2667         for (i = 0; i < pool->base.clk_src_count; i++) {
2668                 if (pool->base.clock_sources[i] == NULL) {
2669                         dm_error("DC: failed to create clock sources!\n");
2670                         BREAK_TO_DEBUGGER();
2671                         goto create_fail;
2672                 }
2673         }
2674
2675         /* DCCG */
2676         pool->base.dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2677         if (pool->base.dccg == NULL) {
2678                 dm_error("DC: failed to create dccg!\n");
2679                 BREAK_TO_DEBUGGER();
2680                 goto create_fail;
2681         }
2682
2683         /* PP Lib and SMU interfaces */
2684         init_soc_bounding_box(dc, pool);
2685
2686         num_pipes = dcn3_0_ip.max_num_dpp;
2687
2688         for (i = 0; i < dcn3_0_ip.max_num_dpp; i++)
2689                 if (pipe_fuses & 1 << i)
2690                         num_pipes--;
2691
2692         dcn3_0_ip.max_num_dpp = num_pipes;
2693         dcn3_0_ip.max_num_otg = num_pipes;
2694
2695         dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30);
2696
2697         /* IRQ */
2698         init_data.ctx = dc->ctx;
2699         pool->base.irqs = dal_irq_service_dcn30_create(&init_data);
2700         if (!pool->base.irqs)
2701                 goto create_fail;
2702
2703         /* HUBBUB */
2704         pool->base.hubbub = dcn30_hubbub_create(ctx);
2705         if (pool->base.hubbub == NULL) {
2706                 BREAK_TO_DEBUGGER();
2707                 dm_error("DC: failed to create hubbub!\n");
2708                 goto create_fail;
2709         }
2710
2711         /* HUBPs, DPPs, OPPs and TGs */
2712         for (i = 0; i < pool->base.pipe_count; i++) {
2713                 pool->base.hubps[i] = dcn30_hubp_create(ctx, i);
2714                 if (pool->base.hubps[i] == NULL) {
2715                         BREAK_TO_DEBUGGER();
2716                         dm_error(
2717                                 "DC: failed to create hubps!\n");
2718                         goto create_fail;
2719                 }
2720
2721                 pool->base.dpps[i] = dcn30_dpp_create(ctx, i);
2722                 if (pool->base.dpps[i] == NULL) {
2723                         BREAK_TO_DEBUGGER();
2724                         dm_error(
2725                                 "DC: failed to create dpps!\n");
2726                         goto create_fail;
2727                 }
2728         }
2729
2730         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2731                 pool->base.opps[i] = dcn30_opp_create(ctx, i);
2732                 if (pool->base.opps[i] == NULL) {
2733                         BREAK_TO_DEBUGGER();
2734                         dm_error(
2735                                 "DC: failed to create output pixel processor!\n");
2736                         goto create_fail;
2737                 }
2738         }
2739
2740         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2741                 pool->base.timing_generators[i] = dcn30_timing_generator_create(
2742                                 ctx, i);
2743                 if (pool->base.timing_generators[i] == NULL) {
2744                         BREAK_TO_DEBUGGER();
2745                         dm_error("DC: failed to create tg!\n");
2746                         goto create_fail;
2747                 }
2748         }
2749         pool->base.timing_generator_count = i;
2750         /* PSR */
2751         pool->base.psr = dmub_psr_create(ctx);
2752
2753         if (pool->base.psr == NULL) {
2754                 dm_error("DC: failed to create PSR obj!\n");
2755                 BREAK_TO_DEBUGGER();
2756                 goto create_fail;
2757         }
2758
2759         /* ABM */
2760         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2761                 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
2762                                 &abm_regs[i],
2763                                 &abm_shift,
2764                                 &abm_mask);
2765                 if (pool->base.multiple_abms[i] == NULL) {
2766                         dm_error("DC: failed to create abm for pipe %d!\n", i);
2767                         BREAK_TO_DEBUGGER();
2768                         goto create_fail;
2769                 }
2770         }
2771         /* MPC and DSC */
2772         pool->base.mpc = dcn30_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
2773         if (pool->base.mpc == NULL) {
2774                 BREAK_TO_DEBUGGER();
2775                 dm_error("DC: failed to create mpc!\n");
2776                 goto create_fail;
2777         }
2778
2779         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2780                 pool->base.dscs[i] = dcn30_dsc_create(ctx, i);
2781                 if (pool->base.dscs[i] == NULL) {
2782                         BREAK_TO_DEBUGGER();
2783                         dm_error("DC: failed to create display stream compressor %d!\n", i);
2784                         goto create_fail;
2785                 }
2786         }
2787
2788         /* DWB and MMHUBBUB */
2789         if (!dcn30_dwbc_create(ctx, &pool->base)) {
2790                 BREAK_TO_DEBUGGER();
2791                 dm_error("DC: failed to create dwbc!\n");
2792                 goto create_fail;
2793         }
2794
2795         if (!dcn30_mmhubbub_create(ctx, &pool->base)) {
2796                 BREAK_TO_DEBUGGER();
2797                 dm_error("DC: failed to create mcif_wb!\n");
2798                 goto create_fail;
2799         }
2800
2801         /* AUX and I2C */
2802         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2803                 pool->base.engines[i] = dcn30_aux_engine_create(ctx, i);
2804                 if (pool->base.engines[i] == NULL) {
2805                         BREAK_TO_DEBUGGER();
2806                         dm_error(
2807                                 "DC:failed to create aux engine!!\n");
2808                         goto create_fail;
2809                 }
2810                 pool->base.hw_i2cs[i] = dcn30_i2c_hw_create(ctx, i);
2811                 if (pool->base.hw_i2cs[i] == NULL) {
2812                         BREAK_TO_DEBUGGER();
2813                         dm_error(
2814                                 "DC:failed to create hw i2c!!\n");
2815                         goto create_fail;
2816                 }
2817                 pool->base.sw_i2cs[i] = NULL;
2818         }
2819
2820         /* Audio, Stream Encoders including DIG and virtual, MPC 3D LUTs */
2821         if (!resource_construct(num_virtual_links, dc, &pool->base,
2822                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2823                         &res_create_funcs : &res_create_maximus_funcs)))
2824                 goto create_fail;
2825
2826         /* HW Sequencer and Plane caps */
2827         dcn30_hw_sequencer_construct(dc);
2828
2829         dc->caps.max_planes =  pool->base.pipe_count;
2830
2831         for (i = 0; i < dc->caps.max_planes; ++i)
2832                 dc->caps.planes[i] = plane_cap;
2833
2834         dc->cap_funcs = cap_funcs;
2835
2836         if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2837                 ddc_init_data.ctx = dc->ctx;
2838                 ddc_init_data.link = NULL;
2839                 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2840                 ddc_init_data.id.enum_id = 0;
2841                 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2842                 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
2843         } else {
2844                 pool->base.oem_device = NULL;
2845         }
2846
2847         DC_FP_END();
2848
2849         return true;
2850
2851 create_fail:
2852
2853         DC_FP_END();
2854         dcn30_resource_destruct(pool);
2855
2856         return false;
2857 }
2858
2859 struct resource_pool *dcn30_create_resource_pool(
2860                 const struct dc_init_data *init_data,
2861                 struct dc *dc)
2862 {
2863         struct dcn30_resource_pool *pool =
2864                 kzalloc(sizeof(struct dcn30_resource_pool), GFP_KERNEL);
2865
2866         if (!pool)
2867                 return NULL;
2868
2869         if (dcn30_resource_construct(init_data->num_virtual_links, dc, pool))
2870                 return &pool->base;
2871
2872         BREAK_TO_DEBUGGER();
2873         kfree(pool);
2874         return NULL;
2875 }