drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c

   1 /*
   2 * Copyright 2018 Advanced Micro Devices, Inc.
   3  * Copyright 2019 Raptor Engineering, LLC
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26
  27 #include <linux/slab.h>
  28
  29 #include "dm_services.h"
  30 #include "dc.h"
  31
  32 #include "dcn21_init.h"
  33
  34 #include "resource.h"
  35 #include "include/irq_service_interface.h"
  36 #include "dcn20/dcn20_resource.h"
  37
  38 #include "clk_mgr.h"
  39 #include "dcn10/dcn10_hubp.h"
  40 #include "dcn10/dcn10_ipp.h"
  41 #include "dcn20/dcn20_hubbub.h"
  42 #include "dcn20/dcn20_mpc.h"
  43 #include "dcn20/dcn20_hubp.h"
  44 #include "dcn21_hubp.h"
  45 #include "irq/dcn21/irq_service_dcn21.h"
  46 #include "dcn20/dcn20_dpp.h"
  47 #include "dcn20/dcn20_optc.h"
  48 #include "dcn21/dcn21_hwseq.h"
  49 #include "dce110/dce110_hw_sequencer.h"
  50 #include "dcn20/dcn20_opp.h"
  51 #include "dcn20/dcn20_dsc.h"
  52 #include "dcn21/dcn21_link_encoder.h"
  53 #include "dcn20/dcn20_stream_encoder.h"
  54 #include "dce/dce_clock_source.h"
  55 #include "dce/dce_audio.h"
  56 #include "dce/dce_hwseq.h"
  57 #include "virtual/virtual_stream_encoder.h"
  58 #include "dce110/dce110_resource.h"
  59 #include "dml/display_mode_vba.h"
  60 #include "dcn20/dcn20_dccg.h"
  61 #include "dcn21_hubbub.h"
  62 #include "dcn10/dcn10_resource.h"
  63 #include "dce110/dce110_resource.h"
  64
  65 #include "dcn20/dcn20_dwb.h"
  66 #include "dcn20/dcn20_mmhubbub.h"
  67 #include "dpcs/dpcs_2_1_0_offset.h"
  68 #include "dpcs/dpcs_2_1_0_sh_mask.h"
  69
  70 #include "renoir_ip_offset.h"
  71 #include "dcn/dcn_2_1_0_offset.h"
  72 #include "dcn/dcn_2_1_0_sh_mask.h"
  73
  74 #include "nbio/nbio_7_0_offset.h"
  75
  76 #include "mmhub/mmhub_2_0_0_offset.h"
  77 #include "mmhub/mmhub_2_0_0_sh_mask.h"
  78
  79 #include "reg_helper.h"
  80 #include "dce/dce_abm.h"
  81 #include "dce/dce_dmcu.h"
  82 #include "dce/dce_aux.h"
  83 #include "dce/dce_i2c.h"
  84 #include "dcn21_resource.h"
  85 #include "vm_helper.h"
  86 #include "dcn20/dcn20_vmid.h"
  87 #include "dce/dmub_psr.h"
  88
  89 #define SOC_BOUNDING_BOX_VALID false
  90 #define DC_LOGGER_INIT(logger)
  91
  92
  93 struct _vcs_dpi_ip_params_st dcn2_1_ip = {
  94         .odm_capable = 1,
  95         .gpuvm_enable = 1,
  96         .hostvm_enable = 1,
  97         .gpuvm_max_page_table_levels = 1,
  98         .hostvm_max_page_table_levels = 4,
  99         .hostvm_cached_page_table_levels = 2,
 100         .num_dsc = 3,
 101         .rob_buffer_size_kbytes = 168,
 102         .det_buffer_size_kbytes = 164,
 103         .dpte_buffer_size_in_pte_reqs_luma = 44,
 104         .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
 105         .dpp_output_buffer_pixels = 2560,
 106         .opp_output_buffer_lines = 1,
 107         .pixel_chunk_size_kbytes = 8,
 108         .pte_enable = 1,
 109         .max_page_table_levels = 4,
 110         .pte_chunk_size_kbytes = 2,
 111         .meta_chunk_size_kbytes = 2,
 112         .writeback_chunk_size_kbytes = 2,
 113         .line_buffer_size_bits = 789504,
 114         .is_line_buffer_bpp_fixed = 0,
 115         .line_buffer_fixed_bpp = 0,
 116         .dcc_supported = true,
 117         .max_line_buffer_lines = 12,
 118         .writeback_luma_buffer_size_kbytes = 12,
 119         .writeback_chroma_buffer_size_kbytes = 8,
 120         .writeback_chroma_line_buffer_width_pixels = 4,
 121         .writeback_max_hscl_ratio = 1,
 122         .writeback_max_vscl_ratio = 1,
 123         .writeback_min_hscl_ratio = 1,
 124         .writeback_min_vscl_ratio = 1,
 125         .writeback_max_hscl_taps = 12,
 126         .writeback_max_vscl_taps = 12,
 127         .writeback_line_buffer_luma_buffer_size = 0,
 128         .writeback_line_buffer_chroma_buffer_size = 14643,
 129         .cursor_buffer_size = 8,
 130         .cursor_chunk_size = 2,
 131         .max_num_otg = 4,
 132         .max_num_dpp = 4,
 133         .max_num_wb = 1,
 134         .max_dchub_pscl_bw_pix_per_clk = 4,
 135         .max_pscl_lb_bw_pix_per_clk = 2,
 136         .max_lb_vscl_bw_pix_per_clk = 4,
 137         .max_vscl_hscl_bw_pix_per_clk = 4,
 138         .max_hscl_ratio = 4,
 139         .max_vscl_ratio = 4,
 140         .hscl_mults = 4,
 141         .vscl_mults = 4,
 142         .max_hscl_taps = 8,
 143         .max_vscl_taps = 8,
 144         .dispclk_ramp_margin_percent = 1,
 145         .underscan_factor = 1.10,
 146         .min_vblank_lines = 32, //
 147         .dppclk_delay_subtotal = 77, //
 148         .dppclk_delay_scl_lb_only = 16,
 149         .dppclk_delay_scl = 50,
 150         .dppclk_delay_cnvc_formatter = 8,
 151         .dppclk_delay_cnvc_cursor = 6,
 152         .dispclk_delay_subtotal = 87, //
 153         .dcfclk_cstate_latency = 10, // SRExitTime
 154         .max_inter_dcn_tile_repeaters = 8,
 155
 156         .xfc_supported = false,
 157         .xfc_fill_bw_overhead_percent = 10.0,
 158         .xfc_fill_constant_bytes = 0,
 159         .ptoi_supported = 0,
 160         .number_of_cursors = 1,
 161 };
 162
 163 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
 164         .clock_limits = {
 165                         {
 166                                 .state = 0,
 167                                 .dcfclk_mhz = 400.0,
 168                                 .fabricclk_mhz = 400.0,
 169                                 .dispclk_mhz = 600.0,
 170                                 .dppclk_mhz = 400.00,
 171                                 .phyclk_mhz = 600.0,
 172                                 .socclk_mhz = 278.0,
 173                                 .dscclk_mhz = 205.67,
 174                                 .dram_speed_mts = 1600.0,
 175                         },
 176                         {
 177                                 .state = 1,
 178                                 .dcfclk_mhz = 464.52,
 179                                 .fabricclk_mhz = 800.0,
 180                                 .dispclk_mhz = 654.55,
 181                                 .dppclk_mhz = 626.09,
 182                                 .phyclk_mhz = 600.0,
 183                                 .socclk_mhz = 278.0,
 184                                 .dscclk_mhz = 205.67,
 185                                 .dram_speed_mts = 1600.0,
 186                         },
 187                         {
 188                                 .state = 2,
 189                                 .dcfclk_mhz = 514.29,
 190                                 .fabricclk_mhz = 933.0,
 191                                 .dispclk_mhz = 757.89,
 192                                 .dppclk_mhz = 685.71,
 193                                 .phyclk_mhz = 600.0,
 194                                 .socclk_mhz = 278.0,
 195                                 .dscclk_mhz = 287.67,
 196                                 .dram_speed_mts = 1866.0,
 197                         },
 198                         {
 199                                 .state = 3,
 200                                 .dcfclk_mhz = 576.00,
 201                                 .fabricclk_mhz = 1067.0,
 202                                 .dispclk_mhz = 847.06,
 203                                 .dppclk_mhz = 757.89,
 204                                 .phyclk_mhz = 600.0,
 205                                 .socclk_mhz = 715.0,
 206                                 .dscclk_mhz = 318.334,
 207                                 .dram_speed_mts = 2134.0,
 208                         },
 209                         {
 210                                 .state = 4,
 211                                 .dcfclk_mhz = 626.09,
 212                                 .fabricclk_mhz = 1200.0,
 213                                 .dispclk_mhz = 900.00,
 214                                 .dppclk_mhz = 847.06,
 215                                 .phyclk_mhz = 810.0,
 216                                 .socclk_mhz = 953.0,
 217                                 .dscclk_mhz = 489.0,
 218                                 .dram_speed_mts = 2400.0,
 219                         },
 220                         {
 221                                 .state = 5,
 222                                 .dcfclk_mhz = 685.71,
 223                                 .fabricclk_mhz = 1333.0,
 224                                 .dispclk_mhz = 1028.57,
 225                                 .dppclk_mhz = 960.00,
 226                                 .phyclk_mhz = 810.0,
 227                                 .socclk_mhz = 278.0,
 228                                 .dscclk_mhz = 287.67,
 229                                 .dram_speed_mts = 2666.0,
 230                         },
 231                         {
 232                                 .state = 6,
 233                                 .dcfclk_mhz = 757.89,
 234                                 .fabricclk_mhz = 1467.0,
 235                                 .dispclk_mhz = 1107.69,
 236                                 .dppclk_mhz = 1028.57,
 237                                 .phyclk_mhz = 810.0,
 238                                 .socclk_mhz = 715.0,
 239                                 .dscclk_mhz = 318.334,
 240                                 .dram_speed_mts = 3200.0,
 241                         },
 242                         {
 243                                 .state = 7,
 244                                 .dcfclk_mhz = 847.06,
 245                                 .fabricclk_mhz = 1600.0,
 246                                 .dispclk_mhz = 1395.0,
 247                                 .dppclk_mhz = 1285.00,
 248                                 .phyclk_mhz = 1325.0,
 249                                 .socclk_mhz = 953.0,
 250                                 .dscclk_mhz = 489.0,
 251                                 .dram_speed_mts = 4266.0,
 252                         },
 253                         /*Extra state, no dispclk ramping*/
 254                         {
 255                                 .state = 8,
 256                                 .dcfclk_mhz = 847.06,
 257                                 .fabricclk_mhz = 1600.0,
 258                                 .dispclk_mhz = 1395.0,
 259                                 .dppclk_mhz = 1285.0,
 260                                 .phyclk_mhz = 1325.0,
 261                                 .socclk_mhz = 953.0,
 262                                 .dscclk_mhz = 489.0,
 263                                 .dram_speed_mts = 4266.0,
 264                         },
 265
 266                 },
 267
 268         .sr_exit_time_us = 12.5,
 269         .sr_enter_plus_exit_time_us = 17.0,
 270         .urgent_latency_us = 4.0,
 271         .urgent_latency_pixel_data_only_us = 4.0,
 272         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 273         .urgent_latency_vm_data_only_us = 4.0,
 274         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 275         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 276         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 277         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
 278         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
 279         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
 280         .max_avg_sdp_bw_use_normal_percent = 60.0,
 281         .max_avg_dram_bw_use_normal_percent = 100.0,
 282         .writeback_latency_us = 12.0,
 283         .max_request_size_bytes = 256,
 284         .dram_channel_width_bytes = 4,
 285         .fabric_datapath_to_dcn_data_return_bytes = 32,
 286         .dcn_downspread_percent = 0.5,
 287         .downspread_percent = 0.5,
 288         .dram_page_open_time_ns = 50.0,
 289         .dram_rw_turnaround_time_ns = 17.5,
 290         .dram_return_buffer_per_channel_bytes = 8192,
 291         .round_trip_ping_latency_dcfclk_cycles = 128,
 292         .urgent_out_of_order_return_per_channel_bytes = 4096,
 293         .channel_interleave_bytes = 256,
 294         .num_banks = 8,
 295         .num_chans = 4,
 296         .vmm_page_size_bytes = 4096,
 297         .dram_clock_change_latency_us = 23.84,
 298         .return_bus_width_bytes = 64,
 299         .dispclk_dppclk_vco_speed_mhz = 3600,
 300         .xfc_bus_transport_time_us = 4,
 301         .xfc_xbuf_latency_tolerance_us = 4,
 302         .use_urgent_burst_bw = 1,
 303         .num_states = 8
 304 };
 305
 306 #ifndef MAX
 307 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
 308 #endif
 309 #ifndef MIN
 310 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
 311 #endif
 312
 313 /* begin *********************
 314  * macros to expend register list macro defined in HW object header file */
 315
 316 /* DCN */
 317 /* TODO awful hack. fixup dcn20_dwb.h */
 318 #undef BASE_INNER
 319 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
 320
 321 #define BASE(seg) BASE_INNER(seg)
 322
 323 #define SR(reg_name)\
 324                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 325                                         mm ## reg_name
 326
 327 #define SRI(reg_name, block, id)\
 328         .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 329                                         mm ## block ## id ## _ ## reg_name
 330
 331 #define SRIR(var_name, reg_name, block, id)\
 332         .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 333                                         mm ## block ## id ## _ ## reg_name
 334
 335 #define SRII(reg_name, block, id)\
 336         .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 337                                         mm ## block ## id ## _ ## reg_name
 338
 339 #define DCCG_SRII(reg_name, block, id)\
 340         .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 341                                         mm ## block ## id ## _ ## reg_name
 342
 343 /* NBIO */
 344 #define NBIO_BASE_INNER(seg) \
 345         NBIF0_BASE__INST0_SEG ## seg
 346
 347 #define NBIO_BASE(seg) \
 348         NBIO_BASE_INNER(seg)
 349
 350 #define NBIO_SR(reg_name)\
 351                 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
 352                                         mm ## reg_name
 353
 354 /* MMHUB */
 355 #define MMHUB_BASE_INNER(seg) \
 356         MMHUB_BASE__INST0_SEG ## seg
 357
 358 #define MMHUB_BASE(seg) \
 359         MMHUB_BASE_INNER(seg)
 360
 361 #define MMHUB_SR(reg_name)\
 362                 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
 363                                         mmMM ## reg_name
 364
 365 #define clk_src_regs(index, pllid)\
 366 [index] = {\
 367         CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
 368 }
 369
 370 static const struct dce110_clk_src_regs clk_src_regs[] = {
 371         clk_src_regs(0, A),
 372         clk_src_regs(1, B),
 373         clk_src_regs(2, C),
 374         clk_src_regs(3, D),
 375         clk_src_regs(4, E),
 376 };
 377
 378 static const struct dce110_clk_src_shift cs_shift = {
 379                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 380 };
 381
 382 static const struct dce110_clk_src_mask cs_mask = {
 383                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 384 };
 385
 386 static const struct bios_registers bios_regs = {
 387                 NBIO_SR(BIOS_SCRATCH_3),
 388                 NBIO_SR(BIOS_SCRATCH_6)
 389 };
 390
 391 static const struct dce_dmcu_registers dmcu_regs = {
 392                 DMCU_DCN20_REG_LIST()
 393 };
 394
 395 static const struct dce_dmcu_shift dmcu_shift = {
 396                 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
 397 };
 398
 399 static const struct dce_dmcu_mask dmcu_mask = {
 400                 DMCU_MASK_SH_LIST_DCN10(_MASK)
 401 };
 402
 403 static const struct dce_abm_registers abm_regs = {
 404                 ABM_DCN20_REG_LIST()
 405 };
 406
 407 static const struct dce_abm_shift abm_shift = {
 408                 ABM_MASK_SH_LIST_DCN20(__SHIFT)
 409 };
 410
 411 static const struct dce_abm_mask abm_mask = {
 412                 ABM_MASK_SH_LIST_DCN20(_MASK)
 413 };
 414
 415 #define audio_regs(id)\
 416 [id] = {\
 417                 AUD_COMMON_REG_LIST(id)\
 418 }
 419
 420 static const struct dce_audio_registers audio_regs[] = {
 421         audio_regs(0),
 422         audio_regs(1),
 423         audio_regs(2),
 424         audio_regs(3),
 425         audio_regs(4),
 426         audio_regs(5),
 427 };
 428
 429 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 430                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 431                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 432                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 433
 434 static const struct dce_audio_shift audio_shift = {
 435                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 436 };
 437
 438 static const struct dce_audio_mask audio_mask = {
 439                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 440 };
 441
 442 static const struct dccg_registers dccg_regs = {
 443                 DCCG_COMMON_REG_LIST_DCN_BASE()
 444 };
 445
 446 static const struct dccg_shift dccg_shift = {
 447                 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
 448 };
 449
 450 static const struct dccg_mask dccg_mask = {
 451                 DCCG_MASK_SH_LIST_DCN2(_MASK)
 452 };
 453
 454 #define opp_regs(id)\
 455 [id] = {\
 456         OPP_REG_LIST_DCN20(id),\
 457 }
 458
 459 static const struct dcn20_opp_registers opp_regs[] = {
 460         opp_regs(0),
 461         opp_regs(1),
 462         opp_regs(2),
 463         opp_regs(3),
 464         opp_regs(4),
 465         opp_regs(5),
 466 };
 467
 468 static const struct dcn20_opp_shift opp_shift = {
 469                 OPP_MASK_SH_LIST_DCN20(__SHIFT)
 470 };
 471
 472 static const struct dcn20_opp_mask opp_mask = {
 473                 OPP_MASK_SH_LIST_DCN20(_MASK)
 474 };
 475
 476 #define tg_regs(id)\
 477 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
 478
 479 static const struct dcn_optc_registers tg_regs[] = {
 480         tg_regs(0),
 481         tg_regs(1),
 482         tg_regs(2),
 483         tg_regs(3)
 484 };
 485
 486 static const struct dcn_optc_shift tg_shift = {
 487         TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 488 };
 489
 490 static const struct dcn_optc_mask tg_mask = {
 491         TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 492 };
 493
 494 static const struct dcn20_mpc_registers mpc_regs = {
 495                 MPC_REG_LIST_DCN2_0(0),
 496                 MPC_REG_LIST_DCN2_0(1),
 497                 MPC_REG_LIST_DCN2_0(2),
 498                 MPC_REG_LIST_DCN2_0(3),
 499                 MPC_REG_LIST_DCN2_0(4),
 500                 MPC_REG_LIST_DCN2_0(5),
 501                 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
 502                 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
 503                 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
 504                 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
 505                 MPC_DBG_REG_LIST_DCN2_0()
 506 };
 507
 508 static const struct dcn20_mpc_shift mpc_shift = {
 509         MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
 510         MPC_DEBUG_REG_LIST_SH_DCN20
 511 };
 512
 513 static const struct dcn20_mpc_mask mpc_mask = {
 514         MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
 515         MPC_DEBUG_REG_LIST_MASK_DCN20
 516 };
 517
 518 #define hubp_regs(id)\
 519 [id] = {\
 520         HUBP_REG_LIST_DCN21(id)\
 521 }
 522
 523 static const struct dcn_hubp2_registers hubp_regs[] = {
 524                 hubp_regs(0),
 525                 hubp_regs(1),
 526                 hubp_regs(2),
 527                 hubp_regs(3)
 528 };
 529
 530 static const struct dcn_hubp2_shift hubp_shift = {
 531                 HUBP_MASK_SH_LIST_DCN21(__SHIFT)
 532 };
 533
 534 static const struct dcn_hubp2_mask hubp_mask = {
 535                 HUBP_MASK_SH_LIST_DCN21(_MASK)
 536 };
 537
 538 static const struct dcn_hubbub_registers hubbub_reg = {
 539                 HUBBUB_REG_LIST_DCN21()
 540 };
 541
 542 static const struct dcn_hubbub_shift hubbub_shift = {
 543                 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
 544 };
 545
 546 static const struct dcn_hubbub_mask hubbub_mask = {
 547                 HUBBUB_MASK_SH_LIST_DCN21(_MASK)
 548 };
 549
 550
 551 #define vmid_regs(id)\
 552 [id] = {\
 553                 DCN20_VMID_REG_LIST(id)\
 554 }
 555
 556 static const struct dcn_vmid_registers vmid_regs[] = {
 557         vmid_regs(0),
 558         vmid_regs(1),
 559         vmid_regs(2),
 560         vmid_regs(3),
 561         vmid_regs(4),
 562         vmid_regs(5),
 563         vmid_regs(6),
 564         vmid_regs(7),
 565         vmid_regs(8),
 566         vmid_regs(9),
 567         vmid_regs(10),
 568         vmid_regs(11),
 569         vmid_regs(12),
 570         vmid_regs(13),
 571         vmid_regs(14),
 572         vmid_regs(15)
 573 };
 574
 575 static const struct dcn20_vmid_shift vmid_shifts = {
 576                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 577 };
 578
 579 static const struct dcn20_vmid_mask vmid_masks = {
 580                 DCN20_VMID_MASK_SH_LIST(_MASK)
 581 };
 582
 583 #define dsc_regsDCN20(id)\
 584 [id] = {\
 585         DSC_REG_LIST_DCN20(id)\
 586 }
 587
 588 static const struct dcn20_dsc_registers dsc_regs[] = {
 589         dsc_regsDCN20(0),
 590         dsc_regsDCN20(1),
 591         dsc_regsDCN20(2),
 592         dsc_regsDCN20(3),
 593         dsc_regsDCN20(4),
 594         dsc_regsDCN20(5)
 595 };
 596
 597 static const struct dcn20_dsc_shift dsc_shift = {
 598         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 599 };
 600
 601 static const struct dcn20_dsc_mask dsc_mask = {
 602         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 603 };
 604
 605 #define ipp_regs(id)\
 606 [id] = {\
 607         IPP_REG_LIST_DCN20(id),\
 608 }
 609
 610 static const struct dcn10_ipp_registers ipp_regs[] = {
 611         ipp_regs(0),
 612         ipp_regs(1),
 613         ipp_regs(2),
 614         ipp_regs(3),
 615 };
 616
 617 static const struct dcn10_ipp_shift ipp_shift = {
 618                 IPP_MASK_SH_LIST_DCN20(__SHIFT)
 619 };
 620
 621 static const struct dcn10_ipp_mask ipp_mask = {
 622                 IPP_MASK_SH_LIST_DCN20(_MASK),
 623 };
 624
 625 #define opp_regs(id)\
 626 [id] = {\
 627         OPP_REG_LIST_DCN20(id),\
 628 }
 629
 630
 631 #define aux_engine_regs(id)\
 632 [id] = {\
 633         AUX_COMMON_REG_LIST0(id), \
 634         .AUXN_IMPCAL = 0, \
 635         .AUXP_IMPCAL = 0, \
 636         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 637 }
 638
 639 static const struct dce110_aux_registers aux_engine_regs[] = {
 640                 aux_engine_regs(0),
 641                 aux_engine_regs(1),
 642                 aux_engine_regs(2),
 643                 aux_engine_regs(3),
 644                 aux_engine_regs(4),
 645 };
 646
 647 #define tf_regs(id)\
 648 [id] = {\
 649         TF_REG_LIST_DCN20(id),\
 650         TF_REG_LIST_DCN20_COMMON_APPEND(id),\
 651 }
 652
 653 static const struct dcn2_dpp_registers tf_regs[] = {
 654         tf_regs(0),
 655         tf_regs(1),
 656         tf_regs(2),
 657         tf_regs(3),
 658 };
 659
 660 static const struct dcn2_dpp_shift tf_shift = {
 661                 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
 662                 TF_DEBUG_REG_LIST_SH_DCN20
 663 };
 664
 665 static const struct dcn2_dpp_mask tf_mask = {
 666                 TF_REG_LIST_SH_MASK_DCN20(_MASK),
 667                 TF_DEBUG_REG_LIST_MASK_DCN20
 668 };
 669
 670 #define stream_enc_regs(id)\
 671 [id] = {\
 672         SE_DCN2_REG_LIST(id)\
 673 }
 674
 675 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 676         stream_enc_regs(0),
 677         stream_enc_regs(1),
 678         stream_enc_regs(2),
 679         stream_enc_regs(3),
 680         stream_enc_regs(4),
 681 };
 682
 683 static const struct dce110_aux_registers_shift aux_shift = {
 684         DCN_AUX_MASK_SH_LIST(__SHIFT)
 685 };
 686
 687 static const struct dce110_aux_registers_mask aux_mask = {
 688         DCN_AUX_MASK_SH_LIST(_MASK)
 689 };
 690
 691 static const struct dcn10_stream_encoder_shift se_shift = {
 692                 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
 693 };
 694
 695 static const struct dcn10_stream_encoder_mask se_mask = {
 696                 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
 697 };
 698
 699 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
 700
 701 static int dcn21_populate_dml_pipes_from_context(
 702                 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes);
 703
 704 static struct input_pixel_processor *dcn21_ipp_create(
 705         struct dc_context *ctx, uint32_t inst)
 706 {
 707         struct dcn10_ipp *ipp =
 708                 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
 709
 710         if (!ipp) {
 711                 BREAK_TO_DEBUGGER();
 712                 return NULL;
 713         }
 714
 715         dcn20_ipp_construct(ipp, ctx, inst,
 716                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 717         return &ipp->base;
 718 }
 719
 720 static struct dpp *dcn21_dpp_create(
 721         struct dc_context *ctx,
 722         uint32_t inst)
 723 {
 724         struct dcn20_dpp *dpp =
 725                 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
 726
 727         if (!dpp)
 728                 return NULL;
 729
 730         if (dpp2_construct(dpp, ctx, inst,
 731                         &tf_regs[inst], &tf_shift, &tf_mask))
 732                 return &dpp->base;
 733
 734         BREAK_TO_DEBUGGER();
 735         kfree(dpp);
 736         return NULL;
 737 }
 738
 739 static struct dce_aux *dcn21_aux_engine_create(
 740         struct dc_context *ctx,
 741         uint32_t inst)
 742 {
 743         struct aux_engine_dce110 *aux_engine =
 744                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 745
 746         if (!aux_engine)
 747                 return NULL;
 748
 749         dce110_aux_engine_construct(aux_engine, ctx, inst,
 750                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 751                                     &aux_engine_regs[inst],
 752                                         &aux_mask,
 753                                         &aux_shift,
 754                                         ctx->dc->caps.extended_aux_timeout_support);
 755
 756         return &aux_engine->base;
 757 }
 758
 759 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 760
 761 static const struct dce_i2c_registers i2c_hw_regs[] = {
 762                 i2c_inst_regs(1),
 763                 i2c_inst_regs(2),
 764                 i2c_inst_regs(3),
 765                 i2c_inst_regs(4),
 766                 i2c_inst_regs(5),
 767 };
 768
 769 static const struct dce_i2c_shift i2c_shifts = {
 770                 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
 771 };
 772
 773 static const struct dce_i2c_mask i2c_masks = {
 774                 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
 775 };
 776
 777 struct dce_i2c_hw *dcn21_i2c_hw_create(
 778         struct dc_context *ctx,
 779         uint32_t inst)
 780 {
 781         struct dce_i2c_hw *dce_i2c_hw =
 782                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 783
 784         if (!dce_i2c_hw)
 785                 return NULL;
 786
 787         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 788                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 789
 790         return dce_i2c_hw;
 791 }
 792
 793 static const struct resource_caps res_cap_rn = {
 794                 .num_timing_generator = 4,
 795                 .num_opp = 4,
 796                 .num_video_plane = 4,
 797                 .num_audio = 4, // 4 audio endpoints.  4 audio streams
 798                 .num_stream_encoder = 5,
 799                 .num_pll = 5,  // maybe 3 because the last two used for USB-c
 800                 .num_dwb = 1,
 801                 .num_ddc = 5,
 802                 .num_vmid = 1,
 803                 .num_dsc = 3,
 804 };
 805
 806 #ifdef DIAGS_BUILD
 807 static const struct resource_caps res_cap_rn_FPGA_4pipe = {
 808                 .num_timing_generator = 4,
 809                 .num_opp = 4,
 810                 .num_video_plane = 4,
 811                 .num_audio = 7,
 812                 .num_stream_encoder = 4,
 813                 .num_pll = 4,
 814                 .num_dwb = 1,
 815                 .num_ddc = 4,
 816                 .num_dsc = 0,
 817 };
 818
 819 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {
 820                 .num_timing_generator = 2,
 821                 .num_opp = 2,
 822                 .num_video_plane = 2,
 823                 .num_audio = 7,
 824                 .num_stream_encoder = 2,
 825                 .num_pll = 4,
 826                 .num_dwb = 1,
 827                 .num_ddc = 4,
 828                 .num_dsc = 2,
 829 };
 830 #endif
 831
 832 static const struct dc_plane_cap plane_cap = {
 833         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
 834         .blends_with_above = true,
 835         .blends_with_below = true,
 836         .per_pixel_alpha = true,
 837
 838         .pixel_format_support = {
 839                         .argb8888 = true,
 840                         .nv12 = true,
 841                         .fp16 = true,
 842                         .p010 = true
 843         },
 844
 845         .max_upscale_factor = {
 846                         .argb8888 = 16000,
 847                         .nv12 = 16000,
 848                         .fp16 = 16000
 849         },
 850
 851         .max_downscale_factor = {
 852                         .argb8888 = 250,
 853                         .nv12 = 250,
 854                         .fp16 = 250
 855         }
 856 };
 857
 858 static const struct dc_debug_options debug_defaults_drv = {
 859                 .disable_dmcu = false,
 860                 .force_abm_enable = false,
 861                 .timing_trace = false,
 862                 .clock_trace = true,
 863                 .disable_pplib_clock_request = true,
 864                 .min_disp_clk_khz = 100000,
 865                 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
 866                 .force_single_disp_pipe_split = false,
 867                 .disable_dcc = DCC_ENABLE,
 868                 .vsr_support = true,
 869                 .performance_trace = false,
 870                 .max_downscale_src_width = 4096,
 871                 .disable_pplib_wm_range = false,
 872                 .scl_reset_length10 = true,
 873                 .sanity_checks = true,
 874                 .disable_48mhz_pwrdwn = false,
 875                 .nv12_iflip_vm_wa = true,
 876                 .usbc_combo_phy_reset_wa = true
 877 };
 878
 879 static const struct dc_debug_options debug_defaults_diags = {
 880                 .disable_dmcu = false,
 881                 .force_abm_enable = false,
 882                 .timing_trace = true,
 883                 .clock_trace = true,
 884                 .disable_dpp_power_gate = true,
 885                 .disable_hubp_power_gate = true,
 886                 .disable_clock_gate = true,
 887                 .disable_pplib_clock_request = true,
 888                 .disable_pplib_wm_range = true,
 889                 .disable_stutter = true,
 890                 .disable_48mhz_pwrdwn = true,
 891 };
 892
 893 enum dcn20_clk_src_array_id {
 894         DCN20_CLK_SRC_PLL0,
 895         DCN20_CLK_SRC_PLL1,
 896         DCN20_CLK_SRC_PLL2,
 897         DCN20_CLK_SRC_TOTAL_DCN21
 898 };
 899
 900 static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
 901 {
 902         unsigned int i;
 903
 904         for (i = 0; i < pool->base.stream_enc_count; i++) {
 905                 if (pool->base.stream_enc[i] != NULL) {
 906                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 907                         pool->base.stream_enc[i] = NULL;
 908                 }
 909         }
 910
 911         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
 912                 if (pool->base.dscs[i] != NULL)
 913                         dcn20_dsc_destroy(&pool->base.dscs[i]);
 914         }
 915
 916         if (pool->base.mpc != NULL) {
 917                 kfree(TO_DCN20_MPC(pool->base.mpc));
 918                 pool->base.mpc = NULL;
 919         }
 920         if (pool->base.hubbub != NULL) {
 921                 kfree(pool->base.hubbub);
 922                 pool->base.hubbub = NULL;
 923         }
 924         for (i = 0; i < pool->base.pipe_count; i++) {
 925                 if (pool->base.dpps[i] != NULL)
 926                         dcn20_dpp_destroy(&pool->base.dpps[i]);
 927
 928                 if (pool->base.ipps[i] != NULL)
 929                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
 930
 931                 if (pool->base.hubps[i] != NULL) {
 932                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
 933                         pool->base.hubps[i] = NULL;
 934                 }
 935
 936                 if (pool->base.irqs != NULL) {
 937                         dal_irq_service_destroy(&pool->base.irqs);
 938                 }
 939         }
 940
 941         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
 942                 if (pool->base.engines[i] != NULL)
 943                         dce110_engine_destroy(&pool->base.engines[i]);
 944                 if (pool->base.hw_i2cs[i] != NULL) {
 945                         kfree(pool->base.hw_i2cs[i]);
 946                         pool->base.hw_i2cs[i] = NULL;
 947                 }
 948                 if (pool->base.sw_i2cs[i] != NULL) {
 949                         kfree(pool->base.sw_i2cs[i]);
 950                         pool->base.sw_i2cs[i] = NULL;
 951                 }
 952         }
 953
 954         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
 955                 if (pool->base.opps[i] != NULL)
 956                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
 957         }
 958
 959         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
 960                 if (pool->base.timing_generators[i] != NULL)    {
 961                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
 962                         pool->base.timing_generators[i] = NULL;
 963                 }
 964         }
 965
 966         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
 967                 if (pool->base.dwbc[i] != NULL) {
 968                         kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
 969                         pool->base.dwbc[i] = NULL;
 970                 }
 971                 if (pool->base.mcif_wb[i] != NULL) {
 972                         kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
 973                         pool->base.mcif_wb[i] = NULL;
 974                 }
 975         }
 976
 977         for (i = 0; i < pool->base.audio_count; i++) {
 978                 if (pool->base.audios[i])
 979                         dce_aud_destroy(&pool->base.audios[i]);
 980         }
 981
 982         for (i = 0; i < pool->base.clk_src_count; i++) {
 983                 if (pool->base.clock_sources[i] != NULL) {
 984                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
 985                         pool->base.clock_sources[i] = NULL;
 986                 }
 987         }
 988
 989         if (pool->base.dp_clock_source != NULL) {
 990                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
 991                 pool->base.dp_clock_source = NULL;
 992         }
 993
 994
 995         if (pool->base.abm != NULL)
 996                 dce_abm_destroy(&pool->base.abm);
 997
 998         if (pool->base.dmcu != NULL)
 999                 dce_dmcu_destroy(&pool->base.dmcu);
1000
1001         if (pool->base.psr != NULL)
1002                 dmub_psr_destroy(&pool->base.psr);
1003
1004         if (pool->base.dccg != NULL)
1005                 dcn_dccg_destroy(&pool->base.dccg);
1006
1007         if (pool->base.pp_smu != NULL)
1008                 dcn21_pp_smu_destroy(&pool->base.pp_smu);
1009 }
1010
1011
1012 static void calculate_wm_set_for_vlevel(
1013                 int vlevel,
1014                 struct wm_range_table_entry *table_entry,
1015                 struct dcn_watermarks *wm_set,
1016                 struct display_mode_lib *dml,
1017                 display_e2e_pipe_params_st *pipes,
1018                 int pipe_cnt)
1019 {
1020         double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
1021
1022         ASSERT(vlevel < dml->soc.num_states);
1023         /* only pipe 0 is read for voltage and dcf/soc clocks */
1024         pipes[0].clks_cfg.voltage = vlevel;
1025         pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
1026         pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
1027
1028         dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
1029         dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
1030         dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
1031
1032         wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
1033         wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
1034         wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
1035         wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
1036         wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
1037         wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
1038         wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
1039         wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
1040         dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
1041
1042 }
1043
1044 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
1045 {
1046         int i;
1047
1048         DC_FP_START();
1049
1050         if (dc->bb_overrides.sr_exit_time_ns) {
1051                 for (i = 0; i < WM_SET_COUNT; i++) {
1052                           dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
1053                                           dc->bb_overrides.sr_exit_time_ns / 1000.0;
1054                 }
1055         }
1056
1057         if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
1058                 for (i = 0; i < WM_SET_COUNT; i++) {
1059                           dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
1060                                           dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
1061                 }
1062         }
1063
1064         if (dc->bb_overrides.urgent_latency_ns) {
1065                 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
1066         }
1067
1068         if (dc->bb_overrides.dram_clock_change_latency_ns) {
1069                 for (i = 0; i < WM_SET_COUNT; i++) {
1070                         dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =
1071                                 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
1072                 }
1073         }
1074
1075         DC_FP_END();
1076 }
1077
1078 void dcn21_calculate_wm(
1079                 struct dc *dc, struct dc_state *context,
1080                 display_e2e_pipe_params_st *pipes,
1081                 int *out_pipe_cnt,
1082                 int *pipe_split_from,
1083                 int vlevel_req)
1084 {
1085         int pipe_cnt, i, pipe_idx;
1086         int vlevel, vlevel_max;
1087         struct wm_range_table_entry *table_entry;
1088         struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
1089
1090         ASSERT(bw_params);
1091
1092         patch_bounding_box(dc, &context->bw_ctx.dml.soc);
1093
1094         for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1095                         if (!context->res_ctx.pipe_ctx[i].stream)
1096                                 continue;
1097
1098                         pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1099                         pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];
1100
1101                         if (pipe_split_from[i] < 0) {
1102                                 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1103                                                 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1104                                 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1105                                         pipes[pipe_cnt].pipe.dest.odm_combine =
1106                                                         context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];
1107                                 else
1108                                         pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1109                                 pipe_idx++;
1110                         } else {
1111                                 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1112                                                 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1113                                 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
1114                                         pipes[pipe_cnt].pipe.dest.odm_combine =
1115                                                         context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];
1116                                 else
1117                                         pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1118                         }
1119                         pipe_cnt++;
1120         }
1121
1122         if (pipe_cnt != pipe_idx) {
1123                 if (dc->res_pool->funcs->populate_dml_pipes)
1124                         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
1125                                 context, pipes);
1126                 else
1127                         pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
1128                                 context, pipes);
1129         }
1130
1131         *out_pipe_cnt = pipe_cnt;
1132
1133         vlevel_max = bw_params->clk_table.num_entries - 1;
1134
1135
1136         /* WM Set D */
1137         table_entry = &bw_params->wm_table.entries[WM_D];
1138         if (table_entry->wm_type == WM_TYPE_RETRAINING)
1139                 vlevel = 0;
1140         else
1141                 vlevel = vlevel_max;
1142         calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
1143                                                 &context->bw_ctx.dml, pipes, pipe_cnt);
1144         /* WM Set C */
1145         table_entry = &bw_params->wm_table.entries[WM_C];
1146         vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
1147         calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
1148                                                 &context->bw_ctx.dml, pipes, pipe_cnt);
1149         /* WM Set B */
1150         table_entry = &bw_params->wm_table.entries[WM_B];
1151         vlevel = MIN(MAX(vlevel_req, 1), vlevel_max);
1152         calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
1153                                                 &context->bw_ctx.dml, pipes, pipe_cnt);
1154
1155         /* WM Set A */
1156         table_entry = &bw_params->wm_table.entries[WM_A];
1157         vlevel = MIN(vlevel_req, vlevel_max);
1158         calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
1159                                                 &context->bw_ctx.dml, pipes, pipe_cnt);
1160 }
1161
1162
1163 bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
1164                 bool fast_validate)
1165 {
1166         bool out = false;
1167
1168         BW_VAL_TRACE_SETUP();
1169
1170         int vlevel = 0;
1171         int pipe_split_from[MAX_PIPES];
1172         int pipe_cnt = 0;
1173         display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
1174         DC_LOGGER_INIT(dc->ctx->logger);
1175
1176         BW_VAL_TRACE_COUNT();
1177
1178         out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
1179
1180         if (pipe_cnt == 0)
1181                 goto validate_out;
1182
1183         if (!out)
1184                 goto validate_fail;
1185
1186         BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1187
1188         if (fast_validate) {
1189                 BW_VAL_TRACE_SKIP(fast);
1190                 goto validate_out;
1191         }
1192
1193         dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
1194         dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1195
1196         BW_VAL_TRACE_END_WATERMARKS();
1197
1198         goto validate_out;
1199
1200 validate_fail:
1201         DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1202                 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1203
1204         BW_VAL_TRACE_SKIP(fail);
1205         out = false;
1206
1207 validate_out:
1208         kfree(pipes);
1209
1210         BW_VAL_TRACE_FINISH();
1211
1212         return out;
1213 }
1214 static void dcn21_destroy_resource_pool(struct resource_pool **pool)
1215 {
1216         struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
1217
1218         dcn21_resource_destruct(dcn21_pool);
1219         kfree(dcn21_pool);
1220         *pool = NULL;
1221 }
1222
1223 static struct clock_source *dcn21_clock_source_create(
1224                 struct dc_context *ctx,
1225                 struct dc_bios *bios,
1226                 enum clock_source_id id,
1227                 const struct dce110_clk_src_regs *regs,
1228                 bool dp_clk_src)
1229 {
1230         struct dce110_clk_src *clk_src =
1231                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1232
1233         if (!clk_src)
1234                 return NULL;
1235
1236         if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1237                         regs, &cs_shift, &cs_mask)) {
1238                 clk_src->base.dp_clk_src = dp_clk_src;
1239                 return &clk_src->base;
1240         }
1241
1242         BREAK_TO_DEBUGGER();
1243         return NULL;
1244 }
1245
1246 static struct hubp *dcn21_hubp_create(
1247         struct dc_context *ctx,
1248         uint32_t inst)
1249 {
1250         struct dcn21_hubp *hubp21 =
1251                 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL);
1252
1253         if (!hubp21)
1254                 return NULL;
1255
1256         if (hubp21_construct(hubp21, ctx, inst,
1257                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1258                 return &hubp21->base;
1259
1260         BREAK_TO_DEBUGGER();
1261         kfree(hubp21);
1262         return NULL;
1263 }
1264
1265 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
1266 {
1267         int i;
1268
1269         struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1270                                           GFP_KERNEL);
1271
1272         if (!hubbub)
1273                 return NULL;
1274
1275         hubbub21_construct(hubbub, ctx,
1276                         &hubbub_reg,
1277                         &hubbub_shift,
1278                         &hubbub_mask);
1279
1280         for (i = 0; i < res_cap_rn.num_vmid; i++) {
1281                 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1282
1283                 vmid->ctx = ctx;
1284
1285                 vmid->regs = &vmid_regs[i];
1286                 vmid->shifts = &vmid_shifts;
1287                 vmid->masks = &vmid_masks;
1288         }
1289
1290         return &hubbub->base;
1291 }
1292
1293 struct output_pixel_processor *dcn21_opp_create(
1294         struct dc_context *ctx, uint32_t inst)
1295 {
1296         struct dcn20_opp *opp =
1297                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1298
1299         if (!opp) {
1300                 BREAK_TO_DEBUGGER();
1301                 return NULL;
1302         }
1303
1304         dcn20_opp_construct(opp, ctx, inst,
1305                         &opp_regs[inst], &opp_shift, &opp_mask);
1306         return &opp->base;
1307 }
1308
1309 struct timing_generator *dcn21_timing_generator_create(
1310                 struct dc_context *ctx,
1311                 uint32_t instance)
1312 {
1313         struct optc *tgn10 =
1314                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1315
1316         if (!tgn10)
1317                 return NULL;
1318
1319         tgn10->base.inst = instance;
1320         tgn10->base.ctx = ctx;
1321
1322         tgn10->tg_regs = &tg_regs[instance];
1323         tgn10->tg_shift = &tg_shift;
1324         tgn10->tg_mask = &tg_mask;
1325
1326         dcn20_timing_generator_init(tgn10);
1327
1328         return &tgn10->base;
1329 }
1330
1331 struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1332 {
1333         struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1334                                           GFP_KERNEL);
1335
1336         if (!mpc20)
1337                 return NULL;
1338
1339         dcn20_mpc_construct(mpc20, ctx,
1340                         &mpc_regs,
1341                         &mpc_shift,
1342                         &mpc_mask,
1343                         6);
1344
1345         return &mpc20->base;
1346 }
1347
1348 static void read_dce_straps(
1349         struct dc_context *ctx,
1350         struct resource_straps *straps)
1351 {
1352         generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1353                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1354
1355 }
1356
1357
1358 struct display_stream_compressor *dcn21_dsc_create(
1359         struct dc_context *ctx, uint32_t inst)
1360 {
1361         struct dcn20_dsc *dsc =
1362                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1363
1364         if (!dsc) {
1365                 BREAK_TO_DEBUGGER();
1366                 return NULL;
1367         }
1368
1369         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1370         return &dsc->base;
1371 }
1372
1373 static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1374 {
1375         struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
1376         struct clk_limit_table *clk_table = &bw_params->clk_table;
1377         unsigned int i, j, k;
1378         int closest_clk_lvl;
1379
1380         // Default clock levels are used for diags, which may lead to overclocking.
1381         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) && !IS_DIAG_DC(dc->ctx->dce_environment)) {
1382                 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1383                 dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
1384                 dcn2_1_soc.num_chans = bw_params->num_channels;
1385
1386                 /* Vmin: leave lowest DCN clocks, override with dcfclk, fclk, memclk from fuse */
1387                 dcn2_1_soc.clock_limits[0].state = 0;
1388                 dcn2_1_soc.clock_limits[0].dcfclk_mhz = clk_table->entries[0].dcfclk_mhz;
1389                 dcn2_1_soc.clock_limits[0].fabricclk_mhz = clk_table->entries[0].fclk_mhz;
1390                 dcn2_1_soc.clock_limits[0].socclk_mhz = clk_table->entries[0].socclk_mhz;
1391                 dcn2_1_soc.clock_limits[0].dram_speed_mts = clk_table->entries[0].memclk_mhz * 2;
1392
1393                 /*
1394                  * Other levels: find closest DCN clocks that fit the given clock limit using dcfclk
1395                  * as indicator
1396                  */
1397
1398                 closest_clk_lvl = -1;
1399                 /* index currently being filled */
1400                 k = 1;
1401                 for (i = 1; i < clk_table->num_entries; i++) {
1402                         /* loop backwards, skip duplicate state*/
1403                         for (j = dcn2_1_soc.num_states - 1; j >= k; j--) {
1404                                 if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
1405                                         closest_clk_lvl = j;
1406                                         break;
1407                                 }
1408                         }
1409
1410                         /* if found a lvl that fits, use the DCN clks from it, if not, go to next clk limit*/
1411                         if (closest_clk_lvl != -1) {
1412                                 dcn2_1_soc.clock_limits[k].state = i;
1413                                 dcn2_1_soc.clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
1414                                 dcn2_1_soc.clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
1415                                 dcn2_1_soc.clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
1416                                 dcn2_1_soc.clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
1417
1418                                 dcn2_1_soc.clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
1419                                 dcn2_1_soc.clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
1420                                 dcn2_1_soc.clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
1421                                 dcn2_1_soc.clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
1422                                 dcn2_1_soc.clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
1423                                 dcn2_1_soc.clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
1424                                 dcn2_1_soc.clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
1425                                 k++;
1426                         }
1427                 }
1428                 dcn2_1_soc.num_states = k;
1429         }
1430
1431         /* duplicate last level */
1432         dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
1433         dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states;
1434
1435         dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1436 }
1437
1438 /* Temporary Place holder until we can get them from fuse */
1439 static struct dpm_clocks dummy_clocks = {
1440                 .DcfClocks = {
1441                                 {.Freq = 400, .Vol = 1},
1442                                 {.Freq = 483, .Vol = 1},
1443                                 {.Freq = 602, .Vol = 1},
1444                                 {.Freq = 738, .Vol = 1} },
1445                 .SocClocks = {
1446                                 {.Freq = 300, .Vol = 1},
1447                                 {.Freq = 400, .Vol = 1},
1448                                 {.Freq = 400, .Vol = 1},
1449                                 {.Freq = 400, .Vol = 1} },
1450                 .FClocks = {
1451                                 {.Freq = 400, .Vol = 1},
1452                                 {.Freq = 800, .Vol = 1},
1453                                 {.Freq = 1067, .Vol = 1},
1454                                 {.Freq = 1600, .Vol = 1} },
1455                 .MemClocks = {
1456                                 {.Freq = 800, .Vol = 1},
1457                                 {.Freq = 1600, .Vol = 1},
1458                                 {.Freq = 1067, .Vol = 1},
1459                                 {.Freq = 1600, .Vol = 1} },
1460
1461 };
1462
1463 static enum pp_smu_status dummy_set_wm_ranges(struct pp_smu *pp,
1464                 struct pp_smu_wm_range_sets *ranges)
1465 {
1466         return PP_SMU_RESULT_OK;
1467 }
1468
1469 static enum pp_smu_status dummy_get_dpm_clock_table(struct pp_smu *pp,
1470                 struct dpm_clocks *clock_table)
1471 {
1472         *clock_table = dummy_clocks;
1473         return PP_SMU_RESULT_OK;
1474 }
1475
1476 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
1477 {
1478         struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
1479
1480         if (!pp_smu)
1481                 return pp_smu;
1482
1483         if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment) || IS_DIAG_DC(ctx->dce_environment)) {
1484                 pp_smu->ctx.ver = PP_SMU_VER_RN;
1485                 pp_smu->rn_funcs.get_dpm_clock_table = dummy_get_dpm_clock_table;
1486                 pp_smu->rn_funcs.set_wm_ranges = dummy_set_wm_ranges;
1487         } else {
1488
1489                 dm_pp_get_funcs(ctx, pp_smu);
1490
1491                 if (pp_smu->ctx.ver != PP_SMU_VER_RN)
1492                         pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
1493         }
1494
1495         return pp_smu;
1496 }
1497
1498 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
1499 {
1500         if (pp_smu && *pp_smu) {
1501                 kfree(*pp_smu);
1502                 *pp_smu = NULL;
1503         }
1504 }
1505
1506 static struct audio *dcn21_create_audio(
1507                 struct dc_context *ctx, unsigned int inst)
1508 {
1509         return dce_audio_create(ctx, inst,
1510                         &audio_regs[inst], &audio_shift, &audio_mask);
1511 }
1512
1513 static struct dc_cap_funcs cap_funcs = {
1514         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1515 };
1516
1517 struct stream_encoder *dcn21_stream_encoder_create(
1518         enum engine_id eng_id,
1519         struct dc_context *ctx)
1520 {
1521         struct dcn10_stream_encoder *enc1 =
1522                 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1523
1524         if (!enc1)
1525                 return NULL;
1526
1527         dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1528                                         &stream_enc_regs[eng_id],
1529                                         &se_shift, &se_mask);
1530
1531         return &enc1->base;
1532 }
1533
1534 static const struct dce_hwseq_registers hwseq_reg = {
1535                 HWSEQ_DCN21_REG_LIST()
1536 };
1537
1538 static const struct dce_hwseq_shift hwseq_shift = {
1539                 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
1540 };
1541
1542 static const struct dce_hwseq_mask hwseq_mask = {
1543                 HWSEQ_DCN21_MASK_SH_LIST(_MASK)
1544 };
1545
1546 static struct dce_hwseq *dcn21_hwseq_create(
1547         struct dc_context *ctx)
1548 {
1549         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1550
1551         if (hws) {
1552                 hws->ctx = ctx;
1553                 hws->regs = &hwseq_reg;
1554                 hws->shifts = &hwseq_shift;
1555                 hws->masks = &hwseq_mask;
1556                 hws->wa.DEGVIDCN21 = true;
1557                 hws->wa.disallow_self_refresh_during_multi_plane_transition = true;
1558         }
1559         return hws;
1560 }
1561
1562 static const struct resource_create_funcs res_create_funcs = {
1563         .read_dce_straps = read_dce_straps,
1564         .create_audio = dcn21_create_audio,
1565         .create_stream_encoder = dcn21_stream_encoder_create,
1566         .create_hwseq = dcn21_hwseq_create,
1567 };
1568
1569 static const struct resource_create_funcs res_create_maximus_funcs = {
1570         .read_dce_straps = NULL,
1571         .create_audio = NULL,
1572         .create_stream_encoder = NULL,
1573         .create_hwseq = dcn21_hwseq_create,
1574 };
1575
1576 static const struct encoder_feature_support link_enc_feature = {
1577                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1578                 .max_hdmi_pixel_clock = 600000,
1579                 .hdmi_ycbcr420_supported = true,
1580                 .dp_ycbcr420_supported = true,
1581                 .fec_supported = true,
1582                 .flags.bits.IS_HBR2_CAPABLE = true,
1583                 .flags.bits.IS_HBR3_CAPABLE = true,
1584                 .flags.bits.IS_TPS3_CAPABLE = true,
1585                 .flags.bits.IS_TPS4_CAPABLE = true
1586 };
1587
1588
1589 #define link_regs(id, phyid)\
1590 [id] = {\
1591         LE_DCN2_REG_LIST(id), \
1592         UNIPHY_DCN2_REG_LIST(phyid), \
1593         DPCS_DCN21_REG_LIST(id), \
1594         SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
1595 }
1596
1597 static const struct dcn10_link_enc_registers link_enc_regs[] = {
1598         link_regs(0, A),
1599         link_regs(1, B),
1600         link_regs(2, C),
1601         link_regs(3, D),
1602         link_regs(4, E),
1603 };
1604
1605 #define aux_regs(id)\
1606 [id] = {\
1607         DCN2_AUX_REG_LIST(id)\
1608 }
1609
1610 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
1611                 aux_regs(0),
1612                 aux_regs(1),
1613                 aux_regs(2),
1614                 aux_regs(3),
1615                 aux_regs(4)
1616 };
1617
1618 #define hpd_regs(id)\
1619 [id] = {\
1620         HPD_REG_LIST(id)\
1621 }
1622
1623 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1624                 hpd_regs(0),
1625                 hpd_regs(1),
1626                 hpd_regs(2),
1627                 hpd_regs(3),
1628                 hpd_regs(4)
1629 };
1630
1631 static const struct dcn10_link_enc_shift le_shift = {
1632         LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
1633         DPCS_DCN21_MASK_SH_LIST(__SHIFT)
1634 };
1635
1636 static const struct dcn10_link_enc_mask le_mask = {
1637         LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
1638         DPCS_DCN21_MASK_SH_LIST(_MASK)
1639 };
1640
1641 static int map_transmitter_id_to_phy_instance(
1642         enum transmitter transmitter)
1643 {
1644         switch (transmitter) {
1645         case TRANSMITTER_UNIPHY_A:
1646                 return 0;
1647         break;
1648         case TRANSMITTER_UNIPHY_B:
1649                 return 1;
1650         break;
1651         case TRANSMITTER_UNIPHY_C:
1652                 return 2;
1653         break;
1654         case TRANSMITTER_UNIPHY_D:
1655                 return 3;
1656         break;
1657         case TRANSMITTER_UNIPHY_E:
1658                 return 4;
1659         break;
1660         default:
1661                 ASSERT(0);
1662                 return 0;
1663         }
1664 }
1665
1666 static struct link_encoder *dcn21_link_encoder_create(
1667         const struct encoder_init_data *enc_init_data)
1668 {
1669         struct dcn21_link_encoder *enc21 =
1670                 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);
1671         int link_regs_id;
1672
1673         if (!enc21)
1674                 return NULL;
1675
1676         link_regs_id =
1677                 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1678
1679         dcn21_link_encoder_construct(enc21,
1680                                       enc_init_data,
1681                                       &link_enc_feature,
1682                                       &link_enc_regs[link_regs_id],
1683                                       &link_enc_aux_regs[enc_init_data->channel - 1],
1684                                       &link_enc_hpd_regs[enc_init_data->hpd_source],
1685                                       &le_shift,
1686                                       &le_mask);
1687
1688         return &enc21->enc10.base;
1689 }
1690 #define CTX ctx
1691
1692 #define REG(reg_name) \
1693         (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
1694
1695 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1696 {
1697         uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1698         /* RV1 support max 4 pipes */
1699         value = value & 0xf;
1700         return value;
1701 }
1702
1703 static int dcn21_populate_dml_pipes_from_context(
1704                 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes)
1705 {
1706         uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes);
1707         int i;
1708         struct resource_context *res_ctx = &context->res_ctx;
1709
1710         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1711
1712                 if (!res_ctx->pipe_ctx[i].stream)
1713                         continue;
1714
1715                 pipes[i].pipe.src.hostvm = 1;
1716                 pipes[i].pipe.src.gpuvm = 1;
1717         }
1718
1719         return pipe_cnt;
1720 }
1721
1722 enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1723 {
1724         enum dc_status result = DC_OK;
1725
1726         if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {
1727                 plane_state->dcc.enable = 1;
1728                 /* align to our worst case block width */
1729                 plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024;
1730         }
1731         result = dcn20_patch_unknown_plane_state(plane_state);
1732         return result;
1733 }
1734
1735 static struct resource_funcs dcn21_res_pool_funcs = {
1736         .destroy = dcn21_destroy_resource_pool,
1737         .link_enc_create = dcn21_link_encoder_create,
1738         .validate_bandwidth = dcn21_validate_bandwidth,
1739         .populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
1740         .add_stream_to_ctx = dcn20_add_stream_to_ctx,
1741         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1742         .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1743         .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
1744         .patch_unknown_plane_state = dcn21_patch_unknown_plane_state,
1745         .set_mcif_arb_params = dcn20_set_mcif_arb_params,
1746         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1747         .update_bw_bounding_box = update_bw_bounding_box
1748 };
1749
1750 static bool dcn21_resource_construct(
1751         uint8_t num_virtual_links,
1752         struct dc *dc,
1753         struct dcn21_resource_pool *pool)
1754 {
1755         int i, j;
1756         struct dc_context *ctx = dc->ctx;
1757         struct irq_service_init_data init_data;
1758         uint32_t pipe_fuses = read_pipe_fuses(ctx);
1759         uint32_t num_pipes;
1760
1761         ctx->dc_bios->regs = &bios_regs;
1762
1763         pool->base.res_cap = &res_cap_rn;
1764 #ifdef DIAGS_BUILD
1765         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1766                 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc;
1767                 pool->base.res_cap = &res_cap_rn_FPGA_4pipe;
1768 #endif
1769
1770         pool->base.funcs = &dcn21_res_pool_funcs;
1771
1772         /*************************************************
1773          *  Resource + asic cap harcoding                *
1774          *************************************************/
1775         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1776
1777         /* max pipe num for ASIC before check pipe fuses */
1778         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1779
1780         dc->caps.max_downscale_ratio = 200;
1781         dc->caps.i2c_speed_in_khz = 100;
1782         dc->caps.max_cursor_size = 256;
1783         dc->caps.dmdata_alloc_size = 2048;
1784         dc->caps.hw_3d_lut = true;
1785
1786         dc->caps.max_slave_planes = 1;
1787         dc->caps.post_blend_color_processing = true;
1788         dc->caps.force_dp_tps4_for_cp2520 = true;
1789         dc->caps.extended_aux_timeout_support = true;
1790         dc->caps.dmcub_support = true;
1791         dc->caps.is_apu = true;
1792
1793         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1794                 dc->debug = debug_defaults_drv;
1795         else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1796                 pool->base.pipe_count = 4;
1797                 dc->debug = debug_defaults_diags;
1798         } else
1799                 dc->debug = debug_defaults_diags;
1800
1801         // Init the vm_helper
1802         if (dc->vm_helper)
1803                 vm_helper_init(dc->vm_helper, 16);
1804
1805         /*************************************************
1806          *  Create resources                             *
1807          *************************************************/
1808
1809         pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
1810                         dcn21_clock_source_create(ctx, ctx->dc_bios,
1811                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1812                                 &clk_src_regs[0], false);
1813         pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
1814                         dcn21_clock_source_create(ctx, ctx->dc_bios,
1815                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1816                                 &clk_src_regs[1], false);
1817         pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
1818                         dcn21_clock_source_create(ctx, ctx->dc_bios,
1819                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
1820                                 &clk_src_regs[2], false);
1821
1822         pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
1823
1824         /* todo: not reuse phy_pll registers */
1825         pool->base.dp_clock_source =
1826                         dcn21_clock_source_create(ctx, ctx->dc_bios,
1827                                 CLOCK_SOURCE_ID_DP_DTO,
1828                                 &clk_src_regs[0], true);
1829
1830         for (i = 0; i < pool->base.clk_src_count; i++) {
1831                 if (pool->base.clock_sources[i] == NULL) {
1832                         dm_error("DC: failed to create clock sources!\n");
1833                         BREAK_TO_DEBUGGER();
1834                         goto create_fail;
1835                 }
1836         }
1837
1838         pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1839         if (pool->base.dccg == NULL) {
1840                 dm_error("DC: failed to create dccg!\n");
1841                 BREAK_TO_DEBUGGER();
1842                 goto create_fail;
1843         }
1844
1845         pool->base.dmcu = dcn21_dmcu_create(ctx,
1846                         &dmcu_regs,
1847                         &dmcu_shift,
1848                         &dmcu_mask);
1849         if (pool->base.dmcu == NULL) {
1850                 dm_error("DC: failed to create dmcu!\n");
1851                 BREAK_TO_DEBUGGER();
1852                 goto create_fail;
1853         }
1854
1855         if (dc->debug.disable_dmcu) {
1856                 pool->base.psr = dmub_psr_create(ctx);
1857
1858                 if (pool->base.psr == NULL) {
1859                         dm_error("DC: failed to create psr obj!\n");
1860                         BREAK_TO_DEBUGGER();
1861                         goto create_fail;
1862                 }
1863         }
1864
1865         pool->base.abm = dce_abm_create(ctx,
1866                         &abm_regs,
1867                         &abm_shift,
1868                         &abm_mask);
1869         if (pool->base.abm == NULL) {
1870                 dm_error("DC: failed to create abm!\n");
1871                 BREAK_TO_DEBUGGER();
1872                 goto create_fail;
1873         }
1874
1875         pool->base.pp_smu = dcn21_pp_smu_create(ctx);
1876
1877         num_pipes = dcn2_1_ip.max_num_dpp;
1878
1879         for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
1880                 if (pipe_fuses & 1 << i)
1881                         num_pipes--;
1882         dcn2_1_ip.max_num_dpp = num_pipes;
1883         dcn2_1_ip.max_num_otg = num_pipes;
1884
1885         dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1886
1887         init_data.ctx = dc->ctx;
1888         pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
1889         if (!pool->base.irqs)
1890                 goto create_fail;
1891
1892         j = 0;
1893         /* mem input -> ipp -> dpp -> opp -> TG */
1894         for (i = 0; i < pool->base.pipe_count; i++) {
1895                 /* if pipe is disabled, skip instance of HW pipe,
1896                  * i.e, skip ASIC register instance
1897                  */
1898                 if ((pipe_fuses & (1 << i)) != 0)
1899                         continue;
1900
1901                 pool->base.hubps[j] = dcn21_hubp_create(ctx, i);
1902                 if (pool->base.hubps[j] == NULL) {
1903                         BREAK_TO_DEBUGGER();
1904                         dm_error(
1905                                 "DC: failed to create memory input!\n");
1906                         goto create_fail;
1907                 }
1908
1909                 pool->base.ipps[j] = dcn21_ipp_create(ctx, i);
1910                 if (pool->base.ipps[j] == NULL) {
1911                         BREAK_TO_DEBUGGER();
1912                         dm_error(
1913                                 "DC: failed to create input pixel processor!\n");
1914                         goto create_fail;
1915                 }
1916
1917                 pool->base.dpps[j] = dcn21_dpp_create(ctx, i);
1918                 if (pool->base.dpps[j] == NULL) {
1919                         BREAK_TO_DEBUGGER();
1920                         dm_error(
1921                                 "DC: failed to create dpps!\n");
1922                         goto create_fail;
1923                 }
1924
1925                 pool->base.opps[j] = dcn21_opp_create(ctx, i);
1926                 if (pool->base.opps[j] == NULL) {
1927                         BREAK_TO_DEBUGGER();
1928                         dm_error(
1929                                 "DC: failed to create output pixel processor!\n");
1930                         goto create_fail;
1931                 }
1932
1933                 pool->base.timing_generators[j] = dcn21_timing_generator_create(
1934                                 ctx, i);
1935                 if (pool->base.timing_generators[j] == NULL) {
1936                         BREAK_TO_DEBUGGER();
1937                         dm_error("DC: failed to create tg!\n");
1938                         goto create_fail;
1939                 }
1940                 j++;
1941         }
1942
1943         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1944                 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
1945                 if (pool->base.engines[i] == NULL) {
1946                         BREAK_TO_DEBUGGER();
1947                         dm_error(
1948                                 "DC:failed to create aux engine!!\n");
1949                         goto create_fail;
1950                 }
1951                 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
1952                 if (pool->base.hw_i2cs[i] == NULL) {
1953                         BREAK_TO_DEBUGGER();
1954                         dm_error(
1955                                 "DC:failed to create hw i2c!!\n");
1956                         goto create_fail;
1957                 }
1958                 pool->base.sw_i2cs[i] = NULL;
1959         }
1960
1961         pool->base.timing_generator_count = j;
1962         pool->base.pipe_count = j;
1963         pool->base.mpcc_count = j;
1964
1965         pool->base.mpc = dcn21_mpc_create(ctx);
1966         if (pool->base.mpc == NULL) {
1967                 BREAK_TO_DEBUGGER();
1968                 dm_error("DC: failed to create mpc!\n");
1969                 goto create_fail;
1970         }
1971
1972         pool->base.hubbub = dcn21_hubbub_create(ctx);
1973         if (pool->base.hubbub == NULL) {
1974                 BREAK_TO_DEBUGGER();
1975                 dm_error("DC: failed to create hubbub!\n");
1976                 goto create_fail;
1977         }
1978
1979         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1980                 pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
1981                 if (pool->base.dscs[i] == NULL) {
1982                         BREAK_TO_DEBUGGER();
1983                         dm_error("DC: failed to create display stream compressor %d!\n", i);
1984                         goto create_fail;
1985                 }
1986         }
1987
1988         if (!dcn20_dwbc_create(ctx, &pool->base)) {
1989                 BREAK_TO_DEBUGGER();
1990                 dm_error("DC: failed to create dwbc!\n");
1991                 goto create_fail;
1992         }
1993         if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
1994                 BREAK_TO_DEBUGGER();
1995                 dm_error("DC: failed to create mcif_wb!\n");
1996                 goto create_fail;
1997         }
1998
1999         if (!resource_construct(num_virtual_links, dc, &pool->base,
2000                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2001                         &res_create_funcs : &res_create_maximus_funcs)))
2002                         goto create_fail;
2003
2004         dcn21_hw_sequencer_construct(dc);
2005
2006         dc->caps.max_planes =  pool->base.pipe_count;
2007
2008         for (i = 0; i < dc->caps.max_planes; ++i)
2009                 dc->caps.planes[i] = plane_cap;
2010
2011         dc->cap_funcs = cap_funcs;
2012
2013         return true;
2014
2015 create_fail:
2016
2017         dcn21_resource_destruct(pool);
2018
2019         return false;
2020 }
2021
2022 struct resource_pool *dcn21_create_resource_pool(
2023                 const struct dc_init_data *init_data,
2024                 struct dc *dc)
2025 {
2026         struct dcn21_resource_pool *pool =
2027                 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL);
2028
2029         if (!pool)
2030                 return NULL;
2031
2032         if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
2033                 return &pool->base;
2034
2035         BREAK_TO_DEBUGGER();
2036         kfree(pool);
2037         return NULL;
2038 }