drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

   1 /*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3  * Copyright 2019 Raptor Engineering, LLC
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: AMD
  24  *
  25  */
  26
  27 #include <linux/slab.h>
  28
  29 #include "dm_services.h"
  30 #include "dc.h"
  31
  32 #include "dcn20_init.h"
  33
  34 #include "resource.h"
  35 #include "include/irq_service_interface.h"
  36 #include "dcn20/dcn20_resource.h"
  37
  38 #include "dcn10/dcn10_hubp.h"
  39 #include "dcn10/dcn10_ipp.h"
  40 #include "dcn20_hubbub.h"
  41 #include "dcn20_mpc.h"
  42 #include "dcn20_hubp.h"
  43 #include "irq/dcn20/irq_service_dcn20.h"
  44 #include "dcn20_dpp.h"
  45 #include "dcn20_optc.h"
  46 #include "dcn20_hwseq.h"
  47 #include "dce110/dce110_hw_sequencer.h"
  48 #include "dcn10/dcn10_resource.h"
  49 #include "dcn20_opp.h"
  50
  51 #include "dcn20_dsc.h"
  52
  53 #include "dcn20_link_encoder.h"
  54 #include "dcn20_stream_encoder.h"
  55 #include "dce/dce_clock_source.h"
  56 #include "dce/dce_audio.h"
  57 #include "dce/dce_hwseq.h"
  58 #include "virtual/virtual_stream_encoder.h"
  59 #include "dce110/dce110_resource.h"
  60 #include "dml/display_mode_vba.h"
  61 #include "dcn20_dccg.h"
  62 #include "dcn20_vmid.h"
  63 #include "dc_link_ddc.h"
  64 #include "dce/dce_panel.h"
  65
  66 #include "navi10_ip_offset.h"
  67
  68 #include "dcn/dcn_2_0_0_offset.h"
  69 #include "dcn/dcn_2_0_0_sh_mask.h"
  70 #include "dpcs/dpcs_2_0_0_offset.h"
  71 #include "dpcs/dpcs_2_0_0_sh_mask.h"
  72
  73 #include "nbio/nbio_2_3_offset.h"
  74
  75 #include "dcn20/dcn20_dwb.h"
  76 #include "dcn20/dcn20_mmhubbub.h"
  77
  78 #include "mmhub/mmhub_2_0_0_offset.h"
  79 #include "mmhub/mmhub_2_0_0_sh_mask.h"
  80
  81 #include "reg_helper.h"
  82 #include "dce/dce_abm.h"
  83 #include "dce/dce_dmcu.h"
  84 #include "dce/dce_aux.h"
  85 #include "dce/dce_i2c.h"
  86 #include "vm_helper.h"
  87
  88 #include "amdgpu_socbb.h"
  89
  90 #define DC_LOGGER_INIT(logger)
  91
  92 struct _vcs_dpi_ip_params_st dcn2_0_ip = {
  93         .odm_capable = 1,
  94         .gpuvm_enable = 0,
  95         .hostvm_enable = 0,
  96         .gpuvm_max_page_table_levels = 4,
  97         .hostvm_max_page_table_levels = 4,
  98         .hostvm_cached_page_table_levels = 0,
  99         .pte_group_size_bytes = 2048,
 100         .num_dsc = 6,
 101         .rob_buffer_size_kbytes = 168,
 102         .det_buffer_size_kbytes = 164,
 103         .dpte_buffer_size_in_pte_reqs_luma = 84,
 104         .pde_proc_buffer_size_64k_reqs = 48,
 105         .dpp_output_buffer_pixels = 2560,
 106         .opp_output_buffer_lines = 1,
 107         .pixel_chunk_size_kbytes = 8,
 108         .pte_chunk_size_kbytes = 2,
 109         .meta_chunk_size_kbytes = 2,
 110         .writeback_chunk_size_kbytes = 2,
 111         .line_buffer_size_bits = 789504,
 112         .is_line_buffer_bpp_fixed = 0,
 113         .line_buffer_fixed_bpp = 0,
 114         .dcc_supported = true,
 115         .max_line_buffer_lines = 12,
 116         .writeback_luma_buffer_size_kbytes = 12,
 117         .writeback_chroma_buffer_size_kbytes = 8,
 118         .writeback_chroma_line_buffer_width_pixels = 4,
 119         .writeback_max_hscl_ratio = 1,
 120         .writeback_max_vscl_ratio = 1,
 121         .writeback_min_hscl_ratio = 1,
 122         .writeback_min_vscl_ratio = 1,
 123         .writeback_max_hscl_taps = 12,
 124         .writeback_max_vscl_taps = 12,
 125         .writeback_line_buffer_luma_buffer_size = 0,
 126         .writeback_line_buffer_chroma_buffer_size = 14643,
 127         .cursor_buffer_size = 8,
 128         .cursor_chunk_size = 2,
 129         .max_num_otg = 6,
 130         .max_num_dpp = 6,
 131         .max_num_wb = 1,
 132         .max_dchub_pscl_bw_pix_per_clk = 4,
 133         .max_pscl_lb_bw_pix_per_clk = 2,
 134         .max_lb_vscl_bw_pix_per_clk = 4,
 135         .max_vscl_hscl_bw_pix_per_clk = 4,
 136         .max_hscl_ratio = 8,
 137         .max_vscl_ratio = 8,
 138         .hscl_mults = 4,
 139         .vscl_mults = 4,
 140         .max_hscl_taps = 8,
 141         .max_vscl_taps = 8,
 142         .dispclk_ramp_margin_percent = 1,
 143         .underscan_factor = 1.10,
 144         .min_vblank_lines = 32, //
 145         .dppclk_delay_subtotal = 77, //
 146         .dppclk_delay_scl_lb_only = 16,
 147         .dppclk_delay_scl = 50,
 148         .dppclk_delay_cnvc_formatter = 8,
 149         .dppclk_delay_cnvc_cursor = 6,
 150         .dispclk_delay_subtotal = 87, //
 151         .dcfclk_cstate_latency = 10, // SRExitTime
 152         .max_inter_dcn_tile_repeaters = 8,
 153
 154         .xfc_supported = true,
 155         .xfc_fill_bw_overhead_percent = 10.0,
 156         .xfc_fill_constant_bytes = 0,
 157         .number_of_cursors = 1,
 158 };
 159
 160 struct _vcs_dpi_ip_params_st dcn2_0_nv14_ip = {
 161         .odm_capable = 1,
 162         .gpuvm_enable = 0,
 163         .hostvm_enable = 0,
 164         .gpuvm_max_page_table_levels = 4,
 165         .hostvm_max_page_table_levels = 4,
 166         .hostvm_cached_page_table_levels = 0,
 167         .num_dsc = 5,
 168         .rob_buffer_size_kbytes = 168,
 169         .det_buffer_size_kbytes = 164,
 170         .dpte_buffer_size_in_pte_reqs_luma = 84,
 171         .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
 172         .dpp_output_buffer_pixels = 2560,
 173         .opp_output_buffer_lines = 1,
 174         .pixel_chunk_size_kbytes = 8,
 175         .pte_enable = 1,
 176         .max_page_table_levels = 4,
 177         .pte_chunk_size_kbytes = 2,
 178         .meta_chunk_size_kbytes = 2,
 179         .writeback_chunk_size_kbytes = 2,
 180         .line_buffer_size_bits = 789504,
 181         .is_line_buffer_bpp_fixed = 0,
 182         .line_buffer_fixed_bpp = 0,
 183         .dcc_supported = true,
 184         .max_line_buffer_lines = 12,
 185         .writeback_luma_buffer_size_kbytes = 12,
 186         .writeback_chroma_buffer_size_kbytes = 8,
 187         .writeback_chroma_line_buffer_width_pixels = 4,
 188         .writeback_max_hscl_ratio = 1,
 189         .writeback_max_vscl_ratio = 1,
 190         .writeback_min_hscl_ratio = 1,
 191         .writeback_min_vscl_ratio = 1,
 192         .writeback_max_hscl_taps = 12,
 193         .writeback_max_vscl_taps = 12,
 194         .writeback_line_buffer_luma_buffer_size = 0,
 195         .writeback_line_buffer_chroma_buffer_size = 14643,
 196         .cursor_buffer_size = 8,
 197         .cursor_chunk_size = 2,
 198         .max_num_otg = 5,
 199         .max_num_dpp = 5,
 200         .max_num_wb = 1,
 201         .max_dchub_pscl_bw_pix_per_clk = 4,
 202         .max_pscl_lb_bw_pix_per_clk = 2,
 203         .max_lb_vscl_bw_pix_per_clk = 4,
 204         .max_vscl_hscl_bw_pix_per_clk = 4,
 205         .max_hscl_ratio = 8,
 206         .max_vscl_ratio = 8,
 207         .hscl_mults = 4,
 208         .vscl_mults = 4,
 209         .max_hscl_taps = 8,
 210         .max_vscl_taps = 8,
 211         .dispclk_ramp_margin_percent = 1,
 212         .underscan_factor = 1.10,
 213         .min_vblank_lines = 32, //
 214         .dppclk_delay_subtotal = 77, //
 215         .dppclk_delay_scl_lb_only = 16,
 216         .dppclk_delay_scl = 50,
 217         .dppclk_delay_cnvc_formatter = 8,
 218         .dppclk_delay_cnvc_cursor = 6,
 219         .dispclk_delay_subtotal = 87, //
 220         .dcfclk_cstate_latency = 10, // SRExitTime
 221         .max_inter_dcn_tile_repeaters = 8,
 222         .xfc_supported = true,
 223         .xfc_fill_bw_overhead_percent = 10.0,
 224         .xfc_fill_constant_bytes = 0,
 225         .ptoi_supported = 0,
 226         .number_of_cursors = 1,
 227 };
 228
 229 struct _vcs_dpi_soc_bounding_box_st dcn2_0_soc = {
 230         /* Defaults that get patched on driver load from firmware. */
 231         .clock_limits = {
 232                         {
 233                                 .state = 0,
 234                                 .dcfclk_mhz = 560.0,
 235                                 .fabricclk_mhz = 560.0,
 236                                 .dispclk_mhz = 513.0,
 237                                 .dppclk_mhz = 513.0,
 238                                 .phyclk_mhz = 540.0,
 239                                 .socclk_mhz = 560.0,
 240                                 .dscclk_mhz = 171.0,
 241                                 .dram_speed_mts = 8960.0,
 242                         },
 243                         {
 244                                 .state = 1,
 245                                 .dcfclk_mhz = 694.0,
 246                                 .fabricclk_mhz = 694.0,
 247                                 .dispclk_mhz = 642.0,
 248                                 .dppclk_mhz = 642.0,
 249                                 .phyclk_mhz = 600.0,
 250                                 .socclk_mhz = 694.0,
 251                                 .dscclk_mhz = 214.0,
 252                                 .dram_speed_mts = 11104.0,
 253                         },
 254                         {
 255                                 .state = 2,
 256                                 .dcfclk_mhz = 875.0,
 257                                 .fabricclk_mhz = 875.0,
 258                                 .dispclk_mhz = 734.0,
 259                                 .dppclk_mhz = 734.0,
 260                                 .phyclk_mhz = 810.0,
 261                                 .socclk_mhz = 875.0,
 262                                 .dscclk_mhz = 245.0,
 263                                 .dram_speed_mts = 14000.0,
 264                         },
 265                         {
 266                                 .state = 3,
 267                                 .dcfclk_mhz = 1000.0,
 268                                 .fabricclk_mhz = 1000.0,
 269                                 .dispclk_mhz = 1100.0,
 270                                 .dppclk_mhz = 1100.0,
 271                                 .phyclk_mhz = 810.0,
 272                                 .socclk_mhz = 1000.0,
 273                                 .dscclk_mhz = 367.0,
 274                                 .dram_speed_mts = 16000.0,
 275                         },
 276                         {
 277                                 .state = 4,
 278                                 .dcfclk_mhz = 1200.0,
 279                                 .fabricclk_mhz = 1200.0,
 280                                 .dispclk_mhz = 1284.0,
 281                                 .dppclk_mhz = 1284.0,
 282                                 .phyclk_mhz = 810.0,
 283                                 .socclk_mhz = 1200.0,
 284                                 .dscclk_mhz = 428.0,
 285                                 .dram_speed_mts = 16000.0,
 286                         },
 287                         /*Extra state, no dispclk ramping*/
 288                         {
 289                                 .state = 5,
 290                                 .dcfclk_mhz = 1200.0,
 291                                 .fabricclk_mhz = 1200.0,
 292                                 .dispclk_mhz = 1284.0,
 293                                 .dppclk_mhz = 1284.0,
 294                                 .phyclk_mhz = 810.0,
 295                                 .socclk_mhz = 1200.0,
 296                                 .dscclk_mhz = 428.0,
 297                                 .dram_speed_mts = 16000.0,
 298                         },
 299                 },
 300         .num_states = 5,
 301         .sr_exit_time_us = 8.6,
 302         .sr_enter_plus_exit_time_us = 10.9,
 303         .urgent_latency_us = 4.0,
 304         .urgent_latency_pixel_data_only_us = 4.0,
 305         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 306         .urgent_latency_vm_data_only_us = 4.0,
 307         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 308         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 309         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 310         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
 311         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
 312         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
 313         .max_avg_sdp_bw_use_normal_percent = 40.0,
 314         .max_avg_dram_bw_use_normal_percent = 40.0,
 315         .writeback_latency_us = 12.0,
 316         .ideal_dram_bw_after_urgent_percent = 40.0,
 317         .max_request_size_bytes = 256,
 318         .dram_channel_width_bytes = 2,
 319         .fabric_datapath_to_dcn_data_return_bytes = 64,
 320         .dcn_downspread_percent = 0.5,
 321         .downspread_percent = 0.38,
 322         .dram_page_open_time_ns = 50.0,
 323         .dram_rw_turnaround_time_ns = 17.5,
 324         .dram_return_buffer_per_channel_bytes = 8192,
 325         .round_trip_ping_latency_dcfclk_cycles = 131,
 326         .urgent_out_of_order_return_per_channel_bytes = 256,
 327         .channel_interleave_bytes = 256,
 328         .num_banks = 8,
 329         .num_chans = 16,
 330         .vmm_page_size_bytes = 4096,
 331         .dram_clock_change_latency_us = 404.0,
 332         .dummy_pstate_latency_us = 5.0,
 333         .writeback_dram_clock_change_latency_us = 23.0,
 334         .return_bus_width_bytes = 64,
 335         .dispclk_dppclk_vco_speed_mhz = 3850,
 336         .xfc_bus_transport_time_us = 20,
 337         .xfc_xbuf_latency_tolerance_us = 4,
 338         .use_urgent_burst_bw = 0
 339 };
 340
 341 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv14_soc = {
 342         .clock_limits = {
 343                         {
 344                                 .state = 0,
 345                                 .dcfclk_mhz = 560.0,
 346                                 .fabricclk_mhz = 560.0,
 347                                 .dispclk_mhz = 513.0,
 348                                 .dppclk_mhz = 513.0,
 349                                 .phyclk_mhz = 540.0,
 350                                 .socclk_mhz = 560.0,
 351                                 .dscclk_mhz = 171.0,
 352                                 .dram_speed_mts = 8960.0,
 353                         },
 354                         {
 355                                 .state = 1,
 356                                 .dcfclk_mhz = 694.0,
 357                                 .fabricclk_mhz = 694.0,
 358                                 .dispclk_mhz = 642.0,
 359                                 .dppclk_mhz = 642.0,
 360                                 .phyclk_mhz = 600.0,
 361                                 .socclk_mhz = 694.0,
 362                                 .dscclk_mhz = 214.0,
 363                                 .dram_speed_mts = 11104.0,
 364                         },
 365                         {
 366                                 .state = 2,
 367                                 .dcfclk_mhz = 875.0,
 368                                 .fabricclk_mhz = 875.0,
 369                                 .dispclk_mhz = 734.0,
 370                                 .dppclk_mhz = 734.0,
 371                                 .phyclk_mhz = 810.0,
 372                                 .socclk_mhz = 875.0,
 373                                 .dscclk_mhz = 245.0,
 374                                 .dram_speed_mts = 14000.0,
 375                         },
 376                         {
 377                                 .state = 3,
 378                                 .dcfclk_mhz = 1000.0,
 379                                 .fabricclk_mhz = 1000.0,
 380                                 .dispclk_mhz = 1100.0,
 381                                 .dppclk_mhz = 1100.0,
 382                                 .phyclk_mhz = 810.0,
 383                                 .socclk_mhz = 1000.0,
 384                                 .dscclk_mhz = 367.0,
 385                                 .dram_speed_mts = 16000.0,
 386                         },
 387                         {
 388                                 .state = 4,
 389                                 .dcfclk_mhz = 1200.0,
 390                                 .fabricclk_mhz = 1200.0,
 391                                 .dispclk_mhz = 1284.0,
 392                                 .dppclk_mhz = 1284.0,
 393                                 .phyclk_mhz = 810.0,
 394                                 .socclk_mhz = 1200.0,
 395                                 .dscclk_mhz = 428.0,
 396                                 .dram_speed_mts = 16000.0,
 397                         },
 398                         /*Extra state, no dispclk ramping*/
 399                         {
 400                                 .state = 5,
 401                                 .dcfclk_mhz = 1200.0,
 402                                 .fabricclk_mhz = 1200.0,
 403                                 .dispclk_mhz = 1284.0,
 404                                 .dppclk_mhz = 1284.0,
 405                                 .phyclk_mhz = 810.0,
 406                                 .socclk_mhz = 1200.0,
 407                                 .dscclk_mhz = 428.0,
 408                                 .dram_speed_mts = 16000.0,
 409                         },
 410                 },
 411         .num_states = 5,
 412         .sr_exit_time_us = 8.6,
 413         .sr_enter_plus_exit_time_us = 10.9,
 414         .urgent_latency_us = 4.0,
 415         .urgent_latency_pixel_data_only_us = 4.0,
 416         .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
 417         .urgent_latency_vm_data_only_us = 4.0,
 418         .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
 419         .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
 420         .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
 421         .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 40.0,
 422         .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 40.0,
 423         .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
 424         .max_avg_sdp_bw_use_normal_percent = 40.0,
 425         .max_avg_dram_bw_use_normal_percent = 40.0,
 426         .writeback_latency_us = 12.0,
 427         .ideal_dram_bw_after_urgent_percent = 40.0,
 428         .max_request_size_bytes = 256,
 429         .dram_channel_width_bytes = 2,
 430         .fabric_datapath_to_dcn_data_return_bytes = 64,
 431         .dcn_downspread_percent = 0.5,
 432         .downspread_percent = 0.38,
 433         .dram_page_open_time_ns = 50.0,
 434         .dram_rw_turnaround_time_ns = 17.5,
 435         .dram_return_buffer_per_channel_bytes = 8192,
 436         .round_trip_ping_latency_dcfclk_cycles = 131,
 437         .urgent_out_of_order_return_per_channel_bytes = 256,
 438         .channel_interleave_bytes = 256,
 439         .num_banks = 8,
 440         .num_chans = 8,
 441         .vmm_page_size_bytes = 4096,
 442         .dram_clock_change_latency_us = 404.0,
 443         .dummy_pstate_latency_us = 5.0,
 444         .writeback_dram_clock_change_latency_us = 23.0,
 445         .return_bus_width_bytes = 64,
 446         .dispclk_dppclk_vco_speed_mhz = 3850,
 447         .xfc_bus_transport_time_us = 20,
 448         .xfc_xbuf_latency_tolerance_us = 4,
 449         .use_urgent_burst_bw = 0
 450 };
 451
 452 struct _vcs_dpi_soc_bounding_box_st dcn2_0_nv12_soc = { 0 };
 453
 454 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
 455         #define mmDP0_DP_DPHY_INTERNAL_CTRL             0x210f
 456         #define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 457         #define mmDP1_DP_DPHY_INTERNAL_CTRL             0x220f
 458         #define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 459         #define mmDP2_DP_DPHY_INTERNAL_CTRL             0x230f
 460         #define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 461         #define mmDP3_DP_DPHY_INTERNAL_CTRL             0x240f
 462         #define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 463         #define mmDP4_DP_DPHY_INTERNAL_CTRL             0x250f
 464         #define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 465         #define mmDP5_DP_DPHY_INTERNAL_CTRL             0x260f
 466         #define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 467         #define mmDP6_DP_DPHY_INTERNAL_CTRL             0x270f
 468         #define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX    2
 469 #endif
 470
 471
 472 enum dcn20_clk_src_array_id {
 473         DCN20_CLK_SRC_PLL0,
 474         DCN20_CLK_SRC_PLL1,
 475         DCN20_CLK_SRC_PLL2,
 476         DCN20_CLK_SRC_PLL3,
 477         DCN20_CLK_SRC_PLL4,
 478         DCN20_CLK_SRC_PLL5,
 479         DCN20_CLK_SRC_TOTAL
 480 };
 481
 482 /* begin *********************
 483  * macros to expend register list macro defined in HW object header file */
 484
 485 /* DCN */
 486 /* TODO awful hack. fixup dcn20_dwb.h */
 487 #undef BASE_INNER
 488 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
 489
 490 #define BASE(seg) BASE_INNER(seg)
 491
 492 #define SR(reg_name)\
 493                 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
 494                                         mm ## reg_name
 495
 496 #define SRI(reg_name, block, id)\
 497         .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 498                                         mm ## block ## id ## _ ## reg_name
 499
 500 #define SRIR(var_name, reg_name, block, id)\
 501         .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 502                                         mm ## block ## id ## _ ## reg_name
 503
 504 #define SRII(reg_name, block, id)\
 505         .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 506                                         mm ## block ## id ## _ ## reg_name
 507
 508 #define DCCG_SRII(reg_name, block, id)\
 509         .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
 510                                         mm ## block ## id ## _ ## reg_name
 511
 512 /* NBIO */
 513 #define NBIO_BASE_INNER(seg) \
 514         NBIO_BASE__INST0_SEG ## seg
 515
 516 #define NBIO_BASE(seg) \
 517         NBIO_BASE_INNER(seg)
 518
 519 #define NBIO_SR(reg_name)\
 520                 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
 521                                         mm ## reg_name
 522
 523 /* MMHUB */
 524 #define MMHUB_BASE_INNER(seg) \
 525         MMHUB_BASE__INST0_SEG ## seg
 526
 527 #define MMHUB_BASE(seg) \
 528         MMHUB_BASE_INNER(seg)
 529
 530 #define MMHUB_SR(reg_name)\
 531                 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
 532                                         mmMM ## reg_name
 533
 534 static const struct bios_registers bios_regs = {
 535                 NBIO_SR(BIOS_SCRATCH_3),
 536                 NBIO_SR(BIOS_SCRATCH_6)
 537 };
 538
 539 #define clk_src_regs(index, pllid)\
 540 [index] = {\
 541         CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
 542 }
 543
 544 static const struct dce110_clk_src_regs clk_src_regs[] = {
 545         clk_src_regs(0, A),
 546         clk_src_regs(1, B),
 547         clk_src_regs(2, C),
 548         clk_src_regs(3, D),
 549         clk_src_regs(4, E),
 550         clk_src_regs(5, F)
 551 };
 552
 553 static const struct dce110_clk_src_shift cs_shift = {
 554                 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 555 };
 556
 557 static const struct dce110_clk_src_mask cs_mask = {
 558                 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 559 };
 560
 561 static const struct dce_dmcu_registers dmcu_regs = {
 562                 DMCU_DCN10_REG_LIST()
 563 };
 564
 565 static const struct dce_dmcu_shift dmcu_shift = {
 566                 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
 567 };
 568
 569 static const struct dce_dmcu_mask dmcu_mask = {
 570                 DMCU_MASK_SH_LIST_DCN10(_MASK)
 571 };
 572
 573 static const struct dce_abm_registers abm_regs = {
 574                 ABM_DCN20_REG_LIST()
 575 };
 576
 577 static const struct dce_abm_shift abm_shift = {
 578                 ABM_MASK_SH_LIST_DCN20(__SHIFT)
 579 };
 580
 581 static const struct dce_abm_mask abm_mask = {
 582                 ABM_MASK_SH_LIST_DCN20(_MASK)
 583 };
 584
 585 #define audio_regs(id)\
 586 [id] = {\
 587                 AUD_COMMON_REG_LIST(id)\
 588 }
 589
 590 static const struct dce_audio_registers audio_regs[] = {
 591         audio_regs(0),
 592         audio_regs(1),
 593         audio_regs(2),
 594         audio_regs(3),
 595         audio_regs(4),
 596         audio_regs(5),
 597         audio_regs(6),
 598 };
 599
 600 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
 601                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
 602                 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
 603                 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
 604
 605 static const struct dce_audio_shift audio_shift = {
 606                 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
 607 };
 608
 609 static const struct dce_audio_mask audio_mask = {
 610                 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
 611 };
 612
 613 #define stream_enc_regs(id)\
 614 [id] = {\
 615         SE_DCN2_REG_LIST(id)\
 616 }
 617
 618 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
 619         stream_enc_regs(0),
 620         stream_enc_regs(1),
 621         stream_enc_regs(2),
 622         stream_enc_regs(3),
 623         stream_enc_regs(4),
 624         stream_enc_regs(5),
 625 };
 626
 627 static const struct dcn10_stream_encoder_shift se_shift = {
 628                 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
 629 };
 630
 631 static const struct dcn10_stream_encoder_mask se_mask = {
 632                 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
 633 };
 634
 635
 636 #define aux_regs(id)\
 637 [id] = {\
 638         DCN2_AUX_REG_LIST(id)\
 639 }
 640
 641 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
 642                 aux_regs(0),
 643                 aux_regs(1),
 644                 aux_regs(2),
 645                 aux_regs(3),
 646                 aux_regs(4),
 647                 aux_regs(5)
 648 };
 649
 650 #define hpd_regs(id)\
 651 [id] = {\
 652         HPD_REG_LIST(id)\
 653 }
 654
 655 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
 656                 hpd_regs(0),
 657                 hpd_regs(1),
 658                 hpd_regs(2),
 659                 hpd_regs(3),
 660                 hpd_regs(4),
 661                 hpd_regs(5)
 662 };
 663
 664 #define link_regs(id, phyid)\
 665 [id] = {\
 666         LE_DCN10_REG_LIST(id), \
 667         UNIPHY_DCN2_REG_LIST(phyid), \
 668         DPCS_DCN2_REG_LIST(id), \
 669         SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
 670 }
 671
 672 static const struct dcn10_link_enc_registers link_enc_regs[] = {
 673         link_regs(0, A),
 674         link_regs(1, B),
 675         link_regs(2, C),
 676         link_regs(3, D),
 677         link_regs(4, E),
 678         link_regs(5, F)
 679 };
 680
 681 static const struct dcn10_link_enc_shift le_shift = {
 682         LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
 683         DPCS_DCN2_MASK_SH_LIST(__SHIFT)
 684 };
 685
 686 static const struct dcn10_link_enc_mask le_mask = {
 687         LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
 688         DPCS_DCN2_MASK_SH_LIST(_MASK)
 689 };
 690
 691 static const struct dce_panel_registers panel_regs[] = {
 692         { DCN_PANEL_REG_LIST() }
 693 };
 694
 695 static const struct dce_panel_shift panel_shift = {
 696         DCE_PANEL_MASK_SH_LIST(__SHIFT)
 697 };
 698
 699 static const struct dce_panel_mask panel_mask = {
 700         DCE_PANEL_MASK_SH_LIST(_MASK)
 701 };
 702
 703 #define ipp_regs(id)\
 704 [id] = {\
 705         IPP_REG_LIST_DCN20(id),\
 706 }
 707
 708 static const struct dcn10_ipp_registers ipp_regs[] = {
 709         ipp_regs(0),
 710         ipp_regs(1),
 711         ipp_regs(2),
 712         ipp_regs(3),
 713         ipp_regs(4),
 714         ipp_regs(5),
 715 };
 716
 717 static const struct dcn10_ipp_shift ipp_shift = {
 718                 IPP_MASK_SH_LIST_DCN20(__SHIFT)
 719 };
 720
 721 static const struct dcn10_ipp_mask ipp_mask = {
 722                 IPP_MASK_SH_LIST_DCN20(_MASK),
 723 };
 724
 725 #define opp_regs(id)\
 726 [id] = {\
 727         OPP_REG_LIST_DCN20(id),\
 728 }
 729
 730 static const struct dcn20_opp_registers opp_regs[] = {
 731         opp_regs(0),
 732         opp_regs(1),
 733         opp_regs(2),
 734         opp_regs(3),
 735         opp_regs(4),
 736         opp_regs(5),
 737 };
 738
 739 static const struct dcn20_opp_shift opp_shift = {
 740                 OPP_MASK_SH_LIST_DCN20(__SHIFT)
 741 };
 742
 743 static const struct dcn20_opp_mask opp_mask = {
 744                 OPP_MASK_SH_LIST_DCN20(_MASK)
 745 };
 746
 747 #define aux_engine_regs(id)\
 748 [id] = {\
 749         AUX_COMMON_REG_LIST0(id), \
 750         .AUXN_IMPCAL = 0, \
 751         .AUXP_IMPCAL = 0, \
 752         .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
 753 }
 754
 755 static const struct dce110_aux_registers aux_engine_regs[] = {
 756                 aux_engine_regs(0),
 757                 aux_engine_regs(1),
 758                 aux_engine_regs(2),
 759                 aux_engine_regs(3),
 760                 aux_engine_regs(4),
 761                 aux_engine_regs(5)
 762 };
 763
 764 #define tf_regs(id)\
 765 [id] = {\
 766         TF_REG_LIST_DCN20(id),\
 767         TF_REG_LIST_DCN20_COMMON_APPEND(id),\
 768 }
 769
 770 static const struct dcn2_dpp_registers tf_regs[] = {
 771         tf_regs(0),
 772         tf_regs(1),
 773         tf_regs(2),
 774         tf_regs(3),
 775         tf_regs(4),
 776         tf_regs(5),
 777 };
 778
 779 static const struct dcn2_dpp_shift tf_shift = {
 780                 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
 781                 TF_DEBUG_REG_LIST_SH_DCN20
 782 };
 783
 784 static const struct dcn2_dpp_mask tf_mask = {
 785                 TF_REG_LIST_SH_MASK_DCN20(_MASK),
 786                 TF_DEBUG_REG_LIST_MASK_DCN20
 787 };
 788
 789 #define dwbc_regs_dcn2(id)\
 790 [id] = {\
 791         DWBC_COMMON_REG_LIST_DCN2_0(id),\
 792                 }
 793
 794 static const struct dcn20_dwbc_registers dwbc20_regs[] = {
 795         dwbc_regs_dcn2(0),
 796 };
 797
 798 static const struct dcn20_dwbc_shift dwbc20_shift = {
 799         DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 800 };
 801
 802 static const struct dcn20_dwbc_mask dwbc20_mask = {
 803         DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 804 };
 805
 806 #define mcif_wb_regs_dcn2(id)\
 807 [id] = {\
 808         MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\
 809                 }
 810
 811 static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = {
 812         mcif_wb_regs_dcn2(0),
 813 };
 814
 815 static const struct dcn20_mmhubbub_shift mcif_wb20_shift = {
 816         MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 817 };
 818
 819 static const struct dcn20_mmhubbub_mask mcif_wb20_mask = {
 820         MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 821 };
 822
 823 static const struct dcn20_mpc_registers mpc_regs = {
 824                 MPC_REG_LIST_DCN2_0(0),
 825                 MPC_REG_LIST_DCN2_0(1),
 826                 MPC_REG_LIST_DCN2_0(2),
 827                 MPC_REG_LIST_DCN2_0(3),
 828                 MPC_REG_LIST_DCN2_0(4),
 829                 MPC_REG_LIST_DCN2_0(5),
 830                 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
 831                 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
 832                 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
 833                 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
 834                 MPC_OUT_MUX_REG_LIST_DCN2_0(4),
 835                 MPC_OUT_MUX_REG_LIST_DCN2_0(5),
 836                 MPC_DBG_REG_LIST_DCN2_0()
 837 };
 838
 839 static const struct dcn20_mpc_shift mpc_shift = {
 840         MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
 841         MPC_DEBUG_REG_LIST_SH_DCN20
 842 };
 843
 844 static const struct dcn20_mpc_mask mpc_mask = {
 845         MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
 846         MPC_DEBUG_REG_LIST_MASK_DCN20
 847 };
 848
 849 #define tg_regs(id)\
 850 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
 851
 852
 853 static const struct dcn_optc_registers tg_regs[] = {
 854         tg_regs(0),
 855         tg_regs(1),
 856         tg_regs(2),
 857         tg_regs(3),
 858         tg_regs(4),
 859         tg_regs(5)
 860 };
 861
 862 static const struct dcn_optc_shift tg_shift = {
 863         TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
 864 };
 865
 866 static const struct dcn_optc_mask tg_mask = {
 867         TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
 868 };
 869
 870 #define hubp_regs(id)\
 871 [id] = {\
 872         HUBP_REG_LIST_DCN20(id)\
 873 }
 874
 875 static const struct dcn_hubp2_registers hubp_regs[] = {
 876                 hubp_regs(0),
 877                 hubp_regs(1),
 878                 hubp_regs(2),
 879                 hubp_regs(3),
 880                 hubp_regs(4),
 881                 hubp_regs(5)
 882 };
 883
 884 static const struct dcn_hubp2_shift hubp_shift = {
 885                 HUBP_MASK_SH_LIST_DCN20(__SHIFT)
 886 };
 887
 888 static const struct dcn_hubp2_mask hubp_mask = {
 889                 HUBP_MASK_SH_LIST_DCN20(_MASK)
 890 };
 891
 892 static const struct dcn_hubbub_registers hubbub_reg = {
 893                 HUBBUB_REG_LIST_DCN20(0)
 894 };
 895
 896 static const struct dcn_hubbub_shift hubbub_shift = {
 897                 HUBBUB_MASK_SH_LIST_DCN20(__SHIFT)
 898 };
 899
 900 static const struct dcn_hubbub_mask hubbub_mask = {
 901                 HUBBUB_MASK_SH_LIST_DCN20(_MASK)
 902 };
 903
 904 #define vmid_regs(id)\
 905 [id] = {\
 906                 DCN20_VMID_REG_LIST(id)\
 907 }
 908
 909 static const struct dcn_vmid_registers vmid_regs[] = {
 910         vmid_regs(0),
 911         vmid_regs(1),
 912         vmid_regs(2),
 913         vmid_regs(3),
 914         vmid_regs(4),
 915         vmid_regs(5),
 916         vmid_regs(6),
 917         vmid_regs(7),
 918         vmid_regs(8),
 919         vmid_regs(9),
 920         vmid_regs(10),
 921         vmid_regs(11),
 922         vmid_regs(12),
 923         vmid_regs(13),
 924         vmid_regs(14),
 925         vmid_regs(15)
 926 };
 927
 928 static const struct dcn20_vmid_shift vmid_shifts = {
 929                 DCN20_VMID_MASK_SH_LIST(__SHIFT)
 930 };
 931
 932 static const struct dcn20_vmid_mask vmid_masks = {
 933                 DCN20_VMID_MASK_SH_LIST(_MASK)
 934 };
 935
 936 static const struct dce110_aux_registers_shift aux_shift = {
 937                 DCN_AUX_MASK_SH_LIST(__SHIFT)
 938 };
 939
 940 static const struct dce110_aux_registers_mask aux_mask = {
 941                 DCN_AUX_MASK_SH_LIST(_MASK)
 942 };
 943
 944 static int map_transmitter_id_to_phy_instance(
 945         enum transmitter transmitter)
 946 {
 947         switch (transmitter) {
 948         case TRANSMITTER_UNIPHY_A:
 949                 return 0;
 950         break;
 951         case TRANSMITTER_UNIPHY_B:
 952                 return 1;
 953         break;
 954         case TRANSMITTER_UNIPHY_C:
 955                 return 2;
 956         break;
 957         case TRANSMITTER_UNIPHY_D:
 958                 return 3;
 959         break;
 960         case TRANSMITTER_UNIPHY_E:
 961                 return 4;
 962         break;
 963         case TRANSMITTER_UNIPHY_F:
 964                 return 5;
 965         break;
 966         default:
 967                 ASSERT(0);
 968                 return 0;
 969         }
 970 }
 971
 972 #define dsc_regsDCN20(id)\
 973 [id] = {\
 974         DSC_REG_LIST_DCN20(id)\
 975 }
 976
 977 static const struct dcn20_dsc_registers dsc_regs[] = {
 978         dsc_regsDCN20(0),
 979         dsc_regsDCN20(1),
 980         dsc_regsDCN20(2),
 981         dsc_regsDCN20(3),
 982         dsc_regsDCN20(4),
 983         dsc_regsDCN20(5)
 984 };
 985
 986 static const struct dcn20_dsc_shift dsc_shift = {
 987         DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
 988 };
 989
 990 static const struct dcn20_dsc_mask dsc_mask = {
 991         DSC_REG_LIST_SH_MASK_DCN20(_MASK)
 992 };
 993
 994 static const struct dccg_registers dccg_regs = {
 995                 DCCG_REG_LIST_DCN2()
 996 };
 997
 998 static const struct dccg_shift dccg_shift = {
 999                 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
1000 };
1001
1002 static const struct dccg_mask dccg_mask = {
1003                 DCCG_MASK_SH_LIST_DCN2(_MASK)
1004 };
1005
1006 static const struct resource_caps res_cap_nv10 = {
1007                 .num_timing_generator = 6,
1008                 .num_opp = 6,
1009                 .num_video_plane = 6,
1010                 .num_audio = 7,
1011                 .num_stream_encoder = 6,
1012                 .num_pll = 6,
1013                 .num_dwb = 1,
1014                 .num_ddc = 6,
1015                 .num_vmid = 16,
1016                 .num_dsc = 6,
1017 };
1018
1019 static const struct dc_plane_cap plane_cap = {
1020         .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
1021         .blends_with_above = true,
1022         .blends_with_below = true,
1023         .per_pixel_alpha = true,
1024
1025         .pixel_format_support = {
1026                         .argb8888 = true,
1027                         .nv12 = true,
1028                         .fp16 = true,
1029                         .p010 = true
1030         },
1031
1032         .max_upscale_factor = {
1033                         .argb8888 = 16000,
1034                         .nv12 = 16000,
1035                         .fp16 = 1
1036         },
1037
1038         .max_downscale_factor = {
1039                         .argb8888 = 250,
1040                         .nv12 = 250,
1041                         .fp16 = 1
1042         }
1043 };
1044 static const struct resource_caps res_cap_nv14 = {
1045                 .num_timing_generator = 5,
1046                 .num_opp = 5,
1047                 .num_video_plane = 5,
1048                 .num_audio = 6,
1049                 .num_stream_encoder = 5,
1050                 .num_pll = 5,
1051                 .num_dwb = 1,
1052                 .num_ddc = 5,
1053                 .num_vmid = 16,
1054                 .num_dsc = 5,
1055 };
1056
1057 static const struct dc_debug_options debug_defaults_drv = {
1058                 .disable_dmcu = false,
1059                 .force_abm_enable = false,
1060                 .timing_trace = false,
1061                 .clock_trace = true,
1062                 .disable_pplib_clock_request = true,
1063                 .pipe_split_policy = MPC_SPLIT_DYNAMIC,
1064                 .force_single_disp_pipe_split = false,
1065                 .disable_dcc = DCC_ENABLE,
1066                 .vsr_support = true,
1067                 .performance_trace = false,
1068                 .max_downscale_src_width = 5120,/*upto 5K*/
1069                 .disable_pplib_wm_range = false,
1070                 .scl_reset_length10 = true,
1071                 .sanity_checks = false,
1072                 .disable_tri_buf = true,
1073                 .underflow_assert_delay_us = 0xFFFFFFFF,
1074 };
1075
1076 static const struct dc_debug_options debug_defaults_diags = {
1077                 .disable_dmcu = false,
1078                 .force_abm_enable = false,
1079                 .timing_trace = true,
1080                 .clock_trace = true,
1081                 .disable_dpp_power_gate = true,
1082                 .disable_hubp_power_gate = true,
1083                 .disable_clock_gate = true,
1084                 .disable_pplib_clock_request = true,
1085                 .disable_pplib_wm_range = true,
1086                 .disable_stutter = true,
1087                 .scl_reset_length10 = true,
1088                 .underflow_assert_delay_us = 0xFFFFFFFF,
1089 };
1090
1091 void dcn20_dpp_destroy(struct dpp **dpp)
1092 {
1093         kfree(TO_DCN20_DPP(*dpp));
1094         *dpp = NULL;
1095 }
1096
1097 struct dpp *dcn20_dpp_create(
1098         struct dc_context *ctx,
1099         uint32_t inst)
1100 {
1101         struct dcn20_dpp *dpp =
1102                 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
1103
1104         if (!dpp)
1105                 return NULL;
1106
1107         if (dpp2_construct(dpp, ctx, inst,
1108                         &tf_regs[inst], &tf_shift, &tf_mask))
1109                 return &dpp->base;
1110
1111         BREAK_TO_DEBUGGER();
1112         kfree(dpp);
1113         return NULL;
1114 }
1115
1116 struct input_pixel_processor *dcn20_ipp_create(
1117         struct dc_context *ctx, uint32_t inst)
1118 {
1119         struct dcn10_ipp *ipp =
1120                 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
1121
1122         if (!ipp) {
1123                 BREAK_TO_DEBUGGER();
1124                 return NULL;
1125         }
1126
1127         dcn20_ipp_construct(ipp, ctx, inst,
1128                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
1129         return &ipp->base;
1130 }
1131
1132
1133 struct output_pixel_processor *dcn20_opp_create(
1134         struct dc_context *ctx, uint32_t inst)
1135 {
1136         struct dcn20_opp *opp =
1137                 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1138
1139         if (!opp) {
1140                 BREAK_TO_DEBUGGER();
1141                 return NULL;
1142         }
1143
1144         dcn20_opp_construct(opp, ctx, inst,
1145                         &opp_regs[inst], &opp_shift, &opp_mask);
1146         return &opp->base;
1147 }
1148
1149 struct dce_aux *dcn20_aux_engine_create(
1150         struct dc_context *ctx,
1151         uint32_t inst)
1152 {
1153         struct aux_engine_dce110 *aux_engine =
1154                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
1155
1156         if (!aux_engine)
1157                 return NULL;
1158
1159         dce110_aux_engine_construct(aux_engine, ctx, inst,
1160                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
1161                                     &aux_engine_regs[inst],
1162                                         &aux_mask,
1163                                         &aux_shift,
1164                                         ctx->dc->caps.extended_aux_timeout_support);
1165
1166         return &aux_engine->base;
1167 }
1168 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
1169
1170 static const struct dce_i2c_registers i2c_hw_regs[] = {
1171                 i2c_inst_regs(1),
1172                 i2c_inst_regs(2),
1173                 i2c_inst_regs(3),
1174                 i2c_inst_regs(4),
1175                 i2c_inst_regs(5),
1176                 i2c_inst_regs(6),
1177 };
1178
1179 static const struct dce_i2c_shift i2c_shifts = {
1180                 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
1181 };
1182
1183 static const struct dce_i2c_mask i2c_masks = {
1184                 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
1185 };
1186
1187 struct dce_i2c_hw *dcn20_i2c_hw_create(
1188         struct dc_context *ctx,
1189         uint32_t inst)
1190 {
1191         struct dce_i2c_hw *dce_i2c_hw =
1192                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
1193
1194         if (!dce_i2c_hw)
1195                 return NULL;
1196
1197         dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
1198                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
1199
1200         return dce_i2c_hw;
1201 }
1202 struct mpc *dcn20_mpc_create(struct dc_context *ctx)
1203 {
1204         struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1205                                           GFP_KERNEL);
1206
1207         if (!mpc20)
1208                 return NULL;
1209
1210         dcn20_mpc_construct(mpc20, ctx,
1211                         &mpc_regs,
1212                         &mpc_shift,
1213                         &mpc_mask,
1214                         6);
1215
1216         return &mpc20->base;
1217 }
1218
1219 struct hubbub *dcn20_hubbub_create(struct dc_context *ctx)
1220 {
1221         int i;
1222         struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1223                                           GFP_KERNEL);
1224
1225         if (!hubbub)
1226                 return NULL;
1227
1228         hubbub2_construct(hubbub, ctx,
1229                         &hubbub_reg,
1230                         &hubbub_shift,
1231                         &hubbub_mask);
1232
1233         for (i = 0; i < res_cap_nv10.num_vmid; i++) {
1234                 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1235
1236                 vmid->ctx = ctx;
1237
1238                 vmid->regs = &vmid_regs[i];
1239                 vmid->shifts = &vmid_shifts;
1240                 vmid->masks = &vmid_masks;
1241         }
1242
1243         return &hubbub->base;
1244 }
1245
1246 struct timing_generator *dcn20_timing_generator_create(
1247                 struct dc_context *ctx,
1248                 uint32_t instance)
1249 {
1250         struct optc *tgn10 =
1251                 kzalloc(sizeof(struct optc), GFP_KERNEL);
1252
1253         if (!tgn10)
1254                 return NULL;
1255
1256         tgn10->base.inst = instance;
1257         tgn10->base.ctx = ctx;
1258
1259         tgn10->tg_regs = &tg_regs[instance];
1260         tgn10->tg_shift = &tg_shift;
1261         tgn10->tg_mask = &tg_mask;
1262
1263         dcn20_timing_generator_init(tgn10);
1264
1265         return &tgn10->base;
1266 }
1267
1268 static const struct encoder_feature_support link_enc_feature = {
1269                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1270                 .max_hdmi_pixel_clock = 600000,
1271                 .hdmi_ycbcr420_supported = true,
1272                 .dp_ycbcr420_supported = true,
1273                 .fec_supported = true,
1274                 .flags.bits.IS_HBR2_CAPABLE = true,
1275                 .flags.bits.IS_HBR3_CAPABLE = true,
1276                 .flags.bits.IS_TPS3_CAPABLE = true,
1277                 .flags.bits.IS_TPS4_CAPABLE = true
1278 };
1279
1280 struct link_encoder *dcn20_link_encoder_create(
1281         const struct encoder_init_data *enc_init_data)
1282 {
1283         struct dcn20_link_encoder *enc20 =
1284                 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1285         int link_regs_id;
1286
1287         if (!enc20)
1288                 return NULL;
1289
1290         link_regs_id =
1291                 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1292
1293         dcn20_link_encoder_construct(enc20,
1294                                       enc_init_data,
1295                                       &link_enc_feature,
1296                                       &link_enc_regs[link_regs_id],
1297                                       &link_enc_aux_regs[enc_init_data->channel - 1],
1298                                       &link_enc_hpd_regs[enc_init_data->hpd_source],
1299                                       &le_shift,
1300                                       &le_mask);
1301
1302         return &enc20->enc10.base;
1303 }
1304
1305 static struct panel *dcn20_panel_create(const struct panel_init_data *init_data)
1306 {
1307         struct dce_panel *panel =
1308                 kzalloc(sizeof(struct dce_panel), GFP_KERNEL);
1309
1310         if (!panel)
1311                 return NULL;
1312
1313         dce_panel_construct(panel,
1314                         init_data,
1315                         &panel_regs[init_data->inst],
1316                         &panel_shift,
1317                         &panel_mask);
1318
1319         return &panel->base;
1320 }
1321
1322 struct clock_source *dcn20_clock_source_create(
1323         struct dc_context *ctx,
1324         struct dc_bios *bios,
1325         enum clock_source_id id,
1326         const struct dce110_clk_src_regs *regs,
1327         bool dp_clk_src)
1328 {
1329         struct dce110_clk_src *clk_src =
1330                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1331
1332         if (!clk_src)
1333                 return NULL;
1334
1335         if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1336                         regs, &cs_shift, &cs_mask)) {
1337                 clk_src->base.dp_clk_src = dp_clk_src;
1338                 return &clk_src->base;
1339         }
1340
1341         kfree(clk_src);
1342         BREAK_TO_DEBUGGER();
1343         return NULL;
1344 }
1345
1346 static void read_dce_straps(
1347         struct dc_context *ctx,
1348         struct resource_straps *straps)
1349 {
1350         generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1351                 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1352 }
1353
1354 static struct audio *dcn20_create_audio(
1355                 struct dc_context *ctx, unsigned int inst)
1356 {
1357         return dce_audio_create(ctx, inst,
1358                         &audio_regs[inst], &audio_shift, &audio_mask);
1359 }
1360
1361 struct stream_encoder *dcn20_stream_encoder_create(
1362         enum engine_id eng_id,
1363         struct dc_context *ctx)
1364 {
1365         struct dcn10_stream_encoder *enc1 =
1366                 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1367
1368         if (!enc1)
1369                 return NULL;
1370
1371         if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
1372                 if (eng_id >= ENGINE_ID_DIGD)
1373                         eng_id++;
1374         }
1375
1376         dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1377                                         &stream_enc_regs[eng_id],
1378                                         &se_shift, &se_mask);
1379
1380         return &enc1->base;
1381 }
1382
1383 static const struct dce_hwseq_registers hwseq_reg = {
1384                 HWSEQ_DCN2_REG_LIST()
1385 };
1386
1387 static const struct dce_hwseq_shift hwseq_shift = {
1388                 HWSEQ_DCN2_MASK_SH_LIST(__SHIFT)
1389 };
1390
1391 static const struct dce_hwseq_mask hwseq_mask = {
1392                 HWSEQ_DCN2_MASK_SH_LIST(_MASK)
1393 };
1394
1395 struct dce_hwseq *dcn20_hwseq_create(
1396         struct dc_context *ctx)
1397 {
1398         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1399
1400         if (hws) {
1401                 hws->ctx = ctx;
1402                 hws->regs = &hwseq_reg;
1403                 hws->shifts = &hwseq_shift;
1404                 hws->masks = &hwseq_mask;
1405         }
1406         return hws;
1407 }
1408
1409 static const struct resource_create_funcs res_create_funcs = {
1410         .read_dce_straps = read_dce_straps,
1411         .create_audio = dcn20_create_audio,
1412         .create_stream_encoder = dcn20_stream_encoder_create,
1413         .create_hwseq = dcn20_hwseq_create,
1414 };
1415
1416 static const struct resource_create_funcs res_create_maximus_funcs = {
1417         .read_dce_straps = NULL,
1418         .create_audio = NULL,
1419         .create_stream_encoder = NULL,
1420         .create_hwseq = dcn20_hwseq_create,
1421 };
1422
1423 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
1424
1425 void dcn20_clock_source_destroy(struct clock_source **clk_src)
1426 {
1427         kfree(TO_DCE110_CLK_SRC(*clk_src));
1428         *clk_src = NULL;
1429 }
1430
1431
1432 struct display_stream_compressor *dcn20_dsc_create(
1433         struct dc_context *ctx, uint32_t inst)
1434 {
1435         struct dcn20_dsc *dsc =
1436                 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1437
1438         if (!dsc) {
1439                 BREAK_TO_DEBUGGER();
1440                 return NULL;
1441         }
1442
1443         dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1444         return &dsc->base;
1445 }
1446
1447 void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
1448 {
1449         kfree(container_of(*dsc, struct dcn20_dsc, base));
1450         *dsc = NULL;
1451 }
1452
1453
1454 static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)
1455 {
1456         unsigned int i;
1457
1458         for (i = 0; i < pool->base.stream_enc_count; i++) {
1459                 if (pool->base.stream_enc[i] != NULL) {
1460                         kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1461                         pool->base.stream_enc[i] = NULL;
1462                 }
1463         }
1464
1465         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1466                 if (pool->base.dscs[i] != NULL)
1467                         dcn20_dsc_destroy(&pool->base.dscs[i]);
1468         }
1469
1470         if (pool->base.mpc != NULL) {
1471                 kfree(TO_DCN20_MPC(pool->base.mpc));
1472                 pool->base.mpc = NULL;
1473         }
1474         if (pool->base.hubbub != NULL) {
1475                 kfree(pool->base.hubbub);
1476                 pool->base.hubbub = NULL;
1477         }
1478         for (i = 0; i < pool->base.pipe_count; i++) {
1479                 if (pool->base.dpps[i] != NULL)
1480                         dcn20_dpp_destroy(&pool->base.dpps[i]);
1481
1482                 if (pool->base.ipps[i] != NULL)
1483                         pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1484
1485                 if (pool->base.hubps[i] != NULL) {
1486                         kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1487                         pool->base.hubps[i] = NULL;
1488                 }
1489
1490                 if (pool->base.irqs != NULL) {
1491                         dal_irq_service_destroy(&pool->base.irqs);
1492                 }
1493         }
1494
1495         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1496                 if (pool->base.engines[i] != NULL)
1497                         dce110_engine_destroy(&pool->base.engines[i]);
1498                 if (pool->base.hw_i2cs[i] != NULL) {
1499                         kfree(pool->base.hw_i2cs[i]);
1500                         pool->base.hw_i2cs[i] = NULL;
1501                 }
1502                 if (pool->base.sw_i2cs[i] != NULL) {
1503                         kfree(pool->base.sw_i2cs[i]);
1504                         pool->base.sw_i2cs[i] = NULL;
1505                 }
1506         }
1507
1508         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1509                 if (pool->base.opps[i] != NULL)
1510                         pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1511         }
1512
1513         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1514                 if (pool->base.timing_generators[i] != NULL)    {
1515                         kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1516                         pool->base.timing_generators[i] = NULL;
1517                 }
1518         }
1519
1520         for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1521                 if (pool->base.dwbc[i] != NULL) {
1522                         kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
1523                         pool->base.dwbc[i] = NULL;
1524                 }
1525                 if (pool->base.mcif_wb[i] != NULL) {
1526                         kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
1527                         pool->base.mcif_wb[i] = NULL;
1528                 }
1529         }
1530
1531         for (i = 0; i < pool->base.audio_count; i++) {
1532                 if (pool->base.audios[i])
1533                         dce_aud_destroy(&pool->base.audios[i]);
1534         }
1535
1536         for (i = 0; i < pool->base.clk_src_count; i++) {
1537                 if (pool->base.clock_sources[i] != NULL) {
1538                         dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1539                         pool->base.clock_sources[i] = NULL;
1540                 }
1541         }
1542
1543         if (pool->base.dp_clock_source != NULL) {
1544                 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1545                 pool->base.dp_clock_source = NULL;
1546         }
1547
1548
1549         if (pool->base.abm != NULL)
1550                 dce_abm_destroy(&pool->base.abm);
1551
1552         if (pool->base.dmcu != NULL)
1553                 dce_dmcu_destroy(&pool->base.dmcu);
1554
1555         if (pool->base.dccg != NULL)
1556                 dcn_dccg_destroy(&pool->base.dccg);
1557
1558         if (pool->base.pp_smu != NULL)
1559                 dcn20_pp_smu_destroy(&pool->base.pp_smu);
1560
1561         if (pool->base.oem_device != NULL)
1562                 dal_ddc_service_destroy(&pool->base.oem_device);
1563 }
1564
1565 struct hubp *dcn20_hubp_create(
1566         struct dc_context *ctx,
1567         uint32_t inst)
1568 {
1569         struct dcn20_hubp *hubp2 =
1570                 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1571
1572         if (!hubp2)
1573                 return NULL;
1574
1575         if (hubp2_construct(hubp2, ctx, inst,
1576                         &hubp_regs[inst], &hubp_shift, &hubp_mask))
1577                 return &hubp2->base;
1578
1579         BREAK_TO_DEBUGGER();
1580         kfree(hubp2);
1581         return NULL;
1582 }
1583
1584 static void get_pixel_clock_parameters(
1585         struct pipe_ctx *pipe_ctx,
1586         struct pixel_clk_params *pixel_clk_params)
1587 {
1588         const struct dc_stream_state *stream = pipe_ctx->stream;
1589         struct pipe_ctx *odm_pipe;
1590         int opp_cnt = 1;
1591
1592         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1593                 opp_cnt++;
1594
1595         pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1596         pixel_clk_params->encoder_object_id = stream->link->link_enc->id;
1597         pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1598         pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1599         /* TODO: un-hardcode*/
1600         pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1601                 LINK_RATE_REF_FREQ_IN_KHZ;
1602         pixel_clk_params->flags.ENABLE_SS = 0;
1603         pixel_clk_params->color_depth =
1604                 stream->timing.display_color_depth;
1605         pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1606         pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1607
1608         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1609                 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1610
1611         if (opp_cnt == 4)
1612                 pixel_clk_params->requested_pix_clk_100hz /= 4;
1613         else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2)
1614                 pixel_clk_params->requested_pix_clk_100hz /= 2;
1615
1616         if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1617                 pixel_clk_params->requested_pix_clk_100hz *= 2;
1618
1619 }
1620
1621 static void build_clamping_params(struct dc_stream_state *stream)
1622 {
1623         stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1624         stream->clamping.c_depth = stream->timing.display_color_depth;
1625         stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1626 }
1627
1628 static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1629 {
1630
1631         get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1632
1633         pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1634                 pipe_ctx->clock_source,
1635                 &pipe_ctx->stream_res.pix_clk_params,
1636                 &pipe_ctx->pll_settings);
1637
1638         pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1639
1640         resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1641                                         &pipe_ctx->stream->bit_depth_params);
1642         build_clamping_params(pipe_ctx->stream);
1643
1644         return DC_OK;
1645 }
1646
1647 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)
1648 {
1649         enum dc_status status = DC_OK;
1650         struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
1651
1652         /*TODO Seems unneeded anymore */
1653         /*      if (old_context && resource_is_stream_unchanged(old_context, stream)) {
1654                         if (stream != NULL && old_context->streams[i] != NULL) {
1655                                  todo: shouldn't have to copy missing parameter here
1656                                 resource_build_bit_depth_reduction_params(stream,
1657                                                 &stream->bit_depth_params);
1658                                 stream->clamping.pixel_encoding =
1659                                                 stream->timing.pixel_encoding;
1660
1661                                 resource_build_bit_depth_reduction_params(stream,
1662                                                                 &stream->bit_depth_params);
1663                                 build_clamping_params(stream);
1664
1665                                 continue;
1666                         }
1667                 }
1668         */
1669
1670         if (!pipe_ctx)
1671                 return DC_ERROR_UNEXPECTED;
1672
1673
1674         status = build_pipe_hw_param(pipe_ctx);
1675
1676         return status;
1677 }
1678
1679
1680 static void acquire_dsc(struct resource_context *res_ctx,
1681                         const struct resource_pool *pool,
1682                         struct display_stream_compressor **dsc,
1683                         int pipe_idx)
1684 {
1685         int i;
1686
1687         ASSERT(*dsc == NULL);
1688         *dsc = NULL;
1689
1690         if (pool->res_cap->num_dsc == pool->res_cap->num_opp) {
1691                 *dsc = pool->dscs[pipe_idx];
1692                 res_ctx->is_dsc_acquired[pipe_idx] = true;
1693                 return;
1694         }
1695
1696         /* Find first free DSC */
1697         for (i = 0; i < pool->res_cap->num_dsc; i++)
1698                 if (!res_ctx->is_dsc_acquired[i]) {
1699                         *dsc = pool->dscs[i];
1700                         res_ctx->is_dsc_acquired[i] = true;
1701                         break;
1702                 }
1703 }
1704
1705 void dcn20_release_dsc(struct resource_context *res_ctx,
1706                         const struct resource_pool *pool,
1707                         struct display_stream_compressor **dsc)
1708 {
1709         int i;
1710
1711         for (i = 0; i < pool->res_cap->num_dsc; i++)
1712                 if (pool->dscs[i] == *dsc) {
1713                         res_ctx->is_dsc_acquired[i] = false;
1714                         *dsc = NULL;
1715                         break;
1716                 }
1717 }
1718
1719
1720
1721 enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc,
1722                 struct dc_state *dc_ctx,
1723                 struct dc_stream_state *dc_stream)
1724 {
1725         enum dc_status result = DC_OK;
1726         int i;
1727         const struct resource_pool *pool = dc->res_pool;
1728
1729         /* Get a DSC if required and available */
1730         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1731                 struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];
1732
1733                 if (pipe_ctx->stream != dc_stream)
1734                         continue;
1735
1736                 if (pipe_ctx->stream_res.dsc)
1737                         continue;
1738
1739                 acquire_dsc(&dc_ctx->res_ctx, pool, &pipe_ctx->stream_res.dsc, i);
1740
1741                 /* The number of DSCs can be less than the number of pipes */
1742                 if (!pipe_ctx->stream_res.dsc) {
1743                         result = DC_NO_DSC_RESOURCE;
1744                 }
1745
1746                 break;
1747         }
1748
1749         return result;
1750 }
1751
1752
1753 static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
1754                 struct dc_state *new_ctx,
1755                 struct dc_stream_state *dc_stream)
1756 {
1757         struct pipe_ctx *pipe_ctx = NULL;
1758         int i;
1759
1760         for (i = 0; i < MAX_PIPES; i++) {
1761                 if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1762                         pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1763
1764                         if (pipe_ctx->stream_res.dsc)
1765                                 dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
1766                 }
1767         }
1768
1769         if (!pipe_ctx)
1770                 return DC_ERROR_UNEXPECTED;
1771         else
1772                 return DC_OK;
1773 }
1774
1775
1776 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1777 {
1778         enum dc_status result = DC_ERROR_UNEXPECTED;
1779
1780         result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1781
1782         if (result == DC_OK)
1783                 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1784
1785         /* Get a DSC if required and available */
1786         if (result == DC_OK && dc_stream->timing.flags.DSC)
1787                 result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
1788
1789         if (result == DC_OK)
1790                 result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
1791
1792         return result;
1793 }
1794
1795
1796 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1797 {
1798         enum dc_status result = DC_OK;
1799
1800         result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);
1801
1802         return result;
1803 }
1804
1805
1806 static void swizzle_to_dml_params(
1807                 enum swizzle_mode_values swizzle,
1808                 unsigned int *sw_mode)
1809 {
1810         switch (swizzle) {
1811         case DC_SW_LINEAR:
1812                 *sw_mode = dm_sw_linear;
1813                 break;
1814         case DC_SW_4KB_S:
1815                 *sw_mode = dm_sw_4kb_s;
1816                 break;
1817         case DC_SW_4KB_S_X:
1818                 *sw_mode = dm_sw_4kb_s_x;
1819                 break;
1820         case DC_SW_4KB_D:
1821                 *sw_mode = dm_sw_4kb_d;
1822                 break;
1823         case DC_SW_4KB_D_X:
1824                 *sw_mode = dm_sw_4kb_d_x;
1825                 break;
1826         case DC_SW_64KB_S:
1827                 *sw_mode = dm_sw_64kb_s;
1828                 break;
1829         case DC_SW_64KB_S_X:
1830                 *sw_mode = dm_sw_64kb_s_x;
1831                 break;
1832         case DC_SW_64KB_S_T:
1833                 *sw_mode = dm_sw_64kb_s_t;
1834                 break;
1835         case DC_SW_64KB_D:
1836                 *sw_mode = dm_sw_64kb_d;
1837                 break;
1838         case DC_SW_64KB_D_X:
1839                 *sw_mode = dm_sw_64kb_d_x;
1840                 break;
1841         case DC_SW_64KB_D_T:
1842                 *sw_mode = dm_sw_64kb_d_t;
1843                 break;
1844         case DC_SW_64KB_R_X:
1845                 *sw_mode = dm_sw_64kb_r_x;
1846                 break;
1847         case DC_SW_VAR_S:
1848                 *sw_mode = dm_sw_var_s;
1849                 break;
1850         case DC_SW_VAR_S_X:
1851                 *sw_mode = dm_sw_var_s_x;
1852                 break;
1853         case DC_SW_VAR_D:
1854                 *sw_mode = dm_sw_var_d;
1855                 break;
1856         case DC_SW_VAR_D_X:
1857                 *sw_mode = dm_sw_var_d_x;
1858                 break;
1859
1860         default:
1861                 ASSERT(0); /* Not supported */
1862                 break;
1863         }
1864 }
1865
1866 bool dcn20_split_stream_for_odm(
1867                 struct resource_context *res_ctx,
1868                 const struct resource_pool *pool,
1869                 struct pipe_ctx *prev_odm_pipe,
1870                 struct pipe_ctx *next_odm_pipe)
1871 {
1872         int pipe_idx = next_odm_pipe->pipe_idx;
1873
1874         *next_odm_pipe = *prev_odm_pipe;
1875
1876         next_odm_pipe->pipe_idx = pipe_idx;
1877         next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
1878         next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
1879         next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
1880         next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
1881         next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
1882         next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
1883         next_odm_pipe->stream_res.dsc = NULL;
1884         if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
1885                 next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
1886                 next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
1887         }
1888         prev_odm_pipe->next_odm_pipe = next_odm_pipe;
1889         next_odm_pipe->prev_odm_pipe = prev_odm_pipe;
1890         ASSERT(next_odm_pipe->top_pipe == NULL);
1891
1892         if (prev_odm_pipe->plane_state) {
1893                 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
1894                 int new_width;
1895
1896                 /* HACTIVE halved for odm combine */
1897                 sd->h_active /= 2;
1898                 /* Calculate new vp and recout for left pipe */
1899                 /* Need at least 16 pixels width per side */
1900                 if (sd->recout.x + 16 >= sd->h_active)
1901                         return false;
1902                 new_width = sd->h_active - sd->recout.x;
1903                 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1904                                 sd->ratios.horz, sd->recout.width - new_width));
1905                 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1906                                 sd->ratios.horz_c, sd->recout.width - new_width));
1907                 sd->recout.width = new_width;
1908
1909                 /* Calculate new vp and recout for right pipe */
1910                 sd = &next_odm_pipe->plane_res.scl_data;
1911                 /* HACTIVE halved for odm combine */
1912                 sd->h_active /= 2;
1913                 /* Need at least 16 pixels width per side */
1914                 if (new_width <= 16)
1915                         return false;
1916                 new_width = sd->recout.width + sd->recout.x - sd->h_active;
1917                 sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1918                                 sd->ratios.horz, sd->recout.width - new_width));
1919                 sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1920                                 sd->ratios.horz_c, sd->recout.width - new_width));
1921                 sd->recout.width = new_width;
1922                 sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
1923                                 sd->ratios.horz, sd->h_active - sd->recout.x));
1924                 sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
1925                                 sd->ratios.horz_c, sd->h_active - sd->recout.x));
1926                 sd->recout.x = 0;
1927         }
1928         next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
1929         if (next_odm_pipe->stream->timing.flags.DSC == 1) {
1930                 acquire_dsc(res_ctx, pool, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);
1931                 ASSERT(next_odm_pipe->stream_res.dsc);
1932                 if (next_odm_pipe->stream_res.dsc == NULL)
1933                         return false;
1934         }
1935
1936         return true;
1937 }
1938
1939 void dcn20_split_stream_for_mpc(
1940                 struct resource_context *res_ctx,
1941                 const struct resource_pool *pool,
1942                 struct pipe_ctx *primary_pipe,
1943                 struct pipe_ctx *secondary_pipe)
1944 {
1945         int pipe_idx = secondary_pipe->pipe_idx;
1946         struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
1947
1948         *secondary_pipe = *primary_pipe;
1949         secondary_pipe->bottom_pipe = sec_bot_pipe;
1950
1951         secondary_pipe->pipe_idx = pipe_idx;
1952         secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
1953         secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
1954         secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
1955         secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
1956         secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
1957         secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
1958         secondary_pipe->stream_res.dsc = NULL;
1959         if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
1960                 ASSERT(!secondary_pipe->bottom_pipe);
1961                 secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
1962                 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
1963         }
1964         primary_pipe->bottom_pipe = secondary_pipe;
1965         secondary_pipe->top_pipe = primary_pipe;
1966
1967         ASSERT(primary_pipe->plane_state);
1968         resource_build_scaling_params(primary_pipe);
1969         resource_build_scaling_params(secondary_pipe);
1970 }
1971
1972 void dcn20_populate_dml_writeback_from_context(
1973                 struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
1974 {
1975         int pipe_cnt, i;
1976
1977         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1978                 struct dc_writeback_info *wb_info = &res_ctx->pipe_ctx[i].stream->writeback_info[0];
1979
1980                 if (!res_ctx->pipe_ctx[i].stream)
1981                         continue;
1982
1983                 /* Set writeback information */
1984                 pipes[pipe_cnt].dout.wb_enable = (wb_info->wb_enabled == true) ? 1 : 0;
1985                 pipes[pipe_cnt].dout.num_active_wb++;
1986                 pipes[pipe_cnt].dout.wb.wb_src_height = wb_info->dwb_params.cnv_params.crop_height;
1987                 pipes[pipe_cnt].dout.wb.wb_src_width = wb_info->dwb_params.cnv_params.crop_width;
1988                 pipes[pipe_cnt].dout.wb.wb_dst_width = wb_info->dwb_params.dest_width;
1989                 pipes[pipe_cnt].dout.wb.wb_dst_height = wb_info->dwb_params.dest_height;
1990                 pipes[pipe_cnt].dout.wb.wb_htaps_luma = 1;
1991                 pipes[pipe_cnt].dout.wb.wb_vtaps_luma = 1;
1992                 pipes[pipe_cnt].dout.wb.wb_htaps_chroma = wb_info->dwb_params.scaler_taps.h_taps_c;
1993                 pipes[pipe_cnt].dout.wb.wb_vtaps_chroma = wb_info->dwb_params.scaler_taps.v_taps_c;
1994                 pipes[pipe_cnt].dout.wb.wb_hratio = 1.0;
1995                 pipes[pipe_cnt].dout.wb.wb_vratio = 1.0;
1996                 if (wb_info->dwb_params.out_format == dwb_scaler_mode_yuv420) {
1997                         if (wb_info->dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
1998                                 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_8;
1999                         else
2000                                 pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_420_10;
2001                 } else
2002                         pipes[pipe_cnt].dout.wb.wb_pixel_format = dm_444_32;
2003
2004                 pipe_cnt++;
2005         }
2006
2007 }
2008
2009 int dcn20_populate_dml_pipes_from_context(
2010                 struct dc *dc, struct dc_state *context, display_e2e_pipe_params_st *pipes)
2011 {
2012         int pipe_cnt, i;
2013         bool synchronized_vblank = true;
2014         struct resource_context *res_ctx = &context->res_ctx;
2015
2016         for (i = 0, pipe_cnt = -1; i < dc->res_pool->pipe_count; i++) {
2017                 if (!res_ctx->pipe_ctx[i].stream)
2018                         continue;
2019
2020                 if (pipe_cnt < 0) {
2021                         pipe_cnt = i;
2022                         continue;
2023                 }
2024                 if (dc->debug.disable_timing_sync || !resource_are_streams_timing_synchronizable(
2025                                 res_ctx->pipe_ctx[pipe_cnt].stream,
2026                                 res_ctx->pipe_ctx[i].stream)) {
2027                         synchronized_vblank = false;
2028                         break;
2029                 }
2030         }
2031
2032         for (i = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2033                 struct dc_crtc_timing *timing = &res_ctx->pipe_ctx[i].stream->timing;
2034                 unsigned int v_total;
2035                 unsigned int front_porch;
2036                 int output_bpc;
2037
2038                 if (!res_ctx->pipe_ctx[i].stream)
2039                         continue;
2040
2041                 v_total = timing->v_total;
2042                 front_porch = timing->v_front_porch;
2043                 /* todo:
2044                 pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = 0;
2045                 pipes[pipe_cnt].pipe.src.dcc = 0;
2046                 pipes[pipe_cnt].pipe.src.vm = 0;*/
2047
2048                 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2049
2050                 pipes[pipe_cnt].dout.dsc_enable = res_ctx->pipe_ctx[i].stream->timing.flags.DSC;
2051                 /* todo: rotation?*/
2052                 pipes[pipe_cnt].dout.dsc_slices = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.num_slices_h;
2053                 if (res_ctx->pipe_ctx[i].stream->use_dynamic_meta) {
2054                         pipes[pipe_cnt].pipe.src.dynamic_metadata_enable = true;
2055                         /* 1/2 vblank */
2056                         pipes[pipe_cnt].pipe.src.dynamic_metadata_lines_before_active =
2057                                 (v_total - timing->v_addressable
2058                                         - timing->v_border_top - timing->v_border_bottom) / 2;
2059                         /* 36 bytes dp, 32 hdmi */
2060                         pipes[pipe_cnt].pipe.src.dynamic_metadata_xmit_bytes =
2061                                 dc_is_dp_signal(res_ctx->pipe_ctx[i].stream->signal) ? 36 : 32;
2062                 }
2063                 pipes[pipe_cnt].pipe.src.dcc = false;
2064                 pipes[pipe_cnt].pipe.src.dcc_rate = 1;
2065                 pipes[pipe_cnt].pipe.dest.synchronized_vblank_all_planes = synchronized_vblank;
2066                 pipes[pipe_cnt].pipe.dest.hblank_start = timing->h_total - timing->h_front_porch;
2067                 pipes[pipe_cnt].pipe.dest.hblank_end = pipes[pipe_cnt].pipe.dest.hblank_start
2068                                 - timing->h_addressable
2069                                 - timing->h_border_left
2070                                 - timing->h_border_right;
2071                 pipes[pipe_cnt].pipe.dest.vblank_start = v_total - front_porch;
2072                 pipes[pipe_cnt].pipe.dest.vblank_end = pipes[pipe_cnt].pipe.dest.vblank_start
2073                                 - timing->v_addressable
2074                                 - timing->v_border_top
2075                                 - timing->v_border_bottom;
2076                 pipes[pipe_cnt].pipe.dest.htotal = timing->h_total;
2077                 pipes[pipe_cnt].pipe.dest.vtotal = v_total;
2078                 pipes[pipe_cnt].pipe.dest.hactive = timing->h_addressable;
2079                 pipes[pipe_cnt].pipe.dest.vactive = timing->v_addressable;
2080                 pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
2081                 pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
2082                 if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2083                         pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
2084                 pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
2085                 pipes[pipe_cnt].dout.dp_lanes = 4;
2086                 pipes[pipe_cnt].pipe.dest.vtotal_min = res_ctx->pipe_ctx[i].stream->adjust.v_total_min;
2087                 pipes[pipe_cnt].pipe.dest.vtotal_max = res_ctx->pipe_ctx[i].stream->adjust.v_total_max;
2088                 switch (get_num_odm_splits(&res_ctx->pipe_ctx[i])) {
2089                 case 1:
2090                         pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_2to1;
2091                         break;
2092                 default:
2093                         pipes[pipe_cnt].pipe.dest.odm_combine = dm_odm_combine_mode_disabled;
2094                 }
2095                 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].pipe_idx;
2096                 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state
2097                                 == res_ctx->pipe_ctx[i].plane_state) {
2098                         struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe;
2099
2100                         while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state
2101                                         == res_ctx->pipe_ctx[i].plane_state)
2102                                 first_pipe = first_pipe->top_pipe;
2103                         pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
2104                 } else if (res_ctx->pipe_ctx[i].prev_odm_pipe) {
2105                         struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].prev_odm_pipe;
2106
2107                         while (first_pipe->prev_odm_pipe)
2108                                 first_pipe = first_pipe->prev_odm_pipe;
2109                         pipes[pipe_cnt].pipe.src.hsplit_grp = first_pipe->pipe_idx;
2110                 }
2111
2112                 switch (res_ctx->pipe_ctx[i].stream->signal) {
2113                 case SIGNAL_TYPE_DISPLAY_PORT_MST:
2114                 case SIGNAL_TYPE_DISPLAY_PORT:
2115                         pipes[pipe_cnt].dout.output_type = dm_dp;
2116                         break;
2117                 case SIGNAL_TYPE_EDP:
2118                         pipes[pipe_cnt].dout.output_type = dm_edp;
2119                         break;
2120                 case SIGNAL_TYPE_HDMI_TYPE_A:
2121                 case SIGNAL_TYPE_DVI_SINGLE_LINK:
2122                 case SIGNAL_TYPE_DVI_DUAL_LINK:
2123                         pipes[pipe_cnt].dout.output_type = dm_hdmi;
2124                         break;
2125                 default:
2126                         /* In case there is no signal, set dp with 4 lanes to allow max config */
2127                         pipes[pipe_cnt].dout.output_type = dm_dp;
2128                         pipes[pipe_cnt].dout.dp_lanes = 4;
2129                 }
2130
2131                 switch (res_ctx->pipe_ctx[i].stream->timing.display_color_depth) {
2132                 case COLOR_DEPTH_666:
2133                         output_bpc = 6;
2134                         break;
2135                 case COLOR_DEPTH_888:
2136                         output_bpc = 8;
2137                         break;
2138                 case COLOR_DEPTH_101010:
2139                         output_bpc = 10;
2140                         break;
2141                 case COLOR_DEPTH_121212:
2142                         output_bpc = 12;
2143                         break;
2144                 case COLOR_DEPTH_141414:
2145                         output_bpc = 14;
2146                         break;
2147                 case COLOR_DEPTH_161616:
2148                         output_bpc = 16;
2149                         break;
2150                 case COLOR_DEPTH_999:
2151                         output_bpc = 9;
2152                         break;
2153                 case COLOR_DEPTH_111111:
2154                         output_bpc = 11;
2155                         break;
2156                 default:
2157                         output_bpc = 8;
2158                         break;
2159                 }
2160
2161                 switch (res_ctx->pipe_ctx[i].stream->timing.pixel_encoding) {
2162                 case PIXEL_ENCODING_RGB:
2163                 case PIXEL_ENCODING_YCBCR444:
2164                         pipes[pipe_cnt].dout.output_format = dm_444;
2165                         pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
2166                         break;
2167                 case PIXEL_ENCODING_YCBCR420:
2168                         pipes[pipe_cnt].dout.output_format = dm_420;
2169                         pipes[pipe_cnt].dout.output_bpp = (output_bpc * 3.0) / 2;
2170                         break;
2171                 case PIXEL_ENCODING_YCBCR422:
2172                         if (true) /* todo */
2173                                 pipes[pipe_cnt].dout.output_format = dm_s422;
2174                         else
2175                                 pipes[pipe_cnt].dout.output_format = dm_n422;
2176                         pipes[pipe_cnt].dout.output_bpp = output_bpc * 2;
2177                         break;
2178                 default:
2179                         pipes[pipe_cnt].dout.output_format = dm_444;
2180                         pipes[pipe_cnt].dout.output_bpp = output_bpc * 3;
2181                 }
2182
2183                 if (res_ctx->pipe_ctx[i].stream->timing.flags.DSC)
2184                         pipes[pipe_cnt].dout.output_bpp = res_ctx->pipe_ctx[i].stream->timing.dsc_cfg.bits_per_pixel / 16.0;
2185
2186                 /* todo: default max for now, until there is logic reflecting this in dc*/
2187                 pipes[pipe_cnt].dout.output_bpc = 12;
2188                 /*
2189                  * For graphic plane, cursor number is 1, nv12 is 0
2190                  * bw calculations due to cursor on/off
2191                  */
2192                 if (res_ctx->pipe_ctx[i].plane_state &&
2193                                 res_ctx->pipe_ctx[i].plane_state->address.type == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2194                         pipes[pipe_cnt].pipe.src.num_cursors = 0;
2195                 else
2196                         pipes[pipe_cnt].pipe.src.num_cursors = dc->dml.ip.number_of_cursors;
2197
2198                 pipes[pipe_cnt].pipe.src.cur0_src_width = 256;
2199                 pipes[pipe_cnt].pipe.src.cur0_bpp = dm_cur_32bit;
2200
2201                 if (!res_ctx->pipe_ctx[i].plane_state) {
2202                         pipes[pipe_cnt].pipe.src.is_hsplit = pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
2203                         pipes[pipe_cnt].pipe.src.source_scan = dm_horz;
2204                         pipes[pipe_cnt].pipe.src.sw_mode = dm_sw_linear;
2205                         pipes[pipe_cnt].pipe.src.macro_tile_size = dm_64k_tile;
2206                         pipes[pipe_cnt].pipe.src.viewport_width = timing->h_addressable;
2207                         if (pipes[pipe_cnt].pipe.src.viewport_width > 1920)
2208                                 pipes[pipe_cnt].pipe.src.viewport_width = 1920;
2209                         pipes[pipe_cnt].pipe.src.viewport_height = timing->v_addressable;
2210                         if (pipes[pipe_cnt].pipe.src.viewport_height > 1080)
2211                                 pipes[pipe_cnt].pipe.src.viewport_height = 1080;
2212                         pipes[pipe_cnt].pipe.src.surface_height_y = pipes[pipe_cnt].pipe.src.viewport_height;
2213                         pipes[pipe_cnt].pipe.src.surface_width_y = pipes[pipe_cnt].pipe.src.viewport_width;
2214                         pipes[pipe_cnt].pipe.src.surface_height_c = pipes[pipe_cnt].pipe.src.viewport_height;
2215                         pipes[pipe_cnt].pipe.src.surface_width_c = pipes[pipe_cnt].pipe.src.viewport_width;
2216                         pipes[pipe_cnt].pipe.src.data_pitch = ((pipes[pipe_cnt].pipe.src.viewport_width + 63) / 64) * 64; /* linear sw only */
2217                         pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2218                         pipes[pipe_cnt].pipe.dest.recout_width = pipes[pipe_cnt].pipe.src.viewport_width; /*vp_width/hratio*/
2219                         pipes[pipe_cnt].pipe.dest.recout_height = pipes[pipe_cnt].pipe.src.viewport_height; /*vp_height/vratio*/
2220                         pipes[pipe_cnt].pipe.dest.full_recout_width = pipes[pipe_cnt].pipe.dest.recout_width;  /*when is_hsplit != 1*/
2221                         pipes[pipe_cnt].pipe.dest.full_recout_height = pipes[pipe_cnt].pipe.dest.recout_height; /*when is_hsplit != 1*/
2222                         pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
2223                         pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = 1.0;
2224                         pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = 1.0;
2225                         pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable = 0; /*Lb only or Full scl*/
2226                         pipes[pipe_cnt].pipe.scale_taps.htaps = 1;
2227                         pipes[pipe_cnt].pipe.scale_taps.vtaps = 1;
2228                         pipes[pipe_cnt].pipe.dest.vtotal_min = v_total;
2229                         pipes[pipe_cnt].pipe.dest.vtotal_max = v_total;
2230
2231                         if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1) {
2232                                 pipes[pipe_cnt].pipe.src.viewport_width /= 2;
2233                                 pipes[pipe_cnt].pipe.dest.recout_width /= 2;
2234                         }
2235                 } else {
2236                         struct dc_plane_state *pln = res_ctx->pipe_ctx[i].plane_state;
2237                         struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data;
2238
2239                         pipes[pipe_cnt].pipe.src.immediate_flip = pln->flip_immediate;
2240                         pipes[pipe_cnt].pipe.src.is_hsplit = (res_ctx->pipe_ctx[i].bottom_pipe && res_ctx->pipe_ctx[i].bottom_pipe->plane_state == pln)
2241                                         || (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln)
2242                                         || pipes[pipe_cnt].pipe.dest.odm_combine != dm_odm_combine_mode_disabled;
2243                         pipes[pipe_cnt].pipe.src.source_scan = pln->rotation == ROTATION_ANGLE_90
2244                                         || pln->rotation == ROTATION_ANGLE_270 ? dm_vert : dm_horz;
2245                         pipes[pipe_cnt].pipe.src.viewport_y_y = scl->viewport_unadjusted.y;
2246                         pipes[pipe_cnt].pipe.src.viewport_y_c = scl->viewport_c_unadjusted.y;
2247                         pipes[pipe_cnt].pipe.src.viewport_width = scl->viewport_unadjusted.width;
2248                         pipes[pipe_cnt].pipe.src.viewport_width_c = scl->viewport_c_unadjusted.width;
2249                         pipes[pipe_cnt].pipe.src.viewport_height = scl->viewport_unadjusted.height;
2250                         pipes[pipe_cnt].pipe.src.viewport_height_c = scl->viewport_c_unadjusted.height;
2251                         pipes[pipe_cnt].pipe.src.surface_width_y = pln->plane_size.surface_size.width;
2252                         pipes[pipe_cnt].pipe.src.surface_height_y = pln->plane_size.surface_size.height;
2253                         pipes[pipe_cnt].pipe.src.surface_width_c = pln->plane_size.chroma_size.width;
2254                         pipes[pipe_cnt].pipe.src.surface_height_c = pln->plane_size.chroma_size.height;
2255                         if (pln->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2256                                 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2257                                 pipes[pipe_cnt].pipe.src.data_pitch_c = pln->plane_size.chroma_pitch;
2258                                 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
2259                                 pipes[pipe_cnt].pipe.src.meta_pitch_c = pln->dcc.meta_pitch_c;
2260                         } else {
2261                                 pipes[pipe_cnt].pipe.src.data_pitch = pln->plane_size.surface_pitch;
2262                                 pipes[pipe_cnt].pipe.src.meta_pitch = pln->dcc.meta_pitch;
2263                         }
2264                         pipes[pipe_cnt].pipe.src.dcc = pln->dcc.enable;
2265                         pipes[pipe_cnt].pipe.dest.recout_width = scl->recout.width;
2266                         pipes[pipe_cnt].pipe.dest.recout_height = scl->recout.height;
2267                         pipes[pipe_cnt].pipe.dest.full_recout_height = scl->recout.height;
2268                         pipes[pipe_cnt].pipe.dest.full_recout_width = scl->recout.width;
2269                         if (pipes[pipe_cnt].pipe.dest.odm_combine == dm_odm_combine_mode_2to1)
2270                                 pipes[pipe_cnt].pipe.dest.full_recout_width *= 2;
2271                         else {
2272                                 struct pipe_ctx *split_pipe = res_ctx->pipe_ctx[i].bottom_pipe;
2273
2274                                 while (split_pipe && split_pipe->plane_state == pln) {
2275                                         pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
2276                                         split_pipe = split_pipe->bottom_pipe;
2277                                 }
2278                                 split_pipe = res_ctx->pipe_ctx[i].top_pipe;
2279                                 while (split_pipe && split_pipe->plane_state == pln) {
2280                                         pipes[pipe_cnt].pipe.dest.full_recout_width += split_pipe->plane_res.scl_data.recout.width;
2281                                         split_pipe = split_pipe->top_pipe;
2282                                 }
2283                         }
2284
2285                         pipes[pipe_cnt].pipe.scale_ratio_depth.lb_depth = dm_lb_16;
2286                         pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio = (double) scl->ratios.horz.value / (1ULL<<32);
2287                         pipes[pipe_cnt].pipe.scale_ratio_depth.hscl_ratio_c = (double) scl->ratios.horz_c.value / (1ULL<<32);
2288                         pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio = (double) scl->ratios.vert.value / (1ULL<<32);
2289                         pipes[pipe_cnt].pipe.scale_ratio_depth.vscl_ratio_c = (double) scl->ratios.vert_c.value / (1ULL<<32);
2290                         pipes[pipe_cnt].pipe.scale_ratio_depth.scl_enable =
2291                                         scl->ratios.vert.value != dc_fixpt_one.value
2292                                         || scl->ratios.horz.value != dc_fixpt_one.value
2293                                         || scl->ratios.vert_c.value != dc_fixpt_one.value
2294                                         || scl->ratios.horz_c.value != dc_fixpt_one.value /*Lb only or Full scl*/
2295                                         || dc->debug.always_scale; /*support always scale*/
2296                         pipes[pipe_cnt].pipe.scale_taps.htaps = scl->taps.h_taps;
2297                         pipes[pipe_cnt].pipe.scale_taps.htaps_c = scl->taps.h_taps_c;
2298                         pipes[pipe_cnt].pipe.scale_taps.vtaps = scl->taps.v_taps;
2299                         pipes[pipe_cnt].pipe.scale_taps.vtaps_c = scl->taps.v_taps_c;
2300
2301                         pipes[pipe_cnt].pipe.src.macro_tile_size =
2302                                         swizzle_mode_to_macro_tile_size(pln->tiling_info.gfx9.swizzle);
2303                         swizzle_to_dml_params(pln->tiling_info.gfx9.swizzle,
2304                                         &pipes[pipe_cnt].pipe.src.sw_mode);
2305
2306                         switch (pln->format) {
2307                         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
2308                         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
2309                                 pipes[pipe_cnt].pipe.src.source_format = dm_420_8;
2310                                 break;
2311                         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
2312                         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
2313                                 pipes[pipe_cnt].pipe.src.source_format = dm_420_10;
2314                                 break;
2315                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
2316                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
2317                         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
2318                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_64;
2319                                 break;
2320                         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
2321                         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
2322                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_16;
2323                                 break;
2324                         case SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS:
2325                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_8;
2326                                 break;
2327                         default:
2328                                 pipes[pipe_cnt].pipe.src.source_format = dm_444_32;
2329                                 break;
2330                         }
2331                 }
2332
2333                 pipe_cnt++;
2334         }
2335
2336         /* populate writeback information */
2337         dc->res_pool->funcs->populate_dml_writeback_from_context(dc, res_ctx, pipes);
2338
2339         return pipe_cnt;
2340 }
2341
2342 unsigned int dcn20_calc_max_scaled_time(
2343                 unsigned int time_per_pixel,
2344                 enum mmhubbub_wbif_mode mode,
2345                 unsigned int urgent_watermark)
2346 {
2347         unsigned int time_per_byte = 0;
2348         unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */
2349         unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */
2350         unsigned int small_free_entry, max_free_entry;
2351         unsigned int buf_lh_capability;
2352         unsigned int max_scaled_time;
2353
2354         if (mode == PACKED_444) /* packed mode */
2355                 time_per_byte = time_per_pixel/4;
2356         else if (mode == PLANAR_420_8BPC)
2357                 time_per_byte  = time_per_pixel;
2358         else if (mode == PLANAR_420_10BPC) /* p010 */
2359                 time_per_byte  = time_per_pixel * 819/1024;
2360
2361         if (time_per_byte == 0)
2362                 time_per_byte = 1;
2363
2364         small_free_entry  = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry;
2365         max_free_entry    = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;
2366         buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */
2367         max_scaled_time   = buf_lh_capability - urgent_watermark;
2368         return max_scaled_time;
2369 }
2370
2371 void dcn20_set_mcif_arb_params(
2372                 struct dc *dc,
2373                 struct dc_state *context,
2374                 display_e2e_pipe_params_st *pipes,
2375                 int pipe_cnt)
2376 {
2377         enum mmhubbub_wbif_mode wbif_mode;
2378         struct mcif_arb_params *wb_arb_params;
2379         int i, j, k, dwb_pipe;
2380
2381         /* Writeback MCIF_WB arbitration parameters */
2382         dwb_pipe = 0;
2383         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2384
2385                 if (!context->res_ctx.pipe_ctx[i].stream)
2386                         continue;
2387
2388                 for (j = 0; j < MAX_DWB_PIPES; j++) {
2389                         if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)
2390                                 continue;
2391
2392                         //wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
2393                         wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
2394
2395                         if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {
2396                                 if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
2397                                         wbif_mode = PLANAR_420_8BPC;
2398                                 else
2399                                         wbif_mode = PLANAR_420_10BPC;
2400                         } else
2401                                 wbif_mode = PACKED_444;
2402
2403                         for (k = 0; k < sizeof(wb_arb_params->cli_watermark)/sizeof(wb_arb_params->cli_watermark[0]); k++) {
2404                                 wb_arb_params->cli_watermark[k] = get_wm_writeback_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2405                                 wb_arb_params->pstate_watermark[k] = get_wm_writeback_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2406                         }
2407                         wb_arb_params->time_per_pixel = 16.0 / context->res_ctx.pipe_ctx[i].stream->phy_pix_clk; /* 4 bit fraction, ms */
2408                         wb_arb_params->slice_lines = 32;
2409                         wb_arb_params->arbitration_slice = 2;
2410                         wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,
2411                                 wbif_mode,
2412                                 wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
2413
2414                         dwb_pipe++;
2415
2416                         if (dwb_pipe >= MAX_DWB_PIPES)
2417                                 return;
2418                 }
2419                 if (dwb_pipe >= MAX_DWB_PIPES)
2420                         return;
2421         }
2422 }
2423
2424 bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
2425 {
2426         int i;
2427
2428         /* Validate DSC config, dsc count validation is already done */
2429         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2430                 struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
2431                 struct dc_stream_state *stream = pipe_ctx->stream;
2432                 struct dsc_config dsc_cfg;
2433                 struct pipe_ctx *odm_pipe;
2434                 int opp_cnt = 1;
2435
2436                 for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
2437                         opp_cnt++;
2438
2439                 /* Only need to validate top pipe */
2440                 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
2441                         continue;
2442
2443                 dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
2444                                 + stream->timing.h_border_right) / opp_cnt;
2445                 dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
2446                                 + stream->timing.v_border_bottom;
2447                 dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
2448                 dsc_cfg.color_depth = stream->timing.display_color_depth;
2449                 dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
2450                 dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
2451                 dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
2452
2453                 if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
2454                         return false;
2455         }
2456         return true;
2457 }
2458
2459 struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
2460                 struct resource_context *res_ctx,
2461                 const struct resource_pool *pool,
2462                 const struct pipe_ctx *primary_pipe)
2463 {
2464         struct pipe_ctx *secondary_pipe = NULL;
2465
2466         if (dc && primary_pipe) {
2467                 int j;
2468                 int preferred_pipe_idx = 0;
2469
2470                 /* first check the prev dc state:
2471                  * if this primary pipe has a bottom pipe in prev. state
2472                  * and if the bottom pipe is still available (which it should be),
2473                  * pick that pipe as secondary
2474                  * Same logic applies for ODM pipes. Since mpo is not allowed with odm
2475                  * check in else case.
2476                  */
2477                 if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {
2478                         preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;
2479                         if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2480                                 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2481                                 secondary_pipe->pipe_idx = preferred_pipe_idx;
2482                         }
2483                 } else if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {
2484                         preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;
2485                         if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2486                                 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2487                                 secondary_pipe->pipe_idx = preferred_pipe_idx;
2488                         }
2489                 }
2490
2491                 /*
2492                  * if this primary pipe does not have a bottom pipe in prev. state
2493                  * start backward and find a pipe that did not used to be a bottom pipe in
2494                  * prev. dc state. This way we make sure we keep the same assignment as
2495                  * last state and will not have to reprogram every pipe
2496                  */
2497                 if (secondary_pipe == NULL) {
2498                         for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2499                                 if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL
2500                                                 && dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) {
2501                                         preferred_pipe_idx = j;
2502
2503                                         if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2504                                                 secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2505                                                 secondary_pipe->pipe_idx = preferred_pipe_idx;
2506                                                 break;
2507                                         }
2508                                 }
2509                         }
2510                 }
2511                 /*
2512                  * We should never hit this assert unless assignments are shuffled around
2513                  * if this happens we will prob. hit a vsync tdr
2514                  */
2515                 ASSERT(secondary_pipe);
2516                 /*
2517                  * search backwards for the second pipe to keep pipe
2518                  * assignment more consistent
2519                  */
2520                 if (secondary_pipe == NULL) {
2521                         for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
2522                                 preferred_pipe_idx = j;
2523
2524                                 if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
2525                                         secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
2526                                         secondary_pipe->pipe_idx = preferred_pipe_idx;
2527                                         break;
2528                                 }
2529                         }
2530                 }
2531         }
2532
2533         return secondary_pipe;
2534 }
2535
2536 static void dcn20_merge_pipes_for_validate(
2537                 struct dc *dc,
2538                 struct dc_state *context)
2539 {
2540         int i;
2541
2542         /* merge previously split odm pipes since mode support needs to make the decision */
2543         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2544                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2545                 struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;
2546
2547                 if (pipe->prev_odm_pipe)
2548                         continue;
2549
2550                 pipe->next_odm_pipe = NULL;
2551                 while (odm_pipe) {
2552                         struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
2553
2554                         odm_pipe->plane_state = NULL;
2555                         odm_pipe->stream = NULL;
2556                         odm_pipe->top_pipe = NULL;
2557                         odm_pipe->bottom_pipe = NULL;
2558                         odm_pipe->prev_odm_pipe = NULL;
2559                         odm_pipe->next_odm_pipe = NULL;
2560                         if (odm_pipe->stream_res.dsc)
2561                                 dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
2562                         /* Clear plane_res and stream_res */
2563                         memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));
2564                         memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res));
2565                         odm_pipe = next_odm_pipe;
2566                 }
2567                 if (pipe->plane_state)
2568                         resource_build_scaling_params(pipe);
2569         }
2570
2571         /* merge previously mpc split pipes since mode support needs to make the decision */
2572         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2573                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2574                 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2575
2576                 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
2577                         continue;
2578
2579                 pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
2580                 if (hsplit_pipe->bottom_pipe)
2581                         hsplit_pipe->bottom_pipe->top_pipe = pipe;
2582                 hsplit_pipe->plane_state = NULL;
2583                 hsplit_pipe->stream = NULL;
2584                 hsplit_pipe->top_pipe = NULL;
2585                 hsplit_pipe->bottom_pipe = NULL;
2586
2587                 /* Clear plane_res and stream_res */
2588                 memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
2589                 memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
2590                 if (pipe->plane_state)
2591                         resource_build_scaling_params(pipe);
2592         }
2593 }
2594
2595 int dcn20_validate_apply_pipe_split_flags(
2596                 struct dc *dc,
2597                 struct dc_state *context,
2598                 int vlevel,
2599                 bool *split,
2600                 bool *merge)
2601 {
2602         int i, pipe_idx, vlevel_split;
2603         int plane_count = 0;
2604         bool force_split = false;
2605         bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID;
2606
2607         if (context->stream_count > 1) {
2608                 if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP)
2609                         avoid_split = true;
2610         } else if (dc->debug.force_single_disp_pipe_split)
2611                         force_split = true;
2612
2613         /* TODO: fix dc bugs and remove this split threshold thing */
2614         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2615                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2616
2617                 if (pipe->stream && !pipe->prev_odm_pipe &&
2618                                 (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state))
2619                         ++plane_count;
2620         }
2621         if (plane_count > dc->res_pool->pipe_count / 2)
2622                 avoid_split = true;
2623
2624         /* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */
2625         if (avoid_split) {
2626                 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2627                         if (!context->res_ctx.pipe_ctx[i].stream)
2628                                 continue;
2629
2630                         for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
2631                                 if (context->bw_ctx.dml.vba.NoOfDPP[vlevel][0][pipe_idx] == 1)
2632                                         break;
2633                         /* Impossible to not split this pipe */
2634                         if (vlevel > context->bw_ctx.dml.soc.num_states)
2635                                 vlevel = vlevel_split;
2636                         pipe_idx++;
2637                 }
2638                 context->bw_ctx.dml.vba.maxMpcComb = 0;
2639         }
2640
2641         /* Split loop sets which pipe should be split based on dml outputs and dc flags */
2642         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
2643                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2644                 int pipe_plane = context->bw_ctx.dml.vba.pipe_plane[pipe_idx];
2645
2646                 if (!context->res_ctx.pipe_ctx[i].stream)
2647                         continue;
2648
2649                 if (force_split || context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_plane] > 1)
2650                         split[i] = true;
2651                 if ((pipe->stream->view_format ==
2652                                 VIEW_3D_FORMAT_SIDE_BY_SIDE ||
2653                                 pipe->stream->view_format ==
2654                                 VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
2655                                 (pipe->stream->timing.timing_3d_format ==
2656                                 TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
2657                                  pipe->stream->timing.timing_3d_format ==
2658                                 TIMING_3D_FORMAT_SIDE_BY_SIDE))
2659                         split[i] = true;
2660                 if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
2661                         split[i] = true;
2662                         context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1;
2663                 }
2664                 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_plane] =
2665                         context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel][pipe_plane];
2666
2667                 if (pipe->prev_odm_pipe && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_plane] != dm_odm_combine_mode_disabled) {
2668                         /*Already split odm pipe tree, don't try to split again*/
2669                         split[i] = false;
2670                         split[pipe->prev_odm_pipe->pipe_idx] = false;
2671                 } else if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state
2672                                 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) {
2673                         /*Already split mpc tree, don't try to split again, assumes only 2x mpc combine*/
2674                         split[i] = false;
2675                         split[pipe->top_pipe->pipe_idx] = false;
2676                 } else if (pipe->prev_odm_pipe || (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)) {
2677                         if (split[i] == false) {
2678                                 /*Exiting mpc/odm combine*/
2679                                 merge[i] = true;
2680                                 if (pipe->prev_odm_pipe) {
2681                                         ASSERT(0); /*should not actually happen yet*/
2682                                         merge[pipe->prev_odm_pipe->pipe_idx] = true;
2683                                 } else
2684                                         merge[pipe->top_pipe->pipe_idx] = true;
2685                         } else {
2686                                 /*Transition from mpc combine to odm combine or vice versa*/
2687                                 ASSERT(0); /*should not actually happen yet*/
2688                                 split[i] = true;
2689                                 merge[i] = true;
2690                                 if (pipe->prev_odm_pipe) {
2691                                         split[pipe->prev_odm_pipe->pipe_idx] = true;
2692                                         merge[pipe->prev_odm_pipe->pipe_idx] = true;
2693                                 } else {
2694                                         split[pipe->top_pipe->pipe_idx] = true;
2695                                         merge[pipe->top_pipe->pipe_idx] = true;
2696                                 }
2697                         }
2698                 }
2699
2700                 /* Adjust dppclk when split is forced, do not bother with dispclk */
2701                 if (split[i] && context->bw_ctx.dml.vba.NoOfDPP[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] == 1)
2702                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] /= 2;
2703                 pipe_idx++;
2704         }
2705
2706         return vlevel;
2707 }
2708
2709 bool dcn20_fast_validate_bw(
2710                 struct dc *dc,
2711                 struct dc_state *context,
2712                 display_e2e_pipe_params_st *pipes,
2713                 int *pipe_cnt_out,
2714                 int *pipe_split_from,
2715                 int *vlevel_out)
2716 {
2717         bool out = false;
2718         bool split[MAX_PIPES] = { false };
2719         int pipe_cnt, i, pipe_idx, vlevel;
2720
2721         ASSERT(pipes);
2722         if (!pipes)
2723                 return false;
2724
2725         dcn20_merge_pipes_for_validate(dc, context);
2726
2727         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes);
2728
2729         *pipe_cnt_out = pipe_cnt;
2730
2731         if (!pipe_cnt) {
2732                 out = true;
2733                 goto validate_out;
2734         }
2735
2736         vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2737
2738         if (vlevel > context->bw_ctx.dml.soc.num_states)
2739                 goto validate_fail;
2740
2741         vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);
2742
2743         /*initialize pipe_just_split_from to invalid idx*/
2744         for (i = 0; i < MAX_PIPES; i++)
2745                 pipe_split_from[i] = -1;
2746
2747         for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2748                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2749                 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2750
2751                 if (!pipe->stream || pipe_split_from[i] >= 0)
2752                         continue;
2753
2754                 pipe_idx++;
2755
2756                 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2757                         hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2758                         ASSERT(hsplit_pipe);
2759                         if (!dcn20_split_stream_for_odm(
2760                                         &context->res_ctx, dc->res_pool,
2761                                         pipe, hsplit_pipe))
2762                                 goto validate_fail;
2763                         pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2764                         dcn20_build_mapped_resource(dc, context, pipe->stream);
2765                 }
2766
2767                 if (!pipe->plane_state)
2768                         continue;
2769                 /* Skip 2nd half of already split pipe */
2770                 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
2771                         continue;
2772
2773                 /* We do not support mpo + odm at the moment */
2774                 if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
2775                                 && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
2776                         goto validate_fail;
2777
2778                 if (split[i]) {
2779                         if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
2780                                 /* pipe not split previously needs split */
2781                                 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2782                                 ASSERT(hsplit_pipe);
2783                                 if (!hsplit_pipe) {
2784                                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2;
2785                                         continue;
2786                                 }
2787                                 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2788                                         if (!dcn20_split_stream_for_odm(
2789                                                         &context->res_ctx, dc->res_pool,
2790                                                         pipe, hsplit_pipe))
2791                                                 goto validate_fail;
2792                                         dcn20_build_mapped_resource(dc, context, pipe->stream);
2793                                 } else
2794                                         dcn20_split_stream_for_mpc(
2795                                                 &context->res_ctx, dc->res_pool,
2796                                                 pipe, hsplit_pipe);
2797                                 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2798                         }
2799                 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
2800                         /* merge should already have been done */
2801                         ASSERT(0);
2802                 }
2803         }
2804         /* Actual dsc count per stream dsc validation*/
2805         if (!dcn20_validate_dsc(dc, context)) {
2806                 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
2807                                 DML_FAIL_DSC_VALIDATION_FAILURE;
2808                 goto validate_fail;
2809         }
2810
2811         *vlevel_out = vlevel;
2812
2813         out = true;
2814         goto validate_out;
2815
2816 validate_fail:
2817         out = false;
2818
2819 validate_out:
2820         return out;
2821 }
2822
2823 static void dcn20_calculate_wm(
2824                 struct dc *dc, struct dc_state *context,
2825                 display_e2e_pipe_params_st *pipes,
2826                 int *out_pipe_cnt,
2827                 int *pipe_split_from,
2828                 int vlevel)
2829 {
2830         int pipe_cnt, i, pipe_idx;
2831
2832         for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
2833                 if (!context->res_ctx.pipe_ctx[i].stream)
2834                         continue;
2835
2836                 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
2837                 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb];
2838
2839                 if (pipe_split_from[i] < 0) {
2840                         pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2841                                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
2842                         if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
2843                                 pipes[pipe_cnt].pipe.dest.odm_combine =
2844                                                 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx];
2845                         else
2846                                 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2847                         pipe_idx++;
2848                 } else {
2849                         pipes[pipe_cnt].clks_cfg.dppclk_mhz =
2850                                         context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
2851                         if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
2852                                 pipes[pipe_cnt].pipe.dest.odm_combine =
2853                                                 context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_split_from[i]];
2854                         else
2855                                 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
2856                 }
2857
2858                 if (dc->config.forced_clocks) {
2859                         pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dispclk_mhz;
2860                         pipes[pipe_cnt].clks_cfg.dppclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dppclk_mhz;
2861                 }
2862                 if (dc->debug.min_disp_clk_khz > pipes[pipe_cnt].clks_cfg.dispclk_mhz * 1000)
2863                         pipes[pipe_cnt].clks_cfg.dispclk_mhz = dc->debug.min_disp_clk_khz / 1000.0;
2864                 if (dc->debug.min_dpp_clk_khz > pipes[pipe_cnt].clks_cfg.dppclk_mhz * 1000)
2865                         pipes[pipe_cnt].clks_cfg.dppclk_mhz = dc->debug.min_dpp_clk_khz / 1000.0;
2866
2867                 pipe_cnt++;
2868         }
2869
2870         if (pipe_cnt != pipe_idx) {
2871                 if (dc->res_pool->funcs->populate_dml_pipes)
2872                         pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
2873                                 context, pipes);
2874                 else
2875                         pipe_cnt = dcn20_populate_dml_pipes_from_context(dc,
2876                                 context, pipes);
2877         }
2878
2879         *out_pipe_cnt = pipe_cnt;
2880
2881         pipes[0].clks_cfg.voltage = vlevel;
2882         pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2883         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2884
2885         /* only pipe 0 is read for voltage and dcf/soc clocks */
2886         if (vlevel < 1) {
2887                 pipes[0].clks_cfg.voltage = 1;
2888                 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].dcfclk_mhz;
2889                 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[1].socclk_mhz;
2890         }
2891         context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2892         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2893         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2894         context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2895         context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2896         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2897         context->bw_ctx.bw.dcn.watermarks.b.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2898         context->bw_ctx.bw.dcn.watermarks.b.urgent_latency_ns = get_urgent_latency(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2899
2900         if (vlevel < 2) {
2901                 pipes[0].clks_cfg.voltage = 2;
2902                 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2903                 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2904         }
2905         context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2906         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2907         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2908         context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2909         context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2910         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2911         context->bw_ctx.bw.dcn.watermarks.c.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2912
2913         if (vlevel < 3) {
2914                 pipes[0].clks_cfg.voltage = 3;
2915                 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].dcfclk_mhz;
2916                 pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[2].socclk_mhz;
2917         }
2918         context->bw_ctx.bw.dcn.watermarks.d.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2919         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2920         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2921         context->bw_ctx.bw.dcn.watermarks.d.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2922         context->bw_ctx.bw.dcn.watermarks.d.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2923         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2924         context->bw_ctx.bw.dcn.watermarks.d.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2925
2926         pipes[0].clks_cfg.voltage = vlevel;
2927         pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].dcfclk_mhz;
2928         pipes[0].clks_cfg.socclk_mhz = context->bw_ctx.dml.soc.clock_limits[vlevel].socclk_mhz;
2929         context->bw_ctx.bw.dcn.watermarks.a.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2930         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2931         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2932         context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2933         context->bw_ctx.bw.dcn.watermarks.a.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2934         context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2935         context->bw_ctx.bw.dcn.watermarks.a.frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(&context->bw_ctx.dml, pipes, pipe_cnt) * 1000;
2936 }
2937
2938 void dcn20_calculate_dlg_params(
2939                 struct dc *dc, struct dc_state *context,
2940                 display_e2e_pipe_params_st *pipes,
2941                 int pipe_cnt,
2942                 int vlevel)
2943 {
2944         int i, j, pipe_idx, pipe_idx_unsplit;
2945         bool visited[MAX_PIPES] = { 0 };
2946
2947         /* Writeback MCIF_WB arbitration parameters */
2948         dc->res_pool->funcs->set_mcif_arb_params(dc, context, pipes, pipe_cnt);
2949
2950         context->bw_ctx.bw.dcn.clk.dispclk_khz = context->bw_ctx.dml.vba.DISPCLK * 1000;
2951         context->bw_ctx.bw.dcn.clk.dcfclk_khz = context->bw_ctx.dml.vba.DCFCLK * 1000;
2952         context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000;
2953         context->bw_ctx.bw.dcn.clk.dramclk_khz = context->bw_ctx.dml.vba.DRAMSpeed * 1000 / 16;
2954         context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = context->bw_ctx.dml.vba.DCFCLKDeepSleep * 1000;
2955         context->bw_ctx.bw.dcn.clk.fclk_khz = context->bw_ctx.dml.vba.FabricClock * 1000;
2956         context->bw_ctx.bw.dcn.clk.p_state_change_support =
2957                 context->bw_ctx.dml.vba.DRAMClockChangeSupport[vlevel][context->bw_ctx.dml.vba.maxMpcComb]
2958                                                         != dm_dram_clock_change_unsupported;
2959         context->bw_ctx.bw.dcn.clk.dppclk_khz = 0;
2960
2961         if (context->bw_ctx.bw.dcn.clk.dispclk_khz < dc->debug.min_disp_clk_khz)
2962                 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz;
2963
2964         /*
2965          * An artifact of dml pipe split/odm is that pipes get merged back together for
2966          * calculation. Therefore we need to only extract for first pipe in ascending index order
2967          * and copy into the other split half.
2968          */
2969         for (i = 0, pipe_idx = 0, pipe_idx_unsplit = 0; i < dc->res_pool->pipe_count; i++) {
2970                 if (!context->res_ctx.pipe_ctx[i].stream)
2971                         continue;
2972
2973                 if (!visited[pipe_idx]) {
2974                         display_pipe_source_params_st *src = &pipes[pipe_idx].pipe.src;
2975                         display_pipe_dest_params_st *dst = &pipes[pipe_idx].pipe.dest;
2976
2977                         dst->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
2978                         dst->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
2979                         dst->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
2980                         dst->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
2981                         /*
2982                          * j iterates inside pipes array, unlike i which iterates inside
2983                          * pipe_ctx array
2984                          */
2985                         if (src->is_hsplit)
2986                                 for (j = pipe_idx + 1; j < pipe_cnt; j++) {
2987                                         display_pipe_source_params_st *src_j = &pipes[j].pipe.src;
2988                                         display_pipe_dest_params_st *dst_j = &pipes[j].pipe.dest;
2989
2990                                         if (src_j->is_hsplit && !visited[j]
2991                                                         && src->hsplit_grp == src_j->hsplit_grp) {
2992                                                 dst_j->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit];
2993                                                 dst_j->vupdate_offset = context->bw_ctx.dml.vba.VUpdateOffsetPix[pipe_idx_unsplit];
2994                                                 dst_j->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
2995                                                 dst_j->vready_offset = context->bw_ctx.dml.vba.VReadyOffsetPix[pipe_idx_unsplit];
2996                                                 visited[j] = true;
2997                                         }
2998                                 }
2999                         visited[pipe_idx] = true;
3000                         pipe_idx_unsplit++;
3001                 }
3002                 pipe_idx++;
3003         }
3004
3005         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3006                 if (!context->res_ctx.pipe_ctx[i].stream)
3007                         continue;
3008                 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000)
3009                         context->bw_ctx.bw.dcn.clk.dppclk_khz = pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
3010                 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz =
3011                                                 pipes[pipe_idx].clks_cfg.dppclk_mhz * 1000;
3012                 ASSERT(visited[pipe_idx]);
3013                 context->res_ctx.pipe_ctx[i].pipe_dlg_param = pipes[pipe_idx].pipe.dest;
3014                 pipe_idx++;
3015         }
3016         /*save a original dppclock copy*/
3017         context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
3018         context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
3019         context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dppclk_mhz * 1000;
3020         context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = context->bw_ctx.dml.soc.clock_limits[vlevel].dispclk_mhz * 1000;
3021
3022         for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
3023                 bool cstate_en = context->bw_ctx.dml.vba.PrefetchMode[vlevel][context->bw_ctx.dml.vba.maxMpcComb] != 2;
3024
3025                 if (!context->res_ctx.pipe_ctx[i].stream)
3026                         continue;
3027
3028                 context->bw_ctx.dml.funcs.rq_dlg_get_dlg_reg(&context->bw_ctx.dml,
3029                                 &context->res_ctx.pipe_ctx[i].dlg_regs,
3030                                 &context->res_ctx.pipe_ctx[i].ttu_regs,
3031                                 pipes,
3032                                 pipe_cnt,
3033                                 pipe_idx,
3034                                 cstate_en,
3035                                 context->bw_ctx.bw.dcn.clk.p_state_change_support,
3036                                 false, false, false);
3037
3038                 context->bw_ctx.dml.funcs.rq_dlg_get_rq_reg(&context->bw_ctx.dml,
3039                                 &context->res_ctx.pipe_ctx[i].rq_regs,
3040                                 pipes[pipe_idx].pipe);
3041                 pipe_idx++;
3042         }
3043 }
3044
3045 static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *context,
3046                 bool fast_validate)
3047 {
3048         bool out = false;
3049
3050         BW_VAL_TRACE_SETUP();
3051
3052         int vlevel = 0;
3053         int pipe_split_from[MAX_PIPES];
3054         int pipe_cnt = 0;
3055         display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
3056         DC_LOGGER_INIT(dc->ctx->logger);
3057
3058         BW_VAL_TRACE_COUNT();
3059
3060         out = dcn20_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel);
3061
3062         if (pipe_cnt == 0)
3063                 goto validate_out;
3064
3065         if (!out)
3066                 goto validate_fail;
3067
3068         BW_VAL_TRACE_END_VOLTAGE_LEVEL();
3069
3070         if (fast_validate) {
3071                 BW_VAL_TRACE_SKIP(fast);
3072                 goto validate_out;
3073         }
3074
3075         dcn20_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel);
3076         dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
3077
3078         BW_VAL_TRACE_END_WATERMARKS();
3079
3080         goto validate_out;
3081
3082 validate_fail:
3083         DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
3084                 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
3085
3086         BW_VAL_TRACE_SKIP(fail);
3087         out = false;
3088
3089 validate_out:
3090         kfree(pipes);
3091
3092         BW_VAL_TRACE_FINISH();
3093
3094         return out;
3095 }
3096
3097
3098 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
3099                 bool fast_validate)
3100 {
3101         bool voltage_supported = false;
3102         bool full_pstate_supported = false;
3103         bool dummy_pstate_supported = false;
3104         double p_state_latency_us;
3105
3106         DC_FP_START();
3107         p_state_latency_us = context->bw_ctx.dml.soc.dram_clock_change_latency_us;
3108         context->bw_ctx.dml.soc.disable_dram_clock_change_vactive_support =
3109                 dc->debug.disable_dram_clock_change_vactive_support;
3110
3111         if (fast_validate) {
3112                 voltage_supported = dcn20_validate_bandwidth_internal(dc, context, true);
3113
3114                 DC_FP_END();
3115                 return voltage_supported;
3116         }
3117
3118         // Best case, we support full UCLK switch latency
3119         voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
3120         full_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
3121
3122         if (context->bw_ctx.dml.soc.dummy_pstate_latency_us == 0 ||
3123                 (voltage_supported && full_pstate_supported)) {
3124                 context->bw_ctx.bw.dcn.clk.p_state_change_support = full_pstate_supported;
3125                 goto restore_dml_state;
3126         }
3127
3128         // Fallback: Try to only support G6 temperature read latency
3129         context->bw_ctx.dml.soc.dram_clock_change_latency_us = context->bw_ctx.dml.soc.dummy_pstate_latency_us;
3130
3131         voltage_supported = dcn20_validate_bandwidth_internal(dc, context, false);
3132         dummy_pstate_supported = context->bw_ctx.bw.dcn.clk.p_state_change_support;
3133
3134         if (voltage_supported && dummy_pstate_supported) {
3135                 context->bw_ctx.bw.dcn.clk.p_state_change_support = false;
3136                 goto restore_dml_state;
3137         }
3138
3139         // ERROR: fallback is supposed to always work.
3140         ASSERT(false);
3141
3142 restore_dml_state:
3143         context->bw_ctx.dml.soc.dram_clock_change_latency_us = p_state_latency_us;
3144
3145         DC_FP_END();
3146         return voltage_supported;
3147 }
3148
3149 struct pipe_ctx *dcn20_acquire_idle_pipe_for_layer(
3150                 struct dc_state *state,
3151                 const struct resource_pool *pool,
3152                 struct dc_stream_state *stream)
3153 {
3154         struct resource_context *res_ctx = &state->res_ctx;
3155         struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);
3156         struct pipe_ctx *idle_pipe = find_idle_secondary_pipe(res_ctx, pool, head_pipe);
3157
3158         if (!head_pipe)
3159                 ASSERT(0);
3160
3161         if (!idle_pipe)
3162                 return NULL;
3163
3164         idle_pipe->stream = head_pipe->stream;
3165         idle_pipe->stream_res.tg = head_pipe->stream_res.tg;
3166         idle_pipe->stream_res.opp = head_pipe->stream_res.opp;
3167
3168         idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
3169         idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
3170         idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
3171         idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
3172
3173         return idle_pipe;
3174 }
3175
3176 bool dcn20_get_dcc_compression_cap(const struct dc *dc,
3177                 const struct dc_dcc_surface_param *input,
3178                 struct dc_surface_dcc_cap *output)
3179 {
3180         return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
3181                         dc->res_pool->hubbub,
3182                         input,
3183                         output);
3184 }
3185
3186 static void dcn20_destroy_resource_pool(struct resource_pool **pool)
3187 {
3188         struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);
3189
3190         dcn20_resource_destruct(dcn20_pool);
3191         kfree(dcn20_pool);
3192         *pool = NULL;
3193 }
3194
3195
3196 static struct dc_cap_funcs cap_funcs = {
3197         .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
3198 };
3199
3200
3201 enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state)
3202 {
3203         enum dc_status result = DC_OK;
3204
3205         enum surface_pixel_format surf_pix_format = plane_state->format;
3206         unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
3207
3208         enum swizzle_mode_values swizzle = DC_SW_LINEAR;
3209
3210         if (bpp == 64)
3211                 swizzle = DC_SW_64KB_D;
3212         else
3213                 swizzle = DC_SW_64KB_S;
3214
3215         plane_state->tiling_info.gfx9.swizzle = swizzle;
3216         return result;
3217 }
3218
3219 static struct resource_funcs dcn20_res_pool_funcs = {
3220         .destroy = dcn20_destroy_resource_pool,
3221         .link_enc_create = dcn20_link_encoder_create,
3222         .panel_create = dcn20_panel_create,
3223         .validate_bandwidth = dcn20_validate_bandwidth,
3224         .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
3225         .add_stream_to_ctx = dcn20_add_stream_to_ctx,
3226         .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
3227         .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
3228         .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
3229         .set_mcif_arb_params = dcn20_set_mcif_arb_params,
3230         .populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
3231         .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
3232 };
3233
3234 bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
3235 {
3236         int i;
3237         uint32_t pipe_count = pool->res_cap->num_dwb;
3238
3239         for (i = 0; i < pipe_count; i++) {
3240                 struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
3241                                                     GFP_KERNEL);
3242
3243                 if (!dwbc20) {
3244                         dm_error("DC: failed to create dwbc20!\n");
3245                         return false;
3246                 }
3247                 dcn20_dwbc_construct(dwbc20, ctx,
3248                                 &dwbc20_regs[i],
3249                                 &dwbc20_shift,
3250                                 &dwbc20_mask,
3251                                 i);
3252                 pool->dwbc[i] = &dwbc20->base;
3253         }
3254         return true;
3255 }
3256
3257 bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
3258 {
3259         int i;
3260         uint32_t pipe_count = pool->res_cap->num_dwb;
3261
3262         ASSERT(pipe_count > 0);
3263
3264         for (i = 0; i < pipe_count; i++) {
3265                 struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub),
3266                                                     GFP_KERNEL);
3267
3268                 if (!mcif_wb20) {
3269                         dm_error("DC: failed to create mcif_wb20!\n");
3270                         return false;
3271                 }
3272
3273                 dcn20_mmhubbub_construct(mcif_wb20, ctx,
3274                                 &mcif_wb20_regs[i],
3275                                 &mcif_wb20_shift,
3276                                 &mcif_wb20_mask,
3277                                 i);
3278
3279                 pool->mcif_wb[i] = &mcif_wb20->base;
3280         }
3281         return true;
3282 }
3283
3284 static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
3285 {
3286         struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
3287
3288         if (!pp_smu)
3289                 return pp_smu;
3290
3291         dm_pp_get_funcs(ctx, pp_smu);
3292
3293         if (pp_smu->ctx.ver != PP_SMU_VER_NV)
3294                 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
3295
3296         return pp_smu;
3297 }
3298
3299 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
3300 {
3301         if (pp_smu && *pp_smu) {
3302                 kfree(*pp_smu);
3303                 *pp_smu = NULL;
3304         }
3305 }
3306
3307 void dcn20_cap_soc_clocks(
3308                 struct _vcs_dpi_soc_bounding_box_st *bb,
3309                 struct pp_smu_nv_clock_table max_clocks)
3310 {
3311         int i;
3312
3313         // First pass - cap all clocks higher than the reported max
3314         for (i = 0; i < bb->num_states; i++) {
3315                 if ((bb->clock_limits[i].dcfclk_mhz > (max_clocks.dcfClockInKhz / 1000))
3316                                 && max_clocks.dcfClockInKhz != 0)
3317                         bb->clock_limits[i].dcfclk_mhz = (max_clocks.dcfClockInKhz / 1000);
3318
3319                 if ((bb->clock_limits[i].dram_speed_mts > (max_clocks.uClockInKhz / 1000) * 16)
3320                                                 && max_clocks.uClockInKhz != 0)
3321                         bb->clock_limits[i].dram_speed_mts = (max_clocks.uClockInKhz / 1000) * 16;
3322
3323                 if ((bb->clock_limits[i].fabricclk_mhz > (max_clocks.fabricClockInKhz / 1000))
3324                                                 && max_clocks.fabricClockInKhz != 0)
3325                         bb->clock_limits[i].fabricclk_mhz = (max_clocks.fabricClockInKhz / 1000);
3326
3327                 if ((bb->clock_limits[i].dispclk_mhz > (max_clocks.displayClockInKhz / 1000))
3328                                                 && max_clocks.displayClockInKhz != 0)
3329                         bb->clock_limits[i].dispclk_mhz = (max_clocks.displayClockInKhz / 1000);
3330
3331                 if ((bb->clock_limits[i].dppclk_mhz > (max_clocks.dppClockInKhz / 1000))
3332                                                 && max_clocks.dppClockInKhz != 0)
3333                         bb->clock_limits[i].dppclk_mhz = (max_clocks.dppClockInKhz / 1000);
3334
3335                 if ((bb->clock_limits[i].phyclk_mhz > (max_clocks.phyClockInKhz / 1000))
3336                                                 && max_clocks.phyClockInKhz != 0)
3337                         bb->clock_limits[i].phyclk_mhz = (max_clocks.phyClockInKhz / 1000);
3338
3339                 if ((bb->clock_limits[i].socclk_mhz > (max_clocks.socClockInKhz / 1000))
3340                                                 && max_clocks.socClockInKhz != 0)
3341                         bb->clock_limits[i].socclk_mhz = (max_clocks.socClockInKhz / 1000);
3342
3343                 if ((bb->clock_limits[i].dscclk_mhz > (max_clocks.dscClockInKhz / 1000))
3344                                                 && max_clocks.dscClockInKhz != 0)
3345                         bb->clock_limits[i].dscclk_mhz = (max_clocks.dscClockInKhz / 1000);
3346         }
3347
3348         // Second pass - remove all duplicate clock states
3349         for (i = bb->num_states - 1; i > 1; i--) {
3350                 bool duplicate = true;
3351
3352                 if (bb->clock_limits[i-1].dcfclk_mhz != bb->clock_limits[i].dcfclk_mhz)
3353                         duplicate = false;
3354                 if (bb->clock_limits[i-1].dispclk_mhz != bb->clock_limits[i].dispclk_mhz)
3355                         duplicate = false;
3356                 if (bb->clock_limits[i-1].dppclk_mhz != bb->clock_limits[i].dppclk_mhz)
3357                         duplicate = false;
3358                 if (bb->clock_limits[i-1].dram_speed_mts != bb->clock_limits[i].dram_speed_mts)
3359                         duplicate = false;
3360                 if (bb->clock_limits[i-1].dscclk_mhz != bb->clock_limits[i].dscclk_mhz)
3361                         duplicate = false;
3362                 if (bb->clock_limits[i-1].fabricclk_mhz != bb->clock_limits[i].fabricclk_mhz)
3363                         duplicate = false;
3364                 if (bb->clock_limits[i-1].phyclk_mhz != bb->clock_limits[i].phyclk_mhz)
3365                         duplicate = false;
3366                 if (bb->clock_limits[i-1].socclk_mhz != bb->clock_limits[i].socclk_mhz)
3367                         duplicate = false;
3368
3369                 if (duplicate)
3370                         bb->num_states--;
3371         }
3372 }
3373
3374 void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
3375                 struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
3376 {
3377         struct _vcs_dpi_voltage_scaling_st calculated_states[DC__VOLTAGE_STATES];
3378         int i;
3379         int num_calculated_states = 0;
3380         int min_dcfclk = 0;
3381
3382         if (num_states == 0)
3383                 return;
3384
3385         memset(calculated_states, 0, sizeof(calculated_states));
3386
3387         if (dc->bb_overrides.min_dcfclk_mhz > 0)
3388                 min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
3389         else {
3390                 if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
3391                         min_dcfclk = 310;
3392                 else
3393                         // Accounting for SOC/DCF relationship, we can go as high as
3394                         // 506Mhz in Vmin.
3395                         min_dcfclk = 506;
3396         }
3397
3398         for (i = 0; i < num_states; i++) {
3399                 int min_fclk_required_by_uclk;
3400                 calculated_states[i].state = i;
3401                 calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
3402
3403                 // FCLK:UCLK ratio is 1.08
3404                 min_fclk_required_by_uclk = mul_u64_u32_shr(BIT_ULL(32) * 1080 / 1000000, uclk_states[i], 32);
3405
3406                 calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
3407                                 min_dcfclk : min_fclk_required_by_uclk;
3408
3409                 calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
3410                                 max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
3411
3412                 calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
3413                                 max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
3414
3415                 calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
3416                 calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
3417                 calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
3418
3419                 calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
3420
3421                 num_calculated_states++;
3422         }
3423
3424         calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
3425         calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
3426         calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
3427
3428         memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
3429         bb->num_states = num_calculated_states;
3430
3431         // Duplicate the last state, DML always an extra state identical to max state to work
3432         memcpy(&bb->clock_limits[num_calculated_states], &bb->clock_limits[num_calculated_states - 1], sizeof(struct _vcs_dpi_voltage_scaling_st));
3433         bb->clock_limits[num_calculated_states].state = bb->num_states;
3434 }
3435
3436 void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
3437 {
3438         if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
3439                         && dc->bb_overrides.sr_exit_time_ns) {
3440                 bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
3441         }
3442
3443         if ((int)(bb->sr_enter_plus_exit_time_us * 1000)
3444                                 != dc->bb_overrides.sr_enter_plus_exit_time_ns
3445                         && dc->bb_overrides.sr_enter_plus_exit_time_ns) {
3446                 bb->sr_enter_plus_exit_time_us =
3447                                 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
3448         }
3449
3450         if ((int)(bb->urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns
3451                         && dc->bb_overrides.urgent_latency_ns) {
3452                 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
3453         }
3454
3455         if ((int)(bb->dram_clock_change_latency_us * 1000)
3456                                 != dc->bb_overrides.dram_clock_change_latency_ns
3457                         && dc->bb_overrides.dram_clock_change_latency_ns) {
3458                 bb->dram_clock_change_latency_us =
3459                                 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
3460         }
3461 }
3462
3463 static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
3464         uint32_t hw_internal_rev)
3465 {
3466         if (ASICREV_IS_NAVI14_M(hw_internal_rev))
3467                 return &dcn2_0_nv14_soc;
3468
3469         if (ASICREV_IS_NAVI12_P(hw_internal_rev))
3470                 return &dcn2_0_nv12_soc;
3471
3472         return &dcn2_0_soc;
3473 }
3474
3475 static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params(
3476         uint32_t hw_internal_rev)
3477 {
3478         /* NV14 */
3479         if (ASICREV_IS_NAVI14_M(hw_internal_rev))
3480                 return &dcn2_0_nv14_ip;
3481
3482         /* NV12 and NV10 */
3483         return &dcn2_0_ip;
3484 }
3485
3486 static enum dml_project get_dml_project_version(uint32_t hw_internal_rev)
3487 {
3488         return DML_PROJECT_NAVI10v2;
3489 }
3490
3491 #define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
3492 #define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
3493
3494 static bool init_soc_bounding_box(struct dc *dc,
3495                                   struct dcn20_resource_pool *pool)
3496 {
3497         const struct gpu_info_soc_bounding_box_v1_0 *bb = dc->soc_bounding_box;
3498         struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3499                         get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);
3500         struct _vcs_dpi_ip_params_st *loaded_ip =
3501                         get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev);
3502
3503         DC_LOGGER_INIT(dc->ctx->logger);
3504
3505         /* TODO: upstream NV12 bounding box when its launched */
3506         if (!bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
3507                 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
3508                 return false;
3509         }
3510
3511         if (bb && ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
3512                 int i;
3513
3514                 dcn2_0_nv12_soc.sr_exit_time_us =
3515                                 fixed16_to_double_to_cpu(bb->sr_exit_time_us);
3516                 dcn2_0_nv12_soc.sr_enter_plus_exit_time_us =
3517                                 fixed16_to_double_to_cpu(bb->sr_enter_plus_exit_time_us);
3518                 dcn2_0_nv12_soc.urgent_latency_us =
3519                                 fixed16_to_double_to_cpu(bb->urgent_latency_us);
3520                 dcn2_0_nv12_soc.urgent_latency_pixel_data_only_us =
3521                                 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_data_only_us);
3522                 dcn2_0_nv12_soc.urgent_latency_pixel_mixed_with_vm_data_us =
3523                                 fixed16_to_double_to_cpu(bb->urgent_latency_pixel_mixed_with_vm_data_us);
3524                 dcn2_0_nv12_soc.urgent_latency_vm_data_only_us =
3525                                 fixed16_to_double_to_cpu(bb->urgent_latency_vm_data_only_us);
3526                 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes =
3527                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_only_bytes);
3528                 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_pixel_and_vm_bytes =
3529                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_pixel_and_vm_bytes);
3530                 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_vm_only_bytes =
3531                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_vm_only_bytes);
3532                 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_only =
3533                                 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_only);
3534                 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm =
3535                                 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm);
3536                 dcn2_0_nv12_soc.pct_ideal_dram_sdp_bw_after_urgent_vm_only =
3537                                 fixed16_to_double_to_cpu(bb->pct_ideal_dram_sdp_bw_after_urgent_vm_only);
3538                 dcn2_0_nv12_soc.max_avg_sdp_bw_use_normal_percent =
3539                                 fixed16_to_double_to_cpu(bb->max_avg_sdp_bw_use_normal_percent);
3540                 dcn2_0_nv12_soc.max_avg_dram_bw_use_normal_percent =
3541                                 fixed16_to_double_to_cpu(bb->max_avg_dram_bw_use_normal_percent);
3542                 dcn2_0_nv12_soc.writeback_latency_us =
3543                                 fixed16_to_double_to_cpu(bb->writeback_latency_us);
3544                 dcn2_0_nv12_soc.ideal_dram_bw_after_urgent_percent =
3545                                 fixed16_to_double_to_cpu(bb->ideal_dram_bw_after_urgent_percent);
3546                 dcn2_0_nv12_soc.max_request_size_bytes =
3547                                 le32_to_cpu(bb->max_request_size_bytes);
3548                 dcn2_0_nv12_soc.dram_channel_width_bytes =
3549                                 le32_to_cpu(bb->dram_channel_width_bytes);
3550                 dcn2_0_nv12_soc.fabric_datapath_to_dcn_data_return_bytes =
3551                                 le32_to_cpu(bb->fabric_datapath_to_dcn_data_return_bytes);
3552                 dcn2_0_nv12_soc.dcn_downspread_percent =
3553                                 fixed16_to_double_to_cpu(bb->dcn_downspread_percent);
3554                 dcn2_0_nv12_soc.downspread_percent =
3555                                 fixed16_to_double_to_cpu(bb->downspread_percent);
3556                 dcn2_0_nv12_soc.dram_page_open_time_ns =
3557                                 fixed16_to_double_to_cpu(bb->dram_page_open_time_ns);
3558                 dcn2_0_nv12_soc.dram_rw_turnaround_time_ns =
3559                                 fixed16_to_double_to_cpu(bb->dram_rw_turnaround_time_ns);
3560                 dcn2_0_nv12_soc.dram_return_buffer_per_channel_bytes =
3561                                 le32_to_cpu(bb->dram_return_buffer_per_channel_bytes);
3562                 dcn2_0_nv12_soc.round_trip_ping_latency_dcfclk_cycles =
3563                                 le32_to_cpu(bb->round_trip_ping_latency_dcfclk_cycles);
3564                 dcn2_0_nv12_soc.urgent_out_of_order_return_per_channel_bytes =
3565                                 le32_to_cpu(bb->urgent_out_of_order_return_per_channel_bytes);
3566                 dcn2_0_nv12_soc.channel_interleave_bytes =
3567                                 le32_to_cpu(bb->channel_interleave_bytes);
3568                 dcn2_0_nv12_soc.num_banks =
3569                                 le32_to_cpu(bb->num_banks);
3570                 dcn2_0_nv12_soc.num_chans =
3571                                 le32_to_cpu(bb->num_chans);
3572                 dcn2_0_nv12_soc.vmm_page_size_bytes =
3573                                 le32_to_cpu(bb->vmm_page_size_bytes);
3574                 dcn2_0_nv12_soc.dram_clock_change_latency_us =
3575                                 fixed16_to_double_to_cpu(bb->dram_clock_change_latency_us);
3576                 // HACK!! Lower uclock latency switch time so we don't switch
3577                 dcn2_0_nv12_soc.dram_clock_change_latency_us = 10;
3578                 dcn2_0_nv12_soc.writeback_dram_clock_change_latency_us =
3579                                 fixed16_to_double_to_cpu(bb->writeback_dram_clock_change_latency_us);
3580                 dcn2_0_nv12_soc.return_bus_width_bytes =
3581                                 le32_to_cpu(bb->return_bus_width_bytes);
3582                 dcn2_0_nv12_soc.dispclk_dppclk_vco_speed_mhz =
3583                                 le32_to_cpu(bb->dispclk_dppclk_vco_speed_mhz);
3584                 dcn2_0_nv12_soc.xfc_bus_transport_time_us =
3585                                 le32_to_cpu(bb->xfc_bus_transport_time_us);
3586                 dcn2_0_nv12_soc.xfc_xbuf_latency_tolerance_us =
3587                                 le32_to_cpu(bb->xfc_xbuf_latency_tolerance_us);
3588                 dcn2_0_nv12_soc.use_urgent_burst_bw =
3589                                 le32_to_cpu(bb->use_urgent_burst_bw);
3590                 dcn2_0_nv12_soc.num_states =
3591                                 le32_to_cpu(bb->num_states);
3592
3593                 for (i = 0; i < dcn2_0_nv12_soc.num_states; i++) {
3594                         dcn2_0_nv12_soc.clock_limits[i].state =
3595                                         le32_to_cpu(bb->clock_limits[i].state);
3596                         dcn2_0_nv12_soc.clock_limits[i].dcfclk_mhz =
3597                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dcfclk_mhz);
3598                         dcn2_0_nv12_soc.clock_limits[i].fabricclk_mhz =
3599                                         fixed16_to_double_to_cpu(bb->clock_limits[i].fabricclk_mhz);
3600                         dcn2_0_nv12_soc.clock_limits[i].dispclk_mhz =
3601                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dispclk_mhz);
3602                         dcn2_0_nv12_soc.clock_limits[i].dppclk_mhz =
3603                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dppclk_mhz);
3604                         dcn2_0_nv12_soc.clock_limits[i].phyclk_mhz =
3605                                         fixed16_to_double_to_cpu(bb->clock_limits[i].phyclk_mhz);
3606                         dcn2_0_nv12_soc.clock_limits[i].socclk_mhz =
3607                                         fixed16_to_double_to_cpu(bb->clock_limits[i].socclk_mhz);
3608                         dcn2_0_nv12_soc.clock_limits[i].dscclk_mhz =
3609                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dscclk_mhz);
3610                         dcn2_0_nv12_soc.clock_limits[i].dram_speed_mts =
3611                                         fixed16_to_double_to_cpu(bb->clock_limits[i].dram_speed_mts);
3612                 }
3613         }
3614
3615         if (pool->base.pp_smu) {
3616                 struct pp_smu_nv_clock_table max_clocks = {0};
3617                 unsigned int uclk_states[8] = {0};
3618                 unsigned int num_states = 0;
3619                 enum pp_smu_status status;
3620                 bool clock_limits_available = false;
3621                 bool uclk_states_available = false;
3622
3623                 if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
3624                         status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
3625                                 (&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
3626
3627                         uclk_states_available = (status == PP_SMU_RESULT_OK);
3628                 }
3629
3630                 if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
3631                         status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
3632                                         (&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
3633                         /* SMU cannot set DCF clock to anything equal to or higher than SOC clock
3634                          */
3635                         if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)
3636                                 max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;
3637                         clock_limits_available = (status == PP_SMU_RESULT_OK);
3638                 }
3639
3640                 if (clock_limits_available && uclk_states_available && num_states)
3641                         dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
3642                 else if (clock_limits_available)
3643                         dcn20_cap_soc_clocks(loaded_bb, max_clocks);
3644         }
3645
3646         loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
3647         loaded_ip->max_num_dpp = pool->base.pipe_count;
3648         dcn20_patch_bounding_box(dc, loaded_bb);
3649
3650         return true;
3651 }
3652
3653 static bool dcn20_resource_construct(
3654         uint8_t num_virtual_links,
3655         struct dc *dc,
3656         struct dcn20_resource_pool *pool)
3657 {
3658         int i;
3659         struct dc_context *ctx = dc->ctx;
3660         struct irq_service_init_data init_data;
3661         struct ddc_service_init_data ddc_init_data;
3662         struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
3663                         get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev);
3664         struct _vcs_dpi_ip_params_st *loaded_ip =
3665                         get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev);
3666         enum dml_project dml_project_version =
3667                         get_dml_project_version(ctx->asic_id.hw_internal_rev);
3668
3669         DC_FP_START();
3670
3671         ctx->dc_bios->regs = &bios_regs;
3672         pool->base.funcs = &dcn20_res_pool_funcs;
3673
3674         if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
3675                 pool->base.res_cap = &res_cap_nv14;
3676                 pool->base.pipe_count = 5;
3677                 pool->base.mpcc_count = 5;
3678         } else {
3679                 pool->base.res_cap = &res_cap_nv10;
3680                 pool->base.pipe_count = 6;
3681                 pool->base.mpcc_count = 6;
3682         }
3683         /*************************************************
3684          *  Resource + asic cap harcoding                *
3685          *************************************************/
3686         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
3687
3688         dc->caps.max_downscale_ratio = 200;
3689         dc->caps.i2c_speed_in_khz = 100;
3690         dc->caps.max_cursor_size = 256;
3691         dc->caps.dmdata_alloc_size = 2048;
3692
3693         dc->caps.max_slave_planes = 1;
3694         dc->caps.post_blend_color_processing = true;
3695         dc->caps.force_dp_tps4_for_cp2520 = true;
3696         dc->caps.hw_3d_lut = true;
3697         dc->caps.extended_aux_timeout_support = true;
3698
3699         if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV) {
3700                 dc->debug = debug_defaults_drv;
3701         } else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
3702                 pool->base.pipe_count = 4;
3703                 pool->base.mpcc_count = pool->base.pipe_count;
3704                 dc->debug = debug_defaults_diags;
3705         } else {
3706                 dc->debug = debug_defaults_diags;
3707         }
3708         //dcn2.0x
3709         dc->work_arounds.dedcn20_305_wa = true;
3710
3711         // Init the vm_helper
3712         if (dc->vm_helper)
3713                 vm_helper_init(dc->vm_helper, 16);
3714
3715         /*************************************************
3716          *  Create resources                             *
3717          *************************************************/
3718
3719         pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
3720                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3721                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
3722                                 &clk_src_regs[0], false);
3723         pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
3724                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3725                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
3726                                 &clk_src_regs[1], false);
3727         pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
3728                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3729                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
3730                                 &clk_src_regs[2], false);
3731         pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
3732                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3733                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
3734                                 &clk_src_regs[3], false);
3735         pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
3736                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3737                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
3738                                 &clk_src_regs[4], false);
3739         pool->base.clock_sources[DCN20_CLK_SRC_PLL5] =
3740                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3741                                 CLOCK_SOURCE_COMBO_PHY_PLL5,
3742                                 &clk_src_regs[5], false);
3743         pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL;
3744         /* todo: not reuse phy_pll registers */
3745         pool->base.dp_clock_source =
3746                         dcn20_clock_source_create(ctx, ctx->dc_bios,
3747                                 CLOCK_SOURCE_ID_DP_DTO,
3748                                 &clk_src_regs[0], true);
3749
3750         for (i = 0; i < pool->base.clk_src_count; i++) {
3751                 if (pool->base.clock_sources[i] == NULL) {
3752                         dm_error("DC: failed to create clock sources!\n");
3753                         BREAK_TO_DEBUGGER();
3754                         goto create_fail;
3755                 }
3756         }
3757
3758         pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
3759         if (pool->base.dccg == NULL) {
3760                 dm_error("DC: failed to create dccg!\n");
3761                 BREAK_TO_DEBUGGER();
3762                 goto create_fail;
3763         }
3764
3765         pool->base.dmcu = dcn20_dmcu_create(ctx,
3766                         &dmcu_regs,
3767                         &dmcu_shift,
3768                         &dmcu_mask);
3769         if (pool->base.dmcu == NULL) {
3770                 dm_error("DC: failed to create dmcu!\n");
3771                 BREAK_TO_DEBUGGER();
3772                 goto create_fail;
3773         }
3774
3775         pool->base.abm = dce_abm_create(ctx,
3776                         &abm_regs,
3777                         &abm_shift,
3778                         &abm_mask);
3779         if (pool->base.abm == NULL) {
3780                 dm_error("DC: failed to create abm!\n");
3781                 BREAK_TO_DEBUGGER();
3782                 goto create_fail;
3783         }
3784
3785         pool->base.pp_smu = dcn20_pp_smu_create(ctx);
3786
3787
3788         if (!init_soc_bounding_box(dc, pool)) {
3789                 dm_error("DC: failed to initialize soc bounding box!\n");
3790                 BREAK_TO_DEBUGGER();
3791                 goto create_fail;
3792         }
3793
3794         dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version);
3795
3796         if (!dc->debug.disable_pplib_wm_range) {
3797                 struct pp_smu_wm_range_sets ranges = {0};
3798                 int i = 0;
3799
3800                 ranges.num_reader_wm_sets = 0;
3801
3802                 if (loaded_bb->num_states == 1) {
3803                         ranges.reader_wm_sets[0].wm_inst = i;
3804                         ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3805                         ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3806                         ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3807                         ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3808
3809                         ranges.num_reader_wm_sets = 1;
3810                 } else if (loaded_bb->num_states > 1) {
3811                         for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
3812                                 ranges.reader_wm_sets[i].wm_inst = i;
3813                                 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3814                                 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3815                                 ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
3816                                 ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
3817
3818                                 ranges.num_reader_wm_sets = i + 1;
3819                         }
3820
3821                         ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3822                         ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3823                 }
3824
3825                 ranges.num_writer_wm_sets = 1;
3826
3827                 ranges.writer_wm_sets[0].wm_inst = 0;
3828                 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3829                 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3830                 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
3831                 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
3832
3833                 /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
3834                 if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
3835                         pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);
3836         }
3837
3838         init_data.ctx = dc->ctx;
3839         pool->base.irqs = dal_irq_service_dcn20_create(&init_data);
3840         if (!pool->base.irqs)
3841                 goto create_fail;
3842
3843         /* mem input -> ipp -> dpp -> opp -> TG */
3844         for (i = 0; i < pool->base.pipe_count; i++) {
3845                 pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
3846                 if (pool->base.hubps[i] == NULL) {
3847                         BREAK_TO_DEBUGGER();
3848                         dm_error(
3849                                 "DC: failed to create memory input!\n");
3850                         goto create_fail;
3851                 }
3852
3853                 pool->base.ipps[i] = dcn20_ipp_create(ctx, i);
3854                 if (pool->base.ipps[i] == NULL) {
3855                         BREAK_TO_DEBUGGER();
3856                         dm_error(
3857                                 "DC: failed to create input pixel processor!\n");
3858                         goto create_fail;
3859                 }
3860
3861                 pool->base.dpps[i] = dcn20_dpp_create(ctx, i);
3862                 if (pool->base.dpps[i] == NULL) {
3863                         BREAK_TO_DEBUGGER();
3864                         dm_error(
3865                                 "DC: failed to create dpps!\n");
3866                         goto create_fail;
3867                 }
3868         }
3869         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
3870                 pool->base.engines[i] = dcn20_aux_engine_create(ctx, i);
3871                 if (pool->base.engines[i] == NULL) {
3872                         BREAK_TO_DEBUGGER();
3873                         dm_error(
3874                                 "DC:failed to create aux engine!!\n");
3875                         goto create_fail;
3876                 }
3877                 pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i);
3878                 if (pool->base.hw_i2cs[i] == NULL) {
3879                         BREAK_TO_DEBUGGER();
3880                         dm_error(
3881                                 "DC:failed to create hw i2c!!\n");
3882                         goto create_fail;
3883                 }
3884                 pool->base.sw_i2cs[i] = NULL;
3885         }
3886
3887         for (i = 0; i < pool->base.res_cap->num_opp; i++) {
3888                 pool->base.opps[i] = dcn20_opp_create(ctx, i);
3889                 if (pool->base.opps[i] == NULL) {
3890                         BREAK_TO_DEBUGGER();
3891                         dm_error(
3892                                 "DC: failed to create output pixel processor!\n");
3893                         goto create_fail;
3894                 }
3895         }
3896
3897         for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
3898                 pool->base.timing_generators[i] = dcn20_timing_generator_create(
3899                                 ctx, i);
3900                 if (pool->base.timing_generators[i] == NULL) {
3901                         BREAK_TO_DEBUGGER();
3902                         dm_error("DC: failed to create tg!\n");
3903                         goto create_fail;
3904                 }
3905         }
3906
3907         pool->base.timing_generator_count = i;
3908
3909         pool->base.mpc = dcn20_mpc_create(ctx);
3910         if (pool->base.mpc == NULL) {
3911                 BREAK_TO_DEBUGGER();
3912                 dm_error("DC: failed to create mpc!\n");
3913                 goto create_fail;
3914         }
3915
3916         pool->base.hubbub = dcn20_hubbub_create(ctx);
3917         if (pool->base.hubbub == NULL) {
3918                 BREAK_TO_DEBUGGER();
3919                 dm_error("DC: failed to create hubbub!\n");
3920                 goto create_fail;
3921         }
3922
3923         for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
3924                 pool->base.dscs[i] = dcn20_dsc_create(ctx, i);
3925                 if (pool->base.dscs[i] == NULL) {
3926                         BREAK_TO_DEBUGGER();
3927                         dm_error("DC: failed to create display stream compressor %d!\n", i);
3928                         goto create_fail;
3929                 }
3930         }
3931
3932         if (!dcn20_dwbc_create(ctx, &pool->base)) {
3933                 BREAK_TO_DEBUGGER();
3934                 dm_error("DC: failed to create dwbc!\n");
3935                 goto create_fail;
3936         }
3937         if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
3938                 BREAK_TO_DEBUGGER();
3939                 dm_error("DC: failed to create mcif_wb!\n");
3940                 goto create_fail;
3941         }
3942
3943         if (!resource_construct(num_virtual_links, dc, &pool->base,
3944                         (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
3945                         &res_create_funcs : &res_create_maximus_funcs)))
3946                         goto create_fail;
3947
3948         dcn20_hw_sequencer_construct(dc);
3949
3950         // IF NV12, set PG function pointer to NULL. It's not that
3951         // PG isn't supported for NV12, it's that we don't want to
3952         // program the registers because that will cause more power
3953         // to be consumed. We could have created dcn20_init_hw to get
3954         // the same effect by checking ASIC rev, but there was a
3955         // request at some point to not check ASIC rev on hw sequencer.
3956         if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
3957                 dc->hwseq->funcs.enable_power_gating_plane = NULL;
3958
3959         dc->caps.max_planes =  pool->base.pipe_count;
3960
3961         for (i = 0; i < dc->caps.max_planes; ++i)
3962                 dc->caps.planes[i] = plane_cap;
3963
3964         dc->cap_funcs = cap_funcs;
3965
3966         if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
3967                 ddc_init_data.ctx = dc->ctx;
3968                 ddc_init_data.link = NULL;
3969                 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
3970                 ddc_init_data.id.enum_id = 0;
3971                 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
3972                 pool->base.oem_device = dal_ddc_service_create(&ddc_init_data);
3973         } else {
3974                 pool->base.oem_device = NULL;
3975         }
3976
3977         DC_FP_END();
3978         return true;
3979
3980 create_fail:
3981
3982         DC_FP_END();
3983         dcn20_resource_destruct(pool);
3984
3985         return false;
3986 }
3987
3988 struct resource_pool *dcn20_create_resource_pool(
3989                 const struct dc_init_data *init_data,
3990                 struct dc *dc)
3991 {
3992         struct dcn20_resource_pool *pool =
3993                 kzalloc(sizeof(struct dcn20_resource_pool), GFP_KERNEL);
3994
3995         if (!pool)
3996                 return NULL;
3997
3998         if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool))
3999                 return &pool->base;
4000
4001         BREAK_TO_DEBUGGER();
4002         kfree(pool);
4003         return NULL;
4004 }