2 * Copyright 2016 Advanced Micro Devices, Inc.
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5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
26 #ifndef __DC_HWSS_DCN20_H__
27 #define __DC_HWSS_DCN20_H__
29 #include "hw_sequencer_private.h"
31 bool dcn20_set_blend_lut(
32 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
33 bool dcn20_set_shaper_3dlut(
34 struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state);
35 void dcn20_program_front_end_for_ctx(
37 struct dc_state *context);
38 void dcn20_post_unlock_program_front_end(
40 struct dc_state *context);
41 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx);
42 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx);
43 bool dcn20_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
44 const struct dc_plane_state *plane_state);
45 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
46 const struct dc_stream_state *stream);
47 void dcn20_program_output_csc(struct dc *dc,
48 struct pipe_ctx *pipe_ctx,
49 enum dc_color_space colorspace,
52 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx);
53 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
54 struct dc_link_settings *link_settings);
55 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx);
56 void dcn20_blank_pixel_data(
58 struct pipe_ctx *pipe_ctx,
60 void dcn20_pipe_control_lock(
62 struct pipe_ctx *pipe,
64 void dcn20_pipe_control_lock_global(
66 struct pipe_ctx *pipe,
68 void dcn20_prepare_bandwidth(
70 struct dc_state *context);
71 void dcn20_optimize_bandwidth(
73 struct dc_state *context);
74 bool dcn20_update_bandwidth(
76 struct dc_state *context);
77 void dcn20_reset_hw_ctx_wrap(
79 struct dc_state *context);
80 enum dc_status dcn20_enable_stream_timing(
81 struct pipe_ctx *pipe_ctx,
82 struct dc_state *context,
84 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx);
85 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx);
86 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx);
87 void dcn20_init_blank(
89 struct timing_generator *tg);
90 void dcn20_disable_vga(
91 struct dce_hwseq *hws);
92 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx);
93 void dcn20_enable_power_gating_plane(
94 struct dce_hwseq *hws,
96 void dcn20_dpp_pg_control(
97 struct dce_hwseq *hws,
98 unsigned int dpp_inst,
100 void dcn20_hubp_pg_control(
101 struct dce_hwseq *hws,
102 unsigned int hubp_inst,
104 void dcn20_program_triple_buffer(
106 struct pipe_ctx *pipe_ctx,
107 bool enable_triple_buffer);
108 void dcn20_enable_writeback(
110 struct dc_writeback_info *wb_info,
111 struct dc_state *context);
112 void dcn20_disable_writeback(
114 unsigned int dwb_pipe_inst);
115 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx);
116 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx);
117 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx);
118 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx);
119 void dcn20_init_vm_ctx(
120 struct dce_hwseq *hws,
122 struct dc_virtual_addr_space_config *va_config,
124 void dcn20_set_flip_control_gsl(
125 struct pipe_ctx *pipe_ctx,
126 bool flip_immediate);
127 void dcn20_dsc_pg_control(
128 struct dce_hwseq *hws,
129 unsigned int dsc_inst,
131 void dcn20_fpga_init_hw(struct dc *dc);
132 bool dcn20_wait_for_blank_complete(
133 struct output_pixel_processor *opp);
134 void dcn20_dccg_init(struct dce_hwseq *hws);
135 int dcn20_init_sys_ctx(struct dce_hwseq *hws,
137 struct dc_phy_addr_space_config *pa_config);
139 #endif /* __DC_HWSS_DCN20_H__ */