drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include <linux/delay.h>
  26
  27 #include "dm_services.h"
  28 #include "basics/dc_common.h"
  29 #include "dm_helpers.h"
  30 #include "core_types.h"
  31 #include "resource.h"
  32 #include "dcn20_resource.h"
  33 #include "dcn20_hwseq.h"
  34 #include "dce/dce_hwseq.h"
  35 #include "dcn20_dsc.h"
  36 #include "dcn20_optc.h"
  37 #include "abm.h"
  38 #include "clk_mgr.h"
  39 #include "dmcu.h"
  40 #include "hubp.h"
  41 #include "timing_generator.h"
  42 #include "opp.h"
  43 #include "ipp.h"
  44 #include "mpc.h"
  45 #include "mcif_wb.h"
  46 #include "dchubbub.h"
  47 #include "reg_helper.h"
  48 #include "dcn10/dcn10_cm_common.h"
  49 #include "dc_link_dp.h"
  50 #include "vm_helper.h"
  51 #include "dccg.h"
  52
  53 #define DC_LOGGER_INIT(logger)
  54
  55 #define CTX \
  56         hws->ctx
  57 #define REG(reg)\
  58         hws->regs->reg
  59
  60 #undef FN
  61 #define FN(reg_name, field_name) \
  62         hws->shifts->field_name, hws->masks->field_name
  63
  64 static int find_free_gsl_group(const struct dc *dc)
  65 {
  66         if (dc->res_pool->gsl_groups.gsl_0 == 0)
  67                 return 1;
  68         if (dc->res_pool->gsl_groups.gsl_1 == 0)
  69                 return 2;
  70         if (dc->res_pool->gsl_groups.gsl_2 == 0)
  71                 return 3;
  72
  73         return 0;
  74 }
  75
  76 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock)
  77  * This is only used to lock pipes in pipe splitting case with immediate flip
  78  * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate,
  79  * so we get tearing with freesync since we cannot flip multiple pipes
  80  * atomically.
  81  * We use GSL for this:
  82  * - immediate flip: find first available GSL group if not already assigned
  83  *                   program gsl with that group, set current OTG as master
  84  *                   and always us 0x4 = AND of flip_ready from all pipes
  85  * - vsync flip: disable GSL if used
  86  *
  87  * Groups in stream_res are stored as +1 from HW registers, i.e.
  88  * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
  89  * Using a magic value like -1 would require tracking all inits/resets
  90  */
  91 static void dcn20_setup_gsl_group_as_lock(
  92                 const struct dc *dc,
  93                 struct pipe_ctx *pipe_ctx,
  94                 bool enable)
  95 {
  96         struct gsl_params gsl;
  97         int group_idx;
  98
  99         memset(&gsl, 0, sizeof(struct gsl_params));
 100
 101         if (enable) {
 102                 /* return if group already assigned since GSL was set up
 103                  * for vsync flip, we would unassign so it can't be "left over"
 104                  */
 105                 if (pipe_ctx->stream_res.gsl_group > 0)
 106                         return;
 107
 108                 group_idx = find_free_gsl_group(dc);
 109                 ASSERT(group_idx != 0);
 110                 pipe_ctx->stream_res.gsl_group = group_idx;
 111
 112                 /* set gsl group reg field and mark resource used */
 113                 switch (group_idx) {
 114                 case 1:
 115                         gsl.gsl0_en = 1;
 116                         dc->res_pool->gsl_groups.gsl_0 = 1;
 117                         break;
 118                 case 2:
 119                         gsl.gsl1_en = 1;
 120                         dc->res_pool->gsl_groups.gsl_1 = 1;
 121                         break;
 122                 case 3:
 123                         gsl.gsl2_en = 1;
 124                         dc->res_pool->gsl_groups.gsl_2 = 1;
 125                         break;
 126                 default:
 127                         BREAK_TO_DEBUGGER();
 128                         return; // invalid case
 129                 }
 130                 gsl.gsl_master_en = 1;
 131         } else {
 132                 group_idx = pipe_ctx->stream_res.gsl_group;
 133                 if (group_idx == 0)
 134                         return; // if not in use, just return
 135
 136                 pipe_ctx->stream_res.gsl_group = 0;
 137
 138                 /* unset gsl group reg field and mark resource free */
 139                 switch (group_idx) {
 140                 case 1:
 141                         gsl.gsl0_en = 0;
 142                         dc->res_pool->gsl_groups.gsl_0 = 0;
 143                         break;
 144                 case 2:
 145                         gsl.gsl1_en = 0;
 146                         dc->res_pool->gsl_groups.gsl_1 = 0;
 147                         break;
 148                 case 3:
 149                         gsl.gsl2_en = 0;
 150                         dc->res_pool->gsl_groups.gsl_2 = 0;
 151                         break;
 152                 default:
 153                         BREAK_TO_DEBUGGER();
 154                         return;
 155                 }
 156                 gsl.gsl_master_en = 0;
 157         }
 158
 159         /* at this point we want to program whether it's to enable or disable */
 160         if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
 161                 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
 162                 pipe_ctx->stream_res.tg->funcs->set_gsl(
 163                         pipe_ctx->stream_res.tg,
 164                         &gsl);
 165
 166                 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(
 167                         pipe_ctx->stream_res.tg, group_idx,     enable ? 4 : 0);
 168         } else
 169                 BREAK_TO_DEBUGGER();
 170 }
 171
 172 void dcn20_set_flip_control_gsl(
 173                 struct pipe_ctx *pipe_ctx,
 174                 bool flip_immediate)
 175 {
 176         if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)
 177                 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(
 178                                 pipe_ctx->plane_res.hubp, flip_immediate);
 179
 180 }
 181
 182 void dcn20_enable_power_gating_plane(
 183         struct dce_hwseq *hws,
 184         bool enable)
 185 {
 186         bool force_on = true; /* disable power gating */
 187
 188         if (enable)
 189                 force_on = false;
 190
 191         /* DCHUBP0/1/2/3/4/5 */
 192         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
 193         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
 194         REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
 195         REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
 196         if (REG(DOMAIN8_PG_CONFIG))
 197                 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
 198         if (REG(DOMAIN10_PG_CONFIG))
 199                 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
 200
 201         /* DPP0/1/2/3/4/5 */
 202         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
 203         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
 204         REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
 205         REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
 206         if (REG(DOMAIN9_PG_CONFIG))
 207                 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
 208         if (REG(DOMAIN11_PG_CONFIG))
 209                 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
 210
 211         /* DCS0/1/2/3/4/5 */
 212         REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on);
 213         REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on);
 214         REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on);
 215         if (REG(DOMAIN19_PG_CONFIG))
 216                 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on);
 217         if (REG(DOMAIN20_PG_CONFIG))
 218                 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on);
 219         if (REG(DOMAIN21_PG_CONFIG))
 220                 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on);
 221 }
 222
 223 void dcn20_dccg_init(struct dce_hwseq *hws)
 224 {
 225         /*
 226          * set MICROSECOND_TIME_BASE_DIV
 227          * 100Mhz refclk -> 0x120264
 228          * 27Mhz refclk -> 0x12021b
 229          * 48Mhz refclk -> 0x120230
 230          *
 231          */
 232         REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264);
 233
 234         /*
 235          * set MILLISECOND_TIME_BASE_DIV
 236          * 100Mhz refclk -> 0x1186a0
 237          * 27Mhz refclk -> 0x106978
 238          * 48Mhz refclk -> 0x10bb80
 239          *
 240          */
 241         REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
 242
 243         /* This value is dependent on the hardware pipeline delay so set once per SOC */
 244         REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c);
 245 }
 246
 247 void dcn20_disable_vga(
 248         struct dce_hwseq *hws)
 249 {
 250         REG_WRITE(D1VGA_CONTROL, 0);
 251         REG_WRITE(D2VGA_CONTROL, 0);
 252         REG_WRITE(D3VGA_CONTROL, 0);
 253         REG_WRITE(D4VGA_CONTROL, 0);
 254         REG_WRITE(D5VGA_CONTROL, 0);
 255         REG_WRITE(D6VGA_CONTROL, 0);
 256 }
 257
 258 void dcn20_program_triple_buffer(
 259         const struct dc *dc,
 260         struct pipe_ctx *pipe_ctx,
 261         bool enable_triple_buffer)
 262 {
 263         if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {
 264                 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(
 265                         pipe_ctx->plane_res.hubp,
 266                         enable_triple_buffer);
 267         }
 268 }
 269
 270 /* Blank pixel data during initialization */
 271 void dcn20_init_blank(
 272                 struct dc *dc,
 273                 struct timing_generator *tg)
 274 {
 275         struct dce_hwseq *hws = dc->hwseq;
 276         enum dc_color_space color_space;
 277         struct tg_color black_color = {0};
 278         struct output_pixel_processor *opp = NULL;
 279         struct output_pixel_processor *bottom_opp = NULL;
 280         uint32_t num_opps, opp_id_src0, opp_id_src1;
 281         uint32_t otg_active_width, otg_active_height;
 282
 283         /* program opp dpg blank color */
 284         color_space = COLOR_SPACE_SRGB;
 285         color_space_to_black_color(dc, color_space, &black_color);
 286
 287         /* get the OTG active size */
 288         tg->funcs->get_otg_active_size(tg,
 289                         &otg_active_width,
 290                         &otg_active_height);
 291
 292         /* get the OPTC source */
 293         tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
 294         ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp);
 295         opp = dc->res_pool->opps[opp_id_src0];
 296
 297         if (num_opps == 2) {
 298                 otg_active_width = otg_active_width / 2;
 299                 ASSERT(opp_id_src1 < dc->res_pool->res_cap->num_opp);
 300                 bottom_opp = dc->res_pool->opps[opp_id_src1];
 301         }
 302
 303         opp->funcs->opp_set_disp_pattern_generator(
 304                         opp,
 305                         CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
 306                         CONTROLLER_DP_COLOR_SPACE_UDEFINED,
 307                         COLOR_DEPTH_UNDEFINED,
 308                         &black_color,
 309                         otg_active_width,
 310                         otg_active_height);
 311
 312         if (num_opps == 2) {
 313                 bottom_opp->funcs->opp_set_disp_pattern_generator(
 314                                 bottom_opp,
 315                                 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
 316                                 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
 317                                 COLOR_DEPTH_UNDEFINED,
 318                                 &black_color,
 319                                 otg_active_width,
 320                                 otg_active_height);
 321         }
 322
 323         hws->funcs.wait_for_blank_complete(opp);
 324 }
 325
 326 void dcn20_dsc_pg_control(
 327                 struct dce_hwseq *hws,
 328                 unsigned int dsc_inst,
 329                 bool power_on)
 330 {
 331         uint32_t power_gate = power_on ? 0 : 1;
 332         uint32_t pwr_status = power_on ? 0 : 2;
 333         uint32_t org_ip_request_cntl = 0;
 334
 335         if (hws->ctx->dc->debug.disable_dsc_power_gate)
 336                 return;
 337
 338         if (REG(DOMAIN16_PG_CONFIG) == 0)
 339                 return;
 340
 341         REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
 342         if (org_ip_request_cntl == 0)
 343                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
 344
 345         switch (dsc_inst) {
 346         case 0: /* DSC0 */
 347                 REG_UPDATE(DOMAIN16_PG_CONFIG,
 348                                 DOMAIN16_POWER_GATE, power_gate);
 349
 350                 REG_WAIT(DOMAIN16_PG_STATUS,
 351                                 DOMAIN16_PGFSM_PWR_STATUS, pwr_status,
 352                                 1, 1000);
 353                 break;
 354         case 1: /* DSC1 */
 355                 REG_UPDATE(DOMAIN17_PG_CONFIG,
 356                                 DOMAIN17_POWER_GATE, power_gate);
 357
 358                 REG_WAIT(DOMAIN17_PG_STATUS,
 359                                 DOMAIN17_PGFSM_PWR_STATUS, pwr_status,
 360                                 1, 1000);
 361                 break;
 362         case 2: /* DSC2 */
 363                 REG_UPDATE(DOMAIN18_PG_CONFIG,
 364                                 DOMAIN18_POWER_GATE, power_gate);
 365
 366                 REG_WAIT(DOMAIN18_PG_STATUS,
 367                                 DOMAIN18_PGFSM_PWR_STATUS, pwr_status,
 368                                 1, 1000);
 369                 break;
 370         case 3: /* DSC3 */
 371                 REG_UPDATE(DOMAIN19_PG_CONFIG,
 372                                 DOMAIN19_POWER_GATE, power_gate);
 373
 374                 REG_WAIT(DOMAIN19_PG_STATUS,
 375                                 DOMAIN19_PGFSM_PWR_STATUS, pwr_status,
 376                                 1, 1000);
 377                 break;
 378         case 4: /* DSC4 */
 379                 REG_UPDATE(DOMAIN20_PG_CONFIG,
 380                                 DOMAIN20_POWER_GATE, power_gate);
 381
 382                 REG_WAIT(DOMAIN20_PG_STATUS,
 383                                 DOMAIN20_PGFSM_PWR_STATUS, pwr_status,
 384                                 1, 1000);
 385                 break;
 386         case 5: /* DSC5 */
 387                 REG_UPDATE(DOMAIN21_PG_CONFIG,
 388                                 DOMAIN21_POWER_GATE, power_gate);
 389
 390                 REG_WAIT(DOMAIN21_PG_STATUS,
 391                                 DOMAIN21_PGFSM_PWR_STATUS, pwr_status,
 392                                 1, 1000);
 393                 break;
 394         default:
 395                 BREAK_TO_DEBUGGER();
 396                 break;
 397         }
 398
 399         if (org_ip_request_cntl == 0)
 400                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
 401 }
 402
 403 void dcn20_dpp_pg_control(
 404                 struct dce_hwseq *hws,
 405                 unsigned int dpp_inst,
 406                 bool power_on)
 407 {
 408         uint32_t power_gate = power_on ? 0 : 1;
 409         uint32_t pwr_status = power_on ? 0 : 2;
 410
 411         if (hws->ctx->dc->debug.disable_dpp_power_gate)
 412                 return;
 413         if (REG(DOMAIN1_PG_CONFIG) == 0)
 414                 return;
 415
 416         switch (dpp_inst) {
 417         case 0: /* DPP0 */
 418                 REG_UPDATE(DOMAIN1_PG_CONFIG,
 419                                 DOMAIN1_POWER_GATE, power_gate);
 420
 421                 REG_WAIT(DOMAIN1_PG_STATUS,
 422                                 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
 423                                 1, 1000);
 424                 break;
 425         case 1: /* DPP1 */
 426                 REG_UPDATE(DOMAIN3_PG_CONFIG,
 427                                 DOMAIN3_POWER_GATE, power_gate);
 428
 429                 REG_WAIT(DOMAIN3_PG_STATUS,
 430                                 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
 431                                 1, 1000);
 432                 break;
 433         case 2: /* DPP2 */
 434                 REG_UPDATE(DOMAIN5_PG_CONFIG,
 435                                 DOMAIN5_POWER_GATE, power_gate);
 436
 437                 REG_WAIT(DOMAIN5_PG_STATUS,
 438                                 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
 439                                 1, 1000);
 440                 break;
 441         case 3: /* DPP3 */
 442                 REG_UPDATE(DOMAIN7_PG_CONFIG,
 443                                 DOMAIN7_POWER_GATE, power_gate);
 444
 445                 REG_WAIT(DOMAIN7_PG_STATUS,
 446                                 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
 447                                 1, 1000);
 448                 break;
 449         case 4: /* DPP4 */
 450                 REG_UPDATE(DOMAIN9_PG_CONFIG,
 451                                 DOMAIN9_POWER_GATE, power_gate);
 452
 453                 REG_WAIT(DOMAIN9_PG_STATUS,
 454                                 DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
 455                                 1, 1000);
 456                 break;
 457         case 5: /* DPP5 */
 458                 /*
 459                  * Do not power gate DPP5, should be left at HW default, power on permanently.
 460                  * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
 461                  * reset.
 462                  * REG_UPDATE(DOMAIN11_PG_CONFIG,
 463                  *              DOMAIN11_POWER_GATE, power_gate);
 464                  *
 465                  * REG_WAIT(DOMAIN11_PG_STATUS,
 466                  *              DOMAIN11_PGFSM_PWR_STATUS, pwr_status,
 467                  *              1, 1000);
 468                  */
 469                 break;
 470         default:
 471                 BREAK_TO_DEBUGGER();
 472                 break;
 473         }
 474 }
 475
 476
 477 void dcn20_hubp_pg_control(
 478                 struct dce_hwseq *hws,
 479                 unsigned int hubp_inst,
 480                 bool power_on)
 481 {
 482         uint32_t power_gate = power_on ? 0 : 1;
 483         uint32_t pwr_status = power_on ? 0 : 2;
 484
 485         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 486                 return;
 487         if (REG(DOMAIN0_PG_CONFIG) == 0)
 488                 return;
 489
 490         switch (hubp_inst) {
 491         case 0: /* DCHUBP0 */
 492                 REG_UPDATE(DOMAIN0_PG_CONFIG,
 493                                 DOMAIN0_POWER_GATE, power_gate);
 494
 495                 REG_WAIT(DOMAIN0_PG_STATUS,
 496                                 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
 497                                 1, 1000);
 498                 break;
 499         case 1: /* DCHUBP1 */
 500                 REG_UPDATE(DOMAIN2_PG_CONFIG,
 501                                 DOMAIN2_POWER_GATE, power_gate);
 502
 503                 REG_WAIT(DOMAIN2_PG_STATUS,
 504                                 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
 505                                 1, 1000);
 506                 break;
 507         case 2: /* DCHUBP2 */
 508                 REG_UPDATE(DOMAIN4_PG_CONFIG,
 509                                 DOMAIN4_POWER_GATE, power_gate);
 510
 511                 REG_WAIT(DOMAIN4_PG_STATUS,
 512                                 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
 513                                 1, 1000);
 514                 break;
 515         case 3: /* DCHUBP3 */
 516                 REG_UPDATE(DOMAIN6_PG_CONFIG,
 517                                 DOMAIN6_POWER_GATE, power_gate);
 518
 519                 REG_WAIT(DOMAIN6_PG_STATUS,
 520                                 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
 521                                 1, 1000);
 522                 break;
 523         case 4: /* DCHUBP4 */
 524                 REG_UPDATE(DOMAIN8_PG_CONFIG,
 525                                 DOMAIN8_POWER_GATE, power_gate);
 526
 527                 REG_WAIT(DOMAIN8_PG_STATUS,
 528                                 DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
 529                                 1, 1000);
 530                 break;
 531         case 5: /* DCHUBP5 */
 532                 /*
 533                  * Do not power gate DCHUB5, should be left at HW default, power on permanently.
 534                  * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
 535                  * reset.
 536                  * REG_UPDATE(DOMAIN10_PG_CONFIG,
 537                  *              DOMAIN10_POWER_GATE, power_gate);
 538                  *
 539                  * REG_WAIT(DOMAIN10_PG_STATUS,
 540                  *              DOMAIN10_PGFSM_PWR_STATUS, pwr_status,
 541                  *              1, 1000);
 542                  */
 543                 break;
 544         default:
 545                 BREAK_TO_DEBUGGER();
 546                 break;
 547         }
 548 }
 549
 550
 551 /* disable HW used by plane.
 552  * note:  cannot disable until disconnect is complete
 553  */
 554 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
 555 {
 556         struct dce_hwseq *hws = dc->hwseq;
 557         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 558         struct dpp *dpp = pipe_ctx->plane_res.dpp;
 559
 560         dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
 561
 562         /* In flip immediate with pipe splitting case GSL is used for
 563          * synchronization so we must disable it when the plane is disabled.
 564          */
 565         if (pipe_ctx->stream_res.gsl_group != 0)
 566                 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);
 567
 568         dc->hwss.set_flip_control_gsl(pipe_ctx, false);
 569
 570         hubp->funcs->hubp_clk_cntl(hubp, false);
 571
 572         dpp->funcs->dpp_dppclk_control(dpp, false, false);
 573
 574         hubp->power_gated = true;
 575
 576         hws->funcs.plane_atomic_power_down(dc,
 577                         pipe_ctx->plane_res.dpp,
 578                         pipe_ctx->plane_res.hubp);
 579
 580         pipe_ctx->stream = NULL;
 581         memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
 582         memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
 583         pipe_ctx->top_pipe = NULL;
 584         pipe_ctx->bottom_pipe = NULL;
 585         pipe_ctx->plane_state = NULL;
 586 }
 587
 588
 589 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
 590 {
 591         DC_LOGGER_INIT(dc->ctx->logger);
 592
 593         if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
 594                 return;
 595
 596         dcn20_plane_atomic_disable(dc, pipe_ctx);
 597
 598         DC_LOG_DC("Power down front end %d\n",
 599                                         pipe_ctx->pipe_idx);
 600 }
 601
 602 enum dc_status dcn20_enable_stream_timing(
 603                 struct pipe_ctx *pipe_ctx,
 604                 struct dc_state *context,
 605                 struct dc *dc)
 606 {
 607         struct dce_hwseq *hws = dc->hwseq;
 608         struct dc_stream_state *stream = pipe_ctx->stream;
 609         struct drr_params params = {0};
 610         unsigned int event_triggers = 0;
 611         struct pipe_ctx *odm_pipe;
 612         int opp_cnt = 1;
 613         int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
 614
 615         /* by upper caller loop, pipe0 is parent pipe and be called first.
 616          * back end is set up by for pipe0. Other children pipe share back end
 617          * with pipe 0. No program is needed.
 618          */
 619         if (pipe_ctx->top_pipe != NULL)
 620                 return DC_OK;
 621
 622         /* TODO check if timing_changed, disable stream if timing changed */
 623
 624         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 625                 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
 626                 opp_cnt++;
 627         }
 628
 629         if (opp_cnt > 1)
 630                 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
 631                                 pipe_ctx->stream_res.tg,
 632                                 opp_inst, opp_cnt,
 633                                 &pipe_ctx->stream->timing);
 634
 635         /* HW program guide assume display already disable
 636          * by unplug sequence. OTG assume stop.
 637          */
 638         pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
 639
 640         if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
 641                         pipe_ctx->clock_source,
 642                         &pipe_ctx->stream_res.pix_clk_params,
 643                         &pipe_ctx->pll_settings)) {
 644                 BREAK_TO_DEBUGGER();
 645                 return DC_ERROR_UNEXPECTED;
 646         }
 647
 648         pipe_ctx->stream_res.tg->funcs->program_timing(
 649                         pipe_ctx->stream_res.tg,
 650                         &stream->timing,
 651                         pipe_ctx->pipe_dlg_param.vready_offset,
 652                         pipe_ctx->pipe_dlg_param.vstartup_start,
 653                         pipe_ctx->pipe_dlg_param.vupdate_offset,
 654                         pipe_ctx->pipe_dlg_param.vupdate_width,
 655                         pipe_ctx->stream->signal,
 656                         true);
 657
 658         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
 659                 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
 660                                 odm_pipe->stream_res.opp,
 661                                 true);
 662
 663         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
 664                         pipe_ctx->stream_res.opp,
 665                         true);
 666
 667         hws->funcs.blank_pixel_data(dc, pipe_ctx, true);
 668
 669         /* VTG is  within DCHUB command block. DCFCLK is always on */
 670         if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
 671                 BREAK_TO_DEBUGGER();
 672                 return DC_ERROR_UNEXPECTED;
 673         }
 674
 675         hws->funcs.wait_for_blank_complete(pipe_ctx->stream_res.opp);
 676
 677         params.vertical_total_min = stream->adjust.v_total_min;
 678         params.vertical_total_max = stream->adjust.v_total_max;
 679         params.vertical_total_mid = stream->adjust.v_total_mid;
 680         params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num;
 681         if (pipe_ctx->stream_res.tg->funcs->set_drr)
 682                 pipe_ctx->stream_res.tg->funcs->set_drr(
 683                         pipe_ctx->stream_res.tg, &params);
 684
 685         // DRR should set trigger event to monitor surface update event
 686         if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
 687                 event_triggers = 0x80;
 688         /* Event triggers and num frames initialized for DRR, but can be
 689          * later updated for PSR use. Note DRR trigger events are generated
 690          * regardless of whether num frames met.
 691          */
 692         if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
 693                 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
 694                                 pipe_ctx->stream_res.tg, event_triggers, 2);
 695
 696         /* TODO program crtc source select for non-virtual signal*/
 697         /* TODO program FMT */
 698         /* TODO setup link_enc */
 699         /* TODO set stream attributes */
 700         /* TODO program audio */
 701         /* TODO enable stream if timing changed */
 702         /* TODO unblank stream if DP */
 703
 704         return DC_OK;
 705 }
 706
 707 void dcn20_program_output_csc(struct dc *dc,
 708                 struct pipe_ctx *pipe_ctx,
 709                 enum dc_color_space colorspace,
 710                 uint16_t *matrix,
 711                 int opp_id)
 712 {
 713         struct mpc *mpc = dc->res_pool->mpc;
 714         enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
 715         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 716
 717         if (mpc->funcs->power_on_mpc_mem_pwr)
 718                 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
 719
 720         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
 721                 if (mpc->funcs->set_output_csc != NULL)
 722                         mpc->funcs->set_output_csc(mpc,
 723                                         opp_id,
 724                                         matrix,
 725                                         ocsc_mode);
 726         } else {
 727                 if (mpc->funcs->set_ocsc_default != NULL)
 728                         mpc->funcs->set_ocsc_default(mpc,
 729                                         opp_id,
 730                                         colorspace,
 731                                         ocsc_mode);
 732         }
 733 }
 734
 735 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
 736                                 const struct dc_stream_state *stream)
 737 {
 738         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 739         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
 740         struct pwl_params *params = NULL;
 741         /*
 742          * program OGAM only for the top pipe
 743          * if there is a pipe split then fix diagnostic is required:
 744          * how to pass OGAM parameter for stream.
 745          * if programming for all pipes is required then remove condition
 746          * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic.
 747          */
 748         if (mpc->funcs->power_on_mpc_mem_pwr)
 749                 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
 750         if (pipe_ctx->top_pipe == NULL
 751                         && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
 752                 if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
 753                         params = &stream->out_transfer_func->pwl;
 754                 else if (pipe_ctx->stream->out_transfer_func->type ==
 755                         TF_TYPE_DISTRIBUTED_POINTS &&
 756                         cm_helper_translate_curve_to_hw_format(
 757                         stream->out_transfer_func,
 758                         &mpc->blender_params, false))
 759                         params = &mpc->blender_params;
 760                 /*
 761                  * there is no ROM
 762                  */
 763                 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
 764                         BREAK_TO_DEBUGGER();
 765         }
 766         /*
 767          * if above if is not executed then 'params' equal to 0 and set in bypass
 768          */
 769         mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
 770
 771         return true;
 772 }
 773
 774 bool dcn20_set_blend_lut(
 775         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
 776 {
 777         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 778         bool result = true;
 779         struct pwl_params *blend_lut = NULL;
 780
 781         if (plane_state->blend_tf) {
 782                 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
 783                         blend_lut = &plane_state->blend_tf->pwl;
 784                 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
 785                         cm_helper_translate_curve_to_hw_format(
 786                                         plane_state->blend_tf,
 787                                         &dpp_base->regamma_params, false);
 788                         blend_lut = &dpp_base->regamma_params;
 789                 }
 790         }
 791         result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
 792
 793         return result;
 794 }
 795
 796 bool dcn20_set_shaper_3dlut(
 797         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
 798 {
 799         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 800         bool result = true;
 801         struct pwl_params *shaper_lut = NULL;
 802
 803         if (plane_state->in_shaper_func) {
 804                 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
 805                         shaper_lut = &plane_state->in_shaper_func->pwl;
 806                 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
 807                         cm_helper_translate_curve_to_hw_format(
 808                                         plane_state->in_shaper_func,
 809                                         &dpp_base->shaper_params, true);
 810                         shaper_lut = &dpp_base->shaper_params;
 811                 }
 812         }
 813
 814         result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut);
 815         if (plane_state->lut3d_func &&
 816                 plane_state->lut3d_func->state.bits.initialized == 1)
 817                 result = dpp_base->funcs->dpp_program_3dlut(dpp_base,
 818                                                                 &plane_state->lut3d_func->lut_3d);
 819         else
 820                 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL);
 821
 822         return result;
 823 }
 824
 825 bool dcn20_set_input_transfer_func(struct dc *dc,
 826                                 struct pipe_ctx *pipe_ctx,
 827                                 const struct dc_plane_state *plane_state)
 828 {
 829         struct dce_hwseq *hws = dc->hwseq;
 830         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 831         const struct dc_transfer_func *tf = NULL;
 832         bool result = true;
 833         bool use_degamma_ram = false;
 834
 835         if (dpp_base == NULL || plane_state == NULL)
 836                 return false;
 837
 838         hws->funcs.set_shaper_3dlut(pipe_ctx, plane_state);
 839         hws->funcs.set_blend_lut(pipe_ctx, plane_state);
 840
 841         if (plane_state->in_transfer_func)
 842                 tf = plane_state->in_transfer_func;
 843
 844
 845         if (tf == NULL) {
 846                 dpp_base->funcs->dpp_set_degamma(dpp_base,
 847                                 IPP_DEGAMMA_MODE_BYPASS);
 848                 return true;
 849         }
 850
 851         if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS)
 852                 use_degamma_ram = true;
 853
 854         if (use_degamma_ram == true) {
 855                 if (tf->type == TF_TYPE_HWPWL)
 856                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
 857                                         &tf->pwl);
 858                 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
 859                         cm_helper_translate_curve_to_degamma_hw_format(tf,
 860                                         &dpp_base->degamma_params);
 861                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
 862                                 &dpp_base->degamma_params);
 863                 }
 864                 return true;
 865         }
 866         /* handle here the optimized cases when de-gamma ROM could be used.
 867          *
 868          */
 869         if (tf->type == TF_TYPE_PREDEFINED) {
 870                 switch (tf->tf) {
 871                 case TRANSFER_FUNCTION_SRGB:
 872                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 873                                         IPP_DEGAMMA_MODE_HW_sRGB);
 874                         break;
 875                 case TRANSFER_FUNCTION_BT709:
 876                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 877                                         IPP_DEGAMMA_MODE_HW_xvYCC);
 878                         break;
 879                 case TRANSFER_FUNCTION_LINEAR:
 880                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 881                                         IPP_DEGAMMA_MODE_BYPASS);
 882                         break;
 883                 case TRANSFER_FUNCTION_PQ:
 884                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_USER_PWL);
 885                         cm_helper_translate_curve_to_degamma_hw_format(tf, &dpp_base->degamma_params);
 886                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base, &dpp_base->degamma_params);
 887                         result = true;
 888                         break;
 889                 default:
 890                         result = false;
 891                         break;
 892                 }
 893         } else if (tf->type == TF_TYPE_BYPASS)
 894                 dpp_base->funcs->dpp_set_degamma(dpp_base,
 895                                 IPP_DEGAMMA_MODE_BYPASS);
 896         else {
 897                 /*
 898                  * if we are here, we did not handle correctly.
 899                  * fix is required for this use case
 900                  */
 901                 BREAK_TO_DEBUGGER();
 902                 dpp_base->funcs->dpp_set_degamma(dpp_base,
 903                                 IPP_DEGAMMA_MODE_BYPASS);
 904         }
 905
 906         return result;
 907 }
 908
 909 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
 910 {
 911         struct pipe_ctx *odm_pipe;
 912         int opp_cnt = 1;
 913         int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
 914
 915         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 916                 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
 917                 opp_cnt++;
 918         }
 919
 920         if (opp_cnt > 1)
 921                 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
 922                                 pipe_ctx->stream_res.tg,
 923                                 opp_inst, opp_cnt,
 924                                 &pipe_ctx->stream->timing);
 925         else
 926                 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
 927                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
 928 }
 929
 930 void dcn20_blank_pixel_data(
 931                 struct dc *dc,
 932                 struct pipe_ctx *pipe_ctx,
 933                 bool blank)
 934 {
 935         struct tg_color black_color = {0};
 936         struct stream_resource *stream_res = &pipe_ctx->stream_res;
 937         struct dc_stream_state *stream = pipe_ctx->stream;
 938         enum dc_color_space color_space = stream->output_color_space;
 939         enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
 940         enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
 941         struct pipe_ctx *odm_pipe;
 942         int odm_cnt = 1;
 943
 944         int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
 945         int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
 946
 947         if (stream->link->test_pattern_enabled)
 948                 return;
 949
 950         /* get opp dpg blank color */
 951         color_space_to_black_color(dc, color_space, &black_color);
 952
 953         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
 954                 odm_cnt++;
 955
 956         width = width / odm_cnt;
 957
 958         if (blank) {
 959                 if (stream_res->abm)
 960                         stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm);
 961
 962                 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {
 963                         test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
 964                         test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
 965                 }
 966         } else {
 967                 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
 968         }
 969
 970         stream_res->opp->funcs->opp_set_disp_pattern_generator(
 971                         stream_res->opp,
 972                         test_pattern,
 973                         test_pattern_color_space,
 974                         stream->timing.display_color_depth,
 975                         &black_color,
 976                         width,
 977                         height);
 978
 979         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 980                 odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator(
 981                                 odm_pipe->stream_res.opp,
 982                                 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ?
 983                                                 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
 984                                 test_pattern_color_space,
 985                                 stream->timing.display_color_depth,
 986                                 &black_color,
 987                                 width,
 988                                 height);
 989         }
 990
 991         if (!blank)
 992                 if (stream_res->abm) {
 993                         stream_res->abm->funcs->set_pipe(stream_res->abm, stream_res->tg->inst + 1);
 994                         stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
 995                 }
 996 }
 997
 998
 999 static void dcn20_power_on_plane(
1000         struct dce_hwseq *hws,
1001         struct pipe_ctx *pipe_ctx)
1002 {
1003         DC_LOGGER_INIT(hws->ctx->logger);
1004         if (REG(DC_IP_REQUEST_CNTL)) {
1005                 REG_SET(DC_IP_REQUEST_CNTL, 0,
1006                                 IP_REQUEST_EN, 1);
1007                 dcn20_dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);
1008                 dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);
1009                 REG_SET(DC_IP_REQUEST_CNTL, 0,
1010                                 IP_REQUEST_EN, 0);
1011                 DC_LOG_DEBUG(
1012                                 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);
1013         }
1014 }
1015
1016 void dcn20_enable_plane(
1017         struct dc *dc,
1018         struct pipe_ctx *pipe_ctx,
1019         struct dc_state *context)
1020 {
1021         //if (dc->debug.sanity_checks) {
1022         //      dcn10_verify_allow_pstate_change_high(dc);
1023         //}
1024         dcn20_power_on_plane(dc->hwseq, pipe_ctx);
1025
1026         /* enable DCFCLK current DCHUB */
1027         pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1028
1029         /* initialize HUBP on power up */
1030         pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);
1031
1032         /* make sure OPP_PIPE_CLOCK_EN = 1 */
1033         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1034                         pipe_ctx->stream_res.opp,
1035                         true);
1036
1037 /* TODO: enable/disable in dm as per update type.
1038         if (plane_state) {
1039                 DC_LOG_DC(dc->ctx->logger,
1040                                 "Pipe:%d 0x%x: addr hi:0x%x, "
1041                                 "addr low:0x%x, "
1042                                 "src: %d, %d, %d,"
1043                                 " %d; dst: %d, %d, %d, %d;\n",
1044                                 pipe_ctx->pipe_idx,
1045                                 plane_state,
1046                                 plane_state->address.grph.addr.high_part,
1047                                 plane_state->address.grph.addr.low_part,
1048                                 plane_state->src_rect.x,
1049                                 plane_state->src_rect.y,
1050                                 plane_state->src_rect.width,
1051                                 plane_state->src_rect.height,
1052                                 plane_state->dst_rect.x,
1053                                 plane_state->dst_rect.y,
1054                                 plane_state->dst_rect.width,
1055                                 plane_state->dst_rect.height);
1056
1057                 DC_LOG_DC(dc->ctx->logger,
1058                                 "Pipe %d: width, height, x, y         format:%d\n"
1059                                 "viewport:%d, %d, %d, %d\n"
1060                                 "recout:  %d, %d, %d, %d\n",
1061                                 pipe_ctx->pipe_idx,
1062                                 plane_state->format,
1063                                 pipe_ctx->plane_res.scl_data.viewport.width,
1064                                 pipe_ctx->plane_res.scl_data.viewport.height,
1065                                 pipe_ctx->plane_res.scl_data.viewport.x,
1066                                 pipe_ctx->plane_res.scl_data.viewport.y,
1067                                 pipe_ctx->plane_res.scl_data.recout.width,
1068                                 pipe_ctx->plane_res.scl_data.recout.height,
1069                                 pipe_ctx->plane_res.scl_data.recout.x,
1070                                 pipe_ctx->plane_res.scl_data.recout.y);
1071                 print_rq_dlg_ttu(dc, pipe_ctx);
1072         }
1073 */
1074         if (dc->vm_pa_config.valid) {
1075                 struct vm_system_aperture_param apt;
1076
1077                 apt.sys_default.quad_part = 0;
1078
1079                 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr;
1080                 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr;
1081
1082                 // Program system aperture settings
1083                 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);
1084         }
1085
1086 //      if (dc->debug.sanity_checks) {
1087 //              dcn10_verify_allow_pstate_change_high(dc);
1088 //      }
1089 }
1090
1091
1092 void dcn20_pipe_control_lock_global(
1093                 struct dc *dc,
1094                 struct pipe_ctx *pipe,
1095                 bool lock)
1096 {
1097         if (lock) {
1098                 pipe->stream_res.tg->funcs->lock_doublebuffer_enable(
1099                                 pipe->stream_res.tg);
1100                 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1101         } else {
1102                 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1103                 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,
1104                                 CRTC_STATE_VACTIVE);
1105                 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,
1106                                 CRTC_STATE_VBLANK);
1107                 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,
1108                                 CRTC_STATE_VACTIVE);
1109                 pipe->stream_res.tg->funcs->lock_doublebuffer_disable(
1110                                 pipe->stream_res.tg);
1111         }
1112 }
1113
1114 void dcn20_pipe_control_lock(
1115         struct dc *dc,
1116         struct pipe_ctx *pipe,
1117         bool lock)
1118 {
1119         bool flip_immediate = false;
1120
1121         /* use TG master update lock to lock everything on the TG
1122          * therefore only top pipe need to lock
1123          */
1124         if (pipe->top_pipe)
1125                 return;
1126
1127         if (pipe->plane_state != NULL)
1128                 flip_immediate = pipe->plane_state->flip_immediate;
1129
1130         if (flip_immediate && lock) {
1131                 const int TIMEOUT_FOR_FLIP_PENDING = 100000;
1132                 int i;
1133
1134                 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
1135                         if (!pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->plane_res.hubp))
1136                                 break;
1137                         udelay(1);
1138                 }
1139
1140                 if (pipe->bottom_pipe != NULL) {
1141                         for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
1142                                 if (!pipe->bottom_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->bottom_pipe->plane_res.hubp))
1143                                         break;
1144                                 udelay(1);
1145                         }
1146                 }
1147         }
1148
1149         /* In flip immediate and pipe splitting case, we need to use GSL
1150          * for synchronization. Only do setup on locking and on flip type change.
1151          */
1152         if (lock && pipe->bottom_pipe != NULL)
1153                 if ((flip_immediate && pipe->stream_res.gsl_group == 0) ||
1154                     (!flip_immediate && pipe->stream_res.gsl_group > 0))
1155                         dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);
1156
1157         if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {
1158                 if (lock)
1159                         pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);
1160                 else
1161                         pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg);
1162         } else {
1163                 if (lock)
1164                         pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1165                 else
1166                         pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1167         }
1168 }
1169
1170 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe)
1171 {
1172         new_pipe->update_flags.raw = 0;
1173
1174         /* Exit on unchanged, unused pipe */
1175         if (!old_pipe->plane_state && !new_pipe->plane_state)
1176                 return;
1177         /* Detect pipe enable/disable */
1178         if (!old_pipe->plane_state && new_pipe->plane_state) {
1179                 new_pipe->update_flags.bits.enable = 1;
1180                 new_pipe->update_flags.bits.mpcc = 1;
1181                 new_pipe->update_flags.bits.dppclk = 1;
1182                 new_pipe->update_flags.bits.hubp_interdependent = 1;
1183                 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1184                 new_pipe->update_flags.bits.gamut_remap = 1;
1185                 new_pipe->update_flags.bits.scaler = 1;
1186                 new_pipe->update_flags.bits.viewport = 1;
1187                 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1188                         new_pipe->update_flags.bits.odm = 1;
1189                         new_pipe->update_flags.bits.global_sync = 1;
1190                 }
1191                 return;
1192         }
1193         if (old_pipe->plane_state && !new_pipe->plane_state) {
1194                 new_pipe->update_flags.bits.disable = 1;
1195                 return;
1196         }
1197
1198         /* Detect top pipe only changes */
1199         if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1200                 /* Detect odm changes */
1201                 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe
1202                         && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx)
1203                                 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe)
1204                                 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe)
1205                                 || old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1206                         new_pipe->update_flags.bits.odm = 1;
1207
1208                 /* Detect global sync changes */
1209                 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset
1210                                 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start
1211                                 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset
1212                                 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width)
1213                         new_pipe->update_flags.bits.global_sync = 1;
1214         }
1215
1216         /*
1217          * Detect opp / tg change, only set on change, not on enable
1218          * Assume mpcc inst = pipe index, if not this code needs to be updated
1219          * since mpcc is what is affected by these. In fact all of our sequence
1220          * makes this assumption at the moment with how hubp reset is matched to
1221          * same index mpcc reset.
1222          */
1223         if (old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1224                 new_pipe->update_flags.bits.opp_changed = 1;
1225         if (old_pipe->stream_res.tg != new_pipe->stream_res.tg)
1226                 new_pipe->update_flags.bits.tg_changed = 1;
1227
1228         /* Detect mpcc blending changes, only dpp inst and bot matter here */
1229         if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp
1230                         || old_pipe->stream_res.opp != new_pipe->stream_res.opp
1231                         || (!old_pipe->bottom_pipe && new_pipe->bottom_pipe)
1232                         || (old_pipe->bottom_pipe && !new_pipe->bottom_pipe)
1233                         || (old_pipe->bottom_pipe && new_pipe->bottom_pipe
1234                                 && old_pipe->bottom_pipe->plane_res.mpcc_inst
1235                                         != new_pipe->bottom_pipe->plane_res.mpcc_inst))
1236                 new_pipe->update_flags.bits.mpcc = 1;
1237
1238         /* Detect dppclk change */
1239         if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz)
1240                 new_pipe->update_flags.bits.dppclk = 1;
1241
1242         /* Check for scl update */
1243         if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data)))
1244                         new_pipe->update_flags.bits.scaler = 1;
1245         /* Check for vp update */
1246         if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect))
1247                         || memcmp(&old_pipe->plane_res.scl_data.viewport_c,
1248                                 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect)))
1249                 new_pipe->update_flags.bits.viewport = 1;
1250
1251         /* Detect dlg/ttu/rq updates */
1252         {
1253                 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs;
1254                 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs;
1255                 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs;
1256                 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs;
1257
1258                 /* Detect pipe interdependent updates */
1259                 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch ||
1260                                 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch ||
1261                                 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c ||
1262                                 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank ||
1263                                 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank ||
1264                                 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip ||
1265                                 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip ||
1266                                 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l ||
1267                                 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c ||
1268                                 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l ||
1269                                 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l ||
1270                                 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c ||
1271                                 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l ||
1272                                 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c ||
1273                                 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 ||
1274                                 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 ||
1275                                 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank ||
1276                                 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) {
1277                         old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch;
1278                         old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch;
1279                         old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c;
1280                         old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank;
1281                         old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank;
1282                         old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip;
1283                         old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip;
1284                         old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l;
1285                         old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c;
1286                         old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l;
1287                         old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l;
1288                         old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c;
1289                         old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l;
1290                         old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c;
1291                         old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0;
1292                         old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1;
1293                         old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank;
1294                         old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip;
1295                         new_pipe->update_flags.bits.hubp_interdependent = 1;
1296                 }
1297                 /* Detect any other updates to ttu/rq/dlg */
1298                 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) ||
1299                                 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) ||
1300                                 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs)))
1301                         new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1302         }
1303 }
1304
1305 static void dcn20_update_dchubp_dpp(
1306         struct dc *dc,
1307         struct pipe_ctx *pipe_ctx,
1308         struct dc_state *context)
1309 {
1310         struct dce_hwseq *hws = dc->hwseq;
1311         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1312         struct dpp *dpp = pipe_ctx->plane_res.dpp;
1313         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1314         bool viewport_changed = false;
1315
1316         if (pipe_ctx->update_flags.bits.dppclk)
1317                 dpp->funcs->dpp_dppclk_control(dpp, false, true);
1318
1319         /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
1320          * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
1321          * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
1322          */
1323         if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) {
1324                 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
1325
1326                 hubp->funcs->hubp_setup(
1327                         hubp,
1328                         &pipe_ctx->dlg_regs,
1329                         &pipe_ctx->ttu_regs,
1330                         &pipe_ctx->rq_regs,
1331                         &pipe_ctx->pipe_dlg_param);
1332         }
1333         if (pipe_ctx->update_flags.bits.hubp_interdependent)
1334                 hubp->funcs->hubp_setup_interdependent(
1335                         hubp,
1336                         &pipe_ctx->dlg_regs,
1337                         &pipe_ctx->ttu_regs);
1338
1339         if (pipe_ctx->update_flags.bits.enable ||
1340                         plane_state->update_flags.bits.bpp_change ||
1341                         plane_state->update_flags.bits.input_csc_change ||
1342                         plane_state->update_flags.bits.color_space_change ||
1343                         plane_state->update_flags.bits.coeff_reduction_change) {
1344                 struct dc_bias_and_scale bns_params = {0};
1345
1346                 // program the input csc
1347                 dpp->funcs->dpp_setup(dpp,
1348                                 plane_state->format,
1349                                 EXPANSION_MODE_ZERO,
1350                                 plane_state->input_csc_color_matrix,
1351                                 plane_state->color_space,
1352                                 NULL);
1353
1354                 if (dpp->funcs->dpp_program_bias_and_scale) {
1355                         //TODO :for CNVC set scale and bias registers if necessary
1356                         build_prescale_params(&bns_params, plane_state);
1357                         dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1358                 }
1359         }
1360
1361         if (pipe_ctx->update_flags.bits.mpcc
1362                         || plane_state->update_flags.bits.global_alpha_change
1363                         || plane_state->update_flags.bits.per_pixel_alpha_change) {
1364                 // MPCC inst is equal to pipe index in practice
1365                 int mpcc_inst = hubp->inst;
1366                 int opp_inst;
1367                 int opp_count = dc->res_pool->pipe_count;
1368
1369                 for (opp_inst = 0; opp_inst < opp_count; opp_inst++) {
1370                         if (dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst]) {
1371                                 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
1372                                 dc->res_pool->opps[opp_inst]->mpcc_disconnect_pending[mpcc_inst] = false;
1373                                 break;
1374                         }
1375                 }
1376                 hws->funcs.update_mpcc(dc, pipe_ctx);
1377         }
1378
1379         if (pipe_ctx->update_flags.bits.scaler ||
1380                         plane_state->update_flags.bits.scaling_change ||
1381                         plane_state->update_flags.bits.position_change ||
1382                         plane_state->update_flags.bits.per_pixel_alpha_change ||
1383                         pipe_ctx->stream->update_flags.bits.scaling) {
1384                 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;
1385                 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_30BPP);
1386                 /* scaler configuration */
1387                 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
1388                                 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
1389         }
1390
1391         if (pipe_ctx->update_flags.bits.viewport ||
1392                         (context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||
1393                         (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) {
1394
1395                 hubp->funcs->mem_program_viewport(
1396                         hubp,
1397                         &pipe_ctx->plane_res.scl_data.viewport,
1398                         &pipe_ctx->plane_res.scl_data.viewport_c);
1399                 viewport_changed = true;
1400         }
1401
1402         /* Any updates are handled in dc interface, just need to apply existing for plane enable */
1403         if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed ||
1404                         pipe_ctx->update_flags.bits.scaler || pipe_ctx->update_flags.bits.viewport)
1405                         && pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
1406                 dc->hwss.set_cursor_position(pipe_ctx);
1407                 dc->hwss.set_cursor_attribute(pipe_ctx);
1408
1409                 if (dc->hwss.set_cursor_sdr_white_level)
1410                         dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
1411         }
1412
1413         /* Any updates are handled in dc interface, just need
1414          * to apply existing for plane enable / opp change */
1415         if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed
1416                         || pipe_ctx->stream->update_flags.bits.gamut_remap
1417                         || pipe_ctx->stream->update_flags.bits.out_csc) {
1418                         /* dpp/cm gamut remap*/
1419                         dc->hwss.program_gamut_remap(pipe_ctx);
1420
1421                 /*call the dcn2 method which uses mpc csc*/
1422                 dc->hwss.program_output_csc(dc,
1423                                 pipe_ctx,
1424                                 pipe_ctx->stream->output_color_space,
1425                                 pipe_ctx->stream->csc_color_matrix.matrix,
1426                                 hubp->opp_id);
1427         }
1428
1429         if (pipe_ctx->update_flags.bits.enable ||
1430                         pipe_ctx->update_flags.bits.opp_changed ||
1431                         plane_state->update_flags.bits.pixel_format_change ||
1432                         plane_state->update_flags.bits.horizontal_mirror_change ||
1433                         plane_state->update_flags.bits.rotation_change ||
1434                         plane_state->update_flags.bits.swizzle_change ||
1435                         plane_state->update_flags.bits.dcc_change ||
1436                         plane_state->update_flags.bits.bpp_change ||
1437                         plane_state->update_flags.bits.scaling_change ||
1438                         plane_state->update_flags.bits.plane_size_change) {
1439                 struct plane_size size = plane_state->plane_size;
1440
1441                 size.surface_size = pipe_ctx->plane_res.scl_data.viewport;
1442                 hubp->funcs->hubp_program_surface_config(
1443                         hubp,
1444                         plane_state->format,
1445                         &plane_state->tiling_info,
1446                         &size,
1447                         plane_state->rotation,
1448                         &plane_state->dcc,
1449                         plane_state->horizontal_mirror,
1450                         0);
1451                 hubp->power_gated = false;
1452         }
1453
1454         if (hubp->funcs->apply_PLAT_54186_wa && viewport_changed)
1455                 hubp->funcs->apply_PLAT_54186_wa(hubp, &plane_state->address);
1456
1457         if (pipe_ctx->update_flags.bits.enable || plane_state->update_flags.bits.addr_update)
1458                 hws->funcs.update_plane_addr(dc, pipe_ctx);
1459
1460
1461
1462         if (pipe_ctx->update_flags.bits.enable)
1463                 hubp->funcs->set_blank(hubp, false);
1464 }
1465
1466
1467 static void dcn20_program_pipe(
1468                 struct dc *dc,
1469                 struct pipe_ctx *pipe_ctx,
1470                 struct dc_state *context)
1471 {
1472         struct dce_hwseq *hws = dc->hwseq;
1473         /* Only need to unblank on top pipe */
1474         if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level)
1475                         && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
1476                 hws->funcs.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
1477
1478         if (pipe_ctx->update_flags.bits.global_sync) {
1479                 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1480                                 pipe_ctx->stream_res.tg,
1481                                 pipe_ctx->pipe_dlg_param.vready_offset,
1482                                 pipe_ctx->pipe_dlg_param.vstartup_start,
1483                                 pipe_ctx->pipe_dlg_param.vupdate_offset,
1484                                 pipe_ctx->pipe_dlg_param.vupdate_width);
1485
1486                 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1487                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1488
1489                 if (hws->funcs.setup_vupdate_interrupt)
1490                         hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1491         }
1492
1493         if (pipe_ctx->update_flags.bits.odm)
1494                 hws->funcs.update_odm(dc, context, pipe_ctx);
1495
1496         if (pipe_ctx->update_flags.bits.enable)
1497                 dcn20_enable_plane(dc, pipe_ctx, context);
1498
1499         if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw)
1500                 dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
1501
1502         if (pipe_ctx->update_flags.bits.enable
1503                         || pipe_ctx->plane_state->update_flags.bits.hdr_mult)
1504                 hws->funcs.set_hdr_multiplier(pipe_ctx);
1505
1506         if (pipe_ctx->update_flags.bits.enable ||
1507                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
1508                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
1509                 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
1510
1511         /* dcn10_translate_regamma_to_hw_format takes 750us to finish
1512          * only do gamma programming for powering on, internal memcmp to avoid
1513          * updating on slave planes
1514          */
1515         if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf)
1516                 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
1517
1518         /* If the pipe has been enabled or has a different opp, we
1519          * should reprogram the fmt. This deals with cases where
1520          * interation between mpc and odm combine on different streams
1521          * causes a different pipe to be chosen to odm combine with.
1522          */
1523         if (pipe_ctx->update_flags.bits.enable
1524             || pipe_ctx->update_flags.bits.opp_changed) {
1525
1526                 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1527                         pipe_ctx->stream_res.opp,
1528                         COLOR_SPACE_YCBCR601,
1529                         pipe_ctx->stream->timing.display_color_depth,
1530                         pipe_ctx->stream->signal);
1531
1532                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1533                         pipe_ctx->stream_res.opp,
1534                         &pipe_ctx->stream->bit_depth_params,
1535                         &pipe_ctx->stream->clamping);
1536         }
1537 }
1538
1539 static bool does_pipe_need_lock(struct pipe_ctx *pipe)
1540 {
1541         if ((pipe->plane_state && pipe->plane_state->update_flags.raw)
1542                         || pipe->update_flags.raw)
1543                 return true;
1544         if (pipe->bottom_pipe)
1545                 return does_pipe_need_lock(pipe->bottom_pipe);
1546
1547         return false;
1548 }
1549
1550 void dcn20_program_front_end_for_ctx(
1551                 struct dc *dc,
1552                 struct dc_state *context)
1553 {
1554         int i;
1555         struct dce_hwseq *hws = dc->hwseq;
1556         bool pipe_locked[MAX_PIPES] = {false};
1557         DC_LOGGER_INIT(dc->ctx->logger);
1558
1559         /* Carry over GSL groups in case the context is changing. */
1560         for (i = 0; i < dc->res_pool->pipe_count; i++)
1561                 if (context->res_ctx.pipe_ctx[i].stream == dc->current_state->res_ctx.pipe_ctx[i].stream)
1562                         context->res_ctx.pipe_ctx[i].stream_res.gsl_group =
1563                                 dc->current_state->res_ctx.pipe_ctx[i].stream_res.gsl_group;
1564
1565         /* Set pipe update flags and lock pipes */
1566         for (i = 0; i < dc->res_pool->pipe_count; i++)
1567                 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i],
1568                                 &context->res_ctx.pipe_ctx[i]);
1569         for (i = 0; i < dc->res_pool->pipe_count; i++)
1570                 if (!context->res_ctx.pipe_ctx[i].top_pipe &&
1571                                 does_pipe_need_lock(&context->res_ctx.pipe_ctx[i])) {
1572                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1573
1574                         if (pipe_ctx->update_flags.bits.tg_changed || pipe_ctx->update_flags.bits.enable)
1575                                 dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
1576                         if (!pipe_ctx->update_flags.bits.enable)
1577                                 dc->hwss.pipe_control_lock(dc, &dc->current_state->res_ctx.pipe_ctx[i], true);
1578                         pipe_locked[i] = true;
1579                 }
1580
1581         /* OTG blank before disabling all front ends */
1582         for (i = 0; i < dc->res_pool->pipe_count; i++)
1583                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1584                                 && !context->res_ctx.pipe_ctx[i].top_pipe
1585                                 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe
1586                                 && context->res_ctx.pipe_ctx[i].stream)
1587                         hws->funcs.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);
1588
1589         /* Disconnect mpcc */
1590         for (i = 0; i < dc->res_pool->pipe_count; i++)
1591                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1592                                 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {
1593                         hws->funcs.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1594                         DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
1595                 }
1596
1597         /*
1598          * Program all updated pipes, order matters for mpcc setup. Start with
1599          * top pipe and program all pipes that follow in order
1600          */
1601         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1602                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1603
1604                 if (pipe->plane_state && !pipe->top_pipe) {
1605                         while (pipe) {
1606                                 dcn20_program_pipe(dc, pipe, context);
1607                                 pipe = pipe->bottom_pipe;
1608                         }
1609                         /* Program secondary blending tree and writeback pipes */
1610                         pipe = &context->res_ctx.pipe_ctx[i];
1611                         if (!pipe->prev_odm_pipe && pipe->stream->num_wb_info > 0
1612                                         && (pipe->update_flags.raw || pipe->plane_state->update_flags.raw || pipe->stream->update_flags.raw)
1613                                         && hws->funcs.program_all_writeback_pipes_in_tree)
1614                                 hws->funcs.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);
1615                 }
1616         }
1617
1618         /* Unlock all locked pipes */
1619         for (i = 0; i < dc->res_pool->pipe_count; i++)
1620                 if (pipe_locked[i]) {
1621                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1622
1623                         if (pipe_ctx->update_flags.bits.tg_changed || pipe_ctx->update_flags.bits.enable)
1624                                 dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
1625                         if (!pipe_ctx->update_flags.bits.enable)
1626                                 dc->hwss.pipe_control_lock(dc, &dc->current_state->res_ctx.pipe_ctx[i], false);
1627                 }
1628 }
1629
1630 void dcn20_post_unlock_program_front_end(
1631                 struct dc *dc,
1632                 struct dc_state *context)
1633 {
1634         int i;
1635         const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100;
1636
1637         DC_LOGGER_INIT(dc->ctx->logger);
1638
1639         for (i = 0; i < dc->res_pool->pipe_count; i++)
1640                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
1641                         dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1642
1643         /*
1644          * If we are enabling a pipe, we need to wait for pending clear as this is a critical
1645          * part of the enable operation otherwise, DM may request an immediate flip which
1646          * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which
1647          * is unsupported on DCN.
1648          */
1649         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1650                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1651
1652                 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable) {
1653                         struct hubp *hubp = pipe->plane_res.hubp;
1654                         int j = 0;
1655
1656                         for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS*1000
1657                                         && hubp->funcs->hubp_is_flip_pending(hubp); j++)
1658                                 mdelay(1);
1659                 }
1660         }
1661
1662         /* WA to apply WM setting*/
1663         if (dc->hwseq->wa.DEGVIDCN21)
1664                 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);
1665 }
1666
1667
1668 void dcn20_prepare_bandwidth(
1669                 struct dc *dc,
1670                 struct dc_state *context)
1671 {
1672         struct hubbub *hubbub = dc->res_pool->hubbub;
1673
1674         dc->clk_mgr->funcs->update_clocks(
1675                         dc->clk_mgr,
1676                         context,
1677                         false);
1678
1679         /* program dchubbub watermarks */
1680         hubbub->funcs->program_watermarks(hubbub,
1681                                         &context->bw_ctx.bw.dcn.watermarks,
1682                                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1683                                         false);
1684 }
1685
1686 void dcn20_optimize_bandwidth(
1687                 struct dc *dc,
1688                 struct dc_state *context)
1689 {
1690         struct hubbub *hubbub = dc->res_pool->hubbub;
1691
1692         /* program dchubbub watermarks */
1693         hubbub->funcs->program_watermarks(hubbub,
1694                                         &context->bw_ctx.bw.dcn.watermarks,
1695                                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1696                                         true);
1697
1698         dc->clk_mgr->funcs->update_clocks(
1699                         dc->clk_mgr,
1700                         context,
1701                         true);
1702 }
1703
1704 bool dcn20_update_bandwidth(
1705                 struct dc *dc,
1706                 struct dc_state *context)
1707 {
1708         int i;
1709         struct dce_hwseq *hws = dc->hwseq;
1710
1711         /* recalculate DML parameters */
1712         if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false))
1713                 return false;
1714
1715         /* apply updated bandwidth parameters */
1716         dc->hwss.prepare_bandwidth(dc, context);
1717
1718         /* update hubp configs for all pipes */
1719         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1720                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1721
1722                 if (pipe_ctx->plane_state == NULL)
1723                         continue;
1724
1725                 if (pipe_ctx->top_pipe == NULL) {
1726                         bool blank = !is_pipe_tree_visible(pipe_ctx);
1727
1728                         pipe_ctx->stream_res.tg->funcs->program_global_sync(
1729                                         pipe_ctx->stream_res.tg,
1730                                         pipe_ctx->pipe_dlg_param.vready_offset,
1731                                         pipe_ctx->pipe_dlg_param.vstartup_start,
1732                                         pipe_ctx->pipe_dlg_param.vupdate_offset,
1733                                         pipe_ctx->pipe_dlg_param.vupdate_width);
1734
1735                         pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1736                                         pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1737
1738                         if (pipe_ctx->prev_odm_pipe == NULL)
1739                                 hws->funcs.blank_pixel_data(dc, pipe_ctx, blank);
1740
1741                         if (hws->funcs.setup_vupdate_interrupt)
1742                                 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1743                 }
1744
1745                 pipe_ctx->plane_res.hubp->funcs->hubp_setup(
1746                                 pipe_ctx->plane_res.hubp,
1747                                         &pipe_ctx->dlg_regs,
1748                                         &pipe_ctx->ttu_regs,
1749                                         &pipe_ctx->rq_regs,
1750                                         &pipe_ctx->pipe_dlg_param);
1751         }
1752
1753         return true;
1754 }
1755
1756 void dcn20_enable_writeback(
1757                 struct dc *dc,
1758                 struct dc_writeback_info *wb_info,
1759                 struct dc_state *context)
1760 {
1761         struct dwbc *dwb;
1762         struct mcif_wb *mcif_wb;
1763         struct timing_generator *optc;
1764
1765         ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
1766         ASSERT(wb_info->wb_enabled);
1767         dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
1768         mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
1769
1770         /* set the OPTC source mux */
1771         optc = dc->res_pool->timing_generators[dwb->otg_inst];
1772         optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);
1773         /* set MCIF_WB buffer and arbitration configuration */
1774         mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height);
1775         mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
1776         /* Enable MCIF_WB */
1777         mcif_wb->funcs->enable_mcif(mcif_wb);
1778         /* Enable DWB */
1779         dwb->funcs->enable(dwb, &wb_info->dwb_params);
1780         /* TODO: add sequence to enable/disable warmup */
1781 }
1782
1783 void dcn20_disable_writeback(
1784                 struct dc *dc,
1785                 unsigned int dwb_pipe_inst)
1786 {
1787         struct dwbc *dwb;
1788         struct mcif_wb *mcif_wb;
1789
1790         ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
1791         dwb = dc->res_pool->dwbc[dwb_pipe_inst];
1792         mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
1793
1794         dwb->funcs->disable(dwb);
1795         mcif_wb->funcs->disable_mcif(mcif_wb);
1796 }
1797
1798 bool dcn20_wait_for_blank_complete(
1799                 struct output_pixel_processor *opp)
1800 {
1801         int counter;
1802
1803         for (counter = 0; counter < 1000; counter++) {
1804                 if (opp->funcs->dpg_is_blanked(opp))
1805                         break;
1806
1807                 udelay(100);
1808         }
1809
1810         if (counter == 1000) {
1811                 dm_error("DC: failed to blank crtc!\n");
1812                 return false;
1813         }
1814
1815         return true;
1816 }
1817
1818 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)
1819 {
1820         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1821
1822         if (!hubp)
1823                 return false;
1824         return hubp->funcs->dmdata_status_done(hubp);
1825 }
1826
1827 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
1828 {
1829         struct dce_hwseq *hws = dc->hwseq;
1830
1831         if (pipe_ctx->stream_res.dsc) {
1832                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1833
1834                 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);
1835                 while (odm_pipe) {
1836                         dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true);
1837                         odm_pipe = odm_pipe->next_odm_pipe;
1838                 }
1839         }
1840 }
1841
1842 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
1843 {
1844         struct dce_hwseq *hws = dc->hwseq;
1845
1846         if (pipe_ctx->stream_res.dsc) {
1847                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1848
1849                 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);
1850                 while (odm_pipe) {
1851                         dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false);
1852                         odm_pipe = odm_pipe->next_odm_pipe;
1853                 }
1854         }
1855 }
1856
1857 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)
1858 {
1859         struct dc_dmdata_attributes attr = { 0 };
1860         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1861
1862         attr.dmdata_mode = DMDATA_HW_MODE;
1863         attr.dmdata_size =
1864                 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;
1865         attr.address.quad_part =
1866                         pipe_ctx->stream->dmdata_address.quad_part;
1867         attr.dmdata_dl_delta = 0;
1868         attr.dmdata_qos_mode = 0;
1869         attr.dmdata_qos_level = 0;
1870         attr.dmdata_repeat = 1; /* always repeat */
1871         attr.dmdata_updated = 1;
1872         attr.dmdata_sw_data = NULL;
1873
1874         hubp->funcs->dmdata_set_attributes(hubp, &attr);
1875 }
1876
1877 void dcn20_init_vm_ctx(
1878                 struct dce_hwseq *hws,
1879                 struct dc *dc,
1880                 struct dc_virtual_addr_space_config *va_config,
1881                 int vmid)
1882 {
1883         struct dcn_hubbub_virt_addr_config config;
1884
1885         if (vmid == 0) {
1886                 ASSERT(0); /* VMID cannot be 0 for vm context */
1887                 return;
1888         }
1889
1890         config.page_table_start_addr = va_config->page_table_start_addr;
1891         config.page_table_end_addr = va_config->page_table_end_addr;
1892         config.page_table_block_size = va_config->page_table_block_size_in_bytes;
1893         config.page_table_depth = va_config->page_table_depth;
1894         config.page_table_base_addr = va_config->page_table_base_addr;
1895
1896         dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid);
1897 }
1898
1899 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
1900 {
1901         struct dcn_hubbub_phys_addr_config config;
1902
1903         config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
1904         config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
1905         config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
1906         config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
1907         config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
1908         config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
1909         config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
1910         config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
1911         config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
1912         config.page_table_default_page_addr = pa_config->page_table_default_page_addr;
1913
1914         return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
1915 }
1916
1917 static bool patch_address_for_sbs_tb_stereo(
1918                 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
1919 {
1920         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1921         bool sec_split = pipe_ctx->top_pipe &&
1922                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
1923         if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
1924                         (pipe_ctx->stream->timing.timing_3d_format ==
1925                         TIMING_3D_FORMAT_SIDE_BY_SIDE ||
1926                         pipe_ctx->stream->timing.timing_3d_format ==
1927                         TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
1928                 *addr = plane_state->address.grph_stereo.left_addr;
1929                 plane_state->address.grph_stereo.left_addr =
1930                                 plane_state->address.grph_stereo.right_addr;
1931                 return true;
1932         }
1933
1934         if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
1935                         plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
1936                 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
1937                 plane_state->address.grph_stereo.right_addr =
1938                                 plane_state->address.grph_stereo.left_addr;
1939         }
1940         return false;
1941 }
1942
1943 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
1944 {
1945         bool addr_patched = false;
1946         PHYSICAL_ADDRESS_LOC addr;
1947         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1948
1949         if (plane_state == NULL)
1950                 return;
1951
1952         addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
1953
1954         // Call Helper to track VMID use
1955         vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);
1956
1957         pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
1958                         pipe_ctx->plane_res.hubp,
1959                         &plane_state->address,
1960                         plane_state->flip_immediate);
1961
1962         plane_state->status.requested_address = plane_state->address;
1963
1964         if (plane_state->flip_immediate)
1965                 plane_state->status.current_address = plane_state->address;
1966
1967         if (addr_patched)
1968                 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
1969 }
1970
1971 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
1972                 struct dc_link_settings *link_settings)
1973 {
1974         struct encoder_unblank_param params = { { 0 } };
1975         struct dc_stream_state *stream = pipe_ctx->stream;
1976         struct dc_link *link = stream->link;
1977         struct dce_hwseq *hws = link->dc->hwseq;
1978         struct pipe_ctx *odm_pipe;
1979
1980         params.opp_cnt = 1;
1981         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1982                 params.opp_cnt++;
1983         }
1984         /* only 3 items below are used by unblank */
1985         params.timing = pipe_ctx->stream->timing;
1986
1987         params.link_settings.link_rate = link_settings->link_rate;
1988
1989         if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1990                 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1)
1991                         params.timing.pix_clk_100hz /= 2;
1992                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
1993                                 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1);
1994                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
1995         }
1996
1997         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1998                 hws->funcs.edp_backlight_control(link, true);
1999         }
2000 }
2001
2002 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
2003 {
2004         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2005         int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
2006
2007         if (start_line < 0)
2008                 start_line = 0;
2009
2010         if (tg->funcs->setup_vertical_interrupt2)
2011                 tg->funcs->setup_vertical_interrupt2(tg, start_line);
2012 }
2013
2014 static void dcn20_reset_back_end_for_pipe(
2015                 struct dc *dc,
2016                 struct pipe_ctx *pipe_ctx,
2017                 struct dc_state *context)
2018 {
2019         int i;
2020         struct dc_link *link;
2021         DC_LOGGER_INIT(dc->ctx->logger);
2022         if (pipe_ctx->stream_res.stream_enc == NULL) {
2023                 pipe_ctx->stream = NULL;
2024                 return;
2025         }
2026
2027         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2028                 link = pipe_ctx->stream->link;
2029                 /* DPMS may already disable or */
2030                 /* dpms_off status is incorrect due to fastboot
2031                  * feature. When system resume from S4 with second
2032                  * screen only, the dpms_off would be true but
2033                  * VBIOS lit up eDP, so check link status too.
2034                  */
2035                 if (!pipe_ctx->stream->dpms_off || link->link_status.link_active)
2036                         core_link_disable_stream(pipe_ctx);
2037                 else if (pipe_ctx->stream_res.audio)
2038                         dc->hwss.disable_audio_stream(pipe_ctx);
2039
2040                 /* free acquired resources */
2041                 if (pipe_ctx->stream_res.audio) {
2042                         /*disable az_endpoint*/
2043                         pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2044
2045                         /*free audio*/
2046                         if (dc->caps.dynamic_audio == true) {
2047                                 /*we have to dynamic arbitrate the audio endpoints*/
2048                                 /*we free the resource, need reset is_audio_acquired*/
2049                                 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
2050                                                 pipe_ctx->stream_res.audio, false);
2051                                 pipe_ctx->stream_res.audio = NULL;
2052                         }
2053                 }
2054         }
2055         else if (pipe_ctx->stream_res.dsc) {
2056                 dp_set_dsc_enable(pipe_ctx, false);
2057         }
2058
2059         /* by upper caller loop, parent pipe: pipe0, will be reset last.
2060          * back end share by all pipes and will be disable only when disable
2061          * parent pipe.
2062          */
2063         if (pipe_ctx->top_pipe == NULL) {
2064                 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
2065
2066                 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
2067                 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
2068                         pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
2069                                         pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
2070
2071                 if (pipe_ctx->stream_res.tg->funcs->set_drr)
2072                         pipe_ctx->stream_res.tg->funcs->set_drr(
2073                                         pipe_ctx->stream_res.tg, NULL);
2074         }
2075
2076         for (i = 0; i < dc->res_pool->pipe_count; i++)
2077                 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
2078                         break;
2079
2080         if (i == dc->res_pool->pipe_count)
2081                 return;
2082
2083         pipe_ctx->stream = NULL;
2084         DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
2085                                         pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
2086 }
2087
2088 void dcn20_reset_hw_ctx_wrap(
2089                 struct dc *dc,
2090                 struct dc_state *context)
2091 {
2092         int i;
2093         struct dce_hwseq *hws = dc->hwseq;
2094
2095         /* Reset Back End*/
2096         for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
2097                 struct pipe_ctx *pipe_ctx_old =
2098                         &dc->current_state->res_ctx.pipe_ctx[i];
2099                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2100
2101                 if (!pipe_ctx_old->stream)
2102                         continue;
2103
2104                 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
2105                         continue;
2106
2107                 if (!pipe_ctx->stream ||
2108                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
2109                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
2110
2111                         dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
2112                         if (hws->funcs.enable_stream_gating)
2113                                 hws->funcs.enable_stream_gating(dc, pipe_ctx);
2114                         if (old_clk)
2115                                 old_clk->funcs->cs_power_down(old_clk);
2116                 }
2117         }
2118 }
2119
2120 void dcn20_get_mpctree_visual_confirm_color(
2121                 struct pipe_ctx *pipe_ctx,
2122                 struct tg_color *color)
2123 {
2124         const struct tg_color pipe_colors[6] = {
2125                         {MAX_TG_COLOR_VALUE, 0, 0}, // red
2126                         {MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, // yellow
2127                         {0, MAX_TG_COLOR_VALUE, 0}, // blue
2128                         {MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, // purple
2129                         {0, 0, MAX_TG_COLOR_VALUE}, // green
2130                         {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE * 2 / 3, 0}, // orange
2131         };
2132
2133         struct pipe_ctx *top_pipe = pipe_ctx;
2134
2135         while (top_pipe->top_pipe) {
2136                 top_pipe = top_pipe->top_pipe;
2137         }
2138
2139         *color = pipe_colors[top_pipe->pipe_idx];
2140 }
2141
2142 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
2143 {
2144         struct dce_hwseq *hws = dc->hwseq;
2145         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2146         struct mpcc_blnd_cfg blnd_cfg = { {0} };
2147         bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
2148         int mpcc_id;
2149         struct mpcc *new_mpcc;
2150         struct mpc *mpc = dc->res_pool->mpc;
2151         struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
2152
2153         // input to MPCC is always RGB, by default leave black_color at 0
2154         if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
2155                 hws->funcs.get_hdr_visual_confirm_color(
2156                                 pipe_ctx, &blnd_cfg.black_color);
2157         } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
2158                 hws->funcs.get_surface_visual_confirm_color(
2159                                 pipe_ctx, &blnd_cfg.black_color);
2160         } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) {
2161                 dcn20_get_mpctree_visual_confirm_color(
2162                                 pipe_ctx, &blnd_cfg.black_color);
2163         }
2164
2165         if (per_pixel_alpha)
2166                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
2167         else
2168                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
2169
2170         blnd_cfg.overlap_only = false;
2171         blnd_cfg.global_gain = 0xff;
2172
2173         if (pipe_ctx->plane_state->global_alpha)
2174                 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
2175         else
2176                 blnd_cfg.global_alpha = 0xff;
2177
2178         blnd_cfg.background_color_bpc = 4;
2179         blnd_cfg.bottom_gain_mode = 0;
2180         blnd_cfg.top_gain = 0x1f000;
2181         blnd_cfg.bottom_inside_gain = 0x1f000;
2182         blnd_cfg.bottom_outside_gain = 0x1f000;
2183         blnd_cfg.pre_multiplied_alpha = per_pixel_alpha;
2184
2185         /*
2186          * TODO: remove hack
2187          * Note: currently there is a bug in init_hw such that
2188          * on resume from hibernate, BIOS sets up MPCC0, and
2189          * we do mpcc_remove but the mpcc cannot go to idle
2190          * after remove. This cause us to pick mpcc1 here,
2191          * which causes a pstate hang for yet unknown reason.
2192          */
2193         mpcc_id = hubp->inst;
2194
2195         /* check if this MPCC is already being used */
2196         new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
2197         /* remove MPCC if being used */
2198         if (new_mpcc != NULL)
2199                 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
2200         else
2201                 if (dc->debug.sanity_checks)
2202                         mpc->funcs->assert_mpcc_idle_before_connect(
2203                                         dc->res_pool->mpc, mpcc_id);
2204
2205         /* Call MPC to insert new plane */
2206         new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
2207                         mpc_tree_params,
2208                         &blnd_cfg,
2209                         NULL,
2210                         NULL,
2211                         hubp->inst,
2212                         mpcc_id);
2213
2214         ASSERT(new_mpcc != NULL);
2215         hubp->opp_id = pipe_ctx->stream_res.opp->inst;
2216         hubp->mpcc_id = mpcc_id;
2217 }
2218
2219 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
2220 {
2221         enum dc_lane_count lane_count =
2222                 pipe_ctx->stream->link->cur_link_settings.lane_count;
2223
2224         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
2225         struct dc_link *link = pipe_ctx->stream->link;
2226
2227         uint32_t active_total_with_borders;
2228         uint32_t early_control = 0;
2229         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2230
2231         /* For MST, there are multiply stream go to only one link.
2232          * connect DIG back_end to front_end while enable_stream and
2233          * disconnect them during disable_stream
2234          * BY this, it is logic clean to separate stream and link
2235          */
2236         link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
2237                                                     pipe_ctx->stream_res.stream_enc->id, true);
2238
2239         if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {
2240                 if (link->dc->hwss.program_dmdata_engine)
2241                         link->dc->hwss.program_dmdata_engine(pipe_ctx);
2242         }
2243
2244         link->dc->hwss.update_info_frame(pipe_ctx);
2245
2246         /* enable early control to avoid corruption on DP monitor*/
2247         active_total_with_borders =
2248                         timing->h_addressable
2249                                 + timing->h_border_left
2250                                 + timing->h_border_right;
2251
2252         if (lane_count != 0)
2253                 early_control = active_total_with_borders % lane_count;
2254
2255         if (early_control == 0)
2256                 early_control = lane_count;
2257
2258         tg->funcs->set_early_control(tg, early_control);
2259
2260         /* enable audio only within mode set */
2261         if (pipe_ctx->stream_res.audio != NULL) {
2262                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2263                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
2264         }
2265 }
2266
2267 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
2268 {
2269         struct dc_stream_state    *stream     = pipe_ctx->stream;
2270         struct hubp               *hubp       = pipe_ctx->plane_res.hubp;
2271         bool                       enable     = false;
2272         struct stream_encoder     *stream_enc = pipe_ctx->stream_res.stream_enc;
2273         enum dynamic_metadata_mode mode       = dc_is_dp_signal(stream->signal)
2274                                                         ? dmdata_dp
2275                                                         : dmdata_hdmi;
2276
2277         /* if using dynamic meta, don't set up generic infopackets */
2278         if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
2279                 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
2280                 enable = true;
2281         }
2282
2283         if (!hubp)
2284                 return;
2285
2286         if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
2287                 return;
2288
2289         stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
2290                                                 hubp->inst, mode);
2291 }
2292
2293 void dcn20_fpga_init_hw(struct dc *dc)
2294 {
2295         int i, j;
2296         struct dce_hwseq *hws = dc->hwseq;
2297         struct resource_pool *res_pool = dc->res_pool;
2298         struct dc_state  *context = dc->current_state;
2299
2300         if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
2301                 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
2302
2303         // Initialize the dccg
2304         if (res_pool->dccg->funcs->dccg_init)
2305                 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
2306
2307         //Enable ability to power gate / don't force power on permanently
2308         hws->funcs.enable_power_gating_plane(hws, true);
2309
2310         // Specific to FPGA dccg and registers
2311         REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
2312         REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
2313
2314         hws->funcs.dccg_init(hws);
2315
2316         REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
2317         REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
2318         REG_WRITE(REFCLK_CNTL, 0);
2319         //
2320
2321
2322         /* Blank pixel data with OPP DPG */
2323         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2324                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2325
2326                 if (tg->funcs->is_tg_enabled(tg))
2327                         dcn20_init_blank(dc, tg);
2328         }
2329
2330         for (i = 0; i < res_pool->timing_generator_count; i++) {
2331                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2332
2333                 if (tg->funcs->is_tg_enabled(tg))
2334                         tg->funcs->lock(tg);
2335         }
2336
2337         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2338                 struct dpp *dpp = res_pool->dpps[i];
2339
2340                 dpp->funcs->dpp_reset(dpp);
2341         }
2342
2343         /* Reset all MPCC muxes */
2344         res_pool->mpc->funcs->mpc_init(res_pool->mpc);
2345
2346         /* initialize OPP mpc_tree parameter */
2347         for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
2348                 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
2349                 res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2350                 for (j = 0; j < MAX_PIPES; j++)
2351                         res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
2352         }
2353
2354         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2355                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2356                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2357                 struct hubp *hubp = dc->res_pool->hubps[i];
2358                 struct dpp *dpp = dc->res_pool->dpps[i];
2359
2360                 pipe_ctx->stream_res.tg = tg;
2361                 pipe_ctx->pipe_idx = i;
2362
2363                 pipe_ctx->plane_res.hubp = hubp;
2364                 pipe_ctx->plane_res.dpp = dpp;
2365                 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
2366                 hubp->mpcc_id = dpp->inst;
2367                 hubp->opp_id = OPP_ID_INVALID;
2368                 hubp->power_gated = false;
2369                 pipe_ctx->stream_res.opp = NULL;
2370
2371                 hubp->funcs->hubp_init(hubp);
2372
2373                 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
2374                 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2375                 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
2376                 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
2377                 /*to do*/
2378                 hws->funcs.plane_atomic_disconnect(dc, pipe_ctx);
2379         }
2380
2381         /* initialize DWB pointer to MCIF_WB */
2382         for (i = 0; i < res_pool->res_cap->num_dwb; i++)
2383                 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
2384
2385         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2386                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2387
2388                 if (tg->funcs->is_tg_enabled(tg))
2389                         tg->funcs->unlock(tg);
2390         }
2391
2392         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2393                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2394
2395                 dc->hwss.disable_plane(dc, pipe_ctx);
2396
2397                 pipe_ctx->stream_res.tg = NULL;
2398                 pipe_ctx->plane_res.hubp = NULL;
2399         }
2400
2401         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2402                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2403
2404                 tg->funcs->tg_init(tg);
2405         }
2406 }