drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25 #include <linux/delay.h>
  26
  27 #include "dm_services.h"
  28 #include "basics/dc_common.h"
  29 #include "dm_helpers.h"
  30 #include "core_types.h"
  31 #include "resource.h"
  32 #include "dcn20_resource.h"
  33 #include "dcn20_hwseq.h"
  34 #include "dce/dce_hwseq.h"
  35 #include "dcn20_dsc.h"
  36 #include "dcn20_optc.h"
  37 #include "abm.h"
  38 #include "clk_mgr.h"
  39 #include "dmcu.h"
  40 #include "hubp.h"
  41 #include "timing_generator.h"
  42 #include "opp.h"
  43 #include "ipp.h"
  44 #include "mpc.h"
  45 #include "mcif_wb.h"
  46 #include "dchubbub.h"
  47 #include "reg_helper.h"
  48 #include "dcn10/dcn10_cm_common.h"
  49 #include "dc_link_dp.h"
  50 #include "vm_helper.h"
  51 #include "dccg.h"
  52
  53 #define DC_LOGGER_INIT(logger)
  54
  55 #define CTX \
  56         hws->ctx
  57 #define REG(reg)\
  58         hws->regs->reg
  59
  60 #undef FN
  61 #define FN(reg_name, field_name) \
  62         hws->shifts->field_name, hws->masks->field_name
  63
  64 static int find_free_gsl_group(const struct dc *dc)
  65 {
  66         if (dc->res_pool->gsl_groups.gsl_0 == 0)
  67                 return 1;
  68         if (dc->res_pool->gsl_groups.gsl_1 == 0)
  69                 return 2;
  70         if (dc->res_pool->gsl_groups.gsl_2 == 0)
  71                 return 3;
  72
  73         return 0;
  74 }
  75
  76 /* NOTE: This is not a generic setup_gsl function (hence the suffix as_lock)
  77  * This is only used to lock pipes in pipe splitting case with immediate flip
  78  * Ordinary MPC/OTG locks suppress VUPDATE which doesn't help with immediate,
  79  * so we get tearing with freesync since we cannot flip multiple pipes
  80  * atomically.
  81  * We use GSL for this:
  82  * - immediate flip: find first available GSL group if not already assigned
  83  *                   program gsl with that group, set current OTG as master
  84  *                   and always us 0x4 = AND of flip_ready from all pipes
  85  * - vsync flip: disable GSL if used
  86  *
  87  * Groups in stream_res are stored as +1 from HW registers, i.e.
  88  * gsl_0 <=> pipe_ctx->stream_res.gsl_group == 1
  89  * Using a magic value like -1 would require tracking all inits/resets
  90  */
  91 static void dcn20_setup_gsl_group_as_lock(
  92                 const struct dc *dc,
  93                 struct pipe_ctx *pipe_ctx,
  94                 bool enable)
  95 {
  96         struct gsl_params gsl;
  97         int group_idx;
  98
  99         memset(&gsl, 0, sizeof(struct gsl_params));
 100
 101         if (enable) {
 102                 /* return if group already assigned since GSL was set up
 103                  * for vsync flip, we would unassign so it can't be "left over"
 104                  */
 105                 if (pipe_ctx->stream_res.gsl_group > 0)
 106                         return;
 107
 108                 group_idx = find_free_gsl_group(dc);
 109                 ASSERT(group_idx != 0);
 110                 pipe_ctx->stream_res.gsl_group = group_idx;
 111
 112                 /* set gsl group reg field and mark resource used */
 113                 switch (group_idx) {
 114                 case 1:
 115                         gsl.gsl0_en = 1;
 116                         dc->res_pool->gsl_groups.gsl_0 = 1;
 117                         break;
 118                 case 2:
 119                         gsl.gsl1_en = 1;
 120                         dc->res_pool->gsl_groups.gsl_1 = 1;
 121                         break;
 122                 case 3:
 123                         gsl.gsl2_en = 1;
 124                         dc->res_pool->gsl_groups.gsl_2 = 1;
 125                         break;
 126                 default:
 127                         BREAK_TO_DEBUGGER();
 128                         return; // invalid case
 129                 }
 130                 gsl.gsl_master_en = 1;
 131         } else {
 132                 group_idx = pipe_ctx->stream_res.gsl_group;
 133                 if (group_idx == 0)
 134                         return; // if not in use, just return
 135
 136                 pipe_ctx->stream_res.gsl_group = 0;
 137
 138                 /* unset gsl group reg field and mark resource free */
 139                 switch (group_idx) {
 140                 case 1:
 141                         gsl.gsl0_en = 0;
 142                         dc->res_pool->gsl_groups.gsl_0 = 0;
 143                         break;
 144                 case 2:
 145                         gsl.gsl1_en = 0;
 146                         dc->res_pool->gsl_groups.gsl_1 = 0;
 147                         break;
 148                 case 3:
 149                         gsl.gsl2_en = 0;
 150                         dc->res_pool->gsl_groups.gsl_2 = 0;
 151                         break;
 152                 default:
 153                         BREAK_TO_DEBUGGER();
 154                         return;
 155                 }
 156                 gsl.gsl_master_en = 0;
 157         }
 158
 159         /* at this point we want to program whether it's to enable or disable */
 160         if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL &&
 161                 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) {
 162                 pipe_ctx->stream_res.tg->funcs->set_gsl(
 163                         pipe_ctx->stream_res.tg,
 164                         &gsl);
 165
 166                 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select(
 167                         pipe_ctx->stream_res.tg, group_idx,     enable ? 4 : 0);
 168         } else
 169                 BREAK_TO_DEBUGGER();
 170 }
 171
 172 void dcn20_set_flip_control_gsl(
 173                 struct pipe_ctx *pipe_ctx,
 174                 bool flip_immediate)
 175 {
 176         if (pipe_ctx && pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl)
 177                 pipe_ctx->plane_res.hubp->funcs->hubp_set_flip_control_surface_gsl(
 178                                 pipe_ctx->plane_res.hubp, flip_immediate);
 179
 180 }
 181
 182 void dcn20_enable_power_gating_plane(
 183         struct dce_hwseq *hws,
 184         bool enable)
 185 {
 186         bool force_on = 1; /* disable power gating */
 187
 188         if (enable)
 189                 force_on = 0;
 190
 191         /* DCHUBP0/1/2/3/4/5 */
 192         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
 193         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
 194         REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
 195         REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
 196         if (REG(DOMAIN8_PG_CONFIG))
 197                 REG_UPDATE(DOMAIN8_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
 198         if (REG(DOMAIN10_PG_CONFIG))
 199                 REG_UPDATE(DOMAIN10_PG_CONFIG, DOMAIN8_POWER_FORCEON, force_on);
 200
 201         /* DPP0/1/2/3/4/5 */
 202         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
 203         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
 204         REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
 205         REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
 206         if (REG(DOMAIN9_PG_CONFIG))
 207                 REG_UPDATE(DOMAIN9_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
 208         if (REG(DOMAIN11_PG_CONFIG))
 209                 REG_UPDATE(DOMAIN11_PG_CONFIG, DOMAIN9_POWER_FORCEON, force_on);
 210
 211         /* DCS0/1/2/3/4/5 */
 212         REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN16_POWER_FORCEON, force_on);
 213         REG_UPDATE(DOMAIN17_PG_CONFIG, DOMAIN17_POWER_FORCEON, force_on);
 214         REG_UPDATE(DOMAIN18_PG_CONFIG, DOMAIN18_POWER_FORCEON, force_on);
 215         if (REG(DOMAIN19_PG_CONFIG))
 216                 REG_UPDATE(DOMAIN19_PG_CONFIG, DOMAIN19_POWER_FORCEON, force_on);
 217         if (REG(DOMAIN20_PG_CONFIG))
 218                 REG_UPDATE(DOMAIN20_PG_CONFIG, DOMAIN20_POWER_FORCEON, force_on);
 219         if (REG(DOMAIN21_PG_CONFIG))
 220                 REG_UPDATE(DOMAIN21_PG_CONFIG, DOMAIN21_POWER_FORCEON, force_on);
 221 }
 222
 223 void dcn20_dccg_init(struct dce_hwseq *hws)
 224 {
 225         /*
 226          * set MICROSECOND_TIME_BASE_DIV
 227          * 100Mhz refclk -> 0x120264
 228          * 27Mhz refclk -> 0x12021b
 229          * 48Mhz refclk -> 0x120230
 230          *
 231          */
 232         REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264);
 233
 234         /*
 235          * set MILLISECOND_TIME_BASE_DIV
 236          * 100Mhz refclk -> 0x1186a0
 237          * 27Mhz refclk -> 0x106978
 238          * 48Mhz refclk -> 0x10bb80
 239          *
 240          */
 241         REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
 242
 243         /* This value is dependent on the hardware pipeline delay so set once per SOC */
 244         REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x801003c);
 245 }
 246
 247 void dcn20_disable_vga(
 248         struct dce_hwseq *hws)
 249 {
 250         REG_WRITE(D1VGA_CONTROL, 0);
 251         REG_WRITE(D2VGA_CONTROL, 0);
 252         REG_WRITE(D3VGA_CONTROL, 0);
 253         REG_WRITE(D4VGA_CONTROL, 0);
 254         REG_WRITE(D5VGA_CONTROL, 0);
 255         REG_WRITE(D6VGA_CONTROL, 0);
 256 }
 257
 258 void dcn20_program_triple_buffer(
 259         const struct dc *dc,
 260         struct pipe_ctx *pipe_ctx,
 261         bool enable_triple_buffer)
 262 {
 263         if (pipe_ctx->plane_res.hubp && pipe_ctx->plane_res.hubp->funcs) {
 264                 pipe_ctx->plane_res.hubp->funcs->hubp_enable_tripleBuffer(
 265                         pipe_ctx->plane_res.hubp,
 266                         enable_triple_buffer);
 267         }
 268 }
 269
 270 /* Blank pixel data during initialization */
 271 void dcn20_init_blank(
 272                 struct dc *dc,
 273                 struct timing_generator *tg)
 274 {
 275         enum dc_color_space color_space;
 276         struct tg_color black_color = {0};
 277         struct output_pixel_processor *opp = NULL;
 278         struct output_pixel_processor *bottom_opp = NULL;
 279         uint32_t num_opps, opp_id_src0, opp_id_src1;
 280         uint32_t otg_active_width, otg_active_height;
 281
 282         /* program opp dpg blank color */
 283         color_space = COLOR_SPACE_SRGB;
 284         color_space_to_black_color(dc, color_space, &black_color);
 285
 286         /* get the OTG active size */
 287         tg->funcs->get_otg_active_size(tg,
 288                         &otg_active_width,
 289                         &otg_active_height);
 290
 291         /* get the OPTC source */
 292         tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1);
 293         ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp);
 294         opp = dc->res_pool->opps[opp_id_src0];
 295
 296         if (num_opps == 2) {
 297                 otg_active_width = otg_active_width / 2;
 298                 ASSERT(opp_id_src1 < dc->res_pool->res_cap->num_opp);
 299                 bottom_opp = dc->res_pool->opps[opp_id_src1];
 300         }
 301
 302         opp->funcs->opp_set_disp_pattern_generator(
 303                         opp,
 304                         CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
 305                         CONTROLLER_DP_COLOR_SPACE_UDEFINED,
 306                         COLOR_DEPTH_UNDEFINED,
 307                         &black_color,
 308                         otg_active_width,
 309                         otg_active_height);
 310
 311         if (num_opps == 2) {
 312                 bottom_opp->funcs->opp_set_disp_pattern_generator(
 313                                 bottom_opp,
 314                                 CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR,
 315                                 CONTROLLER_DP_COLOR_SPACE_UDEFINED,
 316                                 COLOR_DEPTH_UNDEFINED,
 317                                 &black_color,
 318                                 otg_active_width,
 319                                 otg_active_height);
 320         }
 321
 322         dc->hwss.wait_for_blank_complete(opp);
 323 }
 324
 325 void dcn20_dsc_pg_control(
 326                 struct dce_hwseq *hws,
 327                 unsigned int dsc_inst,
 328                 bool power_on)
 329 {
 330         uint32_t power_gate = power_on ? 0 : 1;
 331         uint32_t pwr_status = power_on ? 0 : 2;
 332         uint32_t org_ip_request_cntl = 0;
 333
 334         if (hws->ctx->dc->debug.disable_dsc_power_gate)
 335                 return;
 336
 337         if (REG(DOMAIN16_PG_CONFIG) == 0)
 338                 return;
 339
 340         REG_GET(DC_IP_REQUEST_CNTL, IP_REQUEST_EN, &org_ip_request_cntl);
 341         if (org_ip_request_cntl == 0)
 342                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1);
 343
 344         switch (dsc_inst) {
 345         case 0: /* DSC0 */
 346                 REG_UPDATE(DOMAIN16_PG_CONFIG,
 347                                 DOMAIN16_POWER_GATE, power_gate);
 348
 349                 REG_WAIT(DOMAIN16_PG_STATUS,
 350                                 DOMAIN16_PGFSM_PWR_STATUS, pwr_status,
 351                                 1, 1000);
 352                 break;
 353         case 1: /* DSC1 */
 354                 REG_UPDATE(DOMAIN17_PG_CONFIG,
 355                                 DOMAIN17_POWER_GATE, power_gate);
 356
 357                 REG_WAIT(DOMAIN17_PG_STATUS,
 358                                 DOMAIN17_PGFSM_PWR_STATUS, pwr_status,
 359                                 1, 1000);
 360                 break;
 361         case 2: /* DSC2 */
 362                 REG_UPDATE(DOMAIN18_PG_CONFIG,
 363                                 DOMAIN18_POWER_GATE, power_gate);
 364
 365                 REG_WAIT(DOMAIN18_PG_STATUS,
 366                                 DOMAIN18_PGFSM_PWR_STATUS, pwr_status,
 367                                 1, 1000);
 368                 break;
 369         case 3: /* DSC3 */
 370                 REG_UPDATE(DOMAIN19_PG_CONFIG,
 371                                 DOMAIN19_POWER_GATE, power_gate);
 372
 373                 REG_WAIT(DOMAIN19_PG_STATUS,
 374                                 DOMAIN19_PGFSM_PWR_STATUS, pwr_status,
 375                                 1, 1000);
 376                 break;
 377         case 4: /* DSC4 */
 378                 REG_UPDATE(DOMAIN20_PG_CONFIG,
 379                                 DOMAIN20_POWER_GATE, power_gate);
 380
 381                 REG_WAIT(DOMAIN20_PG_STATUS,
 382                                 DOMAIN20_PGFSM_PWR_STATUS, pwr_status,
 383                                 1, 1000);
 384                 break;
 385         case 5: /* DSC5 */
 386                 REG_UPDATE(DOMAIN21_PG_CONFIG,
 387                                 DOMAIN21_POWER_GATE, power_gate);
 388
 389                 REG_WAIT(DOMAIN21_PG_STATUS,
 390                                 DOMAIN21_PGFSM_PWR_STATUS, pwr_status,
 391                                 1, 1000);
 392                 break;
 393         default:
 394                 BREAK_TO_DEBUGGER();
 395                 break;
 396         }
 397
 398         if (org_ip_request_cntl == 0)
 399                 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0);
 400 }
 401
 402 void dcn20_dpp_pg_control(
 403                 struct dce_hwseq *hws,
 404                 unsigned int dpp_inst,
 405                 bool power_on)
 406 {
 407         uint32_t power_gate = power_on ? 0 : 1;
 408         uint32_t pwr_status = power_on ? 0 : 2;
 409
 410         if (hws->ctx->dc->debug.disable_dpp_power_gate)
 411                 return;
 412         if (REG(DOMAIN1_PG_CONFIG) == 0)
 413                 return;
 414
 415         switch (dpp_inst) {
 416         case 0: /* DPP0 */
 417                 REG_UPDATE(DOMAIN1_PG_CONFIG,
 418                                 DOMAIN1_POWER_GATE, power_gate);
 419
 420                 REG_WAIT(DOMAIN1_PG_STATUS,
 421                                 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
 422                                 1, 1000);
 423                 break;
 424         case 1: /* DPP1 */
 425                 REG_UPDATE(DOMAIN3_PG_CONFIG,
 426                                 DOMAIN3_POWER_GATE, power_gate);
 427
 428                 REG_WAIT(DOMAIN3_PG_STATUS,
 429                                 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
 430                                 1, 1000);
 431                 break;
 432         case 2: /* DPP2 */
 433                 REG_UPDATE(DOMAIN5_PG_CONFIG,
 434                                 DOMAIN5_POWER_GATE, power_gate);
 435
 436                 REG_WAIT(DOMAIN5_PG_STATUS,
 437                                 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
 438                                 1, 1000);
 439                 break;
 440         case 3: /* DPP3 */
 441                 REG_UPDATE(DOMAIN7_PG_CONFIG,
 442                                 DOMAIN7_POWER_GATE, power_gate);
 443
 444                 REG_WAIT(DOMAIN7_PG_STATUS,
 445                                 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
 446                                 1, 1000);
 447                 break;
 448         case 4: /* DPP4 */
 449                 REG_UPDATE(DOMAIN9_PG_CONFIG,
 450                                 DOMAIN9_POWER_GATE, power_gate);
 451
 452                 REG_WAIT(DOMAIN9_PG_STATUS,
 453                                 DOMAIN9_PGFSM_PWR_STATUS, pwr_status,
 454                                 1, 1000);
 455                 break;
 456         case 5: /* DPP5 */
 457                 /*
 458                  * Do not power gate DPP5, should be left at HW default, power on permanently.
 459                  * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
 460                  * reset.
 461                  * REG_UPDATE(DOMAIN11_PG_CONFIG,
 462                  *              DOMAIN11_POWER_GATE, power_gate);
 463                  *
 464                  * REG_WAIT(DOMAIN11_PG_STATUS,
 465                  *              DOMAIN11_PGFSM_PWR_STATUS, pwr_status,
 466                  *              1, 1000);
 467                  */
 468                 break;
 469         default:
 470                 BREAK_TO_DEBUGGER();
 471                 break;
 472         }
 473 }
 474
 475
 476 void dcn20_hubp_pg_control(
 477                 struct dce_hwseq *hws,
 478                 unsigned int hubp_inst,
 479                 bool power_on)
 480 {
 481         uint32_t power_gate = power_on ? 0 : 1;
 482         uint32_t pwr_status = power_on ? 0 : 2;
 483
 484         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 485                 return;
 486         if (REG(DOMAIN0_PG_CONFIG) == 0)
 487                 return;
 488
 489         switch (hubp_inst) {
 490         case 0: /* DCHUBP0 */
 491                 REG_UPDATE(DOMAIN0_PG_CONFIG,
 492                                 DOMAIN0_POWER_GATE, power_gate);
 493
 494                 REG_WAIT(DOMAIN0_PG_STATUS,
 495                                 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
 496                                 1, 1000);
 497                 break;
 498         case 1: /* DCHUBP1 */
 499                 REG_UPDATE(DOMAIN2_PG_CONFIG,
 500                                 DOMAIN2_POWER_GATE, power_gate);
 501
 502                 REG_WAIT(DOMAIN2_PG_STATUS,
 503                                 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
 504                                 1, 1000);
 505                 break;
 506         case 2: /* DCHUBP2 */
 507                 REG_UPDATE(DOMAIN4_PG_CONFIG,
 508                                 DOMAIN4_POWER_GATE, power_gate);
 509
 510                 REG_WAIT(DOMAIN4_PG_STATUS,
 511                                 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
 512                                 1, 1000);
 513                 break;
 514         case 3: /* DCHUBP3 */
 515                 REG_UPDATE(DOMAIN6_PG_CONFIG,
 516                                 DOMAIN6_POWER_GATE, power_gate);
 517
 518                 REG_WAIT(DOMAIN6_PG_STATUS,
 519                                 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
 520                                 1, 1000);
 521                 break;
 522         case 4: /* DCHUBP4 */
 523                 REG_UPDATE(DOMAIN8_PG_CONFIG,
 524                                 DOMAIN8_POWER_GATE, power_gate);
 525
 526                 REG_WAIT(DOMAIN8_PG_STATUS,
 527                                 DOMAIN8_PGFSM_PWR_STATUS, pwr_status,
 528                                 1, 1000);
 529                 break;
 530         case 5: /* DCHUBP5 */
 531                 /*
 532                  * Do not power gate DCHUB5, should be left at HW default, power on permanently.
 533                  * PG on Pipe5 is De-featured, attempting to put it to PG state may result in hard
 534                  * reset.
 535                  * REG_UPDATE(DOMAIN10_PG_CONFIG,
 536                  *              DOMAIN10_POWER_GATE, power_gate);
 537                  *
 538                  * REG_WAIT(DOMAIN10_PG_STATUS,
 539                  *              DOMAIN10_PGFSM_PWR_STATUS, pwr_status,
 540                  *              1, 1000);
 541                  */
 542                 break;
 543         default:
 544                 BREAK_TO_DEBUGGER();
 545                 break;
 546         }
 547 }
 548
 549
 550 /* disable HW used by plane.
 551  * note:  cannot disable until disconnect is complete
 552  */
 553 void dcn20_plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
 554 {
 555         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 556         struct dpp *dpp = pipe_ctx->plane_res.dpp;
 557
 558         dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
 559
 560         /* In flip immediate with pipe splitting case GSL is used for
 561          * synchronization so we must disable it when the plane is disabled.
 562          */
 563         if (pipe_ctx->stream_res.gsl_group != 0)
 564                 dcn20_setup_gsl_group_as_lock(dc, pipe_ctx, false);
 565
 566         dc->hwss.set_flip_control_gsl(pipe_ctx, false);
 567
 568         hubp->funcs->hubp_clk_cntl(hubp, false);
 569
 570         dpp->funcs->dpp_dppclk_control(dpp, false, false);
 571
 572         hubp->power_gated = true;
 573         dc->optimized_required = false; /* We're powering off, no need to optimize */
 574
 575         dc->hwss.plane_atomic_power_down(dc,
 576                         pipe_ctx->plane_res.dpp,
 577                         pipe_ctx->plane_res.hubp);
 578
 579         pipe_ctx->stream = NULL;
 580         memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
 581         memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
 582         pipe_ctx->top_pipe = NULL;
 583         pipe_ctx->bottom_pipe = NULL;
 584         pipe_ctx->plane_state = NULL;
 585 }
 586
 587
 588 void dcn20_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
 589 {
 590         DC_LOGGER_INIT(dc->ctx->logger);
 591
 592         if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
 593                 return;
 594
 595         dcn20_plane_atomic_disable(dc, pipe_ctx);
 596
 597         DC_LOG_DC("Power down front end %d\n",
 598                                         pipe_ctx->pipe_idx);
 599 }
 600
 601 enum dc_status dcn20_enable_stream_timing(
 602                 struct pipe_ctx *pipe_ctx,
 603                 struct dc_state *context,
 604                 struct dc *dc)
 605 {
 606         struct dc_stream_state *stream = pipe_ctx->stream;
 607         struct drr_params params = {0};
 608         unsigned int event_triggers = 0;
 609         struct pipe_ctx *odm_pipe;
 610         int opp_cnt = 1;
 611         int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
 612
 613         /* by upper caller loop, pipe0 is parent pipe and be called first.
 614          * back end is set up by for pipe0. Other children pipe share back end
 615          * with pipe 0. No program is needed.
 616          */
 617         if (pipe_ctx->top_pipe != NULL)
 618                 return DC_OK;
 619
 620         /* TODO check if timing_changed, disable stream if timing changed */
 621
 622         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 623                 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
 624                 opp_cnt++;
 625         }
 626
 627         if (opp_cnt > 1)
 628                 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
 629                                 pipe_ctx->stream_res.tg,
 630                                 opp_inst, opp_cnt,
 631                                 &pipe_ctx->stream->timing);
 632
 633         /* HW program guide assume display already disable
 634          * by unplug sequence. OTG assume stop.
 635          */
 636         pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
 637
 638         if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
 639                         pipe_ctx->clock_source,
 640                         &pipe_ctx->stream_res.pix_clk_params,
 641                         &pipe_ctx->pll_settings)) {
 642                 BREAK_TO_DEBUGGER();
 643                 return DC_ERROR_UNEXPECTED;
 644         }
 645
 646         pipe_ctx->stream_res.tg->funcs->program_timing(
 647                         pipe_ctx->stream_res.tg,
 648                         &stream->timing,
 649                         pipe_ctx->pipe_dlg_param.vready_offset,
 650                         pipe_ctx->pipe_dlg_param.vstartup_start,
 651                         pipe_ctx->pipe_dlg_param.vupdate_offset,
 652                         pipe_ctx->pipe_dlg_param.vupdate_width,
 653                         pipe_ctx->stream->signal,
 654                         true);
 655
 656         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
 657                 odm_pipe->stream_res.opp->funcs->opp_pipe_clock_control(
 658                                 odm_pipe->stream_res.opp,
 659                                 true);
 660
 661         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
 662                         pipe_ctx->stream_res.opp,
 663                         true);
 664
 665         dc->hwss.blank_pixel_data(dc, pipe_ctx, true);
 666
 667         /* VTG is  within DCHUB command block. DCFCLK is always on */
 668         if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
 669                 BREAK_TO_DEBUGGER();
 670                 return DC_ERROR_UNEXPECTED;
 671         }
 672
 673         dc->hwss.wait_for_blank_complete(pipe_ctx->stream_res.opp);
 674
 675         params.vertical_total_min = stream->adjust.v_total_min;
 676         params.vertical_total_max = stream->adjust.v_total_max;
 677         params.vertical_total_mid = stream->adjust.v_total_mid;
 678         params.vertical_total_mid_frame_num = stream->adjust.v_total_mid_frame_num;
 679         if (pipe_ctx->stream_res.tg->funcs->set_drr)
 680                 pipe_ctx->stream_res.tg->funcs->set_drr(
 681                         pipe_ctx->stream_res.tg, &params);
 682
 683         // DRR should set trigger event to monitor surface update event
 684         if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
 685                 event_triggers = 0x80;
 686         if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
 687                 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
 688                                 pipe_ctx->stream_res.tg, event_triggers);
 689
 690         /* TODO program crtc source select for non-virtual signal*/
 691         /* TODO program FMT */
 692         /* TODO setup link_enc */
 693         /* TODO set stream attributes */
 694         /* TODO program audio */
 695         /* TODO enable stream if timing changed */
 696         /* TODO unblank stream if DP */
 697
 698         return DC_OK;
 699 }
 700
 701 void dcn20_program_output_csc(struct dc *dc,
 702                 struct pipe_ctx *pipe_ctx,
 703                 enum dc_color_space colorspace,
 704                 uint16_t *matrix,
 705                 int opp_id)
 706 {
 707         struct mpc *mpc = dc->res_pool->mpc;
 708         enum mpc_output_csc_mode ocsc_mode = MPC_OUTPUT_CSC_COEF_A;
 709         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 710
 711         if (mpc->funcs->power_on_mpc_mem_pwr)
 712                 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
 713
 714         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
 715                 if (mpc->funcs->set_output_csc != NULL)
 716                         mpc->funcs->set_output_csc(mpc,
 717                                         opp_id,
 718                                         matrix,
 719                                         ocsc_mode);
 720         } else {
 721                 if (mpc->funcs->set_ocsc_default != NULL)
 722                         mpc->funcs->set_ocsc_default(mpc,
 723                                         opp_id,
 724                                         colorspace,
 725                                         ocsc_mode);
 726         }
 727 }
 728
 729 bool dcn20_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
 730                                 const struct dc_stream_state *stream)
 731 {
 732         int mpcc_id = pipe_ctx->plane_res.hubp->inst;
 733         struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
 734         struct pwl_params *params = NULL;
 735         /*
 736          * program OGAM only for the top pipe
 737          * if there is a pipe split then fix diagnostic is required:
 738          * how to pass OGAM parameter for stream.
 739          * if programming for all pipes is required then remove condition
 740          * pipe_ctx->top_pipe == NULL ,but then fix the diagnostic.
 741          */
 742         if (mpc->funcs->power_on_mpc_mem_pwr)
 743                 mpc->funcs->power_on_mpc_mem_pwr(mpc, mpcc_id, true);
 744         if (pipe_ctx->top_pipe == NULL
 745                         && mpc->funcs->set_output_gamma && stream->out_transfer_func) {
 746                 if (stream->out_transfer_func->type == TF_TYPE_HWPWL)
 747                         params = &stream->out_transfer_func->pwl;
 748                 else if (pipe_ctx->stream->out_transfer_func->type ==
 749                         TF_TYPE_DISTRIBUTED_POINTS &&
 750                         cm_helper_translate_curve_to_hw_format(
 751                         stream->out_transfer_func,
 752                         &mpc->blender_params, false))
 753                         params = &mpc->blender_params;
 754                 /*
 755                  * there is no ROM
 756                  */
 757                 if (stream->out_transfer_func->type == TF_TYPE_PREDEFINED)
 758                         BREAK_TO_DEBUGGER();
 759         }
 760         /*
 761          * if above if is not executed then 'params' equal to 0 and set in bypass
 762          */
 763         mpc->funcs->set_output_gamma(mpc, mpcc_id, params);
 764
 765         return true;
 766 }
 767
 768 bool dcn20_set_blend_lut(
 769         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
 770 {
 771         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 772         bool result = true;
 773         struct pwl_params *blend_lut = NULL;
 774
 775         if (plane_state->blend_tf) {
 776                 if (plane_state->blend_tf->type == TF_TYPE_HWPWL)
 777                         blend_lut = &plane_state->blend_tf->pwl;
 778                 else if (plane_state->blend_tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
 779                         cm_helper_translate_curve_to_hw_format(
 780                                         plane_state->blend_tf,
 781                                         &dpp_base->regamma_params, false);
 782                         blend_lut = &dpp_base->regamma_params;
 783                 }
 784         }
 785         result = dpp_base->funcs->dpp_program_blnd_lut(dpp_base, blend_lut);
 786
 787         return result;
 788 }
 789
 790 bool dcn20_set_shaper_3dlut(
 791         struct pipe_ctx *pipe_ctx, const struct dc_plane_state *plane_state)
 792 {
 793         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 794         bool result = true;
 795         struct pwl_params *shaper_lut = NULL;
 796
 797         if (plane_state->in_shaper_func) {
 798                 if (plane_state->in_shaper_func->type == TF_TYPE_HWPWL)
 799                         shaper_lut = &plane_state->in_shaper_func->pwl;
 800                 else if (plane_state->in_shaper_func->type == TF_TYPE_DISTRIBUTED_POINTS) {
 801                         cm_helper_translate_curve_to_hw_format(
 802                                         plane_state->in_shaper_func,
 803                                         &dpp_base->shaper_params, true);
 804                         shaper_lut = &dpp_base->shaper_params;
 805                 }
 806         }
 807
 808         result = dpp_base->funcs->dpp_program_shaper_lut(dpp_base, shaper_lut);
 809         if (plane_state->lut3d_func &&
 810                 plane_state->lut3d_func->state.bits.initialized == 1)
 811                 result = dpp_base->funcs->dpp_program_3dlut(dpp_base,
 812                                                                 &plane_state->lut3d_func->lut_3d);
 813         else
 814                 result = dpp_base->funcs->dpp_program_3dlut(dpp_base, NULL);
 815
 816         return result;
 817 }
 818
 819 bool dcn20_set_input_transfer_func(struct dc *dc,
 820                                 struct pipe_ctx *pipe_ctx,
 821                                 const struct dc_plane_state *plane_state)
 822 {
 823         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
 824         const struct dc_transfer_func *tf = NULL;
 825         bool result = true;
 826         bool use_degamma_ram = false;
 827
 828         if (dpp_base == NULL || plane_state == NULL)
 829                 return false;
 830
 831         dc->hwss.set_shaper_3dlut(pipe_ctx, plane_state);
 832         dc->hwss.set_blend_lut(pipe_ctx, plane_state);
 833
 834         if (plane_state->in_transfer_func)
 835                 tf = plane_state->in_transfer_func;
 836
 837
 838         if (tf == NULL) {
 839                 dpp_base->funcs->dpp_set_degamma(dpp_base,
 840                                 IPP_DEGAMMA_MODE_BYPASS);
 841                 return true;
 842         }
 843
 844         if (tf->type == TF_TYPE_HWPWL || tf->type == TF_TYPE_DISTRIBUTED_POINTS)
 845                 use_degamma_ram = true;
 846
 847         if (use_degamma_ram == true) {
 848                 if (tf->type == TF_TYPE_HWPWL)
 849                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
 850                                         &tf->pwl);
 851                 else if (tf->type == TF_TYPE_DISTRIBUTED_POINTS) {
 852                         cm_helper_translate_curve_to_degamma_hw_format(tf,
 853                                         &dpp_base->degamma_params);
 854                         dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
 855                                 &dpp_base->degamma_params);
 856                 }
 857                 return true;
 858         }
 859         /* handle here the optimized cases when de-gamma ROM could be used.
 860          *
 861          */
 862         if (tf->type == TF_TYPE_PREDEFINED) {
 863                 switch (tf->tf) {
 864                 case TRANSFER_FUNCTION_SRGB:
 865                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 866                                         IPP_DEGAMMA_MODE_HW_sRGB);
 867                         break;
 868                 case TRANSFER_FUNCTION_BT709:
 869                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 870                                         IPP_DEGAMMA_MODE_HW_xvYCC);
 871                         break;
 872                 case TRANSFER_FUNCTION_LINEAR:
 873                         dpp_base->funcs->dpp_set_degamma(dpp_base,
 874                                         IPP_DEGAMMA_MODE_BYPASS);
 875                         break;
 876                 case TRANSFER_FUNCTION_PQ:
 877                 default:
 878                         result = false;
 879                         break;
 880                 }
 881         } else if (tf->type == TF_TYPE_BYPASS)
 882                 dpp_base->funcs->dpp_set_degamma(dpp_base,
 883                                 IPP_DEGAMMA_MODE_BYPASS);
 884         else {
 885                 /*
 886                  * if we are here, we did not handle correctly.
 887                  * fix is required for this use case
 888                  */
 889                 BREAK_TO_DEBUGGER();
 890                 dpp_base->funcs->dpp_set_degamma(dpp_base,
 891                                 IPP_DEGAMMA_MODE_BYPASS);
 892         }
 893
 894         return result;
 895 }
 896
 897 void dcn20_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *pipe_ctx)
 898 {
 899         struct pipe_ctx *odm_pipe;
 900         int opp_cnt = 1;
 901         int opp_inst[MAX_PIPES] = { pipe_ctx->stream_res.opp->inst };
 902
 903         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 904                 opp_inst[opp_cnt] = odm_pipe->stream_res.opp->inst;
 905                 opp_cnt++;
 906         }
 907
 908         if (opp_cnt > 1)
 909                 pipe_ctx->stream_res.tg->funcs->set_odm_combine(
 910                                 pipe_ctx->stream_res.tg,
 911                                 opp_inst, opp_cnt,
 912                                 &pipe_ctx->stream->timing);
 913         else
 914                 pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
 915                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
 916 }
 917
 918 void dcn20_blank_pixel_data(
 919                 struct dc *dc,
 920                 struct pipe_ctx *pipe_ctx,
 921                 bool blank)
 922 {
 923         struct tg_color black_color = {0};
 924         struct stream_resource *stream_res = &pipe_ctx->stream_res;
 925         struct dc_stream_state *stream = pipe_ctx->stream;
 926         enum dc_color_space color_space = stream->output_color_space;
 927         enum controller_dp_test_pattern test_pattern = CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR;
 928         enum controller_dp_color_space test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_UDEFINED;
 929         struct pipe_ctx *odm_pipe;
 930         int odm_cnt = 1;
 931
 932         int width = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right;
 933         int height = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
 934
 935         /* get opp dpg blank color */
 936         color_space_to_black_color(dc, color_space, &black_color);
 937
 938         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
 939                 odm_cnt++;
 940
 941         width = width / odm_cnt;
 942
 943         if (blank) {
 944                 if (stream_res->abm)
 945                         stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm);
 946
 947                 if (dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE) {
 948                         test_pattern = CONTROLLER_DP_TEST_PATTERN_COLORSQUARES;
 949                         test_pattern_color_space = CONTROLLER_DP_COLOR_SPACE_RGB;
 950                 }
 951         } else {
 952                 test_pattern = CONTROLLER_DP_TEST_PATTERN_VIDEOMODE;
 953         }
 954
 955         stream_res->opp->funcs->opp_set_disp_pattern_generator(
 956                         stream_res->opp,
 957                         test_pattern,
 958                         test_pattern_color_space,
 959                         stream->timing.display_color_depth,
 960                         &black_color,
 961                         width,
 962                         height);
 963
 964         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
 965                 odm_pipe->stream_res.opp->funcs->opp_set_disp_pattern_generator(
 966                                 odm_pipe->stream_res.opp,
 967                                 dc->debug.visual_confirm != VISUAL_CONFIRM_DISABLE && blank ?
 968                                                 CONTROLLER_DP_TEST_PATTERN_COLORRAMP : test_pattern,
 969                                 test_pattern_color_space,
 970                                 stream->timing.display_color_depth,
 971                                 &black_color,
 972                                 width,
 973                                 height);
 974         }
 975
 976         if (!blank)
 977                 if (stream_res->abm) {
 978                         stream_res->abm->funcs->set_pipe(stream_res->abm, stream_res->tg->inst + 1);
 979                         stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
 980                 }
 981 }
 982
 983
 984 static void dcn20_power_on_plane(
 985         struct dce_hwseq *hws,
 986         struct pipe_ctx *pipe_ctx)
 987 {
 988         DC_LOGGER_INIT(hws->ctx->logger);
 989         if (REG(DC_IP_REQUEST_CNTL)) {
 990                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 991                                 IP_REQUEST_EN, 1);
 992                 dcn20_dpp_pg_control(hws, pipe_ctx->plane_res.dpp->inst, true);
 993                 dcn20_hubp_pg_control(hws, pipe_ctx->plane_res.hubp->inst, true);
 994                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 995                                 IP_REQUEST_EN, 0);
 996                 DC_LOG_DEBUG(
 997                                 "Un-gated front end for pipe %d\n", pipe_ctx->plane_res.hubp->inst);
 998         }
 999 }
1000
1001 void dcn20_enable_plane(
1002         struct dc *dc,
1003         struct pipe_ctx *pipe_ctx,
1004         struct dc_state *context)
1005 {
1006         //if (dc->debug.sanity_checks) {
1007         //      dcn10_verify_allow_pstate_change_high(dc);
1008         //}
1009         dcn20_power_on_plane(dc->hwseq, pipe_ctx);
1010
1011         /* enable DCFCLK current DCHUB */
1012         pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1013
1014         /* initialize HUBP on power up */
1015         pipe_ctx->plane_res.hubp->funcs->hubp_init(pipe_ctx->plane_res.hubp);
1016
1017         /* make sure OPP_PIPE_CLOCK_EN = 1 */
1018         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1019                         pipe_ctx->stream_res.opp,
1020                         true);
1021
1022 /* TODO: enable/disable in dm as per update type.
1023         if (plane_state) {
1024                 DC_LOG_DC(dc->ctx->logger,
1025                                 "Pipe:%d 0x%x: addr hi:0x%x, "
1026                                 "addr low:0x%x, "
1027                                 "src: %d, %d, %d,"
1028                                 " %d; dst: %d, %d, %d, %d;\n",
1029                                 pipe_ctx->pipe_idx,
1030                                 plane_state,
1031                                 plane_state->address.grph.addr.high_part,
1032                                 plane_state->address.grph.addr.low_part,
1033                                 plane_state->src_rect.x,
1034                                 plane_state->src_rect.y,
1035                                 plane_state->src_rect.width,
1036                                 plane_state->src_rect.height,
1037                                 plane_state->dst_rect.x,
1038                                 plane_state->dst_rect.y,
1039                                 plane_state->dst_rect.width,
1040                                 plane_state->dst_rect.height);
1041
1042                 DC_LOG_DC(dc->ctx->logger,
1043                                 "Pipe %d: width, height, x, y         format:%d\n"
1044                                 "viewport:%d, %d, %d, %d\n"
1045                                 "recout:  %d, %d, %d, %d\n",
1046                                 pipe_ctx->pipe_idx,
1047                                 plane_state->format,
1048                                 pipe_ctx->plane_res.scl_data.viewport.width,
1049                                 pipe_ctx->plane_res.scl_data.viewport.height,
1050                                 pipe_ctx->plane_res.scl_data.viewport.x,
1051                                 pipe_ctx->plane_res.scl_data.viewport.y,
1052                                 pipe_ctx->plane_res.scl_data.recout.width,
1053                                 pipe_ctx->plane_res.scl_data.recout.height,
1054                                 pipe_ctx->plane_res.scl_data.recout.x,
1055                                 pipe_ctx->plane_res.scl_data.recout.y);
1056                 print_rq_dlg_ttu(dc, pipe_ctx);
1057         }
1058 */
1059         if (dc->vm_pa_config.valid) {
1060                 struct vm_system_aperture_param apt;
1061
1062                 apt.sys_default.quad_part = 0;
1063
1064                 apt.sys_low.quad_part = dc->vm_pa_config.system_aperture.start_addr;
1065                 apt.sys_high.quad_part = dc->vm_pa_config.system_aperture.end_addr;
1066
1067                 // Program system aperture settings
1068                 pipe_ctx->plane_res.hubp->funcs->hubp_set_vm_system_aperture_settings(pipe_ctx->plane_res.hubp, &apt);
1069         }
1070
1071 //      if (dc->debug.sanity_checks) {
1072 //              dcn10_verify_allow_pstate_change_high(dc);
1073 //      }
1074 }
1075
1076
1077 void dcn20_pipe_control_lock_global(
1078                 struct dc *dc,
1079                 struct pipe_ctx *pipe,
1080                 bool lock)
1081 {
1082         if (lock) {
1083                 pipe->stream_res.tg->funcs->lock_doublebuffer_enable(
1084                                 pipe->stream_res.tg);
1085                 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1086         } else {
1087                 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1088                 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,
1089                                 CRTC_STATE_VACTIVE);
1090                 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,
1091                                 CRTC_STATE_VBLANK);
1092                 pipe->stream_res.tg->funcs->wait_for_state(pipe->stream_res.tg,
1093                                 CRTC_STATE_VACTIVE);
1094                 pipe->stream_res.tg->funcs->lock_doublebuffer_disable(
1095                                 pipe->stream_res.tg);
1096         }
1097 }
1098
1099 void dcn20_pipe_control_lock(
1100         struct dc *dc,
1101         struct pipe_ctx *pipe,
1102         bool lock)
1103 {
1104         bool flip_immediate = false;
1105
1106         /* use TG master update lock to lock everything on the TG
1107          * therefore only top pipe need to lock
1108          */
1109         if (pipe->top_pipe)
1110                 return;
1111
1112         if (pipe->plane_state != NULL)
1113                 flip_immediate = pipe->plane_state->flip_immediate;
1114
1115         if (flip_immediate && lock) {
1116                 const int TIMEOUT_FOR_FLIP_PENDING = 100000;
1117                 int i;
1118
1119                 for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
1120                         if (!pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->plane_res.hubp))
1121                                 break;
1122                         udelay(1);
1123                 }
1124
1125                 if (pipe->bottom_pipe != NULL) {
1126                         for (i = 0; i < TIMEOUT_FOR_FLIP_PENDING; ++i) {
1127                                 if (!pipe->bottom_pipe->plane_res.hubp->funcs->hubp_is_flip_pending(pipe->bottom_pipe->plane_res.hubp))
1128                                         break;
1129                                 udelay(1);
1130                         }
1131                 }
1132         }
1133
1134         /* In flip immediate and pipe splitting case, we need to use GSL
1135          * for synchronization. Only do setup on locking and on flip type change.
1136          */
1137         if (lock && pipe->bottom_pipe != NULL)
1138                 if ((flip_immediate && pipe->stream_res.gsl_group == 0) ||
1139                     (!flip_immediate && pipe->stream_res.gsl_group > 0))
1140                         dcn20_setup_gsl_group_as_lock(dc, pipe, flip_immediate);
1141
1142         if (pipe->plane_state != NULL && pipe->plane_state->triplebuffer_flips) {
1143                 if (lock)
1144                         pipe->stream_res.tg->funcs->triplebuffer_lock(pipe->stream_res.tg);
1145                 else
1146                         pipe->stream_res.tg->funcs->triplebuffer_unlock(pipe->stream_res.tg);
1147         } else {
1148                 if (lock)
1149                         pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1150                 else
1151                         pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1152         }
1153 }
1154
1155 static void dcn20_detect_pipe_changes(struct pipe_ctx *old_pipe, struct pipe_ctx *new_pipe)
1156 {
1157         new_pipe->update_flags.raw = 0;
1158
1159         /* Exit on unchanged, unused pipe */
1160         if (!old_pipe->plane_state && !new_pipe->plane_state)
1161                 return;
1162         /* Detect pipe enable/disable */
1163         if (!old_pipe->plane_state && new_pipe->plane_state) {
1164                 new_pipe->update_flags.bits.enable = 1;
1165                 new_pipe->update_flags.bits.mpcc = 1;
1166                 new_pipe->update_flags.bits.dppclk = 1;
1167                 new_pipe->update_flags.bits.hubp_interdependent = 1;
1168                 new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1169                 new_pipe->update_flags.bits.gamut_remap = 1;
1170                 new_pipe->update_flags.bits.scaler = 1;
1171                 new_pipe->update_flags.bits.viewport = 1;
1172                 if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1173                         new_pipe->update_flags.bits.odm = 1;
1174                         new_pipe->update_flags.bits.global_sync = 1;
1175                 }
1176                 return;
1177         }
1178         if (old_pipe->plane_state && !new_pipe->plane_state) {
1179                 new_pipe->update_flags.bits.disable = 1;
1180                 return;
1181         }
1182
1183         /* Detect top pipe only changes */
1184         if (!new_pipe->top_pipe && !new_pipe->prev_odm_pipe) {
1185                 /* Detect odm changes */
1186                 if ((old_pipe->next_odm_pipe && new_pipe->next_odm_pipe
1187                         && old_pipe->next_odm_pipe->pipe_idx != new_pipe->next_odm_pipe->pipe_idx)
1188                                 || (!old_pipe->next_odm_pipe && new_pipe->next_odm_pipe)
1189                                 || (old_pipe->next_odm_pipe && !new_pipe->next_odm_pipe)
1190                                 || old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1191                         new_pipe->update_flags.bits.odm = 1;
1192
1193                 /* Detect global sync changes */
1194                 if (old_pipe->pipe_dlg_param.vready_offset != new_pipe->pipe_dlg_param.vready_offset
1195                                 || old_pipe->pipe_dlg_param.vstartup_start != new_pipe->pipe_dlg_param.vstartup_start
1196                                 || old_pipe->pipe_dlg_param.vupdate_offset != new_pipe->pipe_dlg_param.vupdate_offset
1197                                 || old_pipe->pipe_dlg_param.vupdate_width != new_pipe->pipe_dlg_param.vupdate_width)
1198                         new_pipe->update_flags.bits.global_sync = 1;
1199         }
1200
1201         /*
1202          * Detect opp / tg change, only set on change, not on enable
1203          * Assume mpcc inst = pipe index, if not this code needs to be updated
1204          * since mpcc is what is affected by these. In fact all of our sequence
1205          * makes this assumption at the moment with how hubp reset is matched to
1206          * same index mpcc reset.
1207          */
1208         if (old_pipe->stream_res.opp != new_pipe->stream_res.opp)
1209                 new_pipe->update_flags.bits.opp_changed = 1;
1210         if (old_pipe->stream_res.tg != new_pipe->stream_res.tg)
1211                 new_pipe->update_flags.bits.tg_changed = 1;
1212
1213         /* Detect mpcc blending changes, only dpp inst and bot matter here */
1214         if (old_pipe->plane_res.dpp != new_pipe->plane_res.dpp
1215                         || old_pipe->stream_res.opp != new_pipe->stream_res.opp
1216                         || (!old_pipe->bottom_pipe && new_pipe->bottom_pipe)
1217                         || (old_pipe->bottom_pipe && !new_pipe->bottom_pipe)
1218                         || (old_pipe->bottom_pipe && new_pipe->bottom_pipe
1219                                 && old_pipe->bottom_pipe->plane_res.mpcc_inst
1220                                         != new_pipe->bottom_pipe->plane_res.mpcc_inst))
1221                 new_pipe->update_flags.bits.mpcc = 1;
1222
1223         /* Detect dppclk change */
1224         if (old_pipe->plane_res.bw.dppclk_khz != new_pipe->plane_res.bw.dppclk_khz)
1225                 new_pipe->update_flags.bits.dppclk = 1;
1226
1227         /* Check for scl update */
1228         if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data)))
1229                         new_pipe->update_flags.bits.scaler = 1;
1230         /* Check for vp update */
1231         if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(struct rect))
1232                         || memcmp(&old_pipe->plane_res.scl_data.viewport_c,
1233                                 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect)))
1234                 new_pipe->update_flags.bits.viewport = 1;
1235
1236         /* Detect dlg/ttu/rq updates */
1237         {
1238                 struct _vcs_dpi_display_dlg_regs_st old_dlg_attr = old_pipe->dlg_regs;
1239                 struct _vcs_dpi_display_ttu_regs_st old_ttu_attr = old_pipe->ttu_regs;
1240                 struct _vcs_dpi_display_dlg_regs_st *new_dlg_attr = &new_pipe->dlg_regs;
1241                 struct _vcs_dpi_display_ttu_regs_st *new_ttu_attr = &new_pipe->ttu_regs;
1242
1243                 /* Detect pipe interdependent updates */
1244                 if (old_dlg_attr.dst_y_prefetch != new_dlg_attr->dst_y_prefetch ||
1245                                 old_dlg_attr.vratio_prefetch != new_dlg_attr->vratio_prefetch ||
1246                                 old_dlg_attr.vratio_prefetch_c != new_dlg_attr->vratio_prefetch_c ||
1247                                 old_dlg_attr.dst_y_per_vm_vblank != new_dlg_attr->dst_y_per_vm_vblank ||
1248                                 old_dlg_attr.dst_y_per_row_vblank != new_dlg_attr->dst_y_per_row_vblank ||
1249                                 old_dlg_attr.dst_y_per_vm_flip != new_dlg_attr->dst_y_per_vm_flip ||
1250                                 old_dlg_attr.dst_y_per_row_flip != new_dlg_attr->dst_y_per_row_flip ||
1251                                 old_dlg_attr.refcyc_per_meta_chunk_vblank_l != new_dlg_attr->refcyc_per_meta_chunk_vblank_l ||
1252                                 old_dlg_attr.refcyc_per_meta_chunk_vblank_c != new_dlg_attr->refcyc_per_meta_chunk_vblank_c ||
1253                                 old_dlg_attr.refcyc_per_meta_chunk_flip_l != new_dlg_attr->refcyc_per_meta_chunk_flip_l ||
1254                                 old_dlg_attr.refcyc_per_line_delivery_pre_l != new_dlg_attr->refcyc_per_line_delivery_pre_l ||
1255                                 old_dlg_attr.refcyc_per_line_delivery_pre_c != new_dlg_attr->refcyc_per_line_delivery_pre_c ||
1256                                 old_ttu_attr.refcyc_per_req_delivery_pre_l != new_ttu_attr->refcyc_per_req_delivery_pre_l ||
1257                                 old_ttu_attr.refcyc_per_req_delivery_pre_c != new_ttu_attr->refcyc_per_req_delivery_pre_c ||
1258                                 old_ttu_attr.refcyc_per_req_delivery_pre_cur0 != new_ttu_attr->refcyc_per_req_delivery_pre_cur0 ||
1259                                 old_ttu_attr.refcyc_per_req_delivery_pre_cur1 != new_ttu_attr->refcyc_per_req_delivery_pre_cur1 ||
1260                                 old_ttu_attr.min_ttu_vblank != new_ttu_attr->min_ttu_vblank ||
1261                                 old_ttu_attr.qos_level_flip != new_ttu_attr->qos_level_flip) {
1262                         old_dlg_attr.dst_y_prefetch = new_dlg_attr->dst_y_prefetch;
1263                         old_dlg_attr.vratio_prefetch = new_dlg_attr->vratio_prefetch;
1264                         old_dlg_attr.vratio_prefetch_c = new_dlg_attr->vratio_prefetch_c;
1265                         old_dlg_attr.dst_y_per_vm_vblank = new_dlg_attr->dst_y_per_vm_vblank;
1266                         old_dlg_attr.dst_y_per_row_vblank = new_dlg_attr->dst_y_per_row_vblank;
1267                         old_dlg_attr.dst_y_per_vm_flip = new_dlg_attr->dst_y_per_vm_flip;
1268                         old_dlg_attr.dst_y_per_row_flip = new_dlg_attr->dst_y_per_row_flip;
1269                         old_dlg_attr.refcyc_per_meta_chunk_vblank_l = new_dlg_attr->refcyc_per_meta_chunk_vblank_l;
1270                         old_dlg_attr.refcyc_per_meta_chunk_vblank_c = new_dlg_attr->refcyc_per_meta_chunk_vblank_c;
1271                         old_dlg_attr.refcyc_per_meta_chunk_flip_l = new_dlg_attr->refcyc_per_meta_chunk_flip_l;
1272                         old_dlg_attr.refcyc_per_line_delivery_pre_l = new_dlg_attr->refcyc_per_line_delivery_pre_l;
1273                         old_dlg_attr.refcyc_per_line_delivery_pre_c = new_dlg_attr->refcyc_per_line_delivery_pre_c;
1274                         old_ttu_attr.refcyc_per_req_delivery_pre_l = new_ttu_attr->refcyc_per_req_delivery_pre_l;
1275                         old_ttu_attr.refcyc_per_req_delivery_pre_c = new_ttu_attr->refcyc_per_req_delivery_pre_c;
1276                         old_ttu_attr.refcyc_per_req_delivery_pre_cur0 = new_ttu_attr->refcyc_per_req_delivery_pre_cur0;
1277                         old_ttu_attr.refcyc_per_req_delivery_pre_cur1 = new_ttu_attr->refcyc_per_req_delivery_pre_cur1;
1278                         old_ttu_attr.min_ttu_vblank = new_ttu_attr->min_ttu_vblank;
1279                         old_ttu_attr.qos_level_flip = new_ttu_attr->qos_level_flip;
1280                         new_pipe->update_flags.bits.hubp_interdependent = 1;
1281                 }
1282                 /* Detect any other updates to ttu/rq/dlg */
1283                 if (memcmp(&old_dlg_attr, &new_pipe->dlg_regs, sizeof(old_dlg_attr)) ||
1284                                 memcmp(&old_ttu_attr, &new_pipe->ttu_regs, sizeof(old_ttu_attr)) ||
1285                                 memcmp(&old_pipe->rq_regs, &new_pipe->rq_regs, sizeof(old_pipe->rq_regs)))
1286                         new_pipe->update_flags.bits.hubp_rq_dlg_ttu = 1;
1287         }
1288 }
1289
1290 static void dcn20_update_dchubp_dpp(
1291         struct dc *dc,
1292         struct pipe_ctx *pipe_ctx,
1293         struct dc_state *context)
1294 {
1295         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1296         struct dpp *dpp = pipe_ctx->plane_res.dpp;
1297         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1298
1299         if (pipe_ctx->update_flags.bits.dppclk)
1300                 dpp->funcs->dpp_dppclk_control(dpp, false, true);
1301
1302         /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
1303          * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
1304          * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
1305          */
1306         if (pipe_ctx->update_flags.bits.hubp_rq_dlg_ttu) {
1307                 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
1308
1309                 hubp->funcs->hubp_setup(
1310                         hubp,
1311                         &pipe_ctx->dlg_regs,
1312                         &pipe_ctx->ttu_regs,
1313                         &pipe_ctx->rq_regs,
1314                         &pipe_ctx->pipe_dlg_param);
1315         }
1316         if (pipe_ctx->update_flags.bits.hubp_interdependent)
1317                 hubp->funcs->hubp_setup_interdependent(
1318                         hubp,
1319                         &pipe_ctx->dlg_regs,
1320                         &pipe_ctx->ttu_regs);
1321
1322         if (pipe_ctx->update_flags.bits.enable ||
1323                         plane_state->update_flags.bits.bpp_change ||
1324                         plane_state->update_flags.bits.input_csc_change ||
1325                         plane_state->update_flags.bits.color_space_change ||
1326                         plane_state->update_flags.bits.coeff_reduction_change) {
1327                 struct dc_bias_and_scale bns_params = {0};
1328
1329                 // program the input csc
1330                 dpp->funcs->dpp_setup(dpp,
1331                                 plane_state->format,
1332                                 EXPANSION_MODE_ZERO,
1333                                 plane_state->input_csc_color_matrix,
1334                                 plane_state->color_space,
1335                                 NULL);
1336
1337                 if (dpp->funcs->dpp_program_bias_and_scale) {
1338                         //TODO :for CNVC set scale and bias registers if necessary
1339                         build_prescale_params(&bns_params, plane_state);
1340                         dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1341                 }
1342         }
1343
1344         if (pipe_ctx->update_flags.bits.mpcc
1345                         || plane_state->update_flags.bits.global_alpha_change
1346                         || plane_state->update_flags.bits.per_pixel_alpha_change) {
1347                 /* Need mpcc to be idle if changing opp */
1348                 if (pipe_ctx->update_flags.bits.opp_changed) {
1349                         struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
1350                         int mpcc_inst;
1351
1352                         for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
1353                                 if (!old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst])
1354                                         continue;
1355                                 dc->res_pool->mpc->funcs->wait_for_idle(dc->res_pool->mpc, mpcc_inst);
1356                                 old_pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
1357                         }
1358                 }
1359                 dc->hwss.update_mpcc(dc, pipe_ctx);
1360         }
1361
1362         if (pipe_ctx->update_flags.bits.scaler ||
1363                         plane_state->update_flags.bits.scaling_change ||
1364                         plane_state->update_flags.bits.position_change ||
1365                         plane_state->update_flags.bits.per_pixel_alpha_change ||
1366                         pipe_ctx->stream->update_flags.bits.scaling) {
1367                 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha;
1368                 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_30BPP);
1369                 /* scaler configuration */
1370                 pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
1371                                 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
1372         }
1373
1374         if (pipe_ctx->update_flags.bits.viewport ||
1375                         (context == dc->current_state && plane_state->update_flags.bits.scaling_change) ||
1376                         (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling))
1377                 hubp->funcs->mem_program_viewport(
1378                         hubp,
1379                         &pipe_ctx->plane_res.scl_data.viewport,
1380                         &pipe_ctx->plane_res.scl_data.viewport_c);
1381
1382         /* Any updates are handled in dc interface, just need to apply existing for plane enable */
1383         if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed)
1384                         && pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
1385                 dc->hwss.set_cursor_position(pipe_ctx);
1386                 dc->hwss.set_cursor_attribute(pipe_ctx);
1387
1388                 if (dc->hwss.set_cursor_sdr_white_level)
1389                         dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
1390         }
1391
1392         /* Any updates are handled in dc interface, just need
1393          * to apply existing for plane enable / opp change */
1394         if (pipe_ctx->update_flags.bits.enable || pipe_ctx->update_flags.bits.opp_changed
1395                         || pipe_ctx->stream->update_flags.bits.gamut_remap
1396                         || pipe_ctx->stream->update_flags.bits.out_csc) {
1397                         /* dpp/cm gamut remap*/
1398                         dc->hwss.program_gamut_remap(pipe_ctx);
1399
1400                 /*call the dcn2 method which uses mpc csc*/
1401                 dc->hwss.program_output_csc(dc,
1402                                 pipe_ctx,
1403                                 pipe_ctx->stream->output_color_space,
1404                                 pipe_ctx->stream->csc_color_matrix.matrix,
1405                                 hubp->opp_id);
1406         }
1407
1408         if (pipe_ctx->update_flags.bits.enable ||
1409                         pipe_ctx->update_flags.bits.opp_changed ||
1410                         plane_state->update_flags.bits.pixel_format_change ||
1411                         plane_state->update_flags.bits.horizontal_mirror_change ||
1412                         plane_state->update_flags.bits.rotation_change ||
1413                         plane_state->update_flags.bits.swizzle_change ||
1414                         plane_state->update_flags.bits.dcc_change ||
1415                         plane_state->update_flags.bits.bpp_change ||
1416                         plane_state->update_flags.bits.scaling_change ||
1417                         plane_state->update_flags.bits.plane_size_change) {
1418                 struct plane_size size = plane_state->plane_size;
1419
1420                 size.surface_size = pipe_ctx->plane_res.scl_data.viewport;
1421                 hubp->funcs->hubp_program_surface_config(
1422                         hubp,
1423                         plane_state->format,
1424                         &plane_state->tiling_info,
1425                         &size,
1426                         plane_state->rotation,
1427                         &plane_state->dcc,
1428                         plane_state->horizontal_mirror,
1429                         0);
1430                 hubp->power_gated = false;
1431         }
1432
1433         if (pipe_ctx->update_flags.bits.enable || plane_state->update_flags.bits.addr_update)
1434                 dc->hwss.update_plane_addr(dc, pipe_ctx);
1435
1436         if (pipe_ctx->update_flags.bits.enable)
1437                 hubp->funcs->set_blank(hubp, false);
1438 }
1439
1440
1441 static void dcn20_program_pipe(
1442                 struct dc *dc,
1443                 struct pipe_ctx *pipe_ctx,
1444                 struct dc_state *context)
1445 {
1446         /* Only need to unblank on top pipe */
1447         if ((pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.abm_level)
1448                         && !pipe_ctx->top_pipe && !pipe_ctx->prev_odm_pipe)
1449                 dc->hwss.blank_pixel_data(dc, pipe_ctx, !pipe_ctx->plane_state->visible);
1450
1451         if (pipe_ctx->update_flags.bits.global_sync) {
1452                 pipe_ctx->stream_res.tg->funcs->program_global_sync(
1453                                 pipe_ctx->stream_res.tg,
1454                                 pipe_ctx->pipe_dlg_param.vready_offset,
1455                                 pipe_ctx->pipe_dlg_param.vstartup_start,
1456                                 pipe_ctx->pipe_dlg_param.vupdate_offset,
1457                                 pipe_ctx->pipe_dlg_param.vupdate_width);
1458
1459                 pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1460                                 pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1461
1462                 if (dc->hwss.setup_vupdate_interrupt)
1463                         dc->hwss.setup_vupdate_interrupt(dc, pipe_ctx);
1464         }
1465
1466         if (pipe_ctx->update_flags.bits.odm)
1467                 dc->hwss.update_odm(dc, context, pipe_ctx);
1468
1469         if (pipe_ctx->update_flags.bits.enable)
1470                 dcn20_enable_plane(dc, pipe_ctx, context);
1471
1472         if (pipe_ctx->update_flags.raw || pipe_ctx->plane_state->update_flags.raw || pipe_ctx->stream->update_flags.raw)
1473                 dcn20_update_dchubp_dpp(dc, pipe_ctx, context);
1474
1475         if (pipe_ctx->update_flags.bits.enable
1476                         || pipe_ctx->plane_state->update_flags.bits.hdr_mult)
1477                 dc->hwss.set_hdr_multiplier(pipe_ctx);
1478
1479         if (pipe_ctx->update_flags.bits.enable ||
1480                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
1481                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
1482                 dc->hwss.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
1483
1484         /* dcn10_translate_regamma_to_hw_format takes 750us to finish
1485          * only do gamma programming for powering on, internal memcmp to avoid
1486          * updating on slave planes
1487          */
1488         if (pipe_ctx->update_flags.bits.enable || pipe_ctx->stream->update_flags.bits.out_tf)
1489                 dc->hwss.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
1490
1491         /* If the pipe has been enabled or has a different opp, we
1492          * should reprogram the fmt. This deals with cases where
1493          * interation between mpc and odm combine on different streams
1494          * causes a different pipe to be chosen to odm combine with.
1495          */
1496         if (pipe_ctx->update_flags.bits.enable
1497             || pipe_ctx->update_flags.bits.opp_changed) {
1498
1499                 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1500                         pipe_ctx->stream_res.opp,
1501                         COLOR_SPACE_YCBCR601,
1502                         pipe_ctx->stream->timing.display_color_depth,
1503                         pipe_ctx->stream->signal);
1504
1505                 pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1506                         pipe_ctx->stream_res.opp,
1507                         &pipe_ctx->stream->bit_depth_params,
1508                         &pipe_ctx->stream->clamping);
1509         }
1510 }
1511
1512 static bool does_pipe_need_lock(struct pipe_ctx *pipe)
1513 {
1514         if ((pipe->plane_state && pipe->plane_state->update_flags.raw)
1515                         || pipe->update_flags.raw)
1516                 return true;
1517         if (pipe->bottom_pipe)
1518                 return does_pipe_need_lock(pipe->bottom_pipe);
1519
1520         return false;
1521 }
1522
1523 void dcn20_program_front_end_for_ctx(
1524                 struct dc *dc,
1525                 struct dc_state *context)
1526 {
1527         const unsigned int TIMEOUT_FOR_PIPE_ENABLE_MS = 100;
1528         int i;
1529         bool pipe_locked[MAX_PIPES] = {false};
1530         DC_LOGGER_INIT(dc->ctx->logger);
1531
1532         /* Carry over GSL groups in case the context is changing. */
1533         for (i = 0; i < dc->res_pool->pipe_count; i++)
1534                 if (context->res_ctx.pipe_ctx[i].stream == dc->current_state->res_ctx.pipe_ctx[i].stream)
1535                         context->res_ctx.pipe_ctx[i].stream_res.gsl_group =
1536                                 dc->current_state->res_ctx.pipe_ctx[i].stream_res.gsl_group;
1537
1538         /* Set pipe update flags and lock pipes */
1539         for (i = 0; i < dc->res_pool->pipe_count; i++)
1540                 dcn20_detect_pipe_changes(&dc->current_state->res_ctx.pipe_ctx[i],
1541                                 &context->res_ctx.pipe_ctx[i]);
1542         for (i = 0; i < dc->res_pool->pipe_count; i++)
1543                 if (!context->res_ctx.pipe_ctx[i].top_pipe &&
1544                                 does_pipe_need_lock(&context->res_ctx.pipe_ctx[i])) {
1545                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1546
1547                         if (pipe_ctx->update_flags.bits.tg_changed || pipe_ctx->update_flags.bits.enable)
1548                                 dc->hwss.pipe_control_lock(dc, pipe_ctx, true);
1549                         if (!pipe_ctx->update_flags.bits.enable)
1550                                 dc->hwss.pipe_control_lock(dc, &dc->current_state->res_ctx.pipe_ctx[i], true);
1551                         pipe_locked[i] = true;
1552                 }
1553
1554         /* OTG blank before disabling all front ends */
1555         for (i = 0; i < dc->res_pool->pipe_count; i++)
1556                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1557                                 && !context->res_ctx.pipe_ctx[i].top_pipe
1558                                 && !context->res_ctx.pipe_ctx[i].prev_odm_pipe
1559                                 && context->res_ctx.pipe_ctx[i].stream)
1560                         dc->hwss.blank_pixel_data(dc, &context->res_ctx.pipe_ctx[i], true);
1561
1562         /* Disconnect mpcc */
1563         for (i = 0; i < dc->res_pool->pipe_count; i++)
1564                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable
1565                                 || context->res_ctx.pipe_ctx[i].update_flags.bits.opp_changed) {
1566                         dc->hwss.plane_atomic_disconnect(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1567                         DC_LOG_DC("Reset mpcc for pipe %d\n", dc->current_state->res_ctx.pipe_ctx[i].pipe_idx);
1568                 }
1569
1570         /*
1571          * Program all updated pipes, order matters for mpcc setup. Start with
1572          * top pipe and program all pipes that follow in order
1573          */
1574         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1575                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1576
1577                 if (pipe->plane_state && !pipe->top_pipe) {
1578                         while (pipe) {
1579                                 dcn20_program_pipe(dc, pipe, context);
1580                                 pipe = pipe->bottom_pipe;
1581                         }
1582                         /* Program secondary blending tree and writeback pipes */
1583                         pipe = &context->res_ctx.pipe_ctx[i];
1584                         if (!pipe->prev_odm_pipe && pipe->stream->num_wb_info > 0
1585                                         && (pipe->update_flags.raw || pipe->plane_state->update_flags.raw || pipe->stream->update_flags.raw)
1586                                         && dc->hwss.program_all_writeback_pipes_in_tree)
1587                                 dc->hwss.program_all_writeback_pipes_in_tree(dc, pipe->stream, context);
1588                 }
1589         }
1590
1591         /* Unlock all locked pipes */
1592         for (i = 0; i < dc->res_pool->pipe_count; i++)
1593                 if (pipe_locked[i]) {
1594                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1595
1596                         if (pipe_ctx->update_flags.bits.tg_changed || pipe_ctx->update_flags.bits.enable)
1597                                 dc->hwss.pipe_control_lock(dc, pipe_ctx, false);
1598                         if (!pipe_ctx->update_flags.bits.enable)
1599                                 dc->hwss.pipe_control_lock(dc, &dc->current_state->res_ctx.pipe_ctx[i], false);
1600                 }
1601
1602         for (i = 0; i < dc->res_pool->pipe_count; i++)
1603                 if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable)
1604                         dc->hwss.disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
1605
1606         /*
1607          * If we are enabling a pipe, we need to wait for pending clear as this is a critical
1608          * part of the enable operation otherwise, DM may request an immediate flip which
1609          * will cause HW to perform an "immediate enable" (as opposed to "vsync enable") which
1610          * is unsupported on DCN.
1611          */
1612         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1613                 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1614
1615                 if (pipe->plane_state && !pipe->top_pipe && pipe->update_flags.bits.enable) {
1616                         struct hubp *hubp = pipe->plane_res.hubp;
1617                         int j = 0;
1618
1619                         for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_MS
1620                                         && hubp->funcs->hubp_is_flip_pending(hubp); j++)
1621                                 msleep(1);
1622                 }
1623         }
1624
1625         /* WA to apply WM setting*/
1626         if (dc->hwseq->wa.DEGVIDCN21)
1627                 dc->res_pool->hubbub->funcs->apply_DEDCN21_147_wa(dc->res_pool->hubbub);
1628 }
1629
1630
1631 void dcn20_prepare_bandwidth(
1632                 struct dc *dc,
1633                 struct dc_state *context)
1634 {
1635         struct hubbub *hubbub = dc->res_pool->hubbub;
1636
1637         dc->clk_mgr->funcs->update_clocks(
1638                         dc->clk_mgr,
1639                         context,
1640                         false);
1641
1642         /* program dchubbub watermarks */
1643         hubbub->funcs->program_watermarks(hubbub,
1644                                         &context->bw_ctx.bw.dcn.watermarks,
1645                                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1646                                         false);
1647 }
1648
1649 void dcn20_optimize_bandwidth(
1650                 struct dc *dc,
1651                 struct dc_state *context)
1652 {
1653         struct hubbub *hubbub = dc->res_pool->hubbub;
1654
1655         /* program dchubbub watermarks */
1656         hubbub->funcs->program_watermarks(hubbub,
1657                                         &context->bw_ctx.bw.dcn.watermarks,
1658                                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
1659                                         true);
1660
1661         dc->clk_mgr->funcs->update_clocks(
1662                         dc->clk_mgr,
1663                         context,
1664                         true);
1665 }
1666
1667 bool dcn20_update_bandwidth(
1668                 struct dc *dc,
1669                 struct dc_state *context)
1670 {
1671         int i;
1672
1673         /* recalculate DML parameters */
1674         if (!dc->res_pool->funcs->validate_bandwidth(dc, context, false))
1675                 return false;
1676
1677         /* apply updated bandwidth parameters */
1678         dc->hwss.prepare_bandwidth(dc, context);
1679
1680         /* update hubp configs for all pipes */
1681         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1682                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1683
1684                 if (pipe_ctx->plane_state == NULL)
1685                         continue;
1686
1687                 if (pipe_ctx->top_pipe == NULL) {
1688                         bool blank = !is_pipe_tree_visible(pipe_ctx);
1689
1690                         pipe_ctx->stream_res.tg->funcs->program_global_sync(
1691                                         pipe_ctx->stream_res.tg,
1692                                         pipe_ctx->pipe_dlg_param.vready_offset,
1693                                         pipe_ctx->pipe_dlg_param.vstartup_start,
1694                                         pipe_ctx->pipe_dlg_param.vupdate_offset,
1695                                         pipe_ctx->pipe_dlg_param.vupdate_width);
1696
1697                         pipe_ctx->stream_res.tg->funcs->set_vtg_params(
1698                                         pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
1699
1700                         if (pipe_ctx->prev_odm_pipe == NULL)
1701                                 dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
1702
1703                         if (dc->hwss.setup_vupdate_interrupt)
1704                                 dc->hwss.setup_vupdate_interrupt(dc, pipe_ctx);
1705                 }
1706
1707                 pipe_ctx->plane_res.hubp->funcs->hubp_setup(
1708                                 pipe_ctx->plane_res.hubp,
1709                                         &pipe_ctx->dlg_regs,
1710                                         &pipe_ctx->ttu_regs,
1711                                         &pipe_ctx->rq_regs,
1712                                         &pipe_ctx->pipe_dlg_param);
1713         }
1714
1715         return true;
1716 }
1717
1718 void dcn20_enable_writeback(
1719                 struct dc *dc,
1720                 const struct dc_stream_status *stream_status,
1721                 struct dc_writeback_info *wb_info,
1722                 struct dc_state *context)
1723 {
1724         struct dwbc *dwb;
1725         struct mcif_wb *mcif_wb;
1726         struct timing_generator *optc;
1727
1728         ASSERT(wb_info->dwb_pipe_inst < MAX_DWB_PIPES);
1729         ASSERT(wb_info->wb_enabled);
1730         dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
1731         mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
1732
1733         /* set the OPTC source mux */
1734         ASSERT(stream_status->primary_otg_inst < MAX_PIPES);
1735         optc = dc->res_pool->timing_generators[stream_status->primary_otg_inst];
1736         optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);
1737         /* set MCIF_WB buffer and arbitration configuration */
1738         mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height);
1739         mcif_wb->funcs->config_mcif_arb(mcif_wb, &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[wb_info->dwb_pipe_inst]);
1740         /* Enable MCIF_WB */
1741         mcif_wb->funcs->enable_mcif(mcif_wb);
1742         /* Enable DWB */
1743         dwb->funcs->enable(dwb, &wb_info->dwb_params);
1744         /* TODO: add sequence to enable/disable warmup */
1745 }
1746
1747 void dcn20_disable_writeback(
1748                 struct dc *dc,
1749                 unsigned int dwb_pipe_inst)
1750 {
1751         struct dwbc *dwb;
1752         struct mcif_wb *mcif_wb;
1753
1754         ASSERT(dwb_pipe_inst < MAX_DWB_PIPES);
1755         dwb = dc->res_pool->dwbc[dwb_pipe_inst];
1756         mcif_wb = dc->res_pool->mcif_wb[dwb_pipe_inst];
1757
1758         dwb->funcs->disable(dwb);
1759         mcif_wb->funcs->disable_mcif(mcif_wb);
1760 }
1761
1762 bool dcn20_wait_for_blank_complete(
1763                 struct output_pixel_processor *opp)
1764 {
1765         int counter;
1766
1767         for (counter = 0; counter < 1000; counter++) {
1768                 if (opp->funcs->dpg_is_blanked(opp))
1769                         break;
1770
1771                 udelay(100);
1772         }
1773
1774         if (counter == 1000) {
1775                 dm_error("DC: failed to blank crtc!\n");
1776                 return false;
1777         }
1778
1779         return true;
1780 }
1781
1782 bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx)
1783 {
1784         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1785
1786         if (!hubp)
1787                 return false;
1788         return hubp->funcs->dmdata_status_done(hubp);
1789 }
1790
1791 void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
1792 {
1793         struct dce_hwseq *hws = dc->hwseq;
1794
1795         if (pipe_ctx->stream_res.dsc) {
1796                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1797
1798                 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, true);
1799                 while (odm_pipe) {
1800                         dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, true);
1801                         odm_pipe = odm_pipe->next_odm_pipe;
1802                 }
1803         }
1804 }
1805
1806 void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx)
1807 {
1808         struct dce_hwseq *hws = dc->hwseq;
1809
1810         if (pipe_ctx->stream_res.dsc) {
1811                 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1812
1813                 dcn20_dsc_pg_control(hws, pipe_ctx->stream_res.dsc->inst, false);
1814                 while (odm_pipe) {
1815                         dcn20_dsc_pg_control(hws, odm_pipe->stream_res.dsc->inst, false);
1816                         odm_pipe = odm_pipe->next_odm_pipe;
1817                 }
1818         }
1819 }
1820
1821 void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx)
1822 {
1823         struct dc_dmdata_attributes attr = { 0 };
1824         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1825
1826         attr.dmdata_mode = DMDATA_HW_MODE;
1827         attr.dmdata_size =
1828                 dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;
1829         attr.address.quad_part =
1830                         pipe_ctx->stream->dmdata_address.quad_part;
1831         attr.dmdata_dl_delta = 0;
1832         attr.dmdata_qos_mode = 0;
1833         attr.dmdata_qos_level = 0;
1834         attr.dmdata_repeat = 1; /* always repeat */
1835         attr.dmdata_updated = 1;
1836         attr.dmdata_sw_data = NULL;
1837
1838         hubp->funcs->dmdata_set_attributes(hubp, &attr);
1839 }
1840
1841 void dcn20_init_vm_ctx(
1842                 struct dce_hwseq *hws,
1843                 struct dc *dc,
1844                 struct dc_virtual_addr_space_config *va_config,
1845                 int vmid)
1846 {
1847         struct dcn_hubbub_virt_addr_config config;
1848
1849         if (vmid == 0) {
1850                 ASSERT(0); /* VMID cannot be 0 for vm context */
1851                 return;
1852         }
1853
1854         config.page_table_start_addr = va_config->page_table_start_addr;
1855         config.page_table_end_addr = va_config->page_table_end_addr;
1856         config.page_table_block_size = va_config->page_table_block_size_in_bytes;
1857         config.page_table_depth = va_config->page_table_depth;
1858         config.page_table_base_addr = va_config->page_table_base_addr;
1859
1860         dc->res_pool->hubbub->funcs->init_vm_ctx(dc->res_pool->hubbub, &config, vmid);
1861 }
1862
1863 int dcn20_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_space_config *pa_config)
1864 {
1865         struct dcn_hubbub_phys_addr_config config;
1866
1867         config.system_aperture.fb_top = pa_config->system_aperture.fb_top;
1868         config.system_aperture.fb_offset = pa_config->system_aperture.fb_offset;
1869         config.system_aperture.fb_base = pa_config->system_aperture.fb_base;
1870         config.system_aperture.agp_top = pa_config->system_aperture.agp_top;
1871         config.system_aperture.agp_bot = pa_config->system_aperture.agp_bot;
1872         config.system_aperture.agp_base = pa_config->system_aperture.agp_base;
1873         config.gart_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr;
1874         config.gart_config.page_table_end_addr = pa_config->gart_config.page_table_end_addr;
1875         config.gart_config.page_table_base_addr = pa_config->gart_config.page_table_base_addr;
1876         config.page_table_default_page_addr = pa_config->page_table_default_page_addr;
1877
1878         return dc->res_pool->hubbub->funcs->init_dchub_sys_ctx(dc->res_pool->hubbub, &config);
1879 }
1880
1881 static bool patch_address_for_sbs_tb_stereo(
1882                 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
1883 {
1884         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1885         bool sec_split = pipe_ctx->top_pipe &&
1886                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
1887         if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
1888                         (pipe_ctx->stream->timing.timing_3d_format ==
1889                         TIMING_3D_FORMAT_SIDE_BY_SIDE ||
1890                         pipe_ctx->stream->timing.timing_3d_format ==
1891                         TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
1892                 *addr = plane_state->address.grph_stereo.left_addr;
1893                 plane_state->address.grph_stereo.left_addr =
1894                                 plane_state->address.grph_stereo.right_addr;
1895                 return true;
1896         }
1897
1898         if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
1899                         plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
1900                 plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
1901                 plane_state->address.grph_stereo.right_addr =
1902                                 plane_state->address.grph_stereo.left_addr;
1903         }
1904         return false;
1905 }
1906
1907 void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
1908 {
1909         bool addr_patched = false;
1910         PHYSICAL_ADDRESS_LOC addr;
1911         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1912
1913         if (plane_state == NULL)
1914                 return;
1915
1916         addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
1917
1918         // Call Helper to track VMID use
1919         vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);
1920
1921         pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
1922                         pipe_ctx->plane_res.hubp,
1923                         &plane_state->address,
1924                         plane_state->flip_immediate);
1925
1926         plane_state->status.requested_address = plane_state->address;
1927
1928         if (plane_state->flip_immediate)
1929                 plane_state->status.current_address = plane_state->address;
1930
1931         if (addr_patched)
1932                 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
1933 }
1934
1935 void dcn20_unblank_stream(struct pipe_ctx *pipe_ctx,
1936                 struct dc_link_settings *link_settings)
1937 {
1938         struct encoder_unblank_param params = { { 0 } };
1939         struct dc_stream_state *stream = pipe_ctx->stream;
1940         struct dc_link *link = stream->link;
1941         struct pipe_ctx *odm_pipe;
1942
1943         params.opp_cnt = 1;
1944         for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe) {
1945                 params.opp_cnt++;
1946         }
1947         /* only 3 items below are used by unblank */
1948         params.timing = pipe_ctx->stream->timing;
1949
1950         params.link_settings.link_rate = link_settings->link_rate;
1951
1952         if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1953                 if (optc2_is_two_pixels_per_containter(&stream->timing) || params.opp_cnt > 1)
1954                         params.timing.pix_clk_100hz /= 2;
1955                 pipe_ctx->stream_res.stream_enc->funcs->dp_set_odm_combine(
1956                                 pipe_ctx->stream_res.stream_enc, params.opp_cnt > 1);
1957                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
1958         }
1959
1960         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1961                 link->dc->hwss.edp_backlight_control(link, true);
1962         }
1963 }
1964
1965 void dcn20_setup_vupdate_interrupt(struct dc *dc, struct pipe_ctx *pipe_ctx)
1966 {
1967         struct timing_generator *tg = pipe_ctx->stream_res.tg;
1968         int start_line = dc->hwss.get_vupdate_offset_from_vsync(pipe_ctx);
1969
1970         if (start_line < 0)
1971                 start_line = 0;
1972
1973         if (tg->funcs->setup_vertical_interrupt2)
1974                 tg->funcs->setup_vertical_interrupt2(tg, start_line);
1975 }
1976
1977 static void dcn20_reset_back_end_for_pipe(
1978                 struct dc *dc,
1979                 struct pipe_ctx *pipe_ctx,
1980                 struct dc_state *context)
1981 {
1982         int i;
1983         DC_LOGGER_INIT(dc->ctx->logger);
1984         if (pipe_ctx->stream_res.stream_enc == NULL) {
1985                 pipe_ctx->stream = NULL;
1986                 return;
1987         }
1988
1989         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1990                 /* DPMS may already disable */
1991                 if (!pipe_ctx->stream->dpms_off)
1992                         core_link_disable_stream(pipe_ctx);
1993                 else if (pipe_ctx->stream_res.audio)
1994                         dc->hwss.disable_audio_stream(pipe_ctx);
1995
1996                 /* free acquired resources */
1997                 if (pipe_ctx->stream_res.audio) {
1998                         /*disable az_endpoint*/
1999                         pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
2000
2001                         /*free audio*/
2002                         if (dc->caps.dynamic_audio == true) {
2003                                 /*we have to dynamic arbitrate the audio endpoints*/
2004                                 /*we free the resource, need reset is_audio_acquired*/
2005                                 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
2006                                                 pipe_ctx->stream_res.audio, false);
2007                                 pipe_ctx->stream_res.audio = NULL;
2008                         }
2009                 }
2010         }
2011         else if (pipe_ctx->stream_res.dsc) {
2012                 dp_set_dsc_enable(pipe_ctx, false);
2013         }
2014
2015         /* by upper caller loop, parent pipe: pipe0, will be reset last.
2016          * back end share by all pipes and will be disable only when disable
2017          * parent pipe.
2018          */
2019         if (pipe_ctx->top_pipe == NULL) {
2020                 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
2021
2022                 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
2023                 if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass)
2024                         pipe_ctx->stream_res.tg->funcs->set_odm_bypass(
2025                                         pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing);
2026
2027                 if (pipe_ctx->stream_res.tg->funcs->set_drr)
2028                         pipe_ctx->stream_res.tg->funcs->set_drr(
2029                                         pipe_ctx->stream_res.tg, NULL);
2030         }
2031
2032         for (i = 0; i < dc->res_pool->pipe_count; i++)
2033                 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
2034                         break;
2035
2036         if (i == dc->res_pool->pipe_count)
2037                 return;
2038
2039         pipe_ctx->stream = NULL;
2040         DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
2041                                         pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
2042 }
2043
2044 void dcn20_reset_hw_ctx_wrap(
2045                 struct dc *dc,
2046                 struct dc_state *context)
2047 {
2048         int i;
2049
2050         /* Reset Back End*/
2051         for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
2052                 struct pipe_ctx *pipe_ctx_old =
2053                         &dc->current_state->res_ctx.pipe_ctx[i];
2054                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2055
2056                 if (!pipe_ctx_old->stream)
2057                         continue;
2058
2059                 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe)
2060                         continue;
2061
2062                 if (!pipe_ctx->stream ||
2063                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
2064                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
2065
2066                         dcn20_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
2067                         if (dc->hwss.enable_stream_gating)
2068                                 dc->hwss.enable_stream_gating(dc, pipe_ctx);
2069                         if (old_clk)
2070                                 old_clk->funcs->cs_power_down(old_clk);
2071                 }
2072         }
2073 }
2074
2075 void dcn20_get_mpctree_visual_confirm_color(
2076                 struct pipe_ctx *pipe_ctx,
2077                 struct tg_color *color)
2078 {
2079         const struct tg_color pipe_colors[6] = {
2080                         {MAX_TG_COLOR_VALUE, 0, 0}, // red
2081                         {MAX_TG_COLOR_VALUE, 0, MAX_TG_COLOR_VALUE}, // yellow
2082                         {0, MAX_TG_COLOR_VALUE, 0}, // blue
2083                         {MAX_TG_COLOR_VALUE / 2, 0, MAX_TG_COLOR_VALUE / 2}, // purple
2084                         {0, 0, MAX_TG_COLOR_VALUE}, // green
2085                         {MAX_TG_COLOR_VALUE, MAX_TG_COLOR_VALUE * 2 / 3, 0}, // orange
2086         };
2087
2088         struct pipe_ctx *top_pipe = pipe_ctx;
2089
2090         while (top_pipe->top_pipe) {
2091                 top_pipe = top_pipe->top_pipe;
2092         }
2093
2094         *color = pipe_colors[top_pipe->pipe_idx];
2095 }
2096
2097 void dcn20_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
2098 {
2099         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2100         struct mpcc_blnd_cfg blnd_cfg = { {0} };
2101         bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha;
2102         int mpcc_id;
2103         struct mpcc *new_mpcc;
2104         struct mpc *mpc = dc->res_pool->mpc;
2105         struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
2106
2107         // input to MPCC is always RGB, by default leave black_color at 0
2108         if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
2109                 dc->hwss.get_hdr_visual_confirm_color(
2110                                 pipe_ctx, &blnd_cfg.black_color);
2111         } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
2112                 dc->hwss.get_surface_visual_confirm_color(
2113                                 pipe_ctx, &blnd_cfg.black_color);
2114         } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_MPCTREE) {
2115                 dcn20_get_mpctree_visual_confirm_color(
2116                                 pipe_ctx, &blnd_cfg.black_color);
2117         }
2118
2119         if (per_pixel_alpha)
2120                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
2121         else
2122                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
2123
2124         blnd_cfg.overlap_only = false;
2125         blnd_cfg.global_gain = 0xff;
2126
2127         if (pipe_ctx->plane_state->global_alpha)
2128                 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
2129         else
2130                 blnd_cfg.global_alpha = 0xff;
2131
2132         blnd_cfg.background_color_bpc = 4;
2133         blnd_cfg.bottom_gain_mode = 0;
2134         blnd_cfg.top_gain = 0x1f000;
2135         blnd_cfg.bottom_inside_gain = 0x1f000;
2136         blnd_cfg.bottom_outside_gain = 0x1f000;
2137         blnd_cfg.pre_multiplied_alpha = per_pixel_alpha;
2138
2139         /*
2140          * TODO: remove hack
2141          * Note: currently there is a bug in init_hw such that
2142          * on resume from hibernate, BIOS sets up MPCC0, and
2143          * we do mpcc_remove but the mpcc cannot go to idle
2144          * after remove. This cause us to pick mpcc1 here,
2145          * which causes a pstate hang for yet unknown reason.
2146          */
2147         mpcc_id = hubp->inst;
2148
2149         /* If there is no full update, don't need to touch MPC tree*/
2150         if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
2151                 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
2152                 return;
2153         }
2154
2155         /* check if this MPCC is already being used */
2156         new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
2157         /* remove MPCC if being used */
2158         if (new_mpcc != NULL)
2159                 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
2160         else
2161                 if (dc->debug.sanity_checks)
2162                         mpc->funcs->assert_mpcc_idle_before_connect(
2163                                         dc->res_pool->mpc, mpcc_id);
2164
2165         /* Call MPC to insert new plane */
2166         new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
2167                         mpc_tree_params,
2168                         &blnd_cfg,
2169                         NULL,
2170                         NULL,
2171                         hubp->inst,
2172                         mpcc_id);
2173
2174         ASSERT(new_mpcc != NULL);
2175         hubp->opp_id = pipe_ctx->stream_res.opp->inst;
2176         hubp->mpcc_id = mpcc_id;
2177 }
2178
2179 void dcn20_enable_stream(struct pipe_ctx *pipe_ctx)
2180 {
2181         enum dc_lane_count lane_count =
2182                 pipe_ctx->stream->link->cur_link_settings.lane_count;
2183
2184         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
2185         struct dc_link *link = pipe_ctx->stream->link;
2186
2187         uint32_t active_total_with_borders;
2188         uint32_t early_control = 0;
2189         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2190
2191         /* For MST, there are multiply stream go to only one link.
2192          * connect DIG back_end to front_end while enable_stream and
2193          * disconnect them during disable_stream
2194          * BY this, it is logic clean to separate stream and link
2195          */
2196         link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
2197                                                     pipe_ctx->stream_res.stream_enc->id, true);
2198
2199         if (pipe_ctx->plane_state && pipe_ctx->plane_state->flip_immediate != 1) {
2200                 if (link->dc->hwss.program_dmdata_engine)
2201                         link->dc->hwss.program_dmdata_engine(pipe_ctx);
2202         }
2203
2204         link->dc->hwss.update_info_frame(pipe_ctx);
2205
2206         /* enable early control to avoid corruption on DP monitor*/
2207         active_total_with_borders =
2208                         timing->h_addressable
2209                                 + timing->h_border_left
2210                                 + timing->h_border_right;
2211
2212         if (lane_count != 0)
2213                 early_control = active_total_with_borders % lane_count;
2214
2215         if (early_control == 0)
2216                 early_control = lane_count;
2217
2218         tg->funcs->set_early_control(tg, early_control);
2219
2220         /* enable audio only within mode set */
2221         if (pipe_ctx->stream_res.audio != NULL) {
2222                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
2223                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
2224         }
2225 }
2226
2227 void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
2228 {
2229         struct dc_stream_state    *stream     = pipe_ctx->stream;
2230         struct hubp               *hubp       = pipe_ctx->plane_res.hubp;
2231         bool                       enable     = false;
2232         struct stream_encoder     *stream_enc = pipe_ctx->stream_res.stream_enc;
2233         enum dynamic_metadata_mode mode       = dc_is_dp_signal(stream->signal)
2234                                                         ? dmdata_dp
2235                                                         : dmdata_hdmi;
2236
2237         /* if using dynamic meta, don't set up generic infopackets */
2238         if (pipe_ctx->stream->dmdata_address.quad_part != 0) {
2239                 pipe_ctx->stream_res.encoder_info_frame.hdrsmd.valid = false;
2240                 enable = true;
2241         }
2242
2243         if (!hubp)
2244                 return;
2245
2246         if (!stream_enc || !stream_enc->funcs->set_dynamic_metadata)
2247                 return;
2248
2249         stream_enc->funcs->set_dynamic_metadata(stream_enc, enable,
2250                                                 hubp->inst, mode);
2251 }
2252
2253 void dcn20_fpga_init_hw(struct dc *dc)
2254 {
2255         int i, j;
2256         struct dce_hwseq *hws = dc->hwseq;
2257         struct resource_pool *res_pool = dc->res_pool;
2258         struct dc_state  *context = dc->current_state;
2259
2260         if (dc->clk_mgr && dc->clk_mgr->funcs->init_clocks)
2261                 dc->clk_mgr->funcs->init_clocks(dc->clk_mgr);
2262
2263         // Initialize the dccg
2264         if (res_pool->dccg->funcs->dccg_init)
2265                 res_pool->dccg->funcs->dccg_init(res_pool->dccg);
2266
2267         //Enable ability to power gate / don't force power on permanently
2268         dc->hwss.enable_power_gating_plane(hws, true);
2269
2270         // Specific to FPGA dccg and registers
2271         REG_WRITE(RBBMIF_TIMEOUT_DIS, 0xFFFFFFFF);
2272         REG_WRITE(RBBMIF_TIMEOUT_DIS_2, 0xFFFFFFFF);
2273
2274         dc->hwss.dccg_init(hws);
2275
2276         REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, 2);
2277         REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
2278         REG_WRITE(REFCLK_CNTL, 0);
2279         //
2280
2281
2282         /* Blank pixel data with OPP DPG */
2283         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2284                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2285
2286                 if (tg->funcs->is_tg_enabled(tg))
2287                         dcn20_init_blank(dc, tg);
2288         }
2289
2290         for (i = 0; i < res_pool->timing_generator_count; i++) {
2291                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2292
2293                 if (tg->funcs->is_tg_enabled(tg))
2294                         tg->funcs->lock(tg);
2295         }
2296
2297         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2298                 struct dpp *dpp = res_pool->dpps[i];
2299
2300                 dpp->funcs->dpp_reset(dpp);
2301         }
2302
2303         /* Reset all MPCC muxes */
2304         res_pool->mpc->funcs->mpc_init(res_pool->mpc);
2305
2306         /* initialize OPP mpc_tree parameter */
2307         for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) {
2308                 res_pool->opps[i]->mpc_tree_params.opp_id = res_pool->opps[i]->inst;
2309                 res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2310                 for (j = 0; j < MAX_PIPES; j++)
2311                         res_pool->opps[i]->mpcc_disconnect_pending[j] = false;
2312         }
2313
2314         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2315                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2316                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2317                 struct hubp *hubp = dc->res_pool->hubps[i];
2318                 struct dpp *dpp = dc->res_pool->dpps[i];
2319
2320                 pipe_ctx->stream_res.tg = tg;
2321                 pipe_ctx->pipe_idx = i;
2322
2323                 pipe_ctx->plane_res.hubp = hubp;
2324                 pipe_ctx->plane_res.dpp = dpp;
2325                 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
2326                 hubp->mpcc_id = dpp->inst;
2327                 hubp->opp_id = OPP_ID_INVALID;
2328                 hubp->power_gated = false;
2329                 pipe_ctx->stream_res.opp = NULL;
2330
2331                 hubp->funcs->hubp_init(hubp);
2332
2333                 //dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
2334                 //dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
2335                 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
2336                 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
2337                 /*to do*/
2338                 dc->hwss.plane_atomic_disconnect(dc, pipe_ctx);
2339         }
2340
2341         /* initialize DWB pointer to MCIF_WB */
2342         for (i = 0; i < res_pool->res_cap->num_dwb; i++)
2343                 res_pool->dwbc[i]->mcif = res_pool->mcif_wb[i];
2344
2345         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2346                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2347
2348                 if (tg->funcs->is_tg_enabled(tg))
2349                         tg->funcs->unlock(tg);
2350         }
2351
2352         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2353                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2354
2355                 dc->hwss.disable_plane(dc, pipe_ctx);
2356
2357                 pipe_ctx->stream_res.tg = NULL;
2358                 pipe_ctx->plane_res.hubp = NULL;
2359         }
2360
2361         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
2362                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2363
2364                 tg->funcs->tg_init(tg);
2365         }
2366 }