drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c

   1 /*
   2  * Copyright 2012-17 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dcn20_hubp.h"
  27
  28 #include "dm_services.h"
  29 #include "dce_calcs.h"
  30 #include "reg_helper.h"
  31 #include "basics/conversion.h"
  32
  33 #define DC_LOGGER_INIT(logger)
  34
  35 #define REG(reg)\
  36         hubp2->hubp_regs->reg
  37
  38 #define CTX \
  39         hubp2->base.ctx
  40
  41 #undef FN
  42 #define FN(reg_name, field_name) \
  43         hubp2->hubp_shift->field_name, hubp2->hubp_mask->field_name
  44
  45 void hubp2_set_vm_system_aperture_settings(struct hubp *hubp,
  46                 struct vm_system_aperture_param *apt)
  47 {
  48         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
  49
  50         PHYSICAL_ADDRESS_LOC mc_vm_apt_default;
  51         PHYSICAL_ADDRESS_LOC mc_vm_apt_low;
  52         PHYSICAL_ADDRESS_LOC mc_vm_apt_high;
  53
  54         // The format of default addr is 48:12 of the 48 bit addr
  55         mc_vm_apt_default.quad_part = apt->sys_default.quad_part >> 12;
  56
  57         // The format of high/low are 48:18 of the 48 bit addr
  58         mc_vm_apt_low.quad_part = apt->sys_low.quad_part >> 18;
  59         mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
  60
  61         REG_UPDATE_2(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
  62                 DCN_VM_SYSTEM_APERTURE_DEFAULT_SYSTEM, 1, /* 1 = system physical memory */
  63                 DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB, mc_vm_apt_default.high_part);
  64
  65         REG_SET(DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, 0,
  66                         DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part);
  67
  68         REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
  69                         MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
  70
  71         REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
  72                         MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
  73
  74         REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
  75                         ENABLE_L1_TLB, 1,
  76                         SYSTEM_ACCESS_MODE, 0x3);
  77 }
  78
  79 void hubp2_program_deadline(
  80                 struct hubp *hubp,
  81                 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
  82                 struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
  83 {
  84         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
  85
  86         /* DLG - Per hubp */
  87         REG_SET_2(BLANK_OFFSET_0, 0,
  88                 REFCYC_H_BLANK_END, dlg_attr->refcyc_h_blank_end,
  89                 DLG_V_BLANK_END, dlg_attr->dlg_vblank_end);
  90
  91         REG_SET(BLANK_OFFSET_1, 0,
  92                 MIN_DST_Y_NEXT_START, dlg_attr->min_dst_y_next_start);
  93
  94         REG_SET(DST_DIMENSIONS, 0,
  95                 REFCYC_PER_HTOTAL, dlg_attr->refcyc_per_htotal);
  96
  97         REG_SET_2(DST_AFTER_SCALER, 0,
  98                 REFCYC_X_AFTER_SCALER, dlg_attr->refcyc_x_after_scaler,
  99                 DST_Y_AFTER_SCALER, dlg_attr->dst_y_after_scaler);
 100
 101         REG_SET(REF_FREQ_TO_PIX_FREQ, 0,
 102                 REF_FREQ_TO_PIX_FREQ, dlg_attr->ref_freq_to_pix_freq);
 103
 104         /* DLG - Per luma/chroma */
 105         REG_SET(VBLANK_PARAMETERS_1, 0,
 106                 REFCYC_PER_PTE_GROUP_VBLANK_L, dlg_attr->refcyc_per_pte_group_vblank_l);
 107
 108         if (REG(NOM_PARAMETERS_0))
 109                 REG_SET(NOM_PARAMETERS_0, 0,
 110                         DST_Y_PER_PTE_ROW_NOM_L, dlg_attr->dst_y_per_pte_row_nom_l);
 111
 112         if (REG(NOM_PARAMETERS_1))
 113                 REG_SET(NOM_PARAMETERS_1, 0,
 114                         REFCYC_PER_PTE_GROUP_NOM_L, dlg_attr->refcyc_per_pte_group_nom_l);
 115
 116         REG_SET(NOM_PARAMETERS_4, 0,
 117                 DST_Y_PER_META_ROW_NOM_L, dlg_attr->dst_y_per_meta_row_nom_l);
 118
 119         REG_SET(NOM_PARAMETERS_5, 0,
 120                 REFCYC_PER_META_CHUNK_NOM_L, dlg_attr->refcyc_per_meta_chunk_nom_l);
 121
 122         REG_SET_2(PER_LINE_DELIVERY, 0,
 123                 REFCYC_PER_LINE_DELIVERY_L, dlg_attr->refcyc_per_line_delivery_l,
 124                 REFCYC_PER_LINE_DELIVERY_C, dlg_attr->refcyc_per_line_delivery_c);
 125
 126         REG_SET(VBLANK_PARAMETERS_2, 0,
 127                 REFCYC_PER_PTE_GROUP_VBLANK_C, dlg_attr->refcyc_per_pte_group_vblank_c);
 128
 129         if (REG(NOM_PARAMETERS_2))
 130                 REG_SET(NOM_PARAMETERS_2, 0,
 131                         DST_Y_PER_PTE_ROW_NOM_C, dlg_attr->dst_y_per_pte_row_nom_c);
 132
 133         if (REG(NOM_PARAMETERS_3))
 134                 REG_SET(NOM_PARAMETERS_3, 0,
 135                         REFCYC_PER_PTE_GROUP_NOM_C, dlg_attr->refcyc_per_pte_group_nom_c);
 136
 137         REG_SET(NOM_PARAMETERS_6, 0,
 138                 DST_Y_PER_META_ROW_NOM_C, dlg_attr->dst_y_per_meta_row_nom_c);
 139
 140         REG_SET(NOM_PARAMETERS_7, 0,
 141                 REFCYC_PER_META_CHUNK_NOM_C, dlg_attr->refcyc_per_meta_chunk_nom_c);
 142
 143         /* TTU - per hubp */
 144         REG_SET_2(DCN_TTU_QOS_WM, 0,
 145                 QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm,
 146                 QoS_LEVEL_HIGH_WM, ttu_attr->qos_level_high_wm);
 147
 148         /* TTU - per luma/chroma */
 149         /* Assumed surf0 is luma and 1 is chroma */
 150
 151         REG_SET_3(DCN_SURF0_TTU_CNTL0, 0,
 152                 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_l,
 153                 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_l,
 154                 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_l);
 155
 156         REG_SET_3(DCN_SURF1_TTU_CNTL0, 0,
 157                 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_c,
 158                 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_c,
 159                 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_c);
 160
 161         REG_SET_3(DCN_CUR0_TTU_CNTL0, 0,
 162                 REFCYC_PER_REQ_DELIVERY, ttu_attr->refcyc_per_req_delivery_cur0,
 163                 QoS_LEVEL_FIXED, ttu_attr->qos_level_fixed_cur0,
 164                 QoS_RAMP_DISABLE, ttu_attr->qos_ramp_disable_cur0);
 165
 166         REG_SET(FLIP_PARAMETERS_1, 0,
 167                 REFCYC_PER_PTE_GROUP_FLIP_L, dlg_attr->refcyc_per_pte_group_flip_l);
 168 }
 169
 170 void hubp2_vready_at_or_After_vsync(struct hubp *hubp,
 171                 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
 172 {
 173         uint32_t value = 0;
 174         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 175         /* disable_dlg_test_mode Set 9th bit to 1 to disable "dv" mode */
 176         REG_WRITE(HUBPREQ_DEBUG_DB, 1 << 8);
 177         /*
 178         if (VSTARTUP_START - (VREADY_OFFSET+VUPDATE_WIDTH+VUPDATE_OFFSET)/htotal)
 179         <= OTG_V_BLANK_END
 180                 Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 1
 181         else
 182                 Set HUBP_VREADY_AT_OR_AFTER_VSYNC = 0
 183         */
 184         if ((pipe_dest->vstartup_start - (pipe_dest->vready_offset+pipe_dest->vupdate_width
 185                 + pipe_dest->vupdate_offset) / pipe_dest->htotal) <= pipe_dest->vblank_end) {
 186                 value = 1;
 187         } else
 188                 value = 0;
 189         REG_UPDATE(DCHUBP_CNTL, HUBP_VREADY_AT_OR_AFTER_VSYNC, value);
 190 }
 191
 192 void hubp2_program_requestor(
 193                 struct hubp *hubp,
 194                 struct _vcs_dpi_display_rq_regs_st *rq_regs)
 195 {
 196         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 197
 198         REG_UPDATE(HUBPRET_CONTROL,
 199                         DET_BUF_PLANE1_BASE_ADDRESS, rq_regs->plane1_base_address);
 200         REG_SET_4(DCN_EXPANSION_MODE, 0,
 201                         DRQ_EXPANSION_MODE, rq_regs->drq_expansion_mode,
 202                         PRQ_EXPANSION_MODE, rq_regs->prq_expansion_mode,
 203                         MRQ_EXPANSION_MODE, rq_regs->mrq_expansion_mode,
 204                         CRQ_EXPANSION_MODE, rq_regs->crq_expansion_mode);
 205         REG_SET_8(DCHUBP_REQ_SIZE_CONFIG, 0,
 206                 CHUNK_SIZE, rq_regs->rq_regs_l.chunk_size,
 207                 MIN_CHUNK_SIZE, rq_regs->rq_regs_l.min_chunk_size,
 208                 META_CHUNK_SIZE, rq_regs->rq_regs_l.meta_chunk_size,
 209                 MIN_META_CHUNK_SIZE, rq_regs->rq_regs_l.min_meta_chunk_size,
 210                 DPTE_GROUP_SIZE, rq_regs->rq_regs_l.dpte_group_size,
 211                 MPTE_GROUP_SIZE, rq_regs->rq_regs_l.mpte_group_size,
 212                 SWATH_HEIGHT, rq_regs->rq_regs_l.swath_height,
 213                 PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
 214         REG_SET_8(DCHUBP_REQ_SIZE_CONFIG_C, 0,
 215                 CHUNK_SIZE_C, rq_regs->rq_regs_c.chunk_size,
 216                 MIN_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_chunk_size,
 217                 META_CHUNK_SIZE_C, rq_regs->rq_regs_c.meta_chunk_size,
 218                 MIN_META_CHUNK_SIZE_C, rq_regs->rq_regs_c.min_meta_chunk_size,
 219                 DPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.dpte_group_size,
 220                 MPTE_GROUP_SIZE_C, rq_regs->rq_regs_c.mpte_group_size,
 221                 SWATH_HEIGHT_C, rq_regs->rq_regs_c.swath_height,
 222                 PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
 223 }
 224
 225 static void hubp2_setup(
 226                 struct hubp *hubp,
 227                 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
 228                 struct _vcs_dpi_display_ttu_regs_st *ttu_attr,
 229                 struct _vcs_dpi_display_rq_regs_st *rq_regs,
 230                 struct _vcs_dpi_display_pipe_dest_params_st *pipe_dest)
 231 {
 232         /* otg is locked when this func is called. Register are double buffered.
 233          * disable the requestors is not needed
 234          */
 235
 236         hubp2_vready_at_or_After_vsync(hubp, pipe_dest);
 237         hubp2_program_requestor(hubp, rq_regs);
 238         hubp2_program_deadline(hubp, dlg_attr, ttu_attr);
 239
 240 }
 241
 242 void hubp2_setup_interdependent(
 243                 struct hubp *hubp,
 244                 struct _vcs_dpi_display_dlg_regs_st *dlg_attr,
 245                 struct _vcs_dpi_display_ttu_regs_st *ttu_attr)
 246 {
 247         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 248
 249         REG_SET_2(PREFETCH_SETTINGS, 0,
 250                         DST_Y_PREFETCH, dlg_attr->dst_y_prefetch,
 251                         VRATIO_PREFETCH, dlg_attr->vratio_prefetch);
 252
 253         REG_SET(PREFETCH_SETTINGS_C, 0,
 254                         VRATIO_PREFETCH_C, dlg_attr->vratio_prefetch_c);
 255
 256         REG_SET_2(VBLANK_PARAMETERS_0, 0,
 257                 DST_Y_PER_VM_VBLANK, dlg_attr->dst_y_per_vm_vblank,
 258                 DST_Y_PER_ROW_VBLANK, dlg_attr->dst_y_per_row_vblank);
 259
 260         REG_SET_2(FLIP_PARAMETERS_0, 0,
 261                 DST_Y_PER_VM_FLIP, dlg_attr->dst_y_per_vm_flip,
 262                 DST_Y_PER_ROW_FLIP, dlg_attr->dst_y_per_row_flip);
 263
 264         REG_SET(VBLANK_PARAMETERS_3, 0,
 265                 REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);
 266
 267         REG_SET(VBLANK_PARAMETERS_4, 0,
 268                 REFCYC_PER_META_CHUNK_VBLANK_C, dlg_attr->refcyc_per_meta_chunk_vblank_c);
 269
 270         REG_SET(FLIP_PARAMETERS_2, 0,
 271                 REFCYC_PER_META_CHUNK_FLIP_L, dlg_attr->refcyc_per_meta_chunk_flip_l);
 272
 273         REG_SET_2(PER_LINE_DELIVERY_PRE, 0,
 274                 REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l,
 275                 REFCYC_PER_LINE_DELIVERY_PRE_C, dlg_attr->refcyc_per_line_delivery_pre_c);
 276
 277         REG_SET(DCN_SURF0_TTU_CNTL1, 0,
 278                 REFCYC_PER_REQ_DELIVERY_PRE,
 279                 ttu_attr->refcyc_per_req_delivery_pre_l);
 280         REG_SET(DCN_SURF1_TTU_CNTL1, 0,
 281                 REFCYC_PER_REQ_DELIVERY_PRE,
 282                 ttu_attr->refcyc_per_req_delivery_pre_c);
 283         REG_SET(DCN_CUR0_TTU_CNTL1, 0,
 284                 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur0);
 285         REG_SET(DCN_CUR1_TTU_CNTL1, 0,
 286                 REFCYC_PER_REQ_DELIVERY_PRE, ttu_attr->refcyc_per_req_delivery_pre_cur1);
 287
 288         REG_SET_2(DCN_GLOBAL_TTU_CNTL, 0,
 289                 MIN_TTU_VBLANK, ttu_attr->min_ttu_vblank,
 290                 QoS_LEVEL_FLIP, ttu_attr->qos_level_flip);
 291 }
 292
 293 /* DCN2 (GFX10), the following GFX fields are deprecated. They can be set but they will not be used:
 294  *      NUM_BANKS
 295  *      NUM_SE
 296  *      NUM_RB_PER_SE
 297  *      RB_ALIGNED
 298  * Other things can be defaulted, since they never change:
 299  *      PIPE_ALIGNED = 0
 300  *      META_LINEAR = 0
 301  * In GFX10, only these apply:
 302  *      PIPE_INTERLEAVE
 303  *      NUM_PIPES
 304  *      MAX_COMPRESSED_FRAGS
 305  *      SW_MODE
 306  */
 307 static void hubp2_program_tiling(
 308         struct dcn20_hubp *hubp2,
 309         const union dc_tiling_info *info,
 310         const enum surface_pixel_format pixel_format)
 311 {
 312         REG_UPDATE_3(DCSURF_ADDR_CONFIG,
 313                         NUM_PIPES, log_2(info->gfx9.num_pipes),
 314                         PIPE_INTERLEAVE, info->gfx9.pipe_interleave,
 315                         MAX_COMPRESSED_FRAGS, log_2(info->gfx9.max_compressed_frags));
 316
 317         REG_UPDATE_4(DCSURF_TILING_CONFIG,
 318                         SW_MODE, info->gfx9.swizzle,
 319                         META_LINEAR, 0,
 320                         RB_ALIGNED, 0,
 321                         PIPE_ALIGNED, 0);
 322 }
 323
 324 void hubp2_program_size(
 325         struct hubp *hubp,
 326         enum surface_pixel_format format,
 327         const struct plane_size *plane_size,
 328         struct dc_plane_dcc_param *dcc)
 329 {
 330         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 331         uint32_t pitch, meta_pitch, pitch_c, meta_pitch_c;
 332         bool use_pitch_c = false;
 333
 334         /* Program data and meta surface pitch (calculation from addrlib)
 335          * 444 or 420 luma
 336          */
 337         use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
 338                 && format < SURFACE_PIXEL_FORMAT_SUBSAMPLE_END;
 339         use_pitch_c = use_pitch_c
 340                 || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA);
 341         if (use_pitch_c) {
 342                 ASSERT(plane_size->chroma_pitch != 0);
 343                 /* Chroma pitch zero can cause system hang! */
 344
 345                 pitch = plane_size->surface_pitch - 1;
 346                 meta_pitch = dcc->meta_pitch - 1;
 347                 pitch_c = plane_size->chroma_pitch - 1;
 348                 meta_pitch_c = dcc->meta_pitch_c - 1;
 349         } else {
 350                 pitch = plane_size->surface_pitch - 1;
 351                 meta_pitch = dcc->meta_pitch - 1;
 352                 pitch_c = 0;
 353                 meta_pitch_c = 0;
 354         }
 355
 356         if (!dcc->enable) {
 357                 meta_pitch = 0;
 358                 meta_pitch_c = 0;
 359         }
 360
 361         REG_UPDATE_2(DCSURF_SURFACE_PITCH,
 362                         PITCH, pitch, META_PITCH, meta_pitch);
 363
 364         use_pitch_c = format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN;
 365         use_pitch_c = use_pitch_c
 366                 || (format == SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA);
 367         if (use_pitch_c)
 368                 REG_UPDATE_2(DCSURF_SURFACE_PITCH_C,
 369                         PITCH_C, pitch_c, META_PITCH_C, meta_pitch_c);
 370 }
 371
 372 void hubp2_program_rotation(
 373         struct hubp *hubp,
 374         enum dc_rotation_angle rotation,
 375         bool horizontal_mirror)
 376 {
 377         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 378         uint32_t mirror;
 379
 380
 381         if (horizontal_mirror)
 382                 mirror = 1;
 383         else
 384                 mirror = 0;
 385
 386         /* Program rotation angle and horz mirror - no mirror */
 387         if (rotation == ROTATION_ANGLE_0)
 388                 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 389                                 ROTATION_ANGLE, 0,
 390                                 H_MIRROR_EN, mirror);
 391         else if (rotation == ROTATION_ANGLE_90)
 392                 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 393                                 ROTATION_ANGLE, 1,
 394                                 H_MIRROR_EN, mirror);
 395         else if (rotation == ROTATION_ANGLE_180)
 396                 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 397                                 ROTATION_ANGLE, 2,
 398                                 H_MIRROR_EN, mirror);
 399         else if (rotation == ROTATION_ANGLE_270)
 400                 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 401                                 ROTATION_ANGLE, 3,
 402                                 H_MIRROR_EN, mirror);
 403 }
 404
 405 void hubp2_dcc_control(struct hubp *hubp, bool enable,
 406                 enum hubp_ind_block_size independent_64b_blks)
 407 {
 408         uint32_t dcc_en = enable ? 1 : 0;
 409         uint32_t dcc_ind_64b_blk = independent_64b_blks ? 1 : 0;
 410         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 411
 412         REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
 413                         PRIMARY_SURFACE_DCC_EN, dcc_en,
 414                         PRIMARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk,
 415                         SECONDARY_SURFACE_DCC_EN, dcc_en,
 416                         SECONDARY_SURFACE_DCC_IND_64B_BLK, dcc_ind_64b_blk);
 417 }
 418
 419 void hubp2_program_pixel_format(
 420         struct hubp *hubp,
 421         enum surface_pixel_format format)
 422 {
 423         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 424         uint32_t red_bar = 3;
 425         uint32_t blue_bar = 2;
 426
 427         /* swap for ABGR format */
 428         if (format == SURFACE_PIXEL_FORMAT_GRPH_ABGR8888
 429                         || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010
 430                         || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS
 431                         || format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F) {
 432                 red_bar = 2;
 433                 blue_bar = 3;
 434         }
 435
 436         REG_UPDATE_2(HUBPRET_CONTROL,
 437                         CROSSBAR_SRC_CB_B, blue_bar,
 438                         CROSSBAR_SRC_CR_R, red_bar);
 439
 440         /* Mapping is same as ipp programming (cnvc) */
 441
 442         switch (format) {
 443         case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
 444                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 445                                 SURFACE_PIXEL_FORMAT, 1);
 446                 break;
 447         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 448                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 449                                 SURFACE_PIXEL_FORMAT, 3);
 450                 break;
 451         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 452         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 453                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 454                                 SURFACE_PIXEL_FORMAT, 8);
 455                 break;
 456         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 457         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 458         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010_XR_BIAS:
 459                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 460                                 SURFACE_PIXEL_FORMAT, 10);
 461                 break;
 462         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 463                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 464                                 SURFACE_PIXEL_FORMAT, 22);
 465                 break;
 466         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
 467         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:/*we use crossbar already*/
 468                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 469                                 SURFACE_PIXEL_FORMAT, 24);
 470                 break;
 471
 472         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
 473                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 474                                 SURFACE_PIXEL_FORMAT, 65);
 475                 break;
 476         case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
 477                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 478                                 SURFACE_PIXEL_FORMAT, 64);
 479                 break;
 480         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
 481                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 482                                 SURFACE_PIXEL_FORMAT, 67);
 483                 break;
 484         case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
 485                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 486                                 SURFACE_PIXEL_FORMAT, 66);
 487                 break;
 488         case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
 489                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 490                                 SURFACE_PIXEL_FORMAT, 12);
 491                 break;
 492         case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
 493                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 494                                 SURFACE_PIXEL_FORMAT, 112);
 495                 break;
 496         case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
 497                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 498                                 SURFACE_PIXEL_FORMAT, 113);
 499                 break;
 500         case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
 501                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 502                                 SURFACE_PIXEL_FORMAT, 114);
 503                 break;
 504         case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
 505                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 506                                 SURFACE_PIXEL_FORMAT, 118);
 507                 break;
 508         case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
 509                 REG_UPDATE(DCSURF_SURFACE_CONFIG,
 510                                 SURFACE_PIXEL_FORMAT, 119);
 511                 break;
 512         case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
 513                 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 514                                 SURFACE_PIXEL_FORMAT, 116,
 515                                 ALPHA_PLANE_EN, 0);
 516                 break;
 517         case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
 518                 REG_UPDATE_2(DCSURF_SURFACE_CONFIG,
 519                                 SURFACE_PIXEL_FORMAT, 116,
 520                                 ALPHA_PLANE_EN, 1);
 521                 break;
 522         default:
 523                 BREAK_TO_DEBUGGER();
 524                 break;
 525         }
 526
 527         /* don't see the need of program the xbar in DCN 1.0 */
 528 }
 529
 530 void hubp2_program_surface_config(
 531         struct hubp *hubp,
 532         enum surface_pixel_format format,
 533         union dc_tiling_info *tiling_info,
 534         struct plane_size *plane_size,
 535         enum dc_rotation_angle rotation,
 536         struct dc_plane_dcc_param *dcc,
 537         bool horizontal_mirror,
 538         unsigned int compat_level)
 539 {
 540         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 541
 542         hubp2_dcc_control(hubp, dcc->enable, dcc->independent_64b_blks);
 543         hubp2_program_tiling(hubp2, tiling_info, format);
 544         hubp2_program_size(hubp, format, plane_size, dcc);
 545         hubp2_program_rotation(hubp, rotation, horizontal_mirror);
 546         hubp2_program_pixel_format(hubp, format);
 547 }
 548
 549 enum cursor_lines_per_chunk hubp2_get_lines_per_chunk(
 550         unsigned int cursor_width,
 551         enum dc_cursor_color_format cursor_mode)
 552 {
 553         enum cursor_lines_per_chunk line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
 554
 555         if (cursor_mode == CURSOR_MODE_MONO)
 556                 line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
 557         else if (cursor_mode == CURSOR_MODE_COLOR_1BIT_AND ||
 558                  cursor_mode == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA ||
 559                  cursor_mode == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) {
 560                 if (cursor_width >= 1   && cursor_width <= 32)
 561                         line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
 562                 else if (cursor_width >= 33  && cursor_width <= 64)
 563                         line_per_chunk = CURSOR_LINE_PER_CHUNK_8;
 564                 else if (cursor_width >= 65  && cursor_width <= 128)
 565                         line_per_chunk = CURSOR_LINE_PER_CHUNK_4;
 566                 else if (cursor_width >= 129 && cursor_width <= 256)
 567                         line_per_chunk = CURSOR_LINE_PER_CHUNK_2;
 568         } else if (cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_PRE_MULTIPLIED ||
 569                    cursor_mode == CURSOR_MODE_COLOR_64BIT_FP_UN_PRE_MULTIPLIED) {
 570                 if (cursor_width >= 1   && cursor_width <= 16)
 571                         line_per_chunk = CURSOR_LINE_PER_CHUNK_16;
 572                 else if (cursor_width >= 17  && cursor_width <= 32)
 573                         line_per_chunk = CURSOR_LINE_PER_CHUNK_8;
 574                 else if (cursor_width >= 33  && cursor_width <= 64)
 575                         line_per_chunk = CURSOR_LINE_PER_CHUNK_4;
 576                 else if (cursor_width >= 65 && cursor_width <= 128)
 577                         line_per_chunk = CURSOR_LINE_PER_CHUNK_2;
 578                 else if (cursor_width >= 129 && cursor_width <= 256)
 579                         line_per_chunk = CURSOR_LINE_PER_CHUNK_1;
 580         }
 581
 582         return line_per_chunk;
 583 }
 584
 585 void hubp2_cursor_set_attributes(
 586                 struct hubp *hubp,
 587                 const struct dc_cursor_attributes *attr)
 588 {
 589         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 590         enum cursor_pitch hw_pitch = hubp1_get_cursor_pitch(attr->pitch);
 591         enum cursor_lines_per_chunk lpc = hubp2_get_lines_per_chunk(
 592                         attr->width, attr->color_format);
 593
 594         hubp->curs_attr = *attr;
 595
 596         REG_UPDATE(CURSOR_SURFACE_ADDRESS_HIGH,
 597                         CURSOR_SURFACE_ADDRESS_HIGH, attr->address.high_part);
 598         REG_UPDATE(CURSOR_SURFACE_ADDRESS,
 599                         CURSOR_SURFACE_ADDRESS, attr->address.low_part);
 600
 601         REG_UPDATE_2(CURSOR_SIZE,
 602                         CURSOR_WIDTH, attr->width,
 603                         CURSOR_HEIGHT, attr->height);
 604
 605         REG_UPDATE_4(CURSOR_CONTROL,
 606                         CURSOR_MODE, attr->color_format,
 607                         CURSOR_2X_MAGNIFY, attr->attribute_flags.bits.ENABLE_MAGNIFICATION,
 608                         CURSOR_PITCH, hw_pitch,
 609                         CURSOR_LINES_PER_CHUNK, lpc);
 610
 611         REG_SET_2(CURSOR_SETTINGS, 0,
 612                         /* no shift of the cursor HDL schedule */
 613                         CURSOR0_DST_Y_OFFSET, 0,
 614                          /* used to shift the cursor chunk request deadline */
 615                         CURSOR0_CHUNK_HDL_ADJUST, 3);
 616 }
 617
 618 void hubp2_dmdata_set_attributes(
 619                 struct hubp *hubp,
 620                 const struct dc_dmdata_attributes *attr)
 621 {
 622         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 623
 624         if (attr->dmdata_mode == DMDATA_HW_MODE) {
 625                 /* set to HW mode */
 626                 REG_UPDATE(DMDATA_CNTL,
 627                                 DMDATA_MODE, 1);
 628
 629                 /* for DMDATA flip, need to use SURFACE_UPDATE_LOCK */
 630                 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 1);
 631
 632                 /* toggle DMDATA_UPDATED and set repeat and size */
 633                 REG_UPDATE(DMDATA_CNTL,
 634                                 DMDATA_UPDATED, 0);
 635                 REG_UPDATE_3(DMDATA_CNTL,
 636                                 DMDATA_UPDATED, 1,
 637                                 DMDATA_REPEAT, attr->dmdata_repeat,
 638                                 DMDATA_SIZE, attr->dmdata_size);
 639
 640                 /* set DMDATA address */
 641                 REG_WRITE(DMDATA_ADDRESS_LOW, attr->address.low_part);
 642                 REG_UPDATE(DMDATA_ADDRESS_HIGH,
 643                                 DMDATA_ADDRESS_HIGH, attr->address.high_part);
 644
 645                 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_UPDATE_LOCK, 0);
 646
 647         } else {
 648                 /* set to SW mode before loading data */
 649                 REG_SET(DMDATA_CNTL, 0,
 650                                 DMDATA_MODE, 0);
 651                 /* toggle DMDATA_SW_UPDATED to start loading sequence */
 652                 REG_UPDATE(DMDATA_SW_CNTL,
 653                                 DMDATA_SW_UPDATED, 0);
 654                 REG_UPDATE_3(DMDATA_SW_CNTL,
 655                                 DMDATA_SW_UPDATED, 1,
 656                                 DMDATA_SW_REPEAT, attr->dmdata_repeat,
 657                                 DMDATA_SW_SIZE, attr->dmdata_size);
 658                 /* load data into hubp dmdata buffer */
 659                 hubp2_dmdata_load(hubp, attr->dmdata_size, attr->dmdata_sw_data);
 660         }
 661
 662         /* Note that DL_DELTA must be programmed if we want to use TTU mode */
 663         REG_SET_3(DMDATA_QOS_CNTL, 0,
 664                         DMDATA_QOS_MODE, attr->dmdata_qos_mode,
 665                         DMDATA_QOS_LEVEL, attr->dmdata_qos_level,
 666                         DMDATA_DL_DELTA, attr->dmdata_dl_delta);
 667 }
 668
 669 void hubp2_dmdata_load(
 670                 struct hubp *hubp,
 671                 uint32_t dmdata_sw_size,
 672                 const uint32_t *dmdata_sw_data)
 673 {
 674         int i;
 675         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 676
 677         /* load dmdata into HUBP buffer in SW mode */
 678         for (i = 0; i < dmdata_sw_size / 4; i++)
 679                 REG_WRITE(DMDATA_SW_DATA, dmdata_sw_data[i]);
 680 }
 681
 682 bool hubp2_dmdata_status_done(struct hubp *hubp)
 683 {
 684         uint32_t status;
 685         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 686
 687         REG_GET(DMDATA_STATUS, DMDATA_DONE, &status);
 688         return (status == 1);
 689 }
 690
 691 bool hubp2_program_surface_flip_and_addr(
 692         struct hubp *hubp,
 693         const struct dc_plane_address *address,
 694         bool flip_immediate)
 695 {
 696         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 697
 698         //program flip type
 699         REG_UPDATE(DCSURF_FLIP_CONTROL,
 700                         SURFACE_FLIP_TYPE, flip_immediate);
 701
 702         // Program VMID reg
 703         REG_UPDATE(VMID_SETTINGS_0,
 704                         VMID, address->vmid);
 705
 706         if (address->type == PLN_ADDR_TYPE_GRPH_STEREO) {
 707                 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x1);
 708                 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x1);
 709
 710         } else {
 711                 // turn off stereo if not in stereo
 712                 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_MODE_FOR_STEREOSYNC, 0x0);
 713                 REG_UPDATE(DCSURF_FLIP_CONTROL, SURFACE_FLIP_IN_STEREOSYNC, 0x0);
 714         }
 715
 716
 717
 718         /* HW automatically latch rest of address register on write to
 719          * DCSURF_PRIMARY_SURFACE_ADDRESS if SURFACE_UPDATE_LOCK is not used
 720          *
 721          * program high first and then the low addr, order matters!
 722          */
 723         switch (address->type) {
 724         case PLN_ADDR_TYPE_GRAPHICS:
 725                 /* DCN1.0 does not support const color
 726                  * TODO: program DCHUBBUB_RET_PATH_DCC_CFGx_0/1
 727                  * base on address->grph.dcc_const_color
 728                  * x = 0, 2, 4, 6 for pipe 0, 1, 2, 3 for rgb and luma
 729                  * x = 1, 3, 5, 7 for pipe 0, 1, 2, 3 for chroma
 730                  */
 731
 732                 if (address->grph.addr.quad_part == 0)
 733                         break;
 734
 735                 REG_UPDATE_2(DCSURF_SURFACE_CONTROL,
 736                                 PRIMARY_SURFACE_TMZ, address->tmz_surface,
 737                                 PRIMARY_META_SURFACE_TMZ, address->tmz_surface);
 738
 739                 if (address->grph.meta_addr.quad_part != 0) {
 740                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
 741                                         PRIMARY_META_SURFACE_ADDRESS_HIGH,
 742                                         address->grph.meta_addr.high_part);
 743
 744                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
 745                                         PRIMARY_META_SURFACE_ADDRESS,
 746                                         address->grph.meta_addr.low_part);
 747                 }
 748
 749                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
 750                                 PRIMARY_SURFACE_ADDRESS_HIGH,
 751                                 address->grph.addr.high_part);
 752
 753                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
 754                                 PRIMARY_SURFACE_ADDRESS,
 755                                 address->grph.addr.low_part);
 756                 break;
 757         case PLN_ADDR_TYPE_VIDEO_PROGRESSIVE:
 758                 if (address->video_progressive.luma_addr.quad_part == 0
 759                                 || address->video_progressive.chroma_addr.quad_part == 0)
 760                         break;
 761
 762                 REG_UPDATE_4(DCSURF_SURFACE_CONTROL,
 763                                 PRIMARY_SURFACE_TMZ, address->tmz_surface,
 764                                 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
 765                                 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
 766                                 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface);
 767
 768                 if (address->video_progressive.luma_meta_addr.quad_part != 0) {
 769                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, 0,
 770                                         PRIMARY_META_SURFACE_ADDRESS_HIGH_C,
 771                                         address->video_progressive.chroma_meta_addr.high_part);
 772
 773                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, 0,
 774                                         PRIMARY_META_SURFACE_ADDRESS_C,
 775                                         address->video_progressive.chroma_meta_addr.low_part);
 776
 777                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
 778                                         PRIMARY_META_SURFACE_ADDRESS_HIGH,
 779                                         address->video_progressive.luma_meta_addr.high_part);
 780
 781                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
 782                                         PRIMARY_META_SURFACE_ADDRESS,
 783                                         address->video_progressive.luma_meta_addr.low_part);
 784                 }
 785
 786                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C, 0,
 787                                 PRIMARY_SURFACE_ADDRESS_HIGH_C,
 788                                 address->video_progressive.chroma_addr.high_part);
 789
 790                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_C, 0,
 791                                 PRIMARY_SURFACE_ADDRESS_C,
 792                                 address->video_progressive.chroma_addr.low_part);
 793
 794                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
 795                                 PRIMARY_SURFACE_ADDRESS_HIGH,
 796                                 address->video_progressive.luma_addr.high_part);
 797
 798                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
 799                                 PRIMARY_SURFACE_ADDRESS,
 800                                 address->video_progressive.luma_addr.low_part);
 801                 break;
 802         case PLN_ADDR_TYPE_GRPH_STEREO:
 803                 if (address->grph_stereo.left_addr.quad_part == 0)
 804                         break;
 805                 if (address->grph_stereo.right_addr.quad_part == 0)
 806                         break;
 807
 808                 REG_UPDATE_8(DCSURF_SURFACE_CONTROL,
 809                                 PRIMARY_SURFACE_TMZ, address->tmz_surface,
 810                                 PRIMARY_SURFACE_TMZ_C, address->tmz_surface,
 811                                 PRIMARY_META_SURFACE_TMZ, address->tmz_surface,
 812                                 PRIMARY_META_SURFACE_TMZ_C, address->tmz_surface,
 813                                 SECONDARY_SURFACE_TMZ, address->tmz_surface,
 814                                 SECONDARY_SURFACE_TMZ_C, address->tmz_surface,
 815                                 SECONDARY_META_SURFACE_TMZ, address->tmz_surface,
 816                                 SECONDARY_META_SURFACE_TMZ_C, address->tmz_surface);
 817
 818                 if (address->grph_stereo.right_meta_addr.quad_part != 0) {
 819
 820                         REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH, 0,
 821                                         SECONDARY_META_SURFACE_ADDRESS_HIGH,
 822                                         address->grph_stereo.right_meta_addr.high_part);
 823
 824                         REG_SET(DCSURF_SECONDARY_META_SURFACE_ADDRESS, 0,
 825                                         SECONDARY_META_SURFACE_ADDRESS,
 826                                         address->grph_stereo.right_meta_addr.low_part);
 827                 }
 828                 if (address->grph_stereo.left_meta_addr.quad_part != 0) {
 829
 830                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH, 0,
 831                                         PRIMARY_META_SURFACE_ADDRESS_HIGH,
 832                                         address->grph_stereo.left_meta_addr.high_part);
 833
 834                         REG_SET(DCSURF_PRIMARY_META_SURFACE_ADDRESS, 0,
 835                                         PRIMARY_META_SURFACE_ADDRESS,
 836                                         address->grph_stereo.left_meta_addr.low_part);
 837                 }
 838
 839                 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH, 0,
 840                                 SECONDARY_SURFACE_ADDRESS_HIGH,
 841                                 address->grph_stereo.right_addr.high_part);
 842
 843                 REG_SET(DCSURF_SECONDARY_SURFACE_ADDRESS, 0,
 844                                 SECONDARY_SURFACE_ADDRESS,
 845                                 address->grph_stereo.right_addr.low_part);
 846
 847                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH, 0,
 848                                 PRIMARY_SURFACE_ADDRESS_HIGH,
 849                                 address->grph_stereo.left_addr.high_part);
 850
 851                 REG_SET(DCSURF_PRIMARY_SURFACE_ADDRESS, 0,
 852                                 PRIMARY_SURFACE_ADDRESS,
 853                                 address->grph_stereo.left_addr.low_part);
 854                 break;
 855         default:
 856                 BREAK_TO_DEBUGGER();
 857                 break;
 858         }
 859
 860         hubp->request_address = *address;
 861
 862         return true;
 863 }
 864
 865 void hubp2_enable_triplebuffer(
 866         struct hubp *hubp,
 867         bool enable)
 868 {
 869         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 870         uint32_t triple_buffer_en = 0;
 871         bool tri_buffer_en;
 872
 873         REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en);
 874         tri_buffer_en = (triple_buffer_en == 1);
 875         if (tri_buffer_en != enable) {
 876                 REG_UPDATE(DCSURF_FLIP_CONTROL2,
 877                         SURFACE_TRIPLE_BUFFER_ENABLE, enable ? DC_TRIPLEBUFFER_ENABLE : DC_TRIPLEBUFFER_DISABLE);
 878         }
 879 }
 880
 881 bool hubp2_is_triplebuffer_enabled(
 882         struct hubp *hubp)
 883 {
 884         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 885         uint32_t triple_buffer_en = 0;
 886
 887         REG_GET(DCSURF_FLIP_CONTROL2, SURFACE_TRIPLE_BUFFER_ENABLE, &triple_buffer_en);
 888
 889         return (bool)triple_buffer_en;
 890 }
 891
 892 void hubp2_set_flip_control_surface_gsl(struct hubp *hubp, bool enable)
 893 {
 894         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 895
 896         REG_UPDATE(DCSURF_FLIP_CONTROL2, SURFACE_GSL_ENABLE, enable ? 1 : 0);
 897 }
 898
 899 bool hubp2_is_flip_pending(struct hubp *hubp)
 900 {
 901         uint32_t flip_pending = 0;
 902         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 903         struct dc_plane_address earliest_inuse_address;
 904
 905         if (hubp && hubp->power_gated)
 906                 return false;
 907
 908         REG_GET(DCSURF_FLIP_CONTROL,
 909                         SURFACE_FLIP_PENDING, &flip_pending);
 910
 911         REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
 912                         SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part);
 913
 914         REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
 915                         SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part);
 916
 917         if (flip_pending)
 918                 return true;
 919
 920         if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part)
 921                 return true;
 922
 923         return false;
 924 }
 925
 926 void hubp2_set_blank(struct hubp *hubp, bool blank)
 927 {
 928         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 929         uint32_t blank_en = blank ? 1 : 0;
 930
 931         REG_UPDATE_2(DCHUBP_CNTL,
 932                         HUBP_BLANK_EN, blank_en,
 933                         HUBP_TTU_DISABLE, blank_en);
 934
 935         if (blank) {
 936                 uint32_t reg_val = REG_READ(DCHUBP_CNTL);
 937
 938                 if (reg_val) {
 939                         /* init sequence workaround: in case HUBP is
 940                          * power gated, this wait would timeout.
 941                          *
 942                          * we just wrote reg_val to non-0, if it stay 0
 943                          * it means HUBP is gated
 944                          */
 945                         REG_WAIT(DCHUBP_CNTL,
 946                                         HUBP_NO_OUTSTANDING_REQ, 1,
 947                                         1, 200);
 948                 }
 949
 950                 hubp->mpcc_id = 0xf;
 951                 hubp->opp_id = OPP_ID_INVALID;
 952         }
 953 }
 954
 955 void hubp2_cursor_set_position(
 956                 struct hubp *hubp,
 957                 const struct dc_cursor_position *pos,
 958                 const struct dc_cursor_mi_param *param)
 959 {
 960         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
 961         int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x;
 962         int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y;
 963         int x_hotspot = pos->x_hotspot;
 964         int y_hotspot = pos->y_hotspot;
 965         int cursor_height = (int)hubp->curs_attr.height;
 966         int cursor_width = (int)hubp->curs_attr.width;
 967         uint32_t dst_x_offset;
 968         uint32_t cur_en = pos->enable ? 1 : 0;
 969
 970         /*
 971          * Guard aganst cursor_set_position() from being called with invalid
 972          * attributes
 973          *
 974          * TODO: Look at combining cursor_set_position() and
 975          * cursor_set_attributes() into cursor_update()
 976          */
 977         if (hubp->curs_attr.address.quad_part == 0)
 978                 return;
 979
 980         // Rotated cursor width/height and hotspots tweaks for offset calculation
 981         if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
 982                 swap(cursor_height, cursor_width);
 983                 if (param->rotation == ROTATION_ANGLE_90) {
 984                         src_x_offset = pos->x - pos->y_hotspot - param->viewport.x;
 985                         src_y_offset = pos->y - pos->x_hotspot - param->viewport.y;
 986                 }
 987         } else if (param->rotation == ROTATION_ANGLE_180) {
 988                 src_x_offset = pos->x - param->viewport.x;
 989                 src_y_offset = pos->y - param->viewport.y;
 990         }
 991
 992         if (param->mirror) {
 993                 x_hotspot = param->viewport.width - x_hotspot;
 994                 src_x_offset = param->viewport.x + param->viewport.width - src_x_offset;
 995         }
 996
 997         dst_x_offset = (src_x_offset >= 0) ? src_x_offset : 0;
 998         dst_x_offset *= param->ref_clk_khz;
 999         dst_x_offset /= param->pixel_clk_khz;
1000
1001         ASSERT(param->h_scale_ratio.value);
1002
1003         if (param->h_scale_ratio.value)
1004                 dst_x_offset = dc_fixpt_floor(dc_fixpt_div(
1005                                 dc_fixpt_from_int(dst_x_offset),
1006                                 param->h_scale_ratio));
1007
1008         if (src_x_offset >= (int)param->viewport.width)
1009                 cur_en = 0;  /* not visible beyond right edge*/
1010
1011         if (src_x_offset + cursor_width <= 0)
1012                 cur_en = 0;  /* not visible beyond left edge*/
1013
1014         if (src_y_offset >= (int)param->viewport.height)
1015                 cur_en = 0;  /* not visible beyond bottom edge*/
1016
1017         if (src_y_offset + cursor_height <= 0)
1018                 cur_en = 0;  /* not visible beyond top edge*/
1019
1020         if (cur_en && REG_READ(CURSOR_SURFACE_ADDRESS) == 0)
1021                 hubp->funcs->set_cursor_attributes(hubp, &hubp->curs_attr);
1022
1023         REG_UPDATE(CURSOR_CONTROL,
1024                         CURSOR_ENABLE, cur_en);
1025
1026         REG_SET_2(CURSOR_POSITION, 0,
1027                         CURSOR_X_POSITION, pos->x,
1028                         CURSOR_Y_POSITION, pos->y);
1029
1030         REG_SET_2(CURSOR_HOT_SPOT, 0,
1031                         CURSOR_HOT_SPOT_X, x_hotspot,
1032                         CURSOR_HOT_SPOT_Y, y_hotspot);
1033
1034         REG_SET(CURSOR_DST_OFFSET, 0,
1035                         CURSOR_DST_X_OFFSET, dst_x_offset);
1036         /* TODO Handle surface pixel formats other than 4:4:4 */
1037 }
1038
1039 void hubp2_clk_cntl(struct hubp *hubp, bool enable)
1040 {
1041         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1042         uint32_t clk_enable = enable ? 1 : 0;
1043
1044         REG_UPDATE(HUBP_CLK_CNTL, HUBP_CLOCK_ENABLE, clk_enable);
1045 }
1046
1047 void hubp2_vtg_sel(struct hubp *hubp, uint32_t otg_inst)
1048 {
1049         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1050
1051         REG_UPDATE(DCHUBP_CNTL, HUBP_VTG_SEL, otg_inst);
1052 }
1053
1054 void hubp2_clear_underflow(struct hubp *hubp)
1055 {
1056         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1057
1058         REG_UPDATE(DCHUBP_CNTL, HUBP_UNDERFLOW_CLEAR, 1);
1059 }
1060
1061 void hubp2_read_state_common(struct hubp *hubp)
1062 {
1063         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1064         struct dcn_hubp_state *s = &hubp2->state;
1065         struct _vcs_dpi_display_dlg_regs_st *dlg_attr = &s->dlg_attr;
1066         struct _vcs_dpi_display_ttu_regs_st *ttu_attr = &s->ttu_attr;
1067         struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
1068
1069         /* Requester */
1070         REG_GET(HUBPRET_CONTROL,
1071                         DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs->plane1_base_address);
1072         REG_GET_4(DCN_EXPANSION_MODE,
1073                         DRQ_EXPANSION_MODE, &rq_regs->drq_expansion_mode,
1074                         PRQ_EXPANSION_MODE, &rq_regs->prq_expansion_mode,
1075                         MRQ_EXPANSION_MODE, &rq_regs->mrq_expansion_mode,
1076                         CRQ_EXPANSION_MODE, &rq_regs->crq_expansion_mode);
1077
1078         /* DLG - Per hubp */
1079         REG_GET_2(BLANK_OFFSET_0,
1080                 REFCYC_H_BLANK_END, &dlg_attr->refcyc_h_blank_end,
1081                 DLG_V_BLANK_END, &dlg_attr->dlg_vblank_end);
1082
1083         REG_GET(BLANK_OFFSET_1,
1084                 MIN_DST_Y_NEXT_START, &dlg_attr->min_dst_y_next_start);
1085
1086         REG_GET(DST_DIMENSIONS,
1087                 REFCYC_PER_HTOTAL, &dlg_attr->refcyc_per_htotal);
1088
1089         REG_GET_2(DST_AFTER_SCALER,
1090                 REFCYC_X_AFTER_SCALER, &dlg_attr->refcyc_x_after_scaler,
1091                 DST_Y_AFTER_SCALER, &dlg_attr->dst_y_after_scaler);
1092
1093         if (REG(PREFETCH_SETTINS))
1094                 REG_GET_2(PREFETCH_SETTINS,
1095                         DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
1096                         VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
1097         else
1098                 REG_GET_2(PREFETCH_SETTINGS,
1099                         DST_Y_PREFETCH, &dlg_attr->dst_y_prefetch,
1100                         VRATIO_PREFETCH, &dlg_attr->vratio_prefetch);
1101
1102         REG_GET_2(VBLANK_PARAMETERS_0,
1103                 DST_Y_PER_VM_VBLANK, &dlg_attr->dst_y_per_vm_vblank,
1104                 DST_Y_PER_ROW_VBLANK, &dlg_attr->dst_y_per_row_vblank);
1105
1106         REG_GET(REF_FREQ_TO_PIX_FREQ,
1107                 REF_FREQ_TO_PIX_FREQ, &dlg_attr->ref_freq_to_pix_freq);
1108
1109         /* DLG - Per luma/chroma */
1110         REG_GET(VBLANK_PARAMETERS_1,
1111                 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr->refcyc_per_pte_group_vblank_l);
1112
1113         REG_GET(VBLANK_PARAMETERS_3,
1114                 REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l);
1115
1116         if (REG(NOM_PARAMETERS_0))
1117                 REG_GET(NOM_PARAMETERS_0,
1118                         DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr->dst_y_per_pte_row_nom_l);
1119
1120         if (REG(NOM_PARAMETERS_1))
1121                 REG_GET(NOM_PARAMETERS_1,
1122                         REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr->refcyc_per_pte_group_nom_l);
1123
1124         REG_GET(NOM_PARAMETERS_4,
1125                 DST_Y_PER_META_ROW_NOM_L, &dlg_attr->dst_y_per_meta_row_nom_l);
1126
1127         REG_GET(NOM_PARAMETERS_5,
1128                 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr->refcyc_per_meta_chunk_nom_l);
1129
1130         REG_GET_2(PER_LINE_DELIVERY_PRE,
1131                 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l,
1132                 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr->refcyc_per_line_delivery_pre_c);
1133
1134         REG_GET_2(PER_LINE_DELIVERY,
1135                 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr->refcyc_per_line_delivery_l,
1136                 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr->refcyc_per_line_delivery_c);
1137
1138         if (REG(PREFETCH_SETTINS_C))
1139                 REG_GET(PREFETCH_SETTINS_C,
1140                         VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
1141         else
1142                 REG_GET(PREFETCH_SETTINGS_C,
1143                         VRATIO_PREFETCH_C, &dlg_attr->vratio_prefetch_c);
1144
1145         REG_GET(VBLANK_PARAMETERS_2,
1146                 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr->refcyc_per_pte_group_vblank_c);
1147
1148         REG_GET(VBLANK_PARAMETERS_4,
1149                 REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr->refcyc_per_meta_chunk_vblank_c);
1150
1151         if (REG(NOM_PARAMETERS_2))
1152                 REG_GET(NOM_PARAMETERS_2,
1153                         DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr->dst_y_per_pte_row_nom_c);
1154
1155         if (REG(NOM_PARAMETERS_3))
1156                 REG_GET(NOM_PARAMETERS_3,
1157                         REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr->refcyc_per_pte_group_nom_c);
1158
1159         REG_GET(NOM_PARAMETERS_6,
1160                 DST_Y_PER_META_ROW_NOM_C, &dlg_attr->dst_y_per_meta_row_nom_c);
1161
1162         REG_GET(NOM_PARAMETERS_7,
1163                 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr->refcyc_per_meta_chunk_nom_c);
1164
1165         /* TTU - per hubp */
1166         REG_GET_2(DCN_TTU_QOS_WM,
1167                 QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm,
1168                 QoS_LEVEL_HIGH_WM, &ttu_attr->qos_level_high_wm);
1169
1170         REG_GET_2(DCN_GLOBAL_TTU_CNTL,
1171                 MIN_TTU_VBLANK, &ttu_attr->min_ttu_vblank,
1172                 QoS_LEVEL_FLIP, &ttu_attr->qos_level_flip);
1173
1174         /* TTU - per luma/chroma */
1175         /* Assumed surf0 is luma and 1 is chroma */
1176
1177         REG_GET_3(DCN_SURF0_TTU_CNTL0,
1178                 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_l,
1179                 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_l,
1180                 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_l);
1181
1182         REG_GET(DCN_SURF0_TTU_CNTL1,
1183                 REFCYC_PER_REQ_DELIVERY_PRE,
1184                 &ttu_attr->refcyc_per_req_delivery_pre_l);
1185
1186         REG_GET_3(DCN_SURF1_TTU_CNTL0,
1187                 REFCYC_PER_REQ_DELIVERY, &ttu_attr->refcyc_per_req_delivery_c,
1188                 QoS_LEVEL_FIXED, &ttu_attr->qos_level_fixed_c,
1189                 QoS_RAMP_DISABLE, &ttu_attr->qos_ramp_disable_c);
1190
1191         REG_GET(DCN_SURF1_TTU_CNTL1,
1192                 REFCYC_PER_REQ_DELIVERY_PRE,
1193                 &ttu_attr->refcyc_per_req_delivery_pre_c);
1194
1195         /* Rest of hubp */
1196         REG_GET(DCSURF_SURFACE_CONFIG,
1197                         SURFACE_PIXEL_FORMAT, &s->pixel_format);
1198
1199         REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
1200                         SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &s->inuse_addr_hi);
1201
1202         REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
1203                         SURFACE_EARLIEST_INUSE_ADDRESS, &s->inuse_addr_lo);
1204
1205         REG_GET_2(DCSURF_PRI_VIEWPORT_DIMENSION,
1206                         PRI_VIEWPORT_WIDTH, &s->viewport_width,
1207                         PRI_VIEWPORT_HEIGHT, &s->viewport_height);
1208
1209         REG_GET_2(DCSURF_SURFACE_CONFIG,
1210                         ROTATION_ANGLE, &s->rotation_angle,
1211                         H_MIRROR_EN, &s->h_mirror_en);
1212
1213         REG_GET(DCSURF_TILING_CONFIG,
1214                         SW_MODE, &s->sw_mode);
1215
1216         REG_GET(DCSURF_SURFACE_CONTROL,
1217                         PRIMARY_SURFACE_DCC_EN, &s->dcc_en);
1218
1219         REG_GET_3(DCHUBP_CNTL,
1220                         HUBP_BLANK_EN, &s->blank_en,
1221                         HUBP_TTU_DISABLE, &s->ttu_disable,
1222                         HUBP_UNDERFLOW_STATUS, &s->underflow_status);
1223
1224         REG_GET(HUBP_CLK_CNTL,
1225                         HUBP_CLOCK_ENABLE, &s->clock_en);
1226
1227         REG_GET(DCN_GLOBAL_TTU_CNTL,
1228                         MIN_TTU_VBLANK, &s->min_ttu_vblank);
1229
1230         REG_GET_2(DCN_TTU_QOS_WM,
1231                         QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,
1232                         QoS_LEVEL_HIGH_WM, &s->qos_level_high_wm);
1233
1234 }
1235
1236 void hubp2_read_state(struct hubp *hubp)
1237 {
1238         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1239         struct dcn_hubp_state *s = &hubp2->state;
1240         struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
1241
1242         hubp2_read_state_common(hubp);
1243
1244         REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
1245                 CHUNK_SIZE, &rq_regs->rq_regs_l.chunk_size,
1246                 MIN_CHUNK_SIZE, &rq_regs->rq_regs_l.min_chunk_size,
1247                 META_CHUNK_SIZE, &rq_regs->rq_regs_l.meta_chunk_size,
1248                 MIN_META_CHUNK_SIZE, &rq_regs->rq_regs_l.min_meta_chunk_size,
1249                 DPTE_GROUP_SIZE, &rq_regs->rq_regs_l.dpte_group_size,
1250                 MPTE_GROUP_SIZE, &rq_regs->rq_regs_l.mpte_group_size,
1251                 SWATH_HEIGHT, &rq_regs->rq_regs_l.swath_height,
1252                 PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
1253
1254         REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
1255                 CHUNK_SIZE_C, &rq_regs->rq_regs_c.chunk_size,
1256                 MIN_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_chunk_size,
1257                 META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.meta_chunk_size,
1258                 MIN_META_CHUNK_SIZE_C, &rq_regs->rq_regs_c.min_meta_chunk_size,
1259                 DPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.dpte_group_size,
1260                 MPTE_GROUP_SIZE_C, &rq_regs->rq_regs_c.mpte_group_size,
1261                 SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
1262                 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
1263
1264 }
1265
1266 void hubp2_validate_dml_output(struct hubp *hubp,
1267                 struct dc_context *ctx,
1268                 struct _vcs_dpi_display_rq_regs_st *dml_rq_regs,
1269                 struct _vcs_dpi_display_dlg_regs_st *dml_dlg_attr,
1270                 struct _vcs_dpi_display_ttu_regs_st *dml_ttu_attr)
1271 {
1272         struct dcn20_hubp *hubp2 = TO_DCN20_HUBP(hubp);
1273         struct _vcs_dpi_display_rq_regs_st rq_regs = {0};
1274         struct _vcs_dpi_display_dlg_regs_st dlg_attr = {0};
1275         struct _vcs_dpi_display_ttu_regs_st ttu_attr = {0};
1276         DC_LOGGER_INIT(ctx->logger);
1277         DC_LOG_DEBUG("DML Validation | Running Validation");
1278
1279         /* Requestor Regs */
1280         REG_GET(HUBPRET_CONTROL,
1281                 DET_BUF_PLANE1_BASE_ADDRESS, &rq_regs.plane1_base_address);
1282         REG_GET_4(DCN_EXPANSION_MODE,
1283                 DRQ_EXPANSION_MODE, &rq_regs.drq_expansion_mode,
1284                 PRQ_EXPANSION_MODE, &rq_regs.prq_expansion_mode,
1285                 MRQ_EXPANSION_MODE, &rq_regs.mrq_expansion_mode,
1286                 CRQ_EXPANSION_MODE, &rq_regs.crq_expansion_mode);
1287         REG_GET_8(DCHUBP_REQ_SIZE_CONFIG,
1288                 CHUNK_SIZE, &rq_regs.rq_regs_l.chunk_size,
1289                 MIN_CHUNK_SIZE, &rq_regs.rq_regs_l.min_chunk_size,
1290                 META_CHUNK_SIZE, &rq_regs.rq_regs_l.meta_chunk_size,
1291                 MIN_META_CHUNK_SIZE, &rq_regs.rq_regs_l.min_meta_chunk_size,
1292                 DPTE_GROUP_SIZE, &rq_regs.rq_regs_l.dpte_group_size,
1293                 MPTE_GROUP_SIZE, &rq_regs.rq_regs_l.mpte_group_size,
1294                 SWATH_HEIGHT, &rq_regs.rq_regs_l.swath_height,
1295                 PTE_ROW_HEIGHT_LINEAR, &rq_regs.rq_regs_l.pte_row_height_linear);
1296         REG_GET_8(DCHUBP_REQ_SIZE_CONFIG_C,
1297                 CHUNK_SIZE_C, &rq_regs.rq_regs_c.chunk_size,
1298                 MIN_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_chunk_size,
1299                 META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.meta_chunk_size,
1300                 MIN_META_CHUNK_SIZE_C, &rq_regs.rq_regs_c.min_meta_chunk_size,
1301                 DPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.dpte_group_size,
1302                 MPTE_GROUP_SIZE_C, &rq_regs.rq_regs_c.mpte_group_size,
1303                 SWATH_HEIGHT_C, &rq_regs.rq_regs_c.swath_height,
1304                 PTE_ROW_HEIGHT_LINEAR_C, &rq_regs.rq_regs_c.pte_row_height_linear);
1305
1306         if (rq_regs.plane1_base_address != dml_rq_regs->plane1_base_address)
1307                 DC_LOG_DEBUG("DML Validation | HUBPRET_CONTROL:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u  Actual: %u\n",
1308                                 dml_rq_regs->plane1_base_address, rq_regs.plane1_base_address);
1309         if (rq_regs.drq_expansion_mode != dml_rq_regs->drq_expansion_mode)
1310                 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DRQ_EXPANSION_MODE - Expected: %u  Actual: %u\n",
1311                                 dml_rq_regs->drq_expansion_mode, rq_regs.drq_expansion_mode);
1312         if (rq_regs.prq_expansion_mode != dml_rq_regs->prq_expansion_mode)
1313                 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:MRQ_EXPANSION_MODE - Expected: %u  Actual: %u\n",
1314                                 dml_rq_regs->prq_expansion_mode, rq_regs.prq_expansion_mode);
1315         if (rq_regs.mrq_expansion_mode != dml_rq_regs->mrq_expansion_mode)
1316                 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:DET_BUF_PLANE1_BASE_ADDRESS - Expected: %u  Actual: %u\n",
1317                                 dml_rq_regs->mrq_expansion_mode, rq_regs.mrq_expansion_mode);
1318         if (rq_regs.crq_expansion_mode != dml_rq_regs->crq_expansion_mode)
1319                 DC_LOG_DEBUG("DML Validation | DCN_EXPANSION_MODE:CRQ_EXPANSION_MODE - Expected: %u  Actual: %u\n",
1320                                 dml_rq_regs->crq_expansion_mode, rq_regs.crq_expansion_mode);
1321
1322         if (rq_regs.rq_regs_l.chunk_size != dml_rq_regs->rq_regs_l.chunk_size)
1323                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:CHUNK_SIZE - Expected: %u  Actual: %u\n",
1324                                 dml_rq_regs->rq_regs_l.chunk_size, rq_regs.rq_regs_l.chunk_size);
1325         if (rq_regs.rq_regs_l.min_chunk_size != dml_rq_regs->rq_regs_l.min_chunk_size)
1326                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_CHUNK_SIZE - Expected: %u  Actual: %u\n",
1327                                 dml_rq_regs->rq_regs_l.min_chunk_size, rq_regs.rq_regs_l.min_chunk_size);
1328         if (rq_regs.rq_regs_l.meta_chunk_size != dml_rq_regs->rq_regs_l.meta_chunk_size)
1329                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:META_CHUNK_SIZE - Expected: %u  Actual: %u\n",
1330                                 dml_rq_regs->rq_regs_l.meta_chunk_size, rq_regs.rq_regs_l.meta_chunk_size);
1331         if (rq_regs.rq_regs_l.min_meta_chunk_size != dml_rq_regs->rq_regs_l.min_meta_chunk_size)
1332                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MIN_META_CHUNK_SIZE - Expected: %u  Actual: %u\n",
1333                                 dml_rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs.rq_regs_l.min_meta_chunk_size);
1334         if (rq_regs.rq_regs_l.dpte_group_size != dml_rq_regs->rq_regs_l.dpte_group_size)
1335                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:DPTE_GROUP_SIZE - Expected: %u  Actual: %u\n",
1336                                 dml_rq_regs->rq_regs_l.dpte_group_size, rq_regs.rq_regs_l.dpte_group_size);
1337         if (rq_regs.rq_regs_l.mpte_group_size != dml_rq_regs->rq_regs_l.mpte_group_size)
1338                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:MPTE_GROUP_SIZE - Expected: %u  Actual: %u\n",
1339                                 dml_rq_regs->rq_regs_l.mpte_group_size, rq_regs.rq_regs_l.mpte_group_size);
1340         if (rq_regs.rq_regs_l.swath_height != dml_rq_regs->rq_regs_l.swath_height)
1341                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:SWATH_HEIGHT - Expected: %u  Actual: %u\n",
1342                                 dml_rq_regs->rq_regs_l.swath_height, rq_regs.rq_regs_l.swath_height);
1343         if (rq_regs.rq_regs_l.pte_row_height_linear != dml_rq_regs->rq_regs_l.pte_row_height_linear)
1344                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG_C:PTE_ROW_HEIGHT_LINEAR - Expected: %u  Actual: %u\n",
1345                                 dml_rq_regs->rq_regs_l.pte_row_height_linear, rq_regs.rq_regs_l.pte_row_height_linear);
1346
1347         if (rq_regs.rq_regs_c.chunk_size != dml_rq_regs->rq_regs_c.chunk_size)
1348                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
1349                                 dml_rq_regs->rq_regs_c.chunk_size, rq_regs.rq_regs_c.chunk_size);
1350         if (rq_regs.rq_regs_c.min_chunk_size != dml_rq_regs->rq_regs_c.min_chunk_size)
1351                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
1352                                 dml_rq_regs->rq_regs_c.min_chunk_size, rq_regs.rq_regs_c.min_chunk_size);
1353         if (rq_regs.rq_regs_c.meta_chunk_size != dml_rq_regs->rq_regs_c.meta_chunk_size)
1354                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:META_CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
1355                                 dml_rq_regs->rq_regs_c.meta_chunk_size, rq_regs.rq_regs_c.meta_chunk_size);
1356         if (rq_regs.rq_regs_c.min_meta_chunk_size != dml_rq_regs->rq_regs_c.min_meta_chunk_size)
1357                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MIN_META_CHUNK_SIZE_C - Expected: %u  Actual: %u\n",
1358                                 dml_rq_regs->rq_regs_c.min_meta_chunk_size, rq_regs.rq_regs_c.min_meta_chunk_size);
1359         if (rq_regs.rq_regs_c.dpte_group_size != dml_rq_regs->rq_regs_c.dpte_group_size)
1360                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:DPTE_GROUP_SIZE_C - Expected: %u  Actual: %u\n",
1361                                 dml_rq_regs->rq_regs_c.dpte_group_size, rq_regs.rq_regs_c.dpte_group_size);
1362         if (rq_regs.rq_regs_c.mpte_group_size != dml_rq_regs->rq_regs_c.mpte_group_size)
1363                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:MPTE_GROUP_SIZE_C - Expected: %u  Actual: %u\n",
1364                                 dml_rq_regs->rq_regs_c.mpte_group_size, rq_regs.rq_regs_c.mpte_group_size);
1365         if (rq_regs.rq_regs_c.swath_height != dml_rq_regs->rq_regs_c.swath_height)
1366                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:SWATH_HEIGHT_C - Expected: %u  Actual: %u\n",
1367                                 dml_rq_regs->rq_regs_c.swath_height, rq_regs.rq_regs_c.swath_height);
1368         if (rq_regs.rq_regs_c.pte_row_height_linear != dml_rq_regs->rq_regs_c.pte_row_height_linear)
1369                 DC_LOG_DEBUG("DML Validation | DCHUBP_REQ_SIZE_CONFIG:PTE_ROW_HEIGHT_LINEAR_C - Expected: %u  Actual: %u\n",
1370                                 dml_rq_regs->rq_regs_c.pte_row_height_linear, rq_regs.rq_regs_c.pte_row_height_linear);
1371
1372         /* DLG - Per hubp */
1373         REG_GET_2(BLANK_OFFSET_0,
1374                 REFCYC_H_BLANK_END, &dlg_attr.refcyc_h_blank_end,
1375                 DLG_V_BLANK_END, &dlg_attr.dlg_vblank_end);
1376         REG_GET(BLANK_OFFSET_1,
1377                 MIN_DST_Y_NEXT_START, &dlg_attr.min_dst_y_next_start);
1378         REG_GET(DST_DIMENSIONS,
1379                 REFCYC_PER_HTOTAL, &dlg_attr.refcyc_per_htotal);
1380         REG_GET_2(DST_AFTER_SCALER,
1381                 REFCYC_X_AFTER_SCALER, &dlg_attr.refcyc_x_after_scaler,
1382                 DST_Y_AFTER_SCALER, &dlg_attr.dst_y_after_scaler);
1383         REG_GET(REF_FREQ_TO_PIX_FREQ,
1384                 REF_FREQ_TO_PIX_FREQ, &dlg_attr.ref_freq_to_pix_freq);
1385
1386         if (dlg_attr.refcyc_h_blank_end != dml_dlg_attr->refcyc_h_blank_end)
1387                 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:REFCYC_H_BLANK_END - Expected: %u  Actual: %u\n",
1388                                 dml_dlg_attr->refcyc_h_blank_end, dlg_attr.refcyc_h_blank_end);
1389         if (dlg_attr.dlg_vblank_end != dml_dlg_attr->dlg_vblank_end)
1390                 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_0:DLG_V_BLANK_END - Expected: %u  Actual: %u\n",
1391                                 dml_dlg_attr->dlg_vblank_end, dlg_attr.dlg_vblank_end);
1392         if (dlg_attr.min_dst_y_next_start != dml_dlg_attr->min_dst_y_next_start)
1393                 DC_LOG_DEBUG("DML Validation | BLANK_OFFSET_1:MIN_DST_Y_NEXT_START - Expected: %u  Actual: %u\n",
1394                                 dml_dlg_attr->min_dst_y_next_start, dlg_attr.min_dst_y_next_start);
1395         if (dlg_attr.refcyc_per_htotal != dml_dlg_attr->refcyc_per_htotal)
1396                 DC_LOG_DEBUG("DML Validation | DST_DIMENSIONS:REFCYC_PER_HTOTAL - Expected: %u  Actual: %u\n",
1397                                 dml_dlg_attr->refcyc_per_htotal, dlg_attr.refcyc_per_htotal);
1398         if (dlg_attr.refcyc_x_after_scaler != dml_dlg_attr->refcyc_x_after_scaler)
1399                 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:REFCYC_X_AFTER_SCALER - Expected: %u  Actual: %u\n",
1400                                 dml_dlg_attr->refcyc_x_after_scaler, dlg_attr.refcyc_x_after_scaler);
1401         if (dlg_attr.dst_y_after_scaler != dml_dlg_attr->dst_y_after_scaler)
1402                 DC_LOG_DEBUG("DML Validation | DST_AFTER_SCALER:DST_Y_AFTER_SCALER - Expected: %u  Actual: %u\n",
1403                                 dml_dlg_attr->dst_y_after_scaler, dlg_attr.dst_y_after_scaler);
1404         if (dlg_attr.ref_freq_to_pix_freq != dml_dlg_attr->ref_freq_to_pix_freq)
1405                 DC_LOG_DEBUG("DML Validation | REF_FREQ_TO_PIX_FREQ:REF_FREQ_TO_PIX_FREQ - Expected: %u  Actual: %u\n",
1406                                 dml_dlg_attr->ref_freq_to_pix_freq, dlg_attr.ref_freq_to_pix_freq);
1407
1408         /* DLG - Per luma/chroma */
1409         REG_GET(VBLANK_PARAMETERS_1,
1410                 REFCYC_PER_PTE_GROUP_VBLANK_L, &dlg_attr.refcyc_per_pte_group_vblank_l);
1411         if (REG(NOM_PARAMETERS_0))
1412                 REG_GET(NOM_PARAMETERS_0,
1413                         DST_Y_PER_PTE_ROW_NOM_L, &dlg_attr.dst_y_per_pte_row_nom_l);
1414         if (REG(NOM_PARAMETERS_1))
1415                 REG_GET(NOM_PARAMETERS_1,
1416                         REFCYC_PER_PTE_GROUP_NOM_L, &dlg_attr.refcyc_per_pte_group_nom_l);
1417         REG_GET(NOM_PARAMETERS_4,
1418                 DST_Y_PER_META_ROW_NOM_L, &dlg_attr.dst_y_per_meta_row_nom_l);
1419         REG_GET(NOM_PARAMETERS_5,
1420                 REFCYC_PER_META_CHUNK_NOM_L, &dlg_attr.refcyc_per_meta_chunk_nom_l);
1421         REG_GET_2(PER_LINE_DELIVERY,
1422                 REFCYC_PER_LINE_DELIVERY_L, &dlg_attr.refcyc_per_line_delivery_l,
1423                 REFCYC_PER_LINE_DELIVERY_C, &dlg_attr.refcyc_per_line_delivery_c);
1424         REG_GET_2(PER_LINE_DELIVERY_PRE,
1425                 REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr.refcyc_per_line_delivery_pre_l,
1426                 REFCYC_PER_LINE_DELIVERY_PRE_C, &dlg_attr.refcyc_per_line_delivery_pre_c);
1427         REG_GET(VBLANK_PARAMETERS_2,
1428                 REFCYC_PER_PTE_GROUP_VBLANK_C, &dlg_attr.refcyc_per_pte_group_vblank_c);
1429         if (REG(NOM_PARAMETERS_2))
1430                 REG_GET(NOM_PARAMETERS_2,
1431                         DST_Y_PER_PTE_ROW_NOM_C, &dlg_attr.dst_y_per_pte_row_nom_c);
1432         if (REG(NOM_PARAMETERS_3))
1433                 REG_GET(NOM_PARAMETERS_3,
1434                         REFCYC_PER_PTE_GROUP_NOM_C, &dlg_attr.refcyc_per_pte_group_nom_c);
1435         REG_GET(NOM_PARAMETERS_6,
1436                 DST_Y_PER_META_ROW_NOM_C, &dlg_attr.dst_y_per_meta_row_nom_c);
1437         REG_GET(NOM_PARAMETERS_7,
1438                 REFCYC_PER_META_CHUNK_NOM_C, &dlg_attr.refcyc_per_meta_chunk_nom_c);
1439         REG_GET(VBLANK_PARAMETERS_3,
1440                         REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr.refcyc_per_meta_chunk_vblank_l);
1441         REG_GET(VBLANK_PARAMETERS_4,
1442                         REFCYC_PER_META_CHUNK_VBLANK_C, &dlg_attr.refcyc_per_meta_chunk_vblank_c);
1443
1444         if (dlg_attr.refcyc_per_pte_group_vblank_l != dml_dlg_attr->refcyc_per_pte_group_vblank_l)
1445                 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_1:REFCYC_PER_PTE_GROUP_VBLANK_L - Expected: %u  Actual: %u\n",
1446                                 dml_dlg_attr->refcyc_per_pte_group_vblank_l, dlg_attr.refcyc_per_pte_group_vblank_l);
1447         if (dlg_attr.dst_y_per_pte_row_nom_l != dml_dlg_attr->dst_y_per_pte_row_nom_l)
1448                 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_0:DST_Y_PER_PTE_ROW_NOM_L - Expected: %u  Actual: %u\n",
1449                                 dml_dlg_attr->dst_y_per_pte_row_nom_l, dlg_attr.dst_y_per_pte_row_nom_l);
1450         if (dlg_attr.refcyc_per_pte_group_nom_l != dml_dlg_attr->refcyc_per_pte_group_nom_l)
1451                 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_1:REFCYC_PER_PTE_GROUP_NOM_L - Expected: %u  Actual: %u\n",
1452                                 dml_dlg_attr->refcyc_per_pte_group_nom_l, dlg_attr.refcyc_per_pte_group_nom_l);
1453         if (dlg_attr.dst_y_per_meta_row_nom_l != dml_dlg_attr->dst_y_per_meta_row_nom_l)
1454                 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_4:DST_Y_PER_META_ROW_NOM_L - Expected: %u  Actual: %u\n",
1455                                 dml_dlg_attr->dst_y_per_meta_row_nom_l, dlg_attr.dst_y_per_meta_row_nom_l);
1456         if (dlg_attr.refcyc_per_meta_chunk_nom_l != dml_dlg_attr->refcyc_per_meta_chunk_nom_l)
1457                 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_5:REFCYC_PER_META_CHUNK_NOM_L - Expected: %u  Actual: %u\n",
1458                                 dml_dlg_attr->refcyc_per_meta_chunk_nom_l, dlg_attr.refcyc_per_meta_chunk_nom_l);
1459         if (dlg_attr.refcyc_per_line_delivery_l != dml_dlg_attr->refcyc_per_line_delivery_l)
1460                 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_L - Expected: %u  Actual: %u\n",
1461                                 dml_dlg_attr->refcyc_per_line_delivery_l, dlg_attr.refcyc_per_line_delivery_l);
1462         if (dlg_attr.refcyc_per_line_delivery_c != dml_dlg_attr->refcyc_per_line_delivery_c)
1463                 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY:REFCYC_PER_LINE_DELIVERY_C - Expected: %u  Actual: %u\n",
1464                                 dml_dlg_attr->refcyc_per_line_delivery_c, dlg_attr.refcyc_per_line_delivery_c);
1465         if (dlg_attr.refcyc_per_pte_group_vblank_c != dml_dlg_attr->refcyc_per_pte_group_vblank_c)
1466                 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_2:REFCYC_PER_PTE_GROUP_VBLANK_C - Expected: %u  Actual: %u\n",
1467                                 dml_dlg_attr->refcyc_per_pte_group_vblank_c, dlg_attr.refcyc_per_pte_group_vblank_c);
1468         if (dlg_attr.dst_y_per_pte_row_nom_c != dml_dlg_attr->dst_y_per_pte_row_nom_c)
1469                 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_2:DST_Y_PER_PTE_ROW_NOM_C - Expected: %u  Actual: %u\n",
1470                                 dml_dlg_attr->dst_y_per_pte_row_nom_c, dlg_attr.dst_y_per_pte_row_nom_c);
1471         if (dlg_attr.refcyc_per_pte_group_nom_c != dml_dlg_attr->refcyc_per_pte_group_nom_c)
1472                 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_3:REFCYC_PER_PTE_GROUP_NOM_C - Expected: %u  Actual: %u\n",
1473                                 dml_dlg_attr->refcyc_per_pte_group_nom_c, dlg_attr.refcyc_per_pte_group_nom_c);
1474         if (dlg_attr.dst_y_per_meta_row_nom_c != dml_dlg_attr->dst_y_per_meta_row_nom_c)
1475                 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_6:DST_Y_PER_META_ROW_NOM_C - Expected: %u  Actual: %u\n",
1476                                 dml_dlg_attr->dst_y_per_meta_row_nom_c, dlg_attr.dst_y_per_meta_row_nom_c);
1477         if (dlg_attr.refcyc_per_meta_chunk_nom_c != dml_dlg_attr->refcyc_per_meta_chunk_nom_c)
1478                 DC_LOG_DEBUG("DML Validation | NOM_PARAMETERS_7:REFCYC_PER_META_CHUNK_NOM_C - Expected: %u  Actual: %u\n",
1479                                 dml_dlg_attr->refcyc_per_meta_chunk_nom_c, dlg_attr.refcyc_per_meta_chunk_nom_c);
1480         if (dlg_attr.refcyc_per_line_delivery_pre_l != dml_dlg_attr->refcyc_per_line_delivery_pre_l)
1481                 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_L - Expected: %u  Actual: %u\n",
1482                                 dml_dlg_attr->refcyc_per_line_delivery_pre_l, dlg_attr.refcyc_per_line_delivery_pre_l);
1483         if (dlg_attr.refcyc_per_line_delivery_pre_c != dml_dlg_attr->refcyc_per_line_delivery_pre_c)
1484                 DC_LOG_DEBUG("DML Validation | PER_LINE_DELIVERY_PRE:REFCYC_PER_LINE_DELIVERY_PRE_C - Expected: %u  Actual: %u\n",
1485                                 dml_dlg_attr->refcyc_per_line_delivery_pre_c, dlg_attr.refcyc_per_line_delivery_pre_c);
1486         if (dlg_attr.refcyc_per_meta_chunk_vblank_l != dml_dlg_attr->refcyc_per_meta_chunk_vblank_l)
1487                 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_3:REFCYC_PER_META_CHUNK_VBLANK_L - Expected: %u  Actual: %u\n",
1488                                 dml_dlg_attr->refcyc_per_meta_chunk_vblank_l, dlg_attr.refcyc_per_meta_chunk_vblank_l);
1489         if (dlg_attr.refcyc_per_meta_chunk_vblank_c != dml_dlg_attr->refcyc_per_meta_chunk_vblank_c)
1490                 DC_LOG_DEBUG("DML Validation | VBLANK_PARAMETERS_4:REFCYC_PER_META_CHUNK_VBLANK_C - Expected: %u  Actual: %u\n",
1491                                 dml_dlg_attr->refcyc_per_meta_chunk_vblank_c, dlg_attr.refcyc_per_meta_chunk_vblank_c);
1492
1493         /* TTU - per hubp */
1494         REG_GET_2(DCN_TTU_QOS_WM,
1495                 QoS_LEVEL_LOW_WM, &ttu_attr.qos_level_low_wm,
1496                 QoS_LEVEL_HIGH_WM, &ttu_attr.qos_level_high_wm);
1497
1498         if (ttu_attr.qos_level_low_wm != dml_ttu_attr->qos_level_low_wm)
1499                 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_LOW_WM - Expected: %u  Actual: %u\n",
1500                                 dml_ttu_attr->qos_level_low_wm, ttu_attr.qos_level_low_wm);
1501         if (ttu_attr.qos_level_high_wm != dml_ttu_attr->qos_level_high_wm)
1502                 DC_LOG_DEBUG("DML Validation | DCN_TTU_QOS_WM:QoS_LEVEL_HIGH_WM - Expected: %u  Actual: %u\n",
1503                                 dml_ttu_attr->qos_level_high_wm, ttu_attr.qos_level_high_wm);
1504
1505         /* TTU - per luma/chroma */
1506         /* Assumed surf0 is luma and 1 is chroma */
1507         REG_GET_3(DCN_SURF0_TTU_CNTL0,
1508                 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_l,
1509                 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_l,
1510                 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_l);
1511         REG_GET_3(DCN_SURF1_TTU_CNTL0,
1512                 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_c,
1513                 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_c,
1514                 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_c);
1515         REG_GET_3(DCN_CUR0_TTU_CNTL0,
1516                 REFCYC_PER_REQ_DELIVERY, &ttu_attr.refcyc_per_req_delivery_cur0,
1517                 QoS_LEVEL_FIXED, &ttu_attr.qos_level_fixed_cur0,
1518                 QoS_RAMP_DISABLE, &ttu_attr.qos_ramp_disable_cur0);
1519         REG_GET(FLIP_PARAMETERS_1,
1520                 REFCYC_PER_PTE_GROUP_FLIP_L, &dlg_attr.refcyc_per_pte_group_flip_l);
1521         REG_GET(DCN_CUR0_TTU_CNTL1,
1522                         REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur0);
1523         REG_GET(DCN_CUR1_TTU_CNTL1,
1524                         REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_cur1);
1525         REG_GET(DCN_SURF0_TTU_CNTL1,
1526                         REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_l);
1527         REG_GET(DCN_SURF1_TTU_CNTL1,
1528                         REFCYC_PER_REQ_DELIVERY_PRE, &ttu_attr.refcyc_per_req_delivery_pre_c);
1529
1530         if (ttu_attr.refcyc_per_req_delivery_l != dml_ttu_attr->refcyc_per_req_delivery_l)
1531                 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u  Actual: %u\n",
1532                                 dml_ttu_attr->refcyc_per_req_delivery_l, ttu_attr.refcyc_per_req_delivery_l);
1533         if (ttu_attr.qos_level_fixed_l != dml_ttu_attr->qos_level_fixed_l)
1534                 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u  Actual: %u\n",
1535                                 dml_ttu_attr->qos_level_fixed_l, ttu_attr.qos_level_fixed_l);
1536         if (ttu_attr.qos_ramp_disable_l != dml_ttu_attr->qos_ramp_disable_l)
1537                 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u  Actual: %u\n",
1538                                 dml_ttu_attr->qos_ramp_disable_l, ttu_attr.qos_ramp_disable_l);
1539         if (ttu_attr.refcyc_per_req_delivery_c != dml_ttu_attr->refcyc_per_req_delivery_c)
1540                 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u  Actual: %u\n",
1541                                 dml_ttu_attr->refcyc_per_req_delivery_c, ttu_attr.refcyc_per_req_delivery_c);
1542         if (ttu_attr.qos_level_fixed_c != dml_ttu_attr->qos_level_fixed_c)
1543                 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u  Actual: %u\n",
1544                                 dml_ttu_attr->qos_level_fixed_c, ttu_attr.qos_level_fixed_c);
1545         if (ttu_attr.qos_ramp_disable_c != dml_ttu_attr->qos_ramp_disable_c)
1546                 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u  Actual: %u\n",
1547                                 dml_ttu_attr->qos_ramp_disable_c, ttu_attr.qos_ramp_disable_c);
1548         if (ttu_attr.refcyc_per_req_delivery_cur0 != dml_ttu_attr->refcyc_per_req_delivery_cur0)
1549                 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:REFCYC_PER_REQ_DELIVERY - Expected: %u  Actual: %u\n",
1550                                 dml_ttu_attr->refcyc_per_req_delivery_cur0, ttu_attr.refcyc_per_req_delivery_cur0);
1551         if (ttu_attr.qos_level_fixed_cur0 != dml_ttu_attr->qos_level_fixed_cur0)
1552                 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_LEVEL_FIXED - Expected: %u  Actual: %u\n",
1553                                 dml_ttu_attr->qos_level_fixed_cur0, ttu_attr.qos_level_fixed_cur0);
1554         if (ttu_attr.qos_ramp_disable_cur0 != dml_ttu_attr->qos_ramp_disable_cur0)
1555                 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL0:QoS_RAMP_DISABLE - Expected: %u  Actual: %u\n",
1556                                 dml_ttu_attr->qos_ramp_disable_cur0, ttu_attr.qos_ramp_disable_cur0);
1557         if (dlg_attr.refcyc_per_pte_group_flip_l != dml_dlg_attr->refcyc_per_pte_group_flip_l)
1558                 DC_LOG_DEBUG("DML Validation | FLIP_PARAMETERS_1:REFCYC_PER_PTE_GROUP_FLIP_L - Expected: %u  Actual: %u\n",
1559                                 dml_dlg_attr->refcyc_per_pte_group_flip_l, dlg_attr.refcyc_per_pte_group_flip_l);
1560         if (ttu_attr.refcyc_per_req_delivery_pre_cur0 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur0)
1561                 DC_LOG_DEBUG("DML Validation | DCN_CUR0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
1562                                 dml_ttu_attr->refcyc_per_req_delivery_pre_cur0, ttu_attr.refcyc_per_req_delivery_pre_cur0);
1563         if (ttu_attr.refcyc_per_req_delivery_pre_cur1 != dml_ttu_attr->refcyc_per_req_delivery_pre_cur1)
1564                 DC_LOG_DEBUG("DML Validation | DCN_CUR1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
1565                                 dml_ttu_attr->refcyc_per_req_delivery_pre_cur1, ttu_attr.refcyc_per_req_delivery_pre_cur1);
1566         if (ttu_attr.refcyc_per_req_delivery_pre_l != dml_ttu_attr->refcyc_per_req_delivery_pre_l)
1567                 DC_LOG_DEBUG("DML Validation | DCN_SURF0_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
1568                                 dml_ttu_attr->refcyc_per_req_delivery_pre_l, ttu_attr.refcyc_per_req_delivery_pre_l);
1569         if (ttu_attr.refcyc_per_req_delivery_pre_c != dml_ttu_attr->refcyc_per_req_delivery_pre_c)
1570                 DC_LOG_DEBUG("DML Validation | DCN_SURF1_TTU_CNTL1:REFCYC_PER_REQ_DELIVERY_PRE - Expected: %u  Actual: %u\n",
1571                                 dml_ttu_attr->refcyc_per_req_delivery_pre_c, ttu_attr.refcyc_per_req_delivery_pre_c);
1572 }
1573
1574 static struct hubp_funcs dcn20_hubp_funcs = {
1575         .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer,
1576         .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled,
1577         .hubp_program_surface_flip_and_addr = hubp2_program_surface_flip_and_addr,
1578         .hubp_program_surface_config = hubp2_program_surface_config,
1579         .hubp_is_flip_pending = hubp2_is_flip_pending,
1580         .hubp_setup = hubp2_setup,
1581         .hubp_setup_interdependent = hubp2_setup_interdependent,
1582         .hubp_set_vm_system_aperture_settings = hubp2_set_vm_system_aperture_settings,
1583         .set_blank = hubp2_set_blank,
1584         .dcc_control = hubp2_dcc_control,
1585         .mem_program_viewport = min_set_viewport,
1586         .set_cursor_attributes  = hubp2_cursor_set_attributes,
1587         .set_cursor_position    = hubp2_cursor_set_position,
1588         .hubp_clk_cntl = hubp2_clk_cntl,
1589         .hubp_vtg_sel = hubp2_vtg_sel,
1590         .dmdata_set_attributes = hubp2_dmdata_set_attributes,
1591         .dmdata_load = hubp2_dmdata_load,
1592         .dmdata_status_done = hubp2_dmdata_status_done,
1593         .hubp_read_state = hubp2_read_state,
1594         .hubp_clear_underflow = hubp2_clear_underflow,
1595         .hubp_set_flip_control_surface_gsl = hubp2_set_flip_control_surface_gsl,
1596         .hubp_init = hubp1_init,
1597         .validate_dml_output = hubp2_validate_dml_output,
1598 };
1599
1600
1601 bool hubp2_construct(
1602         struct dcn20_hubp *hubp2,
1603         struct dc_context *ctx,
1604         uint32_t inst,
1605         const struct dcn_hubp2_registers *hubp_regs,
1606         const struct dcn_hubp2_shift *hubp_shift,
1607         const struct dcn_hubp2_mask *hubp_mask)
1608 {
1609         hubp2->base.funcs = &dcn20_hubp_funcs;
1610         hubp2->base.ctx = ctx;
1611         hubp2->hubp_regs = hubp_regs;
1612         hubp2->hubp_shift = hubp_shift;
1613         hubp2->hubp_mask = hubp_mask;
1614         hubp2->base.inst = inst;
1615         hubp2->base.opp_id = OPP_ID_INVALID;
1616         hubp2->base.mpcc_id = 0xf;
1617
1618         return true;
1619 }