2 * Copyright 2012-16 Advanced Micro Devices, Inc.
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26 #include "reg_helper.h"
27 #include "clk_mgr_internal.h"
28 #include "rv1_clk_mgr_clk.h"
30 #include "ip/Discovery/hwid.h"
31 #include "ip/Discovery/v1/ip_offset_1.h"
32 #include "ip/CLK/clk_10_0_default.h"
33 #include "ip/CLK/clk_10_0_offset.h"
34 #include "ip/CLK/clk_10_0_reg.h"
35 #include "ip/CLK/clk_10_0_sh_mask.h"
37 #include "dce/dce_clk_mgr.h"
39 #define CLK_BASE_INNER(inst) \
40 CLK_BASE__INST ## inst ## _SEG0
43 #define CLK_REG(reg_name, block, inst)\
44 CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
45 mm ## block ## _ ## inst ## _ ## reg_name
47 #define REG(reg_name) \
48 CLK_REG(reg_name, CLK0, 0)
51 /* Only used by testing framework*/
52 void rv1_dump_clk_registers(struct clk_state_registers *regs, struct clk_bypass *bypass, struct clk_mgr *clk_mgr_base)
54 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
56 regs->CLK0_CLK8_CURRENT_CNT = REG_READ(CLK0_CLK8_CURRENT_CNT) / 10; //dcf clk
58 bypass->dcfclk_bypass = REG_READ(CLK0_CLK8_BYPASS_CNTL) & 0x0007;
59 if (bypass->dcfclk_bypass < 0 || bypass->dcfclk_bypass > 4)
60 bypass->dcfclk_bypass = 0;
63 regs->CLK0_CLK8_DS_CNTL = REG_READ(CLK0_CLK8_DS_CNTL) / 10; //dcf deep sleep divider
65 regs->CLK0_CLK8_ALLOW_DS = REG_READ(CLK0_CLK8_ALLOW_DS); //dcf deep sleep allow
67 regs->CLK0_CLK10_CURRENT_CNT = REG_READ(CLK0_CLK10_CURRENT_CNT) / 10; //dpref clk
69 bypass->dispclk_pypass = REG_READ(CLK0_CLK10_BYPASS_CNTL) & 0x0007;
70 if (bypass->dispclk_pypass < 0 || bypass->dispclk_pypass > 4)
71 bypass->dispclk_pypass = 0;
73 regs->CLK0_CLK11_CURRENT_CNT = REG_READ(CLK0_CLK11_CURRENT_CNT) / 10; //disp clk
75 bypass->dprefclk_bypass = REG_READ(CLK0_CLK11_BYPASS_CNTL) & 0x0007;
76 if (bypass->dprefclk_bypass < 0 || bypass->dprefclk_bypass > 4)
77 bypass->dprefclk_bypass = 0;