drivers/gpu/drm/amd/display/dc/dcn10/dcn10_opp.c

   1 /*
   2  * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "dcn10_opp.h"
  28 #include "reg_helper.h"
  29
  30 #define REG(reg) \
  31         (oppn10->regs->reg)
  32
  33 #undef FN
  34 #define FN(reg_name, field_name) \
  35         oppn10->opp_shift->field_name, oppn10->opp_mask->field_name
  36
  37 #define CTX \
  38         oppn10->base.ctx
  39
  40 static void oppn10_set_regamma_mode(
  41         struct output_pixel_processor *opp,
  42         enum opp_regamma mode)
  43 {
  44         struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
  45         uint32_t re_mode = 0;
  46         uint32_t obuf_bypass = 0; /* need for pipe split */
  47         uint32_t obuf_hupscale = 0;
  48
  49         switch (mode) {
  50         case OPP_REGAMMA_BYPASS:
  51                 re_mode = 0;
  52                 break;
  53         case OPP_REGAMMA_SRGB:
  54                 re_mode = 1;
  55                 break;
  56         case OPP_REGAMMA_3_6:
  57                 re_mode = 2;
  58                 break;
  59         case OPP_REGAMMA_USER:
  60                 re_mode = oppn10->is_write_to_ram_a_safe ? 3 : 4;
  61                 oppn10->is_write_to_ram_a_safe = !oppn10->is_write_to_ram_a_safe;
  62                 break;
  63         default:
  64                 break;
  65         }
  66
  67         REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode);
  68         REG_UPDATE_2(OBUF_CONTROL,
  69                         OBUF_BYPASS, obuf_bypass,
  70                         OBUF_H_2X_UPSCALE_EN, obuf_hupscale);
  71 }
  72
  73 /************* FORMATTER ************/
  74
  75 /**
  76  *      set_truncation
  77  *      1) set truncation depth: 0 for 18 bpp or 1 for 24 bpp
  78  *      2) enable truncation
  79  *      3) HW remove 12bit FMT support for DCE11 power saving reason.
  80  */
  81 static void set_truncation(
  82                 struct dcn10_opp *oppn10,
  83                 const struct bit_depth_reduction_params *params)
  84 {
  85         REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL,
  86                 FMT_TRUNCATE_EN, params->flags.TRUNCATE_ENABLED,
  87                 FMT_TRUNCATE_DEPTH, params->flags.TRUNCATE_DEPTH,
  88                 FMT_TRUNCATE_MODE, params->flags.TRUNCATE_MODE);
  89 }
  90
  91 static void set_spatial_dither(
  92         struct dcn10_opp *oppn10,
  93         const struct bit_depth_reduction_params *params)
  94 {
  95         /*Disable spatial (random) dithering*/
  96         REG_UPDATE_7(FMT_BIT_DEPTH_CONTROL,
  97                         FMT_SPATIAL_DITHER_EN, 0,
  98                         FMT_SPATIAL_DITHER_MODE, 0,
  99                         FMT_SPATIAL_DITHER_DEPTH, 0,
 100                         FMT_TEMPORAL_DITHER_EN, 0,
 101                         FMT_HIGHPASS_RANDOM_ENABLE, 0,
 102                         FMT_FRAME_RANDOM_ENABLE, 0,
 103                         FMT_RGB_RANDOM_ENABLE, 0);
 104
 105
 106         /* only use FRAME_COUNTER_MAX if frameRandom == 1*/
 107         if (params->flags.FRAME_RANDOM == 1) {
 108                 if (params->flags.SPATIAL_DITHER_DEPTH == 0 || params->flags.SPATIAL_DITHER_DEPTH == 1) {
 109                         REG_UPDATE_2(FMT_CONTROL,
 110                                         FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 15,
 111                                         FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 2);
 112                 } else if (params->flags.SPATIAL_DITHER_DEPTH == 2) {
 113                         REG_UPDATE_2(FMT_CONTROL,
 114                                         FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 3,
 115                                         FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 1);
 116                 } else {
 117                         return;
 118                 }
 119         } else {
 120                 REG_UPDATE_2(FMT_CONTROL,
 121                                 FMT_SPATIAL_DITHER_FRAME_COUNTER_MAX, 0,
 122                                 FMT_SPATIAL_DITHER_FRAME_COUNTER_BIT_SWAP, 0);
 123         }
 124
 125         /*Set seed for random values for
 126          * spatial dithering for R,G,B channels*/
 127
 128         REG_SET(FMT_DITHER_RAND_R_SEED, 0,
 129                         FMT_RAND_R_SEED, params->r_seed_value);
 130
 131         REG_SET(FMT_DITHER_RAND_G_SEED, 0,
 132                         FMT_RAND_G_SEED, params->g_seed_value);
 133
 134         REG_SET(FMT_DITHER_RAND_B_SEED, 0,
 135                         FMT_RAND_B_SEED, params->b_seed_value);
 136
 137         /* FMT_OFFSET_R_Cr  31:16 0x0 Setting the zero
 138          * offset for the R/Cr channel, lower 4LSB
 139          * is forced to zeros. Typically set to 0
 140          * RGB and 0x80000 YCbCr.
 141          */
 142         /* FMT_OFFSET_G_Y   31:16 0x0 Setting the zero
 143          * offset for the G/Y  channel, lower 4LSB is
 144          * forced to zeros. Typically set to 0 RGB
 145          * and 0x80000 YCbCr.
 146          */
 147         /* FMT_OFFSET_B_Cb  31:16 0x0 Setting the zero
 148          * offset for the B/Cb channel, lower 4LSB is
 149          * forced to zeros. Typically set to 0 RGB and
 150          * 0x80000 YCbCr.
 151          */
 152
 153         REG_UPDATE_6(FMT_BIT_DEPTH_CONTROL,
 154                         /*Enable spatial dithering*/
 155                         FMT_SPATIAL_DITHER_EN, params->flags.SPATIAL_DITHER_ENABLED,
 156                         /* Set spatial dithering mode
 157                          * (default is Seed patterrn AAAA...)
 158                          */
 159                         FMT_SPATIAL_DITHER_MODE, params->flags.SPATIAL_DITHER_MODE,
 160                         /*Set spatial dithering bit depth*/
 161                         FMT_SPATIAL_DITHER_DEPTH, params->flags.SPATIAL_DITHER_DEPTH,
 162                         /*Disable High pass filter*/
 163                         FMT_HIGHPASS_RANDOM_ENABLE, params->flags.HIGHPASS_RANDOM,
 164                         /*Reset only at startup*/
 165                         FMT_FRAME_RANDOM_ENABLE, params->flags.FRAME_RANDOM,
 166                         /*Set RGB data dithered with x^28+x^3+1*/
 167                         FMT_RGB_RANDOM_ENABLE, params->flags.RGB_RANDOM);
 168 }
 169
 170 static void oppn10_program_bit_depth_reduction(
 171         struct output_pixel_processor *opp,
 172         const struct bit_depth_reduction_params *params)
 173 {
 174         struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
 175
 176         set_truncation(oppn10, params);
 177         set_spatial_dither(oppn10, params);
 178         /* TODO
 179          * set_temporal_dither(oppn10, params);
 180          */
 181 }
 182
 183 /**
 184  *      set_pixel_encoding
 185  *
 186  *      Set Pixel Encoding
 187  *              0: RGB 4:4:4 or YCbCr 4:4:4 or YOnly
 188  *              1: YCbCr 4:2:2
 189  */
 190 static void set_pixel_encoding(
 191         struct dcn10_opp *oppn10,
 192         const struct clamping_and_pixel_encoding_params *params)
 193 {
 194         switch (params->pixel_encoding) {
 195
 196         case PIXEL_ENCODING_RGB:
 197         case PIXEL_ENCODING_YCBCR444:
 198                 REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 0);
 199                 break;
 200         case PIXEL_ENCODING_YCBCR422:
 201                 REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 1);
 202                 break;
 203         case PIXEL_ENCODING_YCBCR420:
 204                 REG_UPDATE(FMT_CONTROL, FMT_PIXEL_ENCODING, 2);
 205                 break;
 206         default:
 207                 break;
 208         }
 209 }
 210
 211 /**
 212  *      Set Clamping
 213  *      1) Set clamping format based on bpc - 0 for 6bpc (No clamping)
 214  *              1 for 8 bpc
 215  *              2 for 10 bpc
 216  *              3 for 12 bpc
 217  *              7 for programable
 218  *      2) Enable clamp if Limited range requested
 219  */
 220 static void opp_set_clamping(
 221         struct dcn10_opp *oppn10,
 222         const struct clamping_and_pixel_encoding_params *params)
 223 {
 224         REG_UPDATE_2(FMT_CLAMP_CNTL,
 225                         FMT_CLAMP_DATA_EN, 0,
 226                         FMT_CLAMP_COLOR_FORMAT, 0);
 227
 228         switch (params->clamping_level) {
 229         case CLAMPING_FULL_RANGE:
 230                 REG_UPDATE_2(FMT_CLAMP_CNTL,
 231                                 FMT_CLAMP_DATA_EN, 1,
 232                                 FMT_CLAMP_COLOR_FORMAT, 0);
 233                 break;
 234         case CLAMPING_LIMITED_RANGE_8BPC:
 235                 REG_UPDATE_2(FMT_CLAMP_CNTL,
 236                                 FMT_CLAMP_DATA_EN, 1,
 237                                 FMT_CLAMP_COLOR_FORMAT, 1);
 238                 break;
 239         case CLAMPING_LIMITED_RANGE_10BPC:
 240                 REG_UPDATE_2(FMT_CLAMP_CNTL,
 241                                 FMT_CLAMP_DATA_EN, 1,
 242                                 FMT_CLAMP_COLOR_FORMAT, 2);
 243
 244                 break;
 245         case CLAMPING_LIMITED_RANGE_12BPC:
 246                 REG_UPDATE_2(FMT_CLAMP_CNTL,
 247                                 FMT_CLAMP_DATA_EN, 1,
 248                                 FMT_CLAMP_COLOR_FORMAT, 3);
 249                 break;
 250         case CLAMPING_LIMITED_RANGE_PROGRAMMABLE:
 251                 /* TODO */
 252         default:
 253                 break;
 254         }
 255
 256 }
 257
 258 static void oppn10_set_dyn_expansion(
 259         struct output_pixel_processor *opp,
 260         enum dc_color_space color_sp,
 261         enum dc_color_depth color_dpth,
 262         enum signal_type signal)
 263 {
 264         struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
 265
 266         REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
 267                         FMT_DYNAMIC_EXP_EN, 0,
 268                         FMT_DYNAMIC_EXP_MODE, 0);
 269
 270         /*00 - 10-bit -> 12-bit dynamic expansion*/
 271         /*01 - 8-bit  -> 12-bit dynamic expansion*/
 272         if (signal == SIGNAL_TYPE_HDMI_TYPE_A ||
 273                 signal == SIGNAL_TYPE_DISPLAY_PORT ||
 274                 signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
 275                 switch (color_dpth) {
 276                 case COLOR_DEPTH_888:
 277                         REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
 278                                 FMT_DYNAMIC_EXP_EN, 1,
 279                                 FMT_DYNAMIC_EXP_MODE, 1);
 280                         break;
 281                 case COLOR_DEPTH_101010:
 282                         REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
 283                                 FMT_DYNAMIC_EXP_EN, 1,
 284                                 FMT_DYNAMIC_EXP_MODE, 0);
 285                         break;
 286                 case COLOR_DEPTH_121212:
 287                         REG_UPDATE_2(FMT_DYNAMIC_EXP_CNTL,
 288                                 FMT_DYNAMIC_EXP_EN, 1,/*otherwise last two bits are zero*/
 289                                 FMT_DYNAMIC_EXP_MODE, 0);
 290                         break;
 291                 default:
 292                         break;
 293                 }
 294         }
 295 }
 296
 297 static void opp_program_clamping_and_pixel_encoding(
 298         struct output_pixel_processor *opp,
 299         const struct clamping_and_pixel_encoding_params *params)
 300 {
 301         struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
 302
 303         opp_set_clamping(oppn10, params);
 304         set_pixel_encoding(oppn10, params);
 305 }
 306
 307 static void oppn10_program_fmt(
 308         struct output_pixel_processor *opp,
 309         struct bit_depth_reduction_params *fmt_bit_depth,
 310         struct clamping_and_pixel_encoding_params *clamping)
 311 {
 312         struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
 313
 314         if (clamping->pixel_encoding == PIXEL_ENCODING_YCBCR420)
 315                 REG_UPDATE(FMT_MAP420_MEMORY_CONTROL, FMT_MAP420MEM_PWR_FORCE, 0);
 316
 317         /* dithering is affected by <CrtcSourceSelect>, hence should be
 318          * programmed afterwards */
 319         oppn10_program_bit_depth_reduction(
 320                 opp,
 321                 fmt_bit_depth);
 322
 323         opp_program_clamping_and_pixel_encoding(
 324                 opp,
 325                 clamping);
 326
 327         return;
 328 }
 329
 330 static void oppn10_set_output_csc_default(
 331                 struct output_pixel_processor *opp,
 332                 const struct default_adjustment *default_adjust)
 333 {
 334
 335         struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
 336         uint32_t ocsc_mode = 0;
 337
 338         if (default_adjust != NULL) {
 339                 switch (default_adjust->out_color_space) {
 340                 case COLOR_SPACE_SRGB:
 341                 case COLOR_SPACE_2020_RGB_FULLRANGE:
 342                         ocsc_mode = 0;
 343                         break;
 344                 case COLOR_SPACE_SRGB_LIMITED:
 345                 case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
 346                         ocsc_mode = 1;
 347                         break;
 348                 case COLOR_SPACE_YCBCR601:
 349                 case COLOR_SPACE_YCBCR601_LIMITED:
 350                         ocsc_mode = 2;
 351                         break;
 352                 case COLOR_SPACE_YCBCR709:
 353                 case COLOR_SPACE_YCBCR709_LIMITED:
 354                 case COLOR_SPACE_2020_YCBCR:
 355                         ocsc_mode = 3;
 356                         break;
 357                 case COLOR_SPACE_UNKNOWN:
 358                 default:
 359                         break;
 360                 }
 361         }
 362
 363         REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
 364
 365 }
 366 /*program re gamma RAM B*/
 367 static void opp_program_regamma_lutb_settings(
 368                 struct output_pixel_processor *opp,
 369                 const struct pwl_params *params)
 370 {
 371         const struct gamma_curve *curve;
 372         struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
 373
 374         REG_SET_2(CM_RGAM_RAMB_START_CNTL_B, 0,
 375                 CM_RGAM_RAMB_EXP_REGION_START_B, params->arr_points[0].custom_float_x,
 376                 CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_B, 0);
 377         REG_SET_2(CM_RGAM_RAMB_START_CNTL_G, 0,
 378                 CM_RGAM_RAMB_EXP_REGION_START_G, params->arr_points[0].custom_float_x,
 379                 CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_G, 0);
 380         REG_SET_2(CM_RGAM_RAMB_START_CNTL_R, 0,
 381                 CM_RGAM_RAMB_EXP_REGION_START_R, params->arr_points[0].custom_float_x,
 382                 CM_RGAM_RAMB_EXP_REGION_START_SEGMENT_R, 0);
 383
 384         REG_SET(CM_RGAM_RAMB_SLOPE_CNTL_B, 0,
 385                 CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_B, params->arr_points[0].custom_float_slope);
 386         REG_SET(CM_RGAM_RAMB_SLOPE_CNTL_G, 0,
 387                 CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_G, params->arr_points[0].custom_float_slope);
 388         REG_SET(CM_RGAM_RAMB_SLOPE_CNTL_R, 0,
 389                 CM_RGAM_RAMB_EXP_REGION_LINEAR_SLOPE_R, params->arr_points[0].custom_float_slope);
 390
 391         REG_SET(CM_RGAM_RAMB_END_CNTL1_B, 0,
 392                 CM_RGAM_RAMB_EXP_REGION_END_B, params->arr_points[1].custom_float_x);
 393         REG_SET_2(CM_RGAM_RAMB_END_CNTL2_B, 0,
 394                 CM_RGAM_RAMB_EXP_REGION_END_SLOPE_B, params->arr_points[1].custom_float_slope,
 395                 CM_RGAM_RAMB_EXP_REGION_END_BASE_B, params->arr_points[1].custom_float_y);
 396
 397         REG_SET(CM_RGAM_RAMB_END_CNTL1_G, 0,
 398                 CM_RGAM_RAMB_EXP_REGION_END_G, params->arr_points[1].custom_float_x);
 399         REG_SET_2(CM_RGAM_RAMB_END_CNTL2_G, 0,
 400                 CM_RGAM_RAMB_EXP_REGION_END_SLOPE_G, params->arr_points[1].custom_float_slope,
 401                 CM_RGAM_RAMB_EXP_REGION_END_BASE_G, params->arr_points[1].custom_float_y);
 402
 403         REG_SET(CM_RGAM_RAMB_END_CNTL1_R, 0,
 404                 CM_RGAM_RAMB_EXP_REGION_END_R, params->arr_points[1].custom_float_x);
 405         REG_SET_2(CM_RGAM_RAMB_END_CNTL2_R, 0,
 406                 CM_RGAM_RAMB_EXP_REGION_END_SLOPE_R, params->arr_points[1].custom_float_slope,
 407                 CM_RGAM_RAMB_EXP_REGION_END_BASE_R, params->arr_points[1].custom_float_y);
 408
 409         curve = params->arr_curve_points;
 410         REG_SET_4(CM_RGAM_RAMB_REGION_0_1, 0,
 411                 CM_RGAM_RAMB_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 412                 CM_RGAM_RAMB_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 413                 CM_RGAM_RAMB_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 414                 CM_RGAM_RAMB_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 415
 416         curve += 2;
 417         REG_SET_4(CM_RGAM_RAMB_REGION_2_3, 0,
 418                 CM_RGAM_RAMB_EXP_REGION2_LUT_OFFSET, curve[0].offset,
 419                 CM_RGAM_RAMB_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
 420                 CM_RGAM_RAMB_EXP_REGION3_LUT_OFFSET, curve[1].offset,
 421                 CM_RGAM_RAMB_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
 422
 423         curve += 2;
 424         REG_SET_4(CM_RGAM_RAMB_REGION_4_5, 0,
 425                 CM_RGAM_RAMB_EXP_REGION4_LUT_OFFSET, curve[0].offset,
 426                 CM_RGAM_RAMB_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
 427                 CM_RGAM_RAMB_EXP_REGION5_LUT_OFFSET, curve[1].offset,
 428                 CM_RGAM_RAMB_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
 429
 430         curve += 2;
 431         REG_SET_4(CM_RGAM_RAMB_REGION_6_7, 0,
 432                 CM_RGAM_RAMB_EXP_REGION6_LUT_OFFSET, curve[0].offset,
 433                 CM_RGAM_RAMB_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
 434                 CM_RGAM_RAMB_EXP_REGION7_LUT_OFFSET, curve[1].offset,
 435                 CM_RGAM_RAMB_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
 436
 437         curve += 2;
 438         REG_SET_4(CM_RGAM_RAMB_REGION_8_9, 0,
 439                 CM_RGAM_RAMB_EXP_REGION8_LUT_OFFSET, curve[0].offset,
 440                 CM_RGAM_RAMB_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
 441                 CM_RGAM_RAMB_EXP_REGION9_LUT_OFFSET, curve[1].offset,
 442                 CM_RGAM_RAMB_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
 443
 444         curve += 2;
 445         REG_SET_4(CM_RGAM_RAMB_REGION_10_11, 0,
 446                 CM_RGAM_RAMB_EXP_REGION10_LUT_OFFSET, curve[0].offset,
 447                 CM_RGAM_RAMB_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
 448                 CM_RGAM_RAMB_EXP_REGION11_LUT_OFFSET, curve[1].offset,
 449                 CM_RGAM_RAMB_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
 450
 451         curve += 2;
 452         REG_SET_4(CM_RGAM_RAMB_REGION_12_13, 0,
 453                 CM_RGAM_RAMB_EXP_REGION12_LUT_OFFSET, curve[0].offset,
 454                 CM_RGAM_RAMB_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
 455                 CM_RGAM_RAMB_EXP_REGION13_LUT_OFFSET, curve[1].offset,
 456                 CM_RGAM_RAMB_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
 457
 458         curve += 2;
 459         REG_SET_4(CM_RGAM_RAMB_REGION_14_15, 0,
 460                 CM_RGAM_RAMB_EXP_REGION14_LUT_OFFSET, curve[0].offset,
 461                 CM_RGAM_RAMB_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
 462                 CM_RGAM_RAMB_EXP_REGION15_LUT_OFFSET, curve[1].offset,
 463                 CM_RGAM_RAMB_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
 464
 465         curve += 2;
 466         REG_SET_4(CM_RGAM_RAMB_REGION_16_17, 0,
 467                 CM_RGAM_RAMB_EXP_REGION16_LUT_OFFSET, curve[0].offset,
 468                 CM_RGAM_RAMB_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
 469                 CM_RGAM_RAMB_EXP_REGION17_LUT_OFFSET, curve[1].offset,
 470                 CM_RGAM_RAMB_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
 471
 472         curve += 2;
 473         REG_SET_4(CM_RGAM_RAMB_REGION_18_19, 0,
 474                 CM_RGAM_RAMB_EXP_REGION18_LUT_OFFSET, curve[0].offset,
 475                 CM_RGAM_RAMB_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
 476                 CM_RGAM_RAMB_EXP_REGION19_LUT_OFFSET, curve[1].offset,
 477                 CM_RGAM_RAMB_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
 478
 479         curve += 2;
 480         REG_SET_4(CM_RGAM_RAMB_REGION_20_21, 0,
 481                 CM_RGAM_RAMB_EXP_REGION20_LUT_OFFSET, curve[0].offset,
 482                 CM_RGAM_RAMB_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
 483                 CM_RGAM_RAMB_EXP_REGION21_LUT_OFFSET, curve[1].offset,
 484                 CM_RGAM_RAMB_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
 485
 486         curve += 2;
 487         REG_SET_4(CM_RGAM_RAMB_REGION_22_23, 0,
 488                 CM_RGAM_RAMB_EXP_REGION22_LUT_OFFSET, curve[0].offset,
 489                 CM_RGAM_RAMB_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
 490                 CM_RGAM_RAMB_EXP_REGION23_LUT_OFFSET, curve[1].offset,
 491                 CM_RGAM_RAMB_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
 492
 493         curve += 2;
 494         REG_SET_4(CM_RGAM_RAMB_REGION_24_25, 0,
 495                 CM_RGAM_RAMB_EXP_REGION24_LUT_OFFSET, curve[0].offset,
 496                 CM_RGAM_RAMB_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
 497                 CM_RGAM_RAMB_EXP_REGION25_LUT_OFFSET, curve[1].offset,
 498                 CM_RGAM_RAMB_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
 499
 500         curve += 2;
 501         REG_SET_4(CM_RGAM_RAMB_REGION_26_27, 0,
 502                 CM_RGAM_RAMB_EXP_REGION26_LUT_OFFSET, curve[0].offset,
 503                 CM_RGAM_RAMB_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
 504                 CM_RGAM_RAMB_EXP_REGION27_LUT_OFFSET, curve[1].offset,
 505                 CM_RGAM_RAMB_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
 506
 507         curve += 2;
 508         REG_SET_4(CM_RGAM_RAMB_REGION_28_29, 0,
 509                 CM_RGAM_RAMB_EXP_REGION28_LUT_OFFSET, curve[0].offset,
 510                 CM_RGAM_RAMB_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
 511                 CM_RGAM_RAMB_EXP_REGION29_LUT_OFFSET, curve[1].offset,
 512                 CM_RGAM_RAMB_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
 513
 514         curve += 2;
 515         REG_SET_4(CM_RGAM_RAMB_REGION_30_31, 0,
 516                 CM_RGAM_RAMB_EXP_REGION30_LUT_OFFSET, curve[0].offset,
 517                 CM_RGAM_RAMB_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
 518                 CM_RGAM_RAMB_EXP_REGION31_LUT_OFFSET, curve[1].offset,
 519                 CM_RGAM_RAMB_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
 520
 521         curve += 2;
 522         REG_SET_4(CM_RGAM_RAMB_REGION_32_33, 0,
 523                 CM_RGAM_RAMB_EXP_REGION32_LUT_OFFSET, curve[0].offset,
 524                 CM_RGAM_RAMB_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
 525                 CM_RGAM_RAMB_EXP_REGION33_LUT_OFFSET, curve[1].offset,
 526                 CM_RGAM_RAMB_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
 527
 528 }
 529
 530 /*program re gamma RAM A*/
 531 static void opp_program_regamma_luta_settings(
 532                 struct output_pixel_processor *opp,
 533                 const struct pwl_params *params)
 534 {
 535         const struct gamma_curve *curve;
 536         struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
 537
 538         REG_SET_2(CM_RGAM_RAMA_START_CNTL_B, 0,
 539                 CM_RGAM_RAMA_EXP_REGION_START_B, params->arr_points[0].custom_float_x,
 540                 CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_B, 0);
 541         REG_SET_2(CM_RGAM_RAMA_START_CNTL_G, 0,
 542                 CM_RGAM_RAMA_EXP_REGION_START_G, params->arr_points[0].custom_float_x,
 543                 CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_G, 0);
 544         REG_SET_2(CM_RGAM_RAMA_START_CNTL_R, 0,
 545                 CM_RGAM_RAMA_EXP_REGION_START_R, params->arr_points[0].custom_float_x,
 546                 CM_RGAM_RAMA_EXP_REGION_START_SEGMENT_R, 0);
 547
 548         REG_SET(CM_RGAM_RAMA_SLOPE_CNTL_B, 0,
 549                 CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_B, params->arr_points[0].custom_float_slope);
 550         REG_SET(CM_RGAM_RAMA_SLOPE_CNTL_G, 0,
 551                 CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_G, params->arr_points[0].custom_float_slope);
 552         REG_SET(CM_RGAM_RAMA_SLOPE_CNTL_R, 0,
 553                 CM_RGAM_RAMA_EXP_REGION_LINEAR_SLOPE_R, params->arr_points[0].custom_float_slope);
 554
 555         REG_SET(CM_RGAM_RAMA_END_CNTL1_B, 0,
 556                 CM_RGAM_RAMA_EXP_REGION_END_B, params->arr_points[1].custom_float_x);
 557         REG_SET_2(CM_RGAM_RAMA_END_CNTL2_B, 0,
 558                 CM_RGAM_RAMA_EXP_REGION_END_SLOPE_B, params->arr_points[1].custom_float_slope,
 559                 CM_RGAM_RAMA_EXP_REGION_END_BASE_B, params->arr_points[1].custom_float_y);
 560
 561         REG_SET(CM_RGAM_RAMA_END_CNTL1_G, 0,
 562                 CM_RGAM_RAMA_EXP_REGION_END_G, params->arr_points[1].custom_float_x);
 563         REG_SET_2(CM_RGAM_RAMA_END_CNTL2_G, 0,
 564                 CM_RGAM_RAMA_EXP_REGION_END_SLOPE_G, params->arr_points[1].custom_float_slope,
 565                 CM_RGAM_RAMA_EXP_REGION_END_BASE_G, params->arr_points[1].custom_float_y);
 566
 567         REG_SET(CM_RGAM_RAMA_END_CNTL1_R, 0,
 568                 CM_RGAM_RAMA_EXP_REGION_END_R, params->arr_points[1].custom_float_x);
 569         REG_SET_2(CM_RGAM_RAMA_END_CNTL2_R, 0,
 570                 CM_RGAM_RAMA_EXP_REGION_END_SLOPE_R, params->arr_points[1].custom_float_slope,
 571                 CM_RGAM_RAMA_EXP_REGION_END_BASE_R, params->arr_points[1].custom_float_y);
 572
 573         curve = params->arr_curve_points;
 574         REG_SET_4(CM_RGAM_RAMA_REGION_0_1, 0,
 575                 CM_RGAM_RAMA_EXP_REGION0_LUT_OFFSET, curve[0].offset,
 576                 CM_RGAM_RAMA_EXP_REGION0_NUM_SEGMENTS, curve[0].segments_num,
 577                 CM_RGAM_RAMA_EXP_REGION1_LUT_OFFSET, curve[1].offset,
 578                 CM_RGAM_RAMA_EXP_REGION1_NUM_SEGMENTS, curve[1].segments_num);
 579
 580         curve += 2;
 581         REG_SET_4(CM_RGAM_RAMA_REGION_2_3, 0,
 582                 CM_RGAM_RAMA_EXP_REGION2_LUT_OFFSET, curve[0].offset,
 583                 CM_RGAM_RAMA_EXP_REGION2_NUM_SEGMENTS, curve[0].segments_num,
 584                 CM_RGAM_RAMA_EXP_REGION3_LUT_OFFSET, curve[1].offset,
 585                 CM_RGAM_RAMA_EXP_REGION3_NUM_SEGMENTS, curve[1].segments_num);
 586
 587         curve += 2;
 588         REG_SET_4(CM_RGAM_RAMA_REGION_4_5, 0,
 589                 CM_RGAM_RAMA_EXP_REGION4_LUT_OFFSET, curve[0].offset,
 590                 CM_RGAM_RAMA_EXP_REGION4_NUM_SEGMENTS, curve[0].segments_num,
 591                 CM_RGAM_RAMA_EXP_REGION5_LUT_OFFSET, curve[1].offset,
 592                 CM_RGAM_RAMA_EXP_REGION5_NUM_SEGMENTS, curve[1].segments_num);
 593
 594         curve += 2;
 595         REG_SET_4(CM_RGAM_RAMA_REGION_6_7, 0,
 596                 CM_RGAM_RAMA_EXP_REGION6_LUT_OFFSET, curve[0].offset,
 597                 CM_RGAM_RAMA_EXP_REGION6_NUM_SEGMENTS, curve[0].segments_num,
 598                 CM_RGAM_RAMA_EXP_REGION7_LUT_OFFSET, curve[1].offset,
 599                 CM_RGAM_RAMA_EXP_REGION7_NUM_SEGMENTS, curve[1].segments_num);
 600
 601         curve += 2;
 602         REG_SET_4(CM_RGAM_RAMA_REGION_8_9, 0,
 603                 CM_RGAM_RAMA_EXP_REGION8_LUT_OFFSET, curve[0].offset,
 604                 CM_RGAM_RAMA_EXP_REGION8_NUM_SEGMENTS, curve[0].segments_num,
 605                 CM_RGAM_RAMA_EXP_REGION9_LUT_OFFSET, curve[1].offset,
 606                 CM_RGAM_RAMA_EXP_REGION9_NUM_SEGMENTS, curve[1].segments_num);
 607
 608         curve += 2;
 609         REG_SET_4(CM_RGAM_RAMA_REGION_10_11, 0,
 610                 CM_RGAM_RAMA_EXP_REGION10_LUT_OFFSET, curve[0].offset,
 611                 CM_RGAM_RAMA_EXP_REGION10_NUM_SEGMENTS, curve[0].segments_num,
 612                 CM_RGAM_RAMA_EXP_REGION11_LUT_OFFSET, curve[1].offset,
 613                 CM_RGAM_RAMA_EXP_REGION11_NUM_SEGMENTS, curve[1].segments_num);
 614
 615         curve += 2;
 616         REG_SET_4(CM_RGAM_RAMA_REGION_12_13, 0,
 617                 CM_RGAM_RAMA_EXP_REGION12_LUT_OFFSET, curve[0].offset,
 618                 CM_RGAM_RAMA_EXP_REGION12_NUM_SEGMENTS, curve[0].segments_num,
 619                 CM_RGAM_RAMA_EXP_REGION13_LUT_OFFSET, curve[1].offset,
 620                 CM_RGAM_RAMA_EXP_REGION13_NUM_SEGMENTS, curve[1].segments_num);
 621
 622         curve += 2;
 623         REG_SET_4(CM_RGAM_RAMA_REGION_14_15, 0,
 624                 CM_RGAM_RAMA_EXP_REGION14_LUT_OFFSET, curve[0].offset,
 625                 CM_RGAM_RAMA_EXP_REGION14_NUM_SEGMENTS, curve[0].segments_num,
 626                 CM_RGAM_RAMA_EXP_REGION15_LUT_OFFSET, curve[1].offset,
 627                 CM_RGAM_RAMA_EXP_REGION15_NUM_SEGMENTS, curve[1].segments_num);
 628
 629         curve += 2;
 630         REG_SET_4(CM_RGAM_RAMA_REGION_16_17, 0,
 631                 CM_RGAM_RAMA_EXP_REGION16_LUT_OFFSET, curve[0].offset,
 632                 CM_RGAM_RAMA_EXP_REGION16_NUM_SEGMENTS, curve[0].segments_num,
 633                 CM_RGAM_RAMA_EXP_REGION17_LUT_OFFSET, curve[1].offset,
 634                 CM_RGAM_RAMA_EXP_REGION17_NUM_SEGMENTS, curve[1].segments_num);
 635
 636         curve += 2;
 637         REG_SET_4(CM_RGAM_RAMA_REGION_18_19, 0,
 638                 CM_RGAM_RAMA_EXP_REGION18_LUT_OFFSET, curve[0].offset,
 639                 CM_RGAM_RAMA_EXP_REGION18_NUM_SEGMENTS, curve[0].segments_num,
 640                 CM_RGAM_RAMA_EXP_REGION19_LUT_OFFSET, curve[1].offset,
 641                 CM_RGAM_RAMA_EXP_REGION19_NUM_SEGMENTS, curve[1].segments_num);
 642
 643         curve += 2;
 644         REG_SET_4(CM_RGAM_RAMA_REGION_20_21, 0,
 645                 CM_RGAM_RAMA_EXP_REGION20_LUT_OFFSET, curve[0].offset,
 646                 CM_RGAM_RAMA_EXP_REGION20_NUM_SEGMENTS, curve[0].segments_num,
 647                 CM_RGAM_RAMA_EXP_REGION21_LUT_OFFSET, curve[1].offset,
 648                 CM_RGAM_RAMA_EXP_REGION21_NUM_SEGMENTS, curve[1].segments_num);
 649
 650         curve += 2;
 651         REG_SET_4(CM_RGAM_RAMA_REGION_22_23, 0,
 652                 CM_RGAM_RAMA_EXP_REGION22_LUT_OFFSET, curve[0].offset,
 653                 CM_RGAM_RAMA_EXP_REGION22_NUM_SEGMENTS, curve[0].segments_num,
 654                 CM_RGAM_RAMA_EXP_REGION23_LUT_OFFSET, curve[1].offset,
 655                 CM_RGAM_RAMA_EXP_REGION23_NUM_SEGMENTS, curve[1].segments_num);
 656
 657         curve += 2;
 658         REG_SET_4(CM_RGAM_RAMA_REGION_24_25, 0,
 659                 CM_RGAM_RAMA_EXP_REGION24_LUT_OFFSET, curve[0].offset,
 660                 CM_RGAM_RAMA_EXP_REGION24_NUM_SEGMENTS, curve[0].segments_num,
 661                 CM_RGAM_RAMA_EXP_REGION25_LUT_OFFSET, curve[1].offset,
 662                 CM_RGAM_RAMA_EXP_REGION25_NUM_SEGMENTS, curve[1].segments_num);
 663
 664         curve += 2;
 665         REG_SET_4(CM_RGAM_RAMA_REGION_26_27, 0,
 666                 CM_RGAM_RAMA_EXP_REGION26_LUT_OFFSET, curve[0].offset,
 667                 CM_RGAM_RAMA_EXP_REGION26_NUM_SEGMENTS, curve[0].segments_num,
 668                 CM_RGAM_RAMA_EXP_REGION27_LUT_OFFSET, curve[1].offset,
 669                 CM_RGAM_RAMA_EXP_REGION27_NUM_SEGMENTS, curve[1].segments_num);
 670
 671         curve += 2;
 672         REG_SET_4(CM_RGAM_RAMA_REGION_28_29, 0,
 673                 CM_RGAM_RAMA_EXP_REGION28_LUT_OFFSET, curve[0].offset,
 674                 CM_RGAM_RAMA_EXP_REGION28_NUM_SEGMENTS, curve[0].segments_num,
 675                 CM_RGAM_RAMA_EXP_REGION29_LUT_OFFSET, curve[1].offset,
 676                 CM_RGAM_RAMA_EXP_REGION29_NUM_SEGMENTS, curve[1].segments_num);
 677
 678         curve += 2;
 679         REG_SET_4(CM_RGAM_RAMA_REGION_30_31, 0,
 680                 CM_RGAM_RAMA_EXP_REGION30_LUT_OFFSET, curve[0].offset,
 681                 CM_RGAM_RAMA_EXP_REGION30_NUM_SEGMENTS, curve[0].segments_num,
 682                 CM_RGAM_RAMA_EXP_REGION31_LUT_OFFSET, curve[1].offset,
 683                 CM_RGAM_RAMA_EXP_REGION31_NUM_SEGMENTS, curve[1].segments_num);
 684
 685         curve += 2;
 686         REG_SET_4(CM_RGAM_RAMA_REGION_32_33, 0,
 687                 CM_RGAM_RAMA_EXP_REGION32_LUT_OFFSET, curve[0].offset,
 688                 CM_RGAM_RAMA_EXP_REGION32_NUM_SEGMENTS, curve[0].segments_num,
 689                 CM_RGAM_RAMA_EXP_REGION33_LUT_OFFSET, curve[1].offset,
 690                 CM_RGAM_RAMA_EXP_REGION33_NUM_SEGMENTS, curve[1].segments_num);
 691 }
 692
 693 static void opp_configure_regamma_lut(
 694                 struct output_pixel_processor *opp,
 695                 bool is_ram_a)
 696 {
 697         struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
 698
 699         REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK,
 700                         CM_RGAM_LUT_WRITE_EN_MASK, 7);
 701         REG_UPDATE(CM_RGAM_LUT_WRITE_EN_MASK,
 702                         CM_RGAM_LUT_WRITE_SEL, is_ram_a == true ? 0:1);
 703         REG_SET(CM_RGAM_LUT_INDEX, 0, CM_RGAM_LUT_INDEX, 0);
 704 }
 705
 706 static void oppn10_power_on_regamma_lut(
 707         struct output_pixel_processor *opp,
 708         bool power_on)
 709 {
 710         struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
 711         REG_SET(CM_MEM_PWR_CTRL, 0,
 712                         RGAM_MEM_PWR_FORCE, power_on == true ? 0:1);
 713
 714 }
 715
 716
 717 static void oppn10_program_color_matrix(struct dcn10_opp *oppn10,
 718                 const struct out_csc_color_matrix *tbl_entry)
 719 {
 720         uint32_t mode;
 721
 722         REG_GET(CM_OCSC_CONTROL, CM_OCSC_MODE, &mode);
 723
 724         if (tbl_entry == NULL) {
 725                 BREAK_TO_DEBUGGER();
 726                 return;
 727         }
 728
 729
 730         if (mode == 4) {
 731                 /*R*/
 732                 REG_SET_2(CM_OCSC_C11_C12, 0,
 733                         CM_OCSC_C11, tbl_entry->regval[0],
 734                         CM_OCSC_C12, tbl_entry->regval[1]);
 735
 736                 REG_SET_2(CM_OCSC_C13_C14, 0,
 737                         CM_OCSC_C13, tbl_entry->regval[2],
 738                         CM_OCSC_C14, tbl_entry->regval[3]);
 739
 740                 /*G*/
 741                 REG_SET_2(CM_OCSC_C21_C22, 0,
 742                         CM_OCSC_C21, tbl_entry->regval[4],
 743                         CM_OCSC_C22, tbl_entry->regval[5]);
 744
 745                 REG_SET_2(CM_OCSC_C23_C24, 0,
 746                         CM_OCSC_C23, tbl_entry->regval[6],
 747                         CM_OCSC_C24, tbl_entry->regval[7]);
 748
 749                 /*B*/
 750                 REG_SET_2(CM_OCSC_C31_C32, 0,
 751                         CM_OCSC_C31, tbl_entry->regval[8],
 752                         CM_OCSC_C32, tbl_entry->regval[9]);
 753
 754                 REG_SET_2(CM_OCSC_C33_C34, 0,
 755                         CM_OCSC_C33, tbl_entry->regval[10],
 756                         CM_OCSC_C34, tbl_entry->regval[11]);
 757         } else {
 758                 /*R*/
 759                 REG_SET_2(CM_COMB_C11_C12, 0,
 760                         CM_COMB_C11, tbl_entry->regval[0],
 761                         CM_COMB_C12, tbl_entry->regval[1]);
 762
 763                 REG_SET_2(CM_COMB_C13_C14, 0,
 764                         CM_COMB_C13, tbl_entry->regval[2],
 765                         CM_COMB_C14, tbl_entry->regval[3]);
 766
 767                 /*G*/
 768                 REG_SET_2(CM_COMB_C21_C22, 0,
 769                         CM_COMB_C21, tbl_entry->regval[4],
 770                         CM_COMB_C22, tbl_entry->regval[5]);
 771
 772                 REG_SET_2(CM_COMB_C23_C24, 0,
 773                         CM_COMB_C23, tbl_entry->regval[6],
 774                         CM_COMB_C24, tbl_entry->regval[7]);
 775
 776                 /*B*/
 777                 REG_SET_2(CM_COMB_C31_C32, 0,
 778                         CM_COMB_C31, tbl_entry->regval[8],
 779                         CM_COMB_C32, tbl_entry->regval[9]);
 780
 781                 REG_SET_2(CM_COMB_C33_C34, 0,
 782                         CM_COMB_C33, tbl_entry->regval[10],
 783                         CM_COMB_C34, tbl_entry->regval[11]);
 784         }
 785 }
 786
 787 static void oppn10_set_output_csc_adjustment(
 788                 struct output_pixel_processor *opp,
 789                 const struct out_csc_color_matrix *tbl_entry)
 790 {
 791
 792         struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
 793         //enum csc_color_mode config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
 794
 795
 796         uint32_t ocsc_mode = 4;
 797
 798         /**
 799         *if (tbl_entry != NULL) {
 800         *       switch (tbl_entry->color_space) {
 801         *       case COLOR_SPACE_SRGB:
 802         *       case COLOR_SPACE_2020_RGB_FULLRANGE:
 803         *               ocsc_mode = 0;
 804         *               break;
 805         *       case COLOR_SPACE_SRGB_LIMITED:
 806         *       case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
 807         *               ocsc_mode = 1;
 808         *               break;
 809         *       case COLOR_SPACE_YCBCR601:
 810         *       case COLOR_SPACE_YCBCR601_LIMITED:
 811         *               ocsc_mode = 2;
 812         *               break;
 813         *       case COLOR_SPACE_YCBCR709:
 814         *       case COLOR_SPACE_YCBCR709_LIMITED:
 815         *       case COLOR_SPACE_2020_YCBCR:
 816         *               ocsc_mode = 3;
 817         *               break;
 818         *       case COLOR_SPACE_UNKNOWN:
 819         *       default:
 820         *               break;
 821         *       }
 822         *}
 823         */
 824
 825         REG_SET(CM_OCSC_CONTROL, 0, CM_OCSC_MODE, ocsc_mode);
 826         oppn10_program_color_matrix(oppn10, tbl_entry);
 827 }
 828
 829 static void opp_program_regamma_lut(
 830                 struct output_pixel_processor *opp,
 831                 const struct pwl_result_data *rgb,
 832                 uint32_t num)
 833 {
 834         uint32_t i;
 835         struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
 836         for (i = 0 ; i < num; i++) {
 837                 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].red_reg);
 838                 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].green_reg);
 839                 REG_SET(CM_RGAM_LUT_DATA, 0, CM_RGAM_LUT_DATA, rgb[i].blue_reg);
 840
 841                 REG_SET(CM_RGAM_LUT_DATA, 0,
 842                                 CM_RGAM_LUT_DATA, rgb[i].delta_red_reg);
 843                 REG_SET(CM_RGAM_LUT_DATA, 0,
 844                                 CM_RGAM_LUT_DATA, rgb[i].delta_green_reg);
 845                 REG_SET(CM_RGAM_LUT_DATA, 0,
 846                                 CM_RGAM_LUT_DATA, rgb[i].delta_blue_reg);
 847
 848         }
 849
 850 }
 851
 852 static bool oppn10_set_regamma_pwl(
 853         struct output_pixel_processor *opp, const struct pwl_params *params)
 854 {
 855         struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
 856
 857         oppn10_power_on_regamma_lut(opp, true);
 858         opp_configure_regamma_lut(opp, oppn10->is_write_to_ram_a_safe);
 859
 860         if (oppn10->is_write_to_ram_a_safe)
 861                 opp_program_regamma_luta_settings(opp, params);
 862         else
 863                 opp_program_regamma_lutb_settings(opp, params);
 864
 865         opp_program_regamma_lut(
 866                 opp, params->rgb_resulted, params->hw_points_num);
 867
 868         return true;
 869 }
 870
 871 static void oppn10_set_stereo_polarity(
 872                 struct output_pixel_processor *opp,
 873                 bool enable, bool rightEyePolarity)
 874 {
 875         struct dcn10_opp *oppn10 = TO_DCN10_OPP(opp);
 876
 877         REG_UPDATE(FMT_CONTROL, FMT_STEREOSYNC_OVERRIDE, enable);
 878 }
 879
 880 /*****************************************/
 881 /* Constructor, Destructor               */
 882 /*****************************************/
 883
 884 static void dcn10_opp_destroy(struct output_pixel_processor **opp)
 885 {
 886         dm_free(TO_DCN10_OPP(*opp));
 887         *opp = NULL;
 888 }
 889
 890 static struct opp_funcs dcn10_opp_funcs = {
 891                 .opp_power_on_regamma_lut = oppn10_power_on_regamma_lut,
 892                 .opp_set_csc_adjustment = oppn10_set_output_csc_adjustment,
 893                 .opp_set_csc_default = oppn10_set_output_csc_default,
 894                 .opp_set_dyn_expansion = oppn10_set_dyn_expansion,
 895                 .opp_program_regamma_pwl = oppn10_set_regamma_pwl,
 896                 .opp_set_regamma_mode = oppn10_set_regamma_mode,
 897                 .opp_program_fmt = oppn10_program_fmt,
 898                 .opp_program_bit_depth_reduction = oppn10_program_bit_depth_reduction,
 899                 .opp_set_stereo_polarity = oppn10_set_stereo_polarity,
 900                 .opp_destroy = dcn10_opp_destroy
 901 };
 902
 903 void dcn10_opp_construct(struct dcn10_opp *oppn10,
 904         struct dc_context *ctx,
 905         uint32_t inst,
 906         const struct dcn10_opp_registers *regs,
 907         const struct dcn10_opp_shift *opp_shift,
 908         const struct dcn10_opp_mask *opp_mask)
 909 {
 910         int i;
 911         oppn10->base.ctx = ctx;
 912         oppn10->base.inst = inst;
 913         oppn10->base.funcs = &dcn10_opp_funcs;
 914
 915         for (i = 0; i < MAX_PIPES; i++)
 916                 oppn10->base.mpcc_disconnect_pending[i] = false;
 917
 918         oppn10->regs = regs;
 919         oppn10->opp_shift = opp_shift;
 920         oppn10->opp_mask = opp_mask;
 921 }
 922