drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27 #include "core_types.h"
  28 #include "resource.h"
  29 #include "custom_float.h"
  30 #include "dcn10_hw_sequencer.h"
  31 #include "dce110/dce110_hw_sequencer.h"
  32 #include "dce/dce_hwseq.h"
  33 #include "abm.h"
  34 #include "dmcu.h"
  35 #include "dcn10_optc.h"
  36 #include "dcn10/dcn10_dpp.h"
  37 #include "dcn10/dcn10_mpc.h"
  38 #include "timing_generator.h"
  39 #include "opp.h"
  40 #include "ipp.h"
  41 #include "mpc.h"
  42 #include "reg_helper.h"
  43 #include "dcn10_hubp.h"
  44 #include "dcn10_hubbub.h"
  45 #include "dcn10_cm_common.h"
  46 #include "dc_link_dp.h"
  47 #include "dccg.h"
  48
  49 #define DC_LOGGER_INIT(logger)
  50
  51 #define CTX \
  52         hws->ctx
  53 #define REG(reg)\
  54         hws->regs->reg
  55
  56 #undef FN
  57 #define FN(reg_name, field_name) \
  58         hws->shifts->field_name, hws->masks->field_name
  59
  60 /*print is 17 wide, first two characters are spaces*/
  61 #define DTN_INFO_MICRO_SEC(ref_cycle) \
  62         print_microsec(dc_ctx, log_ctx, ref_cycle)
  63
  64 void print_microsec(struct dc_context *dc_ctx,
  65         struct dc_log_buffer_ctx *log_ctx,
  66         uint32_t ref_cycle)
  67 {
  68         const uint32_t ref_clk_mhz = dc_ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000;
  69         static const unsigned int frac = 1000;
  70         uint32_t us_x10 = (ref_cycle * frac) / ref_clk_mhz;
  71
  72         DTN_INFO("  %11d.%03d",
  73                         us_x10 / frac,
  74                         us_x10 % frac);
  75 }
  76
  77 static void log_mpc_crc(struct dc *dc,
  78         struct dc_log_buffer_ctx *log_ctx)
  79 {
  80         struct dc_context *dc_ctx = dc->ctx;
  81         struct dce_hwseq *hws = dc->hwseq;
  82
  83         if (REG(MPC_CRC_RESULT_GB))
  84                 DTN_INFO("MPC_CRC_RESULT_GB:%d MPC_CRC_RESULT_C:%d MPC_CRC_RESULT_AR:%d\n",
  85                 REG_READ(MPC_CRC_RESULT_GB), REG_READ(MPC_CRC_RESULT_C), REG_READ(MPC_CRC_RESULT_AR));
  86         if (REG(DPP_TOP0_DPP_CRC_VAL_B_A))
  87                 DTN_INFO("DPP_TOP0_DPP_CRC_VAL_B_A:%d DPP_TOP0_DPP_CRC_VAL_R_G:%d\n",
  88                 REG_READ(DPP_TOP0_DPP_CRC_VAL_B_A), REG_READ(DPP_TOP0_DPP_CRC_VAL_R_G));
  89 }
  90
  91 void dcn10_log_hubbub_state(struct dc *dc, struct dc_log_buffer_ctx *log_ctx)
  92 {
  93         struct dc_context *dc_ctx = dc->ctx;
  94         struct dcn_hubbub_wm wm;
  95         int i;
  96
  97         memset(&wm, 0, sizeof(struct dcn_hubbub_wm));
  98         dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm);
  99
 100         DTN_INFO("HUBBUB WM:      data_urgent  pte_meta_urgent"
 101                         "         sr_enter          sr_exit  dram_clk_change\n");
 102
 103         for (i = 0; i < 4; i++) {
 104                 struct dcn_hubbub_wm_set *s;
 105
 106                 s = &wm.sets[i];
 107                 DTN_INFO("WM_Set[%d]:", s->wm_set);
 108                 DTN_INFO_MICRO_SEC(s->data_urgent);
 109                 DTN_INFO_MICRO_SEC(s->pte_meta_urgent);
 110                 DTN_INFO_MICRO_SEC(s->sr_enter);
 111                 DTN_INFO_MICRO_SEC(s->sr_exit);
 112                 DTN_INFO_MICRO_SEC(s->dram_clk_chanage);
 113                 DTN_INFO("\n");
 114         }
 115
 116         DTN_INFO("\n");
 117 }
 118
 119 static void dcn10_log_hubp_states(struct dc *dc, void *log_ctx)
 120 {
 121         struct dc_context *dc_ctx = dc->ctx;
 122         struct resource_pool *pool = dc->res_pool;
 123         int i;
 124
 125         DTN_INFO("HUBP:  format  addr_hi  width  height"
 126                         "  rot  mir  sw_mode  dcc_en  blank_en  ttu_dis  underflow"
 127                         "   min_ttu_vblank       qos_low_wm      qos_high_wm\n");
 128         for (i = 0; i < pool->pipe_count; i++) {
 129                 struct hubp *hubp = pool->hubps[i];
 130                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(hubp)->state);
 131
 132                 hubp->funcs->hubp_read_state(hubp);
 133
 134                 if (!s->blank_en) {
 135                         DTN_INFO("[%2d]:  %5xh  %6xh  %5d  %6d  %2xh  %2xh  %6xh"
 136                                         "  %6d  %8d  %7d  %8xh",
 137                                         hubp->inst,
 138                                         s->pixel_format,
 139                                         s->inuse_addr_hi,
 140                                         s->viewport_width,
 141                                         s->viewport_height,
 142                                         s->rotation_angle,
 143                                         s->h_mirror_en,
 144                                         s->sw_mode,
 145                                         s->dcc_en,
 146                                         s->blank_en,
 147                                         s->ttu_disable,
 148                                         s->underflow_status);
 149                         DTN_INFO_MICRO_SEC(s->min_ttu_vblank);
 150                         DTN_INFO_MICRO_SEC(s->qos_level_low_wm);
 151                         DTN_INFO_MICRO_SEC(s->qos_level_high_wm);
 152                         DTN_INFO("\n");
 153                 }
 154         }
 155
 156         DTN_INFO("\n=========RQ========\n");
 157         DTN_INFO("HUBP:  drq_exp_m  prq_exp_m  mrq_exp_m  crq_exp_m  plane1_ba  L:chunk_s  min_chu_s  meta_ch_s"
 158                 "  min_m_c_s  dpte_gr_s  mpte_gr_s  swath_hei  pte_row_h  C:chunk_s  min_chu_s  meta_ch_s"
 159                 "  min_m_c_s  dpte_gr_s  mpte_gr_s  swath_hei  pte_row_h\n");
 160         for (i = 0; i < pool->pipe_count; i++) {
 161                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
 162                 struct _vcs_dpi_display_rq_regs_st *rq_regs = &s->rq_regs;
 163
 164                 if (!s->blank_en)
 165                         DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
 166                                 pool->hubps[i]->inst, rq_regs->drq_expansion_mode, rq_regs->prq_expansion_mode, rq_regs->mrq_expansion_mode,
 167                                 rq_regs->crq_expansion_mode, rq_regs->plane1_base_address, rq_regs->rq_regs_l.chunk_size,
 168                                 rq_regs->rq_regs_l.min_chunk_size, rq_regs->rq_regs_l.meta_chunk_size,
 169                                 rq_regs->rq_regs_l.min_meta_chunk_size, rq_regs->rq_regs_l.dpte_group_size,
 170                                 rq_regs->rq_regs_l.mpte_group_size, rq_regs->rq_regs_l.swath_height,
 171                                 rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
 172                                 rq_regs->rq_regs_c.meta_chunk_size, rq_regs->rq_regs_c.min_meta_chunk_size,
 173                                 rq_regs->rq_regs_c.dpte_group_size, rq_regs->rq_regs_c.mpte_group_size,
 174                                 rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear);
 175         }
 176
 177         DTN_INFO("========DLG========\n");
 178         DTN_INFO("HUBP:  rc_hbe     dlg_vbe    min_d_y_n  rc_per_ht  rc_x_a_s "
 179                         "  dst_y_a_s  dst_y_pf   dst_y_vvb  dst_y_rvb  dst_y_vfl  dst_y_rfl  rf_pix_fq"
 180                         "  vratio_pf  vrat_pf_c  rc_pg_vbl  rc_pg_vbc  rc_mc_vbl  rc_mc_vbc  rc_pg_fll"
 181                         "  rc_pg_flc  rc_mc_fll  rc_mc_flc  pr_nom_l   pr_nom_c   rc_pg_nl   rc_pg_nc "
 182                         "  mr_nom_l   mr_nom_c   rc_mc_nl   rc_mc_nc   rc_ld_pl   rc_ld_pc   rc_ld_l  "
 183                         "  rc_ld_c    cha_cur0   ofst_cur1  cha_cur1   vr_af_vc0  ddrq_limt  x_rt_dlay"
 184                         "  x_rp_dlay  x_rr_sfl\n");
 185         for (i = 0; i < pool->pipe_count; i++) {
 186                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
 187                 struct _vcs_dpi_display_dlg_regs_st *dlg_regs = &s->dlg_attr;
 188
 189                 if (!s->blank_en)
 190                         DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh"
 191                                 "%  8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh"
 192                                 "  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
 193                                 pool->hubps[i]->inst, dlg_regs->refcyc_h_blank_end, dlg_regs->dlg_vblank_end, dlg_regs->min_dst_y_next_start,
 194                                 dlg_regs->refcyc_per_htotal, dlg_regs->refcyc_x_after_scaler, dlg_regs->dst_y_after_scaler,
 195                                 dlg_regs->dst_y_prefetch, dlg_regs->dst_y_per_vm_vblank, dlg_regs->dst_y_per_row_vblank,
 196                                 dlg_regs->dst_y_per_vm_flip, dlg_regs->dst_y_per_row_flip, dlg_regs->ref_freq_to_pix_freq,
 197                                 dlg_regs->vratio_prefetch, dlg_regs->vratio_prefetch_c, dlg_regs->refcyc_per_pte_group_vblank_l,
 198                                 dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l,
 199                                 dlg_regs->refcyc_per_meta_chunk_vblank_c, dlg_regs->refcyc_per_pte_group_flip_l,
 200                                 dlg_regs->refcyc_per_pte_group_flip_c, dlg_regs->refcyc_per_meta_chunk_flip_l,
 201                                 dlg_regs->refcyc_per_meta_chunk_flip_c, dlg_regs->dst_y_per_pte_row_nom_l,
 202                                 dlg_regs->dst_y_per_pte_row_nom_c, dlg_regs->refcyc_per_pte_group_nom_l,
 203                                 dlg_regs->refcyc_per_pte_group_nom_c, dlg_regs->dst_y_per_meta_row_nom_l,
 204                                 dlg_regs->dst_y_per_meta_row_nom_c, dlg_regs->refcyc_per_meta_chunk_nom_l,
 205                                 dlg_regs->refcyc_per_meta_chunk_nom_c, dlg_regs->refcyc_per_line_delivery_pre_l,
 206                                 dlg_regs->refcyc_per_line_delivery_pre_c, dlg_regs->refcyc_per_line_delivery_l,
 207                                 dlg_regs->refcyc_per_line_delivery_c, dlg_regs->chunk_hdl_adjust_cur0, dlg_regs->dst_y_offset_cur1,
 208                                 dlg_regs->chunk_hdl_adjust_cur1, dlg_regs->vready_after_vcount0, dlg_regs->dst_y_delta_drq_limit,
 209                                 dlg_regs->xfc_reg_transfer_delay, dlg_regs->xfc_reg_precharge_delay,
 210                                 dlg_regs->xfc_reg_remote_surface_flip_latency);
 211         }
 212
 213         DTN_INFO("========TTU========\n");
 214         DTN_INFO("HUBP:  qos_ll_wm  qos_lh_wm  mn_ttu_vb  qos_l_flp  rc_rd_p_l  rc_rd_l    rc_rd_p_c"
 215                         "  rc_rd_c    rc_rd_c0   rc_rd_pc0  rc_rd_c1   rc_rd_pc1  qos_lf_l   qos_rds_l"
 216                         "  qos_lf_c   qos_rds_c  qos_lf_c0  qos_rds_c0 qos_lf_c1  qos_rds_c1\n");
 217         for (i = 0; i < pool->pipe_count; i++) {
 218                 struct dcn_hubp_state *s = &(TO_DCN10_HUBP(pool->hubps[i])->state);
 219                 struct _vcs_dpi_display_ttu_regs_st *ttu_regs = &s->ttu_attr;
 220
 221                 if (!s->blank_en)
 222                         DTN_INFO("[%2d]:  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh  %8xh\n",
 223                                 pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
 224                                 ttu_regs->qos_level_flip, ttu_regs->refcyc_per_req_delivery_pre_l, ttu_regs->refcyc_per_req_delivery_l,
 225                                 ttu_regs->refcyc_per_req_delivery_pre_c, ttu_regs->refcyc_per_req_delivery_c, ttu_regs->refcyc_per_req_delivery_cur0,
 226                                 ttu_regs->refcyc_per_req_delivery_pre_cur0, ttu_regs->refcyc_per_req_delivery_cur1,
 227                                 ttu_regs->refcyc_per_req_delivery_pre_cur1, ttu_regs->qos_level_fixed_l, ttu_regs->qos_ramp_disable_l,
 228                                 ttu_regs->qos_level_fixed_c, ttu_regs->qos_ramp_disable_c, ttu_regs->qos_level_fixed_cur0,
 229                                 ttu_regs->qos_ramp_disable_cur0, ttu_regs->qos_level_fixed_cur1, ttu_regs->qos_ramp_disable_cur1);
 230         }
 231         DTN_INFO("\n");
 232 }
 233
 234 void dcn10_log_hw_state(struct dc *dc,
 235         struct dc_log_buffer_ctx *log_ctx)
 236 {
 237         struct dc_context *dc_ctx = dc->ctx;
 238         struct resource_pool *pool = dc->res_pool;
 239         int i;
 240
 241         DTN_INFO_BEGIN();
 242
 243         dcn10_log_hubbub_state(dc, log_ctx);
 244
 245         dcn10_log_hubp_states(dc, log_ctx);
 246
 247         DTN_INFO("DPP:    IGAM format  IGAM mode    DGAM mode    RGAM mode"
 248                         "  GAMUT mode  C11 C12   C13 C14   C21 C22   C23 C24   "
 249                         "C31 C32   C33 C34\n");
 250         for (i = 0; i < pool->pipe_count; i++) {
 251                 struct dpp *dpp = pool->dpps[i];
 252                 struct dcn_dpp_state s = {0};
 253
 254                 dpp->funcs->dpp_read_state(dpp, &s);
 255
 256                 if (!s.is_enabled)
 257                         continue;
 258
 259                 DTN_INFO("[%2d]:  %11xh  %-11s  %-11s  %-11s"
 260                                 "%8x    %08xh %08xh %08xh %08xh %08xh %08xh",
 261                                 dpp->inst,
 262                                 s.igam_input_format,
 263                                 (s.igam_lut_mode == 0) ? "BypassFixed" :
 264                                         ((s.igam_lut_mode == 1) ? "BypassFloat" :
 265                                         ((s.igam_lut_mode == 2) ? "RAM" :
 266                                         ((s.igam_lut_mode == 3) ? "RAM" :
 267                                                                  "Unknown"))),
 268                                 (s.dgam_lut_mode == 0) ? "Bypass" :
 269                                         ((s.dgam_lut_mode == 1) ? "sRGB" :
 270                                         ((s.dgam_lut_mode == 2) ? "Ycc" :
 271                                         ((s.dgam_lut_mode == 3) ? "RAM" :
 272                                         ((s.dgam_lut_mode == 4) ? "RAM" :
 273                                                                  "Unknown")))),
 274                                 (s.rgam_lut_mode == 0) ? "Bypass" :
 275                                         ((s.rgam_lut_mode == 1) ? "sRGB" :
 276                                         ((s.rgam_lut_mode == 2) ? "Ycc" :
 277                                         ((s.rgam_lut_mode == 3) ? "RAM" :
 278                                         ((s.rgam_lut_mode == 4) ? "RAM" :
 279                                                                  "Unknown")))),
 280                                 s.gamut_remap_mode,
 281                                 s.gamut_remap_c11_c12,
 282                                 s.gamut_remap_c13_c14,
 283                                 s.gamut_remap_c21_c22,
 284                                 s.gamut_remap_c23_c24,
 285                                 s.gamut_remap_c31_c32,
 286                                 s.gamut_remap_c33_c34);
 287                 DTN_INFO("\n");
 288         }
 289         DTN_INFO("\n");
 290
 291         DTN_INFO("MPCC:  OPP  DPP  MPCCBOT  MODE  ALPHA_MODE  PREMULT  OVERLAP_ONLY  IDLE\n");
 292         for (i = 0; i < pool->pipe_count; i++) {
 293                 struct mpcc_state s = {0};
 294
 295                 pool->mpc->funcs->read_mpcc_state(pool->mpc, i, &s);
 296                 if (s.opp_id != 0xf)
 297                         DTN_INFO("[%2d]:  %2xh  %2xh  %6xh  %4d  %10d  %7d  %12d  %4d\n",
 298                                 i, s.opp_id, s.dpp_id, s.bot_mpcc_id,
 299                                 s.mode, s.alpha_mode, s.pre_multiplied_alpha, s.overlap_only,
 300                                 s.idle);
 301         }
 302         DTN_INFO("\n");
 303
 304         DTN_INFO("OTG:  v_bs  v_be  v_ss  v_se  vpol  vmax  vmin  vmax_sel  vmin_sel"
 305                         "  h_bs  h_be  h_ss  h_se  hpol  htot  vtot  underflow\n");
 306
 307         for (i = 0; i < pool->timing_generator_count; i++) {
 308                 struct timing_generator *tg = pool->timing_generators[i];
 309                 struct dcn_otg_state s = {0};
 310
 311                 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
 312
 313                 //only print if OTG master is enabled
 314                 if ((s.otg_enabled & 1) == 0)
 315                         continue;
 316
 317                 DTN_INFO("[%d]: %5d %5d %5d %5d %5d %5d %5d %9d %9d %5d %5d %5d"
 318                                 " %5d %5d %5d %5d  %9d\n",
 319                                 tg->inst,
 320                                 s.v_blank_start,
 321                                 s.v_blank_end,
 322                                 s.v_sync_a_start,
 323                                 s.v_sync_a_end,
 324                                 s.v_sync_a_pol,
 325                                 s.v_total_max,
 326                                 s.v_total_min,
 327                                 s.v_total_max_sel,
 328                                 s.v_total_min_sel,
 329                                 s.h_blank_start,
 330                                 s.h_blank_end,
 331                                 s.h_sync_a_start,
 332                                 s.h_sync_a_end,
 333                                 s.h_sync_a_pol,
 334                                 s.h_total,
 335                                 s.v_total,
 336                                 s.underflow_occurred_status);
 337
 338                 // Clear underflow for debug purposes
 339                 // We want to keep underflow sticky bit on for the longevity tests outside of test environment.
 340                 // This function is called only from Windows or Diags test environment, hence it's safe to clear
 341                 // it from here without affecting the original intent.
 342                 tg->funcs->clear_optc_underflow(tg);
 343         }
 344         DTN_INFO("\n");
 345
 346         DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d  dcfclk_deep_sleep_khz:%d  dispclk_khz:%d\n"
 347                 "dppclk_khz:%d  max_supported_dppclk_khz:%d  fclk_khz:%d  socclk_khz:%d\n\n",
 348                         dc->current_state->bw.dcn.clk.dcfclk_khz,
 349                         dc->current_state->bw.dcn.clk.dcfclk_deep_sleep_khz,
 350                         dc->current_state->bw.dcn.clk.dispclk_khz,
 351                         dc->current_state->bw.dcn.clk.dppclk_khz,
 352                         dc->current_state->bw.dcn.clk.max_supported_dppclk_khz,
 353                         dc->current_state->bw.dcn.clk.fclk_khz,
 354                         dc->current_state->bw.dcn.clk.socclk_khz);
 355
 356         log_mpc_crc(dc, log_ctx);
 357
 358         DTN_INFO_END();
 359 }
 360
 361 static void enable_power_gating_plane(
 362         struct dce_hwseq *hws,
 363         bool enable)
 364 {
 365         bool force_on = 1; /* disable power gating */
 366
 367         if (enable)
 368                 force_on = 0;
 369
 370         /* DCHUBP0/1/2/3 */
 371         REG_UPDATE(DOMAIN0_PG_CONFIG, DOMAIN0_POWER_FORCEON, force_on);
 372         REG_UPDATE(DOMAIN2_PG_CONFIG, DOMAIN2_POWER_FORCEON, force_on);
 373         REG_UPDATE(DOMAIN4_PG_CONFIG, DOMAIN4_POWER_FORCEON, force_on);
 374         REG_UPDATE(DOMAIN6_PG_CONFIG, DOMAIN6_POWER_FORCEON, force_on);
 375
 376         /* DPP0/1/2/3 */
 377         REG_UPDATE(DOMAIN1_PG_CONFIG, DOMAIN1_POWER_FORCEON, force_on);
 378         REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN3_POWER_FORCEON, force_on);
 379         REG_UPDATE(DOMAIN5_PG_CONFIG, DOMAIN5_POWER_FORCEON, force_on);
 380         REG_UPDATE(DOMAIN7_PG_CONFIG, DOMAIN7_POWER_FORCEON, force_on);
 381 }
 382
 383 static void disable_vga(
 384         struct dce_hwseq *hws)
 385 {
 386         unsigned int in_vga1_mode = 0;
 387         unsigned int in_vga2_mode = 0;
 388         unsigned int in_vga3_mode = 0;
 389         unsigned int in_vga4_mode = 0;
 390
 391         REG_GET(D1VGA_CONTROL, D1VGA_MODE_ENABLE, &in_vga1_mode);
 392         REG_GET(D2VGA_CONTROL, D2VGA_MODE_ENABLE, &in_vga2_mode);
 393         REG_GET(D3VGA_CONTROL, D3VGA_MODE_ENABLE, &in_vga3_mode);
 394         REG_GET(D4VGA_CONTROL, D4VGA_MODE_ENABLE, &in_vga4_mode);
 395
 396         if (in_vga1_mode == 0 && in_vga2_mode == 0 &&
 397                         in_vga3_mode == 0 && in_vga4_mode == 0)
 398                 return;
 399
 400         REG_WRITE(D1VGA_CONTROL, 0);
 401         REG_WRITE(D2VGA_CONTROL, 0);
 402         REG_WRITE(D3VGA_CONTROL, 0);
 403         REG_WRITE(D4VGA_CONTROL, 0);
 404
 405         /* HW Engineer's Notes:
 406          *  During switch from vga->extended, if we set the VGA_TEST_ENABLE and
 407          *  then hit the VGA_TEST_RENDER_START, then the DCHUBP timing gets updated correctly.
 408          *
 409          *  Then vBIOS will have it poll for the VGA_TEST_RENDER_DONE and unset
 410          *  VGA_TEST_ENABLE, to leave it in the same state as before.
 411          */
 412         REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_ENABLE, 1);
 413         REG_UPDATE(VGA_TEST_CONTROL, VGA_TEST_RENDER_START, 1);
 414 }
 415
 416 static void dpp_pg_control(
 417                 struct dce_hwseq *hws,
 418                 unsigned int dpp_inst,
 419                 bool power_on)
 420 {
 421         uint32_t power_gate = power_on ? 0 : 1;
 422         uint32_t pwr_status = power_on ? 0 : 2;
 423
 424         if (hws->ctx->dc->debug.disable_dpp_power_gate)
 425                 return;
 426         if (REG(DOMAIN1_PG_CONFIG) == 0)
 427                 return;
 428
 429         switch (dpp_inst) {
 430         case 0: /* DPP0 */
 431                 REG_UPDATE(DOMAIN1_PG_CONFIG,
 432                                 DOMAIN1_POWER_GATE, power_gate);
 433
 434                 REG_WAIT(DOMAIN1_PG_STATUS,
 435                                 DOMAIN1_PGFSM_PWR_STATUS, pwr_status,
 436                                 1, 1000);
 437                 break;
 438         case 1: /* DPP1 */
 439                 REG_UPDATE(DOMAIN3_PG_CONFIG,
 440                                 DOMAIN3_POWER_GATE, power_gate);
 441
 442                 REG_WAIT(DOMAIN3_PG_STATUS,
 443                                 DOMAIN3_PGFSM_PWR_STATUS, pwr_status,
 444                                 1, 1000);
 445                 break;
 446         case 2: /* DPP2 */
 447                 REG_UPDATE(DOMAIN5_PG_CONFIG,
 448                                 DOMAIN5_POWER_GATE, power_gate);
 449
 450                 REG_WAIT(DOMAIN5_PG_STATUS,
 451                                 DOMAIN5_PGFSM_PWR_STATUS, pwr_status,
 452                                 1, 1000);
 453                 break;
 454         case 3: /* DPP3 */
 455                 REG_UPDATE(DOMAIN7_PG_CONFIG,
 456                                 DOMAIN7_POWER_GATE, power_gate);
 457
 458                 REG_WAIT(DOMAIN7_PG_STATUS,
 459                                 DOMAIN7_PGFSM_PWR_STATUS, pwr_status,
 460                                 1, 1000);
 461                 break;
 462         default:
 463                 BREAK_TO_DEBUGGER();
 464                 break;
 465         }
 466 }
 467
 468 static void hubp_pg_control(
 469                 struct dce_hwseq *hws,
 470                 unsigned int hubp_inst,
 471                 bool power_on)
 472 {
 473         uint32_t power_gate = power_on ? 0 : 1;
 474         uint32_t pwr_status = power_on ? 0 : 2;
 475
 476         if (hws->ctx->dc->debug.disable_hubp_power_gate)
 477                 return;
 478         if (REG(DOMAIN0_PG_CONFIG) == 0)
 479                 return;
 480
 481         switch (hubp_inst) {
 482         case 0: /* DCHUBP0 */
 483                 REG_UPDATE(DOMAIN0_PG_CONFIG,
 484                                 DOMAIN0_POWER_GATE, power_gate);
 485
 486                 REG_WAIT(DOMAIN0_PG_STATUS,
 487                                 DOMAIN0_PGFSM_PWR_STATUS, pwr_status,
 488                                 1, 1000);
 489                 break;
 490         case 1: /* DCHUBP1 */
 491                 REG_UPDATE(DOMAIN2_PG_CONFIG,
 492                                 DOMAIN2_POWER_GATE, power_gate);
 493
 494                 REG_WAIT(DOMAIN2_PG_STATUS,
 495                                 DOMAIN2_PGFSM_PWR_STATUS, pwr_status,
 496                                 1, 1000);
 497                 break;
 498         case 2: /* DCHUBP2 */
 499                 REG_UPDATE(DOMAIN4_PG_CONFIG,
 500                                 DOMAIN4_POWER_GATE, power_gate);
 501
 502                 REG_WAIT(DOMAIN4_PG_STATUS,
 503                                 DOMAIN4_PGFSM_PWR_STATUS, pwr_status,
 504                                 1, 1000);
 505                 break;
 506         case 3: /* DCHUBP3 */
 507                 REG_UPDATE(DOMAIN6_PG_CONFIG,
 508                                 DOMAIN6_POWER_GATE, power_gate);
 509
 510                 REG_WAIT(DOMAIN6_PG_STATUS,
 511                                 DOMAIN6_PGFSM_PWR_STATUS, pwr_status,
 512                                 1, 1000);
 513                 break;
 514         default:
 515                 BREAK_TO_DEBUGGER();
 516                 break;
 517         }
 518 }
 519
 520 static void power_on_plane(
 521         struct dce_hwseq *hws,
 522         int plane_id)
 523 {
 524         DC_LOGGER_INIT(hws->ctx->logger);
 525         if (REG(DC_IP_REQUEST_CNTL)) {
 526                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 527                                 IP_REQUEST_EN, 1);
 528                 dpp_pg_control(hws, plane_id, true);
 529                 hubp_pg_control(hws, plane_id, true);
 530                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 531                                 IP_REQUEST_EN, 0);
 532                 DC_LOG_DEBUG(
 533                                 "Un-gated front end for pipe %d\n", plane_id);
 534         }
 535 }
 536
 537 static void undo_DEGVIDCN10_253_wa(struct dc *dc)
 538 {
 539         struct dce_hwseq *hws = dc->hwseq;
 540         struct hubp *hubp = dc->res_pool->hubps[0];
 541
 542         if (!hws->wa_state.DEGVIDCN10_253_applied)
 543                 return;
 544
 545         hubp->funcs->set_blank(hubp, true);
 546
 547         REG_SET(DC_IP_REQUEST_CNTL, 0,
 548                         IP_REQUEST_EN, 1);
 549
 550         hubp_pg_control(hws, 0, false);
 551         REG_SET(DC_IP_REQUEST_CNTL, 0,
 552                         IP_REQUEST_EN, 0);
 553
 554         hws->wa_state.DEGVIDCN10_253_applied = false;
 555 }
 556
 557 static void apply_DEGVIDCN10_253_wa(struct dc *dc)
 558 {
 559         struct dce_hwseq *hws = dc->hwseq;
 560         struct hubp *hubp = dc->res_pool->hubps[0];
 561         int i;
 562
 563         if (dc->debug.disable_stutter)
 564                 return;
 565
 566         if (!hws->wa.DEGVIDCN10_253)
 567                 return;
 568
 569         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 570                 if (!dc->res_pool->hubps[i]->power_gated)
 571                         return;
 572         }
 573
 574         /* all pipe power gated, apply work around to enable stutter. */
 575
 576         REG_SET(DC_IP_REQUEST_CNTL, 0,
 577                         IP_REQUEST_EN, 1);
 578
 579         hubp_pg_control(hws, 0, true);
 580         REG_SET(DC_IP_REQUEST_CNTL, 0,
 581                         IP_REQUEST_EN, 0);
 582
 583         hubp->funcs->set_hubp_blank_en(hubp, false);
 584         hws->wa_state.DEGVIDCN10_253_applied = true;
 585 }
 586
 587 static void bios_golden_init(struct dc *dc)
 588 {
 589         struct dc_bios *bp = dc->ctx->dc_bios;
 590         int i;
 591
 592         /* initialize dcn global */
 593         bp->funcs->enable_disp_power_gating(bp,
 594                         CONTROLLER_ID_D0, ASIC_PIPE_INIT);
 595
 596         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 597                 /* initialize dcn per pipe */
 598                 bp->funcs->enable_disp_power_gating(bp,
 599                                 CONTROLLER_ID_D0 + i, ASIC_PIPE_DISABLE);
 600         }
 601 }
 602
 603 static void false_optc_underflow_wa(
 604                 struct dc *dc,
 605                 const struct dc_stream_state *stream,
 606                 struct timing_generator *tg)
 607 {
 608         int i;
 609         bool underflow;
 610
 611         if (!dc->hwseq->wa.false_optc_underflow)
 612                 return;
 613
 614         underflow = tg->funcs->is_optc_underflow_occurred(tg);
 615
 616         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 617                 struct pipe_ctx *old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
 618
 619                 if (old_pipe_ctx->stream != stream)
 620                         continue;
 621
 622                 dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, old_pipe_ctx);
 623         }
 624
 625         tg->funcs->set_blank_data_double_buffer(tg, true);
 626
 627         if (tg->funcs->is_optc_underflow_occurred(tg) && !underflow)
 628                 tg->funcs->clear_optc_underflow(tg);
 629 }
 630
 631 static enum dc_status dcn10_enable_stream_timing(
 632                 struct pipe_ctx *pipe_ctx,
 633                 struct dc_state *context,
 634                 struct dc *dc)
 635 {
 636         struct dc_stream_state *stream = pipe_ctx->stream;
 637         enum dc_color_space color_space;
 638         struct tg_color black_color = {0};
 639
 640         /* by upper caller loop, pipe0 is parent pipe and be called first.
 641          * back end is set up by for pipe0. Other children pipe share back end
 642          * with pipe 0. No program is needed.
 643          */
 644         if (pipe_ctx->top_pipe != NULL)
 645                 return DC_OK;
 646
 647         /* TODO check if timing_changed, disable stream if timing changed */
 648
 649         /* HW program guide assume display already disable
 650          * by unplug sequence. OTG assume stop.
 651          */
 652         pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, true);
 653
 654         if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
 655                         pipe_ctx->clock_source,
 656                         &pipe_ctx->stream_res.pix_clk_params,
 657                         &pipe_ctx->pll_settings)) {
 658                 BREAK_TO_DEBUGGER();
 659                 return DC_ERROR_UNEXPECTED;
 660         }
 661         pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
 662         pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
 663         pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
 664         pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
 665
 666         pipe_ctx->stream_res.tg->dlg_otg_param.signal =  pipe_ctx->stream->signal;
 667
 668         pipe_ctx->stream_res.tg->funcs->program_timing(
 669                         pipe_ctx->stream_res.tg,
 670                         &stream->timing,
 671                         true);
 672
 673 #if 0 /* move to after enable_crtc */
 674         /* TODO: OPP FMT, ABM. etc. should be done here. */
 675         /* or FPGA now. instance 0 only. TODO: move to opp.c */
 676
 677         inst_offset = reg_offsets[pipe_ctx->stream_res.tg->inst].fmt;
 678
 679         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
 680                                 pipe_ctx->stream_res.opp,
 681                                 &stream->bit_depth_params,
 682                                 &stream->clamping);
 683 #endif
 684         /* program otg blank color */
 685         color_space = stream->output_color_space;
 686         color_space_to_black_color(dc, color_space, &black_color);
 687
 688         if (pipe_ctx->stream_res.tg->funcs->set_blank_color)
 689                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
 690                                 pipe_ctx->stream_res.tg,
 691                                 &black_color);
 692
 693         if (pipe_ctx->stream_res.tg->funcs->is_blanked &&
 694                         !pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) {
 695                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
 696                 hwss_wait_for_blank_complete(pipe_ctx->stream_res.tg);
 697                 false_optc_underflow_wa(dc, pipe_ctx->stream, pipe_ctx->stream_res.tg);
 698         }
 699
 700         /* VTG is  within DCHUB command block. DCFCLK is always on */
 701         if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(pipe_ctx->stream_res.tg)) {
 702                 BREAK_TO_DEBUGGER();
 703                 return DC_ERROR_UNEXPECTED;
 704         }
 705
 706         /* TODO program crtc source select for non-virtual signal*/
 707         /* TODO program FMT */
 708         /* TODO setup link_enc */
 709         /* TODO set stream attributes */
 710         /* TODO program audio */
 711         /* TODO enable stream if timing changed */
 712         /* TODO unblank stream if DP */
 713
 714         return DC_OK;
 715 }
 716
 717 static void dcn10_reset_back_end_for_pipe(
 718                 struct dc *dc,
 719                 struct pipe_ctx *pipe_ctx,
 720                 struct dc_state *context)
 721 {
 722         int i;
 723         DC_LOGGER_INIT(dc->ctx->logger);
 724         if (pipe_ctx->stream_res.stream_enc == NULL) {
 725                 pipe_ctx->stream = NULL;
 726                 return;
 727         }
 728
 729         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
 730                 /* DPMS may already disable */
 731                 if (!pipe_ctx->stream->dpms_off)
 732                         core_link_disable_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
 733                 else if (pipe_ctx->stream_res.audio) {
 734                         dc->hwss.disable_audio_stream(pipe_ctx, FREE_ACQUIRED_RESOURCE);
 735                 }
 736
 737         }
 738
 739         /* by upper caller loop, parent pipe: pipe0, will be reset last.
 740          * back end share by all pipes and will be disable only when disable
 741          * parent pipe.
 742          */
 743         if (pipe_ctx->top_pipe == NULL) {
 744                 pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg);
 745
 746                 pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false);
 747         }
 748
 749         for (i = 0; i < dc->res_pool->pipe_count; i++)
 750                 if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx)
 751                         break;
 752
 753         if (i == dc->res_pool->pipe_count)
 754                 return;
 755
 756         pipe_ctx->stream = NULL;
 757         DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n",
 758                                         pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst);
 759 }
 760
 761 static bool dcn10_hw_wa_force_recovery(struct dc *dc)
 762 {
 763         struct hubp *hubp ;
 764         unsigned int i;
 765         bool need_recover = true;
 766
 767         if (!dc->debug.recovery_enabled)
 768                 return false;
 769
 770         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 771                 struct pipe_ctx *pipe_ctx =
 772                         &dc->current_state->res_ctx.pipe_ctx[i];
 773                 if (pipe_ctx != NULL) {
 774                         hubp = pipe_ctx->plane_res.hubp;
 775                         if (hubp != NULL && hubp->funcs->hubp_get_underflow_status) {
 776                                 if (hubp->funcs->hubp_get_underflow_status(hubp) != 0) {
 777                                         /* one pipe underflow, we will reset all the pipes*/
 778                                         need_recover = true;
 779                                 }
 780                         }
 781                 }
 782         }
 783         if (!need_recover)
 784                 return false;
 785         /*
 786         DCHUBP_CNTL:HUBP_BLANK_EN=1
 787         DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=1
 788         DCHUBP_CNTL:HUBP_DISABLE=1
 789         DCHUBP_CNTL:HUBP_DISABLE=0
 790         DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=0
 791         DCSURF_PRIMARY_SURFACE_ADDRESS
 792         DCHUBP_CNTL:HUBP_BLANK_EN=0
 793         */
 794
 795         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 796                 struct pipe_ctx *pipe_ctx =
 797                         &dc->current_state->res_ctx.pipe_ctx[i];
 798                 if (pipe_ctx != NULL) {
 799                         hubp = pipe_ctx->plane_res.hubp;
 800                         /*DCHUBP_CNTL:HUBP_BLANK_EN=1*/
 801                         if (hubp != NULL && hubp->funcs->set_hubp_blank_en)
 802                                 hubp->funcs->set_hubp_blank_en(hubp, true);
 803                 }
 804         }
 805         /*DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=1*/
 806         hubbub1_soft_reset(dc->res_pool->hubbub, true);
 807
 808         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 809                 struct pipe_ctx *pipe_ctx =
 810                         &dc->current_state->res_ctx.pipe_ctx[i];
 811                 if (pipe_ctx != NULL) {
 812                         hubp = pipe_ctx->plane_res.hubp;
 813                         /*DCHUBP_CNTL:HUBP_DISABLE=1*/
 814                         if (hubp != NULL && hubp->funcs->hubp_disable_control)
 815                                 hubp->funcs->hubp_disable_control(hubp, true);
 816                 }
 817         }
 818         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 819                 struct pipe_ctx *pipe_ctx =
 820                         &dc->current_state->res_ctx.pipe_ctx[i];
 821                 if (pipe_ctx != NULL) {
 822                         hubp = pipe_ctx->plane_res.hubp;
 823                         /*DCHUBP_CNTL:HUBP_DISABLE=0*/
 824                         if (hubp != NULL && hubp->funcs->hubp_disable_control)
 825                                 hubp->funcs->hubp_disable_control(hubp, true);
 826                 }
 827         }
 828         /*DCHUBBUB_SOFT_RESET:DCHUBBUB_GLOBAL_SOFT_RESET=0*/
 829         hubbub1_soft_reset(dc->res_pool->hubbub, false);
 830         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 831                 struct pipe_ctx *pipe_ctx =
 832                         &dc->current_state->res_ctx.pipe_ctx[i];
 833                 if (pipe_ctx != NULL) {
 834                         hubp = pipe_ctx->plane_res.hubp;
 835                         /*DCHUBP_CNTL:HUBP_BLANK_EN=0*/
 836                         if (hubp != NULL && hubp->funcs->set_hubp_blank_en)
 837                                 hubp->funcs->set_hubp_blank_en(hubp, true);
 838                 }
 839         }
 840         return true;
 841
 842 }
 843
 844
 845 void dcn10_verify_allow_pstate_change_high(struct dc *dc)
 846 {
 847         static bool should_log_hw_state; /* prevent hw state log by default */
 848
 849         if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub)) {
 850                 if (should_log_hw_state) {
 851                         dcn10_log_hw_state(dc, NULL);
 852                 }
 853                 BREAK_TO_DEBUGGER();
 854                 if (dcn10_hw_wa_force_recovery(dc)) {
 855                 /*check again*/
 856                         if (!hubbub1_verify_allow_pstate_change_high(dc->res_pool->hubbub))
 857                                 BREAK_TO_DEBUGGER();
 858                 }
 859         }
 860 }
 861
 862 /* trigger HW to start disconnect plane from stream on the next vsync */
 863 void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx)
 864 {
 865         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 866         int dpp_id = pipe_ctx->plane_res.dpp->inst;
 867         struct mpc *mpc = dc->res_pool->mpc;
 868         struct mpc_tree *mpc_tree_params;
 869         struct mpcc *mpcc_to_remove = NULL;
 870         struct output_pixel_processor *opp = pipe_ctx->stream_res.opp;
 871
 872         mpc_tree_params = &(opp->mpc_tree_params);
 873         mpcc_to_remove = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, dpp_id);
 874
 875         /*Already reset*/
 876         if (mpcc_to_remove == NULL)
 877                 return;
 878
 879         mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);
 880         if (opp != NULL)
 881                 opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
 882
 883         dc->optimized_required = true;
 884
 885         if (hubp->funcs->hubp_disconnect)
 886                 hubp->funcs->hubp_disconnect(hubp);
 887
 888         if (dc->debug.sanity_checks)
 889                 dcn10_verify_allow_pstate_change_high(dc);
 890 }
 891
 892 static void plane_atomic_power_down(struct dc *dc,
 893                 struct dpp *dpp,
 894                 struct hubp *hubp)
 895 {
 896         struct dce_hwseq *hws = dc->hwseq;
 897         DC_LOGGER_INIT(dc->ctx->logger);
 898
 899         if (REG(DC_IP_REQUEST_CNTL)) {
 900                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 901                                 IP_REQUEST_EN, 1);
 902                 dpp_pg_control(hws, dpp->inst, false);
 903                 hubp_pg_control(hws, hubp->inst, false);
 904                 dpp->funcs->dpp_reset(dpp);
 905                 REG_SET(DC_IP_REQUEST_CNTL, 0,
 906                                 IP_REQUEST_EN, 0);
 907                 DC_LOG_DEBUG(
 908                                 "Power gated front end %d\n", hubp->inst);
 909         }
 910 }
 911
 912 /* disable HW used by plane.
 913  * note:  cannot disable until disconnect is complete
 914  */
 915 static void plane_atomic_disable(struct dc *dc, struct pipe_ctx *pipe_ctx)
 916 {
 917         struct hubp *hubp = pipe_ctx->plane_res.hubp;
 918         struct dpp *dpp = pipe_ctx->plane_res.dpp;
 919         int opp_id = hubp->opp_id;
 920
 921         dc->hwss.wait_for_mpcc_disconnect(dc, dc->res_pool, pipe_ctx);
 922
 923         hubp->funcs->hubp_clk_cntl(hubp, false);
 924
 925         dpp->funcs->dpp_dppclk_control(dpp, false, false);
 926
 927         if (opp_id != 0xf && pipe_ctx->stream_res.opp->mpc_tree_params.opp_list == NULL)
 928                 pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
 929                                 pipe_ctx->stream_res.opp,
 930                                 false);
 931
 932         hubp->power_gated = true;
 933         dc->optimized_required = false; /* We're powering off, no need to optimize */
 934
 935         plane_atomic_power_down(dc,
 936                         pipe_ctx->plane_res.dpp,
 937                         pipe_ctx->plane_res.hubp);
 938
 939         pipe_ctx->stream = NULL;
 940         memset(&pipe_ctx->stream_res, 0, sizeof(pipe_ctx->stream_res));
 941         memset(&pipe_ctx->plane_res, 0, sizeof(pipe_ctx->plane_res));
 942         pipe_ctx->top_pipe = NULL;
 943         pipe_ctx->bottom_pipe = NULL;
 944         pipe_ctx->plane_state = NULL;
 945 }
 946
 947 static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx)
 948 {
 949         DC_LOGGER_INIT(dc->ctx->logger);
 950
 951         if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated)
 952                 return;
 953
 954         plane_atomic_disable(dc, pipe_ctx);
 955
 956         apply_DEGVIDCN10_253_wa(dc);
 957
 958         DC_LOG_DC("Power down front end %d\n",
 959                                         pipe_ctx->pipe_idx);
 960 }
 961
 962 static void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
 963 {
 964         int i;
 965         bool can_apply_seamless_boot = false;
 966
 967         for (i = 0; i < context->stream_count; i++) {
 968                 if (context->streams[i]->apply_seamless_boot_optimization) {
 969                         can_apply_seamless_boot = true;
 970                         break;
 971                 }
 972         }
 973
 974         for (i = 0; i < dc->res_pool->pipe_count; i++) {
 975                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
 976                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
 977
 978                 /* There is assumption that pipe_ctx is not mapping irregularly
 979                  * to non-preferred front end. If pipe_ctx->stream is not NULL,
 980                  * we will use the pipe, so don't disable
 981                  */
 982                 if (pipe_ctx->stream != NULL)
 983                         continue;
 984
 985                 if (tg->funcs->is_tg_enabled(tg))
 986                         tg->funcs->lock(tg);
 987
 988                 /* Blank controller using driver code instead of
 989                  * command table.
 990                  */
 991                 if (tg->funcs->is_tg_enabled(tg)) {
 992                         tg->funcs->set_blank(tg, true);
 993                         hwss_wait_for_blank_complete(tg);
 994                 }
 995         }
 996
 997         /* Cannot reset the MPC mux if seamless boot */
 998         if (!can_apply_seamless_boot)
 999                 dc->res_pool->mpc->funcs->mpc_init(dc->res_pool->mpc);
1000
1001         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1002                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
1003                 struct hubp *hubp = dc->res_pool->hubps[i];
1004                 struct dpp *dpp = dc->res_pool->dpps[i];
1005                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1006
1007                 /* There is assumption that pipe_ctx is not mapping irregularly
1008                  * to non-preferred front end. If pipe_ctx->stream is not NULL,
1009                  * we will use the pipe, so don't disable
1010                  */
1011                 if (can_apply_seamless_boot &&
1012                         pipe_ctx->stream != NULL &&
1013                         pipe_ctx->stream_res.tg->funcs->is_tg_enabled(
1014                                 pipe_ctx->stream_res.tg))
1015                         continue;
1016
1017                 /* Disable on the current state so the new one isn't cleared. */
1018                 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
1019
1020                 dpp->funcs->dpp_reset(dpp);
1021
1022                 pipe_ctx->stream_res.tg = tg;
1023                 pipe_ctx->pipe_idx = i;
1024
1025                 pipe_ctx->plane_res.hubp = hubp;
1026                 pipe_ctx->plane_res.dpp = dpp;
1027                 pipe_ctx->plane_res.mpcc_inst = dpp->inst;
1028                 hubp->mpcc_id = dpp->inst;
1029                 hubp->opp_id = 0xf;
1030                 hubp->power_gated = false;
1031
1032                 dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
1033                 dc->res_pool->opps[i]->mpc_tree_params.opp_list = NULL;
1034                 dc->res_pool->opps[i]->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;
1035                 pipe_ctx->stream_res.opp = dc->res_pool->opps[i];
1036
1037                 hwss1_plane_atomic_disconnect(dc, pipe_ctx);
1038
1039                 if (tg->funcs->is_tg_enabled(tg))
1040                         tg->funcs->unlock(tg);
1041
1042                 dcn10_disable_plane(dc, pipe_ctx);
1043
1044                 pipe_ctx->stream_res.tg = NULL;
1045                 pipe_ctx->plane_res.hubp = NULL;
1046
1047                 tg->funcs->tg_init(tg);
1048         }
1049 }
1050
1051 static void dcn10_init_hw(struct dc *dc)
1052 {
1053         int i;
1054         struct abm *abm = dc->res_pool->abm;
1055         struct dmcu *dmcu = dc->res_pool->dmcu;
1056         struct dce_hwseq *hws = dc->hwseq;
1057         struct dc_bios *dcb = dc->ctx->dc_bios;
1058
1059         if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
1060                 REG_WRITE(REFCLK_CNTL, 0);
1061                 REG_UPDATE(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_ENABLE, 1);
1062                 REG_WRITE(DIO_MEM_PWR_CTRL, 0);
1063
1064                 if (!dc->debug.disable_clock_gate) {
1065                         /* enable all DCN clock gating */
1066                         REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
1067
1068                         REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
1069
1070                         REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
1071                 }
1072
1073                 enable_power_gating_plane(dc->hwseq, true);
1074
1075                 /* end of FPGA. Below if real ASIC */
1076                 return;
1077         }
1078
1079         if (!dcb->funcs->is_accelerated_mode(dcb)) {
1080                 bool allow_self_fresh_force_enable =
1081                         hububu1_is_allow_self_refresh_enabled(
1082                                                 dc->res_pool->hubbub);
1083
1084                 bios_golden_init(dc);
1085
1086                 /* WA for making DF sleep when idle after resume from S0i3.
1087                  * DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE is set to 1 by
1088                  * command table, if DCHUBBUB_ARB_ALLOW_SELF_REFRESH_FORCE_ENABLE = 0
1089                  * before calling command table and it changed to 1 after,
1090                  * it should be set back to 0.
1091                  */
1092                 if (allow_self_fresh_force_enable == false &&
1093                                 hububu1_is_allow_self_refresh_enabled(dc->res_pool->hubbub))
1094                         hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, true);
1095
1096                 disable_vga(dc->hwseq);
1097         }
1098
1099         for (i = 0; i < dc->link_count; i++) {
1100                 /* Power up AND update implementation according to the
1101                  * required signal (which may be different from the
1102                  * default signal on connector).
1103                  */
1104                 struct dc_link *link = dc->links[i];
1105
1106                 if (link->link_enc->connector.id == CONNECTOR_ID_EDP)
1107                         dc->hwss.edp_power_control(link, true);
1108
1109                 link->link_enc->funcs->hw_init(link->link_enc);
1110
1111                 /* Check for enabled DIG to identify enabled display */
1112                 if (link->link_enc->funcs->is_dig_enabled &&
1113                         link->link_enc->funcs->is_dig_enabled(link->link_enc))
1114                         link->link_status.link_active = true;
1115         }
1116
1117         /* If taking control over from VBIOS, we may want to optimize our first
1118          * mode set, so we need to skip powering down pipes until we know which
1119          * pipes we want to use.
1120          * Otherwise, if taking control is not possible, we need to power
1121          * everything down.
1122          */
1123         if (dcb->funcs->is_accelerated_mode(dcb)) {
1124                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
1125                         struct hubp *hubp = dc->res_pool->hubps[i];
1126                         struct dpp *dpp = dc->res_pool->dpps[i];
1127
1128                         dc->res_pool->opps[i]->mpc_tree_params.opp_id = dc->res_pool->opps[i]->inst;
1129                         plane_atomic_power_down(dc, dpp, hubp);
1130                 }
1131         }
1132
1133         for (i = 0; i < dc->res_pool->audio_count; i++) {
1134                 struct audio *audio = dc->res_pool->audios[i];
1135
1136                 audio->funcs->hw_init(audio);
1137         }
1138
1139         if (abm != NULL) {
1140                 abm->funcs->init_backlight(abm);
1141                 abm->funcs->abm_init(abm);
1142         }
1143
1144         if (dmcu != NULL)
1145                 dmcu->funcs->dmcu_init(dmcu);
1146
1147         /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
1148         REG_WRITE(DIO_MEM_PWR_CTRL, 0);
1149
1150         if (!dc->debug.disable_clock_gate) {
1151                 /* enable all DCN clock gating */
1152                 REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
1153
1154                 REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
1155
1156                 REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
1157         }
1158
1159         enable_power_gating_plane(dc->hwseq, true);
1160
1161         memset(&dc->res_pool->clk_mgr->clks, 0, sizeof(dc->res_pool->clk_mgr->clks));
1162 }
1163
1164 static void dcn10_reset_hw_ctx_wrap(
1165                 struct dc *dc,
1166                 struct dc_state *context)
1167 {
1168         int i;
1169
1170         /* Reset Back End*/
1171         for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) {
1172                 struct pipe_ctx *pipe_ctx_old =
1173                         &dc->current_state->res_ctx.pipe_ctx[i];
1174                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1175
1176                 if (!pipe_ctx_old->stream)
1177                         continue;
1178
1179                 if (pipe_ctx_old->top_pipe)
1180                         continue;
1181
1182                 if (!pipe_ctx->stream ||
1183                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
1184                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
1185
1186                         dcn10_reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state);
1187                         if (dc->hwss.enable_stream_gating)
1188                                 dc->hwss.enable_stream_gating(dc, pipe_ctx);
1189                         if (old_clk)
1190                                 old_clk->funcs->cs_power_down(old_clk);
1191                 }
1192         }
1193 }
1194
1195 static bool patch_address_for_sbs_tb_stereo(
1196                 struct pipe_ctx *pipe_ctx, PHYSICAL_ADDRESS_LOC *addr)
1197 {
1198         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1199         bool sec_split = pipe_ctx->top_pipe &&
1200                         pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state;
1201         if (sec_split && plane_state->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
1202                 (pipe_ctx->stream->timing.timing_3d_format ==
1203                  TIMING_3D_FORMAT_SIDE_BY_SIDE ||
1204                  pipe_ctx->stream->timing.timing_3d_format ==
1205                  TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
1206                 *addr = plane_state->address.grph_stereo.left_addr;
1207                 plane_state->address.grph_stereo.left_addr =
1208                 plane_state->address.grph_stereo.right_addr;
1209                 return true;
1210         } else {
1211                 if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
1212                         plane_state->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
1213                         plane_state->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
1214                         plane_state->address.grph_stereo.right_addr =
1215                         plane_state->address.grph_stereo.left_addr;
1216                 }
1217         }
1218         return false;
1219 }
1220
1221
1222
1223 static void dcn10_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
1224 {
1225         bool addr_patched = false;
1226         PHYSICAL_ADDRESS_LOC addr;
1227         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
1228
1229         if (plane_state == NULL)
1230                 return;
1231
1232         addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
1233
1234         pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
1235                         pipe_ctx->plane_res.hubp,
1236                         &plane_state->address,
1237                         plane_state->flip_immediate,
1238                         0);
1239
1240         plane_state->status.requested_address = plane_state->address;
1241
1242         if (plane_state->flip_immediate)
1243                 plane_state->status.current_address = plane_state->address;
1244
1245         if (addr_patched)
1246                 pipe_ctx->plane_state->address.grph_stereo.left_addr = addr;
1247 }
1248
1249 static bool dcn10_set_input_transfer_func(struct pipe_ctx *pipe_ctx,
1250                                           const struct dc_plane_state *plane_state)
1251 {
1252         struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
1253         const struct dc_transfer_func *tf = NULL;
1254         bool result = true;
1255
1256         if (dpp_base == NULL)
1257                 return false;
1258
1259         if (plane_state->in_transfer_func)
1260                 tf = plane_state->in_transfer_func;
1261
1262         if (plane_state->gamma_correction &&
1263                 !dpp_base->ctx->dc->debug.always_use_regamma
1264                 && !plane_state->gamma_correction->is_identity
1265                         && dce_use_lut(plane_state->format))
1266                 dpp_base->funcs->dpp_program_input_lut(dpp_base, plane_state->gamma_correction);
1267
1268         if (tf == NULL)
1269                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1270         else if (tf->type == TF_TYPE_PREDEFINED) {
1271                 switch (tf->tf) {
1272                 case TRANSFER_FUNCTION_SRGB:
1273                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_sRGB);
1274                         break;
1275                 case TRANSFER_FUNCTION_BT709:
1276                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_HW_xvYCC);
1277                         break;
1278                 case TRANSFER_FUNCTION_LINEAR:
1279                         dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1280                         break;
1281                 case TRANSFER_FUNCTION_PQ:
1282                 default:
1283                         result = false;
1284                         break;
1285                 }
1286         } else if (tf->type == TF_TYPE_BYPASS) {
1287                 dpp_base->funcs->dpp_set_degamma(dpp_base, IPP_DEGAMMA_MODE_BYPASS);
1288         } else {
1289                 cm_helper_translate_curve_to_degamma_hw_format(tf,
1290                                         &dpp_base->degamma_params);
1291                 dpp_base->funcs->dpp_program_degamma_pwl(dpp_base,
1292                                 &dpp_base->degamma_params);
1293                 result = true;
1294         }
1295
1296         return result;
1297 }
1298
1299
1300
1301
1302
1303 static bool
1304 dcn10_set_output_transfer_func(struct pipe_ctx *pipe_ctx,
1305                                const struct dc_stream_state *stream)
1306 {
1307         struct dpp *dpp = pipe_ctx->plane_res.dpp;
1308
1309         if (dpp == NULL)
1310                 return false;
1311
1312         dpp->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
1313
1314         if (stream->out_transfer_func &&
1315             stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
1316             stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB)
1317                 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_SRGB);
1318
1319         /* dcn10_translate_regamma_to_hw_format takes 750us, only do it when full
1320          * update.
1321          */
1322         else if (cm_helper_translate_curve_to_hw_format(
1323                         stream->out_transfer_func,
1324                         &dpp->regamma_params, false)) {
1325                 dpp->funcs->dpp_program_regamma_pwl(
1326                                 dpp,
1327                                 &dpp->regamma_params, OPP_REGAMMA_USER);
1328         } else
1329                 dpp->funcs->dpp_program_regamma_pwl(dpp, NULL, OPP_REGAMMA_BYPASS);
1330
1331         return true;
1332 }
1333
1334 static void dcn10_pipe_control_lock(
1335         struct dc *dc,
1336         struct pipe_ctx *pipe,
1337         bool lock)
1338 {
1339         /* use TG master update lock to lock everything on the TG
1340          * therefore only top pipe need to lock
1341          */
1342         if (pipe->top_pipe)
1343                 return;
1344
1345         if (dc->debug.sanity_checks)
1346                 dcn10_verify_allow_pstate_change_high(dc);
1347
1348         if (lock)
1349                 pipe->stream_res.tg->funcs->lock(pipe->stream_res.tg);
1350         else
1351                 pipe->stream_res.tg->funcs->unlock(pipe->stream_res.tg);
1352
1353         if (dc->debug.sanity_checks)
1354                 dcn10_verify_allow_pstate_change_high(dc);
1355 }
1356
1357 static bool wait_for_reset_trigger_to_occur(
1358         struct dc_context *dc_ctx,
1359         struct timing_generator *tg)
1360 {
1361         bool rc = false;
1362
1363         /* To avoid endless loop we wait at most
1364          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
1365         const uint32_t frames_to_wait_on_triggered_reset = 10;
1366         int i;
1367
1368         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
1369
1370                 if (!tg->funcs->is_counter_moving(tg)) {
1371                         DC_ERROR("TG counter is not moving!\n");
1372                         break;
1373                 }
1374
1375                 if (tg->funcs->did_triggered_reset_occur(tg)) {
1376                         rc = true;
1377                         /* usually occurs at i=1 */
1378                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
1379                                         i);
1380                         break;
1381                 }
1382
1383                 /* Wait for one frame. */
1384                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
1385                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
1386         }
1387
1388         if (false == rc)
1389                 DC_ERROR("GSL: Timeout on reset trigger!\n");
1390
1391         return rc;
1392 }
1393
1394 static void dcn10_enable_timing_synchronization(
1395         struct dc *dc,
1396         int group_index,
1397         int group_size,
1398         struct pipe_ctx *grouped_pipes[])
1399 {
1400         struct dc_context *dc_ctx = dc->ctx;
1401         int i;
1402
1403         DC_SYNC_INFO("Setting up OTG reset trigger\n");
1404
1405         for (i = 1; i < group_size; i++)
1406                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
1407                                 grouped_pipes[i]->stream_res.tg,
1408                                 grouped_pipes[0]->stream_res.tg->inst);
1409
1410         DC_SYNC_INFO("Waiting for trigger\n");
1411
1412         /* Need to get only check 1 pipe for having reset as all the others are
1413          * synchronized. Look at last pipe programmed to reset.
1414          */
1415
1416         wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[1]->stream_res.tg);
1417         for (i = 1; i < group_size; i++)
1418                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
1419                                 grouped_pipes[i]->stream_res.tg);
1420
1421         DC_SYNC_INFO("Sync complete\n");
1422 }
1423
1424 static void dcn10_enable_per_frame_crtc_position_reset(
1425         struct dc *dc,
1426         int group_size,
1427         struct pipe_ctx *grouped_pipes[])
1428 {
1429         struct dc_context *dc_ctx = dc->ctx;
1430         int i;
1431
1432         DC_SYNC_INFO("Setting up\n");
1433         for (i = 0; i < group_size; i++)
1434                 if (grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset)
1435                         grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
1436                                         grouped_pipes[i]->stream_res.tg,
1437                                         0,
1438                                         &grouped_pipes[i]->stream->triggered_crtc_reset);
1439
1440         DC_SYNC_INFO("Waiting for trigger\n");
1441
1442         for (i = 0; i < group_size; i++)
1443                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
1444
1445         DC_SYNC_INFO("Multi-display sync is complete\n");
1446 }
1447
1448 /*static void print_rq_dlg_ttu(
1449                 struct dc *core_dc,
1450                 struct pipe_ctx *pipe_ctx)
1451 {
1452         DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1453                         "\n============== DML TTU Output parameters [%d] ==============\n"
1454                         "qos_level_low_wm: %d, \n"
1455                         "qos_level_high_wm: %d, \n"
1456                         "min_ttu_vblank: %d, \n"
1457                         "qos_level_flip: %d, \n"
1458                         "refcyc_per_req_delivery_l: %d, \n"
1459                         "qos_level_fixed_l: %d, \n"
1460                         "qos_ramp_disable_l: %d, \n"
1461                         "refcyc_per_req_delivery_pre_l: %d, \n"
1462                         "refcyc_per_req_delivery_c: %d, \n"
1463                         "qos_level_fixed_c: %d, \n"
1464                         "qos_ramp_disable_c: %d, \n"
1465                         "refcyc_per_req_delivery_pre_c: %d\n"
1466                         "=============================================================\n",
1467                         pipe_ctx->pipe_idx,
1468                         pipe_ctx->ttu_regs.qos_level_low_wm,
1469                         pipe_ctx->ttu_regs.qos_level_high_wm,
1470                         pipe_ctx->ttu_regs.min_ttu_vblank,
1471                         pipe_ctx->ttu_regs.qos_level_flip,
1472                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_l,
1473                         pipe_ctx->ttu_regs.qos_level_fixed_l,
1474                         pipe_ctx->ttu_regs.qos_ramp_disable_l,
1475                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_l,
1476                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_c,
1477                         pipe_ctx->ttu_regs.qos_level_fixed_c,
1478                         pipe_ctx->ttu_regs.qos_ramp_disable_c,
1479                         pipe_ctx->ttu_regs.refcyc_per_req_delivery_pre_c
1480                         );
1481
1482         DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1483                         "\n============== DML DLG Output parameters [%d] ==============\n"
1484                         "refcyc_h_blank_end: %d, \n"
1485                         "dlg_vblank_end: %d, \n"
1486                         "min_dst_y_next_start: %d, \n"
1487                         "refcyc_per_htotal: %d, \n"
1488                         "refcyc_x_after_scaler: %d, \n"
1489                         "dst_y_after_scaler: %d, \n"
1490                         "dst_y_prefetch: %d, \n"
1491                         "dst_y_per_vm_vblank: %d, \n"
1492                         "dst_y_per_row_vblank: %d, \n"
1493                         "ref_freq_to_pix_freq: %d, \n"
1494                         "vratio_prefetch: %d, \n"
1495                         "refcyc_per_pte_group_vblank_l: %d, \n"
1496                         "refcyc_per_meta_chunk_vblank_l: %d, \n"
1497                         "dst_y_per_pte_row_nom_l: %d, \n"
1498                         "refcyc_per_pte_group_nom_l: %d, \n",
1499                         pipe_ctx->pipe_idx,
1500                         pipe_ctx->dlg_regs.refcyc_h_blank_end,
1501                         pipe_ctx->dlg_regs.dlg_vblank_end,
1502                         pipe_ctx->dlg_regs.min_dst_y_next_start,
1503                         pipe_ctx->dlg_regs.refcyc_per_htotal,
1504                         pipe_ctx->dlg_regs.refcyc_x_after_scaler,
1505                         pipe_ctx->dlg_regs.dst_y_after_scaler,
1506                         pipe_ctx->dlg_regs.dst_y_prefetch,
1507                         pipe_ctx->dlg_regs.dst_y_per_vm_vblank,
1508                         pipe_ctx->dlg_regs.dst_y_per_row_vblank,
1509                         pipe_ctx->dlg_regs.ref_freq_to_pix_freq,
1510                         pipe_ctx->dlg_regs.vratio_prefetch,
1511                         pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_l,
1512                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_l,
1513                         pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_l,
1514                         pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_l
1515                         );
1516
1517         DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1518                         "\ndst_y_per_meta_row_nom_l: %d, \n"
1519                         "refcyc_per_meta_chunk_nom_l: %d, \n"
1520                         "refcyc_per_line_delivery_pre_l: %d, \n"
1521                         "refcyc_per_line_delivery_l: %d, \n"
1522                         "vratio_prefetch_c: %d, \n"
1523                         "refcyc_per_pte_group_vblank_c: %d, \n"
1524                         "refcyc_per_meta_chunk_vblank_c: %d, \n"
1525                         "dst_y_per_pte_row_nom_c: %d, \n"
1526                         "refcyc_per_pte_group_nom_c: %d, \n"
1527                         "dst_y_per_meta_row_nom_c: %d, \n"
1528                         "refcyc_per_meta_chunk_nom_c: %d, \n"
1529                         "refcyc_per_line_delivery_pre_c: %d, \n"
1530                         "refcyc_per_line_delivery_c: %d \n"
1531                         "========================================================\n",
1532                         pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_l,
1533                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_l,
1534                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_l,
1535                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_l,
1536                         pipe_ctx->dlg_regs.vratio_prefetch_c,
1537                         pipe_ctx->dlg_regs.refcyc_per_pte_group_vblank_c,
1538                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_vblank_c,
1539                         pipe_ctx->dlg_regs.dst_y_per_pte_row_nom_c,
1540                         pipe_ctx->dlg_regs.refcyc_per_pte_group_nom_c,
1541                         pipe_ctx->dlg_regs.dst_y_per_meta_row_nom_c,
1542                         pipe_ctx->dlg_regs.refcyc_per_meta_chunk_nom_c,
1543                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_pre_c,
1544                         pipe_ctx->dlg_regs.refcyc_per_line_delivery_c
1545                         );
1546
1547         DC_LOG_BANDWIDTH_CALCS(core_dc->ctx->logger,
1548                         "\n============== DML RQ Output parameters [%d] ==============\n"
1549                         "chunk_size: %d \n"
1550                         "min_chunk_size: %d \n"
1551                         "meta_chunk_size: %d \n"
1552                         "min_meta_chunk_size: %d \n"
1553                         "dpte_group_size: %d \n"
1554                         "mpte_group_size: %d \n"
1555                         "swath_height: %d \n"
1556                         "pte_row_height_linear: %d \n"
1557                         "========================================================\n",
1558                         pipe_ctx->pipe_idx,
1559                         pipe_ctx->rq_regs.rq_regs_l.chunk_size,
1560                         pipe_ctx->rq_regs.rq_regs_l.min_chunk_size,
1561                         pipe_ctx->rq_regs.rq_regs_l.meta_chunk_size,
1562                         pipe_ctx->rq_regs.rq_regs_l.min_meta_chunk_size,
1563                         pipe_ctx->rq_regs.rq_regs_l.dpte_group_size,
1564                         pipe_ctx->rq_regs.rq_regs_l.mpte_group_size,
1565                         pipe_ctx->rq_regs.rq_regs_l.swath_height,
1566                         pipe_ctx->rq_regs.rq_regs_l.pte_row_height_linear
1567                         );
1568 }
1569 */
1570
1571 static void mmhub_read_vm_system_aperture_settings(struct dcn10_hubp *hubp1,
1572                 struct vm_system_aperture_param *apt,
1573                 struct dce_hwseq *hws)
1574 {
1575         PHYSICAL_ADDRESS_LOC physical_page_number;
1576         uint32_t logical_addr_low;
1577         uint32_t logical_addr_high;
1578
1579         REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
1580                         PHYSICAL_PAGE_NUMBER_MSB, &physical_page_number.high_part);
1581         REG_GET(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
1582                         PHYSICAL_PAGE_NUMBER_LSB, &physical_page_number.low_part);
1583
1584         REG_GET(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1585                         LOGICAL_ADDR, &logical_addr_low);
1586
1587         REG_GET(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1588                         LOGICAL_ADDR, &logical_addr_high);
1589
1590         apt->sys_default.quad_part =  physical_page_number.quad_part << 12;
1591         apt->sys_low.quad_part =  (int64_t)logical_addr_low << 18;
1592         apt->sys_high.quad_part =  (int64_t)logical_addr_high << 18;
1593 }
1594
1595 /* Temporary read settings, future will get values from kmd directly */
1596 static void mmhub_read_vm_context0_settings(struct dcn10_hubp *hubp1,
1597                 struct vm_context0_param *vm0,
1598                 struct dce_hwseq *hws)
1599 {
1600         PHYSICAL_ADDRESS_LOC fb_base;
1601         PHYSICAL_ADDRESS_LOC fb_offset;
1602         uint32_t fb_base_value;
1603         uint32_t fb_offset_value;
1604
1605         REG_GET(DCHUBBUB_SDPIF_FB_BASE, SDPIF_FB_BASE, &fb_base_value);
1606         REG_GET(DCHUBBUB_SDPIF_FB_OFFSET, SDPIF_FB_OFFSET, &fb_offset_value);
1607
1608         REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
1609                         PAGE_DIRECTORY_ENTRY_HI32, &vm0->pte_base.high_part);
1610         REG_GET(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
1611                         PAGE_DIRECTORY_ENTRY_LO32, &vm0->pte_base.low_part);
1612
1613         REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
1614                         LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_start.high_part);
1615         REG_GET(VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
1616                         LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_start.low_part);
1617
1618         REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
1619                         LOGICAL_PAGE_NUMBER_HI4, &vm0->pte_end.high_part);
1620         REG_GET(VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
1621                         LOGICAL_PAGE_NUMBER_LO32, &vm0->pte_end.low_part);
1622
1623         REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
1624                         PHYSICAL_PAGE_ADDR_HI4, &vm0->fault_default.high_part);
1625         REG_GET(VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
1626                         PHYSICAL_PAGE_ADDR_LO32, &vm0->fault_default.low_part);
1627
1628         /*
1629          * The values in VM_CONTEXT0_PAGE_TABLE_BASE_ADDR is in UMA space.
1630          * Therefore we need to do
1631          * DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR = VM_CONTEXT0_PAGE_TABLE_BASE_ADDR
1632          * - DCHUBBUB_SDPIF_FB_OFFSET + DCHUBBUB_SDPIF_FB_BASE
1633          */
1634         fb_base.quad_part = (uint64_t)fb_base_value << 24;
1635         fb_offset.quad_part = (uint64_t)fb_offset_value << 24;
1636         vm0->pte_base.quad_part += fb_base.quad_part;
1637         vm0->pte_base.quad_part -= fb_offset.quad_part;
1638 }
1639
1640
1641 void dcn10_program_pte_vm(struct dce_hwseq *hws, struct hubp *hubp)
1642 {
1643         struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
1644         struct vm_system_aperture_param apt = { {{ 0 } } };
1645         struct vm_context0_param vm0 = { { { 0 } } };
1646
1647         mmhub_read_vm_system_aperture_settings(hubp1, &apt, hws);
1648         mmhub_read_vm_context0_settings(hubp1, &vm0, hws);
1649
1650         hubp->funcs->hubp_set_vm_system_aperture_settings(hubp, &apt);
1651         hubp->funcs->hubp_set_vm_context0_settings(hubp, &vm0);
1652 }
1653
1654 static void dcn10_enable_plane(
1655         struct dc *dc,
1656         struct pipe_ctx *pipe_ctx,
1657         struct dc_state *context)
1658 {
1659         struct dce_hwseq *hws = dc->hwseq;
1660
1661         if (dc->debug.sanity_checks) {
1662                 dcn10_verify_allow_pstate_change_high(dc);
1663         }
1664
1665         undo_DEGVIDCN10_253_wa(dc);
1666
1667         power_on_plane(dc->hwseq,
1668                 pipe_ctx->plane_res.hubp->inst);
1669
1670         /* enable DCFCLK current DCHUB */
1671         pipe_ctx->plane_res.hubp->funcs->hubp_clk_cntl(pipe_ctx->plane_res.hubp, true);
1672
1673         /* make sure OPP_PIPE_CLOCK_EN = 1 */
1674         pipe_ctx->stream_res.opp->funcs->opp_pipe_clock_control(
1675                         pipe_ctx->stream_res.opp,
1676                         true);
1677
1678 /* TODO: enable/disable in dm as per update type.
1679         if (plane_state) {
1680                 DC_LOG_DC(dc->ctx->logger,
1681                                 "Pipe:%d 0x%x: addr hi:0x%x, "
1682                                 "addr low:0x%x, "
1683                                 "src: %d, %d, %d,"
1684                                 " %d; dst: %d, %d, %d, %d;\n",
1685                                 pipe_ctx->pipe_idx,
1686                                 plane_state,
1687                                 plane_state->address.grph.addr.high_part,
1688                                 plane_state->address.grph.addr.low_part,
1689                                 plane_state->src_rect.x,
1690                                 plane_state->src_rect.y,
1691                                 plane_state->src_rect.width,
1692                                 plane_state->src_rect.height,
1693                                 plane_state->dst_rect.x,
1694                                 plane_state->dst_rect.y,
1695                                 plane_state->dst_rect.width,
1696                                 plane_state->dst_rect.height);
1697
1698                 DC_LOG_DC(dc->ctx->logger,
1699                                 "Pipe %d: width, height, x, y         format:%d\n"
1700                                 "viewport:%d, %d, %d, %d\n"
1701                                 "recout:  %d, %d, %d, %d\n",
1702                                 pipe_ctx->pipe_idx,
1703                                 plane_state->format,
1704                                 pipe_ctx->plane_res.scl_data.viewport.width,
1705                                 pipe_ctx->plane_res.scl_data.viewport.height,
1706                                 pipe_ctx->plane_res.scl_data.viewport.x,
1707                                 pipe_ctx->plane_res.scl_data.viewport.y,
1708                                 pipe_ctx->plane_res.scl_data.recout.width,
1709                                 pipe_ctx->plane_res.scl_data.recout.height,
1710                                 pipe_ctx->plane_res.scl_data.recout.x,
1711                                 pipe_ctx->plane_res.scl_data.recout.y);
1712                 print_rq_dlg_ttu(dc, pipe_ctx);
1713         }
1714 */
1715         if (dc->config.gpu_vm_support)
1716                 dcn10_program_pte_vm(hws, pipe_ctx->plane_res.hubp);
1717
1718         if (dc->debug.sanity_checks) {
1719                 dcn10_verify_allow_pstate_change_high(dc);
1720         }
1721 }
1722
1723 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
1724 {
1725         int i = 0;
1726         struct dpp_grph_csc_adjustment adjust;
1727         memset(&adjust, 0, sizeof(adjust));
1728         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
1729
1730
1731         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
1732                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
1733                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
1734                         adjust.temperature_matrix[i] =
1735                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
1736         }
1737
1738         pipe_ctx->plane_res.dpp->funcs->dpp_set_gamut_remap(pipe_ctx->plane_res.dpp, &adjust);
1739 }
1740
1741 static void dcn10_program_output_csc(struct dc *dc,
1742                 struct pipe_ctx *pipe_ctx,
1743                 enum dc_color_space colorspace,
1744                 uint16_t *matrix,
1745                 int opp_id)
1746 {
1747         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
1748                 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment != NULL)
1749                         pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_adjustment(pipe_ctx->plane_res.dpp, matrix);
1750         } else {
1751                 if (pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default != NULL)
1752                         pipe_ctx->plane_res.dpp->funcs->dpp_set_csc_default(pipe_ctx->plane_res.dpp, colorspace);
1753         }
1754 }
1755
1756 bool is_lower_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1757 {
1758         if (pipe_ctx->plane_state->visible)
1759                 return true;
1760         if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1761                 return true;
1762         return false;
1763 }
1764
1765 bool is_upper_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1766 {
1767         if (pipe_ctx->plane_state->visible)
1768                 return true;
1769         if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1770                 return true;
1771         return false;
1772 }
1773
1774 bool is_pipe_tree_visible(struct pipe_ctx *pipe_ctx)
1775 {
1776         if (pipe_ctx->plane_state->visible)
1777                 return true;
1778         if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe))
1779                 return true;
1780         if (pipe_ctx->bottom_pipe && is_lower_pipe_tree_visible(pipe_ctx->bottom_pipe))
1781                 return true;
1782         return false;
1783 }
1784
1785 bool is_rgb_cspace(enum dc_color_space output_color_space)
1786 {
1787         switch (output_color_space) {
1788         case COLOR_SPACE_SRGB:
1789         case COLOR_SPACE_SRGB_LIMITED:
1790         case COLOR_SPACE_2020_RGB_FULLRANGE:
1791         case COLOR_SPACE_2020_RGB_LIMITEDRANGE:
1792         case COLOR_SPACE_ADOBERGB:
1793                 return true;
1794         case COLOR_SPACE_YCBCR601:
1795         case COLOR_SPACE_YCBCR709:
1796         case COLOR_SPACE_YCBCR601_LIMITED:
1797         case COLOR_SPACE_YCBCR709_LIMITED:
1798         case COLOR_SPACE_2020_YCBCR:
1799                 return false;
1800         default:
1801                 /* Add a case to switch */
1802                 BREAK_TO_DEBUGGER();
1803                 return false;
1804         }
1805 }
1806
1807 void dcn10_get_surface_visual_confirm_color(
1808                 const struct pipe_ctx *pipe_ctx,
1809                 struct tg_color *color)
1810 {
1811         uint32_t color_value = MAX_TG_COLOR_VALUE;
1812
1813         switch (pipe_ctx->plane_res.scl_data.format) {
1814         case PIXEL_FORMAT_ARGB8888:
1815                 /* set boarder color to red */
1816                 color->color_r_cr = color_value;
1817                 break;
1818
1819         case PIXEL_FORMAT_ARGB2101010:
1820                 /* set boarder color to blue */
1821                 color->color_b_cb = color_value;
1822                 break;
1823         case PIXEL_FORMAT_420BPP8:
1824                 /* set boarder color to green */
1825                 color->color_g_y = color_value;
1826                 break;
1827         case PIXEL_FORMAT_420BPP10:
1828                 /* set boarder color to yellow */
1829                 color->color_g_y = color_value;
1830                 color->color_r_cr = color_value;
1831                 break;
1832         case PIXEL_FORMAT_FP16:
1833                 /* set boarder color to white */
1834                 color->color_r_cr = color_value;
1835                 color->color_b_cb = color_value;
1836                 color->color_g_y = color_value;
1837                 break;
1838         default:
1839                 break;
1840         }
1841 }
1842
1843 void dcn10_get_hdr_visual_confirm_color(
1844                 struct pipe_ctx *pipe_ctx,
1845                 struct tg_color *color)
1846 {
1847         uint32_t color_value = MAX_TG_COLOR_VALUE;
1848
1849         // Determine the overscan color based on the top-most (desktop) plane's context
1850         struct pipe_ctx *top_pipe_ctx  = pipe_ctx;
1851
1852         while (top_pipe_ctx->top_pipe != NULL)
1853                 top_pipe_ctx = top_pipe_ctx->top_pipe;
1854
1855         switch (top_pipe_ctx->plane_res.scl_data.format) {
1856         case PIXEL_FORMAT_ARGB2101010:
1857                 if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_UNITY) {
1858                         /* HDR10, ARGB2101010 - set boarder color to red */
1859                         color->color_r_cr = color_value;
1860                 }
1861                 break;
1862         case PIXEL_FORMAT_FP16:
1863                 if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_PQ) {
1864                         /* HDR10, FP16 - set boarder color to blue */
1865                         color->color_b_cb = color_value;
1866                 } else if (top_pipe_ctx->stream->out_transfer_func->tf == TRANSFER_FUNCTION_GAMMA22) {
1867                         /* FreeSync 2 HDR - set boarder color to green */
1868                         color->color_g_y = color_value;
1869                 }
1870                 break;
1871         default:
1872                 /* SDR - set boarder color to Gray */
1873                 color->color_r_cr = color_value/2;
1874                 color->color_b_cb = color_value/2;
1875                 color->color_g_y = color_value/2;
1876                 break;
1877         }
1878 }
1879
1880 static uint16_t fixed_point_to_int_frac(
1881         struct fixed31_32 arg,
1882         uint8_t integer_bits,
1883         uint8_t fractional_bits)
1884 {
1885         int32_t numerator;
1886         int32_t divisor = 1 << fractional_bits;
1887
1888         uint16_t result;
1889
1890         uint16_t d = (uint16_t)dc_fixpt_floor(
1891                 dc_fixpt_abs(
1892                         arg));
1893
1894         if (d <= (uint16_t)(1 << integer_bits) - (1 / (uint16_t)divisor))
1895                 numerator = (uint16_t)dc_fixpt_floor(
1896                         dc_fixpt_mul_int(
1897                                 arg,
1898                                 divisor));
1899         else {
1900                 numerator = dc_fixpt_floor(
1901                         dc_fixpt_sub(
1902                                 dc_fixpt_from_int(
1903                                         1LL << integer_bits),
1904                                 dc_fixpt_recip(
1905                                         dc_fixpt_from_int(
1906                                                 divisor))));
1907         }
1908
1909         if (numerator >= 0)
1910                 result = (uint16_t)numerator;
1911         else
1912                 result = (uint16_t)(
1913                 (1 << (integer_bits + fractional_bits + 1)) + numerator);
1914
1915         if ((result != 0) && dc_fixpt_lt(
1916                 arg, dc_fixpt_zero))
1917                 result |= 1 << (integer_bits + fractional_bits);
1918
1919         return result;
1920 }
1921
1922 void build_prescale_params(struct  dc_bias_and_scale *bias_and_scale,
1923                 const struct dc_plane_state *plane_state)
1924 {
1925         if (plane_state->format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN
1926                         && plane_state->format != SURFACE_PIXEL_FORMAT_INVALID
1927                         && plane_state->input_csc_color_matrix.enable_adjustment
1928                         && plane_state->coeff_reduction_factor.value != 0) {
1929                 bias_and_scale->scale_blue = fixed_point_to_int_frac(
1930                         dc_fixpt_mul(plane_state->coeff_reduction_factor,
1931                                         dc_fixpt_from_fraction(256, 255)),
1932                                 2,
1933                                 13);
1934                 bias_and_scale->scale_red = bias_and_scale->scale_blue;
1935                 bias_and_scale->scale_green = bias_and_scale->scale_blue;
1936         } else {
1937                 bias_and_scale->scale_blue = 0x2000;
1938                 bias_and_scale->scale_red = 0x2000;
1939                 bias_and_scale->scale_green = 0x2000;
1940         }
1941 }
1942
1943 static void update_dpp(struct dpp *dpp, struct dc_plane_state *plane_state)
1944 {
1945         struct dc_bias_and_scale bns_params = {0};
1946
1947         // program the input csc
1948         dpp->funcs->dpp_setup(dpp,
1949                         plane_state->format,
1950                         EXPANSION_MODE_ZERO,
1951                         plane_state->input_csc_color_matrix,
1952                         COLOR_SPACE_YCBCR601_LIMITED);
1953
1954         //set scale and bias registers
1955         build_prescale_params(&bns_params, plane_state);
1956         if (dpp->funcs->dpp_program_bias_and_scale)
1957                 dpp->funcs->dpp_program_bias_and_scale(dpp, &bns_params);
1958 }
1959
1960 static void dcn10_update_mpcc(struct dc *dc, struct pipe_ctx *pipe_ctx)
1961 {
1962         struct hubp *hubp = pipe_ctx->plane_res.hubp;
1963         struct mpcc_blnd_cfg blnd_cfg = {{0}};
1964         bool per_pixel_alpha = pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
1965         int mpcc_id;
1966         struct mpcc *new_mpcc;
1967         struct mpc *mpc = dc->res_pool->mpc;
1968         struct mpc_tree *mpc_tree_params = &(pipe_ctx->stream_res.opp->mpc_tree_params);
1969
1970         if (dc->debug.visual_confirm == VISUAL_CONFIRM_HDR) {
1971                 dcn10_get_hdr_visual_confirm_color(
1972                                 pipe_ctx, &blnd_cfg.black_color);
1973         } else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) {
1974                 dcn10_get_surface_visual_confirm_color(
1975                                 pipe_ctx, &blnd_cfg.black_color);
1976         } else {
1977                 color_space_to_black_color(
1978                                 dc, pipe_ctx->stream->output_color_space,
1979                                 &blnd_cfg.black_color);
1980         }
1981
1982         if (per_pixel_alpha)
1983                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_PER_PIXEL_ALPHA;
1984         else
1985                 blnd_cfg.alpha_mode = MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA;
1986
1987         blnd_cfg.overlap_only = false;
1988         blnd_cfg.global_gain = 0xff;
1989
1990         if (pipe_ctx->plane_state->global_alpha)
1991                 blnd_cfg.global_alpha = pipe_ctx->plane_state->global_alpha_value;
1992         else
1993                 blnd_cfg.global_alpha = 0xff;
1994
1995         /* DCN1.0 has output CM before MPC which seems to screw with
1996          * pre-multiplied alpha.
1997          */
1998         blnd_cfg.pre_multiplied_alpha = is_rgb_cspace(
1999                         pipe_ctx->stream->output_color_space)
2000                                         && per_pixel_alpha;
2001
2002
2003         /*
2004          * TODO: remove hack
2005          * Note: currently there is a bug in init_hw such that
2006          * on resume from hibernate, BIOS sets up MPCC0, and
2007          * we do mpcc_remove but the mpcc cannot go to idle
2008          * after remove. This cause us to pick mpcc1 here,
2009          * which causes a pstate hang for yet unknown reason.
2010          */
2011         mpcc_id = hubp->inst;
2012
2013         /* If there is no full update, don't need to touch MPC tree*/
2014         if (!pipe_ctx->plane_state->update_flags.bits.full_update) {
2015                 mpc->funcs->update_blending(mpc, &blnd_cfg, mpcc_id);
2016                 return;
2017         }
2018
2019         /* check if this MPCC is already being used */
2020         new_mpcc = mpc->funcs->get_mpcc_for_dpp(mpc_tree_params, mpcc_id);
2021         /* remove MPCC if being used */
2022         if (new_mpcc != NULL)
2023                 mpc->funcs->remove_mpcc(mpc, mpc_tree_params, new_mpcc);
2024         else
2025                 if (dc->debug.sanity_checks)
2026                         mpc->funcs->assert_mpcc_idle_before_connect(
2027                                         dc->res_pool->mpc, mpcc_id);
2028
2029         /* Call MPC to insert new plane */
2030         new_mpcc = mpc->funcs->insert_plane(dc->res_pool->mpc,
2031                         mpc_tree_params,
2032                         &blnd_cfg,
2033                         NULL,
2034                         NULL,
2035                         hubp->inst,
2036                         mpcc_id);
2037
2038         ASSERT(new_mpcc != NULL);
2039
2040         hubp->opp_id = pipe_ctx->stream_res.opp->inst;
2041         hubp->mpcc_id = mpcc_id;
2042 }
2043
2044 static void update_scaler(struct pipe_ctx *pipe_ctx)
2045 {
2046         bool per_pixel_alpha =
2047                         pipe_ctx->plane_state->per_pixel_alpha && pipe_ctx->bottom_pipe;
2048
2049         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha;
2050         pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP;
2051         /* scaler configuration */
2052         pipe_ctx->plane_res.dpp->funcs->dpp_set_scaler(
2053                         pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data);
2054 }
2055
2056 void update_dchubp_dpp(
2057         struct dc *dc,
2058         struct pipe_ctx *pipe_ctx,
2059         struct dc_state *context)
2060 {
2061         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2062         struct dpp *dpp = pipe_ctx->plane_res.dpp;
2063         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2064         union plane_size size = plane_state->plane_size;
2065         unsigned int compat_level = 0;
2066
2067         /* depends on DML calculation, DPP clock value may change dynamically */
2068         /* If request max dpp clk is lower than current dispclk, no need to
2069          * divided by 2
2070          */
2071         if (plane_state->update_flags.bits.full_update) {
2072                 bool should_divided_by_2 = context->bw.dcn.clk.dppclk_khz <=
2073                                 dc->res_pool->clk_mgr->clks.dispclk_khz / 2;
2074
2075                 dpp->funcs->dpp_dppclk_control(
2076                                 dpp,
2077                                 should_divided_by_2,
2078                                 true);
2079
2080                 if (dc->res_pool->dccg)
2081                         dc->res_pool->dccg->funcs->update_dpp_dto(
2082                                         dc->res_pool->dccg,
2083                                         dpp->inst,
2084                                         pipe_ctx->plane_res.bw.dppclk_khz);
2085                 else
2086                         dc->res_pool->clk_mgr->clks.dppclk_khz = should_divided_by_2 ?
2087                                                 dc->res_pool->clk_mgr->clks.dispclk_khz / 2 :
2088                                                         dc->res_pool->clk_mgr->clks.dispclk_khz;
2089         }
2090
2091         /* TODO: Need input parameter to tell current DCHUB pipe tie to which OTG
2092          * VTG is within DCHUBBUB which is commond block share by each pipe HUBP.
2093          * VTG is 1:1 mapping with OTG. Each pipe HUBP will select which VTG
2094          */
2095         if (plane_state->update_flags.bits.full_update) {
2096                 hubp->funcs->hubp_vtg_sel(hubp, pipe_ctx->stream_res.tg->inst);
2097
2098                 hubp->funcs->hubp_setup(
2099                         hubp,
2100                         &pipe_ctx->dlg_regs,
2101                         &pipe_ctx->ttu_regs,
2102                         &pipe_ctx->rq_regs,
2103                         &pipe_ctx->pipe_dlg_param);
2104                 hubp->funcs->hubp_setup_interdependent(
2105                         hubp,
2106                         &pipe_ctx->dlg_regs,
2107                         &pipe_ctx->ttu_regs);
2108         }
2109
2110         size.grph.surface_size = pipe_ctx->plane_res.scl_data.viewport;
2111
2112         if (plane_state->update_flags.bits.full_update ||
2113                 plane_state->update_flags.bits.bpp_change)
2114                 update_dpp(dpp, plane_state);
2115
2116         if (plane_state->update_flags.bits.full_update ||
2117                 plane_state->update_flags.bits.per_pixel_alpha_change ||
2118                 plane_state->update_flags.bits.global_alpha_change)
2119                 dc->hwss.update_mpcc(dc, pipe_ctx);
2120
2121         if (plane_state->update_flags.bits.full_update ||
2122                 plane_state->update_flags.bits.per_pixel_alpha_change ||
2123                 plane_state->update_flags.bits.global_alpha_change ||
2124                 plane_state->update_flags.bits.scaling_change ||
2125                 plane_state->update_flags.bits.position_change) {
2126                 update_scaler(pipe_ctx);
2127         }
2128
2129         if (plane_state->update_flags.bits.full_update ||
2130                 plane_state->update_flags.bits.scaling_change ||
2131                 plane_state->update_flags.bits.position_change) {
2132                 hubp->funcs->mem_program_viewport(
2133                         hubp,
2134                         &pipe_ctx->plane_res.scl_data.viewport,
2135                         &pipe_ctx->plane_res.scl_data.viewport_c);
2136         }
2137
2138         if (pipe_ctx->stream->cursor_attributes.address.quad_part != 0) {
2139                 dc->hwss.set_cursor_position(pipe_ctx);
2140                 dc->hwss.set_cursor_attribute(pipe_ctx);
2141         }
2142
2143         if (plane_state->update_flags.bits.full_update) {
2144                 /*gamut remap*/
2145                 program_gamut_remap(pipe_ctx);
2146
2147                 dc->hwss.program_output_csc(dc,
2148                                 pipe_ctx,
2149                                 pipe_ctx->stream->output_color_space,
2150                                 pipe_ctx->stream->csc_color_matrix.matrix,
2151                                 hubp->opp_id);
2152         }
2153
2154         if (plane_state->update_flags.bits.full_update ||
2155                 plane_state->update_flags.bits.pixel_format_change ||
2156                 plane_state->update_flags.bits.horizontal_mirror_change ||
2157                 plane_state->update_flags.bits.rotation_change ||
2158                 plane_state->update_flags.bits.swizzle_change ||
2159                 plane_state->update_flags.bits.dcc_change ||
2160                 plane_state->update_flags.bits.bpp_change ||
2161                 plane_state->update_flags.bits.scaling_change ||
2162                 plane_state->update_flags.bits.plane_size_change) {
2163                 hubp->funcs->hubp_program_surface_config(
2164                         hubp,
2165                         plane_state->format,
2166                         &plane_state->tiling_info,
2167                         &size,
2168                         plane_state->rotation,
2169                         &plane_state->dcc,
2170                         plane_state->horizontal_mirror,
2171                         compat_level);
2172         }
2173
2174         hubp->power_gated = false;
2175
2176         dc->hwss.update_plane_addr(dc, pipe_ctx);
2177
2178         if (is_pipe_tree_visible(pipe_ctx))
2179                 hubp->funcs->set_blank(hubp, false);
2180 }
2181
2182 static void dcn10_blank_pixel_data(
2183                 struct dc *dc,
2184                 struct pipe_ctx *pipe_ctx,
2185                 bool blank)
2186 {
2187         enum dc_color_space color_space;
2188         struct tg_color black_color = {0};
2189         struct stream_resource *stream_res = &pipe_ctx->stream_res;
2190         struct dc_stream_state *stream = pipe_ctx->stream;
2191
2192         /* program otg blank color */
2193         color_space = stream->output_color_space;
2194         color_space_to_black_color(dc, color_space, &black_color);
2195
2196         /*
2197          * The way 420 is packed, 2 channels carry Y component, 1 channel
2198          * alternate between Cb and Cr, so both channels need the pixel
2199          * value for Y
2200          */
2201         if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
2202                 black_color.color_r_cr = black_color.color_g_y;
2203
2204
2205         if (stream_res->tg->funcs->set_blank_color)
2206                 stream_res->tg->funcs->set_blank_color(
2207                                 stream_res->tg,
2208                                 &black_color);
2209
2210         if (!blank) {
2211                 if (stream_res->tg->funcs->set_blank)
2212                         stream_res->tg->funcs->set_blank(stream_res->tg, blank);
2213                 if (stream_res->abm) {
2214                         stream_res->abm->funcs->set_pipe(stream_res->abm, stream_res->tg->inst + 1);
2215                         stream_res->abm->funcs->set_abm_level(stream_res->abm, stream->abm_level);
2216                 }
2217         } else if (blank) {
2218                 if (stream_res->abm)
2219                         stream_res->abm->funcs->set_abm_immediate_disable(stream_res->abm);
2220                 if (stream_res->tg->funcs->set_blank)
2221                         stream_res->tg->funcs->set_blank(stream_res->tg, blank);
2222         }
2223 }
2224
2225 void set_hdr_multiplier(struct pipe_ctx *pipe_ctx)
2226 {
2227         struct fixed31_32 multiplier = dc_fixpt_from_fraction(
2228                         pipe_ctx->plane_state->sdr_white_level, 80);
2229         uint32_t hw_mult = 0x1f000; // 1.0 default multiplier
2230         struct custom_float_format fmt;
2231
2232         fmt.exponenta_bits = 6;
2233         fmt.mantissa_bits = 12;
2234         fmt.sign = true;
2235
2236         if (pipe_ctx->plane_state->sdr_white_level > 80)
2237                 convert_to_custom_float_format(multiplier, &fmt, &hw_mult);
2238
2239         pipe_ctx->plane_res.dpp->funcs->dpp_set_hdr_multiplier(
2240                         pipe_ctx->plane_res.dpp, hw_mult);
2241 }
2242
2243 void dcn10_program_pipe(
2244                 struct dc *dc,
2245                 struct pipe_ctx *pipe_ctx,
2246                 struct dc_state *context)
2247 {
2248         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2249                 dcn10_enable_plane(dc, pipe_ctx, context);
2250
2251         update_dchubp_dpp(dc, pipe_ctx, context);
2252
2253         set_hdr_multiplier(pipe_ctx);
2254
2255         if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2256                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2257                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
2258                 dc->hwss.set_input_transfer_func(pipe_ctx, pipe_ctx->plane_state);
2259
2260         /* dcn10_translate_regamma_to_hw_format takes 750us to finish
2261          * only do gamma programming for full update.
2262          * TODO: This can be further optimized/cleaned up
2263          * Always call this for now since it does memcmp inside before
2264          * doing heavy calculation and programming
2265          */
2266         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2267                 dc->hwss.set_output_transfer_func(pipe_ctx, pipe_ctx->stream);
2268 }
2269
2270 static void program_all_pipe_in_tree(
2271                 struct dc *dc,
2272                 struct pipe_ctx *pipe_ctx,
2273                 struct dc_state *context)
2274 {
2275         if (pipe_ctx->top_pipe == NULL) {
2276                 bool blank = !is_pipe_tree_visible(pipe_ctx);
2277
2278                 pipe_ctx->stream_res.tg->dlg_otg_param.vready_offset = pipe_ctx->pipe_dlg_param.vready_offset;
2279                 pipe_ctx->stream_res.tg->dlg_otg_param.vstartup_start = pipe_ctx->pipe_dlg_param.vstartup_start;
2280                 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_offset = pipe_ctx->pipe_dlg_param.vupdate_offset;
2281                 pipe_ctx->stream_res.tg->dlg_otg_param.vupdate_width = pipe_ctx->pipe_dlg_param.vupdate_width;
2282                 pipe_ctx->stream_res.tg->dlg_otg_param.signal =  pipe_ctx->stream->signal;
2283
2284                 pipe_ctx->stream_res.tg->funcs->program_global_sync(
2285                                 pipe_ctx->stream_res.tg);
2286
2287                 dc->hwss.blank_pixel_data(dc, pipe_ctx, blank);
2288
2289         }
2290
2291         if (pipe_ctx->plane_state != NULL)
2292                 dcn10_program_pipe(dc, pipe_ctx, context);
2293
2294         if (pipe_ctx->bottom_pipe != NULL && pipe_ctx->bottom_pipe != pipe_ctx)
2295                 program_all_pipe_in_tree(dc, pipe_ctx->bottom_pipe, context);
2296 }
2297
2298 struct pipe_ctx *find_top_pipe_for_stream(
2299                 struct dc *dc,
2300                 struct dc_state *context,
2301                 const struct dc_stream_state *stream)
2302 {
2303         int i;
2304
2305         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2306                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2307                 struct pipe_ctx *old_pipe_ctx =
2308                                 &dc->current_state->res_ctx.pipe_ctx[i];
2309
2310                 if (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state)
2311                         continue;
2312
2313                 if (pipe_ctx->stream != stream)
2314                         continue;
2315
2316                 if (!pipe_ctx->top_pipe)
2317                         return pipe_ctx;
2318         }
2319         return NULL;
2320 }
2321
2322 static void dcn10_apply_ctx_for_surface(
2323                 struct dc *dc,
2324                 const struct dc_stream_state *stream,
2325                 int num_planes,
2326                 struct dc_state *context)
2327 {
2328         int i;
2329         struct timing_generator *tg;
2330         bool removed_pipe[4] = { false };
2331         struct pipe_ctx *top_pipe_to_program =
2332                         find_top_pipe_for_stream(dc, context, stream);
2333         DC_LOGGER_INIT(dc->ctx->logger);
2334
2335         if (!top_pipe_to_program)
2336                 return;
2337
2338         tg = top_pipe_to_program->stream_res.tg;
2339
2340         dcn10_pipe_control_lock(dc, top_pipe_to_program, true);
2341
2342         if (num_planes == 0) {
2343                 /* OTG blank before remove all front end */
2344                 dc->hwss.blank_pixel_data(dc, top_pipe_to_program, true);
2345         }
2346
2347         /* Disconnect unused mpcc */
2348         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2349                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2350                 struct pipe_ctx *old_pipe_ctx =
2351                                 &dc->current_state->res_ctx.pipe_ctx[i];
2352                 /*
2353                  * Powergate reused pipes that are not powergated
2354                  * fairly hacky right now, using opp_id as indicator
2355                  * TODO: After move dc_post to dc_update, this will
2356                  * be removed.
2357                  */
2358                 if (pipe_ctx->plane_state && !old_pipe_ctx->plane_state) {
2359                         if (old_pipe_ctx->stream_res.tg == tg &&
2360                                 old_pipe_ctx->plane_res.hubp &&
2361                                 old_pipe_ctx->plane_res.hubp->opp_id != 0xf) {
2362                                 dcn10_disable_plane(dc, old_pipe_ctx);
2363                                 /*
2364                                  * power down fe will unlock when calling reset, need
2365                                  * to lock it back here. Messy, need rework.
2366                                  */
2367                                 pipe_ctx->stream_res.tg->funcs->lock(pipe_ctx->stream_res.tg);
2368                         }
2369                 }
2370
2371                 if ((!pipe_ctx->plane_state ||
2372                      pipe_ctx->stream_res.tg != old_pipe_ctx->stream_res.tg) &&
2373                     old_pipe_ctx->plane_state &&
2374                     old_pipe_ctx->stream_res.tg == tg) {
2375
2376                         dc->hwss.plane_atomic_disconnect(dc, old_pipe_ctx);
2377                         removed_pipe[i] = true;
2378
2379                         DC_LOG_DC("Reset mpcc for pipe %d\n",
2380                                         old_pipe_ctx->pipe_idx);
2381                 }
2382         }
2383
2384         if (num_planes > 0)
2385                 program_all_pipe_in_tree(dc, top_pipe_to_program, context);
2386
2387         dcn10_pipe_control_lock(dc, top_pipe_to_program, false);
2388
2389         if (top_pipe_to_program->plane_state &&
2390                         top_pipe_to_program->plane_state->update_flags.bits.full_update)
2391                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2392                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2393                         tg = pipe_ctx->stream_res.tg;
2394                         /* Skip inactive pipes and ones already updated */
2395                         if (!pipe_ctx->stream || pipe_ctx->stream == stream
2396                                         || !pipe_ctx->plane_state
2397                                         || !tg->funcs->is_tg_enabled(tg))
2398                                 continue;
2399
2400                         tg->funcs->lock(tg);
2401
2402                         pipe_ctx->plane_res.hubp->funcs->hubp_setup_interdependent(
2403                                 pipe_ctx->plane_res.hubp,
2404                                 &pipe_ctx->dlg_regs,
2405                                 &pipe_ctx->ttu_regs);
2406
2407                         tg->funcs->unlock(tg);
2408                 }
2409
2410         if (num_planes == 0)
2411                 false_optc_underflow_wa(dc, stream, tg);
2412
2413         for (i = 0; i < dc->res_pool->pipe_count; i++)
2414                 if (removed_pipe[i])
2415                         dcn10_disable_plane(dc, &dc->current_state->res_ctx.pipe_ctx[i]);
2416
2417         if (dc->hwseq->wa.DEGVIDCN10_254)
2418                 hubbub1_wm_change_req_wa(dc->res_pool->hubbub);
2419 }
2420
2421 static void dcn10_stereo_hw_frame_pack_wa(struct dc *dc, struct dc_state *context)
2422 {
2423         uint8_t i;
2424
2425         for (i = 0; i < context->stream_count; i++) {
2426                 if (context->streams[i]->timing.timing_3d_format
2427                                 == TIMING_3D_FORMAT_HW_FRAME_PACKING) {
2428                         /*
2429                          * Disable stutter
2430                          */
2431                         hubbub1_allow_self_refresh_control(dc->res_pool->hubbub, false);
2432                         break;
2433                 }
2434         }
2435 }
2436
2437 static void dcn10_prepare_bandwidth(
2438                 struct dc *dc,
2439                 struct dc_state *context)
2440 {
2441         if (dc->debug.sanity_checks)
2442                 dcn10_verify_allow_pstate_change_high(dc);
2443
2444         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2445                 if (context->stream_count == 0)
2446                         context->bw.dcn.clk.phyclk_khz = 0;
2447
2448                 dc->res_pool->clk_mgr->funcs->update_clocks(
2449                                 dc->res_pool->clk_mgr,
2450                                 context,
2451                                 false);
2452         }
2453
2454         hubbub1_program_watermarks(dc->res_pool->hubbub,
2455                         &context->bw.dcn.watermarks,
2456                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
2457                         true);
2458         dcn10_stereo_hw_frame_pack_wa(dc, context);
2459
2460         if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
2461                 dcn_bw_notify_pplib_of_wm_ranges(dc);
2462
2463         if (dc->debug.sanity_checks)
2464                 dcn10_verify_allow_pstate_change_high(dc);
2465 }
2466
2467 static void dcn10_optimize_bandwidth(
2468                 struct dc *dc,
2469                 struct dc_state *context)
2470 {
2471         if (dc->debug.sanity_checks)
2472                 dcn10_verify_allow_pstate_change_high(dc);
2473
2474         if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
2475                 if (context->stream_count == 0)
2476                         context->bw.dcn.clk.phyclk_khz = 0;
2477
2478                 dc->res_pool->clk_mgr->funcs->update_clocks(
2479                                 dc->res_pool->clk_mgr,
2480                                 context,
2481                                 true);
2482         }
2483
2484         hubbub1_program_watermarks(dc->res_pool->hubbub,
2485                         &context->bw.dcn.watermarks,
2486                         dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000,
2487                         true);
2488         dcn10_stereo_hw_frame_pack_wa(dc, context);
2489
2490         if (dc->debug.pplib_wm_report_mode == WM_REPORT_OVERRIDE)
2491                 dcn_bw_notify_pplib_of_wm_ranges(dc);
2492
2493         if (dc->debug.sanity_checks)
2494                 dcn10_verify_allow_pstate_change_high(dc);
2495 }
2496
2497 static void set_drr(struct pipe_ctx **pipe_ctx,
2498                 int num_pipes, int vmin, int vmax)
2499 {
2500         int i = 0;
2501         struct drr_params params = {0};
2502         // DRR should set trigger event to monitor surface update event
2503         unsigned int event_triggers = 0x80;
2504
2505         params.vertical_total_max = vmax;
2506         params.vertical_total_min = vmin;
2507
2508         /* TODO: If multiple pipes are to be supported, you need
2509          * some GSL stuff. Static screen triggers may be programmed differently
2510          * as well.
2511          */
2512         for (i = 0; i < num_pipes; i++) {
2513                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
2514                         pipe_ctx[i]->stream_res.tg, &params);
2515                 if (vmax != 0 && vmin != 0)
2516                         pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
2517                                         pipe_ctx[i]->stream_res.tg,
2518                                         event_triggers);
2519         }
2520 }
2521
2522 static void get_position(struct pipe_ctx **pipe_ctx,
2523                 int num_pipes,
2524                 struct crtc_position *position)
2525 {
2526         int i = 0;
2527
2528         /* TODO: handle pipes > 1
2529          */
2530         for (i = 0; i < num_pipes; i++)
2531                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
2532 }
2533
2534 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
2535                 int num_pipes, const struct dc_static_screen_events *events)
2536 {
2537         unsigned int i;
2538         unsigned int value = 0;
2539
2540         if (events->surface_update)
2541                 value |= 0x80;
2542         if (events->cursor_update)
2543                 value |= 0x2;
2544         if (events->force_trigger)
2545                 value |= 0x1;
2546
2547         for (i = 0; i < num_pipes; i++)
2548                 pipe_ctx[i]->stream_res.tg->funcs->
2549                         set_static_screen_control(pipe_ctx[i]->stream_res.tg, value);
2550 }
2551
2552 static void dcn10_config_stereo_parameters(
2553                 struct dc_stream_state *stream, struct crtc_stereo_flags *flags)
2554 {
2555         enum view_3d_format view_format = stream->view_format;
2556         enum dc_timing_3d_format timing_3d_format =\
2557                         stream->timing.timing_3d_format;
2558         bool non_stereo_timing = false;
2559
2560         if (timing_3d_format == TIMING_3D_FORMAT_NONE ||
2561                 timing_3d_format == TIMING_3D_FORMAT_SIDE_BY_SIDE ||
2562                 timing_3d_format == TIMING_3D_FORMAT_TOP_AND_BOTTOM)
2563                 non_stereo_timing = true;
2564
2565         if (non_stereo_timing == false &&
2566                 view_format == VIEW_3D_FORMAT_FRAME_SEQUENTIAL) {
2567
2568                 flags->PROGRAM_STEREO         = 1;
2569                 flags->PROGRAM_POLARITY       = 1;
2570                 if (timing_3d_format == TIMING_3D_FORMAT_INBAND_FA ||
2571                         timing_3d_format == TIMING_3D_FORMAT_DP_HDMI_INBAND_FA ||
2572                         timing_3d_format == TIMING_3D_FORMAT_SIDEBAND_FA) {
2573                         enum display_dongle_type dongle = \
2574                                         stream->link->ddc->dongle_type;
2575                         if (dongle == DISPLAY_DONGLE_DP_VGA_CONVERTER ||
2576                                 dongle == DISPLAY_DONGLE_DP_DVI_CONVERTER ||
2577                                 dongle == DISPLAY_DONGLE_DP_HDMI_CONVERTER)
2578                                 flags->DISABLE_STEREO_DP_SYNC = 1;
2579                 }
2580                 flags->RIGHT_EYE_POLARITY =\
2581                                 stream->timing.flags.RIGHT_EYE_3D_POLARITY;
2582                 if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
2583                         flags->FRAME_PACKED = 1;
2584         }
2585
2586         return;
2587 }
2588
2589 static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct dc *dc)
2590 {
2591         struct crtc_stereo_flags flags = { 0 };
2592         struct dc_stream_state *stream = pipe_ctx->stream;
2593
2594         dcn10_config_stereo_parameters(stream, &flags);
2595
2596         pipe_ctx->stream_res.opp->funcs->opp_program_stereo(
2597                 pipe_ctx->stream_res.opp,
2598                 flags.PROGRAM_STEREO == 1 ? true:false,
2599                 &stream->timing);
2600
2601         pipe_ctx->stream_res.tg->funcs->program_stereo(
2602                 pipe_ctx->stream_res.tg,
2603                 &stream->timing,
2604                 &flags);
2605
2606         return;
2607 }
2608
2609 static struct hubp *get_hubp_by_inst(struct resource_pool *res_pool, int mpcc_inst)
2610 {
2611         int i;
2612
2613         for (i = 0; i < res_pool->pipe_count; i++) {
2614                 if (res_pool->hubps[i]->inst == mpcc_inst)
2615                         return res_pool->hubps[i];
2616         }
2617         ASSERT(false);
2618         return NULL;
2619 }
2620
2621 static void dcn10_wait_for_mpcc_disconnect(
2622                 struct dc *dc,
2623                 struct resource_pool *res_pool,
2624                 struct pipe_ctx *pipe_ctx)
2625 {
2626         int mpcc_inst;
2627
2628         if (dc->debug.sanity_checks) {
2629                 dcn10_verify_allow_pstate_change_high(dc);
2630         }
2631
2632         if (!pipe_ctx->stream_res.opp)
2633                 return;
2634
2635         for (mpcc_inst = 0; mpcc_inst < MAX_PIPES; mpcc_inst++) {
2636                 if (pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst]) {
2637                         struct hubp *hubp = get_hubp_by_inst(res_pool, mpcc_inst);
2638
2639                         res_pool->mpc->funcs->wait_for_idle(res_pool->mpc, mpcc_inst);
2640                         pipe_ctx->stream_res.opp->mpcc_disconnect_pending[mpcc_inst] = false;
2641                         hubp->funcs->set_blank(hubp, true);
2642                         /*DC_LOG_ERROR(dc->ctx->logger,
2643                                         "[debug_mpo: wait_for_mpcc finished waiting on mpcc %d]\n",
2644                                         i);*/
2645                 }
2646         }
2647
2648         if (dc->debug.sanity_checks) {
2649                 dcn10_verify_allow_pstate_change_high(dc);
2650         }
2651
2652 }
2653
2654 static bool dcn10_dummy_display_power_gating(
2655         struct dc *dc,
2656         uint8_t controller_id,
2657         struct dc_bios *dcb,
2658         enum pipe_gating_control power_gating)
2659 {
2660         return true;
2661 }
2662
2663 static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx)
2664 {
2665         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2666         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2667         bool flip_pending;
2668
2669         if (plane_state == NULL)
2670                 return;
2671
2672         flip_pending = pipe_ctx->plane_res.hubp->funcs->hubp_is_flip_pending(
2673                                         pipe_ctx->plane_res.hubp);
2674
2675         plane_state->status.is_flip_pending = plane_state->status.is_flip_pending || flip_pending;
2676
2677         if (!flip_pending)
2678                 plane_state->status.current_address = plane_state->status.requested_address;
2679
2680         if (plane_state->status.current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2681                         tg->funcs->is_stereo_left_eye) {
2682                 plane_state->status.is_right_eye =
2683                                 !tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2684         }
2685 }
2686
2687 static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)
2688 {
2689         if (hws->ctx->dc->res_pool->hubbub != NULL) {
2690                 struct hubp *hubp = hws->ctx->dc->res_pool->hubps[0];
2691
2692                 if (hubp->funcs->hubp_update_dchub)
2693                         hubp->funcs->hubp_update_dchub(hubp, dh_data);
2694                 else
2695                         hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);
2696         }
2697 }
2698
2699 static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)
2700 {
2701         struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2702         struct hubp *hubp = pipe_ctx->plane_res.hubp;
2703         struct dpp *dpp = pipe_ctx->plane_res.dpp;
2704         struct dc_cursor_mi_param param = {
2705                 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
2706                 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.dchub_ref_clock_inKhz,
2707                 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2708                 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2709                 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2710                 .rotation = pipe_ctx->plane_state->rotation,
2711                 .mirror = pipe_ctx->plane_state->horizontal_mirror
2712         };
2713
2714         pos_cpy.x_hotspot += pipe_ctx->plane_state->dst_rect.x;
2715         pos_cpy.y_hotspot += pipe_ctx->plane_state->dst_rect.y;
2716
2717         if (pipe_ctx->plane_state->address.type
2718                         == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2719                 pos_cpy.enable = false;
2720
2721         hubp->funcs->set_cursor_position(hubp, &pos_cpy, &param);
2722         dpp->funcs->set_cursor_position(dpp, &pos_cpy, &param, hubp->curs_attr.width, hubp->curs_attr.height);
2723 }
2724
2725 static void dcn10_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2726 {
2727         struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2728
2729         pipe_ctx->plane_res.hubp->funcs->set_cursor_attributes(
2730                         pipe_ctx->plane_res.hubp, attributes);
2731         pipe_ctx->plane_res.dpp->funcs->set_cursor_attributes(
2732                 pipe_ctx->plane_res.dpp, attributes->color_format);
2733 }
2734
2735 static void dcn10_set_cursor_sdr_white_level(struct pipe_ctx *pipe_ctx)
2736 {
2737         uint32_t sdr_white_level = pipe_ctx->stream->cursor_attributes.sdr_white_level;
2738         struct fixed31_32 multiplier;
2739         struct dpp_cursor_attributes opt_attr = { 0 };
2740         uint32_t hw_scale = 0x3c00; // 1.0 default multiplier
2741         struct custom_float_format fmt;
2742
2743         if (!pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes)
2744                 return;
2745
2746         fmt.exponenta_bits = 5;
2747         fmt.mantissa_bits = 10;
2748         fmt.sign = true;
2749
2750         if (sdr_white_level > 80) {
2751                 multiplier = dc_fixpt_from_fraction(sdr_white_level, 80);
2752                 convert_to_custom_float_format(multiplier, &fmt, &hw_scale);
2753         }
2754
2755         opt_attr.scale = hw_scale;
2756         opt_attr.bias = 0;
2757
2758         pipe_ctx->plane_res.dpp->funcs->set_optional_cursor_attributes(
2759                         pipe_ctx->plane_res.dpp, &opt_attr);
2760 }
2761
2762 /**
2763 * apply_front_porch_workaround  TODO FPGA still need?
2764 *
2765 * This is a workaround for a bug that has existed since R5xx and has not been
2766 * fixed keep Front porch at minimum 2 for Interlaced mode or 1 for progressive.
2767 */
2768 static void apply_front_porch_workaround(
2769         struct dc_crtc_timing *timing)
2770 {
2771         if (timing->flags.INTERLACE == 1) {
2772                 if (timing->v_front_porch < 2)
2773                         timing->v_front_porch = 2;
2774         } else {
2775                 if (timing->v_front_porch < 1)
2776                         timing->v_front_porch = 1;
2777         }
2778 }
2779
2780 int get_vupdate_offset_from_vsync(struct pipe_ctx *pipe_ctx)
2781 {
2782         struct timing_generator *optc = pipe_ctx->stream_res.tg;
2783         const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;
2784         struct dc_crtc_timing patched_crtc_timing;
2785         int vesa_sync_start;
2786         int asic_blank_end;
2787         int interlace_factor;
2788         int vertical_line_start;
2789
2790         patched_crtc_timing = *dc_crtc_timing;
2791         apply_front_porch_workaround(&patched_crtc_timing);
2792
2793         interlace_factor = patched_crtc_timing.flags.INTERLACE ? 2 : 1;
2794
2795         vesa_sync_start = patched_crtc_timing.v_addressable +
2796                         patched_crtc_timing.v_border_bottom +
2797                         patched_crtc_timing.v_front_porch;
2798
2799         asic_blank_end = (patched_crtc_timing.v_total -
2800                         vesa_sync_start -
2801                         patched_crtc_timing.v_border_top)
2802                         * interlace_factor;
2803
2804         vertical_line_start = asic_blank_end -
2805                         optc->dlg_otg_param.vstartup_start + 1;
2806
2807         return vertical_line_start;
2808 }
2809
2810 static void calc_vupdate_position(
2811                 struct pipe_ctx *pipe_ctx,
2812                 uint32_t *start_line,
2813                 uint32_t *end_line)
2814 {
2815         const struct dc_crtc_timing *dc_crtc_timing = &pipe_ctx->stream->timing;
2816         int vline_int_offset_from_vupdate =
2817                         pipe_ctx->stream->periodic_interrupt0.lines_offset;
2818         int vupdate_offset_from_vsync = get_vupdate_offset_from_vsync(pipe_ctx);
2819         int start_position;
2820
2821         if (vline_int_offset_from_vupdate > 0)
2822                 vline_int_offset_from_vupdate--;
2823         else if (vline_int_offset_from_vupdate < 0)
2824                 vline_int_offset_from_vupdate++;
2825
2826         start_position = vline_int_offset_from_vupdate + vupdate_offset_from_vsync;
2827
2828         if (start_position >= 0)
2829                 *start_line = start_position;
2830         else
2831                 *start_line = dc_crtc_timing->v_total + start_position - 1;
2832
2833         *end_line = *start_line + 2;
2834
2835         if (*end_line >= dc_crtc_timing->v_total)
2836                 *end_line = 2;
2837 }
2838
2839 static void cal_vline_position(
2840                 struct pipe_ctx *pipe_ctx,
2841                 enum vline_select vline,
2842                 uint32_t *start_line,
2843                 uint32_t *end_line)
2844 {
2845         enum vertical_interrupt_ref_point ref_point = INVALID_POINT;
2846
2847         if (vline == VLINE0)
2848                 ref_point = pipe_ctx->stream->periodic_interrupt0.ref_point;
2849         else if (vline == VLINE1)
2850                 ref_point = pipe_ctx->stream->periodic_interrupt1.ref_point;
2851
2852         switch (ref_point) {
2853         case START_V_UPDATE:
2854                 calc_vupdate_position(
2855                                 pipe_ctx,
2856                                 start_line,
2857                                 end_line);
2858                 break;
2859         case START_V_SYNC:
2860                 // Suppose to do nothing because vsync is 0;
2861                 break;
2862         default:
2863                 ASSERT(0);
2864                 break;
2865         }
2866 }
2867
2868 static void dcn10_setup_periodic_interrupt(
2869                 struct pipe_ctx *pipe_ctx,
2870                 enum vline_select vline)
2871 {
2872         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2873
2874         if (vline == VLINE0) {
2875                 uint32_t start_line = 0;
2876                 uint32_t end_line = 0;
2877
2878                 cal_vline_position(pipe_ctx, vline, &start_line, &end_line);
2879
2880                 tg->funcs->setup_vertical_interrupt0(tg, start_line, end_line);
2881
2882         } else if (vline == VLINE1) {
2883                 pipe_ctx->stream_res.tg->funcs->setup_vertical_interrupt1(
2884                                 tg,
2885                                 pipe_ctx->stream->periodic_interrupt1.lines_offset);
2886         }
2887 }
2888
2889 static void dcn10_setup_vupdate_interrupt(struct pipe_ctx *pipe_ctx)
2890 {
2891         struct timing_generator *tg = pipe_ctx->stream_res.tg;
2892         int start_line = get_vupdate_offset_from_vsync(pipe_ctx);
2893
2894         if (start_line < 0) {
2895                 ASSERT(0);
2896                 start_line = 0;
2897         }
2898
2899         if (tg->funcs->setup_vertical_interrupt2)
2900                 tg->funcs->setup_vertical_interrupt2(tg, start_line);
2901 }
2902
2903 static void dcn10_unblank_stream(struct pipe_ctx *pipe_ctx,
2904                 struct dc_link_settings *link_settings)
2905 {
2906         struct encoder_unblank_param params = { { 0 } };
2907         struct dc_stream_state *stream = pipe_ctx->stream;
2908         struct dc_link *link = stream->link;
2909
2910         /* only 3 items below are used by unblank */
2911         params.timing = pipe_ctx->stream->timing;
2912
2913         params.link_settings.link_rate = link_settings->link_rate;
2914
2915         if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
2916                 if (params.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
2917                         params.timing.pix_clk_100hz /= 2;
2918                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
2919         }
2920
2921         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
2922                 link->dc->hwss.edp_backlight_control(link, true);
2923         }
2924 }
2925
2926 static const struct hw_sequencer_funcs dcn10_funcs = {
2927         .program_gamut_remap = program_gamut_remap,
2928         .init_hw = dcn10_init_hw,
2929         .init_pipes = dcn10_init_pipes,
2930         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2931         .apply_ctx_for_surface = dcn10_apply_ctx_for_surface,
2932         .update_plane_addr = dcn10_update_plane_addr,
2933         .plane_atomic_disconnect = hwss1_plane_atomic_disconnect,
2934         .update_dchub = dcn10_update_dchub,
2935         .update_mpcc = dcn10_update_mpcc,
2936         .update_pending_status = dcn10_update_pending_status,
2937         .set_input_transfer_func = dcn10_set_input_transfer_func,
2938         .set_output_transfer_func = dcn10_set_output_transfer_func,
2939         .program_output_csc = dcn10_program_output_csc,
2940         .power_down = dce110_power_down,
2941         .enable_accelerated_mode = dce110_enable_accelerated_mode,
2942         .enable_timing_synchronization = dcn10_enable_timing_synchronization,
2943         .enable_per_frame_crtc_position_reset = dcn10_enable_per_frame_crtc_position_reset,
2944         .update_info_frame = dce110_update_info_frame,
2945         .enable_stream = dce110_enable_stream,
2946         .disable_stream = dce110_disable_stream,
2947         .unblank_stream = dcn10_unblank_stream,
2948         .blank_stream = dce110_blank_stream,
2949         .enable_audio_stream = dce110_enable_audio_stream,
2950         .disable_audio_stream = dce110_disable_audio_stream,
2951         .enable_display_power_gating = dcn10_dummy_display_power_gating,
2952         .disable_plane = dcn10_disable_plane,
2953         .blank_pixel_data = dcn10_blank_pixel_data,
2954         .pipe_control_lock = dcn10_pipe_control_lock,
2955         .prepare_bandwidth = dcn10_prepare_bandwidth,
2956         .optimize_bandwidth = dcn10_optimize_bandwidth,
2957         .reset_hw_ctx_wrap = dcn10_reset_hw_ctx_wrap,
2958         .enable_stream_timing = dcn10_enable_stream_timing,
2959         .set_drr = set_drr,
2960         .get_position = get_position,
2961         .set_static_screen_control = set_static_screen_control,
2962         .setup_stereo = dcn10_setup_stereo,
2963         .set_avmute = dce110_set_avmute,
2964         .log_hw_state = dcn10_log_hw_state,
2965         .get_hw_state = dcn10_get_hw_state,
2966         .clear_status_bits = dcn10_clear_status_bits,
2967         .wait_for_mpcc_disconnect = dcn10_wait_for_mpcc_disconnect,
2968         .edp_backlight_control = hwss_edp_backlight_control,
2969         .edp_power_control = hwss_edp_power_control,
2970         .edp_wait_for_hpd_ready = hwss_edp_wait_for_hpd_ready,
2971         .set_cursor_position = dcn10_set_cursor_position,
2972         .set_cursor_attribute = dcn10_set_cursor_attribute,
2973         .set_cursor_sdr_white_level = dcn10_set_cursor_sdr_white_level,
2974         .disable_stream_gating = NULL,
2975         .enable_stream_gating = NULL,
2976         .setup_periodic_interrupt = dcn10_setup_periodic_interrupt,
2977         .setup_vupdate_interrupt = dcn10_setup_vupdate_interrupt
2978 };
2979
2980
2981 void dcn10_hw_sequencer_construct(struct dc *dc)
2982 {
2983         dc->hwss = dcn10_funcs;
2984 }
2985