drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c

   1 /*
   2 * Copyright 2012-15 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include "dm_services.h"
  27
  28 #include "link_encoder.h"
  29 #include "stream_encoder.h"
  30
  31 #include "resource.h"
  32 #include "include/irq_service_interface.h"
  33 #include "dce110/dce110_resource.h"
  34 #include "dce110/dce110_timing_generator.h"
  35
  36 #include "irq/dce110/irq_service_dce110.h"
  37
  38 #include "dce/dce_mem_input.h"
  39 #include "dce/dce_transform.h"
  40 #include "dce/dce_link_encoder.h"
  41 #include "dce/dce_stream_encoder.h"
  42 #include "dce/dce_audio.h"
  43 #include "dce/dce_opp.h"
  44 #include "dce/dce_ipp.h"
  45 #include "dce/dce_clocks.h"
  46 #include "dce/dce_clock_source.h"
  47
  48 #include "dce/dce_hwseq.h"
  49 #include "dce112/dce112_hw_sequencer.h"
  50 #include "dce/dce_abm.h"
  51 #include "dce/dce_dmcu.h"
  52 #include "dce/dce_aux.h"
  53 #include "dce/dce_i2c.h"
  54
  55 #include "reg_helper.h"
  56
  57 #include "dce/dce_11_2_d.h"
  58 #include "dce/dce_11_2_sh_mask.h"
  59
  60 #include "dce100/dce100_resource.h"
  61 #define DC_LOGGER \
  62                 dc->ctx->logger
  63
  64 #ifndef mmDP_DPHY_INTERNAL_CTRL
  65         #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
  66         #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
  67         #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
  68         #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
  69         #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
  70         #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
  71         #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
  72         #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
  73         #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
  74         #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
  75 #endif
  76
  77 #ifndef mmBIOS_SCRATCH_2
  78         #define mmBIOS_SCRATCH_2 0x05CB
  79         #define mmBIOS_SCRATCH_6 0x05CF
  80 #endif
  81
  82 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
  83         #define mmDP_DPHY_BS_SR_SWAP_CNTL                       0x4ADC
  84         #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL                   0x4ADC
  85         #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL                   0x4BDC
  86         #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL                   0x4CDC
  87         #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL                   0x4DDC
  88         #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL                   0x4EDC
  89         #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL                   0x4FDC
  90         #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL                   0x54DC
  91 #endif
  92
  93 #ifndef mmDP_DPHY_FAST_TRAINING
  94         #define mmDP_DPHY_FAST_TRAINING                         0x4ABC
  95         #define mmDP0_DP_DPHY_FAST_TRAINING                     0x4ABC
  96         #define mmDP1_DP_DPHY_FAST_TRAINING                     0x4BBC
  97         #define mmDP2_DP_DPHY_FAST_TRAINING                     0x4CBC
  98         #define mmDP3_DP_DPHY_FAST_TRAINING                     0x4DBC
  99         #define mmDP4_DP_DPHY_FAST_TRAINING                     0x4EBC
 100         #define mmDP5_DP_DPHY_FAST_TRAINING                     0x4FBC
 101         #define mmDP6_DP_DPHY_FAST_TRAINING                     0x54BC
 102 #endif
 103
 104 enum dce112_clk_src_array_id {
 105         DCE112_CLK_SRC_PLL0,
 106         DCE112_CLK_SRC_PLL1,
 107         DCE112_CLK_SRC_PLL2,
 108         DCE112_CLK_SRC_PLL3,
 109         DCE112_CLK_SRC_PLL4,
 110         DCE112_CLK_SRC_PLL5,
 111
 112         DCE112_CLK_SRC_TOTAL
 113 };
 114
 115 static const struct dce110_timing_generator_offsets dce112_tg_offsets[] = {
 116         {
 117                 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
 118                 .dcp =  (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
 119         },
 120         {
 121                 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
 122                 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
 123         },
 124         {
 125                 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
 126                 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
 127         },
 128         {
 129                 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
 130                 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
 131         },
 132         {
 133                 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
 134                 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
 135         },
 136         {
 137                 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
 138                 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
 139         }
 140 };
 141
 142 /* set register offset */
 143 #define SR(reg_name)\
 144         .reg_name = mm ## reg_name
 145
 146 /* set register offset with instance */
 147 #define SRI(reg_name, block, id)\
 148         .reg_name = mm ## block ## id ## _ ## reg_name
 149
 150
 151 static const struct dccg_registers disp_clk_regs = {
 152                 CLK_COMMON_REG_LIST_DCE_BASE()
 153 };
 154
 155 static const struct dccg_shift disp_clk_shift = {
 156                 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 157 };
 158
 159 static const struct dccg_mask disp_clk_mask = {
 160                 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 161 };
 162
 163 static const struct dce_dmcu_registers dmcu_regs = {
 164                 DMCU_DCE110_COMMON_REG_LIST()
 165 };
 166
 167 static const struct dce_dmcu_shift dmcu_shift = {
 168                 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
 169 };
 170
 171 static const struct dce_dmcu_mask dmcu_mask = {
 172                 DMCU_MASK_SH_LIST_DCE110(_MASK)
 173 };
 174
 175 static const struct dce_abm_registers abm_regs = {
 176                 ABM_DCE110_COMMON_REG_LIST()
 177 };
 178
 179 static const struct dce_abm_shift abm_shift = {
 180                 ABM_MASK_SH_LIST_DCE110(__SHIFT)
 181 };
 182
 183 static const struct dce_abm_mask abm_mask = {
 184                 ABM_MASK_SH_LIST_DCE110(_MASK)
 185 };
 186
 187 #define ipp_regs(id)\
 188 [id] = {\
 189                 IPP_DCE110_REG_LIST_DCE_BASE(id)\
 190 }
 191
 192 static const struct dce_ipp_registers ipp_regs[] = {
 193                 ipp_regs(0),
 194                 ipp_regs(1),
 195                 ipp_regs(2),
 196                 ipp_regs(3),
 197                 ipp_regs(4),
 198                 ipp_regs(5)
 199 };
 200
 201 static const struct dce_ipp_shift ipp_shift = {
 202                 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
 203 };
 204
 205 static const struct dce_ipp_mask ipp_mask = {
 206                 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
 207 };
 208
 209 #define transform_regs(id)\
 210 [id] = {\
 211                 XFM_COMMON_REG_LIST_DCE110(id)\
 212 }
 213
 214 static const struct dce_transform_registers xfm_regs[] = {
 215                 transform_regs(0),
 216                 transform_regs(1),
 217                 transform_regs(2),
 218                 transform_regs(3),
 219                 transform_regs(4),
 220                 transform_regs(5)
 221 };
 222
 223 static const struct dce_transform_shift xfm_shift = {
 224                 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
 225 };
 226
 227 static const struct dce_transform_mask xfm_mask = {
 228                 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
 229 };
 230
 231 #define aux_regs(id)\
 232 [id] = {\
 233         AUX_REG_LIST(id)\
 234 }
 235
 236 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
 237                 aux_regs(0),
 238                 aux_regs(1),
 239                 aux_regs(2),
 240                 aux_regs(3),
 241                 aux_regs(4),
 242                 aux_regs(5)
 243 };
 244
 245 #define hpd_regs(id)\
 246 [id] = {\
 247         HPD_REG_LIST(id)\
 248 }
 249
 250 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
 251                 hpd_regs(0),
 252                 hpd_regs(1),
 253                 hpd_regs(2),
 254                 hpd_regs(3),
 255                 hpd_regs(4),
 256                 hpd_regs(5)
 257 };
 258
 259 #define link_regs(id)\
 260 [id] = {\
 261         LE_DCE110_REG_LIST(id)\
 262 }
 263
 264 static const struct dce110_link_enc_registers link_enc_regs[] = {
 265         link_regs(0),
 266         link_regs(1),
 267         link_regs(2),
 268         link_regs(3),
 269         link_regs(4),
 270         link_regs(5),
 271         link_regs(6),
 272 };
 273
 274 #define stream_enc_regs(id)\
 275 [id] = {\
 276         SE_COMMON_REG_LIST(id),\
 277         .TMDS_CNTL = 0,\
 278 }
 279
 280 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
 281         stream_enc_regs(0),
 282         stream_enc_regs(1),
 283         stream_enc_regs(2),
 284         stream_enc_regs(3),
 285         stream_enc_regs(4),
 286         stream_enc_regs(5)
 287 };
 288
 289 static const struct dce_stream_encoder_shift se_shift = {
 290                 SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT)
 291 };
 292
 293 static const struct dce_stream_encoder_mask se_mask = {
 294                 SE_COMMON_MASK_SH_LIST_DCE112(_MASK)
 295 };
 296
 297 #define opp_regs(id)\
 298 [id] = {\
 299         OPP_DCE_112_REG_LIST(id),\
 300 }
 301
 302 static const struct dce_opp_registers opp_regs[] = {
 303         opp_regs(0),
 304         opp_regs(1),
 305         opp_regs(2),
 306         opp_regs(3),
 307         opp_regs(4),
 308         opp_regs(5)
 309 };
 310
 311 static const struct dce_opp_shift opp_shift = {
 312         OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
 313 };
 314
 315 static const struct dce_opp_mask opp_mask = {
 316         OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK)
 317 };
 318
 319 #define aux_engine_regs(id)\
 320 [id] = {\
 321         AUX_COMMON_REG_LIST(id), \
 322         .AUX_RESET_MASK = 0 \
 323 }
 324
 325 static const struct dce110_aux_registers aux_engine_regs[] = {
 326                 aux_engine_regs(0),
 327                 aux_engine_regs(1),
 328                 aux_engine_regs(2),
 329                 aux_engine_regs(3),
 330                 aux_engine_regs(4),
 331                 aux_engine_regs(5)
 332 };
 333
 334 #define audio_regs(id)\
 335 [id] = {\
 336         AUD_COMMON_REG_LIST(id)\
 337 }
 338
 339 static const struct dce_audio_registers audio_regs[] = {
 340         audio_regs(0),
 341         audio_regs(1),
 342         audio_regs(2),
 343         audio_regs(3),
 344         audio_regs(4),
 345         audio_regs(5)
 346 };
 347
 348 static const struct dce_audio_shift audio_shift = {
 349                 AUD_COMMON_MASK_SH_LIST(__SHIFT)
 350 };
 351
 352 static const struct dce_aduio_mask audio_mask = {
 353                 AUD_COMMON_MASK_SH_LIST(_MASK)
 354 };
 355
 356 #define clk_src_regs(index, id)\
 357 [index] = {\
 358         CS_COMMON_REG_LIST_DCE_112(id),\
 359 }
 360
 361 static const struct dce110_clk_src_regs clk_src_regs[] = {
 362         clk_src_regs(0, A),
 363         clk_src_regs(1, B),
 364         clk_src_regs(2, C),
 365         clk_src_regs(3, D),
 366         clk_src_regs(4, E),
 367         clk_src_regs(5, F)
 368 };
 369
 370 static const struct dce110_clk_src_shift cs_shift = {
 371                 CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT)
 372 };
 373
 374 static const struct dce110_clk_src_mask cs_mask = {
 375                 CS_COMMON_MASK_SH_LIST_DCE_112(_MASK)
 376 };
 377
 378 static const struct bios_registers bios_regs = {
 379         .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
 380 };
 381
 382 static const struct resource_caps polaris_10_resource_cap = {
 383                 .num_timing_generator = 6,
 384                 .num_audio = 6,
 385                 .num_stream_encoder = 6,
 386                 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
 387                 .num_ddc = 6,
 388 };
 389
 390 static const struct resource_caps polaris_11_resource_cap = {
 391                 .num_timing_generator = 5,
 392                 .num_audio = 5,
 393                 .num_stream_encoder = 5,
 394                 .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
 395                 .num_ddc = 5,
 396 };
 397
 398 #define CTX  ctx
 399 #define REG(reg) mm ## reg
 400
 401 #ifndef mmCC_DC_HDMI_STRAPS
 402 #define mmCC_DC_HDMI_STRAPS 0x4819
 403 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
 404 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
 405 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
 406 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
 407 #endif
 408
 409 static void read_dce_straps(
 410         struct dc_context *ctx,
 411         struct resource_straps *straps)
 412 {
 413         REG_GET_2(CC_DC_HDMI_STRAPS,
 414                         HDMI_DISABLE, &straps->hdmi_disable,
 415                         AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
 416
 417         REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
 418 }
 419
 420 static struct audio *create_audio(
 421                 struct dc_context *ctx, unsigned int inst)
 422 {
 423         return dce_audio_create(ctx, inst,
 424                         &audio_regs[inst], &audio_shift, &audio_mask);
 425 }
 426
 427
 428 static struct timing_generator *dce112_timing_generator_create(
 429                 struct dc_context *ctx,
 430                 uint32_t instance,
 431                 const struct dce110_timing_generator_offsets *offsets)
 432 {
 433         struct dce110_timing_generator *tg110 =
 434                 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
 435
 436         if (!tg110)
 437                 return NULL;
 438
 439         dce110_timing_generator_construct(tg110, ctx, instance, offsets);
 440         return &tg110->base;
 441 }
 442
 443 static struct stream_encoder *dce112_stream_encoder_create(
 444         enum engine_id eng_id,
 445         struct dc_context *ctx)
 446 {
 447         struct dce110_stream_encoder *enc110 =
 448                 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
 449
 450         if (!enc110)
 451                 return NULL;
 452
 453         dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
 454                                         &stream_enc_regs[eng_id],
 455                                         &se_shift, &se_mask);
 456         return &enc110->base;
 457 }
 458
 459 #define SRII(reg_name, block, id)\
 460         .reg_name[id] = mm ## block ## id ## _ ## reg_name
 461
 462 static const struct dce_hwseq_registers hwseq_reg = {
 463                 HWSEQ_DCE112_REG_LIST()
 464 };
 465
 466 static const struct dce_hwseq_shift hwseq_shift = {
 467                 HWSEQ_DCE112_MASK_SH_LIST(__SHIFT)
 468 };
 469
 470 static const struct dce_hwseq_mask hwseq_mask = {
 471                 HWSEQ_DCE112_MASK_SH_LIST(_MASK)
 472 };
 473
 474 static struct dce_hwseq *dce112_hwseq_create(
 475         struct dc_context *ctx)
 476 {
 477         struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
 478
 479         if (hws) {
 480                 hws->ctx = ctx;
 481                 hws->regs = &hwseq_reg;
 482                 hws->shifts = &hwseq_shift;
 483                 hws->masks = &hwseq_mask;
 484         }
 485         return hws;
 486 }
 487
 488 static const struct resource_create_funcs res_create_funcs = {
 489         .read_dce_straps = read_dce_straps,
 490         .create_audio = create_audio,
 491         .create_stream_encoder = dce112_stream_encoder_create,
 492         .create_hwseq = dce112_hwseq_create,
 493 };
 494
 495 #define mi_inst_regs(id) { MI_DCE11_2_REG_LIST(id) }
 496 static const struct dce_mem_input_registers mi_regs[] = {
 497                 mi_inst_regs(0),
 498                 mi_inst_regs(1),
 499                 mi_inst_regs(2),
 500                 mi_inst_regs(3),
 501                 mi_inst_regs(4),
 502                 mi_inst_regs(5),
 503 };
 504
 505 static const struct dce_mem_input_shift mi_shifts = {
 506                 MI_DCE11_2_MASK_SH_LIST(__SHIFT)
 507 };
 508
 509 static const struct dce_mem_input_mask mi_masks = {
 510                 MI_DCE11_2_MASK_SH_LIST(_MASK)
 511 };
 512
 513 static struct mem_input *dce112_mem_input_create(
 514         struct dc_context *ctx,
 515         uint32_t inst)
 516 {
 517         struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
 518                                                GFP_KERNEL);
 519
 520         if (!dce_mi) {
 521                 BREAK_TO_DEBUGGER();
 522                 return NULL;
 523         }
 524
 525         dce112_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
 526         return &dce_mi->base;
 527 }
 528
 529 static void dce112_transform_destroy(struct transform **xfm)
 530 {
 531         kfree(TO_DCE_TRANSFORM(*xfm));
 532         *xfm = NULL;
 533 }
 534
 535 static struct transform *dce112_transform_create(
 536         struct dc_context *ctx,
 537         uint32_t inst)
 538 {
 539         struct dce_transform *transform =
 540                 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
 541
 542         if (!transform)
 543                 return NULL;
 544
 545         dce_transform_construct(transform, ctx, inst,
 546                                 &xfm_regs[inst], &xfm_shift, &xfm_mask);
 547         transform->lb_memory_size = 0x1404; /*5124*/
 548         return &transform->base;
 549 }
 550
 551 static const struct encoder_feature_support link_enc_feature = {
 552                 .max_hdmi_deep_color = COLOR_DEPTH_121212,
 553                 .max_hdmi_pixel_clock = 600000,
 554                 .ycbcr420_supported = true,
 555                 .flags.bits.IS_HBR2_CAPABLE = true,
 556                 .flags.bits.IS_HBR3_CAPABLE = true,
 557                 .flags.bits.IS_TPS3_CAPABLE = true,
 558                 .flags.bits.IS_TPS4_CAPABLE = true
 559 };
 560
 561 struct link_encoder *dce112_link_encoder_create(
 562         const struct encoder_init_data *enc_init_data)
 563 {
 564         struct dce110_link_encoder *enc110 =
 565                 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
 566
 567         if (!enc110)
 568                 return NULL;
 569
 570         dce110_link_encoder_construct(enc110,
 571                                       enc_init_data,
 572                                       &link_enc_feature,
 573                                       &link_enc_regs[enc_init_data->transmitter],
 574                                       &link_enc_aux_regs[enc_init_data->channel - 1],
 575                                       &link_enc_hpd_regs[enc_init_data->hpd_source]);
 576         return &enc110->base;
 577 }
 578
 579 static struct input_pixel_processor *dce112_ipp_create(
 580         struct dc_context *ctx, uint32_t inst)
 581 {
 582         struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
 583
 584         if (!ipp) {
 585                 BREAK_TO_DEBUGGER();
 586                 return NULL;
 587         }
 588
 589         dce_ipp_construct(ipp, ctx, inst,
 590                         &ipp_regs[inst], &ipp_shift, &ipp_mask);
 591         return &ipp->base;
 592 }
 593
 594 struct output_pixel_processor *dce112_opp_create(
 595         struct dc_context *ctx,
 596         uint32_t inst)
 597 {
 598         struct dce110_opp *opp =
 599                 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
 600
 601         if (!opp)
 602                 return NULL;
 603
 604         dce110_opp_construct(opp,
 605                              ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
 606         return &opp->base;
 607 }
 608
 609 struct aux_engine *dce112_aux_engine_create(
 610         struct dc_context *ctx,
 611         uint32_t inst)
 612 {
 613         struct aux_engine_dce110 *aux_engine =
 614                 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
 615
 616         if (!aux_engine)
 617                 return NULL;
 618
 619         dce110_aux_engine_construct(aux_engine, ctx, inst,
 620                                     SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
 621                                     &aux_engine_regs[inst]);
 622
 623         return &aux_engine->base;
 624 }
 625 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
 626
 627 static const struct dce_i2c_registers i2c_hw_regs[] = {
 628                 i2c_inst_regs(1),
 629                 i2c_inst_regs(2),
 630                 i2c_inst_regs(3),
 631                 i2c_inst_regs(4),
 632                 i2c_inst_regs(5),
 633                 i2c_inst_regs(6),
 634 };
 635
 636 static const struct dce_i2c_shift i2c_shifts = {
 637                 I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
 638 };
 639
 640 static const struct dce_i2c_mask i2c_masks = {
 641                 I2C_COMMON_MASK_SH_LIST_DCE110(_MASK)
 642 };
 643
 644 struct dce_i2c_hw *dce112_i2c_hw_create(
 645         struct dc_context *ctx,
 646         uint32_t inst)
 647 {
 648         struct dce_i2c_hw *dce_i2c_hw =
 649                 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
 650
 651         if (!dce_i2c_hw)
 652                 return NULL;
 653
 654         dce112_i2c_hw_construct(dce_i2c_hw, ctx, inst,
 655                                     &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
 656
 657         return dce_i2c_hw;
 658 }
 659 struct clock_source *dce112_clock_source_create(
 660         struct dc_context *ctx,
 661         struct dc_bios *bios,
 662         enum clock_source_id id,
 663         const struct dce110_clk_src_regs *regs,
 664         bool dp_clk_src)
 665 {
 666         struct dce110_clk_src *clk_src =
 667                 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
 668
 669         if (!clk_src)
 670                 return NULL;
 671
 672         if (dce112_clk_src_construct(clk_src, ctx, bios, id,
 673                         regs, &cs_shift, &cs_mask)) {
 674                 clk_src->base.dp_clk_src = dp_clk_src;
 675                 return &clk_src->base;
 676         }
 677
 678         BREAK_TO_DEBUGGER();
 679         return NULL;
 680 }
 681
 682 void dce112_clock_source_destroy(struct clock_source **clk_src)
 683 {
 684         kfree(TO_DCE110_CLK_SRC(*clk_src));
 685         *clk_src = NULL;
 686 }
 687
 688 static void destruct(struct dce110_resource_pool *pool)
 689 {
 690         unsigned int i;
 691
 692         for (i = 0; i < pool->base.pipe_count; i++) {
 693                 if (pool->base.opps[i] != NULL)
 694                         dce110_opp_destroy(&pool->base.opps[i]);
 695
 696                 if (pool->base.engines[i] != NULL)
 697                         dce110_engine_destroy(&pool->base.engines[i]);
 698
 699                 if (pool->base.transforms[i] != NULL)
 700                         dce112_transform_destroy(&pool->base.transforms[i]);
 701
 702                 if (pool->base.ipps[i] != NULL)
 703                         dce_ipp_destroy(&pool->base.ipps[i]);
 704
 705                 if (pool->base.mis[i] != NULL) {
 706                         kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
 707                         pool->base.mis[i] = NULL;
 708                 }
 709
 710                 if (pool->base.timing_generators[i] != NULL) {
 711                         kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
 712                         pool->base.timing_generators[i] = NULL;
 713                 }
 714                 if (pool->base.hw_i2cs[i] != NULL) {
 715                         kfree(pool->base.hw_i2cs[i]);
 716                         pool->base.hw_i2cs[i] = NULL;
 717                 }
 718                 if (pool->base.sw_i2cs[i] != NULL) {
 719                         kfree(pool->base.sw_i2cs[i]);
 720                         pool->base.sw_i2cs[i] = NULL;
 721                 }
 722         }
 723
 724         for (i = 0; i < pool->base.stream_enc_count; i++) {
 725                 if (pool->base.stream_enc[i] != NULL)
 726                         kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
 727         }
 728
 729         for (i = 0; i < pool->base.clk_src_count; i++) {
 730                 if (pool->base.clock_sources[i] != NULL) {
 731                         dce112_clock_source_destroy(&pool->base.clock_sources[i]);
 732                 }
 733         }
 734
 735         if (pool->base.dp_clock_source != NULL)
 736                 dce112_clock_source_destroy(&pool->base.dp_clock_source);
 737
 738         for (i = 0; i < pool->base.audio_count; i++)    {
 739                 if (pool->base.audios[i] != NULL) {
 740                         dce_aud_destroy(&pool->base.audios[i]);
 741                 }
 742         }
 743
 744         if (pool->base.abm != NULL)
 745                 dce_abm_destroy(&pool->base.abm);
 746
 747         if (pool->base.dmcu != NULL)
 748                 dce_dmcu_destroy(&pool->base.dmcu);
 749
 750         if (pool->base.dccg != NULL)
 751                 dce_dccg_destroy(&pool->base.dccg);
 752
 753         if (pool->base.irqs != NULL) {
 754                 dal_irq_service_destroy(&pool->base.irqs);
 755         }
 756 }
 757
 758 static struct clock_source *find_matching_pll(
 759                 struct resource_context *res_ctx,
 760                 const struct resource_pool *pool,
 761                 const struct dc_stream_state *const stream)
 762 {
 763         switch (stream->sink->link->link_enc->transmitter) {
 764         case TRANSMITTER_UNIPHY_A:
 765                 return pool->clock_sources[DCE112_CLK_SRC_PLL0];
 766         case TRANSMITTER_UNIPHY_B:
 767                 return pool->clock_sources[DCE112_CLK_SRC_PLL1];
 768         case TRANSMITTER_UNIPHY_C:
 769                 return pool->clock_sources[DCE112_CLK_SRC_PLL2];
 770         case TRANSMITTER_UNIPHY_D:
 771                 return pool->clock_sources[DCE112_CLK_SRC_PLL3];
 772         case TRANSMITTER_UNIPHY_E:
 773                 return pool->clock_sources[DCE112_CLK_SRC_PLL4];
 774         case TRANSMITTER_UNIPHY_F:
 775                 return pool->clock_sources[DCE112_CLK_SRC_PLL5];
 776         default:
 777                 return NULL;
 778         };
 779
 780         return 0;
 781 }
 782
 783 static enum dc_status build_mapped_resource(
 784                 const struct dc *dc,
 785                 struct dc_state *context,
 786                 struct dc_stream_state *stream)
 787 {
 788         struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
 789
 790         if (!pipe_ctx)
 791                 return DC_ERROR_UNEXPECTED;
 792
 793         dce110_resource_build_pipe_hw_param(pipe_ctx);
 794
 795         resource_build_info_frame(pipe_ctx);
 796
 797         return DC_OK;
 798 }
 799
 800 bool dce112_validate_bandwidth(
 801         struct dc *dc,
 802         struct dc_state *context)
 803 {
 804         bool result = false;
 805
 806         DC_LOG_BANDWIDTH_CALCS(
 807                 "%s: start",
 808                 __func__);
 809
 810         if (bw_calcs(
 811                         dc->ctx,
 812                         dc->bw_dceip,
 813                         dc->bw_vbios,
 814                         context->res_ctx.pipe_ctx,
 815                         dc->res_pool->pipe_count,
 816                         &context->bw.dce))
 817                 result = true;
 818
 819         if (!result)
 820                 DC_LOG_BANDWIDTH_VALIDATION(
 821                         "%s: Bandwidth validation failed!",
 822                         __func__);
 823
 824         if (memcmp(&dc->current_state->bw.dce,
 825                         &context->bw.dce, sizeof(context->bw.dce))) {
 826
 827                 DC_LOG_BANDWIDTH_CALCS(
 828                         "%s: finish,\n"
 829                         "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
 830                         "stutMark_b: %d stutMark_a: %d\n"
 831                         "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
 832                         "stutMark_b: %d stutMark_a: %d\n"
 833                         "nbpMark_b: %d nbpMark_a: %d urgentMark_b: %d urgentMark_a: %d\n"
 834                         "stutMark_b: %d stutMark_a: %d stutter_mode_enable: %d\n"
 835                         "cstate: %d pstate: %d nbpstate: %d sync: %d dispclk: %d\n"
 836                         "sclk: %d sclk_sleep: %d yclk: %d blackout_recovery_time_us: %d\n"
 837                         ,
 838                         __func__,
 839                         context->bw.dce.nbp_state_change_wm_ns[0].b_mark,
 840                         context->bw.dce.nbp_state_change_wm_ns[0].a_mark,
 841                         context->bw.dce.urgent_wm_ns[0].b_mark,
 842                         context->bw.dce.urgent_wm_ns[0].a_mark,
 843                         context->bw.dce.stutter_exit_wm_ns[0].b_mark,
 844                         context->bw.dce.stutter_exit_wm_ns[0].a_mark,
 845                         context->bw.dce.nbp_state_change_wm_ns[1].b_mark,
 846                         context->bw.dce.nbp_state_change_wm_ns[1].a_mark,
 847                         context->bw.dce.urgent_wm_ns[1].b_mark,
 848                         context->bw.dce.urgent_wm_ns[1].a_mark,
 849                         context->bw.dce.stutter_exit_wm_ns[1].b_mark,
 850                         context->bw.dce.stutter_exit_wm_ns[1].a_mark,
 851                         context->bw.dce.nbp_state_change_wm_ns[2].b_mark,
 852                         context->bw.dce.nbp_state_change_wm_ns[2].a_mark,
 853                         context->bw.dce.urgent_wm_ns[2].b_mark,
 854                         context->bw.dce.urgent_wm_ns[2].a_mark,
 855                         context->bw.dce.stutter_exit_wm_ns[2].b_mark,
 856                         context->bw.dce.stutter_exit_wm_ns[2].a_mark,
 857                         context->bw.dce.stutter_mode_enable,
 858                         context->bw.dce.cpuc_state_change_enable,
 859                         context->bw.dce.cpup_state_change_enable,
 860                         context->bw.dce.nbp_state_change_enable,
 861                         context->bw.dce.all_displays_in_sync,
 862                         context->bw.dce.dispclk_khz,
 863                         context->bw.dce.sclk_khz,
 864                         context->bw.dce.sclk_deep_sleep_khz,
 865                         context->bw.dce.yclk_khz,
 866                         context->bw.dce.blackout_recovery_time_us);
 867         }
 868         return result;
 869 }
 870
 871 enum dc_status resource_map_phy_clock_resources(
 872                 const struct dc *dc,
 873                 struct dc_state *context,
 874                 struct dc_stream_state *stream)
 875 {
 876
 877         /* acquire new resources */
 878         struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(
 879                         &context->res_ctx, stream);
 880
 881         if (!pipe_ctx)
 882                 return DC_ERROR_UNEXPECTED;
 883
 884         if (dc_is_dp_signal(pipe_ctx->stream->signal)
 885                 || pipe_ctx->stream->signal == SIGNAL_TYPE_VIRTUAL)
 886                 pipe_ctx->clock_source =
 887                                 dc->res_pool->dp_clock_source;
 888         else
 889                 pipe_ctx->clock_source = find_matching_pll(
 890                         &context->res_ctx, dc->res_pool,
 891                         stream);
 892
 893         if (pipe_ctx->clock_source == NULL)
 894                 return DC_NO_CLOCK_SOURCE_RESOURCE;
 895
 896         resource_reference_clock_source(
 897                 &context->res_ctx,
 898                 dc->res_pool,
 899                 pipe_ctx->clock_source);
 900
 901         return DC_OK;
 902 }
 903
 904 static bool dce112_validate_surface_sets(
 905                 struct dc_state *context)
 906 {
 907         int i;
 908
 909         for (i = 0; i < context->stream_count; i++) {
 910                 if (context->stream_status[i].plane_count == 0)
 911                         continue;
 912
 913                 if (context->stream_status[i].plane_count > 1)
 914                         return false;
 915
 916                 if (context->stream_status[i].plane_states[0]->format
 917                                 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
 918                         return false;
 919         }
 920
 921         return true;
 922 }
 923
 924 enum dc_status dce112_add_stream_to_ctx(
 925                 struct dc *dc,
 926                 struct dc_state *new_ctx,
 927                 struct dc_stream_state *dc_stream)
 928 {
 929         enum dc_status result = DC_ERROR_UNEXPECTED;
 930
 931         result = resource_map_pool_resources(dc, new_ctx, dc_stream);
 932
 933         if (result == DC_OK)
 934                 result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
 935
 936
 937         if (result == DC_OK)
 938                 result = build_mapped_resource(dc, new_ctx, dc_stream);
 939
 940         return result;
 941 }
 942
 943 enum dc_status dce112_validate_global(
 944                 struct dc *dc,
 945                 struct dc_state *context)
 946 {
 947         if (!dce112_validate_surface_sets(context))
 948                 return DC_FAIL_SURFACE_VALIDATE;
 949
 950         return DC_OK;
 951 }
 952
 953 static void dce112_destroy_resource_pool(struct resource_pool **pool)
 954 {
 955         struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
 956
 957         destruct(dce110_pool);
 958         kfree(dce110_pool);
 959         *pool = NULL;
 960 }
 961
 962 static const struct resource_funcs dce112_res_pool_funcs = {
 963         .destroy = dce112_destroy_resource_pool,
 964         .link_enc_create = dce112_link_encoder_create,
 965         .validate_bandwidth = dce112_validate_bandwidth,
 966         .validate_plane = dce100_validate_plane,
 967         .add_stream_to_ctx = dce112_add_stream_to_ctx,
 968         .validate_global = dce112_validate_global
 969 };
 970
 971 static void bw_calcs_data_update_from_pplib(struct dc *dc)
 972 {
 973         struct dm_pp_clock_levels_with_latency eng_clks = {0};
 974         struct dm_pp_clock_levels_with_latency mem_clks = {0};
 975         struct dm_pp_wm_sets_with_clock_ranges clk_ranges = {0};
 976         struct dm_pp_clock_levels clks = {0};
 977
 978         /*do system clock  TODO PPLIB: after PPLIB implement,
 979          * then remove old way
 980          */
 981         if (!dm_pp_get_clock_levels_by_type_with_latency(
 982                         dc->ctx,
 983                         DM_PP_CLOCK_TYPE_ENGINE_CLK,
 984                         &eng_clks)) {
 985
 986                 /* This is only for temporary */
 987                 dm_pp_get_clock_levels_by_type(
 988                                 dc->ctx,
 989                                 DM_PP_CLOCK_TYPE_ENGINE_CLK,
 990                                 &clks);
 991                 /* convert all the clock fro kHz to fix point mHz */
 992                 dc->bw_vbios->high_sclk = bw_frc_to_fixed(
 993                                 clks.clocks_in_khz[clks.num_levels-1], 1000);
 994                 dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
 995                                 clks.clocks_in_khz[clks.num_levels/8], 1000);
 996                 dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
 997                                 clks.clocks_in_khz[clks.num_levels*2/8], 1000);
 998                 dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
 999                                 clks.clocks_in_khz[clks.num_levels*3/8], 1000);
1000                 dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
1001                                 clks.clocks_in_khz[clks.num_levels*4/8], 1000);
1002                 dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
1003                                 clks.clocks_in_khz[clks.num_levels*5/8], 1000);
1004                 dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
1005                                 clks.clocks_in_khz[clks.num_levels*6/8], 1000);
1006                 dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
1007                                 clks.clocks_in_khz[0], 1000);
1008
1009                 /*do memory clock*/
1010                 dm_pp_get_clock_levels_by_type(
1011                                 dc->ctx,
1012                                 DM_PP_CLOCK_TYPE_MEMORY_CLK,
1013                                 &clks);
1014
1015                 dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1016                         clks.clocks_in_khz[0] * MEMORY_TYPE_MULTIPLIER, 1000);
1017                 dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1018                         clks.clocks_in_khz[clks.num_levels>>1] * MEMORY_TYPE_MULTIPLIER,
1019                         1000);
1020                 dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1021                         clks.clocks_in_khz[clks.num_levels-1] * MEMORY_TYPE_MULTIPLIER,
1022                         1000);
1023
1024                 return;
1025         }
1026
1027         /* convert all the clock fro kHz to fix point mHz  TODO: wloop data */
1028         dc->bw_vbios->high_sclk = bw_frc_to_fixed(
1029                 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000);
1030         dc->bw_vbios->mid1_sclk  = bw_frc_to_fixed(
1031                 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000);
1032         dc->bw_vbios->mid2_sclk  = bw_frc_to_fixed(
1033                 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000);
1034         dc->bw_vbios->mid3_sclk  = bw_frc_to_fixed(
1035                 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000);
1036         dc->bw_vbios->mid4_sclk  = bw_frc_to_fixed(
1037                 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000);
1038         dc->bw_vbios->mid5_sclk  = bw_frc_to_fixed(
1039                 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000);
1040         dc->bw_vbios->mid6_sclk  = bw_frc_to_fixed(
1041                 eng_clks.data[eng_clks.num_levels*6/8].clocks_in_khz, 1000);
1042         dc->bw_vbios->low_sclk  = bw_frc_to_fixed(
1043                         eng_clks.data[0].clocks_in_khz, 1000);
1044
1045         /*do memory clock*/
1046         dm_pp_get_clock_levels_by_type_with_latency(
1047                         dc->ctx,
1048                         DM_PP_CLOCK_TYPE_MEMORY_CLK,
1049                         &mem_clks);
1050
1051         /* we don't need to call PPLIB for validation clock since they
1052          * also give us the highest sclk and highest mclk (UMA clock).
1053          * ALSO always convert UMA clock (from PPLIB)  to YCLK (HW formula):
1054          * YCLK = UMACLK*m_memoryTypeMultiplier
1055          */
1056         dc->bw_vbios->low_yclk = bw_frc_to_fixed(
1057                 mem_clks.data[0].clocks_in_khz * MEMORY_TYPE_MULTIPLIER, 1000);
1058         dc->bw_vbios->mid_yclk = bw_frc_to_fixed(
1059                 mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
1060                 1000);
1061         dc->bw_vbios->high_yclk = bw_frc_to_fixed(
1062                 mem_clks.data[mem_clks.num_levels-1].clocks_in_khz * MEMORY_TYPE_MULTIPLIER,
1063                 1000);
1064
1065         /* Now notify PPLib/SMU about which Watermarks sets they should select
1066          * depending on DPM state they are in. And update BW MGR GFX Engine and
1067          * Memory clock member variables for Watermarks calculations for each
1068          * Watermark Set
1069          */
1070         clk_ranges.num_wm_sets = 4;
1071         clk_ranges.wm_clk_ranges[0].wm_set_id = WM_SET_A;
1072         clk_ranges.wm_clk_ranges[0].wm_min_eng_clk_in_khz =
1073                         eng_clks.data[0].clocks_in_khz;
1074         clk_ranges.wm_clk_ranges[0].wm_max_eng_clk_in_khz =
1075                         eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1076         clk_ranges.wm_clk_ranges[0].wm_min_mem_clk_in_khz =
1077                         mem_clks.data[0].clocks_in_khz;
1078         clk_ranges.wm_clk_ranges[0].wm_max_mem_clk_in_khz =
1079                         mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1080
1081         clk_ranges.wm_clk_ranges[1].wm_set_id = WM_SET_B;
1082         clk_ranges.wm_clk_ranges[1].wm_min_eng_clk_in_khz =
1083                         eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1084         /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1085         clk_ranges.wm_clk_ranges[1].wm_max_eng_clk_in_khz = 5000000;
1086         clk_ranges.wm_clk_ranges[1].wm_min_mem_clk_in_khz =
1087                         mem_clks.data[0].clocks_in_khz;
1088         clk_ranges.wm_clk_ranges[1].wm_max_mem_clk_in_khz =
1089                         mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz - 1;
1090
1091         clk_ranges.wm_clk_ranges[2].wm_set_id = WM_SET_C;
1092         clk_ranges.wm_clk_ranges[2].wm_min_eng_clk_in_khz =
1093                         eng_clks.data[0].clocks_in_khz;
1094         clk_ranges.wm_clk_ranges[2].wm_max_eng_clk_in_khz =
1095                         eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz - 1;
1096         clk_ranges.wm_clk_ranges[2].wm_min_mem_clk_in_khz =
1097                         mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1098         /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1099         clk_ranges.wm_clk_ranges[2].wm_max_mem_clk_in_khz = 5000000;
1100
1101         clk_ranges.wm_clk_ranges[3].wm_set_id = WM_SET_D;
1102         clk_ranges.wm_clk_ranges[3].wm_min_eng_clk_in_khz =
1103                         eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz;
1104         /* 5 GHz instead of data[7].clockInKHz to cover Overdrive */
1105         clk_ranges.wm_clk_ranges[3].wm_max_eng_clk_in_khz = 5000000;
1106         clk_ranges.wm_clk_ranges[3].wm_min_mem_clk_in_khz =
1107                         mem_clks.data[mem_clks.num_levels>>1].clocks_in_khz;
1108         /* 5 GHz instead of data[2].clockInKHz to cover Overdrive */
1109         clk_ranges.wm_clk_ranges[3].wm_max_mem_clk_in_khz = 5000000;
1110
1111         /* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
1112         dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
1113 }
1114
1115 const struct resource_caps *dce112_resource_cap(
1116         struct hw_asic_id *asic_id)
1117 {
1118         if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev) ||
1119             ASIC_REV_IS_POLARIS12_V(asic_id->hw_internal_rev))
1120                 return &polaris_11_resource_cap;
1121         else
1122                 return &polaris_10_resource_cap;
1123 }
1124
1125 static bool construct(
1126         uint8_t num_virtual_links,
1127         struct dc *dc,
1128         struct dce110_resource_pool *pool)
1129 {
1130         unsigned int i;
1131         struct dc_context *ctx = dc->ctx;
1132         struct dm_pp_static_clock_info static_clk_info = {0};
1133
1134         ctx->dc_bios->regs = &bios_regs;
1135
1136         pool->base.res_cap = dce112_resource_cap(&ctx->asic_id);
1137         pool->base.funcs = &dce112_res_pool_funcs;
1138
1139         /*************************************************
1140          *  Resource + asic cap harcoding                *
1141          *************************************************/
1142         pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1143         pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1144         pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1145         dc->caps.max_downscale_ratio = 200;
1146         dc->caps.i2c_speed_in_khz = 100;
1147         dc->caps.max_cursor_size = 128;
1148         dc->caps.dual_link_dvi = true;
1149
1150
1151         /*************************************************
1152          *  Create resources                             *
1153          *************************************************/
1154
1155         pool->base.clock_sources[DCE112_CLK_SRC_PLL0] =
1156                         dce112_clock_source_create(
1157                                 ctx, ctx->dc_bios,
1158                                 CLOCK_SOURCE_COMBO_PHY_PLL0,
1159                                 &clk_src_regs[0], false);
1160         pool->base.clock_sources[DCE112_CLK_SRC_PLL1] =
1161                         dce112_clock_source_create(
1162                                 ctx, ctx->dc_bios,
1163                                 CLOCK_SOURCE_COMBO_PHY_PLL1,
1164                                 &clk_src_regs[1], false);
1165         pool->base.clock_sources[DCE112_CLK_SRC_PLL2] =
1166                         dce112_clock_source_create(
1167                                 ctx, ctx->dc_bios,
1168                                 CLOCK_SOURCE_COMBO_PHY_PLL2,
1169                                 &clk_src_regs[2], false);
1170         pool->base.clock_sources[DCE112_CLK_SRC_PLL3] =
1171                         dce112_clock_source_create(
1172                                 ctx, ctx->dc_bios,
1173                                 CLOCK_SOURCE_COMBO_PHY_PLL3,
1174                                 &clk_src_regs[3], false);
1175         pool->base.clock_sources[DCE112_CLK_SRC_PLL4] =
1176                         dce112_clock_source_create(
1177                                 ctx, ctx->dc_bios,
1178                                 CLOCK_SOURCE_COMBO_PHY_PLL4,
1179                                 &clk_src_regs[4], false);
1180         pool->base.clock_sources[DCE112_CLK_SRC_PLL5] =
1181                         dce112_clock_source_create(
1182                                 ctx, ctx->dc_bios,
1183                                 CLOCK_SOURCE_COMBO_PHY_PLL5,
1184                                 &clk_src_regs[5], false);
1185         pool->base.clk_src_count = DCE112_CLK_SRC_TOTAL;
1186
1187         pool->base.dp_clock_source =  dce112_clock_source_create(
1188                 ctx, ctx->dc_bios,
1189                 CLOCK_SOURCE_ID_DP_DTO, &clk_src_regs[0], true);
1190
1191
1192         for (i = 0; i < pool->base.clk_src_count; i++) {
1193                 if (pool->base.clock_sources[i] == NULL) {
1194                         dm_error("DC: failed to create clock sources!\n");
1195                         BREAK_TO_DEBUGGER();
1196                         goto res_create_fail;
1197                 }
1198         }
1199
1200         pool->base.dccg = dce112_dccg_create(ctx,
1201                         &disp_clk_regs,
1202                         &disp_clk_shift,
1203                         &disp_clk_mask);
1204         if (pool->base.dccg == NULL) {
1205                 dm_error("DC: failed to create display clock!\n");
1206                 BREAK_TO_DEBUGGER();
1207                 goto res_create_fail;
1208         }
1209
1210         pool->base.dmcu = dce_dmcu_create(ctx,
1211                         &dmcu_regs,
1212                         &dmcu_shift,
1213                         &dmcu_mask);
1214         if (pool->base.dmcu == NULL) {
1215                 dm_error("DC: failed to create dmcu!\n");
1216                 BREAK_TO_DEBUGGER();
1217                 goto res_create_fail;
1218         }
1219
1220         pool->base.abm = dce_abm_create(ctx,
1221                         &abm_regs,
1222                         &abm_shift,
1223                         &abm_mask);
1224         if (pool->base.abm == NULL) {
1225                 dm_error("DC: failed to create abm!\n");
1226                 BREAK_TO_DEBUGGER();
1227                 goto res_create_fail;
1228         }
1229
1230         /* get static clock information for PPLIB or firmware, save
1231          * max_clock_state
1232          */
1233         if (dm_pp_get_static_clocks(ctx, &static_clk_info))
1234                 pool->base.dccg->max_clks_state =
1235                                 static_clk_info.max_clocks_state;
1236
1237         {
1238                 struct irq_service_init_data init_data;
1239                 init_data.ctx = dc->ctx;
1240                 pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1241                 if (!pool->base.irqs)
1242                         goto res_create_fail;
1243         }
1244
1245         for (i = 0; i < pool->base.pipe_count; i++) {
1246                 pool->base.timing_generators[i] =
1247                                 dce112_timing_generator_create(
1248                                         ctx,
1249                                         i,
1250                                         &dce112_tg_offsets[i]);
1251                 if (pool->base.timing_generators[i] == NULL) {
1252                         BREAK_TO_DEBUGGER();
1253                         dm_error("DC: failed to create tg!\n");
1254                         goto res_create_fail;
1255                 }
1256
1257                 pool->base.mis[i] = dce112_mem_input_create(ctx, i);
1258                 if (pool->base.mis[i] == NULL) {
1259                         BREAK_TO_DEBUGGER();
1260                         dm_error(
1261                                 "DC: failed to create memory input!\n");
1262                         goto res_create_fail;
1263                 }
1264
1265                 pool->base.ipps[i] = dce112_ipp_create(ctx, i);
1266                 if (pool->base.ipps[i] == NULL) {
1267                         BREAK_TO_DEBUGGER();
1268                         dm_error(
1269                                 "DC:failed to create input pixel processor!\n");
1270                         goto res_create_fail;
1271                 }
1272
1273                 pool->base.transforms[i] = dce112_transform_create(ctx, i);
1274                 if (pool->base.transforms[i] == NULL) {
1275                         BREAK_TO_DEBUGGER();
1276                         dm_error(
1277                                 "DC: failed to create transform!\n");
1278                         goto res_create_fail;
1279                 }
1280
1281                 pool->base.opps[i] = dce112_opp_create(
1282                         ctx,
1283                         i);
1284                 if (pool->base.opps[i] == NULL) {
1285                         BREAK_TO_DEBUGGER();
1286                         dm_error(
1287                                 "DC:failed to create output pixel processor!\n");
1288                         goto res_create_fail;
1289                 }
1290         }
1291
1292         for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1293                 pool->base.engines[i] = dce112_aux_engine_create(ctx, i);
1294                 if (pool->base.engines[i] == NULL) {
1295                         BREAK_TO_DEBUGGER();
1296                         dm_error(
1297                                 "DC:failed to create aux engine!!\n");
1298                         goto res_create_fail;
1299                 }
1300                 pool->base.hw_i2cs[i] = dce112_i2c_hw_create(ctx, i);
1301                 if (pool->base.hw_i2cs[i] == NULL) {
1302                         BREAK_TO_DEBUGGER();
1303                         dm_error(
1304                                 "DC:failed to create i2c engine!!\n");
1305                         goto res_create_fail;
1306                 }
1307                 pool->base.sw_i2cs[i] = NULL;
1308         }
1309
1310         if (!resource_construct(num_virtual_links, dc, &pool->base,
1311                           &res_create_funcs))
1312                 goto res_create_fail;
1313
1314         dc->caps.max_planes =  pool->base.pipe_count;
1315
1316         /* Create hardware sequencer */
1317         dce112_hw_sequencer_construct(dc);
1318
1319         bw_calcs_init(dc->bw_dceip, dc->bw_vbios, dc->ctx->asic_id);
1320
1321         bw_calcs_data_update_from_pplib(dc);
1322
1323         return true;
1324
1325 res_create_fail:
1326         destruct(pool);
1327         return false;
1328 }
1329
1330 struct resource_pool *dce112_create_resource_pool(
1331         uint8_t num_virtual_links,
1332         struct dc *dc)
1333 {
1334         struct dce110_resource_pool *pool =
1335                 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1336
1337         if (!pool)
1338                 return NULL;
1339
1340         if (construct(num_virtual_links, dc, pool))
1341                 return &pool->base;
1342
1343         BREAK_TO_DEBUGGER();
1344         return NULL;
1345 }