drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <linux/delay.h>
  27
  28 #include "dm_services.h"
  29 #include "dc.h"
  30 #include "dc_bios_types.h"
  31 #include "core_types.h"
  32 #include "core_status.h"
  33 #include "resource.h"
  34 #include "dm_helpers.h"
  35 #include "dce110_hw_sequencer.h"
  36 #include "dce110_timing_generator.h"
  37 #include "dce/dce_hwseq.h"
  38 #include "gpio_service_interface.h"
  39
  40 #include "dce110_compressor.h"
  41
  42 #include "bios/bios_parser_helper.h"
  43 #include "timing_generator.h"
  44 #include "mem_input.h"
  45 #include "opp.h"
  46 #include "ipp.h"
  47 #include "transform.h"
  48 #include "stream_encoder.h"
  49 #include "link_encoder.h"
  50 #include "link_hwss.h"
  51 #include "dc_link_dp.h"
  52 #include "clock_source.h"
  53 #include "clk_mgr.h"
  54 #include "abm.h"
  55 #include "audio.h"
  56 #include "reg_helper.h"
  57 #include "panel_cntl.h"
  58
  59 /* include DCE11 register header files */
  60 #include "dce/dce_11_0_d.h"
  61 #include "dce/dce_11_0_sh_mask.h"
  62 #include "custom_float.h"
  63
  64 #include "atomfirmware.h"
  65
  66 #include "dce110_hw_sequencer.h"
  67 #include "dcn10/dcn10_hw_sequencer.h"
  68
  69 #define GAMMA_HW_POINTS_NUM 256
  70
  71 /*
  72  * All values are in milliseconds;
  73  * For eDP, after power-up/power/down,
  74  * 300/500 msec max. delay from LCDVCC to black video generation
  75  */
  76 #define PANEL_POWER_UP_TIMEOUT 300
  77 #define PANEL_POWER_DOWN_TIMEOUT 500
  78 #define HPD_CHECK_INTERVAL 10
  79 #define OLED_POST_T7_DELAY 100
  80 #define OLED_PRE_T11_DELAY 150
  81
  82 #define CTX \
  83         hws->ctx
  84
  85 #define DC_LOGGER_INIT()
  86
  87 #define REG(reg)\
  88         hws->regs->reg
  89
  90 #undef FN
  91 #define FN(reg_name, field_name) \
  92         hws->shifts->field_name, hws->masks->field_name
  93
  94 struct dce110_hw_seq_reg_offsets {
  95         uint32_t crtc;
  96 };
  97
  98 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = {
  99 {
 100         .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 101 },
 102 {
 103         .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 104 },
 105 {
 106         .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 107 },
 108 {
 109         .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL),
 110 }
 111 };
 112
 113 #define HW_REG_BLND(reg, id)\
 114         (reg + reg_offsets[id].blnd)
 115
 116 #define HW_REG_CRTC(reg, id)\
 117         (reg + reg_offsets[id].crtc)
 118
 119 #define MAX_WATERMARK 0xFFFF
 120 #define SAFE_NBP_MARK 0x7FFF
 121
 122 /*******************************************************************************
 123  * Private definitions
 124  ******************************************************************************/
 125 /***************************PIPE_CONTROL***********************************/
 126 static void dce110_init_pte(struct dc_context *ctx)
 127 {
 128         uint32_t addr;
 129         uint32_t value = 0;
 130         uint32_t chunk_int = 0;
 131         uint32_t chunk_mul = 0;
 132
 133         addr = mmUNP_DVMM_PTE_CONTROL;
 134         value = dm_read_reg(ctx, addr);
 135
 136         set_reg_field_value(
 137                 value,
 138                 0,
 139                 DVMM_PTE_CONTROL,
 140                 DVMM_USE_SINGLE_PTE);
 141
 142         set_reg_field_value(
 143                 value,
 144                 1,
 145                 DVMM_PTE_CONTROL,
 146                 DVMM_PTE_BUFFER_MODE0);
 147
 148         set_reg_field_value(
 149                 value,
 150                 1,
 151                 DVMM_PTE_CONTROL,
 152                 DVMM_PTE_BUFFER_MODE1);
 153
 154         dm_write_reg(ctx, addr, value);
 155
 156         addr = mmDVMM_PTE_REQ;
 157         value = dm_read_reg(ctx, addr);
 158
 159         chunk_int = get_reg_field_value(
 160                 value,
 161                 DVMM_PTE_REQ,
 162                 HFLIP_PTEREQ_PER_CHUNK_INT);
 163
 164         chunk_mul = get_reg_field_value(
 165                 value,
 166                 DVMM_PTE_REQ,
 167                 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 168
 169         if (chunk_int != 0x4 || chunk_mul != 0x4) {
 170
 171                 set_reg_field_value(
 172                         value,
 173                         255,
 174                         DVMM_PTE_REQ,
 175                         MAX_PTEREQ_TO_ISSUE);
 176
 177                 set_reg_field_value(
 178                         value,
 179                         4,
 180                         DVMM_PTE_REQ,
 181                         HFLIP_PTEREQ_PER_CHUNK_INT);
 182
 183                 set_reg_field_value(
 184                         value,
 185                         4,
 186                         DVMM_PTE_REQ,
 187                         HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER);
 188
 189                 dm_write_reg(ctx, addr, value);
 190         }
 191 }
 192 /**************************************************************************/
 193
 194 static void enable_display_pipe_clock_gating(
 195         struct dc_context *ctx,
 196         bool clock_gating)
 197 {
 198         /*TODO*/
 199 }
 200
 201 static bool dce110_enable_display_power_gating(
 202         struct dc *dc,
 203         uint8_t controller_id,
 204         struct dc_bios *dcb,
 205         enum pipe_gating_control power_gating)
 206 {
 207         enum bp_result bp_result = BP_RESULT_OK;
 208         enum bp_pipe_control_action cntl;
 209         struct dc_context *ctx = dc->ctx;
 210         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
 211
 212         if (IS_FPGA_MAXIMUS_DC(ctx->dce_environment))
 213                 return true;
 214
 215         if (power_gating == PIPE_GATING_CONTROL_INIT)
 216                 cntl = ASIC_PIPE_INIT;
 217         else if (power_gating == PIPE_GATING_CONTROL_ENABLE)
 218                 cntl = ASIC_PIPE_ENABLE;
 219         else
 220                 cntl = ASIC_PIPE_DISABLE;
 221
 222         if (controller_id == underlay_idx)
 223                 controller_id = CONTROLLER_ID_UNDERLAY0 - 1;
 224
 225         if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0){
 226
 227                 bp_result = dcb->funcs->enable_disp_power_gating(
 228                                                 dcb, controller_id + 1, cntl);
 229
 230                 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2
 231                  * by default when command table is called
 232                  *
 233                  * Bios parser accepts controller_id = 6 as indicative of
 234                  * underlay pipe in dce110. But we do not support more
 235                  * than 3.
 236                  */
 237                 if (controller_id < CONTROLLER_ID_MAX - 1)
 238                         dm_write_reg(ctx,
 239                                 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id),
 240                                 0);
 241         }
 242
 243         if (power_gating != PIPE_GATING_CONTROL_ENABLE)
 244                 dce110_init_pte(ctx);
 245
 246         if (bp_result == BP_RESULT_OK)
 247                 return true;
 248         else
 249                 return false;
 250 }
 251
 252 static void build_prescale_params(struct ipp_prescale_params *prescale_params,
 253                 const struct dc_plane_state *plane_state)
 254 {
 255         prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED;
 256
 257         switch (plane_state->format) {
 258         case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
 259                 prescale_params->scale = 0x2082;
 260                 break;
 261         case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
 262         case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
 263                 prescale_params->scale = 0x2020;
 264                 break;
 265         case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
 266         case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
 267                 prescale_params->scale = 0x2008;
 268                 break;
 269         case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
 270         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
 271         case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
 272                 prescale_params->scale = 0x2000;
 273                 break;
 274         default:
 275                 ASSERT(false);
 276                 break;
 277         }
 278 }
 279
 280 static bool
 281 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
 282                                const struct dc_plane_state *plane_state)
 283 {
 284         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
 285         const struct dc_transfer_func *tf = NULL;
 286         struct ipp_prescale_params prescale_params = { 0 };
 287         bool result = true;
 288
 289         if (ipp == NULL)
 290                 return false;
 291
 292         if (plane_state->in_transfer_func)
 293                 tf = plane_state->in_transfer_func;
 294
 295         build_prescale_params(&prescale_params, plane_state);
 296         ipp->funcs->ipp_program_prescale(ipp, &prescale_params);
 297
 298         if (plane_state->gamma_correction &&
 299                         !plane_state->gamma_correction->is_identity &&
 300                         dce_use_lut(plane_state->format))
 301                 ipp->funcs->ipp_program_input_lut(ipp, plane_state->gamma_correction);
 302
 303         if (tf == NULL) {
 304                 /* Default case if no input transfer function specified */
 305                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 306         } else if (tf->type == TF_TYPE_PREDEFINED) {
 307                 switch (tf->tf) {
 308                 case TRANSFER_FUNCTION_SRGB:
 309                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB);
 310                         break;
 311                 case TRANSFER_FUNCTION_BT709:
 312                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC);
 313                         break;
 314                 case TRANSFER_FUNCTION_LINEAR:
 315                         ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 316                         break;
 317                 case TRANSFER_FUNCTION_PQ:
 318                 default:
 319                         result = false;
 320                         break;
 321                 }
 322         } else if (tf->type == TF_TYPE_BYPASS) {
 323                 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS);
 324         } else {
 325                 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/
 326                 result = false;
 327         }
 328
 329         return result;
 330 }
 331
 332 static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted,
 333                                     struct curve_points *arr_points,
 334                                     uint32_t hw_points_num)
 335 {
 336         struct custom_float_format fmt;
 337
 338         struct pwl_result_data *rgb = rgb_resulted;
 339
 340         uint32_t i = 0;
 341
 342         fmt.exponenta_bits = 6;
 343         fmt.mantissa_bits = 12;
 344         fmt.sign = true;
 345
 346         if (!convert_to_custom_float_format(arr_points[0].x, &fmt,
 347                                             &arr_points[0].custom_float_x)) {
 348                 BREAK_TO_DEBUGGER();
 349                 return false;
 350         }
 351
 352         if (!convert_to_custom_float_format(arr_points[0].offset, &fmt,
 353                                             &arr_points[0].custom_float_offset)) {
 354                 BREAK_TO_DEBUGGER();
 355                 return false;
 356         }
 357
 358         if (!convert_to_custom_float_format(arr_points[0].slope, &fmt,
 359                                             &arr_points[0].custom_float_slope)) {
 360                 BREAK_TO_DEBUGGER();
 361                 return false;
 362         }
 363
 364         fmt.mantissa_bits = 10;
 365         fmt.sign = false;
 366
 367         if (!convert_to_custom_float_format(arr_points[1].x, &fmt,
 368                                             &arr_points[1].custom_float_x)) {
 369                 BREAK_TO_DEBUGGER();
 370                 return false;
 371         }
 372
 373         if (!convert_to_custom_float_format(arr_points[1].y, &fmt,
 374                                             &arr_points[1].custom_float_y)) {
 375                 BREAK_TO_DEBUGGER();
 376                 return false;
 377         }
 378
 379         if (!convert_to_custom_float_format(arr_points[1].slope, &fmt,
 380                                             &arr_points[1].custom_float_slope)) {
 381                 BREAK_TO_DEBUGGER();
 382                 return false;
 383         }
 384
 385         fmt.mantissa_bits = 12;
 386         fmt.sign = true;
 387
 388         while (i != hw_points_num) {
 389                 if (!convert_to_custom_float_format(rgb->red, &fmt,
 390                                                     &rgb->red_reg)) {
 391                         BREAK_TO_DEBUGGER();
 392                         return false;
 393                 }
 394
 395                 if (!convert_to_custom_float_format(rgb->green, &fmt,
 396                                                     &rgb->green_reg)) {
 397                         BREAK_TO_DEBUGGER();
 398                         return false;
 399                 }
 400
 401                 if (!convert_to_custom_float_format(rgb->blue, &fmt,
 402                                                     &rgb->blue_reg)) {
 403                         BREAK_TO_DEBUGGER();
 404                         return false;
 405                 }
 406
 407                 if (!convert_to_custom_float_format(rgb->delta_red, &fmt,
 408                                                     &rgb->delta_red_reg)) {
 409                         BREAK_TO_DEBUGGER();
 410                         return false;
 411                 }
 412
 413                 if (!convert_to_custom_float_format(rgb->delta_green, &fmt,
 414                                                     &rgb->delta_green_reg)) {
 415                         BREAK_TO_DEBUGGER();
 416                         return false;
 417                 }
 418
 419                 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt,
 420                                                     &rgb->delta_blue_reg)) {
 421                         BREAK_TO_DEBUGGER();
 422                         return false;
 423                 }
 424
 425                 ++rgb;
 426                 ++i;
 427         }
 428
 429         return true;
 430 }
 431
 432 #define MAX_LOW_POINT      25
 433 #define NUMBER_REGIONS     16
 434 #define NUMBER_SW_SEGMENTS 16
 435
 436 static bool
 437 dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf,
 438                                       struct pwl_params *regamma_params)
 439 {
 440         struct curve_points *arr_points;
 441         struct pwl_result_data *rgb_resulted;
 442         struct pwl_result_data *rgb;
 443         struct pwl_result_data *rgb_plus_1;
 444         struct fixed31_32 y_r;
 445         struct fixed31_32 y_g;
 446         struct fixed31_32 y_b;
 447         struct fixed31_32 y1_min;
 448         struct fixed31_32 y3_max;
 449
 450         int32_t region_start, region_end;
 451         uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points;
 452
 453         if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS)
 454                 return false;
 455
 456         arr_points = regamma_params->arr_points;
 457         rgb_resulted = regamma_params->rgb_resulted;
 458         hw_points = 0;
 459
 460         memset(regamma_params, 0, sizeof(struct pwl_params));
 461
 462         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 463                 /* 16 segments
 464                  * segments are from 2^-11 to 2^5
 465                  */
 466                 region_start = -11;
 467                 region_end = region_start + NUMBER_REGIONS;
 468
 469                 for (i = 0; i < NUMBER_REGIONS; i++)
 470                         seg_distr[i] = 4;
 471
 472         } else {
 473                 /* 10 segments
 474                  * segment is from 2^-10 to 2^1
 475                  * We include an extra segment for range [2^0, 2^1). This is to
 476                  * ensure that colors with normalized values of 1 don't miss the
 477                  * LUT.
 478                  */
 479                 region_start = -10;
 480                 region_end = 1;
 481
 482                 seg_distr[0] = 4;
 483                 seg_distr[1] = 4;
 484                 seg_distr[2] = 4;
 485                 seg_distr[3] = 4;
 486                 seg_distr[4] = 4;
 487                 seg_distr[5] = 4;
 488                 seg_distr[6] = 4;
 489                 seg_distr[7] = 4;
 490                 seg_distr[8] = 4;
 491                 seg_distr[9] = 4;
 492                 seg_distr[10] = 0;
 493                 seg_distr[11] = -1;
 494                 seg_distr[12] = -1;
 495                 seg_distr[13] = -1;
 496                 seg_distr[14] = -1;
 497                 seg_distr[15] = -1;
 498         }
 499
 500         for (k = 0; k < 16; k++) {
 501                 if (seg_distr[k] != -1)
 502                         hw_points += (1 << seg_distr[k]);
 503         }
 504
 505         j = 0;
 506         for (k = 0; k < (region_end - region_start); k++) {
 507                 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]);
 508                 start_index = (region_start + k + MAX_LOW_POINT) *
 509                                 NUMBER_SW_SEGMENTS;
 510                 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS;
 511                                 i += increment) {
 512                         if (j == hw_points - 1)
 513                                 break;
 514                         rgb_resulted[j].red = output_tf->tf_pts.red[i];
 515                         rgb_resulted[j].green = output_tf->tf_pts.green[i];
 516                         rgb_resulted[j].blue = output_tf->tf_pts.blue[i];
 517                         j++;
 518                 }
 519         }
 520
 521         /* last point */
 522         start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS;
 523         rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index];
 524         rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index];
 525         rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index];
 526
 527         arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2),
 528                                              dc_fixpt_from_int(region_start));
 529         arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2),
 530                                              dc_fixpt_from_int(region_end));
 531
 532         y_r = rgb_resulted[0].red;
 533         y_g = rgb_resulted[0].green;
 534         y_b = rgb_resulted[0].blue;
 535
 536         y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b));
 537
 538         arr_points[0].y = y1_min;
 539         arr_points[0].slope = dc_fixpt_div(arr_points[0].y,
 540                                                  arr_points[0].x);
 541
 542         y_r = rgb_resulted[hw_points - 1].red;
 543         y_g = rgb_resulted[hw_points - 1].green;
 544         y_b = rgb_resulted[hw_points - 1].blue;
 545
 546         /* see comment above, m_arrPoints[1].y should be the Y value for the
 547          * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1)
 548          */
 549         y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b));
 550
 551         arr_points[1].y = y3_max;
 552
 553         arr_points[1].slope = dc_fixpt_zero;
 554
 555         if (output_tf->tf == TRANSFER_FUNCTION_PQ) {
 556                 /* for PQ, we want to have a straight line from last HW X point,
 557                  * and the slope to be such that we hit 1.0 at 10000 nits.
 558                  */
 559                 const struct fixed31_32 end_value = dc_fixpt_from_int(125);
 560
 561                 arr_points[1].slope = dc_fixpt_div(
 562                                 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y),
 563                                 dc_fixpt_sub(end_value, arr_points[1].x));
 564         }
 565
 566         regamma_params->hw_points_num = hw_points;
 567
 568         k = 0;
 569         for (i = 1; i < 16; i++) {
 570                 if (seg_distr[k] != -1) {
 571                         regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 572                         regamma_params->arr_curve_points[i].offset =
 573                                         regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]);
 574                 }
 575                 k++;
 576         }
 577
 578         if (seg_distr[k] != -1)
 579                 regamma_params->arr_curve_points[k].segments_num = seg_distr[k];
 580
 581         rgb = rgb_resulted;
 582         rgb_plus_1 = rgb_resulted + 1;
 583
 584         i = 1;
 585
 586         while (i != hw_points + 1) {
 587                 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red))
 588                         rgb_plus_1->red = rgb->red;
 589                 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green))
 590                         rgb_plus_1->green = rgb->green;
 591                 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue))
 592                         rgb_plus_1->blue = rgb->blue;
 593
 594                 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red);
 595                 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green);
 596                 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue);
 597
 598                 ++rgb_plus_1;
 599                 ++rgb;
 600                 ++i;
 601         }
 602
 603         convert_to_custom_float(rgb_resulted, arr_points, hw_points);
 604
 605         return true;
 606 }
 607
 608 static bool
 609 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx,
 610                                 const struct dc_stream_state *stream)
 611 {
 612         struct transform *xfm = pipe_ctx->plane_res.xfm;
 613
 614         xfm->funcs->opp_power_on_regamma_lut(xfm, true);
 615         xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
 616
 617         if (stream->out_transfer_func &&
 618             stream->out_transfer_func->type == TF_TYPE_PREDEFINED &&
 619             stream->out_transfer_func->tf == TRANSFER_FUNCTION_SRGB) {
 620                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
 621         } else if (dce110_translate_regamma_to_hw_format(stream->out_transfer_func,
 622                                                          &xfm->regamma_params)) {
 623                 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
 624                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
 625         } else {
 626                 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS);
 627         }
 628
 629         xfm->funcs->opp_power_on_regamma_lut(xfm, false);
 630
 631         return true;
 632 }
 633
 634 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
 635 {
 636         bool is_hdmi_tmds;
 637         bool is_dp;
 638
 639         ASSERT(pipe_ctx->stream);
 640
 641         if (pipe_ctx->stream_res.stream_enc == NULL)
 642                 return;  /* this is not root pipe */
 643
 644         is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal);
 645         is_dp = dc_is_dp_signal(pipe_ctx->stream->signal);
 646
 647         if (!is_hdmi_tmds && !is_dp)
 648                 return;
 649
 650         if (is_hdmi_tmds)
 651                 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets(
 652                         pipe_ctx->stream_res.stream_enc,
 653                         &pipe_ctx->stream_res.encoder_info_frame);
 654         else
 655                 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets(
 656                         pipe_ctx->stream_res.stream_enc,
 657                         &pipe_ctx->stream_res.encoder_info_frame);
 658 }
 659
 660 void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
 661 {
 662         enum dc_lane_count lane_count =
 663                 pipe_ctx->stream->link->cur_link_settings.lane_count;
 664         struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
 665         struct dc_link *link = pipe_ctx->stream->link;
 666         const struct dc *dc = link->dc;
 667
 668         uint32_t active_total_with_borders;
 669         uint32_t early_control = 0;
 670         struct timing_generator *tg = pipe_ctx->stream_res.tg;
 671
 672         /* For MST, there are multiply stream go to only one link.
 673          * connect DIG back_end to front_end while enable_stream and
 674          * disconnect them during disable_stream
 675          * BY this, it is logic clean to separate stream and link */
 676         link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
 677                                                     pipe_ctx->stream_res.stream_enc->id, true);
 678
 679         dc->hwss.update_info_frame(pipe_ctx);
 680
 681         /* enable early control to avoid corruption on DP monitor*/
 682         active_total_with_borders =
 683                         timing->h_addressable
 684                                 + timing->h_border_left
 685                                 + timing->h_border_right;
 686
 687         if (lane_count != 0)
 688                 early_control = active_total_with_borders % lane_count;
 689
 690         if (early_control == 0)
 691                 early_control = lane_count;
 692
 693         tg->funcs->set_early_control(tg, early_control);
 694
 695         /* enable audio only within mode set */
 696         if (pipe_ctx->stream_res.audio != NULL) {
 697                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
 698                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
 699         }
 700
 701
 702
 703
 704 }
 705
 706 static enum bp_result link_transmitter_control(
 707                 struct dc_bios *bios,
 708         struct bp_transmitter_control *cntl)
 709 {
 710         enum bp_result result;
 711
 712         result = bios->funcs->transmitter_control(bios, cntl);
 713
 714         return result;
 715 }
 716
 717 /*
 718  * @brief
 719  * eDP only.
 720  */
 721 void dce110_edp_wait_for_hpd_ready(
 722                 struct dc_link *link,
 723                 bool power_up)
 724 {
 725         struct dc_context *ctx = link->ctx;
 726         struct graphics_object_id connector = link->link_enc->connector;
 727         struct gpio *hpd;
 728         struct dc_sink *sink = link->local_sink;
 729         bool edp_hpd_high = false;
 730         uint32_t time_elapsed = 0;
 731         uint32_t timeout = power_up ?
 732                 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT;
 733
 734         if (dal_graphics_object_id_get_connector_id(connector)
 735                         != CONNECTOR_ID_EDP) {
 736                 BREAK_TO_DEBUGGER();
 737                 return;
 738         }
 739
 740         if (!power_up)
 741                 /*
 742                  * From KV, we will not HPD low after turning off VCC -
 743                  * instead, we will check the SW timer in power_up().
 744                  */
 745                 return;
 746
 747         /*
 748          * When we power on/off the eDP panel,
 749          * we need to wait until SENSE bit is high/low.
 750          */
 751
 752         /* obtain HPD */
 753         /* TODO what to do with this? */
 754         hpd = get_hpd_gpio(ctx->dc_bios, connector, ctx->gpio_service);
 755
 756         if (!hpd) {
 757                 BREAK_TO_DEBUGGER();
 758                 return;
 759         }
 760
 761         if (sink != NULL) {
 762                 if (sink->edid_caps.panel_patch.extra_t3_ms > 0) {
 763                         int extra_t3_in_ms = sink->edid_caps.panel_patch.extra_t3_ms;
 764
 765                         msleep(extra_t3_in_ms);
 766                 }
 767         }
 768
 769         dal_gpio_open(hpd, GPIO_MODE_INTERRUPT);
 770
 771         /* wait until timeout or panel detected */
 772
 773         do {
 774                 uint32_t detected = 0;
 775
 776                 dal_gpio_get_value(hpd, &detected);
 777
 778                 if (!(detected ^ power_up)) {
 779                         edp_hpd_high = true;
 780                         break;
 781                 }
 782
 783                 msleep(HPD_CHECK_INTERVAL);
 784
 785                 time_elapsed += HPD_CHECK_INTERVAL;
 786         } while (time_elapsed < timeout);
 787
 788         dal_gpio_close(hpd);
 789
 790         dal_gpio_destroy_irq(&hpd);
 791
 792         if (false == edp_hpd_high) {
 793                 DC_LOG_ERROR(
 794                                 "%s: wait timed out!\n", __func__);
 795         }
 796 }
 797
 798 void dce110_edp_power_control(
 799                 struct dc_link *link,
 800                 bool power_up)
 801 {
 802         struct dc_context *ctx = link->ctx;
 803         struct bp_transmitter_control cntl = { 0 };
 804         enum bp_result bp_result;
 805         uint8_t panel_instance;
 806
 807
 808         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 809                         != CONNECTOR_ID_EDP) {
 810                 BREAK_TO_DEBUGGER();
 811                 return;
 812         }
 813
 814         if (!link->panel_cntl)
 815                 return;
 816         if (power_up !=
 817                 link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) {
 818
 819                 unsigned long long current_ts = dm_get_timestamp(ctx);
 820                 unsigned long long time_since_edp_poweroff_ms =
 821                                 div64_u64(dm_get_elapse_time_in_ns(
 822                                                 ctx,
 823                                                 current_ts,
 824                                                 link->link_trace.time_stamp.edp_poweroff), 1000000);
 825                 unsigned long long time_since_edp_poweron_ms =
 826                                 div64_u64(dm_get_elapse_time_in_ns(
 827                                                 ctx,
 828                                                 current_ts,
 829                                                 link->link_trace.time_stamp.edp_poweron), 1000000);
 830                 DC_LOG_HW_RESUME_S3(
 831                                 "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu",
 832                                 __func__,
 833                                 power_up,
 834                                 current_ts,
 835                                 link->link_trace.time_stamp.edp_poweroff,
 836                                 link->link_trace.time_stamp.edp_poweron,
 837                                 time_since_edp_poweroff_ms,
 838                                 time_since_edp_poweron_ms);
 839
 840                 /* Send VBIOS command to prompt eDP panel power */
 841                 if (power_up) {
 842                         /* edp requires a min of 500ms from LCDVDD off to on */
 843                         unsigned long long remaining_min_edp_poweroff_time_ms = 500;
 844
 845                         /* add time defined by a patch, if any (usually patch extra_t12_ms is 0) */
 846                         if (link->local_sink != NULL)
 847                                 remaining_min_edp_poweroff_time_ms +=
 848                                         link->local_sink->edid_caps.panel_patch.extra_t12_ms;
 849
 850                         /* Adjust remaining_min_edp_poweroff_time_ms if this is not the first time. */
 851                         if (link->link_trace.time_stamp.edp_poweroff != 0) {
 852                                 if (time_since_edp_poweroff_ms < remaining_min_edp_poweroff_time_ms)
 853                                         remaining_min_edp_poweroff_time_ms =
 854                                                 remaining_min_edp_poweroff_time_ms - time_since_edp_poweroff_ms;
 855                                 else
 856                                         remaining_min_edp_poweroff_time_ms = 0;
 857                         }
 858
 859                         if (remaining_min_edp_poweroff_time_ms) {
 860                                 DC_LOG_HW_RESUME_S3(
 861                                                 "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n",
 862                                                 __func__, remaining_min_edp_poweroff_time_ms);
 863                                 msleep(remaining_min_edp_poweroff_time_ms);
 864                                 DC_LOG_HW_RESUME_S3(
 865                                                 "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n",
 866                                                 __func__, remaining_min_edp_poweroff_time_ms);
 867                                 dm_output_to_console("%s: wait %lld ms to power on eDP.\n",
 868                                                 __func__, remaining_min_edp_poweroff_time_ms);
 869                         } else {
 870                                 DC_LOG_HW_RESUME_S3(
 871                                                 "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n",
 872                                                 __func__, remaining_min_edp_poweroff_time_ms);
 873                         }
 874                 }
 875
 876                 DC_LOG_HW_RESUME_S3(
 877                                 "%s: BEGIN: Panel Power action: %s\n",
 878                                 __func__, (power_up ? "On":"Off"));
 879
 880                 cntl.action = power_up ?
 881                         TRANSMITTER_CONTROL_POWER_ON :
 882                         TRANSMITTER_CONTROL_POWER_OFF;
 883                 cntl.transmitter = link->link_enc->transmitter;
 884                 cntl.connector_obj_id = link->link_enc->connector;
 885                 cntl.coherent = false;
 886                 cntl.lanes_number = LANE_COUNT_FOUR;
 887                 cntl.hpd_sel = link->link_enc->hpd_source;
 888                 panel_instance = link->panel_cntl->inst;
 889
 890                 if (ctx->dc->ctx->dmub_srv &&
 891                                 ctx->dc->debug.dmub_command_table) {
 892                         if (cntl.action == TRANSMITTER_CONTROL_POWER_ON)
 893                                 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
 894                                                 LVTMA_CONTROL_POWER_ON,
 895                                                 panel_instance);
 896                         else
 897                                 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
 898                                                 LVTMA_CONTROL_POWER_OFF,
 899                                                 panel_instance);
 900                 }
 901
 902                 bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
 903
 904                 DC_LOG_HW_RESUME_S3(
 905                                 "%s: END: Panel Power action: %s bp_result=%u\n",
 906                                 __func__, (power_up ? "On":"Off"),
 907                                 bp_result);
 908
 909                 if (!power_up)
 910                         /*save driver power off time stamp*/
 911                         link->link_trace.time_stamp.edp_poweroff = dm_get_timestamp(ctx);
 912                 else
 913                         link->link_trace.time_stamp.edp_poweron = dm_get_timestamp(ctx);
 914
 915                 DC_LOG_HW_RESUME_S3(
 916                                 "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n",
 917                                 __func__,
 918                                 link->link_trace.time_stamp.edp_poweroff,
 919                                 link->link_trace.time_stamp.edp_poweron);
 920
 921                 if (bp_result != BP_RESULT_OK)
 922                         DC_LOG_ERROR(
 923                                         "%s: Panel Power bp_result: %d\n",
 924                                         __func__, bp_result);
 925         } else {
 926                 DC_LOG_HW_RESUME_S3(
 927                                 "%s: Skipping Panel Power action: %s\n",
 928                                 __func__, (power_up ? "On":"Off"));
 929         }
 930 }
 931
 932 void dce110_edp_wait_for_T12(
 933                 struct dc_link *link)
 934 {
 935         struct dc_context *ctx = link->ctx;
 936
 937         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 938                         != CONNECTOR_ID_EDP) {
 939                 BREAK_TO_DEBUGGER();
 940                 return;
 941         }
 942
 943         if (!link->panel_cntl)
 944                 return;
 945
 946         if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) &&
 947                         link->link_trace.time_stamp.edp_poweroff != 0) {
 948                 unsigned int t12_duration = 500; // Default T12 as per spec
 949                 unsigned long long current_ts = dm_get_timestamp(ctx);
 950                 unsigned long long time_since_edp_poweroff_ms =
 951                                 div64_u64(dm_get_elapse_time_in_ns(
 952                                                 ctx,
 953                                                 current_ts,
 954                                                 link->link_trace.time_stamp.edp_poweroff), 1000000);
 955
 956                 t12_duration += link->local_sink->edid_caps.panel_patch.extra_t12_ms; // Add extra T12
 957
 958                 if (time_since_edp_poweroff_ms < t12_duration)
 959                         msleep(t12_duration - time_since_edp_poweroff_ms);
 960         }
 961 }
 962
 963 /*todo: cloned in stream enc, fix*/
 964 /*
 965  * @brief
 966  * eDP only. Control the backlight of the eDP panel
 967  */
 968 void dce110_edp_backlight_control(
 969                 struct dc_link *link,
 970                 bool enable)
 971 {
 972         struct dc_context *ctx = link->ctx;
 973         struct bp_transmitter_control cntl = { 0 };
 974         uint8_t panel_instance;
 975
 976         if (dal_graphics_object_id_get_connector_id(link->link_enc->connector)
 977                 != CONNECTOR_ID_EDP) {
 978                 BREAK_TO_DEBUGGER();
 979                 return;
 980         }
 981
 982         if (link->panel_cntl) {
 983                 bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl);
 984
 985                 if ((enable && is_backlight_on) || (!enable && !is_backlight_on)) {
 986                         DC_LOG_HW_RESUME_S3(
 987                                 "%s: panel already powered up/off. Do nothing.\n",
 988                                 __func__);
 989                         return;
 990                 }
 991         }
 992
 993         /* Send VBIOS command to control eDP panel backlight */
 994
 995         DC_LOG_HW_RESUME_S3(
 996                         "%s: backlight action: %s\n",
 997                         __func__, (enable ? "On":"Off"));
 998
 999         cntl.action = enable ?
1000                 TRANSMITTER_CONTROL_BACKLIGHT_ON :
1001                 TRANSMITTER_CONTROL_BACKLIGHT_OFF;
1002
1003         /*cntl.engine_id = ctx->engine;*/
1004         cntl.transmitter = link->link_enc->transmitter;
1005         cntl.connector_obj_id = link->link_enc->connector;
1006         /*todo: unhardcode*/
1007         cntl.lanes_number = LANE_COUNT_FOUR;
1008         cntl.hpd_sel = link->link_enc->hpd_source;
1009         cntl.signal = SIGNAL_TYPE_EDP;
1010
1011         /* For eDP, the following delays might need to be considered
1012          * after link training completed:
1013          * idle period - min. accounts for required BS-Idle pattern,
1014          * max. allows for source frame synchronization);
1015          * 50 msec max. delay from valid video data from source
1016          * to video on dislpay or backlight enable.
1017          *
1018          * Disable the delay for now.
1019          * Enable it in the future if necessary.
1020          */
1021         /* dc_service_sleep_in_milliseconds(50); */
1022                 /*edp 1.2*/
1023         panel_instance = link->panel_cntl->inst;
1024         if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
1025                 edp_receiver_ready_T7(link);
1026
1027         if (ctx->dc->ctx->dmub_srv &&
1028                         ctx->dc->debug.dmub_command_table) {
1029                 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON)
1030                         ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
1031                                         LVTMA_CONTROL_LCD_BLON,
1032                                         panel_instance);
1033                 else
1034                         ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios,
1035                                         LVTMA_CONTROL_LCD_BLOFF,
1036                                         panel_instance);
1037         }
1038
1039         link_transmitter_control(ctx->dc_bios, &cntl);
1040
1041         if (enable && link->dpcd_sink_ext_caps.bits.oled)
1042                 msleep(OLED_POST_T7_DELAY);
1043
1044         if (link->dpcd_sink_ext_caps.bits.oled ||
1045                 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
1046                 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)
1047                 dc_link_backlight_enable_aux(link, enable);
1048
1049         /*edp 1.2*/
1050         if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF)
1051                 edp_add_delay_for_T9(link);
1052
1053         if (!enable && link->dpcd_sink_ext_caps.bits.oled)
1054                 msleep(OLED_PRE_T11_DELAY);
1055 }
1056
1057 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx)
1058 {
1059         /* notify audio driver for audio modes of monitor */
1060         struct dc *dc;
1061         struct clk_mgr *clk_mgr;
1062         unsigned int i, num_audio = 1;
1063
1064         if (!pipe_ctx->stream)
1065                 return;
1066
1067         dc = pipe_ctx->stream->ctx->dc;
1068         clk_mgr = dc->clk_mgr;
1069
1070         if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true)
1071                 return;
1072
1073         if (pipe_ctx->stream_res.audio) {
1074                 for (i = 0; i < MAX_PIPES; i++) {
1075                         /*current_state not updated yet*/
1076                         if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL)
1077                                 num_audio++;
1078                 }
1079
1080                 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio);
1081
1082                 if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa)
1083                         /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1084                         clk_mgr->funcs->enable_pme_wa(clk_mgr);
1085                 /* un-mute audio */
1086                 /* TODO: audio should be per stream rather than per link */
1087                 pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1088                                         pipe_ctx->stream_res.stream_enc, false);
1089                 if (pipe_ctx->stream_res.audio)
1090                         pipe_ctx->stream_res.audio->enabled = true;
1091         }
1092 }
1093
1094 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx)
1095 {
1096         struct dc *dc;
1097         struct clk_mgr *clk_mgr;
1098
1099         if (!pipe_ctx || !pipe_ctx->stream)
1100                 return;
1101
1102         dc = pipe_ctx->stream->ctx->dc;
1103         clk_mgr = dc->clk_mgr;
1104
1105         if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false)
1106                 return;
1107
1108         pipe_ctx->stream_res.stream_enc->funcs->audio_mute_control(
1109                         pipe_ctx->stream_res.stream_enc, true);
1110         if (pipe_ctx->stream_res.audio) {
1111                 pipe_ctx->stream_res.audio->enabled = false;
1112
1113                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1114                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_disable(
1115                                         pipe_ctx->stream_res.stream_enc);
1116                 else
1117                         pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_disable(
1118                                         pipe_ctx->stream_res.stream_enc);
1119
1120                 if (clk_mgr->funcs->enable_pme_wa)
1121                         /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/
1122                         clk_mgr->funcs->enable_pme_wa(clk_mgr);
1123
1124                 /* TODO: notify audio driver for if audio modes list changed
1125                  * add audio mode list change flag */
1126                 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio,
1127                  * stream->stream_engine_id);
1128                  */
1129         }
1130 }
1131
1132 void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
1133 {
1134         struct dc_stream_state *stream = pipe_ctx->stream;
1135         struct dc_link *link = stream->link;
1136         struct dc *dc = pipe_ctx->stream->ctx->dc;
1137
1138         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) {
1139                 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets(
1140                         pipe_ctx->stream_res.stream_enc);
1141                 pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute(
1142                         pipe_ctx->stream_res.stream_enc);
1143         }
1144
1145         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1146                 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets(
1147                         pipe_ctx->stream_res.stream_enc);
1148
1149         dc->hwss.disable_audio_stream(pipe_ctx);
1150
1151         link->link_enc->funcs->connect_dig_be_to_fe(
1152                         link->link_enc,
1153                         pipe_ctx->stream_res.stream_enc->id,
1154                         false);
1155
1156 }
1157
1158 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
1159                 struct dc_link_settings *link_settings)
1160 {
1161         struct encoder_unblank_param params = { { 0 } };
1162         struct dc_stream_state *stream = pipe_ctx->stream;
1163         struct dc_link *link = stream->link;
1164         struct dce_hwseq *hws = link->dc->hwseq;
1165
1166         /* only 3 items below are used by unblank */
1167         params.timing = pipe_ctx->stream->timing;
1168         params.link_settings.link_rate = link_settings->link_rate;
1169
1170         if (dc_is_dp_signal(pipe_ctx->stream->signal))
1171                 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(pipe_ctx->stream_res.stream_enc, &params);
1172
1173         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1174                 hws->funcs.edp_backlight_control(link, true);
1175         }
1176 }
1177
1178 void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
1179 {
1180         struct dc_stream_state *stream = pipe_ctx->stream;
1181         struct dc_link *link = stream->link;
1182         struct dce_hwseq *hws = link->dc->hwseq;
1183
1184         if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1185                 hws->funcs.edp_backlight_control(link, false);
1186                 link->dc->hwss.set_abm_immediate_disable(pipe_ctx);
1187         }
1188
1189         if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
1190                 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(pipe_ctx->stream_res.stream_enc);
1191
1192                 if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) {
1193                         /*
1194                          * After output is idle pattern some sinks need time to recognize the stream
1195                          * has changed or they enter protection state and hang.
1196                          */
1197                         msleep(60);
1198                 } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP)
1199                         edp_receiver_ready_T9(link);
1200         }
1201
1202 }
1203
1204
1205 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
1206 {
1207         if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL)
1208                 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable);
1209 }
1210
1211 static enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id)
1212 {
1213         switch (crtc_id) {
1214         case CONTROLLER_ID_D0:
1215                 return DTO_SOURCE_ID0;
1216         case CONTROLLER_ID_D1:
1217                 return DTO_SOURCE_ID1;
1218         case CONTROLLER_ID_D2:
1219                 return DTO_SOURCE_ID2;
1220         case CONTROLLER_ID_D3:
1221                 return DTO_SOURCE_ID3;
1222         case CONTROLLER_ID_D4:
1223                 return DTO_SOURCE_ID4;
1224         case CONTROLLER_ID_D5:
1225                 return DTO_SOURCE_ID5;
1226         default:
1227                 return DTO_SOURCE_UNKNOWN;
1228         }
1229 }
1230
1231 static void build_audio_output(
1232         struct dc_state *state,
1233         const struct pipe_ctx *pipe_ctx,
1234         struct audio_output *audio_output)
1235 {
1236         const struct dc_stream_state *stream = pipe_ctx->stream;
1237         audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id;
1238
1239         audio_output->signal = pipe_ctx->stream->signal;
1240
1241         /* audio_crtc_info  */
1242
1243         audio_output->crtc_info.h_total =
1244                 stream->timing.h_total;
1245
1246         /*
1247          * Audio packets are sent during actual CRTC blank physical signal, we
1248          * need to specify actual active signal portion
1249          */
1250         audio_output->crtc_info.h_active =
1251                         stream->timing.h_addressable
1252                         + stream->timing.h_border_left
1253                         + stream->timing.h_border_right;
1254
1255         audio_output->crtc_info.v_active =
1256                         stream->timing.v_addressable
1257                         + stream->timing.v_border_top
1258                         + stream->timing.v_border_bottom;
1259
1260         audio_output->crtc_info.pixel_repetition = 1;
1261
1262         audio_output->crtc_info.interlaced =
1263                         stream->timing.flags.INTERLACE;
1264
1265         audio_output->crtc_info.refresh_rate =
1266                 (stream->timing.pix_clk_100hz*100)/
1267                 (stream->timing.h_total*stream->timing.v_total);
1268
1269         audio_output->crtc_info.color_depth =
1270                 stream->timing.display_color_depth;
1271
1272         audio_output->crtc_info.requested_pixel_clock_100Hz =
1273                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1274
1275         audio_output->crtc_info.calculated_pixel_clock_100Hz =
1276                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz;
1277
1278 /*for HDMI, audio ACR is with deep color ratio factor*/
1279         if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) &&
1280                 audio_output->crtc_info.requested_pixel_clock_100Hz ==
1281                                 (stream->timing.pix_clk_100hz)) {
1282                 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1283                         audio_output->crtc_info.requested_pixel_clock_100Hz =
1284                                         audio_output->crtc_info.requested_pixel_clock_100Hz/2;
1285                         audio_output->crtc_info.calculated_pixel_clock_100Hz =
1286                                         pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2;
1287
1288                 }
1289         }
1290
1291         if (state->clk_mgr &&
1292                 (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT ||
1293                         pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) {
1294                 audio_output->pll_info.dp_dto_source_clock_in_khz =
1295                                 state->clk_mgr->funcs->get_dp_ref_clk_frequency(
1296                                                 state->clk_mgr);
1297         }
1298
1299         audio_output->pll_info.feed_back_divider =
1300                         pipe_ctx->pll_settings.feedback_divider;
1301
1302         audio_output->pll_info.dto_source =
1303                 translate_to_dto_source(
1304                         pipe_ctx->stream_res.tg->inst + 1);
1305
1306         /* TODO hard code to enable for now. Need get from stream */
1307         audio_output->pll_info.ss_enabled = true;
1308
1309         audio_output->pll_info.ss_percentage =
1310                         pipe_ctx->pll_settings.ss_percentage;
1311 }
1312
1313 static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
1314                 struct tg_color *color)
1315 {
1316         uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4;
1317
1318         switch (pipe_ctx->plane_res.scl_data.format) {
1319         case PIXEL_FORMAT_ARGB8888:
1320                 /* set boarder color to red */
1321                 color->color_r_cr = color_value;
1322                 break;
1323
1324         case PIXEL_FORMAT_ARGB2101010:
1325                 /* set boarder color to blue */
1326                 color->color_b_cb = color_value;
1327                 break;
1328         case PIXEL_FORMAT_420BPP8:
1329                 /* set boarder color to green */
1330                 color->color_g_y = color_value;
1331                 break;
1332         case PIXEL_FORMAT_420BPP10:
1333                 /* set boarder color to yellow */
1334                 color->color_g_y = color_value;
1335                 color->color_r_cr = color_value;
1336                 break;
1337         case PIXEL_FORMAT_FP16:
1338                 /* set boarder color to white */
1339                 color->color_r_cr = color_value;
1340                 color->color_b_cb = color_value;
1341                 color->color_g_y = color_value;
1342                 break;
1343         default:
1344                 break;
1345         }
1346 }
1347
1348 static void program_scaler(const struct dc *dc,
1349                 const struct pipe_ctx *pipe_ctx)
1350 {
1351         struct tg_color color = {0};
1352
1353 #if defined(CONFIG_DRM_AMD_DC_DCN)
1354         /* TOFPGA */
1355         if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL)
1356                 return;
1357 #endif
1358
1359         if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE)
1360                 get_surface_visual_confirm_color(pipe_ctx, &color);
1361         else
1362                 color_space_to_black_color(dc,
1363                                 pipe_ctx->stream->output_color_space,
1364                                 &color);
1365
1366         pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth(
1367                 pipe_ctx->plane_res.xfm,
1368                 pipe_ctx->plane_res.scl_data.lb_params.depth,
1369                 &pipe_ctx->stream->bit_depth_params);
1370
1371         if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) {
1372                 /*
1373                  * The way 420 is packed, 2 channels carry Y component, 1 channel
1374                  * alternate between Cb and Cr, so both channels need the pixel
1375                  * value for Y
1376                  */
1377                 if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1378                         color.color_r_cr = color.color_g_y;
1379
1380                 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color(
1381                                 pipe_ctx->stream_res.tg,
1382                                 &color);
1383         }
1384
1385         pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm,
1386                 &pipe_ctx->plane_res.scl_data);
1387 }
1388
1389 static enum dc_status dce110_enable_stream_timing(
1390                 struct pipe_ctx *pipe_ctx,
1391                 struct dc_state *context,
1392                 struct dc *dc)
1393 {
1394         struct dc_stream_state *stream = pipe_ctx->stream;
1395         struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx.
1396                         pipe_ctx[pipe_ctx->pipe_idx];
1397         struct tg_color black_color = {0};
1398
1399         if (!pipe_ctx_old->stream) {
1400
1401                 /* program blank color */
1402                 color_space_to_black_color(dc,
1403                                 stream->output_color_space, &black_color);
1404                 pipe_ctx->stream_res.tg->funcs->set_blank_color(
1405                                 pipe_ctx->stream_res.tg,
1406                                 &black_color);
1407
1408                 /*
1409                  * Must blank CRTC after disabling power gating and before any
1410                  * programming, otherwise CRTC will be hung in bad state
1411                  */
1412                 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true);
1413
1414                 if (false == pipe_ctx->clock_source->funcs->program_pix_clk(
1415                                 pipe_ctx->clock_source,
1416                                 &pipe_ctx->stream_res.pix_clk_params,
1417                                 &pipe_ctx->pll_settings)) {
1418                         BREAK_TO_DEBUGGER();
1419                         return DC_ERROR_UNEXPECTED;
1420                 }
1421
1422                 pipe_ctx->stream_res.tg->funcs->program_timing(
1423                                 pipe_ctx->stream_res.tg,
1424                                 &stream->timing,
1425                                 0,
1426                                 0,
1427                                 0,
1428                                 0,
1429                                 pipe_ctx->stream->signal,
1430                                 true);
1431         }
1432
1433         if (!pipe_ctx_old->stream) {
1434                 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc(
1435                                 pipe_ctx->stream_res.tg)) {
1436                         BREAK_TO_DEBUGGER();
1437                         return DC_ERROR_UNEXPECTED;
1438                 }
1439         }
1440
1441         return DC_OK;
1442 }
1443
1444 static enum dc_status apply_single_controller_ctx_to_hw(
1445                 struct pipe_ctx *pipe_ctx,
1446                 struct dc_state *context,
1447                 struct dc *dc)
1448 {
1449         struct dc_stream_state *stream = pipe_ctx->stream;
1450         struct drr_params params = {0};
1451         unsigned int event_triggers = 0;
1452         struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe;
1453         struct dce_hwseq *hws = dc->hwseq;
1454
1455         if (hws->funcs.disable_stream_gating) {
1456                 hws->funcs.disable_stream_gating(dc, pipe_ctx);
1457         }
1458
1459         if (pipe_ctx->stream_res.audio != NULL) {
1460                 struct audio_output audio_output;
1461
1462                 build_audio_output(context, pipe_ctx, &audio_output);
1463
1464                 if (dc_is_dp_signal(pipe_ctx->stream->signal))
1465                         pipe_ctx->stream_res.stream_enc->funcs->dp_audio_setup(
1466                                         pipe_ctx->stream_res.stream_enc,
1467                                         pipe_ctx->stream_res.audio->inst,
1468                                         &pipe_ctx->stream->audio_info);
1469                 else
1470                         pipe_ctx->stream_res.stream_enc->funcs->hdmi_audio_setup(
1471                                         pipe_ctx->stream_res.stream_enc,
1472                                         pipe_ctx->stream_res.audio->inst,
1473                                         &pipe_ctx->stream->audio_info,
1474                                         &audio_output.crtc_info);
1475
1476                 pipe_ctx->stream_res.audio->funcs->az_configure(
1477                                 pipe_ctx->stream_res.audio,
1478                                 pipe_ctx->stream->signal,
1479                                 &audio_output.crtc_info,
1480                                 &pipe_ctx->stream->audio_info);
1481         }
1482
1483         /*  */
1484         /* Do not touch stream timing on seamless boot optimization. */
1485         if (!pipe_ctx->stream->apply_seamless_boot_optimization)
1486                 hws->funcs.enable_stream_timing(pipe_ctx, context, dc);
1487
1488         if (hws->funcs.setup_vupdate_interrupt)
1489                 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx);
1490
1491         params.vertical_total_min = stream->adjust.v_total_min;
1492         params.vertical_total_max = stream->adjust.v_total_max;
1493         if (pipe_ctx->stream_res.tg->funcs->set_drr)
1494                 pipe_ctx->stream_res.tg->funcs->set_drr(
1495                         pipe_ctx->stream_res.tg, &params);
1496
1497         // DRR should set trigger event to monitor surface update event
1498         if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0)
1499                 event_triggers = 0x80;
1500         /* Event triggers and num frames initialized for DRR, but can be
1501          * later updated for PSR use. Note DRR trigger events are generated
1502          * regardless of whether num frames met.
1503          */
1504         if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control)
1505                 pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
1506                                 pipe_ctx->stream_res.tg, event_triggers, 2);
1507
1508         if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
1509                 pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(
1510                         pipe_ctx->stream_res.stream_enc,
1511                         pipe_ctx->stream_res.tg->inst);
1512
1513         pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion(
1514                         pipe_ctx->stream_res.opp,
1515                         COLOR_SPACE_YCBCR601,
1516                         stream->timing.display_color_depth,
1517                         stream->signal);
1518
1519         pipe_ctx->stream_res.opp->funcs->opp_program_fmt(
1520                 pipe_ctx->stream_res.opp,
1521                 &stream->bit_depth_params,
1522                 &stream->clamping);
1523         while (odm_pipe) {
1524                 odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion(
1525                                 odm_pipe->stream_res.opp,
1526                                 COLOR_SPACE_YCBCR601,
1527                                 stream->timing.display_color_depth,
1528                                 stream->signal);
1529
1530                 odm_pipe->stream_res.opp->funcs->opp_program_fmt(
1531                                 odm_pipe->stream_res.opp,
1532                                 &stream->bit_depth_params,
1533                                 &stream->clamping);
1534                 odm_pipe = odm_pipe->next_odm_pipe;
1535         }
1536
1537         if (!stream->dpms_off)
1538                 core_link_enable_stream(context, pipe_ctx);
1539
1540         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
1541
1542         pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false;
1543
1544         return DC_OK;
1545 }
1546
1547 /******************************************************************************/
1548
1549 static void power_down_encoders(struct dc *dc)
1550 {
1551         int i;
1552
1553         /* do not know BIOS back-front mapping, simply blank all. It will not
1554          * hurt for non-DP
1555          */
1556         for (i = 0; i < dc->res_pool->stream_enc_count; i++) {
1557                 dc->res_pool->stream_enc[i]->funcs->dp_blank(
1558                                         dc->res_pool->stream_enc[i]);
1559         }
1560
1561         for (i = 0; i < dc->link_count; i++) {
1562                 enum signal_type signal = dc->links[i]->connector_signal;
1563
1564                 if ((signal == SIGNAL_TYPE_EDP) ||
1565                         (signal == SIGNAL_TYPE_DISPLAY_PORT))
1566                         if (!dc->links[i]->wa_flags.dp_keep_receiver_powered)
1567                                 dp_receiver_power_ctrl(dc->links[i], false);
1568
1569                 if (signal != SIGNAL_TYPE_EDP)
1570                         signal = SIGNAL_TYPE_NONE;
1571
1572                 dc->links[i]->link_enc->funcs->disable_output(
1573                                 dc->links[i]->link_enc, signal);
1574
1575                 dc->links[i]->link_status.link_active = false;
1576                 memset(&dc->links[i]->cur_link_settings, 0,
1577                                 sizeof(dc->links[i]->cur_link_settings));
1578         }
1579 }
1580
1581 static void power_down_controllers(struct dc *dc)
1582 {
1583         int i;
1584
1585         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1586                 dc->res_pool->timing_generators[i]->funcs->disable_crtc(
1587                                 dc->res_pool->timing_generators[i]);
1588         }
1589 }
1590
1591 static void power_down_clock_sources(struct dc *dc)
1592 {
1593         int i;
1594
1595         if (dc->res_pool->dp_clock_source->funcs->cs_power_down(
1596                 dc->res_pool->dp_clock_source) == false)
1597                 dm_error("Failed to power down pll! (dp clk src)\n");
1598
1599         for (i = 0; i < dc->res_pool->clk_src_count; i++) {
1600                 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down(
1601                                 dc->res_pool->clock_sources[i]) == false)
1602                         dm_error("Failed to power down pll! (clk src index=%d)\n", i);
1603         }
1604 }
1605
1606 static void power_down_all_hw_blocks(struct dc *dc)
1607 {
1608         power_down_encoders(dc);
1609
1610         power_down_controllers(dc);
1611
1612         power_down_clock_sources(dc);
1613
1614         if (dc->fbc_compressor)
1615                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
1616 }
1617
1618 static void disable_vga_and_power_gate_all_controllers(
1619                 struct dc *dc)
1620 {
1621         int i;
1622         struct timing_generator *tg;
1623         struct dc_context *ctx = dc->ctx;
1624
1625         for (i = 0; i < dc->res_pool->timing_generator_count; i++) {
1626                 tg = dc->res_pool->timing_generators[i];
1627
1628                 if (tg->funcs->disable_vga)
1629                         tg->funcs->disable_vga(tg);
1630         }
1631         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1632                 /* Enable CLOCK gating for each pipe BEFORE controller
1633                  * powergating. */
1634                 enable_display_pipe_clock_gating(ctx,
1635                                 true);
1636
1637                 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i;
1638                 dc->hwss.disable_plane(dc,
1639                         &dc->current_state->res_ctx.pipe_ctx[i]);
1640         }
1641 }
1642
1643
1644 static void get_edp_streams(struct dc_state *context,
1645                 struct dc_stream_state **edp_streams,
1646                 int *edp_stream_num)
1647 {
1648         int i;
1649
1650         *edp_stream_num = 0;
1651         for (i = 0; i < context->stream_count; i++) {
1652                 if (context->streams[i]->signal == SIGNAL_TYPE_EDP) {
1653                         edp_streams[*edp_stream_num] = context->streams[i];
1654                         if (++(*edp_stream_num) == MAX_NUM_EDP)
1655                                 return;
1656                 }
1657         }
1658 }
1659
1660 static void get_edp_links_with_sink(
1661                 struct dc *dc,
1662                 struct dc_link **edp_links_with_sink,
1663                 int *edp_with_sink_num)
1664 {
1665         int i;
1666
1667         /* check if there is an eDP panel not in use */
1668         *edp_with_sink_num = 0;
1669         for (i = 0; i < dc->link_count; i++) {
1670                 if (dc->links[i]->local_sink &&
1671                         dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) {
1672                         edp_links_with_sink[*edp_with_sink_num] = dc->links[i];
1673                         if (++(*edp_with_sink_num) == MAX_NUM_EDP)
1674                                 return;
1675                 }
1676         }
1677 }
1678
1679 /*
1680  * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need:
1681  *  1. Power down all DC HW blocks
1682  *  2. Disable VGA engine on all controllers
1683  *  3. Enable power gating for controller
1684  *  4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
1685  */
1686 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context)
1687 {
1688         struct dc_link *edp_links_with_sink[MAX_NUM_EDP];
1689         struct dc_link *edp_links[MAX_NUM_EDP];
1690         struct dc_stream_state *edp_streams[MAX_NUM_EDP];
1691         struct dc_link *edp_link_with_sink = NULL;
1692         struct dc_link *edp_link = NULL;
1693         struct dc_stream_state *edp_stream = NULL;
1694         struct dce_hwseq *hws = dc->hwseq;
1695         int edp_with_sink_num;
1696         int edp_num;
1697         int edp_stream_num;
1698         int i;
1699         bool can_apply_edp_fast_boot = false;
1700         bool can_apply_seamless_boot = false;
1701         bool keep_edp_vdd_on = false;
1702         DC_LOGGER_INIT();
1703
1704
1705         get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num);
1706         get_edp_links(dc, edp_links, &edp_num);
1707
1708         if (hws->funcs.init_pipes)
1709                 hws->funcs.init_pipes(dc, context);
1710
1711         get_edp_streams(context, edp_streams, &edp_stream_num);
1712
1713         // Check fastboot support, disable on DCE8 because of blank screens
1714         if (edp_num && dc->ctx->dce_version != DCE_VERSION_8_0 &&
1715                     dc->ctx->dce_version != DCE_VERSION_8_1 &&
1716                     dc->ctx->dce_version != DCE_VERSION_8_3) {
1717                 for (i = 0; i < edp_num; i++) {
1718                         edp_link = edp_links[i];
1719                         // enable fastboot if backend is enabled on eDP
1720                         if (edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc)) {
1721                                 /* Set optimization flag on eDP stream*/
1722                                 if (edp_stream_num && edp_link->link_status.link_active) {
1723                                         edp_stream = edp_streams[0];
1724                                         can_apply_edp_fast_boot = !is_edp_ilr_optimization_required(edp_stream->link, &edp_stream->timing);
1725                                         edp_stream->apply_edp_fast_boot_optimization = can_apply_edp_fast_boot;
1726                                         if (can_apply_edp_fast_boot)
1727                                                 DC_LOG_EVENT_LINK_TRAINING("eDP fast boot disabled to optimize link rate\n");
1728
1729                                         break;
1730                                 }
1731                         }
1732                 }
1733                 // We are trying to enable eDP, don't power down VDD
1734                 if (edp_stream_num)
1735                         keep_edp_vdd_on = true;
1736         }
1737
1738         // Check seamless boot support
1739         for (i = 0; i < context->stream_count; i++) {
1740                 if (context->streams[i]->apply_seamless_boot_optimization) {
1741                         can_apply_seamless_boot = true;
1742                         break;
1743                 }
1744         }
1745
1746         /* eDP should not have stream in resume from S4 and so even with VBios post
1747          * it should get turned off
1748          */
1749         if (edp_with_sink_num)
1750                 edp_link_with_sink = edp_links_with_sink[0];
1751
1752         if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) {
1753                 if (edp_link_with_sink && !keep_edp_vdd_on) {
1754                         /*turn off backlight before DP_blank and encoder powered down*/
1755                         hws->funcs.edp_backlight_control(edp_link_with_sink, false);
1756                 }
1757                 /*resume from S3, no vbios posting, no need to power down again*/
1758                 power_down_all_hw_blocks(dc);
1759                 disable_vga_and_power_gate_all_controllers(dc);
1760                 if (edp_link_with_sink && !keep_edp_vdd_on)
1761                         dc->hwss.edp_power_control(edp_link_with_sink, false);
1762         }
1763         bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1);
1764 }
1765
1766 static uint32_t compute_pstate_blackout_duration(
1767         struct bw_fixed blackout_duration,
1768         const struct dc_stream_state *stream)
1769 {
1770         uint32_t total_dest_line_time_ns;
1771         uint32_t pstate_blackout_duration_ns;
1772
1773         pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
1774
1775         total_dest_line_time_ns = 1000000UL *
1776                 (stream->timing.h_total * 10) /
1777                 stream->timing.pix_clk_100hz +
1778                 pstate_blackout_duration_ns;
1779
1780         return total_dest_line_time_ns;
1781 }
1782
1783 static void dce110_set_displaymarks(
1784         const struct dc *dc,
1785         struct dc_state *context)
1786 {
1787         uint8_t i, num_pipes;
1788         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1789
1790         for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) {
1791                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
1792                 uint32_t total_dest_line_time_ns;
1793
1794                 if (pipe_ctx->stream == NULL)
1795                         continue;
1796
1797                 total_dest_line_time_ns = compute_pstate_blackout_duration(
1798                         dc->bw_vbios->blackout_duration, pipe_ctx->stream);
1799                 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks(
1800                         pipe_ctx->plane_res.mi,
1801                         context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1802                         context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1803                         context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes],
1804                         context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1805                         total_dest_line_time_ns);
1806                 if (i == underlay_idx) {
1807                         num_pipes++;
1808                         pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1809                                 pipe_ctx->plane_res.mi,
1810                                 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes],
1811                                 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes],
1812                                 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes],
1813                                 total_dest_line_time_ns);
1814                 }
1815                 num_pipes++;
1816         }
1817 }
1818
1819 void dce110_set_safe_displaymarks(
1820                 struct resource_context *res_ctx,
1821                 const struct resource_pool *pool)
1822 {
1823         int i;
1824         int underlay_idx = pool->underlay_pipe_index;
1825         struct dce_watermarks max_marks = {
1826                 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK };
1827         struct dce_watermarks nbp_marks = {
1828                 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK };
1829         struct dce_watermarks min_marks = { 0, 0, 0, 0};
1830
1831         for (i = 0; i < MAX_PIPES; i++) {
1832                 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL)
1833                         continue;
1834
1835                 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks(
1836                                 res_ctx->pipe_ctx[i].plane_res.mi,
1837                                 nbp_marks,
1838                                 max_marks,
1839                                 min_marks,
1840                                 max_marks,
1841                                 MAX_WATERMARK);
1842
1843                 if (i == underlay_idx)
1844                         res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks(
1845                                 res_ctx->pipe_ctx[i].plane_res.mi,
1846                                 nbp_marks,
1847                                 max_marks,
1848                                 max_marks,
1849                                 MAX_WATERMARK);
1850
1851         }
1852 }
1853
1854 /*******************************************************************************
1855  * Public functions
1856  ******************************************************************************/
1857
1858 static void set_drr(struct pipe_ctx **pipe_ctx,
1859                 int num_pipes, struct dc_crtc_timing_adjust adjust)
1860 {
1861         int i = 0;
1862         struct drr_params params = {0};
1863         // DRR should set trigger event to monitor surface update event
1864         unsigned int event_triggers = 0x80;
1865         // Note DRR trigger events are generated regardless of whether num frames met.
1866         unsigned int num_frames = 2;
1867
1868         params.vertical_total_max = adjust.v_total_max;
1869         params.vertical_total_min = adjust.v_total_min;
1870
1871         /* TODO: If multiple pipes are to be supported, you need
1872          * some GSL stuff. Static screen triggers may be programmed differently
1873          * as well.
1874          */
1875         for (i = 0; i < num_pipes; i++) {
1876                 pipe_ctx[i]->stream_res.tg->funcs->set_drr(
1877                         pipe_ctx[i]->stream_res.tg, &params);
1878
1879                 if (adjust.v_total_max != 0 && adjust.v_total_min != 0)
1880                         pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control(
1881                                         pipe_ctx[i]->stream_res.tg,
1882                                         event_triggers, num_frames);
1883         }
1884 }
1885
1886 static void get_position(struct pipe_ctx **pipe_ctx,
1887                 int num_pipes,
1888                 struct crtc_position *position)
1889 {
1890         int i = 0;
1891
1892         /* TODO: handle pipes > 1
1893          */
1894         for (i = 0; i < num_pipes; i++)
1895                 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position);
1896 }
1897
1898 static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
1899                 int num_pipes, const struct dc_static_screen_params *params)
1900 {
1901         unsigned int i;
1902         unsigned int triggers = 0;
1903
1904         if (params->triggers.overlay_update)
1905                 triggers |= 0x100;
1906         if (params->triggers.surface_update)
1907                 triggers |= 0x80;
1908         if (params->triggers.cursor_update)
1909                 triggers |= 0x2;
1910         if (params->triggers.force_trigger)
1911                 triggers |= 0x1;
1912
1913         if (num_pipes) {
1914                 struct dc *dc = pipe_ctx[0]->stream->ctx->dc;
1915
1916                 if (dc->fbc_compressor)
1917                         triggers |= 0x84;
1918         }
1919
1920         for (i = 0; i < num_pipes; i++)
1921                 pipe_ctx[i]->stream_res.tg->funcs->
1922                         set_static_screen_control(pipe_ctx[i]->stream_res.tg,
1923                                         triggers, params->num_frames);
1924 }
1925
1926 /*
1927  *  Check if FBC can be enabled
1928  */
1929 static bool should_enable_fbc(struct dc *dc,
1930                 struct dc_state *context,
1931                 uint32_t *pipe_idx)
1932 {
1933         uint32_t i;
1934         struct pipe_ctx *pipe_ctx = NULL;
1935         struct resource_context *res_ctx = &context->res_ctx;
1936         unsigned int underlay_idx = dc->res_pool->underlay_pipe_index;
1937
1938
1939         ASSERT(dc->fbc_compressor);
1940
1941         /* FBC memory should be allocated */
1942         if (!dc->ctx->fbc_gpu_addr)
1943                 return false;
1944
1945         /* Only supports single display */
1946         if (context->stream_count != 1)
1947                 return false;
1948
1949         for (i = 0; i < dc->res_pool->pipe_count; i++) {
1950                 if (res_ctx->pipe_ctx[i].stream) {
1951
1952                         pipe_ctx = &res_ctx->pipe_ctx[i];
1953
1954                         if (!pipe_ctx)
1955                                 continue;
1956
1957                         /* fbc not applicable on underlay pipe */
1958                         if (pipe_ctx->pipe_idx != underlay_idx) {
1959                                 *pipe_idx = i;
1960                                 break;
1961                         }
1962                 }
1963         }
1964
1965         if (i == dc->res_pool->pipe_count)
1966                 return false;
1967
1968         if (!pipe_ctx->stream->link)
1969                 return false;
1970
1971         /* Only supports eDP */
1972         if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP)
1973                 return false;
1974
1975         /* PSR should not be enabled */
1976         if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled)
1977                 return false;
1978
1979         /* Nothing to compress */
1980         if (!pipe_ctx->plane_state)
1981                 return false;
1982
1983         /* Only for non-linear tiling */
1984         if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL)
1985                 return false;
1986
1987         return true;
1988 }
1989
1990 /*
1991  *  Enable FBC
1992  */
1993 static void enable_fbc(
1994                 struct dc *dc,
1995                 struct dc_state *context)
1996 {
1997         uint32_t pipe_idx = 0;
1998
1999         if (should_enable_fbc(dc, context, &pipe_idx)) {
2000                 /* Program GRPH COMPRESSED ADDRESS and PITCH */
2001                 struct compr_addr_and_pitch_params params = {0, 0, 0};
2002                 struct compressor *compr = dc->fbc_compressor;
2003                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];
2004
2005                 params.source_view_width = pipe_ctx->stream->timing.h_addressable;
2006                 params.source_view_height = pipe_ctx->stream->timing.v_addressable;
2007                 params.inst = pipe_ctx->stream_res.tg->inst;
2008                 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr;
2009
2010                 compr->funcs->surface_address_and_pitch(compr, &params);
2011                 compr->funcs->set_fbc_invalidation_triggers(compr, 1);
2012
2013                 compr->funcs->enable_fbc(compr, &params);
2014         }
2015 }
2016
2017 static void dce110_reset_hw_ctx_wrap(
2018                 struct dc *dc,
2019                 struct dc_state *context)
2020 {
2021         int i;
2022
2023         /* Reset old context */
2024         /* look up the targets that have been removed since last commit */
2025         for (i = 0; i < MAX_PIPES; i++) {
2026                 struct pipe_ctx *pipe_ctx_old =
2027                         &dc->current_state->res_ctx.pipe_ctx[i];
2028                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2029
2030                 /* Note: We need to disable output if clock sources change,
2031                  * since bios does optimization and doesn't apply if changing
2032                  * PHY when not already disabled.
2033                  */
2034
2035                 /* Skip underlay pipe since it will be handled in commit surface*/
2036                 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe)
2037                         continue;
2038
2039                 if (!pipe_ctx->stream ||
2040                                 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) {
2041                         struct clock_source *old_clk = pipe_ctx_old->clock_source;
2042
2043                         /* Disable if new stream is null. O/w, if stream is
2044                          * disabled already, no need to disable again.
2045                          */
2046                         if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) {
2047                                 core_link_disable_stream(pipe_ctx_old);
2048
2049                                 /* free acquired resources*/
2050                                 if (pipe_ctx_old->stream_res.audio) {
2051                                         /*disable az_endpoint*/
2052                                         pipe_ctx_old->stream_res.audio->funcs->
2053                                                         az_disable(pipe_ctx_old->stream_res.audio);
2054
2055                                         /*free audio*/
2056                                         if (dc->caps.dynamic_audio == true) {
2057                                                 /*we have to dynamic arbitrate the audio endpoints*/
2058                                                 /*we free the resource, need reset is_audio_acquired*/
2059                                                 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool,
2060                                                                 pipe_ctx_old->stream_res.audio, false);
2061                                                 pipe_ctx_old->stream_res.audio = NULL;
2062                                         }
2063                                 }
2064                         }
2065
2066                         pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true);
2067                         if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) {
2068                                 dm_error("DC: failed to blank crtc!\n");
2069                                 BREAK_TO_DEBUGGER();
2070                         }
2071                         pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg);
2072                         pipe_ctx_old->plane_res.mi->funcs->free_mem_input(
2073                                         pipe_ctx_old->plane_res.mi, dc->current_state->stream_count);
2074
2075                         if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx,
2076                                                                                 dc->res_pool,
2077                                                                                 old_clk))
2078                                 old_clk->funcs->cs_power_down(old_clk);
2079
2080                         dc->hwss.disable_plane(dc, pipe_ctx_old);
2081
2082                         pipe_ctx_old->stream = NULL;
2083                 }
2084         }
2085 }
2086
2087 static void dce110_setup_audio_dto(
2088                 struct dc *dc,
2089                 struct dc_state *context)
2090 {
2091         int i;
2092
2093         /* program audio wall clock. use HDMI as clock source if HDMI
2094          * audio active. Otherwise, use DP as clock source
2095          * first, loop to find any HDMI audio, if not, loop find DP audio
2096          */
2097         /* Setup audio rate clock source */
2098         /* Issue:
2099         * Audio lag happened on DP monitor when unplug a HDMI monitor
2100         *
2101         * Cause:
2102         * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL
2103         * is set to either dto0 or dto1, audio should work fine.
2104         * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1,
2105         * set to dto0 will cause audio lag.
2106         *
2107         * Solution:
2108         * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx,
2109         * find first available pipe with audio, setup audio wall DTO per topology
2110         * instead of per pipe.
2111         */
2112         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2113                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2114
2115                 if (pipe_ctx->stream == NULL)
2116                         continue;
2117
2118                 if (pipe_ctx->top_pipe)
2119                         continue;
2120                 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
2121                         continue;
2122                 if (pipe_ctx->stream_res.audio != NULL) {
2123                         struct audio_output audio_output;
2124
2125                         build_audio_output(context, pipe_ctx, &audio_output);
2126
2127                         pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2128                                 pipe_ctx->stream_res.audio,
2129                                 pipe_ctx->stream->signal,
2130                                 &audio_output.crtc_info,
2131                                 &audio_output.pll_info);
2132                         break;
2133                 }
2134         }
2135
2136         /* no HDMI audio is found, try DP audio */
2137         if (i == dc->res_pool->pipe_count) {
2138                 for (i = 0; i < dc->res_pool->pipe_count; i++) {
2139                         struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2140
2141                         if (pipe_ctx->stream == NULL)
2142                                 continue;
2143
2144                         if (pipe_ctx->top_pipe)
2145                                 continue;
2146
2147                         if (!dc_is_dp_signal(pipe_ctx->stream->signal))
2148                                 continue;
2149
2150                         if (pipe_ctx->stream_res.audio != NULL) {
2151                                 struct audio_output audio_output;
2152
2153                                 build_audio_output(context, pipe_ctx, &audio_output);
2154
2155                                 pipe_ctx->stream_res.audio->funcs->wall_dto_setup(
2156                                         pipe_ctx->stream_res.audio,
2157                                         pipe_ctx->stream->signal,
2158                                         &audio_output.crtc_info,
2159                                         &audio_output.pll_info);
2160                                 break;
2161                         }
2162                 }
2163         }
2164 }
2165
2166 enum dc_status dce110_apply_ctx_to_hw(
2167                 struct dc *dc,
2168                 struct dc_state *context)
2169 {
2170         struct dce_hwseq *hws = dc->hwseq;
2171         struct dc_bios *dcb = dc->ctx->dc_bios;
2172         enum dc_status status;
2173         int i;
2174
2175         /* Reset old context */
2176         /* look up the targets that have been removed since last commit */
2177         hws->funcs.reset_hw_ctx_wrap(dc, context);
2178
2179         /* Skip applying if no targets */
2180         if (context->stream_count <= 0)
2181                 return DC_OK;
2182
2183         /* Apply new context */
2184         dcb->funcs->set_scratch_critical_state(dcb, true);
2185
2186         /* below is for real asic only */
2187         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2188                 struct pipe_ctx *pipe_ctx_old =
2189                                         &dc->current_state->res_ctx.pipe_ctx[i];
2190                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2191
2192                 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe)
2193                         continue;
2194
2195                 if (pipe_ctx->stream == pipe_ctx_old->stream) {
2196                         if (pipe_ctx_old->clock_source != pipe_ctx->clock_source)
2197                                 dce_crtc_switch_to_clk_src(dc->hwseq,
2198                                                 pipe_ctx->clock_source, i);
2199                         continue;
2200                 }
2201
2202                 hws->funcs.enable_display_power_gating(
2203                                 dc, i, dc->ctx->dc_bios,
2204                                 PIPE_GATING_CONTROL_DISABLE);
2205         }
2206
2207         if (dc->fbc_compressor)
2208                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2209
2210         dce110_setup_audio_dto(dc, context);
2211
2212         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2213                 struct pipe_ctx *pipe_ctx_old =
2214                                         &dc->current_state->res_ctx.pipe_ctx[i];
2215                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2216
2217                 if (pipe_ctx->stream == NULL)
2218                         continue;
2219
2220                 if (pipe_ctx->stream == pipe_ctx_old->stream &&
2221                         pipe_ctx->stream->link->link_state_valid) {
2222                         continue;
2223                 }
2224
2225                 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx))
2226                         continue;
2227
2228                 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe)
2229                         continue;
2230
2231                 status = apply_single_controller_ctx_to_hw(
2232                                 pipe_ctx,
2233                                 context,
2234                                 dc);
2235
2236                 if (DC_OK != status)
2237                         return status;
2238         }
2239
2240         if (dc->fbc_compressor)
2241                 enable_fbc(dc, dc->current_state);
2242
2243         dcb->funcs->set_scratch_critical_state(dcb, false);
2244
2245         return DC_OK;
2246 }
2247
2248 /*******************************************************************************
2249  * Front End programming
2250  ******************************************************************************/
2251 static void set_default_colors(struct pipe_ctx *pipe_ctx)
2252 {
2253         struct default_adjustment default_adjust = { 0 };
2254
2255         default_adjust.force_hw_default = false;
2256         default_adjust.in_color_space = pipe_ctx->plane_state->color_space;
2257         default_adjust.out_color_space = pipe_ctx->stream->output_color_space;
2258         default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW;
2259         default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format;
2260
2261         /* display color depth */
2262         default_adjust.color_depth =
2263                 pipe_ctx->stream->timing.display_color_depth;
2264
2265         /* Lb color depth */
2266         default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth;
2267
2268         pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default(
2269                                         pipe_ctx->plane_res.xfm, &default_adjust);
2270 }
2271
2272
2273 /*******************************************************************************
2274  * In order to turn on/off specific surface we will program
2275  * Blender + CRTC
2276  *
2277  * In case that we have two surfaces and they have a different visibility
2278  * we can't turn off the CRTC since it will turn off the entire display
2279  *
2280  * |----------------------------------------------- |
2281  * |bottom pipe|curr pipe  |              |         |
2282  * |Surface    |Surface    | Blender      |  CRCT   |
2283  * |visibility |visibility | Configuration|         |
2284  * |------------------------------------------------|
2285  * |   off     |    off    | CURRENT_PIPE | blank   |
2286  * |   off     |    on     | CURRENT_PIPE | unblank |
2287  * |   on      |    off    | OTHER_PIPE   | unblank |
2288  * |   on      |    on     | BLENDING     | unblank |
2289  * -------------------------------------------------|
2290  *
2291  ******************************************************************************/
2292 static void program_surface_visibility(const struct dc *dc,
2293                 struct pipe_ctx *pipe_ctx)
2294 {
2295         enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
2296         bool blank_target = false;
2297
2298         if (pipe_ctx->bottom_pipe) {
2299
2300                 /* For now we are supporting only two pipes */
2301                 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL);
2302
2303                 if (pipe_ctx->bottom_pipe->plane_state->visible) {
2304                         if (pipe_ctx->plane_state->visible)
2305                                 blender_mode = BLND_MODE_BLENDING;
2306                         else
2307                                 blender_mode = BLND_MODE_OTHER_PIPE;
2308
2309                 } else if (!pipe_ctx->plane_state->visible)
2310                         blank_target = true;
2311
2312         } else if (!pipe_ctx->plane_state->visible)
2313                 blank_target = true;
2314
2315         dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode);
2316         pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target);
2317
2318 }
2319
2320 static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
2321 {
2322         int i = 0;
2323         struct xfm_grph_csc_adjustment adjust;
2324         memset(&adjust, 0, sizeof(adjust));
2325         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2326
2327
2328         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2329                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2330
2331                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2332                         adjust.temperature_matrix[i] =
2333                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2334         }
2335
2336         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2337 }
2338 static void update_plane_addr(const struct dc *dc,
2339                 struct pipe_ctx *pipe_ctx)
2340 {
2341         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2342
2343         if (plane_state == NULL)
2344                 return;
2345
2346         pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr(
2347                         pipe_ctx->plane_res.mi,
2348                         &plane_state->address,
2349                         plane_state->flip_immediate);
2350
2351         plane_state->status.requested_address = plane_state->address;
2352 }
2353
2354 static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
2355 {
2356         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2357
2358         if (plane_state == NULL)
2359                 return;
2360
2361         plane_state->status.is_flip_pending =
2362                         pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending(
2363                                         pipe_ctx->plane_res.mi);
2364
2365         if (plane_state->status.is_flip_pending && !plane_state->visible)
2366                 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address;
2367
2368         plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address;
2369         if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
2370                         pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) {
2371                 plane_state->status.is_right_eye =\
2372                                 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg);
2373         }
2374 }
2375
2376 void dce110_power_down(struct dc *dc)
2377 {
2378         power_down_all_hw_blocks(dc);
2379         disable_vga_and_power_gate_all_controllers(dc);
2380 }
2381
2382 static bool wait_for_reset_trigger_to_occur(
2383         struct dc_context *dc_ctx,
2384         struct timing_generator *tg)
2385 {
2386         bool rc = false;
2387
2388         /* To avoid endless loop we wait at most
2389          * frames_to_wait_on_triggered_reset frames for the reset to occur. */
2390         const uint32_t frames_to_wait_on_triggered_reset = 10;
2391         uint32_t i;
2392
2393         for (i = 0; i < frames_to_wait_on_triggered_reset; i++) {
2394
2395                 if (!tg->funcs->is_counter_moving(tg)) {
2396                         DC_ERROR("TG counter is not moving!\n");
2397                         break;
2398                 }
2399
2400                 if (tg->funcs->did_triggered_reset_occur(tg)) {
2401                         rc = true;
2402                         /* usually occurs at i=1 */
2403                         DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n",
2404                                         i);
2405                         break;
2406                 }
2407
2408                 /* Wait for one frame. */
2409                 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE);
2410                 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK);
2411         }
2412
2413         if (false == rc)
2414                 DC_ERROR("GSL: Timeout on reset trigger!\n");
2415
2416         return rc;
2417 }
2418
2419 /* Enable timing synchronization for a group of Timing Generators. */
2420 static void dce110_enable_timing_synchronization(
2421                 struct dc *dc,
2422                 int group_index,
2423                 int group_size,
2424                 struct pipe_ctx *grouped_pipes[])
2425 {
2426         struct dc_context *dc_ctx = dc->ctx;
2427         struct dcp_gsl_params gsl_params = { 0 };
2428         int i;
2429
2430         DC_SYNC_INFO("GSL: Setting-up...\n");
2431
2432         /* Designate a single TG in the group as a master.
2433          * Since HW doesn't care which one, we always assign
2434          * the 1st one in the group. */
2435         gsl_params.gsl_group = 0;
2436         gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst;
2437
2438         for (i = 0; i < group_size; i++)
2439                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2440                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2441
2442         /* Reset slave controllers on master VSync */
2443         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2444
2445         for (i = 1 /* skip the master */; i < group_size; i++)
2446                 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger(
2447                                 grouped_pipes[i]->stream_res.tg,
2448                                 gsl_params.gsl_group);
2449
2450         for (i = 1 /* skip the master */; i < group_size; i++) {
2451                 DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2452                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2453                 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger(
2454                                 grouped_pipes[i]->stream_res.tg);
2455         }
2456
2457         /* GSL Vblank synchronization is a one time sync mechanism, assumption
2458          * is that the sync'ed displays will not drift out of sync over time*/
2459         DC_SYNC_INFO("GSL: Restoring register states.\n");
2460         for (i = 0; i < group_size; i++)
2461                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2462
2463         DC_SYNC_INFO("GSL: Set-up complete.\n");
2464 }
2465
2466 static void dce110_enable_per_frame_crtc_position_reset(
2467                 struct dc *dc,
2468                 int group_size,
2469                 struct pipe_ctx *grouped_pipes[])
2470 {
2471         struct dc_context *dc_ctx = dc->ctx;
2472         struct dcp_gsl_params gsl_params = { 0 };
2473         int i;
2474
2475         gsl_params.gsl_group = 0;
2476         gsl_params.gsl_master = 0;
2477
2478         for (i = 0; i < group_size; i++)
2479                 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock(
2480                                         grouped_pipes[i]->stream_res.tg, &gsl_params);
2481
2482         DC_SYNC_INFO("GSL: enabling trigger-reset\n");
2483
2484         for (i = 1; i < group_size; i++)
2485                 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(
2486                                 grouped_pipes[i]->stream_res.tg,
2487                                 gsl_params.gsl_master,
2488                                 &grouped_pipes[i]->stream->triggered_crtc_reset);
2489
2490         DC_SYNC_INFO("GSL: waiting for reset to occur.\n");
2491         for (i = 1; i < group_size; i++)
2492                 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg);
2493
2494         for (i = 0; i < group_size; i++)
2495                 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg);
2496
2497 }
2498
2499 static void init_pipes(struct dc *dc, struct dc_state *context)
2500 {
2501         // Do nothing
2502 }
2503
2504 static void init_hw(struct dc *dc)
2505 {
2506         int i;
2507         struct dc_bios *bp;
2508         struct transform *xfm;
2509         struct abm *abm;
2510         struct dmcu *dmcu;
2511         struct dce_hwseq *hws = dc->hwseq;
2512         uint32_t backlight = MAX_BACKLIGHT_LEVEL;
2513
2514         bp = dc->ctx->dc_bios;
2515         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2516                 xfm = dc->res_pool->transforms[i];
2517                 xfm->funcs->transform_reset(xfm);
2518
2519                 hws->funcs.enable_display_power_gating(
2520                                 dc, i, bp,
2521                                 PIPE_GATING_CONTROL_INIT);
2522                 hws->funcs.enable_display_power_gating(
2523                                 dc, i, bp,
2524                                 PIPE_GATING_CONTROL_DISABLE);
2525                 hws->funcs.enable_display_pipe_clock_gating(
2526                         dc->ctx,
2527                         true);
2528         }
2529
2530         dce_clock_gating_power_up(dc->hwseq, false);
2531         /***************************************/
2532
2533         for (i = 0; i < dc->link_count; i++) {
2534                 /****************************************/
2535                 /* Power up AND update implementation according to the
2536                  * required signal (which may be different from the
2537                  * default signal on connector). */
2538                 struct dc_link *link = dc->links[i];
2539
2540                 link->link_enc->funcs->hw_init(link->link_enc);
2541         }
2542
2543         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2544                 struct timing_generator *tg = dc->res_pool->timing_generators[i];
2545
2546                 tg->funcs->disable_vga(tg);
2547
2548                 /* Blank controller using driver code instead of
2549                  * command table. */
2550                 tg->funcs->set_blank(tg, true);
2551                 hwss_wait_for_blank_complete(tg);
2552         }
2553
2554         for (i = 0; i < dc->res_pool->audio_count; i++) {
2555                 struct audio *audio = dc->res_pool->audios[i];
2556                 audio->funcs->hw_init(audio);
2557         }
2558
2559         for (i = 0; i < dc->link_count; i++) {
2560                 struct dc_link *link = dc->links[i];
2561
2562                 if (link->panel_cntl)
2563                         backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl);
2564         }
2565
2566         abm = dc->res_pool->abm;
2567         if (abm != NULL)
2568                 abm->funcs->abm_init(abm, backlight);
2569
2570         dmcu = dc->res_pool->dmcu;
2571         if (dmcu != NULL && abm != NULL)
2572                 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu);
2573
2574         if (dc->fbc_compressor)
2575                 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor);
2576
2577 }
2578
2579
2580 void dce110_prepare_bandwidth(
2581                 struct dc *dc,
2582                 struct dc_state *context)
2583 {
2584         struct clk_mgr *dccg = dc->clk_mgr;
2585
2586         dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool);
2587
2588         dccg->funcs->update_clocks(
2589                         dccg,
2590                         context,
2591                         false);
2592 }
2593
2594 void dce110_optimize_bandwidth(
2595                 struct dc *dc,
2596                 struct dc_state *context)
2597 {
2598         struct clk_mgr *dccg = dc->clk_mgr;
2599
2600         dce110_set_displaymarks(dc, context);
2601
2602         dccg->funcs->update_clocks(
2603                         dccg,
2604                         context,
2605                         true);
2606 }
2607
2608 static void dce110_program_front_end_for_pipe(
2609                 struct dc *dc, struct pipe_ctx *pipe_ctx)
2610 {
2611         struct mem_input *mi = pipe_ctx->plane_res.mi;
2612         struct dc_plane_state *plane_state = pipe_ctx->plane_state;
2613         struct xfm_grph_csc_adjustment adjust;
2614         struct out_csc_color_matrix tbl_entry;
2615         unsigned int i;
2616         struct dce_hwseq *hws = dc->hwseq;
2617
2618         DC_LOGGER_INIT();
2619         memset(&tbl_entry, 0, sizeof(tbl_entry));
2620
2621         memset(&adjust, 0, sizeof(adjust));
2622         adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
2623
2624         dce_enable_fe_clock(dc->hwseq, mi->inst, true);
2625
2626         set_default_colors(pipe_ctx);
2627         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
2628                         == true) {
2629                 tbl_entry.color_space =
2630                         pipe_ctx->stream->output_color_space;
2631
2632                 for (i = 0; i < 12; i++)
2633                         tbl_entry.regval[i] =
2634                         pipe_ctx->stream->csc_color_matrix.matrix[i];
2635
2636                 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment
2637                                 (pipe_ctx->plane_res.xfm, &tbl_entry);
2638         }
2639
2640         if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
2641                 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
2642
2643                 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++)
2644                         adjust.temperature_matrix[i] =
2645                                 pipe_ctx->stream->gamut_remap_matrix.matrix[i];
2646         }
2647
2648         pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust);
2649
2650         pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0;
2651
2652         program_scaler(dc, pipe_ctx);
2653
2654         mi->funcs->mem_input_program_surface_config(
2655                         mi,
2656                         plane_state->format,
2657                         &plane_state->tiling_info,
2658                         &plane_state->plane_size,
2659                         plane_state->rotation,
2660                         NULL,
2661                         false);
2662         if (mi->funcs->set_blank)
2663                 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
2664
2665         if (dc->config.gpu_vm_support)
2666                 mi->funcs->mem_input_program_pte_vm(
2667                                 pipe_ctx->plane_res.mi,
2668                                 plane_state->format,
2669                                 &plane_state->tiling_info,
2670                                 plane_state->rotation);
2671
2672         /* Moved programming gamma from dc to hwss */
2673         if (pipe_ctx->plane_state->update_flags.bits.full_update ||
2674                         pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change ||
2675                         pipe_ctx->plane_state->update_flags.bits.gamma_change)
2676                 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state);
2677
2678         if (pipe_ctx->plane_state->update_flags.bits.full_update)
2679                 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream);
2680
2681         DC_LOG_SURFACE(
2682                         "Pipe:%d %p: addr hi:0x%x, "
2683                         "addr low:0x%x, "
2684                         "src: %d, %d, %d,"
2685                         " %d; dst: %d, %d, %d, %d;"
2686                         "clip: %d, %d, %d, %d\n",
2687                         pipe_ctx->pipe_idx,
2688                         (void *) pipe_ctx->plane_state,
2689                         pipe_ctx->plane_state->address.grph.addr.high_part,
2690                         pipe_ctx->plane_state->address.grph.addr.low_part,
2691                         pipe_ctx->plane_state->src_rect.x,
2692                         pipe_ctx->plane_state->src_rect.y,
2693                         pipe_ctx->plane_state->src_rect.width,
2694                         pipe_ctx->plane_state->src_rect.height,
2695                         pipe_ctx->plane_state->dst_rect.x,
2696                         pipe_ctx->plane_state->dst_rect.y,
2697                         pipe_ctx->plane_state->dst_rect.width,
2698                         pipe_ctx->plane_state->dst_rect.height,
2699                         pipe_ctx->plane_state->clip_rect.x,
2700                         pipe_ctx->plane_state->clip_rect.y,
2701                         pipe_ctx->plane_state->clip_rect.width,
2702                         pipe_ctx->plane_state->clip_rect.height);
2703
2704         DC_LOG_SURFACE(
2705                         "Pipe %d: width, height, x, y\n"
2706                         "viewport:%d, %d, %d, %d\n"
2707                         "recout:  %d, %d, %d, %d\n",
2708                         pipe_ctx->pipe_idx,
2709                         pipe_ctx->plane_res.scl_data.viewport.width,
2710                         pipe_ctx->plane_res.scl_data.viewport.height,
2711                         pipe_ctx->plane_res.scl_data.viewport.x,
2712                         pipe_ctx->plane_res.scl_data.viewport.y,
2713                         pipe_ctx->plane_res.scl_data.recout.width,
2714                         pipe_ctx->plane_res.scl_data.recout.height,
2715                         pipe_ctx->plane_res.scl_data.recout.x,
2716                         pipe_ctx->plane_res.scl_data.recout.y);
2717 }
2718
2719 static void dce110_apply_ctx_for_surface(
2720                 struct dc *dc,
2721                 const struct dc_stream_state *stream,
2722                 int num_planes,
2723                 struct dc_state *context)
2724 {
2725         int i;
2726
2727         if (num_planes == 0)
2728                 return;
2729
2730         if (dc->fbc_compressor)
2731                 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor);
2732
2733         for (i = 0; i < dc->res_pool->pipe_count; i++) {
2734                 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i];
2735
2736                 if (pipe_ctx->stream != stream)
2737                         continue;
2738
2739                 /* Need to allocate mem before program front end for Fiji */
2740                 pipe_ctx->plane_res.mi->funcs->allocate_mem_input(
2741                                 pipe_ctx->plane_res.mi,
2742                                 pipe_ctx->stream->timing.h_total,
2743                                 pipe_ctx->stream->timing.v_total,
2744                                 pipe_ctx->stream->timing.pix_clk_100hz / 10,
2745                                 context->stream_count);
2746
2747                 dce110_program_front_end_for_pipe(dc, pipe_ctx);
2748
2749                 dc->hwss.update_plane_addr(dc, pipe_ctx);
2750
2751                 program_surface_visibility(dc, pipe_ctx);
2752
2753         }
2754
2755         if (dc->fbc_compressor)
2756                 enable_fbc(dc, context);
2757 }
2758
2759 static void dce110_post_unlock_program_front_end(
2760                 struct dc *dc,
2761                 struct dc_state *context)
2762 {
2763 }
2764
2765 static void dce110_power_down_fe(struct dc *dc, struct pipe_ctx *pipe_ctx)
2766 {
2767         struct dce_hwseq *hws = dc->hwseq;
2768         int fe_idx = pipe_ctx->plane_res.mi ?
2769                 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx;
2770
2771         /* Do not power down fe when stream is active on dce*/
2772         if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream)
2773                 return;
2774
2775         hws->funcs.enable_display_power_gating(
2776                 dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
2777
2778         dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
2779                                 dc->res_pool->transforms[fe_idx]);
2780 }
2781
2782 static void dce110_wait_for_mpcc_disconnect(
2783                 struct dc *dc,
2784                 struct resource_pool *res_pool,
2785                 struct pipe_ctx *pipe_ctx)
2786 {
2787         /* do nothing*/
2788 }
2789
2790 static void program_output_csc(struct dc *dc,
2791                 struct pipe_ctx *pipe_ctx,
2792                 enum dc_color_space colorspace,
2793                 uint16_t *matrix,
2794                 int opp_id)
2795 {
2796         int i;
2797         struct out_csc_color_matrix tbl_entry;
2798
2799         if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) {
2800                 enum dc_color_space color_space = pipe_ctx->stream->output_color_space;
2801
2802                 for (i = 0; i < 12; i++)
2803                         tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
2804
2805                 tbl_entry.color_space = color_space;
2806
2807                 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment(
2808                                 pipe_ctx->plane_res.xfm, &tbl_entry);
2809         }
2810 }
2811
2812 static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx)
2813 {
2814         struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position;
2815         struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp;
2816         struct mem_input *mi = pipe_ctx->plane_res.mi;
2817         struct dc_cursor_mi_param param = {
2818                 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10,
2819                 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz,
2820                 .viewport = pipe_ctx->plane_res.scl_data.viewport,
2821                 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz,
2822                 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert,
2823                 .rotation = pipe_ctx->plane_state->rotation,
2824                 .mirror = pipe_ctx->plane_state->horizontal_mirror
2825         };
2826
2827         /**
2828          * If the cursor's source viewport is clipped then we need to
2829          * translate the cursor to appear in the correct position on
2830          * the screen.
2831          *
2832          * This translation isn't affected by scaling so it needs to be
2833          * done *after* we adjust the position for the scale factor.
2834          *
2835          * This is only done by opt-in for now since there are still
2836          * some usecases like tiled display that might enable the
2837          * cursor on both streams while expecting dc to clip it.
2838          */
2839         if (pos_cpy.translate_by_source) {
2840                 pos_cpy.x += pipe_ctx->plane_state->src_rect.x;
2841                 pos_cpy.y += pipe_ctx->plane_state->src_rect.y;
2842         }
2843
2844         if (pipe_ctx->plane_state->address.type
2845                         == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE)
2846                 pos_cpy.enable = false;
2847
2848         if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state)
2849                 pos_cpy.enable = false;
2850
2851         if (ipp->funcs->ipp_cursor_set_position)
2852                 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, &param);
2853         if (mi->funcs->set_cursor_position)
2854                 mi->funcs->set_cursor_position(mi, &pos_cpy, &param);
2855 }
2856
2857 static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx)
2858 {
2859         struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes;
2860
2861         if (pipe_ctx->plane_res.ipp &&
2862             pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes)
2863                 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes(
2864                                 pipe_ctx->plane_res.ipp, attributes);
2865
2866         if (pipe_ctx->plane_res.mi &&
2867             pipe_ctx->plane_res.mi->funcs->set_cursor_attributes)
2868                 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes(
2869                                 pipe_ctx->plane_res.mi, attributes);
2870
2871         if (pipe_ctx->plane_res.xfm &&
2872             pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes)
2873                 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes(
2874                                 pipe_ctx->plane_res.xfm, attributes);
2875 }
2876
2877 bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx,
2878                 uint32_t backlight_pwm_u16_16,
2879                 uint32_t frame_ramp)
2880 {
2881         struct dc_link *link = pipe_ctx->stream->link;
2882         struct dc  *dc = link->ctx->dc;
2883         struct abm *abm = pipe_ctx->stream_res.abm;
2884         struct panel_cntl *panel_cntl = link->panel_cntl;
2885         struct dmcu *dmcu = dc->res_pool->dmcu;
2886         bool fw_set_brightness = true;
2887         /* DMCU -1 for all controller id values,
2888          * therefore +1 here
2889          */
2890         uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1;
2891
2892         if (abm == NULL || panel_cntl == NULL || (abm->funcs->set_backlight_level_pwm == NULL))
2893                 return false;
2894
2895         if (dmcu)
2896                 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2897
2898         if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight)
2899                 panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16);
2900         else
2901                 abm->funcs->set_backlight_level_pwm(
2902                                 abm,
2903                                 backlight_pwm_u16_16,
2904                                 frame_ramp,
2905                                 controller_id,
2906                                 link->panel_cntl->inst);
2907
2908         return true;
2909 }
2910
2911 void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx)
2912 {
2913         struct abm *abm = pipe_ctx->stream_res.abm;
2914         struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
2915
2916         if (abm)
2917                 abm->funcs->set_abm_immediate_disable(abm,
2918                                 pipe_ctx->stream->link->panel_cntl->inst);
2919
2920         if (panel_cntl)
2921                 panel_cntl->funcs->store_backlight_level(panel_cntl);
2922 }
2923
2924 void dce110_set_pipe(struct pipe_ctx *pipe_ctx)
2925 {
2926         struct abm *abm = pipe_ctx->stream_res.abm;
2927         struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl;
2928         uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1;
2929
2930         if (abm && panel_cntl)
2931                 abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst);
2932 }
2933
2934 static const struct hw_sequencer_funcs dce110_funcs = {
2935         .program_gamut_remap = program_gamut_remap,
2936         .program_output_csc = program_output_csc,
2937         .init_hw = init_hw,
2938         .apply_ctx_to_hw = dce110_apply_ctx_to_hw,
2939         .apply_ctx_for_surface = dce110_apply_ctx_for_surface,
2940         .post_unlock_program_front_end = dce110_post_unlock_program_front_end,
2941         .update_plane_addr = update_plane_addr,
2942         .update_pending_status = dce110_update_pending_status,
2943         .enable_accelerated_mode = dce110_enable_accelerated_mode,
2944         .enable_timing_synchronization = dce110_enable_timing_synchronization,
2945         .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset,
2946         .update_info_frame = dce110_update_info_frame,
2947         .enable_stream = dce110_enable_stream,
2948         .disable_stream = dce110_disable_stream,
2949         .unblank_stream = dce110_unblank_stream,
2950         .blank_stream = dce110_blank_stream,
2951         .enable_audio_stream = dce110_enable_audio_stream,
2952         .disable_audio_stream = dce110_disable_audio_stream,
2953         .disable_plane = dce110_power_down_fe,
2954         .pipe_control_lock = dce_pipe_control_lock,
2955         .interdependent_update_lock = NULL,
2956         .cursor_lock = dce_pipe_control_lock,
2957         .prepare_bandwidth = dce110_prepare_bandwidth,
2958         .optimize_bandwidth = dce110_optimize_bandwidth,
2959         .set_drr = set_drr,
2960         .get_position = get_position,
2961         .set_static_screen_control = set_static_screen_control,
2962         .setup_stereo = NULL,
2963         .set_avmute = dce110_set_avmute,
2964         .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect,
2965         .edp_backlight_control = dce110_edp_backlight_control,
2966         .edp_power_control = dce110_edp_power_control,
2967         .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready,
2968         .set_cursor_position = dce110_set_cursor_position,
2969         .set_cursor_attribute = dce110_set_cursor_attribute,
2970         .set_backlight_level = dce110_set_backlight_level,
2971         .set_abm_immediate_disable = dce110_set_abm_immediate_disable,
2972         .set_pipe = dce110_set_pipe,
2973 };
2974
2975 static const struct hwseq_private_funcs dce110_private_funcs = {
2976         .init_pipes = init_pipes,
2977         .update_plane_addr = update_plane_addr,
2978         .set_input_transfer_func = dce110_set_input_transfer_func,
2979         .set_output_transfer_func = dce110_set_output_transfer_func,
2980         .power_down = dce110_power_down,
2981         .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating,
2982         .enable_display_power_gating = dce110_enable_display_power_gating,
2983         .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap,
2984         .enable_stream_timing = dce110_enable_stream_timing,
2985         .disable_stream_gating = NULL,
2986         .enable_stream_gating = NULL,
2987         .edp_backlight_control = dce110_edp_backlight_control,
2988 };
2989
2990 void dce110_hw_sequencer_construct(struct dc *dc)
2991 {
2992         dc->hwss = dce110_funcs;
2993         dc->hwseq->funcs = dce110_private_funcs;
2994 }
2995